LG 42LB65 Series, 42LB650V Service Manual

Printed in KoreaP/NO : MFL67985212 (1403-REV00)

CHASSIS : LD42B

MODEL : 42LB65** 42LB65**-Z*

42LB650V 42LB650V-TA

CAUTION

BEFORE SERVICING THE CHASSIS, READ THE SAFETY PRECAUTIONS IN THIS MANUAL.

LED TV

SERVICE MANUAL

North/Latin America http://aic.lgservice.com Europe/Africa http://eic.lgservice.com Asia/Oceania http://biz.lgservice.com

Internal Use Only

- 2 -

Only for training and service purposes

CONTENTS

CONTENTS .............................................................................................. 2

SAFETY PRECAUTIONS ........................................................................ 3

SERVICING PRECAUTIONS .................................................................... 4

SPECIFICATION ....................................................................................... 6

ADJUSTMENT INSTRUCTION .............................................................. 13

BLOCK DIAGRAM ................................................................................. 21

EXPLODED VIEW .................................................................................. 22

SCHEMATIC CIRCUIT DIAGRAM ..............................................................

- 3 -

Only for training and service purposes

Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the Schematic Diagram and Exploded View. It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent Shock, Fire, or other Hazards. Do not modify the original design without permission of manufacturer.

General Guidance

An isolation Transformer should always be used during the servicing of a receiver whose chassis is not isolated from the AC power line. Use a transformer of adequate power rating as this protects the technician from accidents resulting in personal injury from electrical shocks.

It will also protect the receiver and it's components from being damaged by accidental sh orts of the cir cui try that may be inadvertently introduced during the service operation.

If any fuse (or Fusible Resistor) in this TV receiver is blown, replace it with the specified.

When replacing a high wattage resistor (Oxide Metal Film Resistor, over 1 W), keep the resistor 10 mm away from PCB.

Keep wires away from high voltage or high temperature parts.

Before returning the receiver to the customer,

always perform an AC leakage current check on the exposed metallic parts of the cabinet, such as antennas, terminals, etc., to be sure the set is safe to operate without damage of electrical shock.

Leakage Current Cold Check(Antenna Cold Check)

With the instrument AC plug removed from AC source, connect an electrical jumper across the two AC plug prongs. Place the AC switch in the on position, connect one lead of ohm-meter to the AC plug prongs tied together and touch other ohm-meter lead in turn to each exposed metallic parts such as antenna terminals, phone jacks, etc. If the exposed metallic part has a return path to the chassis, the

measured resistance should be between 1 MΩ and 5.2 MΩ.

When the exposed metal has no return path to the chassis the reading must be infinite. An other abnormality exists that must be corrected before the receiver is returned to the customer.

Leakage Current Hot Check (See below Figure)

Plug the AC cord directly into the AC outlet.

Do not use a line Isolation Transformer during this check. Connect 1.5 K / 10 watt resistor in parallel with a 0.15 uF capacitor between a known good earth ground (Water Pipe, Conduit, etc.) and the exposed metallic parts. Measure the AC voltage across the resistor using AC voltmeter with 1000 ohms/volt or more sensitivity. Reverse plug the AC cord into the AC outlet and repeat AC voltage measurements for each exposed metallic part. Any voltage measured must not exceed 0.75 volt RMS which is corresponds to

0.5 mA. In case any measurement is out of the limits specified, there is possibility of shock hazard and the set must be checked and repaired before it is returned to the customer.

Leakage Current Hot Check circuit

IMPORTANT SAFETY NOTICE

SAFETY PRECAUTIONS

- 4 -

Only for training and service purposes

SERVICING PRECAUTIONS

CAUTION: Before servicing receivers covered by this service manual and its supplements and addenda, read and follow the

SAFETY PRECAUTIONS on page 3 of this publication. NOTE: If unforeseen circumstances create conict between the

following servicing precautions and any of the safety precautions on page 3 of this publication, always follow the safety precautions. Remember: Safety First.

General Servicing Precautions

1. Always unplug the receiver AC power cord from the AC power source before;

a. Removing or reinstalling any component, circuit board

module or any other receiver assembly.

b. Disconnecting or reconnecting any receiver electrical plug

or other electrical connection.

c. Connecting a test substitute in parallel with an electrolytic

capacitor in the receiver. CAUTION: A wrong part substitution or incorrect polarity installation of electrolytic capacitors may result in an explosion hazard.

2. Test high voltage only by measuring it with an appropriate high voltage meter or other voltage measuring device (DVM, FETVOM, etc) equipped with a suitable high voltage probe. Do not test high voltage by "drawing an arc".

3. Do not spray chemicals on or near this receiver or any of its assemblies.

4. Unless specied otherwise in this service manual, clean

electrical contacts only by applying the following mixture to the contacts with a pipe cleaner, cotton-tipped stick or comparable non-abrasive applicator; 10 % (by volume) Acetone and 90 % (by volume) isopropyl alcohol (90 % - 99 % strength)

CAUTION: This is a ammable mixture. Unless specied otherwise in this service manual, lubrication

of contacts in not required.

5. Do not defeat any plug/socket B+ voltage interlocks with which receivers covered by this service manual might be equipped.

6. Do not apply AC power to this instrument and/or any of its electrical assemblies unless all solid-state device heat sinks are correctly installed.

7. Always connect the test receiver ground lead to the receiver chassis ground before connecting the test receiver positive lead. Always remove the test receiver ground lead last.

8. Use with this receiver only the test xtures specied in this

service manual.

CAUTION: Do not connect the test xture ground strap to any

heat sink in this receiver.

Electrostatically Sensitive (ES) Devices

Some semiconductor (solid-state) devices can be damaged easily by static electricity. Such components commonly are called Electrostatically Sensitive (ES) Devices. Examples of typical ES

devices are integrated circuits and some eld-effect transistors

and semiconductor “chip” components. The following techniques should be used to help reduce the incidence of component damage caused by static by static electricity.

1. Immediately before handling any semiconductor component or semiconductor-equipped assembly, drain off any electrostatic charge on your body by touching a known earth ground. Alternatively, obtain and wear a commercially available discharging wrist strap device, which should be removed to prevent potential shock reasons prior to applying power to the unit under test.

2. After removing an electrical assembly equipped with ES devices, place the assembly on a conductive surface such as aluminum foil, to prevent electrostatic charge buildup or exposure of the assembly.

3. Use only a grounded-tip soldering iron to solder or unsolder ES devices.

4. Use only an anti-static type solder removal device. Some sol-

der removal devices not classied as “anti-static” can generate electrical charges sufcient to damage ES devices.

5. Do not use freon-propelled chemicals. These can generate

electrical charges sufcient to damage ES devices.

6. Do not remove a replacement ES device from its protective package until immediately before you are ready to install it. (Most replacement ES devices are packaged with leads electrically shorted together by conductive foam, aluminum foil or comparable conductive material).

7. Immediately before removing the protective material from the leads of a replacement ES device, touch the protective material to the chassis or circuit assembly into which the device will be installed. CAUTION: Be sure no power is applied to the chassis or circuit, and observe all other safety precautions.

8. Minimize bodily motions when handling unpackaged replacement ES devices. (Otherwise harmless motion such as the brushing together of your clothes fabric or the lifting of your

foot from a carpeted oor can generate static electricity sufcient to damage an ES device.)

General Soldering Guidelines

1. Use a grounded-tip, low-wattage soldering iron and appropriate tip size and shape that will maintain tip temperature within the range or 500 °F to 600 °F.

2. Use an appropriate gauge of RMA resin-core solder composed of 60 parts tin/40 parts lead.

3. Keep the soldering iron tip clean and well tinned.

4. Thoroughly clean the surfaces to be soldered. Use a mall wirebristle (0.5 inch, or 1.25 cm) brush with a metal handle. Do not use freon-propelled spray-on cleaners.

5. Use the following unsoldering technique

a. Allow the soldering iron tip to reach normal temperature.

(500 °F to 600 °F) b. Heat the component lead until the solder melts. c. Quickly draw the melted solder with an anti-static, suction-

type solder removal device or with solder braid.

CAUTION: Work quickly to avoid overheating the circuit

board printed foil.

6. Use the following soldering technique. a. Allow the soldering iron tip to reach a normal temperature

(500 °F to 600 °F)

b. First, hold the soldering iron tip and solder the strand

against the component lead until the solder melts.

c. Quickly move the soldering iron tip to the junction of the

component lead and the printed circuit foil, and hold it there only until the solder ows onto and around both the component lead and the foil. CAUTION: Work quickly to avoid overheating the circuit board printed foil.

d. Closely inspect the solder area and remove any excess or

splashed solder with a small wire-bristle brush.

- 5 -

Only for training and service purposes

IC Remove/Replacement

Some chassis circuit boards have slotted holes (oblong) through which the IC leads are inserted and then bent at against the circuit foil. When holes are the slotted type, the following technique should be used to remove and replace the IC. When working with boards using the familiar round hole, use the standard technique as outlined in paragraphs 5 and 6 above.

Removal

1. Desolder and straighten each IC lead in one operation by gently prying up on the lead with the soldering iron tip as the solder melts.

2. Draw away the melted solder with an anti-static suction-type solder removal device (or with solder braid) before removing the IC.

Replacement

1. Carefully insert the replacement IC in the circuit board.

2. Carefully bend each IC lead against the circuit foil pad and solder it.

3. Clean the soldered areas with a small wire-bristle brush. (It is not necessary to reapply acrylic coating to the areas).

"Small-Signal" Discrete Transistor Removal/Replacement

1. Remove the defective transistor by clipping its leads as close as possible to the component body.

2. Bend into a "U" shape the end of each of three leads remaining on the circuit board.

3. Bend into a "U" shape the replacement transistor leads.

4. Connect the replacement transistor leads to the corresponding leads extending from the circuit board and crimp the "U" with long nose pliers to insure metal to metal contact then solder each connection.

Power Output, Transistor Device Removal/Replacement

1. Heat and remove all solder from around the transistor leads.

2. Remove the heat sink mounting screw (if so equipped).

3. Carefully remove the transistor from the heat sink of the circuit board.

4. Insert new transistor in the circuit board.

5. Solder each transistor lead, and clip off excess lead.

6. Replace heat sink.

Diode Removal/Replacement

1. Remove defective diode by clipping its leads as close as possible to diode body.

2. Bend the two remaining leads perpendicular y to the circuit board.

3. Observing diode polarity, wrap each lead of the new diode around the corresponding lead on the circuit board.

4. Securely crimp each connection and solder it.

5. Inspect (on the circuit board copper side) the solder joints of the two "original" leads. If they are not shiny, reheat them and if necessary, apply additional solder.

Fuse and Conventional Resistor Removal/Replacement

1. Clip each fuse or resistor lead at top of the circuit board hollow stake.

2. Securely crimp the leads of replacement component around notch at stake top.

3. Solder the connections. CAUTION: Maintain original spacing between the replaced component and adjacent components and the circuit board to prevent excessive component temperatures.

Circuit Board Foil Repair

Excessive heat applied to the copper foil of any printed circuit board will weaken the adhesive that bonds the foil to the circuit board causing the foil to separate from or "lift-off" the board. The following guidelines and procedures should be followed whenever this condition is encountered.

At IC Connections

To repair a defective copper pattern at IC connections use the following procedure to install a jumper wire on the copper pattern side of the circuit board. (Use this technique only on IC connections).

1. Carefully remove the damaged copper pattern with a sharp knife. (Remove only as much copper as absolutely necessary).

2. carefully scratch away the solder resist and acrylic coating (if used) from the end of the remaining copper pattern.

3. Bend a small "U" in one end of a small gauge jumper wire and carefully crimp it around the IC pin. Solder the IC connection.

4. Route the jumper wire along the path of the out-away copper pattern and let it overlap the previously scraped end of the good copper pattern. Solder the overlapped area and clip off any excess jumper wire.

At Other Connections

Use the following technique to repair the defective copper pattern at connections other than IC Pins. This technique involves the installation of a jumper wire on the component side of the circuit board.

1. Remove the defective copper pattern with a sharp knife. Remove at least 1/4 inch of copper, to ensure that a hazardous condition will not exist if the jumper wire opens.

2. Trace along the copper pattern from both sides of the pattern break and locate the nearest component that is directly connected to the affected copper pattern.

3. Connect insulated 20-gauge jumper wire from the lead of the nearest component on one side of the pattern break to the lead of the nearest component on the other side. Carefully crimp and solder the connections. CAUTION: Be sure the insulated jumper wire is dressed so the it does not touch components or sharp edges.

- 6 -

Only for training and service purposes

SPECIFICATION

NOTE : Specifications and others are subject to change without notice for improvement

.

1. Application range

This specification is applied to the LED TV used LD42B chassis.

2. Requirement for Test

Each part is tested as below without special appointment.

(1) Temperature: 25 °C ± 5 °C(77 °F ± 9 °F), CST: 40 °C ± 5 °C (2) Relative Humidity: 65 % ± 10 % (3) Power Voltage

: Standard input voltage (AC 100-240 V~, 50/60 Hz) * Standard Voltage of each products is marked by models.

(4) Specification and performance of each parts are followed

ea ch dra wing and spe cificat ion by part n umber in accordance with BOM.

(5) The receiver must be operated for about 20 minutes prior

to the adjustment.

3. Test method

(1) Performance: LGE TV test method followed (2) Demanded other specification

- Safety : CE, IEC specification

- EMC : CE, IEC

4. Model General Specification

No. Item Specication Remarks

1 Market EU(PAL Market-37Countries) DTV & Analog (Total 37 countries)

DTV (MPEG2/4, DVB-T) : 29 countries

Germany, Netherland, Switzerland, Hungary, Austria, Slovenia, Bulgaria, France, Spain, Italy, Belgium, Luxemburg, Greece, Czech, Croatia, Turkey, Moroco, Ireland, Latvia, Estonia, Lithuania, Poland, Portugal, Romania, Albania, Bosnia, Serbia, Slovakia, Beralus

DTV (MPEG2/4, DVB-T2): 8 countries

UK(Ireland), Sweden, Denmark, Finland, Norway, Ukraine, Kazakhstan, Russia

DTV (MPEG2/4, DVB-C): 37 countries

Germany, Netherland, Switzerland, Hungary, Austria, Slovenia, Bulgaria, France, Spain, Italy, Belgium, Russia, Luxemburg, Greece, Czech, Croatia, Turkey, Moroco, Ireland, Latvia, Estonia, Lithuania, Poland, Portugal, Romania, Albania, Bosnia, Serbia, Slovakia, Beralus, UK, Sweden, Denmark, Finland, Norway, Ukraine, Kazakhstan

DTV (MPEG2/4,DVB-S): 30 countries

Germany, Netherland, Switzerland, Hungary, Austria, Slovenia, Bulgaria, France, Spain, Italy, Belgium, Russia, Luxemburg, Greece, Czech, Croatia, Turkey, Moroco, Ireland, Latvia, Estonia, Lithuania, Poland, Portugal, Romania, Albania, Bosnia, Serbia, Slovakia, Beralus

Supported satellite : 22 satellites

HISPASAT 1C/1D, ATLANTIC BIRD 2, NILESAT 101/102, ATLANTIC BIRD 3, AMOS 2/3, THOR 5/6, IRIUS 4, EUTELSAT-W3A, EUROBIRD 9A, EUTELSAT-W2A, HOTBIRD 6/8/9, EUTELSAT-SESAT, ASTRA 1L/H/M/ KR, ASTRA 3A/3B, BADR 4/6, ASTRA 2D, EUROBIRD 3, EUTELSAT-W7, HELLASSAT 2, EXPRESS AM1, TURKSAT 2A/3A, INTERSAT10

- 7 -

Only for training and service purposes

No. Item Specication Remarks

2 Television system

1) Digital TV

- DVB-T/T2

- DVB-C

- DVB-S/S2

2) Analogue TV

- PAL/SECAM B/G/I/D/K

- SECAM L/L’

3 Program coverage

1) Digital TV

- VHF, UHF

- C-Band, Ku-Band

2) Analogue TV

- VHF : E2 to E12

- UHF : E21 to E69

- CATV : S1 to S20

- HYPER : S21 to S47

4 Receiving system

Analog : Upper Heterodyne Digital : COFDM, QAM

► DVB-T

- Guard Interval(Bitrate_Mbit/s) 1/4, 1/8, 1/16, 1/32

- Modulation : Code Rate QPSK : 1/2, 2/3, 3/4, 5/6, 7/8 16-QAM : 1/2, 2/3, 3/4, 5/6, 7/8 64-QAM : 1/2, 2/3, 3/4, 5/6, 7/8

► DVB-T2 (Model : *L*V*-Z* (T2 only Model))

- Guard Interval(Bitrate_Mbit/s) 1/4, 1/8, 1/16, 1/32, 1/128, 19/128, 19/256,

- Modulation : Code Rate QPSK : 1/2, 2/5, 2/3, 3/4, 5/6 16-QAM : 1/2, 2/5, 2/3, 3/4, 5/6 64-QAM : 1/2, 2/5, 2/3, 3/4, 5/6 256-QAM : 1/2, 2/5, 2/3, 3/4, 5/6

► DVB-C

- Symbolrate : 4.0Msymbols/s to 7.2Msymbols/s

- Modulation : 16QAM, 64-QAM, 128-QAM and 256-QAM

► DVB-S/S2

- symbolrate DVB-S2 (8PSK / QPSK) : 2 ~ 45Msymbol/s DVB-S (QPSK) : 2 ~ 45Msymbol/s

- viterbi DVB-S mode : 1/2, 2/3, 3/4, 5/6, 7/8 DVB-S2 mode : 1/2, 2/3, 3/4, 3/5, 4/5, 5/6, 8/9, 9/10

5 Scart (1EA) PAL, SECAM

Scart 1 Jack is Full scart and support ATV/DTV-OUT (not support DTV Auto AV)

6 Video Input RCA(1EA) PAL, SECAM, NTSC4.43

4 System : PAL, SECAM, NTSC4.43, PAL60 Hybrid Type

7 Head phone out

Antenna, AV1, AV2, Component, HDMI1, HDMI2, HDMI3, USB1, USB2, USB3

8 Component Input (1EA)

Y/Cb/Cr Y/Pb/Pr

Hybrid Type

9 HDMI Input (3EA)

HDMI1-DTV HDMI2-DTV HDMI3-DTV

HDMI1: PC support(HDMI version 1.3) Support HDCP

10 Audio Input (3EA)

DVI Audio Component/AV2 AV1

L/R Input.

11 SDPIF out (1EA) SPDIF out 12 USB (1EA) EMF, DivX HD, For SVC (download) JPEG, MP3, DivX HD 13 Ethernet Connect(1EA) Ethernet Connect 14 PCMCIA Card slot (1EA) PCMCIA slot

- 8 -

Only for training and service purposes

5. Component Video Input (Y,

Pb, Pr)

No.

Specication

Resolution H-freq(kHz) V-freq(Hz) Pixel clock

1. 720×480 15.73 60.00 SDTV, DVD 480i

2. 720×480 15.63 59.94 SDTV, DVD 480i

3. 720×480 31.47 59.94 480p

4. 720×480 31.50 60.00 480p

5. 720×576 15.625 50.00 SDTV, DVD 625 Line

6. 720×576 31.25 50.00 HDTV 576p

7. 1280×720 45.00 50.00 HDTV 720p

8. 1280×720 44.96 59.94 HDTV 720p

9. 1280×720 45.00 60.00 HDTV 720p

10. 1920×1080 31.25 50.00 HDTV 1080i

11. 1920×1080 33.75 60.00 HDTV 1080i

12. 1920×1080 33.72 59.94 HDTV 1080i

13. 1920×1080 56.250 50 HDTV 1080p

14. 1920×1080 67.5 60 HDTV 1080p

- 9 -

Only for training and service purposes

6.2. PC mode

No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz)

1 640 x 350 @70Hz 31.468 70.09 EGA

2 720 x 400 @70Hz 31.469 70.08 DOS

3 640 x 480 @60Hz 31.469 59.94 VESA(VGA)

4 800 x 600 @60Hz 37.879 60.31 VESA(SVGA)

5 1024 x 768 @60Hz 48.363 60.00 VESA(XGA)

6 1152 x 864 @60Hz 54.348 60.053 VESA

7 1280 x 1024 @60Hz 63.981 60.020 VESA(SXGA)

8 1360 x 768 @60Hz 47.712 60.015 VESA(WXGA)

9 1920 x 1080 @60Hz 67.5 60.00 WUXGA(Reduced Blanking)

6. HDMI Input

6.1. DTV mode

No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz)

1. 640*480 31.469 / 31.5 59.94/60 SDTV 480P

2. 720*480 31.469 / 31.5 59.94 / 60 SDTV 480P

3. 720*576 31.25 50 SDTV 576P

4. 720*576 15.625 50 SDTV 576I

5. 1280*720 37.500 50 HDTV 720P

6. 1280*720 44.96 / 45 59.94 / 60 HDTV 720P

7. 1920*1080 33.72 / 33.75 59.94 / 60 HDTV 1080I

8. 1920*1080 28.125 50.00 HDTV 1080I

9. 1920*1080 26.97 / 27 23.97 / 24 HDTV 1080P

10. 1920*1080 28.125 25 HDTV 1080P

11. 1920*1080 33.716 / 33.75 29.976 / 30.00 HDTV 1080P

12. 1920*1080 56.250 50 HDTV 1080P

13. 1920*1080 67.43 / 67.5 59.94 / 60 HDTV 1080P

- 10 -

Only for training and service purposes

No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) VIC 3D input proposed mode Proposed

1

640*480

31.469 / 31.5 59.94/ 60 25.125 1

Top-and-Bottom Side-by-side(half)

Secondary(SDTV 480P) Secondary(SDTV 480P)

2 62.938/63 59.94/ 60 50.35/50.4 1

Frame packing Line alternative

Secondary(SDTV 480P) (SDTV 480P)

3 31.469 / 31.5 59.94/ 60 50.35/50.4 1 Side-by-side(Full) (SDTV 480P)

4

720*480

31.469 / 31.5 59.94 / 60 27.00/27.03 2,3

Top-and-Bottom Side-by-side(half)

Secondary(SDTV 480P) Secondary(SDTV 480P)

5 62.938/63 59.94 / 60 54/54.06 2,3

Frame packing Line alternative

Secondary(SDTV 480P) (SDTV 480P)

6 31.469 / 31.5 59.94 / 60 54/54.06 2,3 Side-by-side(Full) (SDTV 480P)

7

720*576

31.25 50 27 17,18

Top-and-Bottom Side-by-side(half)

Secondary(SDTV 576P) Secondary(SDTV 576P)

8 62.5 50 54 17,18

Frame packing Line alternative

Secondary(SDTV 576P) (SDTV 576P)

9 31.25 50 54 17,18 Side-by-side(Full) (SDTV 576P)

10

1280*720

37.5 50 74.25 19

Top-and-Bottom Side-by-side(half)

Primary(HDTV 720P) Primary(HDTV 720P)

11 75 50 148.5 19

Frame packing Line alternative

Primary(HDTV 720P) (HDTV 720P)

12 37.500 50 148.5 19 Side-by-side(Full) (HDTV 720P)

13 44.96 / 45 59.94 / 60 74.18/74.25 4

Top-and-Bottom Side-by-side(half)

Primary(HDTV 720P) Primary(HDTV 720P)

14 89.91/90 59.94 / 60 148.35/148.5 4

Frame packing Line alternative

Primary(HDTV 720P) (HDTV 720P)

15 44.96 / 45 59.94 / 60 148.35/148.5 4 Side-by-side(Full) (HDTV 720P)

16

1920*1080

33.72 / 33.75 59.94 / 60 74.18/74.25 5

Top-and-Bottom Side-by-side(half)

Secondary(HDTV 1080I) Primary(HDTV 1080I)

17 67.432 / 67.50 59.94 / 60 148.35/148.5 5

Frame packing Field alternative

Primary(HDTV 1080I) (HDTV 1080I)

18 33.72 / 33.75 59.94 / 60 148.35/148.5 5 Side-by-side(Full) (HDTV 1080I)

19 28.125 50.00 74.25 20

Top-and-Bottom Side-by-side(half)

Secondary(HDTV 1080I) Primary(HDTV 1080I)

20 56.25 50.00 148.5 20

Frame packing Field alternative

Primary(HDTV 1080I) (HDTV 1080I)

21 28.125 50.00 148.5 20 Side-by-side(Full) (HDTV 1080I)

22 26.97 / 27 23.97 / 24 74.18/74.25 32

Top-and-Bottom Side-by-side(half)

Primary(HDTV 1080P) Primary(HDTV 1080P)

23 43.94/54 23.97 / 24 148.35/148.5 32

Frame packing Line alternative

Primary(HDTV 1080P) (HDTV 1080P)

24 26.97 / 27 23.97 / 24 148.35/148.5 32 Side-by-side(Full) (HDTV 1080P)

25 28.125 25 74.25 33

Top-and-Bottom Side-by-side(half)

Secondary(HDTV 1080P) Secondary(HDTV 1080P)

26 56.24 25 148.5 33

Frame packing Line alternative

Secondary(HDTV 1080P) (HDTV 1080P)

27 28.12 25 148.5 33 Side-by-side(Full) (HDTV 1080P)

28 33.716 / 33.75 29.976 / 30.00 74.18/74.25 34

Top-and-Bottom Side-by-side(half)

Primary(HDTV 1080P) Secondary(HDTV 1080P)

29 67.432 / 67.5 29.976 / 30.00 148.35/148.5 34

Frame packing Line alternative

Primary(HDTV 1080P) (HDTV 1080P)

30 33.716 / 33.75 29.976 / 30.00 148.35/148.5 34 Side-by-side(Full) (HDTV 1080P)

31 56.250 50 148.5 31

Top-and-Bottom Side-by-side(half)

Primary(HDTV 1080P) Secondary(HDTV 1080P)

32 67.43 / 67.5 59.94 / 60 148.35/148.50 16

Top-and-Bottom Side-by-side(half)

Primary(HDTV 1080P) Secondary(HDTV 1080P)

7. 3D Mode

7.1. HDMI 1.4b (3D supported mode automatically)

- 11 -

Only for training and service purposes

7.3. RF Input(3D supported mode manually)

No. Resolution Proposed 3D input proposed mode

1 HD

1080I

720P

2D to 3D Side by Side(Half) Top & Bottom

2 SD

576P

576I

3 SD (ATV : CVBS / SCART) -

7.4. RF Input (3D supported mode automatically)

No. Signal 3D input proposed mode

1 Frame Compatible Side by Side(Half), Top & Bottom

7.2. HDMI Input(1.3)

No. Resolution H-freq(kHz) V-freq.(kHz) Pixel clock(MHz) Proposed 3D input proposed mode

1 720*480 31.5 60 27.03 SDTV 480P

2D to 3D, Side by Side(Half), Top & Bottom, Checker Board, Frame Sequential, Row Interleaving, Column Interleaving

2 720*576 31.25 50 27 SDTV 576P

3 1280*720 45.00 60.00 74.25 HDTV 720P

4 1280*720 37.500 50 74.25 HDTV 720P

5 1920*1080 33.75 60.00 74.25 HDTV 1080I

2D to 3D, Side by Side(Half), Top & Bottom

6 1920*1080 28.125 50.00 74.25 HDTV 1080I

7 1920*1080 27.00 24.00 74.25 HDTV 1080P

2D to 3D, Side by Side(Half), Top & Bottom, Checker Board, Row Interleaving, Column Interleaving

8 1920*1080 28.12 25 74.25 HDTV 1080P

9 1920*1080 33.75 30.00 74.25 HDTV 1080P

10 1920*1080 67.50 60.00 148.5 HDTV 1080P

2D to 3D, Side by Side(Half), Top & Bottom, Checker Board, Single Frame Sequential, Row Interleaving, Column Interleaving

11 1920*1080 56.250 50 148.5 HDTV 1080P

No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode

1 Under 704x480 - - - 2D to 3D

2

Over 704x480 interlaced

- - - 2D to 3D, Side by Side(Half), Top & Bottom

3

Over 704x480 progressive

- 50 / 60 -

2D to 3D, Side by Side(Half), Top & Bottom, Checker Board, Row Interleaving, Column Interleaving, Frame Sequential

4

Over 704x480 progressive

- others -

2D to 3D, Side by Side(Half), Top & Bottom, Checker Board, Row Interleaving, Column Interleaving

No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode

1 Under 320x240 - - - 2D to 3D

2 Over 320x240 - - - 2D to 3D, Side by Side(Half), Top & Bottom

7.5. USB, DLNA (Movie) Input (3D supported mode manually)

7.6. USB, DLNA (Photo) Input (3D supported mode manually)

- 12 -

Only for training and service purposes

No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock Proposed 3D input proposed mode

1 1280*720 45.00 60.00 74.25 HDTV 720P

2D to 3D, Side by Side(Half), Top & Bottom

2 1280*720 37.500 50 74.25 HDTV 720P

3 1920*1080 33.75 60.00 74.25 HDTV 1080I

4 1920*1080 28.125 50.00 74.25 HDTV 1080I

5 1920*1080 27.00 24.00 74.25 HDTV 1080P

6 1920*1080 28.12 25 74.25 HDTV 1080P

7 1920*1080 33.75 30.00 74.25 HDTV 1080P

8 1920*1080 67.50 60.00 148.5 HDTV 1080P

9 1920*1080 56.250 50 148.5 HDTV 1080P

10 Others - - - SDTV

7.8. Component Input(3D) (3D supported mode manually)

No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode Proposed

1 1024*768 48.36 60 65

2D to 3D, Side by Side(half) Top & Bottom

HDTV 768P

2 1360*768 47.71 60 85.5

3 1920*1080 67.500 60 148.50

2D to 3D, Side by Side(half), Top & Bottom, Checker Board, Single Frame Sequential, Row Interleaving, Column Interleaving

HDTV 1080P

4 Others - - -

2D to 3D, Side by Side(half) Top & Bottom

640*350 720*400 640*480 800*600 1152*864

7.7. HDMI-PC Input (3D supported mode manually)

* USB, DNLA Input (3D supported mode automatically)

No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode

1 1080P 33.75 30 -

2D to 3D, Side by Side(Half)*,Top & Bottom*,Checker Board*, Row Interleaving, Column Interleaving(Photo : Side by Side(Half), Top&Bottom)

7.10. 3D Input mode

No. Side by Side Top & Bottom Checker board

Single Frame

Sequential

Frame

Packing

2D to 3D

1

ii.

iii.

iv.

v.

vi.

7.9. Miracast, Widi (3D supported mode manually)

No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode

1 1024X768p - 30 / 60 -

2D to 3D, Side by Side(Half), Top & Bottom2. 1280x720p - 30 / 60 -

3 1920X1080p 30 / 60

4 Others - 2D to 3D

- 13 -

Only for training and service purposes

ADJUSTMENT INSTRUCTION

1. Application Range

This specification sheet is applied to all of the LED TV with LD42B chassis.

2. Designation

(1) Because this is not a hot chassis, it is not necessary to

use an isolation transformer. However, the use of isolation

transformer will help protect test instrument. (2) Adjustment must be done in the correct order. (3) The adjustment must be performed in the circumstance of

25 °C ± 5 °C of temperature and 65 % ± 10 % of relative

humidity if there is no specific designation. (4) The input voltage of the receiver must keep AC 100-240

V~, 50/60 Hz. (5) The receiver must be operated for about 5 minutes prior to

the adjustment when module is in the circumstance of over

15.

In case of keeping module is in the circumstance of 0 °C, it should be placed in the circumstance of above 15 °C for 2 hours.

In case of keeping module is in the circumstance of below

-20 °C, it should be placed in the circumstance of above 15 °C for 3 hours.

[Caution] When still image is displayed for a period of 20 minutes or longer (Especially where W/B scale is strong. Digital pattern 13ch and/or Cross hatch pattern 09ch), there can some afterimage in the black level area.

3. Automatic Adjustment

3.1. MAC address D/L, CI+ key D/L, Widevine key D/L, ESN D/L, HDCP14/20 D/L, DTCP

Connect: USB port Communication Prot connection

▪ Com 1,2,3,4 and 115200(Baudrate)

Mode check: Online Only

▪ Check the test process: DETECT → MAC → CI → Widevine

→ ESN → HDCP14 → HDCP20 → DTCP ▪ Play: Press Enter key ▪ Result: Ready, Test, OK or NG ▪ Printer Out (MAC Address Label)

3.2. LAN Inspection

3.2.1. Equipment & Condition

▪ Each other connection to LAN Port of IP Hub and Jig

3.2.2. LAN inspection solution

▪ LAN Port connection with PCB ▪ Setting automatic IP

▪ If you want manual connection, enter Network connection at

MENU Mode of TV. Press Start connection key, then Network will be connected.

▪ Setting state confirmation

- If automatic setting is finished, you confirm IP and MAC Address at ‘in start’ menu mode.

3.2.3. WIDEVINE key Inspection

- Confirm key input data at the "IN START" MENU Mode.



- 14 -

Only for training and service purposes

3.3. LAN PORT INSPECTION(PING TEST)

Connect SET → LAN port == PC → LAN Port

3.3.1. Equipment setting

(1) Play the LAN Port Test PROGRAM. (2) Input IP set up for an inspection to Test Program.

*IP Number : 12.12.2.2

3.3.2. LAN PORT inspection(PING TEST)

(1) Play the LAN Port Test Program. (2) Connect each other LAN Port Jack. (3) Play Test (F9) button and confirm OK Message. (4) Remove LAN cable.

3.4. Model name & Serial number Download

3.4.1. Model name & Serial number D/L

▪ Press "P-ONLY" key of service remote control.

(Baud rate : 115200 bps)

▪ Connect RS-232C Signal to USB Cable to USB. ▪ Write Serial number by use USB port. ▪ Must check the serial number at Instart menu.

3.4.2. Method & notice

(1) Serial number D/L is using of scan equipment. (2) Setting of scan equipment operated by Manufacturing

Technology Group.

(3) Serial number D/L must be conformed when it is produced

in production line, because serial number D/L is mandatory by D-book 4.0.

* Manual Download (Model Name and Serial Number)

If the TV set is downloaded by OTA or service man, sometimes model name or serial number is initialized.(Not always) It is impossible to download by bar code scan, so It need Manual download.

1) Press the "Instart" key of Adjustment remote control.

2) Go to the menu "7.Model Number D/L" like below photo.

3) Input the Factory model name(ex 47LB650V-ZA) or Serial

number like photo.

4) Check the model name Instart menu. → Factory name

displayed. (ex 47LB650V-ZA)

5) Check the Diagnostics.(DTV country only) → Buyer

model displayed. (ex 47LB650V-ZA)

3.5. CI+ Key checking method

- Check the Section 3.1 Check whether the key was downloaded or not at ‘In Start’ menu. (Refer to below).

=> Check the Download to CI+ Key value in LGset.

3.5.1. Check the method of CI+ Key value

(1) Check the method on Instart menu (2) Check the method of RS232C Command

1) Into the main ass’y mode(RS232: aa 00 00)

2) Check the key download for transmitted command (RS232: ci 00 10)

3) Result value

- Normally status for download : OKx

- Abnormally status for download : NGx

3.5.2. Check the method of CI+ key value(RS232)

1) Into the main ass’y mode(RS232: aa 00 00)

2) Check the mothed of CI+ key by command (RS232: ci 00 20)

3) Result value

i 01 OK 1d1852d21c1ed5dcx

SET PC

CMD 1 CMD 2 Data 0

A A 0 0

CMD 1 CMD 2 Data 0

C I 1 0

CMD 1 CMD 2 Data 0

A A 0 0

CMD 1 CMD 2 Data 0

C I 2 0

CI+ Key Value

- 15 -

Only for training and service purposes

3.6. WIFI MAC ADDRESS CHECK

(1) Using RS232 Command

(2) Check the menu on in-start

4. Manual Adjustment

* ADC adjustment is not needed because of OTP(Auto ADC

adjustment)

4.1. EDID DATA

4.1.1. 3D EDID

▪ Reference

- HDMI1 ~ HDMI3

- In the data of EDID, bellows may be different by S/W or Input mode.

ⓐ Product ID

ⓑ Serial No: Controlled on production line. ⓒ Month, Year: Controlled on production line:

ex) Monthly : ‘01’ → ‘01’

Year : ‘2014’ → ‘18’

ⓓ Model Name(Hex): LGTV

ⓔ Checksum(LG TV): Changeable by total EDID data.

ⓕ Vendor Specific(HDMI)

1) Deep color (module 10bit)

2) None deep color (module 8bit)

ⓖ Colorimetry Data Block(HDMI)

1) The Model not supporting XvYcc

4.1.2. 2D EDID

▪ Reference

- HDMI1 ~ HDMI3

- In the data of EDID, bellows may be different by S/W or Input mode.

ⓐ Product ID

ⓑ Serial No: Controlled on production line. ⓒ Month, Year: Controlled on production line:

ex) Monthly : ‘01’ → ‘01’

Year : ‘2013’ → ‘17’

ⓓ Model Name(Hex): LGTV

ⓔ Checksum(LG TV): Changeable by total EDID data.

ⓕ Vendor Specific(HDMI)

H-freq(kHz) V-freq.(Hz)

Transmission [A][I][][Set ID][][20][Cr] [O][K][X] or [NG]

HEX EDID Table DDC Function

0001 0100 Analog

0001 0100 Digital

Chassis MODEL NAME(HEX)

LD42B 00 00 00 FC 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20

ⓔ1

ⓔ2 ⓔ2

ⓔ3

10bit

/none XvYcc

8bit

/none XvYcc

HDMI1 E7 85 CC X

HDMI2 E7 75 BC X

HDMI3 E7 65 AC X

INPUT MODEL NAME(HEX)

HDMI1 78 03 0C 00 10 00 B8 2D 20 C0 0E 01 4F 3F FC 08 10 18 10 06 10 16 10 28 10

HDMI2 78 03 0C 00 20 00 B8 2D 20 C0 0E 01 4F 3F FC 08 10 18 10 06 10 16 10 28 10

HDMI3 78 03 0C 00 30 00 B8 2D 20 C0 0E 01 4F 3F FC 08 10 18 10 06 10 16 10 28 10

INPUT MODEL NAME(HEX)

HDMI1 E3 05 00 00

HDMI2 E3 05 00 00

HDMI3 E3 05 00 00

INPUT MODEL NAME(HEX)

HDMI1 78 03 0C 00 10 00 80 1E 20 C0 0E 01 4F 3F FC 08 10 18 10 06 10 16 10 28 10

HDMI2 78 03 0C 00 20 00 80 1E 20 C0 0E 01 4F 3F FC 08 10 18 10 06 10 16 10 28 10

HDMI3 78 03 0C 00 30 00 80 1E 20 C0 0E 01 4F 3F FC 08 10 18 10 06 10 16 10 28 10

HEX EDID Table DDC Function

0001 0100 Analog

0001 0100 Digital

Chassis MODEL NAME(HEX)

LD33B 00 00 00 FC 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20

ⓔ1 ⓔ2 ⓔ3

HDMI1 42 1B X

HDMI2 42 0B X

HDMI3 42 FB X

INPUT MODEL NAME(HEX)

HDMI1 67 03 0C 00 10 00 80 1E

HDMI2 67 03 0C 00 20 00 80 1E

HDMI3 67 03 0C 00 30 00 80 1E

- 16 -

Only for training and service purposes

4.2. White Balance Adjustment

4.2.1. Overview

▪ W/B adj. Objective & How-it-works

(1) Objective: To reduce each Panel's W/B deviation (2) How-it-works : When R/G/B gain in the OSD is at 192, it

means the panel is at its Full Dynamic Range. In order to prevent saturation of Full Dynamic range and data, one of R/G/B is fixed at 192, and the other two is lowered to find the desired value.

(3) Adjustment condition : normal temperature

1) Surrounding Temperature : 25 °C ± 5 °C

2) Surrounding Humidity : 20 % ~ 80 %

4.2.2. Equipment

(1) Color Analyzer: CA-210 (LED Module : CH 14) (2) Adjustment Computer(During auto adj., RS-232C protocol

is needed) (3) Adjustment Remote control (4) Video Signal Generator MSPG-925F 720p/204-Gray

(Model: 217, Pattern: 49)

→ Only when internal pattern is not available

▪ Color Analyzer Matrix should be calibrated using CS-1000.

4.2.3. Equipment connection MAP

4.2.4. Adj. Command (Protocol)

- LEN: Number of Data Byte to be sent

- CMD: Command

- VAL: FOS Data value

- CS: Checksum of sent data

- A: Acknowledge Ex) [Send: JA_00_DD] / [Ack: A_00_okDDX]

▪ RS-232C Command used during auto-adjustment.

Ex) wb 00 00 -> Begin white balance auto-adj.

wb 00 10 -> Gain adj. ja 00 ff -> Adj. data

jb 00 c0 ... ...

wb 00 1f → Gain adj. completed *(wb 00 20(Start), wb 00 2f(end)) → Off-set adj. wb 00 ff → End white balance auto-adj.

▪ Adj. Map

Applied Model : LD42B Chassis ALL MODELS

4.2.5. Adj. method

(1) Auto adj. method

1) Set TV in adj. mode using P-Only key.

2) Zero calibrate probe then place it on the center of the

Display.

3) Connect Cable.(RS-232C to USB)

4) Select mode in adj. Program and begin adj.

5) When adj. is complete (OK Sign), check adj. status pre mode. (Cool, Medium, Warm)

6) Remove probe and RS-232C cable to complete adj.

▪ W/B Adj. must begin as start command “wb 00 00” , and

finish as end command “wb 00 ff”, and Adj. offset if need.

(2) Manual adjustment. method

1) Set TV in Adj. mode using P-Only key.

2) Zero Calibrate the probe of Color Analyzer, then place it

on the center of LCD module within 10 cm of the surface.

3) Press ADJ key → EZ adjust using adj. R/C → 7. WhiteBalance then press the cursor to the right(key ►).

(When right key(►) is pressed 204 Gray internal pattern

will be displayed)

4) One of R Gain / G Gain / B Gain should be fixed at 192, and the rest will be lowered to meet the desired value.

5) Adjustment is performed in COOL, MEDIUM, WARM 3

modes of color temperature.

▪ If internal pattern is not available, use RF input. In EZ Adj.

menu 7.White Balance, you can select one of 2 Testpattern: ON, OFF. Default is inner(ON). By selecting OFF, you can adjust using RF signal in 204 Gray pattern.

▪ Adjustment condition and cautionary items

1) Lighting condition in surrounding area

Surrounding lighting should be lower 10 lux. Try to isolate adj. area into dark surrounding.

2) Probe location

: Color Analyzer(CA-210) probe should be within 10 cm

and perpendicular of the module surface (80° ~ 100°)

START 6E A 50 A LEN A 03 A CMD A 00 A VAL A CS STOP

Col or Analy zer

Com puter

* Pat tern Ge nerat or

RS- 232C

USB t o RS-23 2C

RS- 232C

Pro be

Sig nal Sou rce

* If TV internal pattern is used, not needed

RS-232C COMMAND

[CMD ID DATA]

Explanation

wb 00 00 Begin White Balance adjustment

wb 00 10 Gain adjustment(internal white pattern)

wb 00 1f Gain adjustment completed

wb 00 20 Offset adjustment(internal white pattern)

wb 00 2f Offset adjustment completed

wb 00 ff

End White Balance adjustment (internal pattern disappears )

Adj. item

Command

(lower caseASCII)

Data Range

(Hex.)

Default

(Decimal)

CMD1 CMD2 MIN MAX

Cool

R Gain j g 00 C0 G Gain j h 00 C0 B Gain j i 00 C0 R Cut G Cut B Cut

Medium

R Gain j a 00 C0 G Gain j b 00 C0 B Gain j c 00 C0 R Cut G Cut B Cut

Warm

R Gain j d 00 C0 G Gain j e 00 C0 B Gain j f 00 C0 R Cut

G Cut

- 17 -

Only for training and service purposes

4.2.6. Reference (White balance Adj. coordinate and color temperature)

▪ Luminance : 204 Gray ▪ Standard color coordinate and temperature using CS-1000

(over 26 inch)

▪ Standard color coordinate and temperature using CA-210(CH 14)

4.2.7. LED White balance table

- EDGE LED module change color coordinate because of aging time.

- Apply under the color coordinate table, for compensated aging time.

Only march to December & Global Model: (normal line)LGD (LB5xxx, LB6xxx, LB7xxx, LB8xxx)

Only January to Febuary & Global Model: (normal line)LGD (LB5xxx, LB6xxx, LB7xxx, LB8xxx)

AUO, INX, Sharp, CSOT, BOE (Cool : 13000 K)

4.3. Local Dimming Function Check

(1) Normal Edge LED Model

Step 1) Turn on TV. Step 2) Press “TILT” key on the Adj. Remote control. Step 3) A t the Local D im mi ng mo de , module Edge

Backlight moving right to left Back light of IOP

module moving. Step 4) Confirm the Local Dimming mode. Step 5) Press "exit" key.

(2) Only 50inch AUO Local dimming Model(50LA66)

- Test method

Insert the USB memo ry included vide o fi le below inspection pattern in Poweronly mode. Play repeat first, second pattern once per second

(3) Only LA71 Series LGD Local Dimming Model (47/55LA71,

16 block) Step 1) Turn on TV Step 2) Press “TILT” key on the Adj. R/C. Step 3) A t the Local D im mi ng mo de , module Edge

Backlight moving left to right, bottom to Up, Back

light of ALEF module moving. (No1->2->3->….->14

->15->16)

Step 4) Confirm the Local Dimming mode Step 5) Press “exit” Key

Mode

Coordinate

Temp ∆uv

x y

Cool 0.271 0.270 13000 K 0.0000

Medium 0.286 0.289 9300 K 0.0000

Warm 0.313 0.329 6500 K 0.0000

Mode

Coordinate

Temp ∆uv

x y

Cool 0.271 ± 0.002 0.270 ± 0.002 13000 K 0.0000

Medium 0.286 ± 0.002 0.289 ± 0.002 9300 K 0.0000

Warm 0.313 ± 0.002 0.329 ± 0.002 6500K 0.0000

NC4.0

Aging

time

(Min)

Cool Medium Warm

x y x y x y

271 270 286 289 313 329 1 0-2 282 289 297 308 324 348 2 3-5 281 287 296 306 323 346 3 6-9 279 284 294 303 321 333 4 10-19 277 280 292 299 319 339 5 20-35 275 277 290 296 317 336 6 36-49 274 274 289 293 316 333 7 50-79 273 272 288 291 315 331 8 80-119 272 271 287 290 314 330 9 Over 120 271 270 286 289 313 329

NC4.0

Aging

time

(Min)

Cool Medium Warm

x y x y x y

271 270 286 289 313 329 1 0-5 286 295 301 314 328 354 2 6-10 284 290 299 309 326 349 3 11-20 282 287 297 306 324 346 4 21-30 279 283 294 302 321 342 5 31-40 276 278 291 297 318 337 6 41-50 274 275 289 294 316 334 7 51-80 273 272 288 291 315 331 8 81-119 272 271 287 290 314 330 9 Over 120 271 270 286 289 313 329

NC4.0

Cool Medium Warm

x y x y x y

spec 271 270 286 289 313 329

target 278 280 293 299 320 339

- 18 -

Only for training and service purposes

4.4. Magic Motion Remote control test

- Results are automatically marked in Instart OSD after through the AP/Magic Remocon Equipment on the line

4.5. 3D function test(Except Non-3D product)

(Pattern Generator MSHG-600, MSPG-6100[Support HDMI1.4]) * HDMI mode NO. 872 , pattern No.83 (1) Please input 3D test pattern like below.

(2) When 3D OSD appear automatically, then select OK key.

(3) Don't wear a 3D Glasses, check the picture like below.

4.6. Wi-Fi Test

Step 1) Turn on TV Step 2) Select Wi-Fi Connection option in Network Menu.

Step 3) Click Off Button to On in Wi-Fi Connection.

Step 4) The system finds any AP like blow PIC.

Step 5) Select the AP you want to connect.

- 19 -

Only for training and service purposes

4.7. LNB voltage and 22KHz tone check

(only for DVB-S/S2 model)

▪ Test method

(1) Set TV in Adj. mode using POWER ON. (2) Connect cable between satellite ANT and test JIG. (3) Press Yellow key(ETC+SWAP) in Adj Remote control to

make LNB on. (4) Check LED light ‘ON’ at 18 V menu. (5) Check LED light ‘ON’ at 22 KHz tone menu. (6) Press Blue key(ETC+PIP INPUT) in Adj Remote control

to make LNB off. (7) Check LED light ‘OFF’ at 18 V menu. (8) Check LED light ‘OFF’ at 22 KHz tone menu.

▪ Test result

(1) After press LNB On key, ‘18 V LED’ and ‘22 KHz tone

LED’ should be ON.

(2) After press LNB OFF key, ‘18 V LED’ and ‘22 KHz tone

LED’ should be OFF.

4.8. Option selection per country

4.8.1. Overview

- Option selection is only done for models in Non-EU

4.8.2. Method

(1) Press ADJ key on the Adj. R/C, then select Country Group

Meun.

(2) Select Country Group Code 04 or Country Group EU.

5. Tool Option selection

▪ Method : Press "ADJ" key on the Adjustment remote control,

then select Tool option.

6. Ship-out mode check(In-stop)

▪ After final inspection, press "IN-STOP" key of the Adjustment

remote control and check that the unit goes to Stand-by mode.

7. GND and Internal Pressure check

7.1. Method

(1) GND & Internal Pressure auto-check preparation

- Check that Power cord is fully inserted to the SET. (If loose, re-insert)

(2) Perform GND & Internal Pressure auto-check

- Unit fully inserted Power cord, Antenna cable and A/V arrive to the auto-check process.

- Connect D-terminal to AV JACK TESTER

- Auto CONTROLLER(GWS103-4) ON

- Perform GND TEST

- If NG, Buzzer will sound to inform the operator.

- If OK, changeover to I/P check automatically. (Remove CORD, A/V form AV JACK BOX.)

- Perform I/P test

- If NG, Buzzer will sound to inform the operator.

- If OK, Good lamp will lit up and the stopper will allow the pallet to move on to next process.

7.2. Checkpoint

▪ TEST voltage

(1) DQA Test

- GND: 1.5 KV / min at 100 mA

- SIGNAL: 3 KV / min at 100 mA

(2) Mass Production Line Test

- GND: AC 1.5 KV / sec, Cut off current not exceed 100 mA

▪ TEST time: DQA 1 min, Mass Production Line 1 sec ▪ TEST POINT

- GND TEST = POWER CORD GND & SIGNAL CABLE

METAL GND

- Internal Pressure TEST = POWER CORD GND & LIVE &

NEUTRAL

▪ LEAKAGE CURRENT: At 0.5 mArms

8. Audio

Measurement condition:

(1) RF input: Mono, 1 KHz sine wave signal, 100 % Modulation (2) CVBS, Component: 1 KHz sine wave signal 0.5 Vrms (3) RGB PC: 1 KHz sine wave signal 0.7 Vrms

No. Item Min Typ Max Unit Remark

1.

Audio practical max Output, L/R

(Distortion=10%

max Output)

9 10 12 W

EQ Off AVL Off Clear Voice Off

8.10 10.8 Vrms

2.

Speaker (8Ω

Impedance)

9 10 12 W

- 20 -

Only for training and service purposes

9. USB S/W Download(Service only)

(1) Put the USB Stick to the USB socket. (2) Go to General menu then enter to About This TV.

(3) Enter the USB EXPERT MODE.

(4) Updating is starting. (5) Updating completed, the TV will restart automatically (6) If your TV is turned on, check your updated version and

Tool option. (explain the Tool option, next stage)

* If downloading version is more high than your TV have,

TV can lost all channel data. In this case, you have to channel recover. if all channel data is cleared, you didn’t have a DTV/ATV test on production line.

* After downloading, have to adjust Tool Option again.

(1) Push "IN-START" key in service remote control. (2) Select "Tool Option 1" and push "OK" key. (3) Punch in the number. (Each model has their number)

- 21 -

Only for training and service purposes

Audio AMP

NTP

IC101

M14

IF (+/-)

USB1(2.0)

OPTIC

LAN

DDR3 1600 X 16

(512MB X 2EA)

HDMI1

HDMI2

HDMI3

Analog Demod

Digital Demod(T/C)

SYSTEM EEPROM

(256Kb)

USB2(2.0)

USB3(2.0)

41P

51P

eMMC

(4/8GB)

Sub Micom

(RENESAS

R5F1000G)

DDR3 1600 X 16

(512MB X 2EA)

P_TS

50P

X_TAL

24MHz

A B

X_TAL

32.768KHz

I2S Out

I2C 1

EPI

I2C 2

LVDS

USB 2.0

I2C 5

H/P (Line Out)

AV/COMP

D-Demod : I2C 4

OCP

1.5A

(ARC)

REA

R

SID

E

SID

E

REA

R

(H)

AMP

TI

CVBS/YPbPr

SPDIF OUT

ETHERNET

I2C 3

LOCAL DIMMING

BLUTOOTH

IR / KEY/EYE

PM

IC

WIFI

LOGO LIGHT

I2C 2

IR

KEY

UART_BT

(IR Bla Ready)

Tuner : I2C 6

LAN

PHY

OCP

1A

(MHL)

X_TAL

25MHz

I2C(EYE)

PWM

DVB T2/C TUNER

Si2158B

ATV /

DVB-T/C

AIF

TS_ [0:7]

SI2169B

DIF

Si2158B

ATV /

DVB-T/C

IF

DVB T/C TUNER

P_TS P_TS

HDMI Rx.

HDMI / MHL Rx.

USB_WIFI

SCART

CVBS/RGB

DVB T2/C/S2 TUNER

Si2158B

RDA

5815M

ATV /

DVB-T/C

DVB-S

AIF

TS_ [0:7]

SI2169B

DIF

IQ

BLOCK DIAGRAM

- 22 -

Only for training and service purposes

EXPLODED VIEW

Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the Schematic Diagram and EXPLODED VIEW. It is essenti al that these sp ecial safet y parts shoul d be replac ed with the same compon ents as recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards. Do not modify the original design without permission of manufacturer.

IMPORTANT SAFETY NOTICE

900

200

400

800

801

540

521

530

820

500

120

570

910

810

410

420

121

LV1

LV2

A22

A10

Set + Stand

AT1

AG1

AW1

A2

A9

Option

(Option)

Option

Stand Base+Stand Body

(Option)

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

M14-Peripheral

EB_ADDR[4]

EMMC_DATA[0]

EB_ADDR[1]

EB_DATA[2]

EB_ADDR[3]

EMMC_DATA[2]

EB_ADDR[10]

EB_DATA[0]

EMMC_DATA[7]

EMMC_DATA[4]

EB_ADDR[13]

EB_ADDR[6]

EMMC_DATA[3]

EB_ADDR[0]

EB_ADDR[2]

EB_DATA[3]

EMMC_DATA[1]

EB_ADDR[8]

EMMC_DATA[6]

EB_ADDR[5]

EB_DATA[6]

EB_DATA[4]

EB_ADDR[9]

EB_ADDR[7]

EB_DATA[7]

EB_DATA[5]

EB_ADDR[12]

EB_ADDR[14]

EB_DATA[1]

EMMC_DATA[5]

EB_ADDR[11]

OPM1

CAM_INPACK_N

C101-*1

6.8pF 50V

LOADCAP_DVB_PCB

IRB_SPI_MISO/TDI1

C107

0.1uF 16V

R159

3.3K

TP111

I2C_SCL4

TRST_N1

USB_DP3

R101 3.3K

OPT

R156

1.2K

KR_PIP_NOT

TDI0

USB_DM1

SOC_RESET

USB_DP1

I2C_SCL2

LED_SDA

EB_ADDR[0-14]

/PCM_CE1

C102-*1

6.8pF 50V

LOADCAP_DVB_PCB

CAM_IREQ_N

PLLSET1

XTAL_IN

R104 3.3K

OPT

TRST_N1

R162

3.3K

OPM0

LED_SCL

R155-*1

3.3K

KR_PIP

I2C_SCL5

R108

33

I2C_SDA6

USB_CTL2 USB_CTL3

I2C_SDA2

EB_WE_N

R158

3.3K

R163 10K OPT

EB_BE_N1

R182 10K

OPT

R161

3.3K

I2C_SCL4

R105

3.3K

OPT

TP113

IRB_SPI_MISO/TDI1

I2C_SDA1

IRB_SPI_MOSI/TDO1

XTAL_OUT

USB_CTL1

C104

0.1uF 16V

I2C_SDA6

I2C_SDA5

+3.3V_NORMAL

I2C_SDA5

R149

3.3K

TP116

EB_WE_N

I2C_SDA_MICOM_SOC

P102

12507WS-04L

OPT

1

2

3

4

5

I2C_SCL5

R183 10K

I2C_SDA1

PCM_RESET

INSTANT_BOOT

R148-*1

1.5K

KR_PIP

SOC_RESET

USB_DP2

EB_BE_N1

R102 3.3K

OPT

P104

12505WS-10A00

OPT

1

2

3

4

5

6

7

8

9

10

11

PLLSET0

/PCM_CE2

CAM_WAIT_N

PCM_5V_CTL

PLLSET0

I2C_SCL_MICOM_SOC

/PCM_CE1

I2C_SCL6

R184 10K

IRB_SPI_MOSI/TDO1

EB_DATA[0-7]

+3.3V_NORMAL

CAM_CD2_N

EB_BE_N0

TP108

OPM0

R157

3.3K

SOC_TX

+3.3V_NORMAL

R107

33

EB_OE_N

WIFI_DP

R179 10K

1/16W 5%

I2C_SCL2

EB_BE_N0

/USB_OCD3

/USB_OCD2

IRB_SPI_CK/TCK1

EMMC_DATA[0-7]

R185 10K

L/DIM0_VS

(TRST0_N)

CAM_CD2_N

I2C_SDA4

I2C_SDA5

IRB_SPI_SS/TMS1

R1712001%

R150

3.3K

PWM_DIM2

I2C_SDA_MICOM_SOC

+3.3V_NORMAL

I2C_SDA4

R178 33

R106

3.3K

OPT

CAM_REG_N

TP115

TP106

CAM_REG_N

R118

1M

FORCED_JTAG_0

TP110

BOOT_MODE

TCK0

I2C_SCL_MICOM_SOC

PLLSET1

CAM_CD1_N

TP109

EB_ADDR[0-14]

+3.3V_NORMAL

M_REMOTE_TX

I2C_SCL1

L/DIM0_SCLK

TP114

EMMC_CLK

R148

3.3K

KR_PIP_NOT

P103

12505WS-10A00

JTAG_CPU

1

2

3

4

5

6

7

8

9

10

11

R146

3.3K

KR_PIP_NOT

TP103

R143 33

FORCED_JTAG_0

XTAL_OUT

R1722001%

I2C_SCL1

R160

3.3K

TP105

PCM_RESET

USB_DM3

R156-*1

3.3K

KR_PIP

AR101

33

R103 3.3K

OPT

L/DIM0_SCLK

(TMS0)

R121

3.3K

OPT

+3.3V_NORMAL

R180 560

USB_DM2

+3.3V_NORMAL

R128

3.3K

CAM_CD1_N

EB_OE_N

+3.3V_NORMAL

CAM_INPACK_N

PCM_5V_CTL

R169

33

+3.3V_NORMAL

I2C_SCL5

WIFI_DM

IRB_SPI_SS/TMS1

IRB_SPI_CK/TCK1

I2C_SCL6

PWM_DIM

TP102

IC103

AT24C256C-SSHL-T

NVRAM_ATMEL

3

A2

2

A1

4

GND

1

A0

5

SDA

6

SCL

7

WP

8

VCC

CAM_IREQ_N

TP107

SOC_RESET

/USB_OCD1

EB_DATA[0-7]

TP117

R146-*1

1.5K

KR_PIP

M_REMOTE_RX

TDI0

CAM_WAIT_N

BOOT_MODE

TP112

EMMC_CMD

R144 33

R155

1.2K

KR_PIP_NOT

L/DIM0_MOSI

(TDO0)

EMMC_RST

IC103-*1

M24256-BRMN6TP

NVRAM_ST

3

E2

2

E1

4

VSS

1

E0

5

SDA

6

SCL

7

WC

8

VCC

L/DIM0_VS

L/DIM0_MOSI

TP104

/PCM_CE2

TCK0

R127

3.3K

OPT

I2C_SDA2

+3.3V_TUNER

R1742001%

+3.3V_TUNER

R1732001%

OPM1

X101

24MHz

4

GND_2

1

X-TAL_12GND_1

3

X-TAL_2

SOC_RX

AR100

33

1/16W

IC101

LG1311

XIN_MAIN

B23

XO_MAIN

A23

PORES_N

AG21

BOOT_MODE

AJ18

PLLSET0

AB8

PLLSET1

AC8

OPM0

AD8

OPM1

AE8

L_VSOUT_LD/TRST0_N

Y7

DIM0_SCLK/TMS0

Y6

DIM1_SCLK/TCK0

W7

DIM1_MOSI/TDI0

W6

DIM0_MOSI/TDO0

W5

SPI_CS0

AG30

SPI_SCLK0

AG28

SPI_DO0

AG29

SPI_DI0/TRST1_N

AH29

SPI_CS1/TMS1

AJ27

SPI_SCLK1/TCK1

AH27

SPI_DO1/TDO1

AG26

SPI_DI1/TDI1

AH26

EXT_INTR0

AJ12

EXT_INTR1

AJ13

EXT_INTR2

AH12

EXT_INTR3

AG12

UART0_RXD

AH23

UART0_TXD

AG22

UART1_RXD

AH7

UART1_TXD

AJ7

UART1_RTS_N

AG8

UART1_CTS_N

AH8

SCL0

AH11

SDA0

AG11

SCL1

AH9

SDA1

AG9

SCL2

AG10

SDA2

AJ9

SCL3

AH22

SDA3

AJ22

SCL4

AH10

SDA4

AJ10

SCL5

AG23

SDA5

AH24

PWM0

AC6

PWM1

AC7

PWM2

AD7

PWM_IN

AB7

EMMC_CLK

G32

EMMC_CMD

G33

EMMC_RESETN

G31

EMMC_DATA7

D31

EMMC_DATA6

F33

EMMC_DATA5

F32

EMMC_DATA4

E32

EMMC_DATA3

F31

EMMC_DATA2

D33

EMMC_DATA1

D32

EMMC_DATA0

E31

USB2_0_DP0

AN9

USB2_0_DM0

AM9

USB2_0_TXRTUNE

AN8

USB2_1_DP0

H32

USB2_1_DM0

J31

USB2_1_TXRTUNE

H33

USB3_DP0

N31

USB3_DM0

N32

USB3_TXP0

P33

USB3_TXM0

P32

USB3_RXP0

M32

USB3_RXM0

M33

USB3_RESREF0

P31

USB3_DP1

K33

USB3_DM1

K32

USB3_TXP1

L32

USB3_TXM1

L31

USB3_RXP1

K31

USB3_RXM1

J32

USB3_RESREF1

M31

HUB_PORT_OVER0

W28

HUB_VBUS_CTRL0

W29

EB_CS3

H28

EB_CS2

J30

EB_CS1

J28

EB_CS0

J29

EB_WE_N

G30

EB_OE_N

F30

EB_WAIT

H29

EB_BE_N1

G29

EB_BE_N0

G28

CAM_CD1_N

P28

CAM_CD2_N

P27

CAM_CE1_N

U28

CAM_CE2_N

R29

CAM_IREQ_N

V27

CAM_RESET

T28

CAM_INPACK_N

T29

CAM_VCCEN_N

R28

CAM_WAIT_N

U27

CAM_REG_N

N29

EB_ADDR0

K30

EB_ADDR1

E30

EB_ADDR2

M30

EB_ADDR3

N28

EB_ADDR4

M28

EB_ADDR5

M29

EB_ADDR6

L29

EB_ADDR7

K29

EB_ADDR8

K28

EB_ADDR9

L28

EB_ADDR10

D30

EB_ADDR11

F29

EB_ADDR12

C32

EB_ADDR13

C33

EB_ADDR14

C31

EB_ADDR15

B33

EB_DATA0

B32

EB_DATA1

A32

EB_DATA2

B31

EB_DATA3

A31

EB_DATA4

A30

EB_DATA5

B30

EB_DATA6

C30

EB_DATA7

C29

C101

10pF

LOADCAP_ATSC_PCB

C102

10pF

LOADCAP_ATSC_PCB

1

MID_LG1311

2013.04.04 31

M14 Symbol A

PLL SET[1:0] : internal pull up "00" : CPU(1200Mhz),M0 / M1 DDR(792,792 Mhz) "01" : CPU(1056Mhz),M0 / M1 DDR(672,672 Mhz) "10" : CPU(1056Mhz),M0 / M1 DDR(792,792 Mhz) "11" : CPU( 960Mhz),M0 / M1 DDR(792,792 Mhz)

MAIN Clock(24Mhz)

System Configuration

I2C

OP MODE[1:0] "00" : Normal Mode "01/10/11" : Internal Test mode

Extenal test only

BOOT_MODE0

INSTANT_MODE0

INSTANT boot MODE "1 : Instant boot "0 : normal

(internal pull down)

I2C PULL UP

NVRAM

BOOT MODE "0 : EMMC "1 : TEST MODE



Write Protection

- Low : Normal Operation

- High : Write Protection

Jtag-0 I/F

System Clock for Analog block(24Mhz)

Extenal test only

PAGE 1

Clock for M14-A0

Jtag-1 I/F

LOCAL DIMMING I2C CONTROL

I2C_1 : AMP I2C_2 : T-CON,L/DIMING I2C_3 : MICOM I2C_4 : S/Demod,T2/Demod, LNB I2C_5 : NVRAM I2C_6 : TUNER_MOPLL(T/C,ATV)

LGE Internal Use Only

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

M14-Display In/Out

TPI_DATA[3]

FE_DEMOD1_TS_DATA[6]

FE_DEMOD1_TS_DATA[3] FE_DEMOD1_TS_DATA[2]

TPI_DATA[7]

TPO_DATA[0]

TPI_DATA[0]

TPO_DATA[5]

FE_DEMOD1_TS_DATA[7]

TPO_DATA[6]

TPI_DATA[6]

FE_DEMOD1_TS_DATA[0]

TPO_DATA[3]

TPI_DATA[2]

TPO_DATA[1]

TPO_DATA[4]

TPO_DATA[2]

TPI_DATA[1]

TPI_DATA[5]

TPI_DATA[4]

TPO_DATA[7]

FE_DEMOD1_TS_DATA[5]

FE_DEMOD1_TS_DATA[1]

FE_DEMOD1_TS_DATA[4]

TP209

R226

100

1/16W

5%

TPI_ERR

TP210

BT_RESET

FE_DEMOD2_TS_CLK

R221 10K

DDR_3G

FE_DEMOD2_TS_CLK

GST_SOC

TXDCLKN/TX14N

TXBCLKN/TX2N

TXCCLKP/TX20P

R202 10K

BIT0_0

TXC4N/TX18N

R210 10K

BIT4_0

TXA1N/TX10N

BIT5

MODEL_OPT_10

SC_DET

TXC1P/TX22P

FE_DEMOD3_TS_SYNC

BIT1

TP203

BIT7

SC_DET

TPO_SOP

FE_DEMOD3_TS_CLK

BIT3

TPO_VAL

BIT2

FE_DEMOD2_TS_SYNC

TP213

R224

33

OPT

OPC_EN

BIT3

TP219

TPO_CLK

BIT4

COMP1_DET

FE_DEMOD2_TS_DATA

TXC2N/TX21N

TPO_ERR

TXD1N/TX16N

TXD2P/TX15P

TPO_DATA[0-7]

EO_SOC

CAM_SLIDE_DET

TP227

TXB3N/TX1NFE_DEMOD3_TS_ERROR

FE_DEMOD2_TS_VAL

FE_DEMOD3_TS_DATA

TP226

MODEL_OPT_9

FE_DEMOD2_TS_SYNC

R219 10K

DDR3_1.5GB

TPI_VAL

TXBCLKP/TX2P

BIT6

/RST_HUB

FE_DEMOD2_TS_DATA

TP204

TXC2P/TX21P

CAM_SLIDE_DET

TXB2N/TX3N

TP211

TXD1P/TX16P

LED_SCL

BIT0

R201 10K

BIT0_1

TXB4N/TX0N

FE_DEMOD1_TS_SYNC

TP221

C200

1000pF

50V

FE_DEMOD1_TS_ERROR

TPI_CLK

+3.3V_NORMAL

TPI_DATA[0-7]

R215 10K

BIT7_1

TP206

TP202

/TU_RESET1

TXC0N/TX23N

R205 10K

BIT2_1

TXB1N/TX4N

R220 10K

DDR3_2GB

EPI_SOE

TXA2N/TX9N

TPI_DATA[0-7]

FE_DEMOD1_TS_DATA[0-7]

TP208

TXD4N/TX12N

MODEL_OPT_9

TPI_SOP

TP212

TXB4P/TX0P

DEBUG

TPI_VAL

RF_SWITCH_CTL

TXA3N/TX7N

R225 33

OPT

/TU_RESET2

TP214

TXACLKN/TX8N

2D/3D_CTL

/RST_PHY

MCLK_SOC

TXA2P/TX9P

FE_DEMOD2_TS_ERROR

TP228

R203 10K

BIT1_1

LED_SDA

R206 10K

BIT2_0

FE_DEMOD3_TS_CLK

TXC3N/TX19N

TXC4P/TX18P

FE_DEMOD3_TS_DATA

TPI_ERR

TXD4P/TX12P

R209 10K

BIT4_1

TP220

TPI_CLK

BIT2

TXA3P/TX7P

TXD0N/TX17N TXD0P/TX17P

TXA4P/TX6P

FE_DEMOD2_TS_VAL

R222 10K

NON_DDR_3G

GCLK_SOC

TPI_SOP

TXACLKP/TX8P

IR_B_RESET

BIT1

R211 10K

BIT5_1

FE_DEMOD3_TS_ERROR

TXD3N/TX13N

TP225

FE_DEMOD1_TS_VAL

CAM_TRIGGER_DET

MODEL_OPT_8

BIT4

R217 10K

DDR3_DDP

TXA4N/TX6N

R207 10K

BIT3_1

FE_DEMOD2_TS_ERROR

R212 10K

BIT5_0

MODEL_OPT_8

R214 10K

BIT6_0

TXA0N/TX11N

TXC3P/TX19P

TXC0P/TX23P

TP215

BIT5

FE_DEMOD3_TS_VAL

INSTANT_BOOT

EPI_SOE

TPO_ERR

TP207

AV1_CVBS_DET

TXA1P/TX10P

TPO_CLK

TXD2N/TX15N

TXB1P/TX4P

R223

3.3K

TXA0P/TX11P

TXC1N/TX22N

TXB0P/TX5P

BIT7

TP218

R204 10K

BIT1_0

TXD3P/TX13P

TP205

TXDCLKP/TX14P

BIT6

R208 10K

BIT3_0

TXCCLKN/TX20N

TXB3P/TX1P

TXB2P/TX3P

AMP_RESET_N

R218 10K

DDR3_NON_DDP

FE_DEMOD1_TS_CLK

TXB0N/TX5N

FE_DEMOD3_TS_VAL

BIT0

MODEL_OPT_10 EPI_LOCK8/6

TPO_DATA[0-7]

R213 10K

BIT6_1

DEBUG

R216 10K

BIT7_0

HP_DET

TPO_VAL

CAM_TRIGGER_DET

/RST_HUB

+3.3V_NORMAL

FE_DEMOD3_TS_SYNC

SW201

JTP-1127WEM

12

4

3

TPO_SOP

MODEL_OPT_11

MODEL_OPT_12

MODEL_OPT_11

R227 10K

OPT

R229 10K

OPT

R228 10K

OPT

R230 10K

OPT

R231

4.7K

IC101

LG1311

TP_DVB_CLK

AH30

TP_DVB_SOP

AH32

TP_DVB_VAL

AH31

TP_DVB_ERR

AH33

TP_DVB_DATA7

AM33

TP_DVB_DATA6

AL32

TP_DVB_DATA5

AL33

TP_DVB_DATA4

AK32

TP_DVB_DATA3

AK33

TP_DVB_DATA2

AK31

TP_DVB_DATA1

AJ30

TP_DVB_DATA0

AJ31

STPI0_CLK

AL31

STPI0_SOP

AN32

STPI0_VAL

AM32

STPI0_ERR

AN31

STPI0_DATA

AM31

STPI1_CLK

AH28

STPI1_SOP

AJ28

STPI1_VAL

AK30

STPI1_ERR

AJ29

STPI1_DATA

AG27

TPI_CLK

A28

TPI_SOP

B28

TPI_VAL

B29

TPI_ERR

C28

TPI_DATA0

A27

TPI_DATA1

B27

TPI_DATA2

C27

TPI_DATA3

B26

TPI_DATA4

C26

TPI_DATA5

B25

TPI_DATA6

A25

TPI_DATA7

C25

GPIO31

AG13

GPIO30

AJ19

GPIO29

AG14

GPIO28

AG15

GPIO27

AJ15

GPIO26

AH19

GPIO25

AH18

GPIO24

AG19

GPIO23

AH5

GPIO22

AJ5

GPIO21

AJ6

GPIO20

AH6

GPIO19

AG6

GPIO18

AG5

GPIO17

AF7

GPIO16

AG7

GPIO15

AG24

GPIO14

AH16

GPIO13

V29

GPIO12

AJ21

GPIO11

AH21

GPIO10

V28

GPIO9

AG16

GPIO8

AJ24

GPIO7

AH17

GPIO6

AG17

GPIO5

AH13

GPIO4

AH15

GPIO3

AG18

GPIO2

AH14

GPIO1

AJ16

GPIO0

AH20

TPIO_CLK

D28

TPIO_SOP

E29

TPIO_VAL

E28

TPIO_ERR

F28

TPIO_DATA0

D27

TPIO_DATA1

E27

TPIO_DATA2

F27

TPIO_DATA3

E26

TPIO_DATA4

F26

TPIO_DATA5

E25

TPIO_DATA6

D25

TPIO_DATA7

F25

EPI_SOE

AA5

EPI_MCLK

AB5

EPI_GCLK

AA7

EPI_EO

AA6

EPI_VST

AB6

TX_0N

AK8

TX_0P

AL8

TX_1N

AK7

TX_1P

AL7

TX_2N

AM6

TX_2P

AN6

TX_3N

AK6

TX_3P

AL6

TX_4N

AK5

TX_4P

AL5

TX_5N

AN4

TX_5P

AN3

TX_6N

AM2

TX_6P

AM1

TX_7N

AM4

TX_7P

AM3

TX_8N

AL4

TX_8P

AL3

TX_9N

AK2

TX_9P

AK1

TX_10N

AK4

TX_10P

AK3

TX_11N

AJ4

TX_11P

AJ3

TX_12N

AH2

TX_12P

AH1

TX_13N

AH4

TX_13P

AH3

TX_14N

AG4

TX_14P

AG3

TX_15N

AF2

TX_15P

AF1

TX_16N

AF4

TX_16P

AF3

TX_17N

AE4

TX_17P

AE3

TX_18N

AD2

TX_18P

AD1

TX_19N

AD4

TX_19P

AD3

TX_20N

AC4

TX_20P

AC3

TX_21N

AB2

TX_21P

AB1

TX_22N

AB4

TX_22P

AB3

TX_23N

AA4

TX_23P

AA3

TX_LOCKN

AM8

2013.04.04

M14 Symbol B

2

MID_LG1311

31

For ISP

EPI FHD, 60Hz, V14_32 inch (6lane)

HIGH

EPI FHD, 120Hz, V13 (6 lane)

LVDS HD, 60Hz SMALL SMART

1 / 1

1 / 0

TYPE

0 / 0 / 0 / 1

LVDS FHD, 60Hz

DDR3

DDP

FRC

1 / 1 / 0 / 0

0 / 1 / 1 / 1

LVDS FHD, 120Hz

TAIWAN/COLOM

1 / 1 / 1 / 0

OLED

0 / 1 / 0 / 0

EU/CIS

0 / 1 / 1 / 0

0 / 0 / 0 / 0

0 / 1 / 0 / 1

1 / 0 / 1 / 0

0 / 0

1 / 0 / 0 / 1

PAGE 2

PANEL TYPE

BACK-END OPTIONAREA OPTION

2GB

FHD

0 / 0 / 1 / 0

Model Option

MODEL_OPT_8

1 / 0 / 1 / 1

EPI FHD, 120Hz, v14_32inch (6 lane)

Vby1 FHD, 120Hz

1.5GB

BIT[2/3/4/5]DVB

LVDS FHD, 60Hz, CP BOX

1 / 0 / 0 / 0

NON_DDP

EPI FHD, 120Hz, V12 (6 lane)

LOW

1 / 1 / 0 / 1

LVDS HD, 60Hz

DDR3

MODEL_OPT_10

BIT [0/1]

0 / 1

ATSC

0 / 0 / 1 / 1

JP

CHINA/HONGKONG

MODEL_OPT_9

1 / 1 / 1 / 1

EPI FHD, 120Hz, V14 (8 lane)

Near AMP

ASIA/AFRICA

KOREA

N/AMERICA

S/AMERCIA

JAPAN

TAIWAN/COL

T/C

1 / 1

T2/C

BIT [6/7]

1 / 0

0 / 1

T2/C/S2/ATV_SOC

AJJA

0 / 0

T2/C/S2/ATV_EXT

EU/CIS

CHINA/HONG

T/C

T2/C/ATV_SOC

T2/C/S2

DDR3 3G

NON_DDR3 3G

FOR UD

T/C

T2/C

T2/C PIP

Default Default

ISDB

BRAZILKOREA

ISDB PIP

ATSC PIP

ATV_EXT

JAPAN

ATV_SOC

NORTH AMERICA

ATSC PIP ATV_SOC ATV_EXT

MODEL_OPT_11

MODEL_OPT_12

LVDS FHD, 120Hz OLED

T2/C/ATV_EXT

LGE Internal Use Only

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

M14-AV In/Out

C309 1000pF 50V

OPT

TP304

COMP1/AV1/DVI_L_IN

EPHY_REFCLK

D2-_HDMI1

TP316

C337 33pF OPT

C365

0.22uF 10V

HP_OUT

C318 0.047uF

TU_ALL_2178B

D0-_HDMI2

TUNER_SIF

HP_ROUT

R353 0

EU

R373 10

AUDA_OUTR

R365 100

TP308

C316 4.7uF

C346 0.047uF

C351 0.1uF

C11011

0.1uF

16V

INT_ADEMOD

COMP2_PB_IN_SOC

TP312

C356 1uF 10V

SOC_CVBS_OUT

AUDA_OUTL

D1+_HDMI4

EPHY_MDIO

R323 10K

1%

EPHY_TXD0

COMP1_PR_IN_SOC

TP305

R309 27K

1%

SC_CVBS_IN_SOC

+3.3V_NORMAL

ADC_I_INP

C343 0.047uF

TU_CVBS_SOC

SC_FB_SOC

TP302

CK+_HDMI4

R377

5.1K

HP_LOUT_MAIN

ADC_I_INN

R322 10K

1%

C11009 68pF 50V

INT_ADEMOD

C333

0.01uF TU_ALL_IntDemod

TP313

D1+_HDMI1

L305

BLM15BD121SN1

EPHY_TXD1

L307

120-ohm

COMP1_Y_IN_SOC_SOY

C324 0.047uF

C334

0.01uF 50V

EU

R345

51

TU_ALL_IntDemod

C342 22pF OPT

SMARTCARD_PWR_SEL/SD_EMMC_DATA[1]

SMARTCARD_RST/SD_EMMC_DATA[2]

C335 22pF OPT

IF_AGC

R326

75

1%

1005

R350

470

TU_ALL_IntDemod

D1+_HDMI2

COMP2_PR_IN_SOC

CK+_HDMI1

D2+_HDMI1

TP310

C332

0.01uF

TU_ALL_IntDemod

COMP1/AV1/DVI_R_IN

AUDA_OUTL

DDC_SDA_4

R520733

R372 10

C352 0.1uF

SMARTCARD_DATA/SD_EMMC_CLK

SMARTCARD_CLK/SD_EMMC_DATA[0]

C317 4.7uF

R384

4.7K

ADC_I_INP

C306

0.01uF 50V

DDC_SCL_2

TU_CVBS

SMARTCARD_CLK/SD_EMMC_DATA[0]

TP315

SC_ID_SOC

C336

0.01uF 50V

EU

AUAD_R_REF

R11023 390

INT_ADEMOD

DDC_SDA_2

SCART_LOUT_SOC

COMP2_PB_IN_SOC

TP319

HP_LOUT

COMP1_PB_IN_SOC

AUAD_R_CH2_IN

R344

51

TU_ALL_IntDemod

R335 33

SPDIF_OUT

C345 0.047uF

SCART_ROUT_SOC

D0+_HDMI4

5V_HDMI_4

R11022 390

INT_ADEMOD

CK-_HDMI4

L308

BLM18PG121SN1D

HP_OUT

SC_FB_SOC

AUAD_L_REF

R358 68

R303

22K

R520633

AUAD_R_CH2_IN

R310 27K

1%

DDC_SDA_1

COMP1_Y_IN_SOC_SOY

D1-_HDMI2

ADC_I_INN

R359 68

COMP2_Y_IN_SOC

5V_HDMI_2

EPHY_RXD0

COMP1_PB_IN_SOC

TU_CVBS_SOC

D0-_HDMI4

L303 OPT

C344

0.047uF

AUAD_L_CH3_IN

C348 2.2uF

10V

SMARTCARD_DATA/SD_EMMC_CLK

AUD_MASTER_CLK

SMARTCARD_DET/SD_EMMC_DATA[3]

AUAD_L_REF

DDR3_OPT2

AUAD_R_CH3_IN

D2+_HDMI2

D0-_HDMI1

C353

4.7uF 10V

R375 10

COMP1_PR_IN_SOC

DDR3_OPT2

R381 47K 1%

AUAD_L_CH2_IN

DTV/MNT_V_OUT_SOC

SMARTCARD_PWR_SEL/SD_EMMC_DATA[1]

COMP2_PR_IN_SOC

TP314

R312 0

L309

BLM18PG121SN1D

HP_OUT

C349

0.1uF 16V

AVDD25

R357 68

CK+_HDMI2

AUDA_OUTR

DDC_SCL_1

COMP2_Y_IN_SOC_SOY

TP307

L304

BLM15BD121SN1

C338

0.1uF OPT

DDC_SCL_4

DTV/MNT_V_OUT_SOC

R374

51K

1%

SMARTCARD_VCC/SD_EMMC_CMD

AVDD25

AUAD_R_REF

D2-_HDMI2

TP303

C366

0.22uF 10V

HP_OUT

AUD_LRCK

R367 0

GOOGLE

SC_ID_SOC

HDMI_HPD_2

DDR3_OPT1

EPHY_CRS_DV

R380 51K 1%

TP318

TP306

C303 150pF 50V OPT

AV1_CVBS_IN_SOC

EPHY_EN

C305

0.01uF 50V

R368 100 R369

100

TP311

R379

5.1K

10uF

10V

C354

R304

22K

IF_P

COMP1_Y_IN_SOC

R311 0

R351 22K

EU

TP317

R382

4.7K

C331 22pF

TU_ALL_IntDemod

EPHY_MDC

C340 22pF OPT

R383 4.7K

OPT

AUD_LRCH

C312 0.1uF

TU_ALL_2178B

R376

5.1K

SOC_CVBS_OUT

COMP1_Pr

10uF 10VC347

HP_ROUT_AMP

HP_LOUT_AMP

D0+_HDMI2

R354 0

EU

D2-_HDMI4

R329 100

TU_ALL_2178B

TP320

MHL_DET

R356

68

C359 1uF 10V

SPDIF_OUT_ARC

D2+_HDMI4

R318

75

1%

1005

SCART_ROUT_SOC

HDMI_HPD_4

R355 0

EU

AUAD_L_CH3_IN

EPHY_RXD1

D1-_HDMI4

R371 0

GOOGLE

R366 100

CK-_HDMI1

C322 0.047uF

R378 47K 1%

5V_HDMI_1

AUAD_L_CH2_IN

HDMI_HPD_1

DDR3_OPT1

COMP1_Pb

R370 0

GOOGLE

SMARTCARD_RST/SD_EMMC_DATA[2]

R352 22K

EU

I2S_AMP

SC_CVBS_IN_SOC

C357 1uF 10V

D1-_HDMI1

AUD_SCK

D0+_HDMI1

R333

33

C313

4.7uF 10V

COMP1_Y_IN_SOC

SCART_LOUT_SOC

C11010 68pF 50V

INT_ADEMOD

R360 33

IF_N

AUAD_R_CH3_IN

CK-_HDMI2

HP_ROUT_MAIN

SMARTCARD_VCC/SD_EMMC_CMD

C339 100pF 50V

OPT

R385 4.7K

OPT

SMARTCARD_DET/SD_EMMC_DATA[3]

D1-_HDMI3

CK+_HDMI3

D0+_HDMI3

D2-_HDMI3

D2+_HDMI3

CK-_HDMI3

D0-_HDMI3 D1+_HDMI3

HDMI_HPD_3

DDC_SDA_3

DDC_SCL_3

5V_HDMI_3_SOC

D0-_HDMI3

D2+_HDMI3

D1+_HDMI3

CK-_HDMI3

HDMI_HPD_3

D2-_HDMI3 CK+_HDMI3

DDC_SDA_3

D0+_HDMI3

DDC_SCL_3

D1-_HDMI3

5V_HDMI_3_SOC

TP321 TP322 TP323 TP324

TP325 TP326 TP327 TP328 TP329 TP330 TP331 TP332

IC101

LG1311

CVBS_IN1

AL27

CVBS_IN2

AK26

CVBS_IN3

AM27

CVBS_VCM

AL26

BUF_OUT1

AN27

SC1_SID

AL25

SC1_FB

AM25

SOY1_IN

AN23

Y1_IN

AL22

PB1_IN

AK21

PR1_IN

AK22

SOY2_IN

AL24

Y2_IN

AK23

PB2_IN

AL23

PR2_IN

AK24

ADC1_COM

AL21

ADC2_COM

AM23

ADC3_COM

AN25

AVSS25_COMP_REF

AM21

AVDD25_COMP_REF

AN21

AUDA_SCART_OUTL

AK16

AUDA_SCART_OUTR

AL16

AUAD_L_CH1_IN

AL19

AUAD_R_CH1_IN

AK19

AUAD_L_CH2_IN

AN19

AUAD_R_CH2_IN

AM19

AUAD_L_CH3_IN

AN17

AUAD_R_CH3_IN

AM17

AUAD_L_CH4_IN

AL17

AUAD_R_CH4_IN

AK17

AUDA_OUTL

AK20

AUDA_OUTR

AL20

AUAD_L_REF

AK18

AUAD_R_REF

AL18

AUD_VBG_EXT

AN15

IEC958OUT

AM15

AUDCLK_OUT

AN11

DAC_LRCH

AK11

DAC_SLRCH

AK10

DAC_CLFCH

AL10

DAC_SCK

AL11

DAC_LRCK

AM11

PCMI3LRCH

AD5

PCMI3LRCK

AE5

PCMI3SCK

AE7

AUDCLK_IN

AE6

FRC_LRSYNC

AD6

AAD_ADC_SIF

AK29

AAD_ADC_SIFM

AL29

IFAGC

AM29

DMD_DAC_OUT

AK27

DMD_SIF_OUT

AL30

DMD_ADC_INP

AK28

DMD_ADC_INN

AL28

DMD_ADC_INCOM

AN29

SD_CLK

E22

SD_CMD

D22

SD_CD_N

F22

SD_WP_N

F24

SD_DATA3

D24

SD_DATA2

E24

SD_DATA1

F23

SD_DATA0

E23

RMII_REF_CLK

AK14

RMII_CRS_DV

AK12

RMII_MDIO

AL12

RMII_MDC

AK13

RMII_TXEN

AL13

RMII_TXD1

AM13

RMII_TXD0

AN13

RMII_RXD1

AL14

RMII_RXD0

AK15

HDMI_1_SCL

AE27

HDMI_1_SDA

AF28

HDMI_1_HPD

AE29

HDMI_1_5V_DET

AF27

HDMI_1_ARC

AE28

HDMI_1_RX_0

AF33

HDMI_1_RX_0B

AF32

HDMI_1_RX_1

AE31

HDMI_1_RX_1B

AE30

HDMI_1_RX_2

AD31

HDMI_1_RX_2B

AD30

HDMI_1_RX_C

AF31

HDMI_1_RX_CB

AF30

HDMI_2_SCL

AD28

HDMI_2_SDA

AD29

HDMI_2_HPD

AC27

HDMI_2_5V_DET

AD27

HDMI_2_RX_0

AC31

HDMI_2_RX_0B

AC30

HDMI_2_RX_1

AB33

HDMI_2_RX_1B

AB32

HDMI_2_RX_2

AA31

HDMI_2_RX_2B

AA30

HDMI_2_RX_C

AD32

HDMI_2_RX_CB

AD33

HDMI_3_SCL

AB28

HDMI_3_SDA

AB27

HDMI_3_HPD

AB29

HDMI_3_5V_DET

AC28

HDMI_3_RX_0

Y32

HDMI_3_RX_0B

Y33

HDMI_3_RX_1

W31

HDMI_3_RX_1B

W30

HDMI_3_RX_2

V33

HDMI_3_RX_2B

V32

HDMI_3_RX_C

Y31

HDMI_3_RX_CB

Y30

HDMI_4_SCL

Y27

HDMI_4_SDA

AA28

HDMI_4_CBUS_HPD

Y28

HDMI_4_CD_SENSE

AA29

HDMI_4_5V_DET

AA27

HDMI_4_RX_0

T31

HDMI_4_RX_0B

T30

HDMI_4_RX_1

T32

HDMI_4_RX_1B

T33

HDMI_4_RX_2

R31

HDMI_4_RX_2B

R30

HDMI_4_RX_C

U31

HDMI_4_RX_CB

U30

3

2013.04.04

MID_LG1311

31

M14 Symbol C

Close to IC101

AUDIO OUT

Tuner IF Filter

Place SOC Side

Place JACK Side

AV1_CVBS/COMP1_Y Circuit was moved to 34Page

AUDIO IN

COMP

Placed as close as possible to LG1311

PLACE AT JACK SIDE

Placed as close as possible to IC101

Place at JACK SIDE

DDR3 VENDOR OPTION

PAGE 3

MAIN I2S_I/F

To ADC

LGE Internal Use Only

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

M0_DDR_DQ19

M0_DDR_DQ1

M0_DDR_DQS2

R402

1K 1%

M0_DDR_A9

M0_1_DDR_VREFCA

M0_DDR_DQS_N1

M0_DDR_DQS1

M0_DDR_DQ1

R415

1K 1%

VREF_M0_0

M0_DDR_DQ10

R411

1K 1%

M0_DDR_DQ25

M0_DDR_A15

M0_DDR_WEN

R408

1K 1%

M0_DDR_DQ8

M0_DDR_A7

M0_DDR_DQS_N0

M0_1_DDR_VREFDQ

M0_DDR_A6

M0_DDR_DQ15

M0_DDR_A13

M0_DDR_DQS_N2

C401

0.1uF

M0_DDR_DQ4

M0_DDR_A11

M0_DDR_DQS1

M0_DDR_DQ26

M0_DDR_DQ21

M0_DDR_A5

+1.5V_DDR

R410

100

M0_DDR_BA0M0_D_CLKN

M0_DDR_DQ16

M0_DDR_DQ13

M0_DDR_A8

M0_DDR_A10

M0_DDR_DQ21

R412

1K 1%

M0_DDR_DM1

M0_DDR_DQ25

+1.5V_DDR

M0_U_CLKN

M0_DDR_DQS0

M0_DDR_A4

M0_D_CLK

M0_DDR_A13

M0_DDR_A9

M0_D_CLK

M0_DDR_DQ17

M0_DDR_DQS3

M0_DDR_A6

M0_DDR_VREFDQ

M0_DDR_A14

M0_DDR_DQ12

M0_D_CLKN

M0_DDR_DQ23

H5TQ4G63AFR-PBC

IC402

DDR_512MB_HYNIX_1600_29n

A0

N3

A1

P7

A2

P3

A3

N2

A4

P8

A5

P2

A6

R8

A7

R2

A8

T8

A9

R3

A10/AP

L7

A11

R7

A12/BC

N7

A13

T3

A15

M7

BA0

M2

BA1

N8

BA2

M3

CK

J7

CK

K7

CKE

K9

CS

L2

ODT

K1

RAS

J3

CAS

K3

WE

L3

RESET

T2

DQSL

F3

DQSL

G3

DQSU

C7

DQSU

B7

DML

E7

DMU

D3

DQL0

E3

DQL1

F7

DQL2

F2

DQL3

F8

DQL4

H3

DQL5

H8

DQL6

G2

DQL7

H7

DQU0

D7

DQU1

C3

DQU2

C8

DQU3

C2

DQU4

A7

DQU5

A2

DQU6

B8

DQU7

A3

VREFCA

M8

VREFDQ

H1

ZQ

L8

VDD_1

B2

VDD_2

D9

VDD_3

G7

VDD_4

K2

VDD_5

K8

VDD_6

N1

VDD_7

N9

VDD_8

R1

VDD_9

R9

VDDQ_1

A1

VDDQ_2

A8

VDDQ_3

C1

VDDQ_4

C9

VDDQ_5

D2

VDDQ_6

E9

VDDQ_7

F1

VDDQ_8

H2

VDDQ_9

H9

NC_1

J1

NC_2

J9

NC_3

L1

NC_4

L9

A14

T7

VSS_1

A9

VSS_2

B3

VSS_3

E1

VSS_4

G8

VSS_5

J2

VSS_6

J8

VSS_7

M1

VSS_8

M9

VSS_9

P1

VSS_10

P9

VSS_11

T1

VSS_12

T9

VSSQ_1

B1

VSSQ_2

B9

VSSQ_3

D1

VSSQ_4

D8

VSSQ_5

E2

VSSQ_6

E8

VSSQ_7

F9

VSSQ_8

G1

VSSQ_9

G9

M0_DDR_BA0

M0_DDR_A5

M0_DDR_BA2

M0_DDR_DQS_N3

M0_DDR_A1

M0_DDR_BA2

M0_DDR_DQ11

M0_DDR_DQ27

M0_DDR_DQS0

M0_DDR_DQ17

VREF_M0_1

R416

1K 1%

M0_DDR_DQ3

M0_DDR_A3

M0_DDR_A2

M0_DDR_A14

M0_DDR_CKE

M0_DDR_CASN

C407

0.1uF

M0_DDR_A4

R419

240 1%

M0_DDR_DQ24

M0_DDR_CKE

M0_DDR_A13

M0_DDR_DQ7

M0_DDR_DQ9

M0_DDR_DM1

M0_DDR_DQ9

M0_DDR_DQ13

M0_DDR_A12

+1.5V_DDR

C406

0.1uF

M0_U_CLK

M0_DDR_WEN

R414

1K 1%

M0_DDR_DQS_N2

VREF_M0_1

M0_1_DDR_VREFCA

M0_DDR_BA1

C408

0.1uF

M0_DDR_CKE

M0_DDR_DQ20

M0_DDR_DQ5

M0_DDR_A1

R404 10K

OPT

M0_U_CLKN

M0_DDR_DM2

M0_DDR_BA2

M0_DDR_DQS2

M0_DDR_DQ31

M0_DDR_DQ11

M0_DDR_DQ30

R409

1K 1%

M0_DDR_DQ15

M0_DDR_A14

M0_DDR_BA1

M0_DDR_DQS_N3

M0_DDR_A15

M0_DDR_DQ5

M0_DDR_A8

M0_DDR_DQ30

M0_DDR_A6

M0_DDR_DQS_N1

M0_DDR_DQ6

R403

1K 1%

M0_DDR_ODT

M0_DDR_A10

C403

0.1uF

C402

0.1uF

MT41K256M16HA-125:E

IC402-*1

DDR_512MB_MICRON

A0

N3

A1

P7

A2

P3

A3

N2

A4

P8

A5

P2

A6

R8

A7

R2

A8

T8

A9

R3

A10/AP

L7

A11

R7

A12/BC

N7

A13

T3

NC_5

M7

BA0

M2

BA1

N8

BA2

M3

CK

J7

CK

K7

CKE

K9

CS

L2

ODT

K1

RAS

J3

CAS

K3

WE

L3

RESET

T2

DQSL

F3

DQSL

G3

DQSU

C7

DQSU

B7

DML

E7

DMU

D3

DQ0

E3

DQ1

F7

DQ2

F2

DQ3

F8

DQ4

H3

DQ5

H8

DQ6

G2

DQ7

H7

DQ8

D7

DQ9

C3

DQ10

C8

DQ11

C2

DQ12

A7

DQ13

A2

DQ14

B8

DQ15

A3

VREFCA

M8

VREFDQ

H1

ZQ

L8

VDD_1

B2

VDD_2

D9

VDD_3

G7

VDD_4

K2

VDD_5

K8

VDD_6

N1

VDD_7

N9

VDD_8

R1

VDD_9

R9

VDDQ_1

A1

VDDQ_2

A8

VDDQ_3

C1

VDDQ_4

C9

VDDQ_5

D2

VDDQ_6

E9

VDDQ_7

F1

VDDQ_8

H2

VDDQ_9

H9

NC_1

J1

NC_2

J9

NC_3

L1

NC_4

L9

A14

T7

VSS_1

A9

VSS_2

B3

VSS_3

E1

VSS_4

G8

VSS_5

J2

VSS_6

J8

VSS_7

M1

VSS_8

M9

VSS_9

P1

VSS_10

P9

VSS_11

T1

VSS_12

T9

VSSQ_1

B1

VSSQ_2

B9

VSSQ_3

D1

VSSQ_4

D8

VSSQ_5

E2

VSSQ_6

E8

VSSQ_7

F9

VSSQ_8

G1

VSSQ_9

G9

M0_DDR_A3

M0_DDR_DQ27

+1.5V_DDR

M0_DDR_DQ3

M0_DDR_A12

C430

1uF

M0_DDR_DQ19

M0_DDR_DQ8

M0_DDR_BA0

M0_DDR_DQ26

R401 240

1%

M0_DDR_DQ22

M0_DDR_DQS3

M0_DDR_ODT

M0_DDR_A15

M0_D_CLKN

+1.5V_DDR

M0_DDR_RESET_N

C414 1uF

M0_DDR_DQ7

M0_DDR_DQ14

R406

1K 1%

M0_DDR_DM0

M0_DDR_BA1

M0_DDR_RASN

M0_DDR_DQ14

M0_DDR_DQ12

M0_U_CLKN

MT41K256M16HA-125:E

IC401-*1

DDR_512MB_MICRON

A0

N3

A1

P7

A2

P3

A3

N2

A4

P8

A5

P2

A6

R8

A7

R2

A8

T8

A9

R3

A10/AP

L7

A11

R7

A12/BC

N7

A13

T3

NC_5

M7

BA0

M2

BA1

N8

BA2

M3

CK

J7

CK

K7

CKE

K9

CS

L2

ODT

K1

RAS

J3

CAS

K3

WE

L3

RESET

T2

DQSL

F3

DQSL

G3

DQSU

C7

DQSU

B7

DML

E7

DMU

D3

DQ0

E3

DQ1

F7

DQ2

F2

DQ3

F8

DQ4

H3

DQ5

H8

DQ6

G2

DQ7

H7

DQ8

D7

DQ9

C3

DQ10

C8

DQ11

C2

DQ12

A7

DQ13

A2

DQ14

B8

DQ15

A3

VREFCA

M8

VREFDQ

H1

ZQ

L8

VDD_1

B2

VDD_2

D9

VDD_3

G7

VDD_4

K2

VDD_5

K8

VDD_6

N1

VDD_7

N9

VDD_8

R1

VDD_9

R9

VDDQ_1

A1

VDDQ_2

A8

VDDQ_3

C1

VDDQ_4

C9

VDDQ_5

D2

VDDQ_6

E9

VDDQ_7

F1

VDDQ_8

H2

VDDQ_9

H9

NC_1

J1

NC_2

J9

NC_3

L1

NC_4

L9

A14

T7

VSS_1

A9

VSS_2

B3

VSS_3

E1

VSS_4

G8

VSS_5

J2

VSS_6

J8

VSS_7

M1

VSS_8

M9

VSS_9

P1

VSS_10

P9

VSS_11

T1

VSS_12

T9

VSSQ_1

B1

VSSQ_2

B9

VSSQ_3

D1

VSSQ_4

D8

VSSQ_5

E2

VSSQ_6

E8

VSSQ_7

F9

VSSQ_8

G1

VSSQ_9

G9

M0_DDR_CASN

M0_DDR_A2

M0_DDR_CKE

M0_DDR_DQ0

M0_DDR_CASN

M0_DDR_A9

M0_DDR_RESET_N

M0_DDR_DM0

M0_DDR_A11

M0_DDR_A0

M0_DDR_A11

M0_DDR_DQ29

M0_DDR_A7

M0_DDR_DQ6

C429

1uF

R418

240 1%

M0_DDR_A10

+1.5V_DDR

M0_DDR_A5

M0_DDR_RASN

M0_DDR_DM2 M0_DDR_DM3

M0_D_CLK

M0_DDR_DQ29

M0_DDR_DQ18

M0_DDR_DQ31

M0_DDR_DQ10

R405

100

M0_DDR_DQ2

M0_DDR_A8

M0_DDR_RASN

M0_DDR_A4

M0_DDR_DQS_N0

M0_DDR_DQ22

VREF_M0_0

M0_DDR_RESET_N

M0_DDR_DQ16

M0_DDR_DQ20

M0_DDR_DQ0

+1.5V_DDR

M0_DDR_A3

M0_DDR_DQ2

M0_DDR_DQ23

M0_1_DDR_VREFDQ

M0_DDR_DQ24

M0_DDR_A2

M0_DDR_A0

R417 10K

H5TQ4G63AFR-PBC

IC401

DDR_512MB_HYNIX_1600_29n

A0

N3

A1

P7

A2

P3

A3

N2

A4

P8

A5

P2

A6

R8

A7

R2

A8

T8

A9

R3

A10/AP

L7

A11

R7

A12/BC

N7

A13

T3

A15

M7

BA0

M2

BA1

N8

BA2

M3

CK

J7

CK

K7

CKE

K9

CS

L2

ODT

K1

RAS

J3

CAS

K3

WE

L3

RESET

T2

DQSL

F3

DQSL

G3

DQSU

C7

DQSU

B7

DML

E7

DMU

D3

DQL0

E3

DQL1

F7

DQL2

F2

DQL3

F8

DQL4

H3

DQL5

H8

DQL6

G2

DQL7

H7

DQU0

D7

DQU1

C3

DQU2

C8

DQU3

C2

DQU4

A7

DQU5

A2

DQU6

B8

DQU7

A3

VREFCA

M8

VREFDQ

H1

ZQ

L8

VDD_1

B2

VDD_2

D9

VDD_3

G7

VDD_4

K2

VDD_5

K8

VDD_6

N1

VDD_7

N9

VDD_8

R1

VDD_9

R9

VDDQ_1

A1

VDDQ_2

A8

VDDQ_3

C1

VDDQ_4

C9

VDDQ_5

D2

VDDQ_6

E9

VDDQ_7

F1

VDDQ_8

H2

VDDQ_9

H9

NC_1

J1

NC_2

J9

NC_3

L1

NC_4

L9

A14

T7

VSS_1

A9

VSS_2

B3

VSS_3

E1

VSS_4

G8

VSS_5

J2

VSS_6

J8

VSS_7

M1

VSS_8

M9

VSS_9

P1

VSS_10

P9

VSS_11

T1

VSS_12

T9

VSSQ_1

B1

VSSQ_2

B9

VSSQ_3

D1

VSSQ_4

D8

VSSQ_5

E2

VSSQ_6

E8

VSSQ_7

F9

VSSQ_8

G1

VSSQ_9

G9

M0_U_CLK

M0_DDR_DQ18

M0_DDR_VREFDQ

R407

1K 1%

M0_DDR_DQ28

C413 1uF

M0_DDR_RESET_N

M0_DDR_DM3

M0_DDR_WEN

M0_DDR_ODT

+1.5V_DDR

M0_DDR_VREFCA

M0_DDR_A0

M0_DDR_A1

M0_DDR_VREFCA

M0_DDR_DQ28

R413

1K 1%

M0_DDR_DQ4

M0_DDR_A7

+1.5V_DDR

M0_DDR_A12

IC101

LG1311

M0_DDR_VREF1

A22

M0_DDR_VREF2

A3

M0_DDR_A0

E13

M0_DDR_A1

E11

M0_DDR_A2

E15

M0_DDR_A3

E17

M0_DDR_A4

D8

M0_DDR_A5

D16

M0_DDR_A6

D9

M0_DDR_A7

E16

M0_DDR_A8

E9

M0_DDR_A9

E14

M0_DDR_A10

D7

M0_DDR_A11

D10

M0_DDR_A12

D11

M0_DDR_A13

D14

M0_DDR_A14

E10

M0_DDR_A15

E12

M0_DDR_BA0

D17

M0_DDR_BA1

E8

M0_DDR_BA2

D13

M0_DDR_U_CLKP

C8

M0_DDR_U_CLKN

B8

M0_DDR_D_CLKP

C17

M0_DDR_D_CLKN

B17

M0_DDR_CKE

D12

M0_DDR_ODT

E19

M0_DDR_RASN

D19

M0_DDR_CASN

D18

M0_DDR_WEN

E18

M0_DDR_RESET_N

D15

M0_DDR_DQS_P0

B18

M0_DDR_DQS_N0

C18

M0_DDR_DQS_P1

B16

M0_DDR_DQS_N1

A16

M0_DDR_DQS_P2

B9

M0_DDR_DQS_N2

C9

M0_DDR_DQS_P3

B7

M0_DDR_DQS_N3

A7

M0_DDR_DM0

A15

M0_DDR_DM1

A18

M0_DDR_DM2

A6

M0_DDR_DM3

A9

M0_DDR_DQ0

B20

M0_DDR_DQ1

B13

M0_DDR_DQ2

C21

M0_DDR_DQ3

C14

M0_DDR_DQ4

A21

M0_DDR_DQ5

A13

M0_DDR_DQ6

B21

M0_DDR_DQ7

C13

M0_DDR_DQ8

B14

M0_DDR_DQ9

B19

M0_DDR_DQ10

C15

M0_DDR_DQ11

C20

M0_DDR_DQ12

C16

M0_DDR_DQ13

A19

M0_DDR_DQ14

B15

M0_DDR_DQ15

C19

M0_DDR_DQ16

B11

M0_DDR_DQ17

C5

M0_DDR_DQ18

C12

M0_DDR_DQ19

B4

M0_DDR_DQ20

A12

M0_DDR_DQ21

A4

M0_DDR_DQ22

B12

M0_DDR_DQ23

C4

M0_DDR_DQ24

B5

M0_DDR_DQ25

B10

M0_DDR_DQ26

C6

M0_DDR_DQ27

C11

M0_DDR_DQ28

C7

M0_DDR_DQ29

A10

M0_DDR_DQ30

B6

M0_DDR_DQ31

C10

M0_DDR_ZQCAL

E7

MID_LG1311

4

2013.04.04

M14 DDR3-M0

31

DDR3 4Gbit (x16)

PAGE 4

LGE Internal Use Only

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

+1.5V_DDR

M1_DDR_DQS1

M1_DDR_DQS_N3

M1_D_CLK

MT41K256M16HA-125:E

IC502-*1

DDR_512MB_MICRON

A0

N3

A1

P7

A2

P3

A3

N2

A4

P8

A5

P2

A6

R8

A7

R2

A8

T8

A9

R3

A10/AP

L7

A11

R7

A12/BC

N7

A13

T3

NC_5

M7

BA0

M2

BA1

N8

BA2

M3

CK

J7

CK

K7

CKE

K9

CS

L2

ODT

K1

RAS

J3

CAS

K3

WE

L3

RESET

T2

DQSL

F3

DQSL

G3

DQSU

C7

DQSU

B7

DML

E7

DMU

D3

DQ0

E3

DQ1

F7

DQ2

F2

DQ3

F8

DQ4

H3

DQ5

H8

DQ6

G2

DQ7

H7

DQ8

D7

DQ9

C3

DQ10

C8

DQ11

C2

DQ12

A7

DQ13

A2

DQ14

B8

DQ15

A3

VREFCA

M8

VREFDQ

H1

ZQ

L8

VDD_1

B2

VDD_2

D9

VDD_3

G7

VDD_4

K2

VDD_5

K8

VDD_6

N1

VDD_7

N9

VDD_8

R1

VDD_9

R9

VDDQ_1

A1

VDDQ_2

A8

VDDQ_3

C1

VDDQ_4

C9

VDDQ_5

D2

VDDQ_6

E9

VDDQ_7

F1

VDDQ_8

H2

VDDQ_9

H9

NC_1

J1

NC_2

J9

NC_3

L1

NC_4

L9

A14

T7

VSS_1

A9

VSS_2

B3

VSS_3

E1

VSS_4

G8

VSS_5

J2

VSS_6

J8

VSS_7

M1

VSS_8

M9

VSS_9

P1

VSS_10

P9

VSS_11

T1

VSS_12

T9

VSSQ_1

B1

VSSQ_2

B9

VSSQ_3

D1

VSSQ_4

D8

VSSQ_5

E2

VSSQ_6

E8

VSSQ_7

F9

VSSQ_8

G1

VSSQ_9

G9

M1_DDR_A2

M1_DDR_DM2

M1_DDR_DM1

M1_1_DDR_VREFCA

R515

1K 1%

M1_DDR_DQ1

M1_DDR_DQ27

M1_DDR_A14

M1_DDR_A13

M1_DDR_DQS3

C503

0.1uF

M1_DDR_A12

M1_DDR_BA2

M1_DDR_DQS0

M1_DDR_DQ19

M1_DDR_ODT

M1_DDR_A0

M1_DDR_RASN

M1_DDR_CKE

M1_DDR_DQS1M1_DDR_DM1

M1_DDR_DM0

M1_DDR_A13

+1.5V_DDR

M1_DDR_A8

M1_DDR_A6

M1_DDR_DQ15

M1_DDR_DQ0

M1_DDR_VREFCA

R508

1K 1%

R517 10K

C541 1uF

M1_DDR_A0

R507

1K 1%

R506

1K 1%

M1_DDR_A7

+1.5V_DDR

M1_DDR_A5

C507

0.1uF

M1_DDR_DQ10

M1_DDR_DQS_N1

M1_DDR_A10

C502

0.1uF

M1_DDR_DQ9

M1_DDR_DQ6

M1_DDR_BA1

M1_DDR_DQ21

R505

1K 1%

M1_U_CLKN

M1_DDR_DQ3

M1_DDR_DQ21

M1_DDR_DQS_N3

M1_DDR_A8

M1_DDR_A10

R509

1K 1%

M1_DDR_A2

M1_DDR_DQ11

C501

0.1uF

C508

0.1uF

M1_DDR_A3

M1_DDR_A11

M1_DDR_DQ29

M1_DDR_BA1

M1_D_CLK

M1_DDR_BA0

M1_DDR_DM3

M1_DDR_DQ14

M1_DDR_DQ24

H5TQ4G63AFR-PBC

IC502

DDR_512MB_HYNIX_1600_29n

A0

N3

A1

P7

A2

P3

A3

N2

A4

P8

A5

P2

A6

R8

A7

R2

A8

T8

A9

R3

A10/AP

L7

A11

R7

A12/BC

N7

A13

T3

A15

M7

BA0

M2

BA1

N8

BA2

M3

CK

J7

CK

K7

CKE

K9

CS

L2

ODT

K1

RAS

J3

CAS

K3

WE

L3

RESET

T2

DQSL

F3

DQSL

G3

DQSU

C7

DQSU

B7

DML

E7

DMU

D3

DQL0

E3

DQL1

F7

DQL2

F2

DQL3

F8

DQL4

H3

DQL5

H8

DQL6

G2

DQL7

H7

DQU0

D7

DQU1

C3

DQU2

C8

DQU3

C2

DQU4

A7

DQU5

A2

DQU6

B8

DQU7

A3

VREFCA

M8

VREFDQ

H1

ZQ

L8

VDD_1

B2

VDD_2

D9

VDD_3

G7

VDD_4

K2

VDD_5

K8

VDD_6

N1

VDD_7

N9

VDD_8

R1

VDD_9

R9

VDDQ_1

A1

VDDQ_2

A8

VDDQ_3

C1

VDDQ_4

C9

VDDQ_5

D2

VDDQ_6

E9

VDDQ_7

F1

VDDQ_8

H2

VDDQ_9

H9

NC_1

J1

NC_2

J9

NC_3

L1

NC_4

L9

A14

T7

VSS_1

A9

VSS_2

B3

VSS_3

E1

VSS_4

G8

VSS_5

J2

VSS_6

J8

VSS_7

M1

VSS_8

M9

VSS_9

P1

VSS_10

P9

VSS_11

T1

VSS_12

T9

VSSQ_1

B1

VSSQ_2

B9

VSSQ_3

D1

VSSQ_4

D8

VSSQ_5

E2

VSSQ_6

E8

VSSQ_7

F9

VSSQ_8

G1

VSSQ_9

G9

R510

100

M1_DDR_A11

M1_DDR_DQ5

M1_DDR_A10

M1_DDR_DQ23

M1_DDR_DQ16

M1_DDR_DQS_N2

M1_DDR_A5

+1.5V_DDR

M1_DDR_A7

M1_DDR_RASN

M1_DDR_DQ31

M1_DDR_A11

+1.5V_DDR

M1_DDR_DQ22

M1_DDR_DQ18

M1_DDR_DQS_N0

M1_DDR_WEN

M1_DDR_RESET_N

M1_D_CLKN

M1_DDR_DQ22

M1_DDR_BA0

M1_DDR_A5

R519

240

VREF_M1_1

M1_DDR_DQ16

M1_DDR_BA2

R502 10K

OPT

M1_DDR_DQ14

M1_U_CLK

M1_DDR_RESET_N

M1_DDR_DM3

M1_DDR_A4

M1_DDR_DQ0

M1_DDR_A6

M1_DDR_A12

C524

1uF

M1_DDR_A14

M1_DDR_DQ29

M1_DDR_A15

M1_DDR_DQ26

M1_D_CLK

M1_DDR_A13

M1_DDR_DQ6

M1_DDR_DQ4

M1_DDR_DQ17

M1_DDR_A6

M1_DDR_CASN

M1_DDR_A3

M1_DDR_CKE

M1_DDR_DQ12

M1_DDR_WEN

M1_DDR_A1

+1.5V_DDR

M1_DDR_DQ25

M1_DDR_BA0

M1_DDR_DQ23

M1_DDR_DQ3

M1_D_CLKN

M1_DDR_RASNM1_DDR_DQS0 M1_DDR_CASN

R504

1K 1%

R512

1K 1%

M1_DDR_A8

M1_DDR_A0

M1_DDR_DQ13

M1_DDR_DQ11

M1_DDR_DQ20

M1_DDR_DQ15

VREF_M1_0

M1_DDR_CKE

H5TQ4G63AFR-PBC

IC501

DDR_512MB_HYNIX_1600_29n

A0

N3

A1

P7

A2

P3

A3

N2

A4

P8

A5

P2

A6

R8

A7

R2

A8

T8

A9

R3

A10/AP

L7

A11

R7

A12/BC

N7

A13

T3

A15

M7

BA0

M2

BA1

N8

BA2

M3

CK

J7

CK

K7

CKE

K9

CS

L2

ODT

K1

RAS

J3

CAS

K3

WE

L3

RESET

T2

DQSL

F3

DQSL

G3

DQSU

C7

DQSU

B7

DML

E7

DMU

D3

DQL0

E3

DQL1

F7

DQL2

F2

DQL3

F8

DQL4

H3

DQL5

H8

DQL6

G2

DQL7

H7

DQU0

D7

DQU1

C3

DQU2

C8

DQU3

C2

DQU4

A7

DQU5

A2

DQU6

B8

DQU7

A3

VREFCA

M8

VREFDQ

H1

ZQ

L8

VDD_1

B2

VDD_2

D9

VDD_3

G7

VDD_4

K2

VDD_5

K8

VDD_6

N1

VDD_7

N9

VDD_8

R1

VDD_9

R9

VDDQ_1

A1

VDDQ_2

A8

VDDQ_3

C1

VDDQ_4

C9

VDDQ_5

D2

VDDQ_6

E9

VDDQ_7

F1

VDDQ_8

H2

VDDQ_9

H9

NC_1

J1

NC_2

J9

NC_3

L1

NC_4

L9

A14

T7

VSS_1

A9

VSS_2

B3

VSS_3

E1

VSS_4

G8

VSS_5

J2

VSS_6

J8

VSS_7

M1

VSS_8

M9

VSS_9

P1

VSS_10

P9

VSS_11

T1

VSS_12

T9

VSSQ_1

B1

VSSQ_2

B9

VSSQ_3

D1

VSSQ_4

D8

VSSQ_5

E2

VSSQ_6

E8

VSSQ_7

F9

VSSQ_8

G1

VSSQ_9

G9

M1_U_CLKN

M1_DDR_DQS3

R511

1K 1%

M1_DDR_DQ12

M1_DDR_DQS2

VREF_M1_0

M1_DDR_DQ19

M1_DDR_DQS2

M1_DDR_BA1

M1_DDR_A4

C506

0.1uF

M1_DDR_DQ7

M1_DDR_DQ2

M1_1_DDR_VREFCA

M1_DDR_DQ28

M1_DDR_DQ1

M1_DDR_A1

M1_DDR_DM2

M1_DDR_A9

M1_DDR_DQ27

M1_DDR_DQ7

M1_DDR_A7

M1_DDR_BA2

M1_DDR_DQ2

M1_DDR_A1

M1_DDR_VREFCA

M1_DDR_VREFDQ

M1_DDR_DQS_N1

VREF_M1_1

MT41K256M16HA-125:E

IC501-*1

DDR_512MB_MICRON

A0

N3

A1

P7

A2

P3

A3

N2

A4

P8

A5

P2

A6

R8

A7

R2

A8

T8

A9

R3

A10/AP

L7

A11

R7

A12/BC

N7

A13

T3

NC_5

M7

BA0

M2

BA1

N8

BA2

M3

CK

J7

CK

K7

CKE

K9

CS

L2

ODT

K1

RAS

J3

CAS

K3

WE

L3

RESET

T2

DQSL

F3

DQSL

G3

DQSU

C7

DQSU

B7

DML

E7

DMU

D3

DQ0

E3

DQ1

F7

DQ2

F2

DQ3

F8

DQ4

H3

DQ5

H8

DQ6

G2

DQ7

H7

DQ8

D7

DQ9

C3

DQ10

C8

DQ11

C2

DQ12

A7

DQ13

A2

DQ14

B8

DQ15

A3

VREFCA

M8

VREFDQ

H1

ZQ

L8

VDD_1

B2

VDD_2

D9

VDD_3

G7

VDD_4

K2

VDD_5

K8

VDD_6

N1

VDD_7

N9

VDD_8

R1

VDD_9

R9

VDDQ_1

A1

VDDQ_2

A8

VDDQ_3

C1

VDDQ_4

C9

VDDQ_5

D2

VDDQ_6

E9

VDDQ_7

F1

VDDQ_8

H2

VDDQ_9

H9

NC_1

J1

NC_2

J9

NC_3

L1

NC_4

L9

A14

T7

VSS_1

A9

VSS_2

B3

VSS_3

E1

VSS_4

G8

VSS_5

J2

VSS_6

J8

VSS_7

M1

VSS_8

M9

VSS_9

P1

VSS_10

P9

VSS_11

T1

VSS_12

T9

VSSQ_1

B1

VSSQ_2

B9

VSSQ_3

D1

VSSQ_4

D8

VSSQ_5

E2

VSSQ_6

E8

VSSQ_7

F9

VSSQ_8

G1

VSSQ_9

G9

M1_DDR_A9

M1_1_DDR_VREFDQ

M1_DDR_DQ20

M1_DDR_A15

M1_DDR_ODT

M1_DDR_DQ13

M1_DDR_DQ5

R503

100

C525 1uF

M1_DDR_CASN

M1_DDR_DQ4

+1.5V_DDR

M1_DDR_DQ26

M1_DDR_DQ18

+1.5V_DDR

C540

1uF

M1_DDR_DM0

+1.5V_DDR

M1_DDR_DQS_N0

M1_DDR_A9

M1_DDR_DQ28

M1_1_DDR_VREFDQ

M1_DDR_DQ30

M1_U_CLK

M1_DDR_A2

M1_DDR_WEN

M1_DDR_VREFDQ

R501

240

1%

M1_DDR_CKE

M1_DDR_ODT

M1_DDR_DQ24

M1_DDR_DQ8

+1.5V_DDR

M1_DDR_A4

M1_U_CLKN

R516

1K 1%

M1_DDR_DQ25

M1_DDR_DQ8

M1_DDR_DQS_N2

R513

1K 1%

M1_DDR_A14

M1_DDR_RESET_N

R518

240

M1_DDR_RESET_N

M1_DDR_DQ10

M1_DDR_DQ30

M1_U_CLK

M1_D_CLKN

M1_DDR_DQ17

M1_DDR_DQ9

R514

1K 1%

M1_DDR_DQ31

M1_DDR_A12

M1_DDR_A15

H5TQ2G63FFR-PBC

IC501-*2

DDR_256MB_HYNIX_1600_29n

A0

N3

A1

P7

A2

P3

A3

N2

A4

P8

A5

P2

A6

R8

A7

R2

A8

T8

A9

R3

A10/AP

L7

A11

R7

A12/BC

N7

A13

T3

NC_5

M7

BA0

M2

BA1

N8

BA2

M3

CK

J7

CK

K7

CKE

K9

CS

L2

ODT

K1

RAS

J3

CAS

K3

WE

L3

RESET

T2

DQSL

F3

DQSL

G3

DQSU

C7

DQSU

B7

DML

E7

DMU

D3

DQL0

E3

DQL1

F7

DQL2

F2

DQL3

F8

DQL4

H3

DQL5

H8

DQL6

G2

DQL7

H7

DQU0

D7

DQU1

C3

DQU2

C8

DQU3

C2

DQU4

A7

DQU5

A2

DQU6

B8

DQU7

A3

VREFCA

M8

VREFDQ

H1

ZQ

L8

VDD_1

B2

VDD_2

D9

VDD_3

G7

VDD_4

K2

VDD_5

K8

VDD_6

N1

VDD_7

N9

VDD_8

R1

VDD_9

R9

VDDQ_1

A1

VDDQ_2

A8

VDDQ_3

C1

VDDQ_4

C9

VDDQ_5

D2

VDDQ_6

E9

VDDQ_7

F1

VDDQ_8

H2

VDDQ_9

H9

NC_1

J1

NC_2

J9

NC_3

L1

NC_4

L9

NC_6

T7

VSS_1

A9

VSS_2

B3

VSS_3

E1

VSS_4

G8

VSS_5

J2

VSS_6

J8

VSS_7

M1

VSS_8

M9

VSS_9

P1

VSS_10

P9

VSS_11

T1

VSS_12

T9

VSSQ_1

B1

VSSQ_2

B9

VSSQ_3

D1

VSSQ_4

D8

VSSQ_5

E2

VSSQ_6

E8

VSSQ_7

F9

VSSQ_8

G1

VSSQ_9

G9

H5TQ2G63FFR-PBC

IC502-*2

DDR_256MB_HYNIX_1600_29n

A0

N3

A1

P7

A2

P3

A3

N2

A4

P8

A5

P2

A6

R8

A7

R2

A8

T8

A9

R3

A10/AP

L7

A11

R7

A12/BC

N7

A13

T3

NC_5

M7

BA0

M2

BA1

N8

BA2

M3

CK

J7

CK

K7

CKE

K9

CS

L2

ODT

K1

RAS

J3

CAS

K3

WE

L3

RESET

T2

DQSL

F3

DQSL

G3

DQSU

C7

DQSU

B7

DML

E7

DMU

D3

DQL0

E3

DQL1

F7

DQL2

F2

DQL3

F8

DQL4

H3

DQL5

H8

DQL6

G2

DQL7

H7

DQU0

D7

DQU1

C3

DQU2

C8

DQU3

C2

DQU4

A7

DQU5

A2

DQU6

B8

DQU7

A3

VREFCA

M8

VREFDQ

H1

ZQ

L8

VDD_1

B2

VDD_2

D9

VDD_3

G7

VDD_4

K2

VDD_5

K8

VDD_6

N1

VDD_7

N9

VDD_8

R1

VDD_9

R9

VDDQ_1

A1

VDDQ_2

A8

VDDQ_3

C1

VDDQ_4

C9

VDDQ_5

D2

VDDQ_6

E9

VDDQ_7

F1

VDDQ_8

H2

VDDQ_9

H9

NC_1

J1

NC_2

J9

NC_3

L1

NC_4

L9

NC_6

T7

VSS_1

A9

VSS_2

B3

VSS_3

E1

VSS_4

G8

VSS_5

J2

VSS_6

J8

VSS_7

M1

VSS_8

M9

VSS_9

P1

VSS_10

P9

VSS_11

T1

VSS_12

T9

VSSQ_1

B1

VSSQ_2

B9

VSSQ_3

D1

VSSQ_4

D8

VSSQ_5

E2

VSSQ_6

E8

VSSQ_7

F9

VSSQ_8

G1

VSSQ_9

G9

MT41K128M16JT-125:K

IC501-*3

DDR_256MB_MICRON

A0

N3

A1

P7

A2

P3

A3

N2

A4

P8

A5

P2

A6

R8

A7

R2

A8

T8

A9

R3

A10/AP

L7

A11

R7

A12/BC

N7

A13

T3

NC_5

M7

BA0

M2

BA1

N8

BA2

M3

CK

J7

CK

K7

CKE

K9

CS

L2

ODT

K1

RAS

J3

CAS

K3

WE

L3

RESET

T2

DQSL

F3

DQSL

G3

DQSU

C7

DQSU

B7

DML

E7

DMU

D3

DQ0

E3

DQ1

F7

DQ2

F2

DQ3

F8

DQ4

H3

DQ5

H8

DQ6

G2

DQ7

H7

DQ8

D7

DQ9

C3

DQ10

C8

DQ11

C2

DQ12

A7

DQ13

A2

DQ14

B8

DQ15

A3

VREFCA

M8

VREFDQ

H1

ZQ

L8

VDD_1

B2

VDD_2

D9

VDD_3

G7

VDD_4

K2

VDD_5

K8

VDD_6

N1

VDD_7

N9

VDD_8

R1

VDD_9

R9

VDDQ_1

A1

VDDQ_2

A8

VDDQ_3

C1

VDDQ_4

C9

VDDQ_5

D2

VDDQ_6

E9

VDDQ_7

F1

VDDQ_8

H2

VDDQ_9

H9

NC_1

J1

NC_2

J9

NC_3

L1

NC_4

L9

NC_6

T7

VSS_1

A9

VSS_2

B3

VSS_3

E1

VSS_4

G8

VSS_5

J2

VSS_6

J8

VSS_7

M1

VSS_8

M9

VSS_9

P1

VSS_10

P9

VSS_11

T1

VSS_12

T9

VSSQ_1

B1

VSSQ_2

B9

VSSQ_3

D1

VSSQ_4

D8

VSSQ_5

E2

VSSQ_6

E8

VSSQ_7

F9

VSSQ_8

G1

VSSQ_9

G9

MT41K128M16JT-125:K

IC502-*3

DDR_256MB_MICRON

A0

N3

A1

P7

A2

P3

A3

N2

A4

P8

A5

P2

A6

R8

A7

R2

A8

T8

A9

R3

A10/AP

L7

A11

R7

A12/BC

N7

A13

T3

NC_5

M7

BA0

M2

BA1

N8

BA2

M3

CK

J7

CK

K7

CKE

K9

CS

L2

ODT

K1

RAS

J3

CAS

K3

WE

L3

RESET

T2

DQSL

F3

DQSL

G3

DQSU

C7

DQSU

B7

DML

E7

DMU

D3

DQ0

E3

DQ1

F7

DQ2

F2

DQ3

F8

DQ4

H3

DQ5

H8

DQ6

G2

DQ7

H7

DQ8

D7

DQ9

C3

DQ10

C8

DQ11

C2

DQ12

A7

DQ13

A2

DQ14

B8

DQ15

A3

VREFCA

M8

VREFDQ

H1

ZQ

L8

VDD_1

B2

VDD_2

D9

VDD_3

G7

VDD_4

K2

VDD_5

K8

VDD_6

N1

VDD_7

N9

VDD_8

R1

VDD_9

R9

VDDQ_1

A1

VDDQ_2

A8

VDDQ_3

C1

VDDQ_4

C9

VDDQ_5

D2

VDDQ_6

E9

VDDQ_7

F1

VDDQ_8

H2

VDDQ_9

H9

NC_1

J1

NC_2

J9

NC_3

L1

NC_4

L9

NC_6

T7

VSS_1

A9

VSS_2

B3

VSS_3

E1

VSS_4

G8

VSS_5

J2

VSS_6

J8

VSS_7

M1

VSS_8

M9

VSS_9

P1

VSS_10

P9

VSS_11

T1

VSS_12

T9

VSSQ_1

B1

VSSQ_2

B9

VSSQ_3

D1

VSSQ_4

D8

VSSQ_5

E2

VSSQ_6

E8

VSSQ_7

F9

VSSQ_8

G1

VSSQ_9

G9

IC101

LG1311

M1_DDR_VREF1

A2

M1_DDR_VREF2

Y1

M1_DDR_A0

M5

M1_DDR_A1

N5

M1_DDR_A2

K5

M1_DDR_A3

H5

M1_DDR_A4

T4

M1_DDR_A5

H4

M1_DDR_A6

R4

M1_DDR_A7

J5

M1_DDR_A8

T5

M1_DDR_A9

L5

M1_DDR_A10

U4

M1_DDR_A11

P4

M1_DDR_A12

P5

M1_DDR_A13

K4

M1_DDR_A14

R5

M1_DDR_A15

N4

M1_DDR_BA0

G4

M1_DDR_BA1

U5

M1_DDR_BA2

L4

M1_DDR_U_CLKP

R3

M1_DDR_U_CLKN

R2

M1_DDR_D_CLKP

F3

M1_DDR_D_CLKN

F2

M1_DDR_CKE

M4

M1_DDR_ODT

F5

M1_DDR_RASN

E4

M1_DDR_CASN

F4

M1_DDR_WEN

G5

M1_DDR_RESET_N

J4

M1_DDR_DQS_P0

E2

M1_DDR_DQS_N0

E3

M1_DDR_DQS_P1

G2

M1_DDR_DQS_N1

G1

M1_DDR_DQS_P2

P2

M1_DDR_DQS_N2

P3

M1_DDR_DQS_P3

T2

M1_DDR_DQS_N3

T1

M1_DDR_DM0

H1

M1_DDR_DM1

E1

M1_DDR_DM2

U1

M1_DDR_DM3

P1

M1_DDR_DQ0

C2

M1_DDR_DQ1

K2

M1_DDR_DQ2

B3

M1_DDR_DQ3

J3

M1_DDR_DQ4

B1

M1_DDR_DQ5

K1

M1_DDR_DQ6

B2

M1_DDR_DQ7

K3

M1_DDR_DQ8

J2

M1_DDR_DQ9

D2

M1_DDR_DQ10

H3

M1_DDR_DQ11

C3

M1_DDR_DQ12

G3

M1_DDR_DQ13

D1

M1_DDR_DQ14

H2

M1_DDR_DQ15

D3

M1_DDR_DQ16

M2

M1_DDR_DQ17

V3

M1_DDR_DQ18

L3

M1_DDR_DQ19

W2

M1_DDR_DQ20

L1

M1_DDR_DQ21

W1

M1_DDR_DQ22

L2

M1_DDR_DQ23

W3

M1_DDR_DQ24

V2

M1_DDR_DQ25

N2

M1_DDR_DQ26

U3

M1_DDR_DQ27

M3

M1_DDR_DQ28

T3

M1_DDR_DQ29

N1

M1_DDR_DQ30

U2

M1_DDR_DQ31

N3

M1_DDR_ZQCAL

E5

31

M14 DDR3-M1

2013.04.04

MID_LG1311

5

PAGE 5

4Gbit : T7(A14)

DDR3 1.5V bypass Cap

: Place these caps near Memory

DDR3 4Gbit

DDR3 1.5V bypass Cap

: Place these caps near Memory

1_2Gbit : T7(NC_6)

LGE Internal Use Only

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

11/05/31

+1.5V_DDR

C609

0.1uF 16V

C633

0.1uF 16V

C610

JP604

+3.3V_NORMAL

JP601

4.7uF 10V

C602

+2.5V_NORMAL

22uF 10V

C630

OPT

L604

BLM18PG121SN1D

C634

0.1uF 16V

AVDD25_C4TX

22uF 10V

C629

OPT

4.7uF 10V

C618

+3.3V_NORMAL

4.7uF 10V

C614

TP5209

L607

BLM18PG121SN1D

TP5207

DVDD33

L602

BLM18PG121SN1D

+1.1V_VDD

4.7uF 10V

C601

C608

0.1uF 16V

4.7uF 10V

C619

4.7uF 10V

C606

C625

0.1uF 16V

AVDD25_AUD

C628

0.1uF 16V

4.7uF 10V

C613

JP602

+2.5V_NORMAL

4.7uF 10V

C617

C631

0.1uF 16V

AVDD25

TP5210

+1.5V_DDR

DVDD18_EMMC

AVDD11_DMD

C607

0.1uF 16V

AVDD33

AVDD25_AUD

4.7uF 10V

C620

4.7uF 10V

C605

+1.1V_VDD

C627

0.1uF 16V

AVDD25

4.7uF 10V

C604

4.7uF 10V

C622

4.7uF 10V

C623

+1.1V_VDD

AVDD25_C4TX

+1.1V_VDD

L606

BLM18PG121SN1D

AVDD33

L603

BLM18PG121SN1D

4.7uF 10V

C603

C637

0.1uF 16V

C632

0.1uF 16V

C616

0.1uF 16V

C626

0.1uF 16V

+1.5V_DDR

TP5208

+2.5V_NORMAL

VDD3V3_HDMI

JP603

L601

BLM18PG121SN1D

AVDD11_DMD

DVDD33

C615

0.1uF 16V

IC101

LG1311

DVDD33_1

L18

DVDD33_2

L21

DVDD33_3

L22

DVDD33_4

L23

DVDD33_5

M23

DVDD33_6

T11

DVDD33_7

Y23

DVDD33_8

AA23

DVDD33_9

AC12

DVDD33_10

AC13

DVDD33_11

AC14

DVDD33_12

AC15

AVDD33_BT_USB

AC11

AVDD33_USB_1

P23

AVDD33_USB_2

R23

AVDD33_HDMI_1

T23

AVDD33_HDMI_2

U23

AVDD33_HDMI_3

V23

AVDD33_CVBS

AF22

DVDD15_M0_1

F9

DVDD15_M0_2

F10

DVDD15_M0_3

F11

DVDD15_M0_4

F12

DVDD15_M0_5

F13

DVDD15_M0_6

F14

DVDD15_M0_7

F15

DVDD15_M0_8

F16

DVDD15_M0_9

F17

DVDD15_M1_1

G6

DVDD15_M1_2

H6

DVDD15_M1_3

J6

DVDD15_M1_4

K6

DVDD15_M1_5

L6

DVDD15_M1_6

M6

DVDD15_M1_7

N6

DVDD15_M1_8

P6

DVDD15_M1_9

R6

AVDD25_C4TX_1

V11

AVDD25_C4TX_2

W11

AVDD25_C4TX_3

Y11

AVDD25_C4TX_4

AA11

AVDD25_COMP_1

AC18

AVDD25_COMP_2

AC19

AVDD25_CVBS_1

AC20

AVDD25_CVBS_2

AC21

AVDD25_DMD

AC22

AVDD25_AAD

AC23

DVDD25_XTAL

G19

AVDD25_DR3PLL

H19

SP_VQPS

H20

AVDD25_AUD

AC17

AVDD25_APLL

AB23

DVDD11_1

M20

DVDD11_2

M21

DVDD11_3

N13

DVDD11_4

N14

DVDD11_5

N15

DVDD11_6

N16

DVDD11_7

N17

DVDD11_8

N18

DVDD11_9

P20

DVDD11_10

P21

DVDD11_11

R13

DVDD11_12

R14

DVDD11_13

R15

DVDD11_14

R16

DVDD11_15

R17

DVDD11_16

R18

DVDD11_17

R19

DVDD11_18

R20

DVDD11_19

R21

DVDD11_20

T13

DVDD11_21

T20

DVDD11_22

T21

DVDD11_23

U14

DVDD11_24

U15

DVDD11_25

U16

DVDD11_26

U17

DVDD11_27

U18

DVDD11_28

U19

DVDD11_29

U20

DVDD11_30

U21

DVDD11_31

V13

DVDD11_32

V20

DVDD11_33

V21

DVDD11_34

W13

DVDD11_35

W14

DVDD11_36

W15

DVDD11_37

W16

DVDD11_38

W17

DVDD11_39

W18

DVDD11_40

W19

DVDD11_41

Y13

DVDD11_42

Y20

DVDD11_43

Y21

DVDD11_44

AA13

DVDD11_45

AA14

DVDD11_46

AA15

DVDD11_47

AA17

DVDD11_48

AA18

DVDD11_49

AA19

DVDD11_50

AA20

DVDD11_51

AA21

AVDD11_APLL

AB21

AVDD11_COMP_LLPLL

AB19

AVDD11_C4TX_1

V12

AVDD11_C4TX_2

W12

AVDD11_C4TX_3

Y12

AVDD11_C4TX_4

AA12

DVDD11_XTAL

G18

DVDD11_DR3PLL

H18

DVDD11_CVBSPLL

AF23

AVDD11_DMD_1

AF24

AVDD11_DMD_2

AF25

DVDD18_EMMC_1

L26

DVDD18_EMMC_2

M26

IC101

LG1311

GND_1

B22

GND_2

B24

GND_3

C22

GND_4

C23

GND_5

C24

GND_6

D4

GND_7

D5

GND_8

D6

GND_9

D20

GND_10

D21

GND_11

E6

GND_12

E20

GND_13

E21

GND_14

F6

GND_15

F7

GND_16

F8

GND_17

F18

GND_18

F19

GND_19

F20

GND_20

F21

GND_21

G7

GND_22

G8

GND_23

G9

GND_24

G10

GND_25

G11

GND_26

G12

GND_27

G13

GND_28

G14

GND_29

G15

GND_30

G16

GND_31

G17

GND_32

G20

GND_33

G21

GND_34

G22

GND_35

G23

GND_36

G24

GND_37

G25

GND_38

G26

GND_39

G27

GND_40

H7

GND_41

H8

GND_42

H9

GND_43

H10

GND_44

H11

GND_45

H12

GND_46

H13

GND_47

H14

GND_48

H15

GND_49

H16

GND_50

H17

GND_51

H21

GND_52

H22

GND_53

H23

GND_54

H24

GND_55

H25

GND_56

H26

GND_57

H27

GND_58

H31

GND_59

J7

GND_60

J8

GND_61

J26

GND_62

J27

GND_63

K7

GND_64

K8

GND_65

K26

GND_66

K27

GND_67

L7

GND_68

L8

GND_69

L11

GND_70

L12

GND_71

L13

GND_72

L14

GND_73

L15

GND_74

L16

GND_75

L17

GND_76

L19

GND_77

L20

GND_78

L27

GND_79

M7

GND_80

M8

GND_81

M11

GND_82

M12

GND_83

M13

GND_84

M14

GND_85

M15

GND_86

M16

GND_87

M17

GND_88

M18

GND_89

M19

GND_90

M22

GND_91

M27

GND_92

N7

GND_93

N8

GND_94

N11

GND_95

N12

GND_96

N19

GND_97

N20

GND_98

N21

GND_99

N22

GND_100

N23

GND_101

N26

GND_102

N27

GND_103

N30

GND_104

P7

GND_105

P8

GND_106

P11

GND_107

P12

GND_108

P13

GND_109

P14

GND_110

P15

GND_111

P16

GND_112

P17

GND_113

P18

GND_114

P19

GND_115

P22

GND_116

P26

GND_117

P30

GND_118

R7

GND_119

R8

GND_120

R11

GND_121

R12

GND_122

R22

GND_123

R26

GND_124

R27

GND_125

T6

GND_126

T7

GND_127

T8

GND_128

T12

GND_129

T14

GND_130

T15

GND_131

T16

GND_132

T17

GND_133

T18

GND_134

T19

GND_135

T22

GND_136

T26

GND_137

T27

GND_138

U6

GND_139

U7

GND_140

U8

GND_141

U11

GND_142

U12

GND_143

U13

GND_144

U22

GND_145

U26

GND_146

V4

GND_147

V5

GND_148

V6

GND_149

V7

GND_150

V8

GND_151

V14

GND_152

V15

GND_153

V16

GND_154

V17

GND_155

V18

GND_156

V19

GND_157

V22

GND_158

V26

GND_159

V30

GND_160

V31

GND_161

W4

GND_162

W8

GND_163

W20

GND_164

W21

GND_165

W22

GND_166

W23

GND_167

W26

GND_168

W27

GND_169

Y2

GND_170

Y3

GND_171

Y4

GND_172

Y8

GND_173

Y14

GND_174

Y15

GND_175

Y16

GND_176

Y17

GND_177

Y18

GND_178

Y19

GND_179

Y22

GND_180

Y26

GND_181

AA8

GND_182

AA16

GND_183

AA22

GND_184

AA26

GND_185

AB11

GND_186

AB12

GND_187

AB13

GND_188

AB14

GND_189

AB15

GND_190

AB16

GND_191

AB17

GND_192

AB18

GND_193

AB20

GND_194

AB22

GND_195

AB26

GND_196

AB30

GND_197

AB31

GND_198

AC16

GND_199

AC26

GND_200

AD26

GND_201

AE26

GND_202

AF6

GND_203

AF8

GND_204

AF9

GND_205

AF10

GND_206

AF11

GND_207

AF12

GND_208

AF13

GND_209

AF14

GND_210

AF15

GND_211

AF16

GND_212

AF17

GND_213

AF18

GND_214

AF19

GND_215

AF20

GND_216

AF21

GND_217

AF26

GND_218

AG20

GND_219

AG25

GND_220

AG31

GND_221

AH25

GND_222

AJ25

GND_223

AK9

GND_224

AK25

GND_225

AL9

GND_226

AL15

MID_LG1311

6

31

VCC & GND

2013.04.04

+2.5V_Bypass Cap

+3.3V_Bypass Cap

+1.1V_Bypass Cap

GND JIG POINT

+1.5V_Bypass Cap

AFE 3CH Power

PAGE 6

LGE Internal Use Only

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

CI_DATA[0]

CI_ADDR[4]

EB_DATA[7]

CI_DATA[5]

CI_ADDR[1]

CI_IN_TS_DATA[0]

CI_DATA[7]

CI_DATA[1]

CI_DATA[3]

CI_IN_TS_DATA[5] CI_IN_TS_DATA[6]

TPO_DATA[7]

TPO_DATA[3]

CI_ADDR[11]

EB_DATA[5]

TPO_DATA[5]

TPO_DATA[2]

CI_ADDR[3]

CI_DATA[4]

CI_ADDR[5]

CI_IN_TS_DATA[3]

EB_DATA[6]

CI_IN_TS_DATA[1]

CI_ADDR[7]

EB_DATA[2]

TPO_DATA[0]

CI_ADDR[13]

CI_IN_TS_DATA[4]

CI_ADDR[8]

EB_DATA[4]

CI_ADDR[6]

CI_IN_TS_DATA[7]

CI_ADDR[14]

CI_ADDR[2]

EB_DATA[0]

CI_DATA[4]

CI_ADDR[12]

TPO_DATA[4]

EB_DATA[0-7]

EB_DATA[3]

TPO_DATA[6]

EB_DATA[1]

CI_ADDR[0]

CI_ADDR[10]

CI_DATA[0]

CI_DATA[1]

CI_IN_TS_DATA[2]

TPO_DATA[1]

CI_DATA[6]

CI_DATA[2]

CI_DATA[7]

CI_ADDR[9]

CI_DATA[3]

CI_DATA[2]

CI_DATA[5] CI_DATA[6]

+5V_CI_ON

CAM_REG_N

CI_ADDR[10]

CI_TS_DATA[2]

AR709

33

CI

CI_TS_DATA[4]

CI_IN_TS_CLK

C707

0.1uF 16V

CI

/PCM_IOWR

CI_ADDR[8]

EB_ADDR[2]

CI_IN_TS_DATA[3]

R701

33

OPT

CI_TS_DATA[5]

EB_ADDR[9]

CI_TS_CLK

PCM_INPACK

C703 12pF 50V OPT

EB_ADDR[11]

CI_TS_SYNC

C705

0.1uF 16V

CI

TPI_DATA[6]

EB_ADDR[12]

/PCM_CE2

EB_ADDR[10]

CI_IN_TS_DATA[4]

CI_TS_DATA[6]

/PCM_WE

CI_ADDR[10]

PCM_INPACK

AR705

100

CI

R720 33

CI

EB_WE_N

C701

0.1uF CI

PCM_RESET

CI_TS_VAL

CI_ADDR[7]

CI_ADDR[0]

R715

100

CI

AR712

33

CI

CI_IN_TS_DATA[2]

R726

10K

CI_ADDR[5]

AR708

33

CI

CI_TS_DATA[7]

AR706

100

CI

EB_ADDR[3]

CI_TS_DATA[2]

CI_IN_TS_SYNC

CI_TS_CLK

CI_ADDR[8]

/PCM_OE

R722 10K

AR713

33

CI

CI_IN_TS_DATA[5]

CI_TS_DATA[0]

AR711

33

CI

CI_TS_DATA[1]

TPO_VAL

TPI_DATA[1]

/PCM_IORD

CI_IN_TS_DATA[0-7]

/CI_CD1

CI_ADDR[13]

CI_TS_DATA[0]

CI_ADDR[5]

AR704

100

EB_DATA[0-7]

CI_IN_TS_DATA[1]

R725

10K

AR710

33

CI

CI_ADDR[4]

TPO_CLK

C706

0.1uF 16V

CI

CAM_CD2_N

CI_ADDR[0]

CI_ADDR[6]

CI_IN_TS_VAL

/PCM_WAIT

+5V_NORMAL

CI_DATA[0-7]

R707

10K

CI

CI_IN_TS_DATA[0]

CI_TS_DATA[1]

CI_ADDR[9]

/CI_CD1

/PCM_REG

CAM_INPACK_N

/PCM_IRQA

R721 33

OPT

CI_ADDR[7]

/PCM_IOWR

CI_ADDR[14]

CI_ADDR[11]

CI_ADDR[2]

TPI_CLK

EB_ADDR[6]

CI_TS_DATA[7]

CI_IN_TS_DATA[6]

TPI_DATA[0]

EB_ADDR[13]

CI_ADDR[1]

AR714

33

CI

CAM_CD1_N

/CI_CD2

+5V_CI_ON

/PCM_IRQA

EB_ADDR[14]

CI_ADDR[6]

CI_TS_DATA[4]

CI_ADDR[4]

CI_IN_TS_DATA[7]

CAM_WAIT_N

CI_ADDR[11]

/PCM_REG

CI_ADDR[13]

TPO_DATA[0-7]

AR707

100

CI

TPI_SOP

R703

33

CI

CI_ADDR[3]

CI_TS_VAL

EB_BE_N0

R716 100

CI

CI_TS_DATA[5]

R702

33

CI

/CI_CD2

/PCM_WE

AR701

33

CI

TPI_DATA[4]

EB_ADDR[1]

CI_ADDR[14]

TPO_SOP

TPI_DATA[7]

PCM_INPACK

/PCM_CE2

EB_ADDR[7]

+5V_CI_ON

TPI_DATA[3]

EB_ADDR[5]

C704 0.1uF

CI

AR703

33

CI

C708 12pF 50V OPT

EB_BE_N1

CI_ADDR[2]

/PCM_IORD

CI_IN_TS_CLK

TPI_DATA[5]

CI_ADDR[12]

TPI_VAL

/PCM_WAIT

EB_ADDR[4]

CI_DATA[0-7]

AR702

33

CI

C702

4.7uF 10V CI

CI_ADDR[1]

EB_OE_N

CI_IN_TS_VAL

CAM_IREQ_N

CI_TS_DATA[3]

CI_ADDR[3]

CI_ADDR[9]

/PCM_CE1

CI_TS_SYNC

TPI_DATA[2]

EB_ADDR[8]

CI_TS_DATA[6]

CI_ADDR[12]

CI_TS_DATA[3]

EB_ADDR[0]

/PCM_OE

CI_IN_TS_SYNC

JK701

10125901-015LF

CI

G1G2

57

21

52

16

10

47

41

5

36

59

23

45

54

18

49

43

13

7

38

2

25

56

20

51

15

9

46

40

4

35

58

22

53

17

11

48

42

12

6

37

1

24

55

19

50

44

14

8

39

3

2660 2761 2862 2963 3064 31 32 33 34

65 66 67 68

69

PCMCIA

31

7

2013.03.22

MID_LG1311

PAGE 7

LGE Internal Use Only

LG 42LB65 Series, 42LB650V Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual