LG 37LV370S, 37LV375G/S/W, 47LV370S, 47LV375G, 47LV375W Service Manual
...
LED LCD TV
SERVICE MANUAL
CAUTION
BEFORE SERVICING THE CHASSIS,
READ THE SAFETY PRECAUTIONS IN THIS MANUAL.
CHASSIS : LD12B
MODEL : 37LV370S 37LV370S-ZB
MODEL : 37LV375G/S/W
37LV375G/S/W-ZC
North/Latin America http://aic.lgservice.com
Europe/Africa http://eic.lgservice.com
Asia/Oceania http://biz.lgservice.com
Internal Use Only
Printed in KoreaP/NO : MFL67002312 (1103-REV00)
- 2 -
LGE Internal Use OnlyCopyright © 2011 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
CONTENTS
CONTENTS .............................................................................................. 2
PRODUCT SAFETY ................................................................................. 3
SPECIFICATION ....................................................................................... 4
ADJUSTMENT INSTRUCTION ................................................................ 8
BLOCK DIAGRAM.................................................................................. 14
EXPLODED VIEW .................................................................................. 15
SCHEMATIC CIRCUIT DIAGRAM ..............................................................
- 3 -
LGE Internal Use OnlyCopyright © 2011 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
SAFETY PRECAUTIONS
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the
Schematic Diagram and Exploded View.
It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent
Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.
General Guidance
An isolation Transformer should always be used during the
servicing of a receiver whose chassis is not isolated from the AC
power line. Use a transformer of adequate power rating as this
protects the technician from accidents resulting in personal injury
from electrical shocks.
It will also protect the receiver and it's components from being
damaged by accidental shorts of the circuitry that may be
inadvertently introduced during the service operation.
If any fuse (or Fusible Resistor) in this TV receiver is blown,
replace it with the specified.
When replacing a high wattage resistor (Oxide Metal Film Resistor,
over 1 W), keep the resistor 10 mm away from PCB.
Keep wires away from high voltage or high temperature parts.
Before returning the receiver to the customer,
always perform an AC leakage current check on the exposed
metallic parts of the cabinet, such as antennas, terminals, etc., to
be sure the set is safe to operate without damage of electrical
shock.
Leakage Current Cold Check(Antenna Cold Check)
With the instrument AC plug removed from AC source, connect an
electrical jumper across the two AC plug prongs. Place the AC
switch in the on position, connect one lead of ohm-meter to the AC
plug prongs tied together and touch other ohm-meter lead in turn to
each exposed metallic parts such as antenna terminals, phone
jacks, etc.
If the exposed metallic part has a return path to the chassis, the
measured resistance should be between 1 MΩ and 5.2 MΩ.
When the exposed metal has no return path to the chassis the
reading must be infinite.
An other abnormality exists that must be corrected before the
receiver is returned to the customer.
Leakage Current Hot Check (See below Figure)
Plug the AC cord directly into the AC outlet.
Do not use a line Isolation Transformer during this check.
Connect 1.5 K / 10 watt resistor in parallel with a 0.15 uF capacitor
between a known good earth ground (Water Pipe, Conduit, etc.)
and the exposed metallic parts.
Measure the AC voltage across the resistor using AC voltmeter
with 1000 ohms/volt or more sensitivity.
Reverse plug the AC cord into the AC outlet and repeat AC voltage
measurements for each exposed metallic part. Any voltage
measured must not exceed 0.75 volt RMS which is corresponds to
0.5 mA.
In case any measurement is out of the limits specified, there is
possibility of shock hazard and the set must be checked and
repaired before it is returned to the customer.
Leakage Current Hot Check circuit
1.5 Kohm/10W
To Instrument's
exposed
METALLIC PARTS
Good Earth Ground
such as WATER PIPE,
CONDUIT etc.
AC Volt-meter
When 25A is impressed between Earth and 2nd Ground
for 1 second, Resistance must be less than 0.1
*Base on Adjustment standard
IMPORTANT SAFETY NOTICE
0.15 uF
Ω
- 4 -
LGE Internal Use OnlyCopyright © 2011 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
SPECIFICATION
NOTE : Specifications and others are subject to change without notice for improvement
.
1. Application range
This specification is applied to the LCD TV used LD12B chassis.
2. Requirement for Test
Each part is tested as below without special appointment.
1) Temperature: 25 ºC ± 5 ºC(77 ºF ± 9 ºF), CST: 40 ºC ± 5 ºC
2) Relative Humidity : 65 % ± 10 %
3) Power Voltage
: Standard input voltage (AC 100-240 V~, 50 / 60 Hz)
* Standard Voltage of each products is marked by models.
4) Specification and performance of each parts are followed each drawing and specification by part number in accordance with
BOM.
5) The receiver must be operated for about 5 minutes prior to the adjustment.
3. Test method
1) Performance: LGE TV test method followed
2) Demanded other specification
- Safety : CE, IEC specification
- EMC :CE, IEC
- 5 -
LGE Internal Use OnlyCopyright © 2011 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
4. Model General Specification
No. Item Specification Remarks
1 Market EU(PAL Market-36Countries) DTV & Analog (Total 36 countries)
DTV (MPEG2/4, DVB-T) : 31 countries
(England/Italy/Germany/France/Spain/Sweden/Finland/Netherlands/Belgium/Luxemburg/
Greece/Denmark/Czech/Austria /Hungary/Swiss/Croatia/Turkey/Norway/Slovenia/Poland/
Ukraine/Portugal/Ireland/Moroco/Latvia/Estonia/Lithania/Rumania/Russia/Slovakia)
DTV (MPEG2/4, DVB-T2): 5 countries
(England/Sweden/Finland/Denmark/Norway)
DTV (MPEG2/4, DVB-C): 10 countries
(Sweden/Finland/Denmark/Norway/Austria/Swiss/Germany/Netherlands/Hungary/Slovenia)
Analog Only - 5 countries
(Bosnia/Serbia/Bulgaria/Albania/Kazakhstan)
2 Broadcasting system 1) PAL-BG - DVB-T2/S is supported in specific models.
2) PAL-DK 1. DVB-T2 : Model name : xxxxxxxT
3) PAL-I/I’ 2. DVB-S : Model name : xxxxxxxS
4) SECAM L/L’ - SECAM L/L’ is not supported in DVB-T2 models.
5) DVB-T/C
6) DVB-T2
7) DVB-S
3 Receiving system Analog : Upper Heterodyne
G DVB-T
Digital : COFDM , QAM - Guard Interval(Bitrate_Mbit/s)
1/4, 1/8, 1/16, 1/32
- Modulation : Code Rate
QPSK : 1/2, 2/3, 3/4, 5/6, 7/8
16-QAM : 1/2, 2/3, 3/4, 5/6, 7/8
64-QAM : 1/2, 2/3, 3/4, 5/6, 7/8
G DVB-C
- Symbolrate : 4.0Msymbols/s to 7.2Msymbols/s
- Modulation : 16QAM, 64-QAM, 128-QAM and 256-QAM
G DVB-T2
- Guard Interval(Bitrate_Mbit/s)
1/4,1/8,1/16,1/32,1/128,19/128,19/256,
- Modulation : Code Rate
QPSK : 1/2, 2/5, 2/3, 3/4, 5/6
16-QAM : 1/2, 2/5, 2/3, 3/4, 5/6
64-QAM : 1/2, 2/5, 2/3, 3/4, 5/6
256-QAM : 1/2, 2/5, 2/3, 3/4, 5/6
G DVB-S
G DVB-S2
4 Scart Jack (1EA) PAL, SECAM Scart Jack is Full scart and support RF-OUT(analog & DTV)
SECAM is not supported in DVB-T2 models.
5 Video Input RCA(1EA) PAL, SECAM, NTSC 4System : PAL, SECAM, NTSC, PAL60
SECAM is not supported in DVB-T2 models.
6 Component Input(1EA) Y/Cb/Cr, Y/Pb/Pr
7 RGB Input RGB-PC Analog(D-SUB 15PIN)
8 HDMI Input (3EA) HDMI1-DTV (DVI) PC(HDMI version 1.3)
HDMI2-DTV Support HDCP
HDMI3-DTV
9 Audio Input (3EA) RGB/DVI Audio, Component, AV L/R Input
10 SDPIF out (1EA) SPDIF out
11 Earphone out (1EA) Antenna, AV1, AV2, AV3, Component,
RGB, HDMI1, HDMI2, HDMI3, USB
12 USB (1EA) EMF JPEG, MP3
For SVC (download)
DivX HD
- 6 -
LGE Internal Use OnlyCopyright © 2011 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
5. Component Video Input (Y, CB/PB, CR/PR)
No.
Specification
Remark
Resolution H-freq(kHz) V-freq(Hz)
1. 720x480 15.73 60.00 SDTV,DVD 480i
2. 720x480 15.63 59.94 SDTV,DVD 480i
3. 720x480 31.47 59.94 480p
4. 720x480 31.50 60.00 480p
5. 720x576 15.625 50.00 SDTV,DVD 625 Line
6. 720x576 31.25 50.00 HDTV 576p
7. 1280x720 45.00 50.00 HDTV 720p
8. 1280x720 44.96 59.94 HDTV 720p
9. 1280x720 45.00 60.00 HDTV 720p
10. 1920x1080 31.25 50.00 HDTV 1080i
11. 1920x1080 33.75 60.00 HDTV 1080i
12. 1920x1080 33.72 59.94 HDTV 1080i
13. 1920x1080 56.250 50 HDTV 1080p
14. 1920x1080 67.5 60 HDTV 1080p
No.
Specification
Proposed Remarks
Resolution H-freq(kHz) V-freq(Hz) Pixel Clock(MHz)
1. 720*400 31.468 70.08 28.321 For only DOS mode
2. 640*480 31.469 59.94 25.17 VESA Input 848*480 60 Hz, 852*480 60 Hz
-> 640*480 60 Hz Display
3. 800*600 37.879 60.31 40.00 VESA
4. 1024*768 48.363 60.00 65.00 VESA(XGA)
5. 1280*768 47.78 59.87 79.5 WXGA
6. 1360*768 47.72 59.8 84.75 WXGA
7. 1920*1080 66.587 59.93 138.625 WUXGA FHD model
6. RGB Input (PC)
- 7 -
LGE Internal Use OnlyCopyright © 2011 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
7. HDMI Input
(1) DTV Mode
No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed Remark
1. 720*400 31.468 70.08 28.321 HDCP
2. 640*480 31.469 59.94 25.17 VESA HDCP
3. 800*600 37.879 60.31 40.00 VESA HDCP
4. 1024*768 48.363 60.00 65.00 VESA(XGA) HDCP
5. 1360*768 47.72 59.8 84.75 WXGA HDCP
6. 1920*1080 67.5 60.00 138.625 WUXGA HDCP/FHD model
(2) PC Mode
No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed Remark
1. 720*480 31.469 /31.5 59.94 /60 27.00/27.03 SDTV 480P
2. 720*576 31.25 50 54 SDTV 576P
3. 1280*720 37.500 50 74.25 HDTV 720P
4. 1280*720 44.96 /45 59.94 /60 74.17/74.25 HDTV 720P
5. 1920*1080 33.72 /33.75 59.94 /60 74.17/74.25 HDTV 1080I
6. 1920*1080 28.125 50.00 74.25 HDTV 1080I
7. 1920*1080 26.97 /27 23.97 /24 74.17/74.25 HDTV 1080P
8. 1920*1080 33.716 /33.75 29.976 /30.00 74.25 HDTV 1080P
9. 1920*1080 56.250 50 148.5 HDTV 1080P
10. 1920*1080 67.43 /67.5 59.94 /60 148.35/148.50 HDTV 1080P
- 8 -
LGE Internal Use OnlyCopyright © 2011 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
ADJUSTMENT INSTRUCTION
1. Application Range
This specification sheet is applied to all of the LCD TV with
LD12B chassis.
2. Designation
(1) Because this is not a hot chassis, it is not necessary to use
an isolation transformer. However, the use of isolation
transformer will help protect test instrument.
(2) Adjustment must be done in the correct order.
(3) The adjustment must be performed in the circumstance of
25 ºC ± 5 ºC of temperature and 65 % ± 10 % of relative
humidity if there is no specific designation.
(4) The input voltage of the receiver must keep AC 100-240
V~, 50 / 60Hz.
(5) The receiver must be operated for about 5 minutes prior to
the adjustment when module is in the circumstance of over
15.
In case of keeping module is in the circumstance of 0 °C, it
should be placed in the circumstance of above 15 °C for 2
hours
In case of keeping module is in the circumstance of below 20 °C, it should be placed in the circumstance of above 15
°C for 3 hours.
[Caution]
When still image is displayed for a period of 20 minutes or
longer (especially where W/B scale is strong. Digital pattern
13ch and/or Cross hatch pattern 09ch), there can some
afterimage in the black level area.
3. Automatic Adjustment
3.1. MAC Address
(1) Equipment & Condition
- Play file: Serial.exe
- MAC Address edit
- Input Start / End MAC address
(2) Download method
1) Communication Prot connection
Connect: PCBA Jig-> RS-232C Port== PC-> RS-232C Port
2) MAC Address & CI+ key Download
- Set CI+ key path Directory at start Mac & CI Download
Program
- Com 1,2,3,4 and 115200(Baud rate)
- Port connection button click(1)
- Push the (2) MAC Address write.
- At success Download, check the OK(3)
- Start CI+ Download, Push the (4)
- Check the OK or NG.(5)
3.2. LAN
(1) Equipment & Condition
A Each other connection to LAN Port of IP Hub and Jig
(2) LAN inspection solution
A LAN Port connection with PCB
A Network setting at MENU Mode of TV
A setting automatic IP
A Setting state confirmation
-> If automatic setting is finished, you confirm IP and
MAC Address.
PCBA
PC(RS-232C)
RS-232C Po r t
- 9 -
LGE Internal Use OnlyCopyright © 2011 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
3.3. LAN PORT INSPECTION(PING TEST)
Connect SET -> LAN port == PC -> LAN Port
(1) Equipment setting
1) Play the LAN Port Test PROGRAM.
2) Input IP set up for an inspection to Test
Program.
*IP Number : 12.12.2.2
(2) LAN PORT inspection (PING TEST)
1) Play the LAN Port Test Program.
2) Connect each other LAN Port Jack.
3) Play Test (F9) button and confirm OK Message.
4) Remove LAN CABLE
3.4. Model name & serial number download
(1) Model name & Serial number D/L
A Press “Power on” key of service remote control.(Baud
rate : 115200 bps)
A Connect RS232 Signal Cable to RS-232 Jack.
A Write Serial number by use RS-232.
A Must check the serial number at Instart menu.
(2) Method & notice
A. Serial number D/L is using of scan equipment.
B. Setting of scan equipment operated by Manufacturing
Technology Group.
C. Serial number D/L must be conformed when it is produced
in production line, because serial number D/L is mandatory
by D-book 4.0
* Manual Download (Model Name and Serial Number)
If the TV set is downloaded by OTA or service man,
sometimes model name or serial number is initialized.(Not
always)
There is impossible to download by bar code scan, so It
need Manual download.
a. Press the ‘instart’ key of ADJ remote control.
b. Go to the menu ‘5.Model Number D/L’ like below photo.
c. Input the Factory model name(ex 42LD450-ZA) or Serial
number like photo.
d. Check the model name Instart menu -> Factory name
displayed (ex 32LV3700-ZA)
e. Check the Diagnostics (DTV country only) -> Buyer model
displayed (ex 32LV3700)
4. Manual Adjustment
4.1. EDID(The Extended Display Identification
Data)/DDC(Display Data Channel) download
(1) Overview
It is a VESA regulation. A PC or a MNT will display an
optimal resolution through information sharing without any
necessity of user input. It is a realization of “Plug and Play”.
(2) Equipment
- Adjust remote control
- Since embedded EDID data is used, EDID download JIG,
HDMI cable and D-sub cable are not need.
(3)Download method
1) Press Adj. key on the Adj. R/C, then select “12.EDID
D/L”, By pressing Enter key, enter EDID D/L menu.
2) Select [Start] button by pressing Enter key, HDMI1/
HDMI2/ HDMI3/ RGB are Writing and display OK or NG.
(4) EDID DATA
A HDMI
SET PC
0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C0x0D 0x0E 0x0F
0x00 00 FF FF FF FF FF FF 00 1E 6D
ⓐⓑ
0x01 ⓒ 01 03 80 10 09 78 0A EE 91 A3 54 4C 99 26
0x02 0F 50 54 A1 08 00 71 40 81 C0 81 00 81 80 95 00
0x03 90 40 A9 C0 B3 00 02 3A 80 18 71 38 2D 40 58 2C
0x04 45 00 A0 5A 00 00 00 1E 66 21 50 B0 51 00 1B 30
0x05 40 70 36 00 A0 5A 00 00 00 1E 00 00 00 FD 00 39
0x06 3F 1F 52 10 00 0A 20 20 20 20 20 20 ⓓ
0x07 ⓓ 01 ⓔ1
0x00 02 03 26 F1 4E 10 1F 84 13 05 14 03 02 12 20 21
0x01 22 15 01 26 15 07 50 09 57 07 67 ⓕ
0x02 ⓕ E3 05 03 01 01 1D 80 18 71 1C 16 20 58 2C
0x03 25 00 A0 5A 00 00 00 9E 01 1D 00 80 51 D0 1A 20
0x04 6E 88 55 00 A0 5A 00 00 00 1A 02 3A 80 18 71 38
0x05 2D 40 58 2C 45 00 A0 5A 00 00 00 1E 66 21 50 B0
0x06 51 00 1B 30 40 70 36 00 A0 5A 00 00 00 1E 00 00
0x07 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ⓔ2
- 10 -
LGE Internal Use OnlyCopyright © 2011 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
A RGB
A Reference
- HDMI1 ~ HDMI3 / RGB
- In the data of EDID, bellows may be different by S/W or
Input mode.
ⓐ Product ID
ⓑ Serial No. : Controlled on product line
ⓒ Month, Year: Controlled on production line:
ex) Monthly : ‘01’ -> ‘01’
Year : ‘2010’ -> ‘14’
ⓓ Model Name(Hex):
ⓔ Checksum: Changeable by total EDID data.
ⓕ Vendor Specific(HDMI)
4.2. White Balance Adjustment
4.2.1. Overview
(1) W/B adj. Objective & How-it-works
(2) Objective: To reduce each Panel’s W/B deviation
(3) How-it-works : When R/G/B gain in the OSD is at 192, it
means the panel is at its Full Dynamic Range. In order to
prevent saturation of Full Dynamic range and data, one of
R/G/B is fixed at 192, and the other two is lowered to find
the desired value.
(4) Adj. condition : normal temperature
1) Surrounding Temperature : 25 ºC ± 5 ºC
2) Warm-up time: About 5 Min
3) Surrounding Humidity : 20 % ~ 80 %
4.2.2 Equipment
1) Color Analyzer: CA-210 (LED Module : CH 14)
2) Adj. Computer(During auto adj., RS-232C protocol is
needed)
3) Adjust Remote control
4) Video Signal Generator MSPG-925F 720p/204-Gray
(Model:217, Pattern:49)
-> Only when internal pattern is not available
A Color Analyzer Matrix should be calibrated using CS-1000
4.2.3. Equipment connection MAP
4.2.4. Adj. Command (Protocol)
<Command Format>
- LEN: Number of Data Byte to be sent
- CMD: Command
- VAL: FOS Data value
- CS: Checksum of sent data
- A: Acknowledge
Ex) [Send: JA_00_DD] / [Ack: A_00_okDDX]
A RS-232C Command used during auto-adj.
Ex) wb 00 00 -> Begin white balance auto-adj.
wb 00 10 -> Gain adj.
ja 00 ff -> Adj. data
jb 00 c0
...
...
wb 00 1f -> Gain adj. completed
*(wb 00 20(Start), wb 00 2f(completed)) -> Off-set adj.
wb 00 ff -> End white balance auto-adj.
0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C0x0D 0x0E 0x0F
0x00 00 FF FF FF FF FF FF 00 1E 6D ⓐⓑ
0x01 ⓒ 01 03 68 10 09 78 0A EE 91 A3 54 4C 99 26
0x02 0F 50 54 A1 08 00 71 4F 01 01 01 01 01 01 95 00
0x03 90 40 A9 C0 B3 00 02 3A 80 18 71 38 2D 40 58 2C
0x04 45 00 A0 5A 00 00 00 1E 66 21 50 B0 51 00 1B 30
0x05 40 70 36 00 A0 5A 00 00 00 1E 00 00 00 FD 00 3A
0x06 3E 1E 53 10 00 0A 20 20 20 20 20 20 ⓓ
0x07 ⓓ 01 ⓔ3
Model Name HEX EDID Table DDC Function
ALL 0001 0100 Analog
0001 0100 Digital
MODEL MODEL NAME(HEX)
all 00 00 00 FC 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20
INPUT MODEL NAME(HEX)
HDMI1 67 03 0C 00 10 00 B8 2D
HDMI2 67 03 0C 00 20 00 B8 2D
HDMI3 67 03 0C 00 30 00 B8 2D
RGB 67 03 0C 00 40 00 B8 2D
INPUT ⓔ1 ⓔ2 ⓔ3
HDMI1 7F D9 X
HDMI2 7F C9 X
HDMI3 7F B9 X
RGB X X 46
Color Analyzer
Comp uter
Pattern Generator
RS- 232C
RS-232C
RS-232C
Probe
Signal Source
* If TV internal pattern is used, not needed
LEN CMD VAL
CS
RS-232C COMMAND Explanation
[CMD ID DATA]
wb 00 00 Begin White Balance adj.
wb 00 10 Gain adj.(internal white pattern)
wb 00 1f Gain adj. completed
wb 00 20 Offset adj.(internal white pattern)
wb 00 2f Offset adj. completed
wb 00 ff End White Balance adj.(Internal pattern disappears)
- 11 -
LGE Internal Use OnlyCopyright © 2011 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
A Adj. Map
A 3 Command White Balance Adj. Map
A Infrared Sensor Adj. Map
4.2.5. Adj. method
(1) Auto adj. method
1) Set TV in adj. mode using POWER ON key.
2) Zero calibrate probe then place it on the center of the
Display.
3) Connect Cable (RS-232C)
4) Select mode in adj. Program and begin adjustment.
5) When adj. is complete (OK Sing), check adj. status pre
mode. (Warm, Medium, Cool)
6) Remove probe and RS-232C cable to complete adj.
A W/B Adj. must begin as start command “wb 00 00” , and
finish as end command “wb 00 ff”, and Adj. offset if need.
(2) Manual adj. method
1) Set TV in Adj. mode using POWER ON
2) Zero Calibrate the probe of Color Analyzer, then place it
on the center of LCD module within 10cm of the surface.
3) Press ADJ key -> EZ adjust using adj. R/C -> 9.WhiteBalance then press the cursor to the right (KEY
G).
(When KEY(G) is pressed 216 Gray internal pattern will
be displayed)
4) One of R Gain / G Gain / B Gain should be fixed at 192,
and the rest will be lowered to meet the desired value.
5) Adj. is performed in COOL, MEDIUM, WARM 3 modes
of color temperature.
A If internal pattern is not available, use RF input. In EZ
Adj. menu 9.White Balance, you can select one of 2 Test
-pattern: ON, OFF. Default is inner(ON). By selecting
OFF, you can adjust using RF signal in 216 gray pattern.
A Adj. condition and cautionary items
1) Lighting condition in surrounding area
Surrounding lighting should be lower 10 lux. Try to
isolate adj. area into dark surrounding.
2) Probe location
: Color Analyzer (CA-210) probe should be within
10cm and perpendicular of the module surface (80°~
100°)
3) Aging time
- After Aging Start, Keep the Power ON status during
5 Minutes.
- In case of LCD, Back-light on should be checked
using no signal or Full-white pattern.
4.2.6. Reference (White Balance Adj. coordinate
and temperature)
A Luminance : 204 Gray
A Standard color coordinate and temperature using CS-1000
(over 26 inch)
A Standard color coordinate and temperature using CA-
210(CH 14)
ITEM Command Data Range(Hex.) Default(Decimal)
Cmd 1 Cmd 2 Min Max
Cool R-Gain j g 00 C0
G-Gain j h 00 C0
B-Gain j i 00 C0
R-Cut
G-Cut
B-Cut
Medium R-Gain j a 00 C0
G-Gain j b 00 C0
B-Gain j c 00 C0
R-Cut
G-Cut
B-Cut
Warm R-Gain j d 00 C0
G-Gain j e 00 C0
B-Gain j f 00 C0
R-Cut
G-Cut
Command SetID R Gain(HEX) G Gain(HEX) B Gain(HEX)
(lower case ASCII)
CMD1 CMD2 MIN MAX MIN MAX MIN MAX
Cool j j 00 00 C0 00 C0 00 C0
Medium j k 00 00 C0 00 C0 00 C0
Warm j l 00 00 C0 00 C0 00 C0
Command R Gain(HEX) G Gain(HEX) B Gain(HEX)
(lower case ASCII)
CMD1 CMD2 MIN MAX MIN MAX MIN MAX
Cool 1 C 00 C0 00 C0 00 C0
Medium 1 D 00 C0 00 C0 00 C0
Warm 1 E 00 C0 00 C0 00 C0
Mode Color Coordination Temp ∆UV
xy
COOL 0.269 0.273 13000 K 0.0000
MEDIUM 0.285 0.293 9300 K 0.0000
WARM 0.313 0.329 6500 K 0.0000
Mode Color Coordination Temp ∆UV
xy
COOL 0.269 ± 0.002 0.273 ± 0.002 13000 K 0.0000
MEDIUM 0.285 ± 0.002 0.293 ± 0.002 9300 K 0.0000
WARM 0.313 ± 0.002 0.329 ± 0.002 6500 K 0.0000
- 12 -
LGE Internal Use OnlyCopyright © 2011 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
4.2.7. Edge LED White balance table
A IOP & Edge LED module change color coordinate because
of aging time.
A apply under the color coordinate table, for compensated
aging time.
- EDGE LED(LV3700)
4.3. EYE-Q function check
Step 1) Turn on TV
Step 2) Press EYE key of Adj. R/C
Step 3) Cover the Eye Q II sensor on the front of the using
your hand and wait for 6 seconds
Step 4) Confirm that R/G/B value is lower than 10 of the “Raw
Data (Sensor data, Back light)”. If after 6 seconds,
R/G/B value is not lower than 10, replace Eye Q II
sensor.
Step 5) Remove your hand from the Eye Q II sensor and wait
for 6 seconds.
Step 6) Confirm that “ok” pop up. If change is not seen,
replace Eye Q II sensor.
4.4. Option selection per country
(1) Overview
- Option selection is only done for models in Non-EU.
- Applied model: LD12B Chassis applied EU model.
(2) Method
1) Press ADJ key on the Adj. Remote Control, then select
Country Group Menu.
2) Depending on destination, select Country Group Code
04 or Country Group EU then on the lower Country
option, select US, CA, MX. Selection is done using +, or
GF KEY.
5. Tool Option selection
- Method : Press Adj. key on the Adj. Remote Control, then
select Tool option.
6. Ship-out mode check(In-stop)
After final inspection, press IN-STOP key of the Adj. R/C and
check that the unit goes to Stand-by mode.
7. GND and Internal Pressure check
7.1. Method
1) GND & Internal Pressure auto-check preparation
- Check that Power Cord is fully inserted to the SET.
(If loose, re-insert)
2) Perform GND & Internal Pressure auto-check
- Unit fully inserted Power cord, Antenna cable and A/V
arrive to the auto-check process.
- Connect D-terminal to AV JACK TESTER
- Auto CONTROLLER(GWS103-4) ON
- Perform GND TEST
- If NG, Buzzer will sound to inform the operator.
- If OK, changeover to I/P check automatically.
(Remove CORD, A/V form AV JACK BOX)
- Perform I/P test
- If NG, Buzzer will sound to inform the operator.
- If OK, Good lamp will lit up and the stopper will allow the
pallet to move on to next process.
7.2. Checkpoint
• TEST voltage
- GND: 1.5 KV/min at 100 mA
- SIGNAL: 3 KV/min at 100 mA
• TEST time: 1 second
• TEST POINT
- GND TEST = POWER CORD GND & SIGNAL CABLE
METAL GND
- Internal Pressure TEST = POWER CORD GND & LIVE &
NEUTRAL
• LEAKAGE CURRENT: At 0.5 mArms
GP2 Aging Time Cool Medium Warm
(Min.) X Y X Y X Y
269 273 285 293 313 329
1 0-2 280 291 296 311 319 340
2 3-5 278 288 294 308 317 338
3 6-9 276 285 292 305 315 335
4 10-15 274 282 290 302 313 332
5 20-35 273 279 289 299 312 329
6 36-49 270 276 287 296 310 326
7 50-79 269 273 286 293 308 323
8 Over 80 269 273 285 293 308 323
- 13 -
LGE Internal Use OnlyCopyright © 2011 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
8. USB S/W download(option, Service only)
1) Put the USB Stick to the USB socket
2) Automatically detecting update file in USB Stick
- If your downloaded program version in USB Stick is Low,
it didn’t work. But your downloaded version is High, USB
data is automatically detecting
3) Show the message “Copying files from memory”
4) Updating is starting.
5) Updating Completed, The TV will restart automatically
6) If your TV is turned on, check your updated version and
Tool option. (explain the Tool option, next stage)
* If downloading version is more high than your TV have,
TV can lost all channel data. In this case, you have to
channel recover. if all channel data is cleared, you didn’t
have a DTV/ATV test on production line.
* After downloading, have to adjust TOOL OPTION again.
1) Push "IN-START" key in service remote control.
2) Select "Tool Option 1" and Push “OK” button.
3) Push in the number. (Each model has their number.)
- 14 -
LGE Internal Use OnlyCopyright © 2011 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
BLOCK DIAGRAM
- 15 -
LGE Internal Use OnlyCopyright LG Electronics. Inc. All rights reserved.
Only for training and service purposes
300
200
LV1
400
540
530
521
900
910
800
710
120
511
510
A2
A21
A10
310
320
A5
* Set + Stand
* Stand Base + Body
EXPLODED VIEW
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These
parts are identified by in the Schematic Diagram and EXPLODED VIEW.
It is essential that these special safety parts should be replaced with the same components as
recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.
IMPORTANT SAFETY NOTICE
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
NAND_DATA[0]
NAND_DATA[1]
CI_ADDR[12]
NAND_DATA[2]
CI_ADDR[2]
NAND_DATA[1]
NAND_DATA[3]
CI_ADDR[7]
CI_ADDR[13]
CI_ADDR[14]
NAND_DATA[4]
NAND_DATA[2]
NAND_DATA[3]
NAND_DATA[7]
NAND_DATA[5]
CI_ADDR[8]
NAND_DATA[7]
NAND_DATA[0]
NAND_DATA[6]
CI_ADDR[4]
CI_ADDR[9]
NAND_DATA[4]
CI_ADDR[3]
NAND_DATA[6]
NAND_DATA[5]
CI_ADDR[10]
CI_ADDR[11]
CI_ADDR[5]
CI_ADDR[6]
R185 0
TXA0N
SOC_RESET
TXBCLKP
R151
0
16Gbit
R147
1K
JTAG
TXD0P
R170
10K
SDA2_3.3V
HDMI_ARC
R172
4.7K
OPT
TXD1P
C103
0.1uF
54MHz_XTAL_P
R183
10K
C101
0.1uF
TXA1P
DTV/MNT_V_OUT
TXC0P
TXC1P
R180
10K
TXDCLKN
TXA3N
R115
10K
R132 4.7K
R120
10K
SCL0_3.3V
TXACLKN
+3.3V_Normal
R116
10K
OPT
NAND_DATA[6]
+3.3V_Normal
HDMI_CLK+
R118
10K
R150
1K
JTAG
NAND_WEb
+3.3V_Normal
P101
TJC2508-4A
1
VCC
2
SCL
3
SDA
4
GND
TXD2P
NAND_DATA[5]
C106
4.7uF
CI_ADDR[8]
SC_ID
JTAG_RESET
NAND_CEb2
+3.3V_Normal
R145 22
OPT
R157
10K
OPT
CI_ADDR[12]
R169
0
CI_ADDR[7]
C112 0.1uF
TXB4P
R107 2.7K
C107
33pF
50V
DVB_S
TXD1N
NAND_CEb
NAND_RBb
R101
4.7K
R124
1K
OPT
C119
0.1uF
16V
NAND_CLE
TXB2N
+3.3V_Normal
TXD4P
5V_HDMI_2
NAND_CEb2
C104 10uF
10V
TXA1N
TXB3N
BSS83
Q101
SBD
G
NAND_DATA[3]
HDMI_CLK-
R176
10K
SDA0_3.3V
JTAG_RESET
R111
10K
OPT
R191 33
TXD3P
TXB0P
R154
10K
OPT
BCM_RX
HDMI_RX2+
TXC2P
R103
4.7K
OPT
+3.3V_Normal
TXD2N
TXCCLKP
C113
10pF
BCM_CRYSTAL_10pF
C102
4700pF
R198
10K
C111 0.01uF
NAND_ALE
TXBCLKN
NAND_DATA[0-7]
TXCCLKN
R179
10K
OPT
HDMI_RX1+
R117
10K
OPT
R135
33
C108
33pF
50V
DVB_S
R177
10K
FLASH_WP
TXA4N
R165
10K
R195
4.7K
IC103
M24M01-HRMN6TP
3
E2
2
E1
4
VSS
1
NC
5
SDA
6
SCL
7
WP
8
VCC
NAND_DATA[7]
R173
4.7K
TXB4N
R190 33
NAND_DATA[0-7]
NAND_WEb
R196
10K
NAND_CEb
R108 10K
CI_ADDR[4]
+3.3V_Normal
NAND_REb
R156
1K
JTAG
C114
10pF
BCM_CRYSTAL_10pF
/CI_CE1
R155
10K
A_DIM
R153
1K
JTAG
TXA3P
HDMI_RX1-
NAND_DATA[0]
5V_HDMI_1
R194
2.7K
R127
10K
OPT
NAND_CLE
R125
1K
R178
10K
OPT
C105
2.2uF
10V
CI_ADDR[13]
C109
33pF
50V
54MHz_XTAL_N
R159
1K
JTAG
5V_HDMI_4
R128
10K
/PCM_WAIT
+3.3V_Normal
HDMI_RX0-
CI_ADDR[3]
BCM_TX
C110
33pF
50V
TXB1P
+3.3V_Normal
R184
10K
OPT
NAND_ALE
R144 22
OPT
TXA0P
R122
10K
SCL2_3.3V
NAND_DATA[1]
+3.3V_Normal
R106
3K
R119
10K
OPT
TXC3N
R175
10K
OPT
SCL3_3.3V
HDMI_RX0+
R123
10K
OPT
R167
10K
OPT
CI_ADDR[2]
R130
2K
OPT
R110
1.5K
R113
10K
R193
10K
R181
10K
OPT
R112
10K
TXACLKP
R148
0
16Gbit
TXB3P
R182
10K
TXC4N
R163
1K
JTAG
+3.3V_Normal
LNB_INT
R114
10K
OPT
P102
12505WS-10A00
JTAG
1
/TRST
2
TDI
3
TDO
4
TMS
5
TCK
6
/RST
7
DINT
8
VIO
9
GND
10
GND
11
GND
R140
560
1%
R158
10K
R162
1K
JTAG
TXA2P
TXA2N
NAND_RBb
NAND_DATA[4]
R136 33
R149 0
16Gbit
R143 22
OPT
TXC4P
R186 0
BSS83
Q102
SBD
G
NAND_DATA[2]
R139 0
JTAG
TXB1N
CI_ADDR[11]
CI_ADDR[9]
5V_HDMI_3
+3.3V_Normal
R166
1K
JTAG
RGB_DDC_SCL
+3.3V_Normal
TXD4N
TXC1N
54MHz_XTAL_P
TXDCLKP
R171
10K
OPT
TXC2N
TXC0N
R160
10K
OPT
TXB0N
NAND_REb
TXC3P
CI_ADDR[6]
R168
10K
PCM_5V_CTL
R189
1M
OPT
+3.3V_Normal
R141 4.7K
TXD0N
54MHz_XTAL_N
R192
10K
OPT
R146 10K
C118
0.1uF
16V
+3.3V_Normal
+3.3V_Normal
/CI_CE2
TXA4P
R164
10K
OPT
+3.3V_Normal
R161
10K
R142 22
OPT
R188
10K
R187
10K
OPT
SDA3_3.3V
NAND_CLE
R109
1.5K
FLASH_WP
TXB2P
+3.3V_Normal
TXD3N
+3.3V_Normal
CI_ADDR[2-14]
HDMI_RX2-
R174
4.7K
OPT
RGB_DDC_SDA
NAND_ALE
R126
1.2K
R129
1.2K
R121
1.2K
R131
1.2K
R199 22
R197 22
R105
4.7K
R104
4.7K
IC102
TC58DVG3S0ETA00
NAND_8Gbit
26
NC_17
27
NC_18
28
NC_19
29
I/O1
30
I/O2
31
I/O3
32
I/O4
33
NC_20
34
NC_21
35
NC_22
36
VSS_2
37
VCC_2
38
NC_23
39
PSL
40
NC_24
41
I/O5
42
I/O6
43
I/O7
44
I/O8
45
NC_25
46
NC_26
47
NC_27
48
NC_28
17
ALE
3
NC_3
6
NC_6
16
CLE
15
NC_10
14
NC_9
13
VSS_1
12
VCC_1
11
NC_8
10
NC_7
9
CE
8
RE
7
RY/BY
4
NC_4
5
NC_5
25
NC_16
24
NC_15
23
NC_14
2
NC_2
22
NC_13
21
NC_12
1
NC_1
20
NC_11
19
WP
18
WE
IC102-*1
TH58DVG4S0ETA20
DEV_NAND_16Gbit
26
NC_15
27
NC_16
28
NC_17
29
I/O1
30
I/O2
31
I/O3
32
I/O4
33
NC_18
34
NC_19
35
NC_20
36
VSS_2
37
VCC_2
38
NC_21
39
PSL
40
NC_22
41
I/O5
42
I/O6
43
I/O7
44
I/O8
45
NC_23
46
NC_24
47
NC_25
48
NC_26
17
ALE
3
NC_3
6
RY/BY2
16
CLE
15
NC_8
14
NC_7
13
VSS_1
12
VCC_1
11
NC_6
10
CE2
9
CE1
8
RE
7
RY/BY1
4
NC_4
5
NC_5
25
NC_14
24
NC_13
23
NC_12
2
NC_2
22
NC_11
21
NC_10
1
NC_1
20
NC_9
19
WP
18
WE
LGE35230(BCM35230KFSBG)
IC101
NON_BCM_CAP
HDMI0_CLKN
B5
HDMI0_CLKP
C5
HDMI0_D0N
A4
HDMI0_D0P
B4
HDMI0_D1N
A3
HDMI0_D1P
B3
HDMI0_D2N
A2
HDMI0_D2P
B2
CEC
W2
DDC0_SCL
V4
DDC0_SDA
W4
HDMI0_HTPLG_IN
V3
HDMI0_HTPLG_OUT
V2
HDMI0_ARC
D13
HDMI0_RESREF
E6
TXOUT0_L0N
AE27
TXOUT0_L0P
AE28
TXOUT0_L1N
AF27
TXOUT0_L1P
AF28
TXOUT0_L2N
AG27
TXOUT0_L2P
AG28
TXCLK_LN
AE26
TXCLK_LP
AF26
TXOUT0_L3N
AH27
TXOUT0_L3P
AG26
TXOUT0_L4N
AF25
TXOUT0_L4P
AE25
TXOUT0_U0N
AH26
TXOUT0_U0P
AG25
TXOUT0_U1N
AE24
TXOUT0_U1P
AD24
TXOUT0_U2N
AH25
TXOUT0_U2P
AF24
TXCLK_UN
AE23
TXCLK_UP
AD23
TXOUT0_U3N
AG24
TXOUT0_U3P
AF23
TXOUT0_U4N
AC22
TXOUT0_U4P
AD22
TXOUT1_L0N
AG23
TXOUT1_L0P
AH23
TXOUT1_L1N
AE22
TXOUT1_L1P
AE21
TXOUT1_L2N
AF22
TXOUT1_L2P
AH22
TXCLK1_LN
AG22
TXCLK1_LP
AF21
TXOUT1_L3N
AG21
TXOUT1_L3P
AF20
TXOUT1_L4N
AD21
TXOUT1_L4P
AC21
TXOUT1_U0N
AG20
TXOUT1_U0P
AH20
TXOUT1_U1N
AD19
TXOUT1_U1P
AE19
TXOUT1_U2N
AF19
TXOUT1_U2P
AH19
TXCLK1_UN
AE18
TXCLK1_UP
AD18
TXOUT1_U3N
AG19
TXOUT1_U3P
AF18
TXOUT1_U4N
AG18
TXOUT1_U4P
AF17
LT0VCAL_MONITOR
AC18
GPIO_BL_ON
AH16
BL_PWM/GPIO
AG16
LGE35230(BCM35230KFSBG)
IC101
NON_BCM_CAP
TVM_XTALIN
AG6
TVM_XTALOUT
AF6
IRRXDA
V5
FP_IN0
AB4
FP_IN1
Y4
SPARE_ADC1
AA4
SPARE_ADC2
Y5
FS_IN1
AB2
FS_IN2
AB5
VGA_SDA
U3
VGA_SCL
U2
RDA
Y2
TDA
Y1
BSCDATAA
AA3
BSCCLKA
AA2
RDB/GPIO
H3
TDB/GPIO
H2
BSC_S_SCL
H4
BSC_S_SDA
H5
NMIB
F25
POWER_CTRL
W5
AON_HSYNC
U5
AON_VSYNC
U4
AON_GPIO_36
W3
AON_GPIO_37
W1
AON_RESETOUTB
AB6
TVM_BYPASS
Y6
RESETB
Y3
RESETOUTB
G24
TMODE
J6
TESTEN
W6
VDAC_VREG
F7
VDAC_RBIAS
E7
FAD_7
AB1
FAD_6
AB3
FAD_5
AC1
FAD_4
AC2
FAD_3
AC3
FAD_2
AD2
FAD_1
AD3
FAD_0
AE2
FALE
AG1
FCEB_0
AF1
FCEB_1
AC5
FCEB_2
AE6
FCEB_3
AG5
NFWPB
AF3
FWE
AG2
FRD
AE3
FRDYB
AA5
FA_0
AF2
FA_1
AE1
FA_2
AC4
FA_3
AD5
FA_4
AD4
FA_5
AE4
FA_6
AE5
FA_7
AD6
FA_8
AH3
FA_9
AF4
FA_10
AH4
FA_11
AG4
FA_12
AF5
FA_13
AG3
FA_14
AH2
FA_15
AH5
TRSTB
AD15
TDI/GPIO
AF14
TDO
AH14
TMS/GPIO
AD14
TCK/GPIO
AG14
DINT/GPIO
AC16
AVS_VFB
AH7
AVS_VSENSE
AG7
AVS_RESETB
AD7
AVS_NDRIVE_1
AF7
AVS_PDRIVE_1
AH8
VDAC_1
C6
VDAC_2
D7
X101
54MHz
EAW58812611
SUNNY ELECTRONICS CORPORATION
CRYSTAL_BCM_Sunny
4
GND_21X-TAL_1
2
GND_1
3
X-TAL_2
X101-*2
54MHz
CRYSTAL_BCM_Lihom
EAW60763703
LIHOM CO., LTD.
4
GND_2
1
X-TAL_1
2
GND_13X-TAL_2
X101-*3
54MHz
CRYSTAL_BCM_KDS
DAISHINKU CORPORATION.
EAW58239604
4
GND_2
1
X-TAL_1
2
GND_13X-TAL_2
C113-*1
12pF
BCM_CRYSTAL_12pF
C114-*1
12pF
BCM_CRYSTAL_12pF
MAIN & NAND FLASH
BBS CONNECT
Write Protection
- High : Normal Operation
- Low : Write Protection
NAND_DATA[0]:
0: System is LITTLE endian (O)
1: System is BIG endian
CI_ADDR[7]:
0: Disable EDID automatic Downloading from Flash (O)
1: Enable EDID automatic Downloading from Flash
NAND_DATA[6] :
0: Disable OSC clock output on chip Pin (O)
1: Enable OSC clock output on chip pin.
CI_ADDR[6]:
0: Host MIPS run at 500 MHz (O)
1: Host MIPS run at 250 MHz
NAND_CLE:
0: Differential Oscillators TVM not bypassed (O)
1: Differential Oscillators TVM bypassed
NAND_DATA[4]:
0: 27MHz TVM Crystal Frequency
1: 54MHz TVM Crystal Frequency (O)
Write Protection
- Low : Normal Operation
- High : Write Protection
000 = ECC disabled
001 = ECC 1-bit repair
010 = ECC 4-bit BCH (O)
011 = ECC 8-bit BCH, 27 byte spare
100 = ECC 12-bit BCH, 27 byte spare
101 = ECC 8-bit BCH, 16 byte spare
110, 111 = Reservedd
NAND ECC (FA3, FA2, FALE)
BCM REFRENCE is 562ohm
A8’h
FOR HDMI STANDARD
APPLY ONLY WHEN CONNECT TO PULL-UP GPIO
BCM35230
1
CI_ADDR[9],CI_ADDR[11],CI_ADDR[12],CI_ADDR[13]
TVM Crystal oscillator bias/gain control
0000: 210uA
0001: 390uA
0010: 570uA
0011: 730uA
0100: 890uA (O)
0111: 1290uA
1000: 1416uA
1111: 2196uA
0101, 0110, 1001, 1010, 1011, 1100, 1101, 1110: Reserved
CI_ADDR[8]:
0: RESETOUTb (in On/Off only) stay asserted until software releases them.
1: Fix amount of delay for de-assertion on RESETOUTb (in On/IOff only)
at end of RESETb pulse (O)
NAND_DATA[3]:
0: MIPS will boot from external flash (O)
1: MIPS will boot from ROM
NAND_DATA[5]:
0: FLASH MODE (O)
1: BSC_SLAVE(BBS) MODE
Boot ROM Device Select - (FA4,FAD7,FAD2,FAD1)
0000: ST Micro M25P or compatible Serial Flash
0010: 8-bit 512Mbit 512B page SLC NAND Flash devices
0100: 8-bit 128, 256Mbit 512B page SLC NAND Flash devices
0110: 8-bit 1Gbit 2KB page SLC NAND Flash devices
1000: 8-bit 2Gbit, 4Gbit, 8Gbit 2KB page SLC NAND Flash devices
1010: 8-bit 16Gbit, 32Gbit 4KB page SLC NAND Flash devices (O)
0001: 8-bit 8/16/32Gbit 2KB page MLC NAND Flash devices
0011: 8-bit 16/32Gbit 4KB page MLC NAND Flash devices
0101: 8-bit 32Gbit 8KB page MLC NAND Flash devices
0111: 3B dual IO Serial Flash
1001: BB dual IO Serial Flash
1011: fast Serail Flash > 50Mhz
1100: OneNAND Flash (always 16-bit)
1110: Reserved
1101, 1111: Reserved
NAND FLASH MEMORY 8Gbit
57
Strap Setting
54MHz X-TAL
NVRAM
IC102 1ST : EAN60999801 2ND : T-TC58DVG3S0ETA00
DUAL COMPONENT
IC102-*1
DVB_S Option: apply EU Satellite model
2010.09.18
16Gbit
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
FE_TS_DATA[2]
PCM_MDI[7]
PCM_MDI[5]
PCM_MDI[6]
FE_TS_DATA[7]
PCM_MDI[4]
FE_TS_DATA[4]
PCM_TS_DATA[5]
FE_TS_DATA[5]
PCM_MDI[2]
PCM_MDI[1]
PCM_MDI[0]
FE_TS_DATA[3]
FE_TS_DATA[6]
FE_TS_DATA[0]
PCM_TS_DATA[1]
PCM_TS_DATA[3]
PCM_TS_DATA[0]
FE_TS_DATA[1]
PCM_TS_DATA[2]
PCM_TS_DATA[7]
PCM_TS_DATA[6]
PCM_MDI[3]
PCM_TS_DATA[4]
CHBO_TS_CLK
PCM_TS_VAL
COMP1_DET
PLL_MIPS_AVDD
L213
BLM18PG121SN1D
ADAC_AVDD25
C231
33pF
50V
NON_NTP
+0.9V_CORE
C227
33pF
50V
NON_NTP
R264
1K
OPT
+2.5V_BCM35230
PCM_TS_SYNC
EPHY_VDD25
SIDE_USB_CTL2
R266
1K
NO_S_TUNNER
C281
0.1uF
MODEL_OPT_2
C290
0.1uF
VAFE2_DVDD
SDA1_3.3V
R241
100
PLL_VAFE_AVDD25
TU_TS_SYNC
C220
0.1uF
C280
0.1uF
C234
0.1uF
3D_GPIO_1
SCL1_3.3V
C257
0.1uF
+0.9V_CORE
L216
BLM18PG121SN1D
MODEL_OPT_2
MODEL_OPT_3
L209
BLM18PG121SN1D
C247
22uF
/PCM_IRQA
R227 22
RF_BOOSTER_CTL
AADC_AVDD25
+0.9V_CORE
R208 0
F/NIM_EU_CN
+0.9V_CORE
+0.9V_CORE
+0.9V_CORE
+0.9V_CORE
C299
0.1uF
R267
1K
NO_PHM
R253
1K
OLED
+0.9V_CORE
PCM_MISTRT
ADAC_AVDD25
L/DIM0_MOSI
R251
1K
BCM_FRC/URSA5
C242
0.1uF
SIDE_USB_OCD2
R226 22
R285 22
PWM_DIM
C278
0.1uF
C236
0.1uF
+2.5V_BCM35230
USB_AVDD33
+2.5V_BCM35230
+3.3V_Normal
HDMI_AVDD33
+1.5V_DDR
R281 22
C273
0.1uF
R218 22
MODEL_OPT_4
R204 0
F/NIM_EU_CN
TW9910_RESET
C213
0.1uF
R221 22
BCM_L/DIM
SC_DET/COMP2_DET
R254
1K
R203 0
F/NIM_EU_CN
R265
1K
NO_T2_TUNER
C272
0.01uF
IF_N
C211
0.1uF
+0.9V_CORE
R215 22
PCM_MIVAL_ERR
HDMI_AVDD33
C215
0.01uF
L/DIM0_VS
MODEL_OPT_0
MODEL_OPT_7
R282 22
CHB_RESET
SIDE_USB_DM
HDMI_AVDD
R242
100
C276
0.01uF
OPT
C270
0.1uF
C201
100pF
OPT
R256
1K
S_TUNER
IF_AGC
CI_DET
+0.9V_CORE
R230 22
BCM_L/DIM
C269
0.1uF
+3.3V_Normal
PCM_TS_DATA[0-7]
C283
0.1uF
3D_GPIO_2
FE_TS_DATA[0-7]
L211
BLM18PG121SN1D
R262
1K
HD
C255
0.1uF
R255
1K
T2_TUNER
L204
BLM18PG121SN1D
SIDE_USB_OCD1
R261
1K
NO_FRC/FRC2
R240
2.7K
R225 0
OPT
PLL_MIPS_AVDD
VAFE2_VDD25
ERROR_OUT
EPHY_VDD25
L218
BLM18PG121SN1D
MODEL_OPT_7
L215
BLM18PG121SN1D
R283
22
VAFE3_DVDD
+3.3V_Normal
R211
6.04K
C297
0.1uF
PLL_VAFE_AVDD
DTV_ATV_SELECT
L207
BLM18PG121SN1D
R260
1K
NO_FRC/BCM_FRC
R207 0
F/NIM_EU_CN
+2.5V_BCM35230
SIDE_USB_CTL1
R286
10K
WIFI
R210
4.87K
1%
M_RFModule_RESET
USB_AVDD
EPHY_RDN
R205 0
F/NIM_EU_CN
CHBO_TS_SERIAL
C289
0.1uF
+2.5V_BCM35230
AV2_CVBS_DET
R220 22
3D_GPIO_0
+3.3V_Normal
L/DIM0_SCLK
C222
0.01uF
VAFE3_VDD25
RF_SWITCH_CTL_2
VAFE3_VDD25
+0.9V_CORE
R222 22
BCM_L/DIM
+3.3V_Normal
R206 0
F/NIM_EU_CN
L202
BLM18PG121SN1D
VDAC_AVDD33
PCM_TS_CLK
MODEL_OPT_1
+3.3V_Normal
R228 22
PLL_AUD_AVDD
+2.5V_BCM35230
C268
0.1uF
EPHY_TDP
R202
0
F/NIM_EU_CN
+2.5V_BCM35230
L212
BLM18PG121SN1D
MODEL_OPT_4
MODEL_OPT_3
C288
0.1uF
MODEL_OPT_6
EPHY_TDN
TS_VAL_ERR
C282
0.1uF
+1.5V_DDR
+3.3V_Normal
L214
BLM18PG121SN1D
PCM_MDI[0-7]
C274
22uF
R250
1K
FRC2/URSA5
R235
100
MODEL_OPT_1
M_REMOTE_RX
R223 22
R280
22
C258
0.1uF
FRC_RESET
L206
BLM18PG121SN1D
C298
0.1uF
DC_MREMOTE
USB_AVDD33
IF_P
L219
BLM18PG121SN1D
R263
1K
LCD
WIFI_DM
SIDE_USB_DP
C221
0.1uF
VDAC_AVDD33
MODEL_OPT_5
C229
0.1uF
C218
0.1uF
16V
MODEL_OPT_6
INSTANT_MODE
EPHY_RDP
PCM_RST
PLL_VAFE_AVDD25
L201
BLM18PG121SN1D
+3.3V_Normal
WIFI_DP
+0.9V_CORE
RF_SWITCH_CTL
R257
1K
PHM
CHBO_TS_SYNC
+2.5V_BCM35230
R201 0
OPT
+0.9V_CORE
C293
0.1uF
AADC_AVDD25
R284 22
L217
BLM18PG121SN1D
R214 22
+3.3V_Normal
C217
0.1uF
16V
C223
0.01uF
PLL_MAIN_AVDD
L210
BLM18PG121SN1D
R224 22
C284
22uF
PLL_MAIN_AVDD
C267
0.1uF
+3.3V_Normal
C216 0.01uF
PLL_VAFE_AVDD
MODEL_OPT_5
C275
0.1uF
OPT
CHBO_TS_VAL_ERR
VAFE2_DVDD
+2.5V_BCM35230
+3.3V_Normal
C292
22uF
R213 2K
USB_AVDD
L203
BLM18PG121SN1D
VAFE2_VDD25
+3.3V_Normal
C256
0.1uF
VAFE3_DVDD
DD_MREMOTE
R212
1K
Non_CHB
L205
BLM18PG121SN1D
PCM_MCLKI
MODEL_OPT_0
R252
1K
FHD
PLL_AUD_AVDD
+3.3V_Normal
C251
0.1uF
16V
HDMI_AVDD
TU_TS_CLK
DSUB_DET
R209 0
F/NIM_EU_CN
R216 22
C271
0.01uF
EPHY_ACTIVITY
EPHY_LINK
3D_SYNC
R233
1.2K
R234
1.2K
R231 100
URSA_RESET
R231-*1 0
FRC2_RESET
R232
4.7K
URSA_RESET
+3.3V_Normal
C203
10uF
10V
C205
10uF
10V
C248
10uF
10V
C249
10uF
10V
C253
10uF
10V
C259
10uF
10V
C261
10uF
10V
C262
10uF
C207
4.7uF
10V
C209
4.7uF
10V
C238
4.7uF
10V
C250
4.7uF
10V
C254
4.7uF
C252
4.7uF
10V
C260
4.7uF
C263
4.7uF
C264
4.7uF
C265
4.7uF
C266
4.7uF C277
4.7uF
C279
4.7uF
C285
4.7uF
C286
4.7uF
C287
4.7uF
C291
4.7uF
C294
4.7uF
C295
4.7uF
C296
4.7uF
C225
0.22uF
6.3V
LGE35230(BCM35230KFSBG)
IC101
NON_BCM_CAP
EPHY_VREF
F26
EPHY_RDAC
D26
EPHY_TDP
F27
EPHY_TDN
F28
EPHY_RDP
E27
EPHY_RDN
E26
USB_MONCDR
F5
USB_RREF
E5
USB_PORT1DN
C2
USB_PORT1DP
D1
USB_PWRFLT_1/GPIO
E1
USB_PWRON_1/GPIO
D2
USB_PORT2DN
B1
USB_PORT2DP
C1
USB_PWRFLT_2/GPIO
C3
USB_PWRON_2/GPIO
C4
TCLKA/GPIO
M4
TDATA_0/GPIO
L5
TDATA_1/GPIO
M5
TDATA_2/GPIO
L6
TDATA_3/GPIO
N3
TDATA_4/GPIO
N1
TDATA_5/GPIO
N2
TDATA_6/GPIO
M3
TDATA_7/GPIO
M2
TSTRTA/GPIO
L4
TVLDA/GPIO
N4
TCLKD/GPIO
K6
TDATD_0/GPIO
J4
TDATD_1/GPIO
K5
TDATD_2/GPIO
J2
TDATD_3/GPIO
J3
TDATD_4/GPIO
K2
TDATD_5/GPIO
K1
TDATD_6/GPIO
K3
TDATD_7/GPIO
L1
TSTRTD/GPIO
L3
TVLDD/GPIO
L2
MPEG_CLK/GPIO
P4
MPEG_D_0/GPIO
T2
MPEG_D_1/GPIO
R3
MPEG_D_2/GPIO
R2
MPEG_D_3/GPIO
P3
MPEG_D_4/GPIO
P2
MPEG_D_5/GPIO
P1
MPEG_D_6/GPIO
R6
MPEG_D_7/GPIO
N5
MPEG_SYNC/GPIO
T4
MPEG_DATA_EN/GPIO
P5
MCIF_RESET/GPIO
R4
MCIF_SCLK/GPIO
U1
MCIF_SCTL/GPIO
T3
MCIF_SDI/GPIO
T1
MCIF_SDO/GPIO
T5
VI_IFP0
C17
VI_IFM0
B17
VDDR_AGC
D15
AGC_SDM_2
B16
AGC_SDM_1
A16
GPIO_0
A15
GPIO_1
C16
GPIO_2
G28
GPIO_3
G26
PCI_VIO_0
W14
PCI_VIO_1
W15
PCI_VIO_2
W13
GPIO_4
J5
GPIO_5
R5
GPIO_6
V6
GPIO_7
H6
GPIO_70
AE15
GPIO_71
AF15
GPIO_72
AG15
GPIO_73
AF16
GPIO_74
AD16
GPIO_75
AE16
GPIO_76
AG17
GPIO_77
AH17
GPIO_78
AE17
GPIO_79
AD17
PCI_AD05
AB13
PCI_AD06
AC15
PCI_AD07
AB12
PCI_AD08
AB11
PCI_AD09/GPIO
AE14
PCI_AD10/GPIO
AG13
PCI_AD11/GPIO
AH13
PCI_AD12/GPIO
AF13
PCI_AD13/GPIO
AE13
PCI_AD14/GPIO
AD12
PCI_AD15/GPIO
AF12
PCI_AD16/GPIO
AG10
PCI_AD17/GPIO
AF10
PCI_AD18/GPIO
AE10
PCI_AD19/GPIO
AD10
PCI_AD20/GPIO
AE9
PCI_AD21/GPIO
AE8
PCI_AD22
AC10
PCI_AD23
AC11
PCI_AD24
AC8
PCI_AD25
AB8
PCI_CBE00
AC14
PCI_CBE01/GPIO
AG12
PCI_CBE02/GPIO
AH10
PCI_CBE03
AB7
PCI_DEVSELB/GPIO
AG11
PCI_FRAMEB/GPIO
AD11
PCI_IRDYB/GPIO
AE11
PCI_PAR/GPIO
AD13
PCI_PERRB/GPIO
AE12
PCI_REQ1B
AC12
PCI_SERRB/GPIO
AC13
PCI_STOPB/GPIO
AH11
PCI_TRDYB/GPIO
AF11
LGE35230(BCM35230KFSBG)
IC101
NON_BCM_CAP
VDDC_1
V12
VDDC_2
V7
VDDC_3
M10
VDDC_4
N10
VDDC_5
P10
VDDC_6
R10
VDDC_7
T10
VDDC_8
U10
VDDC_9
V10
VDDC_10
W10
VDDC_11
V13
VDDC_12
L11
VDDC_13
M11
VDDC_14
N11
VDDC_15
P11
VDDC_16
R11
VDDC_17
T11
VDDC_18
U11
VDDC_19
V11
VDDC_20
W11
VDDC_21
V14
VDDC_22
L18
VDDC_23
M18
VDDC_24
N18
VDDC_25
P18
VDDC_26
R18
VDDC_27
T18
VDDC_28
U18
VDDC_29
V18
VDDC_30
W18
VDDC_31
V15
VDDC_32
L19
VDDC_33
M19
VDDC_34
N19
VDDC_35
P19
VDDC_36
R19
VDDC_37
T19
VDDC_38
U19
VDDC_39
V19
VDDC_40
W19
VDDC_41
V16
VDDC_42
V17
POR_VDD
L10
VDDR1_1
L22
VDDR1_2
AA28
VDDR1_3
V28
VDDR1_4
R28
VDDR1_5
M28
VDDR1_6
J28
VDDR1_7
K23
VDDR1_8
M22
VDDR1_9
T22
VDDR1_10
T23
VDDR1_11
U22
VDDR1_12
Y22
DDR_LDO_VDDO
R22
VDDR3_1
G15
VDDR3_2
H22
VDDR3_3
G23
VDDR3_4
AB9
VDDR3_5
K7
VDDR3_6
AB15
VDDR3_7
L7
VDDR3_8
AB14
VDDR3_9
M7
VDDR3_10
N6
VDDR3_11
P6
AON_VDDC_1
AA6
AON_VDDC_2
AA7
AON_POR_VDD
Y7
AON_VDDR3
U7
AON_VDDR10_1
T7
AON_VDDR10_2
T6
VSS_1
K10
VSS_2
K11
VSS_3
K12
VSS_4
L12
VSS_5
M12
VSS_6
N12
VSS_7
P12
VSS_8
R12
VSS_9
T12
VSS_10
U12
VSS_11
W12
VSS_12
K13
VSS_13
L13
VSS_14
M13
VSS_15
N13
VSS_16
P13
VSS_17
R13
VSS_18
T13
VSS_19
U13
VSS_20
W16
VSS_21
K14
VSS_22
L14
VSS_23
M14
VSS_24
N14
VSS_25
P14
VSS_26
R14
VSS_27
T14
VSS_28
U14
VSS_29
K15
VSS_30
L15
VSS_31
M15
VSS_32
N15
VSS_33
P15
VSS_34
R15
VSS_35
T15
VSS_36
U15
VSS_37
K16
VSS_38
L16
VSS_39
M16
VSS_40
N16
VSS_41
P16
VSS_42
R16
VSS_43
T16
VSS_44
U16
VSS_45
K17
VSS_46
L17
VSS_47
M17
VSS_48
N17
VSS_49
P17
VSS_50
R17
VSS_51
T17
VSS_52
U17
VSS_53
W17
VSS_54
K18
VSS_55
K19
VSS_56
H7
VSS_57
G14
VSS_58
AB16
VSS_59
R7
VSS_60
M6
VSS_61
AB23
VSS_62
P7
VSS_63
W7
VSS_64
J7
VSS_65
N7
VSS_66
AB10
VSS_67
AC23
VSS_68
AC6
VSS_69
G19
VSS_70
AA22
VSS_71
J23
VSS_72
J22
VSS_73
K22
VSS_74
J25
VSS_75
N22
VSS_76
N23
VSS_77
M25
VSS_78
P22
VSS_79
R25
VSS_80
V22
VSS_81
W22
VSS_82
W23
VSS_83
V25
VSS_84
AA25
LGE35230(BCM35230KFSBG)
IC101
NON_BCM_CAP
AADC_AVDD25
F19
ADACA_AVDD25
D25
ADACC_AVDD25
D24
ADACD_AVDD25
E24
EPHY_BVDD25
F24
EPHY_AVDD25
E25
POR_VDD25
F8
HDMI0_AVDD
D5
HDMI0_AVDD33
D4
LT0VDD25_1
AE20
LT0VDD25_2
AD20
LT0VDD25_3
AC20
LT0VDD25_4
AB20
SPDIF_IN_AVDD25
D14
USB_AVDD
E4
USB_AVDD33
D3
VDAC_AVDD33
D6
VAFE2_DVDD
D18
VAFE2_AVDD25_1
E17
VAFE2_AVDD25_2
D16
VAFE2_DVDD25
D17
VAFE3_DVDD
D9
VAFE3_AVDD25_1
D8
VAFE3_AVDD25_2
E8
VAFE3_AVDD25_3
F9
VAFE3_DVDD25
E9
PLL_AUD_AVDD
G25
PLL_MAIN_AVDD
K4
PLL_MIPS_AVDD
AD25
PLL_VAFE_AVDD
D11
TVM_OSC_AVDD
AE7
AUX_AVDD33
U6
AADC_AVSS
F20
ADACA_AVSS
G22
ADACC_AVSS
G21
ADACD_AVSS
F22
EPHY_AVSS
F23
HDMI0_AVSS_1
F6
HDMI0_AVSS_2
G6
LT0VSS_1
AB22
LT0VSS_2
AB21
LT0VSS_3
AB19
LT0VSS_4
AC19
LT0VSS_5
AB18
LT0VSS_6
AB17
LT0VSS_7
AC17
SPDIF_IN_AVSS
F15
USB_AVSS_1
G7
USB_AVSS_2
G8
VDAC_AVSS
G9
VAFE2_VSS_1
G20
VAFE2_VSS_2
E18
VAFE2_VSS_3
G18
VAFE2_VSS_4
G17
VAFE2_VSS_5
F18
VAFE2_VSS_6
G16
VAFE2_VSS_7
F16
VAFE3_VSS_1
G13
VAFE3_VSS_2
G12
VAFE3_VSS_3
F12
VAFE3_VSS_4
G11
VAFE3_VSS_5
G10
VAFE3_VSS_6
F10
PLL_MIPS_AVSS
AD26
PLL_VAFE_AVDD25
D12
TVM_OSC_AVSS
AC7
R232-*1
4.7K
FRC2_RESET
NFM18PS105R0J
C233
6.3V
OUTIN
GND
NFM18PS105R0J
C244
6.3V
OUTIN
GND
NFM18PS105R0J
C204
6.3V
OUTIN
GND
R287
10K
WIFI
C202
390pF
50V
C206
390pF
50V
C208
390pF
50V
C210
390pF
50V
BCM_C0
C210-*1
220pF
50V
BCM_A0/B0
C212
390pF
50V
C214
390pF
50V
C224
1uF
25V
OPT
C226
0.1uF
16V
OPT
C232
4.7uF
10V
L220
MLG1005S22NJT
POWER 2.5V
MAIN POWER
closed to soc
CORE 0.9V
close to soc
50
BCM35230
POWER 3.3V
2
MODEL_OPT_2
LOW
MODEL OPTION
HIGH
HDFHD
LCDOLED
16001333
Support
DDR speed
MODEL_OPT_3
MODEL_OPT_4
MODEL_OPT_5
MODEL_OPT_6
MODEL_OPT_7 Enable Disable
Not Support
Not SupportSupport
MODEL_OPT_0
MODEL_OPT_1
00 11
1 100
NO_FRC
BCM
internal
FRC
LG FRC2
external
URSA5
T2 Tuner
S Tuner
PHM
use only for A0/B0 chip
Place as close as possible to the pad
Place as close as possible to the pad
Very close to R22 Ball
Place Cap
Place as close as possible to the pad
Very close to R22 Ball
Place Cap
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
DSUB_B+
C305 1uF 10V
INCM_VID_AV2
INCM_G
C307 1uF 10V
INCM_G
C330 0.1uF
INCM_AUD_AV2
R328 100
SC/COMP2_L_IN
R317
36
R327 100
C311 1uF 10V
R326 100
R324 0
C322 0.1uF
C335 0.1uF
INCM_SIF
SC_B/COMP2_Pb
HP_LOUT_P
SC_RE2INCM_AUD_PC
C319 0.1uF
C306 1uF 10V
AUD_SCK
INCM_B
DSUB_G+
C339
22pF
OPT
C302
33pF
50V
AV1_R_IN
INCM_VID_SC/COMP2
C320 0.1uF
SC/COMP2_R_IN
DSUB_VSYNC
TU_RESET_SUB
DSUB_HSYNC
R320
12K
OPT
C334 0.1uF
INCM_R
C328 0.1uF
R304
36
INCM_VID_COMP1
C338
22pF
OPT
INCM_TUNER
PC_R_IN
SDA3_3.3V
SCL3_3.3V
R303
36
SC_RE1
AUD_MASTER_CLK
C312 1uF 10V
AV2_CVBS_IN
C303 0.1uF
R329 100
C336 0.1uF
INCM_AUD_PC
C324 0.1uF
SC_R/COMP2_Pr
HP_ROUT_N
HP_DET
C340
33pF
OPT
C337
22pF
OPT
C329 0.1uF
INCM_VID_SC
C314 1uF 10V
SC_CVBS_IN
INCM_VID_AV1
SC_FB
R316
36
HP_ROUT_P
TU_SIF
AUD_LRCH
C332 0.1uF
C310 1uF 10V
C323 0.1uF
INCM_B
C313 1uF 10V
C325 0.1uF
R319
10K
OPT
R306
75
1%
OPT
SCART1_Lout_N
M_REMOTE_TX
R311
36
SCART1_Lout_P
C321 0.1uF
INCM_TUNER
TU_RESET
INCM_AUD_SC/COMP2
AV1_CVBS_IN
R314
12K
PC_L_IN
R322 0
C333 0.1uF
R323 0
C318 0.1uF
C316 1uF 10V
DSUB_R+
C331 0.1uF
INCM_AUD_SC/COMP2
SCART1_Rout_P
+3.3V_Normal
INCM_SIF
C317 0.1uF
INCM_AUD_AV2
INCM_R
TU_CVBS
AV1_L_IN
C315 1uF 10V
R315
120
OPT
S2_RESET
C326 0.1uF
INCM_VID_AV2
C327 0.1uF
INCM_AUD_AV1
COMP1_Pb
C304 0.1uF
INCM_VID_AV1
SCART1_Rout_N
INCM_VID_COMP1
AV2_R_IN
C309 1uF 10V
C301
33pF
50V
AV1_CVBS_DET
R313
10K
AV2_L_IN
SC_G/COMP2_Y
COMP1_Y
HP_LOUT_N
SPDIF_OUT
+2.5V_BCM35230
C308 1uF 10V
R321 0
R305
240
OPT
AUD_LRCK
+2.5V_BCM35230
INCM_VID_SC/COMP2
INCM_AUD_AV1
R312
36
/RST_HUB
COMP1_Pr
R302
1.2K
R301
1.2K
LGE35230(BCM35230KFSBG)
IC101
NON_BCM_CAP
VI_R
B6
VI_INCM_R
A6
VI_G
C7
VI_INCM_G
A7
VI_B
B7
VI_INCM_B
C8
HSYNC_IN
C13
VSYNC_IN
A13
VI_Y1
C9
VI_PR1
A9
VI_PB1
B9
VI_INCM_COMP1
B8
VI_SC_R1
C11
VI_SC_G1
A10
VI_SC_B1
B10
VI_INCM_SC1
C10
VI_FB_1/GPIO
D10
VI_FS1
F13
VI_SC_R2
A12
VI_SC_G2
C12
VI_SC_B2
B12
VI_INCM_SC2
B11
VI_FB_2/GPIO
E12
VI_FS2
E14
VI_L1
E15
VI_C1_1
F17
VI_INCM_LC1_1
E16
VI_C1_2
F14
VI_INCM_LC1_2
E11
VI_CVBS1
C18
VI_INCM_CVBS1
B18
VI_CVBS2
A18
VI_INCM_CVBS2
C19
VI_CVBS3
A19
VI_INCM_CVBS3
B19
VI_CVBS4
C20
VI_INCM_CVBS4
B20
VI_SIF1_1
E19
VI_INCM_SIF1_1
D19
VI_SIF1_2
E10
VI_INCM_SIF1_2
F11
LGE35230(BCM35230KFSBG)
IC101
NON_BCM_CAP
SPDIF_INC_P
B15
SPDIF_INC_N
C15
SPDIF_IND_P
C14
SPDIF_IND_N
B14
I2SSCK_IN/GPIO
G4
I2SWS_IN
F4
I2SSD_IN/GPIO
G5
AADC_LINE_L1
C25
AADC_LINE_R1
B24
AADC_INCM1
A24
AADC_LINE_L2
E22
AADC_LINE_R2
E23
AADC_INCM2
D23
AADC_LINE_L3
C24
AADC_LINE_R3
C23
AADC_INCM3
B23
AADC_LINE_L4
E21
AADC_LINE_R4
D21
AADC_INCM4
D22
AADC_LINE_L5
B22
AADC_LINE_R5
C22
AADC_INCM5
A22
AADC_LINE_L6
F21
AADC_LINE_R6
D20
AADC_INCM6
E20
AADC_LINE_L7
A21
AADC_LINE_R7
C21
AADC_INCM7
B21
I2SSCK_OUTA/GPIO
AF8
I2SWS_OUTA/GPIO
AF9
I2SSD_OUTA0/GPIO
AG9
I2SSOSCK_OUTA/GPIO
AC9
I2SSD_OUTA1/GPIO
AD8
I2SSD_OUTA2/GPIO
AD9
I2SSCK_OUTC/GPIO
E2
I2SWS_OUTC/GPIO
F2
I2SSD_OUTC/GPIO
E3
I2SSOSCK_OUTC/GPIO
F3
I2SSCK_OUTD/GPIO
G2
I2SWS_OUTD/GPIO
G3
I2SSD_OUTD/GPIO
G1
I2SSOSCK_OUTD/GPIO
H1
SPDIF_OUTA/GPIO
B13
AUDMUTE_0/GPIO
AG8
AUDMUTE_1
E13
ADAC_AL_N
C28
ADAC_AL_P
C27
ADAC_AR_N
D28
ADAC_AR_P
D27
ADAC_CL_N
C26
ADAC_CL_P
A27
ADAC_CR_N
B27
ADAC_CR_P
B28
ADAC_DL_N
B25
ADAC_DL_P
A25
ADAC_DR_N
A26
ADAC_DR_P
B26
R310
0
R318
0
R325 0
NON_EU
R325-*1
10
EU
LGE35230
IC101-*1
BCM_CAP
VI_R
B6
VI_INCM_R
A6
VI_G
C7
VI_INCM_G
A7
VI_B
B7
VI_INCM_B
C8
HSYNC_IN
C13
VSYNC_IN
A13
VI_Y1
C9
VI_PR1
A9
VI_PB1
B9
VI_INCM_COMP1
B8
VI_SC_R1
C11
VI_SC_G1
A10
VI_SC_B1
B10
VI_INCM_SC1
C10
VI_FB_1/GPIO
D10
VI_FS1
F13
VI_SC_R2
A12
VI_SC_G2
C12
VI_SC_B2
B12
VI_INCM_SC2
B11
VI_FB_2/GPIO
E12
VI_FS2
E14
VI_L1
E15
VI_C1_1
F17
VI_INCM_LC1_1
E16
VI_C1_2
F14
VI_INCM_LC1_2
E11
VI_CVBS1
C18
VI_INCM_CVBS1
B18
VI_CVBS2
A18
VI_INCM_CVBS2
C19
VI_CVBS3
A19
VI_INCM_CVBS3
B19
VI_CVBS4
C20
VI_INCM_CVBS4
B20
VI_SIF1_1
E19
VI_INCM_SIF1_1
D19
VI_SIF1_2
E10
VI_INCM_SIF1_2
F11
BCM35230
3
MAIN AUDIO/VIDEO
50
Run Along DSUB_R Trace
PHONE JACK
Near
TU2101/2
TU2201/2/3
Near
Near
AUDIO INCM
JK1104
Near
Near
Near
JK1102
Route Between PC_L_IN & PC_R_IN Trace
Route Between AV2_L_IN & AV2_R_IN Trace
Run Along AV1_CVBS Trace
JK1102
Run Along TUNER_CVBS_IF_P Trace
JK1103
JK2501
Run Along DSUB_G Trace
Run Along COMP_Y_IN,COMP_Pr_IN,COMP_Pb_IN Trace
Run Along COMP_Y_IN,COMP_Pr_IN,COMP_Pb_IN/SC R,G,B Trace
VIDEO INCM
Route Along With TUNER_SIF_IF_N
Run Along DSUB_B Trace
Near
Run Along AV2_CVBS Trace
Near
JK1103
JK2501
P801
JK1101
TU2101/2
TU2201/2/3
Route Between AV1_L_IN & AV1_R_IN Trace
Route Between SC/COMP2_L_IN & SC/COMP2_R_IN Trace
Near
P801
Near
Near
P801
Near
JK801
Near
JK1104
BCM35230_with_CAP_220pF
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
DDR_DQ[6]
DDR_DQ[20]
DDR_DQ[25]
DDR_DQ[27]
DDR_DQ[29]
DDR_DQ[23]
DDR_DQ[9]
DDR_DQ[0]
DDR_DQ[9]
DDR_DM[0]
DDR_DQ[24]
DDR_DQ[22]
DDR_DM[1]
DDR_DQ[14]
DDR_DQ[20]
DDR_DQ[4]
DDR_DQ[5]
DDR_DQ[23]
DDR_DQ[30]
DDR_DQ[11]
DDR_DQ[21]
DDR_DQ[1]
DDR_DQ[21]
DDR_DQ[16]
DDR_DQ[3]
DDR_DM[2]
DDR_DQ[17]
DDR_DQ[2]
DDR_DQ[1]
DDR_DQ[27]
DDR_DQ[6]
DDR_DQ[8]
DDR_DQ[5]
DDR_DQ[16]
DDR_DQ[15]
DDR_DQ[7]
DDR_DQ[15]
DDR_DQ[30]
DDR_DQ[13]
DDR_DQ[12]
DDR_DQ[11]
DDR_DQ[26]
DDR_DM[3]
DDR_DQ[0]
DDR_DQ[28]
DDR_DQ[14]
DDR_DQ[13]
DDR_DQ[7]
DDR_DQ[31]
DDR_DQ[24]
DDR_DQ[26]
DDR_DQ[17]
DDR_DQ[19]
DDR_DQ[22]
DDR_DQ[28]
DDR_DQ[19]
DDR_DQ[4]
DDR_DQ[18]
DDR_DQ[2]
DDR_DQ[12]
DDR_DQ[29]
DDR_DQ[10]
DDR_DQ[31]
DDR_DQ[8]
DDR_DQ[25]
DDR_DQ[3]
DDR_DQ[10]
DDR_DQ[18]
+1.5V_DDR
C415
0.01uF
R419
56
1%
DDR_AA2
C440
1uF
DDR_AA11
C416
0.01uF
DDR_CKE
DDR_BAA2
K4B2G1646C
IC402
DDR_1333
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
NC_6
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
AR402 56
DDR_AA0
DDR_AA14
DDR_AA7
DDR_AA10
R430
4.7K
OPT
DDR_AA3
C438
1uF
DDR23_AA4
DDR_DQ[24-31]
DDR_BAA0
DDR_BAA0
DDR_DQ[16-23]
DDR23_AA5
AR405 56
DDR01_AA4
R414 10K
DDR_BAA2
DDR_BAA2
R426 56
DDR_AA3
DDR_DQ[24-31]
DDR_BAA0
DDR01_AA5
R424 56
DDR_AA11
DDR23_AA4
R412
56
1%
DDR_DQ[6]
+1.5V_DDR
DDR_QS2b
C412
1uF
DDR23_CLK
C437
100pF
DDR_QS2
+1.5V_DDR
DDR_CASb
DDR_VREFA
DDR_AA12
DDR01_AA4
C435
0.01uF
DDR_RASb
DDR_AA0
DDR_DQ[10]
DDR_AA2
C436
0.01uF
DDR_QS0
DDR_RASb
C441 1uF
DDR_DQ[0]
DDR_AA11
DDR_AA7
DDR01_CLK
DDR_AA13
DDR23_CLKb
DDR_AA3
R431
4.7K
OPT
DDR_QS1b
R411 240
1%
+1.5V_DDR
C453
1uF
6.3V
DDR01_AA6
DDR_AA2
DDR_QS3b
DDR_AA0
DDR_AA14
R405
4.7K
DDR_1333
DDR_RASb
C454
1uF
6.3V
DDR_AA9
DDR_AA14
DDR_QS3b
DDR_DQ[1]
DDR_AA8
R402
4.7K
OPT
R429
82
C426
1uF
AR401 56
DDR_RESETb
DDR_AA12
DDR01_CLKb
DDR_VREFA
DDR23_AA6
DDR_WEb
+1.5V_DDR
DDR_AA14
DDR_DM[1]
C442
100pF
DDR23_CLK
R427 56
DDR_DM[0]
DDR_DQ[4]
DDR_DQ[8-15]
DDR_CKE
+1.5V_DDR
AR406 56
DDR_AA10
R421 240
1%
DDR_QS1
AR403 56
R407
4.7K
R420 10K
DDR_QS0b
DDR_RASb
DDR_AA8
DDR_AA3
DDR_WEb
DDR_AA2
DDR_AA1
DDR01_AA5
DDR_AA8
DDR_AA13
DDR23_AA5
+1.5V_DDR
DDR_DM[3]
DDR_AA7
DDR_QS1
DDR_DM[2]
R408
4.7K
DDR_AA1
R416
4.99K
1%
R413
56
1%
DDR23_AA4
DDR_AA8
C417
470pF
DDR23_AA5
R422
4.99K
1%
R404
4.7K
HYNIX_DDR
C450
0.1uF
DDR_CKE
DDR_BAA1
DDR_DQ[5]
DDR_RESETb
DDR01_AA5
+1.5V_DDR
C451
0.1uF
DDR_AA12
DDR_CASb
DDR_BAA2
DDR_QS1b
DDR23_AA6
DDR_RESETb
DDR_AA9
DDR_BAA1
AR404 56
DDR_AA9
DDR_WEb
DDR_RESETb
R406
4.7K
OPT
DDR_DQ[8]
R410
4.7K
OPT
DDR_CASb
R409
4.7K
OPT
DDR_VREFA
R425 56
OPT
+1.5V_DDR
DDR01_AA6
DDR_AA13
DDR_AA10
DDR_BAA0
DDR01_CLKb
C419
1000pF
DDR_AA10
DDR_CASb
R415 240
1%
DDR01_AA6
K4B2G1646C
IC401
DDR_1333
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
NC_6
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
DDR_AA13
+1.5V_DDR
R401
4.7K
DDR_1333
DDR_AA11
DDR_AA1
DDR_QS2
C452
0.1uF
DDR_QS3
DDR_CKE
DDR_BAA1
DDR_QS0
+1.5V_DDR
R403
4.7K
DDR_AA12
R418
56
1%
DDR01_CLK
C455
1uF
6.3V
DDR_QS2b
DDR_DQ[3]
R423
4.99K
1%
DDR_DQ[2]
DDR_AA9
+1.5V_DDR
DDR_BAA1
DDR_DQ[16-23]
DDR_AA0
DDR_DQ[8-15]
DDR23_CLKb
DDR_WEb
DDR_AA1
R428
82
C401
1000pF
DDR_DQ[0-7]
C439
1uF
DDR_DM[0-3] DDR_QS3
R417
4.99K
1%
DDR_AA7
DDR23_AA6
DDR_DQ[7]
DDR_QS0b
DDR_DQ[0-7]
DDR01_AA4
DDR_DQ[9]
R432
4.7K
OPT
C405
10uF
C425
10uF
C423
10uF
LGE35230(BCM35230KFSBG)
IC101
NON_BCM_CAP
DDR_DQA_0
U26
DDR_DQA_1
R26
DDR_DQA_2
U27
DDR_DQA_3
R27
DDR_DQA_4
V27
DDR_DQA_5
P26
DDR_DQA_6
U25
DDR_DQA_7
P27
DDR_DQA_8
R24
DDR_DQA_9
N24
DDR_DQA_10
T25
DDR_DQA_11
M23
DDR_DQA_12
R23
DDR_DQA_13
N25
DDR_DQA_14
T24
DDR_DQA_15
N26
DDR_DQA_16
L26
DDR_DQA_17
H27
DDR_DQA_18
L27
DDR_DQA_19
J26
DDR_DQA_20
M27
DDR_DQA_21
G27
DDR_DQA_22
M26
DDR_DQA_23
H26
DDR_DQA_24
L23
DDR_DQA_25
H25
DDR_DQA_26
L24
DDR_DQA_27
J24
DDR_DQA_28
M24
DDR_DQA_29
H23
DDR_DQA_30
L25
DDR_DQA_31
H24
DDR_DMA_0
T26
DDR_DMA_1
P25
DDR_DMA_2
J27
DDR_DMA_3
K24
DDR_DQSA_P_0
T27
DDR_DQSA_N_0
T28
DDR_DQSA_P_1
P24
DDR_DQSA_N_1
P23
DDR_DQSA_P_2
K27
DDR_DQSA_N_2
K28
DDR_DQSA_P_3
K25
DDR_DQSA_N_3
K26
DDR_ADA_0
V23
DDR_ADA_1
AB27
DDR_ADA_2
Y23
DDR_ADA_3
Y26
DDR_ADA_4
AB26
DDR_ADA_5
Y24
DDR_ADA_6
AC26
DDR_ADA_ALT_4
AB24
DDR_ADA_ALT_5
AC25
DDR_ADA_ALT_6
AC24
DDR_ADA_7
AB25
DDR_ADA_8
AD28
DDR_ADA_9
Y25
DDR_ADA_10
AA27
DDR_ADA_11
AC27
DDR_ADA_12
AA26
DDR_ADA_13
AA24
DDR_ADA_14
AD27
DDR_BAA_0
Y27
DDR_BAA_1
AB28
DDR_BAA_2
W24
DDR_RASA_N
V24
DDR_CASA_N
W25
DDR_WEA_N
V26
DDR_CKEA
U24
DDR_CKA01_P
W27
DDR_CKA01_N
W28
DDR_CKA23_P
N28
DDR_CKA23_N
N27
DDR_VREFA
U23
DDR_RST_N
AA23
DDR_ZQ
W26
C421
2.2uF
C403
2.2uF
C407
2.2uF
NFM18PS105R0J
C410
6.3V
OUTIN
GND
NFM18PS105R0J
C432
6.3V
OUTIN
GND
NFM18PS105R0J
C433
6.3V
OUTIN
GND
NFM18PS105R0J
C402
6.3V
OUTIN
GND
K4B2G1646C-HCK0
IC402-*1
DDR_1600
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
NC_6
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
K4B2G1646C-HCK0
IC401-*1
DDR_1600
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
NC_6
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
C404
0.1uF
C406
0.1uF
C408
0.1uF
C409
0.1uF
C411
0.1uF
BCM35230
Bus Width : DDR_DQ[10]
0 - 16b
1 - 32b (O)
Chip Width : DDR_DQ[8]
0 - 8b
1 - 16b (O)
Chip Size : DDR_DQ[6:5]
00 - 4Gbit
01 - 2Gbit (O)
10 - 1Gbit
11 - 512Mbit
DUAL COMPONENT
IC401-*1
IC402-*1
1ST : T-K4B2G1646B_HCK0, 2ND : T-H5TQ2G63BFR-PBC
DDR STRAP
4
JEDEC Types : DDR_DQ[0:4]
00001 : DDR3-1333H (CasL=9)
10101 : DDR3-1600K (CasL=11) (O)
MAIN DDR
50
IC401,IC402 1ST : EAN61667501, 2ND : EAN61570701
DDR_DQ[9] DDR_DQ[7] Maker
1 1 SS
Hynix
Reserve
Reserve
01
10
00
THERMAL
THERMAL
THERMAL
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
R524
0
POWER_24_GND
R552
10K
OPT
L503
MLB-201209-0120P-N2
C510
0.01uF
50V
R558-*1
22K
5V_PANEL
A_DIM
+2.5V_BCM35230
0R540
NON_OPC/NON_IOP
PWM_DIM_22
+3.5V_ST
C519
0.1uF
50V
C503
10uF
16V
+12V
+0.9V_CORE
Q502
RT1P141C-T112
1
2
3
R543
6.8K
OPT
C513
0.1uF
16V
C530
3300pF
50V
R547
10K
PANEL_VCC
+3.3V_Normal
R554
10K
OPT
A_DIM_20
POWER_ON/OFF2_1
C558
0.1uF
16V
OPT
C532
0.1uF
16V
OPT
R575
2K
1/8W
PANEL_DISCHARGE_REG
L509
3.6uH
INV_CTL
R531 0
POWER_20_A_DIM
C546
10uF
16V
A_DIM_20
C507
1000pF
50V
INV_CTL_18
R559
1.8K
12V_PANEL
R535 0
POWER_22_A_DIM
C509
220pF
50V
PANEL_CTL
R566
10K
R522
10K
OPT
R505
6.8K
C560
1uF
25V
OPT
Q504
2SC3052
E
B
C
0R527
POWER_24_PWM_DIM
0
R526
POWER_22_PWM_DIM
C538
47uF
10V
+5V_Normal
L516
3.6uH
NR8040T3R6N
R520
100
R577 4.7
0.1uF
C533
OPT
+12V
R576
2K
1/8W
PANEL_DISCHARGE_REG
+3.5V_ST
L514
BLM18PG121SN1D
R572
10K
1%
C570
22uF
16V
C5552700pF
+3.5V_ST
C551
0.1uF
50V
+12V
ERROR_OUT_24
R545
59K
1%
L515
3.6uH
NR8040T3R6N
R532
100
POWER_18_INV_CTL
R501
12K
1/16W
1%
C581
0.1uF
16V
NON_PD_+3.5V
C5572200pF
C527
10uF
6.3V
C528
10uF
16V
+24V
A_DIM
C505
10uF
16V
C568
22uF
10V
R502
10K
IC505
AOZ1024DI
EAN60660601
1
PGND
2
VIN
3
AGND
4
FB
5
COMP
6
EN
7
LX
+3.3V_Normal
R542
10K
C522
22uF
10V
0R538
POWER_20_PWM_DIM
Q501
2SC3052
E
B
C
R567
51K
1%
C508
0.1uF
16V
+5V_USB
C564
100pF
50V
OPT
C516
4.7uF
10V
R578 4.7
L501
MLB-201209-0120P-N2
R544
18K
1%
INV_CTL_18
R551
10K
OPT
R536
10K
+3.5V_ST
R515
0
5%
PD_+3.5V
POWER_ON/OFF2_1
C559
0.1uF
16V
OPT
C524
47uF
10V
OPT
R533
0
POWER_18_A_DIM
C565
100pF
50V
OPT
C531
1uF
OPT
R558
10K
12V_PANEL
R565
10K
C563
0.1uF
50V
+3.3V_Normal
L506
120-ohm
R507
10K
OPT
C525
10uF
10V
R568
1.5K
1%
+12V
L502
BLM18PG121SN1D
+12V
Q506
2SC3052
E
B
C
R570
51K
1%
C567
22uF
10V
L507
BLM18PG121SN1D
C537
50V
OPT
R528
10K
OPT
C571
22uF
16V
OPT
+3.5V_ST
L504
MLB-201209-0120P-N2
PWM_DIM
P502
FW20020-24S
NORMAL_26~55
19
14
9
4
18
13
8
3
17
12
7
2
16
11
6
1
20
15
10
5
21 22
23 24
ERROR_OUT
C520
0.1uF
16V
ESD
POWER_ON/OFF2_1
C523
22uF
10V
OPT
ERROR_OUT
+3.5V_ST
R525
13K
R550
10K
1%
Q505
2SC3052
E
B
C
+3.3V_Normal
0R541
POWER_24_ERROR_OUT
POWER_ON/OFF2_2
C552
10uF
25V
PWM_DIM_22
R555
22K
R508
4.7K
R557
22K
0R529
POWER_20_ERROR_OUT
R504
2K
R537
100
POWER_24_INV_CTL
POWER_ON/OFF2_2
R559-*1
2.7K
5V_PANEL
R523
4.7K
ERROR_OUT_PULL_UP
L513
BLM18PG121SN1D
R519
100
NON_PD_+3.5V
PWM_DIM
IC504
AP2132MP-2.5TRG1
EAN61387601
3
VIN
2
EN
4
VCTRL
1
PG
5
NC
6
VOUT
7
ADJ
8
GND
9
[EP]
+12V
+24V
+5V_Normal
C545
10uF
16V
R549
4.7K
1%
Q507
AO3407A
G
D
S
R506
330
L511
MLB-201209-0120P-N2
12V_PANEL
ERROR_OUT_24
R546
1K
+12V
C580
0.1uF
16V
A_DIM
POWER_DET
P501
SMAW200-H24S2
SLIM_32~55
19
12V
14
GND
9
3.5V
4
24V
18
INV ON
13
GND
8
GND
3
24V
17
12V
12
3.5V
7
GND
2
24V
16
GND/V-sync
11
3.5V
6
GND
1
PWR ON
20
A.DIM
15
GND
10
3.5V
5
GND
21
12V22P.DIM1
23
GND/P.DIM224Err OUT
25
C506
0.1uF
50V
R548
27K
1%
R569
10K
1%
RL_ON
R553
47K
C515
0.47uF
25V
+1.5V_DDR
R591
10K
POWER_ON/OFF1
+3.5V_ST
R518
0
POWER_16_GND
C591
0.1uF
16V
C539
10uF
6.3V
C594
22uF
10V
560pF
C593
50V
10uF
C590
10V
L517
BLM18PG121SN1D
L/DIM0_VS
L_VS
R574 0
POWER_16_URSA_SCAN
R573 0
POWER_16_BCM_SCAN
R595
4.3K
1%
R593
3.9K
1%
R592
1K
1%
R510-*3
4.7K
1%
PD_+18.5V
R510-*4
5.6K
1%
PD_+20V
R511-*3
1.21K
1%
PD_+18.5V
R511-*4
1.3K
1%
PD_+20V
R517
100K
R516
100K
NON_PD_+3.5V
R512
2.7K
1%
PD_+12V
R513
1.21K
1%
NON_PD_+3.5V
R510
8.2K
1%
PD_24V
R511
1.5K
1%
PD_24V
C550
0.01uF
50V
C534
22uF
10V
C535
22uF
10V
IC503
APX803D29
1
GND
3
VCC2RESET
Q503
AON7430
3 S_3
2 S_2
4 G
1 S_1
5D
Q508
AON7200
3S_3
2S_2
4G
1S_1
5 D
L505
1uH
IC502
APX803D29
NON_PD_+3.5V
1
GND
3
VCC2RESET
IC508
AP7173-SPG-13 HF(DIODES)
3
VCC
2
PG
4
EN
1
IN
5
GND
6
SS
7
FB
8
OUT
9
[EP]
IC501
TPS40192DRCR
3
COMP
2
FB
4
VDD
1
ENABLE
5
PGD
6
BP5
7
LDRV
8
BOOT
9
SW
10
HDRV
11
EP_GND
R564
12K
R563
12K
IC506
AOZ1073AIL-3
3
AGND
2
VIN
4
FB
1
PGND
5
COMP
6
EN
7
LX_1
8
LX_2
IC507
AOZ1073AIL-3
3
AGND
2
VIN
4
FB
1
PGND
5
COMP
6
EN
7
LX_1
8
LX_2
C504
100pF
50V
R503
1K
R571
3.6K
1/16W
1%
DUAL COMPONENT
+1.5V_DDR
Err_out
PANEL_POWER
Q502
R1
+2.5V_BCM35230
+3.3V_NORMAL
22
LED:GND
FROM LIPS & POWER B/D
IC502,IC503
Max 960 mA
R2
INV_ON
20
Vout=0.8*(1+R1/R2)
R1
Q501,Q504,
Q505,Q506
PWM_DIM
R2
Err_out
Switching freq: 500K
PIN No
R2
+5V_USB+WIFI
A-DIM
58
R1
Vout=0.591*(1+R1/R2)
Vout=0.6*(1+R1/R2)
Placed on SMD-TOP
OS Module OPT
5
15V-->3.6V
Vout=0.8*(1+R1/R2)
CMO(09)
<OS MODULE PIN MAP>
24
1ST : EAN61151001, 2ND : EAN60670101
20V-->3.5V
TYP 1450mA
LGD
R2
1ST : 0TRIY80001A 2ND : 0TR387500AA
Power_DET
PWM_DIM
Switching freq: 500K
AUO
3A
A-DIM
GND
ST_3.5V-->3.5V
CHECK PWR/MODULE PIN MAP
Max 7350 mA
Placed on SMD-TOP
INV_ON
MAX 2.8A
PWM_DIM
PWM_DIM
not to RESET at 8kV ESD
Vout=0.8*(1+R1/R2)
3A
R1
INV_ON
MAX 1A
TEST
Vout=0.8*(1+R1/R2)
NC
Switching freq: 500K
24V-->3.48V
2A
1ST : EBK60752501, 2ND : EBK61011501
SHARP
Placed on SMD-TOP
Max 800mA
Err_out
12V-->3.58V
Q507
INV_ON
Switching freq: 600K
BCM35230
POWER
R2
R1
1ST : 0TRIH80004A, 2ND : EBK61012501, 3RD : 0TR102009AM
MAX 1.9A
4A
18
+5V_Normal
+0.9V_CORE_BCM35230
V4:VBR-A
V5:NC
#16/#20/#23
LD - GND OR USE
LE(N.L.D.) - OPEN
LE(L.D.) - USE
R2
R1
Vout=0.8*(1+R1/R2)
1.5A
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
+3.5V_ST
EDID_WP
C602
13pF
50V
R645
270K
OPT
SCART_MUTE
KEY2
NEC_ISP_Rx
C607 15pF
R624 10K
10YEAR_TOOL
NEC_RXD MICOM_RESET
R619
22
SIDE_HP_MUTE
R612 10K
LCD/OLED
X601
10MHz
POWER_ON/OFF1
R613 10K
TOUCH_KEY
R616
22
+3.5V_ST
R622 10K
I2C LED
R628 4.7K
+3.5V_ST
R644
47K
KEY1
+3.5V_ST
+3.5V_ST
+3.5V_ST
R617 22
R615 22
R641
0
MODEL1_OPT_0
MODEL1_OPT_1
C609 1uF
C604
0.1uF
RL_ON
R626 4.7K
R647 20K
1/16W
1%
+3.5V_ST
OCD1A
EEPROM_SCL
INSTANT_MODE
MODEL1_OPT_1
R642
4.7M
OPT
AMP_RESET_N
S/T_SCL
C605 0.1uF
FLMD0
EEPROM_SDA
LED_B/LG_LOGO
R638 22
OPT
R601
47K
AMP_MUTE
R625 10K
11YEAR_TOOL
R646
20K
1/16W
1%
GND
R632 22
MODEL1_OPT_2
MODEL1_OPT_0
R614 10K
TACT_KEY
R602 100
R637
47K
OPT
NEC_ISP_Tx
C606
15pF
R610
10K
R611 10K
PDP/3D
X602
32.768KHz
OCD1B
R605 100
MODEL1_OPT_2
R621 22
INV_CTL
R629
22
NEC_ISP_Tx
R639 10K
R606 10K
NEC_TXD
R607
10K
+3.5V_ST
R603 100
PANEL_CTL
MODEL1_OPT_3
MICOM_DOWNLOAD
+3.5V_ST
POWER_ON/OFF2_1
GND
R631 22
NEC_ISP_Rx
R604 100
R643 22
S/T_SDA
LED_R/BUZZ
C603
13pF
50V
C608
0.1uF
16V
R640
10K
R623 10K
PWM_LED
FLMD0
EEPROM_SDA
HDMI_CEC
SDA2_3.3V
R630
22
WIRELESS_DET
NEC_ISP_Rx
IC602
uPD78F0514
NEC_MICOM
1
P60/SCL0
2
P61/SDA0
3
P62/EXSCL0
4
P63
5
P33/TI51/TO51/INTP4
6
P75
7
P74
8
P73/KR3
9
P72/KR2
10
P71/KR1
11
P70/KR0
12
P32/INTP3/OCD1B
13
P31/INTP2/OCD1A
14
P30/INTP1
15
P17/TI50/TO50
16
P16/TOH1/INTP5
17
P15/TOH018P14/RXD619P13/TXD620P12/SO10
21
P11/SL10/RXD0
22
P10/SCK10/TXD0
23
AVREF
24
AVSS
25
ANI7/P27
26
ANI6/P26
27
ANI5/P25
28
ANI4/P24
29
ANI3/P23
30
ANI2/P22
31
ANI1/P21
32
P20/ANI0
33
P130
34
P01/TI010/TO00
35
P00/TI000
36
P140/PCL/INTP6
37
P120/INTP0/EXLVI
38
P4139P4040RESET41P124/XT2/EXCLKS
42
P123/XT1
43
FLMD044P122/X2/EXCLK/OCD0B
45
P121/X1/OCD0A
46
REGC47VSS48VDD
POWER_ON/OFF2_2
R649 0
OPT
OCD1A
MICOM_DOWNLOAD
+3.5V_ST
IR
POWER_DET
MICOM_RESET
MODEL1_OPT_3
P601
12505WS-12A00
1
2
3
4
5
6
7
8
9
10
11
12
13
OCD1B
IC601
M24C16-WMN6T
3
NC/E2
2
NC/E1
4
VSS
1
NC/E0
5
SDA
6
SCL
7
WC
8
VCC
NEC_ISP_Tx
EEPROM_SCL
R627
4.7K
SCL2_3.3V
+3.5V_ST
R636
4.7K
R633
22
OPT
SOC_RESET
WIRELESS_PWR_EN
Q601
2SC3052
E
B
C
SW1
JTP-1127WEM
12
4 3
R648 10K
BCM35230
MICOM
EEPROM for Micom
30
MODEL_OPT_2
MICOM MODEL OPTION
PWM_LED
LOW
11
MODEL_OPT_0
PIN NAME
31
8
HIGH
For Debug
11YEAR_TOOL
(11 SENSOR)
10YEAR_TOOL
(10 SENSOR)
50
PDP/3D
6
MODEL OPTION
MODEL_OPT_3
TACT_KEY
10Mhz Crystal
LCD/OLED
MODEL_OPT_1 I2C_LED
TOUCH_KEY
PIN NO.
HIGHLOW_SMALL
MODEL_OPT_3
TBD
1
LCD
1
0
0 10
MODEL_OPT_2
MODEL_OPT_1
OLED 3D
0 0
10
1
PDP
LOW
1
NEC MICOM
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
SCL2_3.3V
R1602 33
LPB_42/47/55
SDA2_3.3V
R1601 33
LPB_42/47/55
L/DIM0_MOSI
L/DIM0_SCLK
L/DIM0_VS
P1601
12507WR-08L
1
2
3
4
5
6
7
8
9
50
BCM35230
16
L_DIMMING
[Local Dimming Block]
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
CI_TS_DATA[1]
NAND_DATA[6]
FE_TS_DATA[3]
PCM_MDI[3]
NAND_DATA[5]
CI_DATA[1]
PCM_ADDR[2]
PCM_ADDR[4]
PCM_ADDR[9]
FE_TS_DATA[2]
CI_TS_DATA[5]
CI_DATA[6]
FE_TS_DATA[1]
PCM_TS_DATA[2]
CI_DATA[7]
PCM_ADDR[12]
CI_ADDR[1]
NAND_DATA[2]
CI_MDI[5]
PCM_MDI[5]
PCM_MDI[7]
CI_DATA[2]
PCM_TS_DATA[4]
CI_DATA[0]
CI_MDI[4]
CI_MDI[0]
CI_TS_DATA[7]
CI_MDI[1]
CI_DATA[6]
CI_MDI[5]
NAND_DATA[4]
CI_MDI[0]
FE_TS_DATA[0]
CI_ADDR[14]
CI_ADDR[10]
CI_TS_DATA[2]
PCM_MDI[6]
PCM_MDI[2]
PCM_TS_DATA[5]
CI_DATA[0]
CI_TS_DATA[6]
CI_MDI[3]
CI_MDI[6]
PCM_TS_DATA[3]
NAND_DATA[0]
CI_MDI[6]
CI_ADDR[8]
PCM_TS_DATA[6]
FE_TS_DATA[4]
PCM_MDI[4]
PCM_MDI[0]
PCM_TS_DATA[1]
CI_TS_DATA[0]
CI_ADDR[6]
NAND_DATA[7]
CI_MDI[2]
PCM_ADDR[3]
CI_DATA[7]
CI_DATA[5]
CI_MDI[7]
FE_TS_DATA[6]
CI_MDI[4]
PCM_ADDR[7]
PCM_TS_DATA[7]
CI_ADDR[0]
PCM_ADDR[11]
CI_TS_DATA[4]
PCM_TS_DATA[0]
CI_MDI[1]
FE_TS_DATA[5]
CI_DATA[3]
CI_MDI[7]
CI_DATA[3]
CI_DATA[2]
CI_ADDR[5]
CI_DATA[1]
CI_DATA[4]
CI_TS_DATA[3]
CI_DATA[5]
CI_DATA[4]
CI_MDI[2]
CI_MDI[3]
PCM_MDI[1]
FE_TS_DATA[7]
NAND_DATA[3]
PCM_ADDR[13]
NAND_DATA[1]
CI_TS_SYNC
R1954
22
CI
R1970
22
CI
R1961
22
CI
P1901
10067972-000LF CI
G1G2
57
TS_OUT_CLK
21
ADDR12
52
VPP
16
/IRQA
10
ADDR11
47
TS_IN0
41
TS_OUT7
5
DAT6
36
/CI_DET1
59
CI_WAIT
23
ADDR6
45
IOWR
54
TS_IN5
18
VPP
49
TS_IN2
43
VS1
13
ADDR13
7
/CARD_EN1
38
TS_OUT4
2
DAT3
25
ADDR4
56
TS_IN7
20
TS_IN_CLK
51
VCC
15
/WR_EN
9
/O_EN
46
TS_IN_SYN
40
TS_OUT6
4
DAT5
35
GND
58
CI_RESET
22
ADDR7
53
TS_IN4
17
VCC
11
ADDR10
48
TS_IN1
42
CARD_EN2
12
ADDR8
6
DAT6
37
TS_OUT3
1
GND
24
ADDR5
55
TS_IN6
19
TS_IN_VAL
50
TS_IN3
44
IORD
14
ADDR14
8
ADDR10
39
TS_OUT5
3
DAT4
26
ADDR3
60
INPACK
27
ADDR2
61
REG
28
ADDR1
62
TS_OUT_VAL
29
ADDR0
63
TS_OUT_SYN
30
DAT0
64
TS_OUT0
31
DAT1
32
DAT2
33
/IO_BIT
34
GND
65
TS_OUT1
66
TS_OUT2
67
/CI_DET2
68
GND
69
R1902
22
CI
R1933
10K
OPT
R1917
22
OPT
L1901
BLM18PG121SN1D
CI
R1909 22
OPT
R1953
22
CI
R1919
22
OPT
CI_TS_DATA[3]
+3.3V_CI
AR1903 22
OPT
R1986 22
CI
NIM_TS_SYNC
/PCM_WE
CI 15
/CI_EN1
CI_ADDR[5]
CI_ADDR[0]
R1960
22
CI
PCM_ADDR[13]
NIM_VAL_ERR
R1929
10K
OPT
/PCM_IRQA
C1909
4.7uF
16V
OPT
C1914
0.1uF
16V
CI
CI_TS_DATA[6]
PCM_TS_CLK
R1922
22
CI
+5V_CI_ON
/CI_CE1
R1957 22
CI
CI_ADDR[11]
/CI_CE1
C1912
0.1uF
16V
CI
R1941
10K
CI
R1927
22
CI
R1967 22
CI
NAND_REb
+3.3V_Normal
R1938 62
CI
+5V_CI_ON
R1971
10K
CI
R1951
22
CI
CI_MDI[0-7]
R1907 22
CI
+3.3V_CI
/CI_CD2
+5V_CI_ON
/CI_CD1
R1940
10K
OPT
NIM_TS_CLK
C1901
0.1uF
16V
OPT
+5V_Normal
PCM_TS_DATA[0-7]
R1946
10K
OPT
+3.3V_CI
PCM_ADDR[9]
NAND_WEb
R1910
22
OPT
R1901 22
CI
C1902
0.1uF
16V
OPT
/PCM_IORD
Q1902
AO3407A
CI
G
D
S
/CI_CD2
CI_ADDR[1]
CI_TS_CLK
C1911
0.1uF
16V
OPT
R1969
10K
CI
CI_ADDR[9]
C1915
0.1uF
16V
OPT
R1980 100
CI
R1945
10K
OPT
R1966
10K
CI
R1985
10K
CI
R1936
0
OPT
R1949
22
CI
R1937
62
CI
R1959
22
CI
PCM_MCLKI
PCM_TS_SYNC
C1904
0.1uF
CI
CI_MIVAL_ERR
CI_ADDR[13]
CI_MISTRT
R1947
22
CI
PCM_ADDR[4]
PCM_MDI[0-7]
PCM_ADDR[9]
+3.3V_CI
R1931 22
CI
CI_ADDR[12]
R1918
22
OPT
R1903 22
CI
PCM_MIVAL_ERR
R1939
10K
CI
PCM_ADDR[12]
PCM_ADDR[12]
IC1903
74LVC245A
CI
3
A1
2
A0
4
A2
1
DIR
6
A4
5
A3
7
A5
8
A6
9
A7
10
GND11B7
12
B6
13
B5
14
B4
15
B3
16
B2
17
B1
18
B0
19
OE
20
VCC
CI_TS_DATA[0-7]
NAND_REb
PCM_ADDR[13]
R1956 22
CI
/PCM_OE
CI 9
CI_ADDR[2]
CI_ADDR[0]
PCM_ADDR[3]
+3.3V_CI
IC1904
74LVC1G32GW
CI
3GND2A4 Y
1B 5 VCC
+3.3V_CI
CI_MDI[0-7]
CI_TS_VAL
PCM_ADDR[2]
CI_TS_DATA[0]
R1948
22
CI
CI_ADDR[10]
C1908
0.1uF
CI
CI_ADDR[3]
C1906
0.1uF
16V
OPT
R1958
22
CI
R1942
4.7K
CI
R1934
10K
OPT
/PCM_IOWR
R1965
47
CI
FE_TS_DATA[0-7]
/PCM_OE
/PCM_WAIT
CI_TS_DATA[1]
NAND_REb
NAND_RBb
R1962
22
CI
C1907
0.1uF
CI
AR1904 100
CI
/PCM_IOWR
CI 45
PCM_5V_CTL
CI_MISTRT
CI_TS_VAL
R1963
22
CI
L1902
BLM18PG121SN1D
CI
PCM_TS_VAL
GND
+3.3V_CI
CI_MCLKI
R1952
22
CI
PCM_ADDR[7]
R1935 0
CI
R1904 22
CI
CI_TS_DATA[5]
/CI_EN1
/CI_EN1
Q1901
2SC3052
CI
E
B
C
CI_DATA[0-7]
R1964 22
CI
NAND_DATA[0-7]
NAND_CLE
CI_ADDR[8]
PCM_MISTRT
CI_TS_CLK
R1928
22
CI
R1932
10K
CI
R1972
10K
CI
CI_ADDR[4]
/CI_CD1
R1973
10K
CI
CI_MIVAL_ERR
+5V_CI_ON
CI_ADDR[6]
+5V_CI_ON
/PCM_CE1
PCM_ADDR[7]
PCM_RST
/CI_EN1
R1976
22
CI
R1974
22
CI
NAND_WEb
CI_ADDR[7]
+5V_CI_ON
CI_ADDR[1]
+3.3V_CI
CI_TS_DATA[2]
CI_DATA[0-7]
CI_ADDR[14]
PCM_ADDR[2]
PCM_ADDR[11]
PCM_ADDR[4]
R1920
22
CI
R1926
22
CI
R1905 22
CI
C1905
10uF
10V
CI
R1943
22K
CI
C1903
0.1uF
16V
OPT
R1915 22
OPT
AR1905 100
CI
IC1901
74LVC125APW
CI
3
1Y
2
1A
4
2OE
1
1OE
6
2Y
5
2A
7
GND83Y
9
3A
10
3OE
11
4Y
12
4A
13
4OE
14
VCC
/PCM_WE
/PCM_IORD
CI 44
+5V_CI_ON
R1906
22
CI
R1955
22
CI
CI_TS_SYNC
C1910 0.1uF
CI
PCM_ADDR[11]
R1968
10K
CI
/CI_CE2
/PCM_CE1
CI 7
R1944
0
OPT
R1950
22
CI
R1921
22
CI
/CI_CE2
CI_TS_DATA[7]
R1908 22
CI
+5V_CI_ON
CI_DET
CI_TS_DATA[4]
CI_MCLKI
PCM_ADDR[3]
IC1905
74LVC245A
CI
3
A1
2
A0
4
A2
1
DIR
6
A4
5
A3
7
A5
8
A6
9
A7
10
GND11B7
12
B6
13
B5
14
B4
15
B3
16
B2
17
B1
18
B0
19
OE
20
VCC
R1916 22
OPT
C1913
0.1uF
16V
CI
R1930
10K
OPT
R1975
10K
CI
IC1902
74AHC08PW
CI
3
1Y
2
1B
4
2A
1
1A
6
2Y
5
2B
7
GND83Y
9
3A
10
3B
11
4Y
12
4A
13
4B
14
VCC
C1916
12pF
50V
OPT
R1987
2.2K
CI
AR1901
100
CI
AR1902 100
CI
R1924
100
CI
R1925
100
CI
R1923
220
CI
R1977
10K
OPT
1ST : EBK60752501, 2ND : EBK61011501
Close to CI Slot
3,3V_CI POWER
Close to Tuner
Q1901
NAND F/M Data
CI DETECT
1ST : 0TRIY80001A 2ND : 0TR387500AA
Close to CI Slot
Close to BCM35230
Close to BCM35230
CI
BCM INT Demod
CI TS OUTPUT
CI CONTROL INTERFACE
OE DIR CI_DATA NAND_DATA
L L OUTPUT INPUT
L H INPUT OUTPUT
H X Z Z
CI TS INPUT
CI POWER ENABLE CONTROL
DUAL COMPONENT
Q1902
19
IC1904
BCM INT Demod
BCM35230
1ST : 0ISTLPH062A, 2ND : EAN40055001
58
2010.11.11
Loading...