Lenovo Xiaoxin AIR-14IIL 2020 Schematic

A

www.forums-fastunlock.com

1 1

B

C

D

E

Compal Confidential

2 2

FLMS0

DIS M/B Schematic Document

Intel Ice Lake-U Processor with DDR4 Memory Down

3 3

2019-08-22

LA-J551P

R E V

：

0 . 2

4 4

Security Classification

A

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2019/05/ 15 2020/05/ 15

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date : Sheet

Date : Sheet of

D

Date : Sheet of

Compal Electronics, Inc.

Cover Page

LA-LJ551PR02

E

0.2

o f

1 67Thursday, August 2 2, 2019

A

www.forums-fastunlock.com

B

C

D

E

NVIDIA N17S-G3/G4

VRAM(GDDR5) X2 2GB TDP18W

1 1

eDP Panel

FHD LCD

PCIe x4 , Gen3 8Gb/s

eDP x4 , HBR 5.4Gb/s eDP x2 , HBR 2.7Gb/s

DDR4 3200MHz

USB2.0 x1, 480Mb/s

USB3.1 x1, Gen1 5Gb/s

UHD LCD (Reserve)

HDMI Conn.

TCSS x4 , 2.97GT/s

USB3.1 x1, Gen1 5Gb/s

CH-A on board RAM x4 CH-B on board RAM x4

USB Charger

TI SN1702001

USB3 redriver

Parade PS8719

USB3 redriver

Parade PS8719

USB2.0 x1, 480Mb/s

USB3.1 x1, Gen1 5Gb/s

USB Conn. with AOU

USB Conn.

USB2.0 x1, 480Mb/s

Intel ICL-U

15W

NGFF (Key M)

PCIE/SATA SSD

2 2

2242/2280 conn.

NGFF (Key E)

WLAN/BT 2230 conn.

VBus

PWR Switch

DIODE DPS1155

PD_PWR_EN

CC/SBU/Vconn

CC+DP

Realtek RTS5457V

+5VALW

Type-C Conn.

USB3.1 Gen1

3 3

VBus

CC/Vconn

CC +VBUS

Realtek RTS5467A (Reserve)

+5VALW

PCIe x4 , Gen3 8Gb/s SATA , Gen3 6Gb/s

PCIe x1 , Gen1 2.5Gb/s

USB2.0 x1, 480Mb/s

CNVi

I2C_3VLP

EC

PD_AUX

TCSS x4 Lane

USB2.0 x1, 480Mb/s

1528pin BGA

USB2.0 x1, 480Mb/s

PCIe x1 , Gen1 2.5Gb/s

HDA

FingerPrint

Int. Camera

Touch Panel

Card Reader

Realtek RTS5232S

Audio Codec

Realtek ALC3287

IO Board

FP Module Board

SDIO

IO Board

HP

SPK

SD Card Conn.

Combo Jack

Int. Speaker

SPI ROM

16MB

SPI

I2C

TouchPad

eSPI

Int. KBD

LED

4 4

A

B

KBC

ENE KB9052

C

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF THE COMPET ENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF THE COMPET ENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF THE COMPET ENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Block Diagram

Size

Document Number Rev

Size

Document Number Rev

Size

Document Number Rev

Custom

LA-LJ551PR02

Date: Sheet of

E

2 6 7Thursday, August 22, 201 9

0.2

1

www.forums-fastunlock.com

Voltage Rails

+5VS

+3VS

power plane

+5VALW

A A

State

S0

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery don't exist

B B

EC SM Bus1 address

Device

Smart Battery

Charger (ISL88739A)

PCH SM Bus address

Device

DDR_JDI MM1 Touch Pad

+12.6V B

Address

0001 011x 16h

0001 001x 12h

Address

1010 010x A4h

+3VALW

+1.8VAL W

O

X

EC SM Bus2 address

Device

Thermal Sensor (F75305M)

Thermal Sensor (F75397M)

GPU SM Bus address

Device

Internal thermal sensor

+1.2V

+2.5V

O O

O

X

+1.8VS

+0.6VS

+1.05V_V CCST

+1.05VS_ VCCSTG

+VCCIN

+VCCIN_A UX

+1.8VS_D GPU

+1.8VS_D GPU_AON

+VGA_COR E

+1.0VS_D GPU

+1.35VS_ VRAM

Address

1001_101xb 9Ah

1001_100xb 98h

Address

1001 111x 9Eh

X

XX

X

XXX

SMBUS Control Table

SOURCE

C C

EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 EC_SMB_CK4 EC_SMB_DA4 SOC_SMBC LK SOC_SMBDAT A SOC_SML 0CLK SOC_SML0DA TA

SOC

KB905 2

X

+3VL

KB905 2

V

+3VS

KB905 2

X

+3VS

SOC

X

+3VS

SOC

X X

+3VS

CHARGER

V X

V

+19V_V IN

+3VALW

X

X X X X

X

SODIMMKB9052BATT

X

+3VS

2

BOM Structure Table

Item

GPU N17S-G0/G2

Debug

Memory Down - SDP Package

Memory Down - DDP Package

Only CHB Memory Down Intel CNVi Keyboard Back Light

ESD Categ ory ESD@ RF Category RF@ Normal FP Device SLIM_ FP +12V FAN CAP +5V F AN CAP

CPU MIC (Reserve )

Modern standby

Project select

DDR4 Memory Down CHB

GPU G C6 M ode

Touch Screen Power EC9052Q C Ver sion

Option Bypass US B Charger

RMT tool test

CPU select

Thermal

DGPU

Sensor

X

V

X

+3VS

V

+3VS

BOM Structure

DIS@ UMA@ DCI@ SDP@ SDP_C HB@ DDP@ DDP_C HB@ CHB@ CNVi@ KBL@ EMI@EMI Categ ory

FP@ SLIM_ FP@

Arrary _MIC@ Single _MIC@ S0iX@ NOS0i X@

CHB@ GC6@ NOGC6 @ TS@ EC905 2_C@

NON_A OU@ RMT@ QSQS_ R1@ QSQP_ R1@ QSQV_ R1@ QSVV_ R1@ QSQW_ R1@

X

V

X

3

Item

DGPU chip select

VRAM chip select

VRAM

ZZZ11

X76_H2G@

X76 HYNIX 2GB

X7684838L11

ICL-U CPU

UC1

QSQS_R1@

I7-1065G7

SA0000CT610

DGPU

R1

R3

BOM Structure

N17S_G 0_R1@ N17S_G 0_R3@ N17S_G 2_R1@ N17S_G 2_R3@

VRAM_M 2G_R1 @ VRAM_M 2G_R3 @ VRAM_H 2G_R1 @ VRAM_H 2G_R3 @ VRAM_S 2G_R1 @ VRAM_S 2G_R3 @

UC1

QSQP_R1@

I5-1034G1

SA0000CUQ10

UV1

SA0000CC940

N17S_G0_R1@

N17S-G0

UV1

SA0000CC910

N17S_G0_R3@

N17S-G0

ZZZ12

X76_S2G@

X76 SAMSUNG 2GB

X7684838L12

UC1

QSQV_R1@

I5-1035G1

SA0000CTB10

UV1

N17S_G2_R1@

N17S-G2

UV1

N17S_G2_R3@

N17S-G2

4

USB 2.0 Port Table

External USB Por tPort

1

USB2/3 Port (IO - 1)

2

USB2/3 Port (IO - 2)

3

USB2/3 Port (Type-C)

4

Touch Screen

5 6

Camera

7

Fingrt Print

8 9 10

NGFF WLAN+BT

USB 3.0 Port Table PCIE Port Table

Port

1

USB2/3 Port (IO - 1)

2

USB2/3 Port (IO - 2)

3 4 5 6

SATA Port Table

Port

0 1A

1B

SSD

ON BOARD RAM X76

ZZZ13

X76_M2G@

X76 MICRON 2GB

X7684838L13

ZZZ10

X76_M4G_1CH_3200@

X76 MICRON 4GB SINGEL

X7684838L10

ZZ9

X76_M8G_2CH_3200@

X76 MICRON 8GB DUAL

X7684838L09

PCB PN

ZZZ

SA0000CCB30

SA0000CCB10

UC1

QSVV_R1@

I3-1005G1

SA0000CVQ10

UC1

QSQW_R1@

I3-1005G1

SA0000CTD10

5

TCP Port Table

Port Lane

0

TYPE C (PD + CC)

1

HDMI

2 3

Port

Lane

1 2 3 4

0

5

0

6

1

7

2

8

3

9

1

10

0 11 12

0 13

3 14

2 15

1 16

0

ZZZ7

X76_H16G_2CH_2666@

X76 HYNIX 16GB DUAL

X7684838L07

ZZZ6

X76_H4G_1CH_2666@

X76 HYNIX 4GB SINGEL

X7684838L04

ZZZ5

X76_H8G_2CH_2666@

X76 HYNIX 8GB DUAL

X7684838L03

GPU

CardReader NGFF WLAN+BT

SSD

ZZZ3

X76_S16G_2CH_2666@

X76 SAMSUNG 16GB DUAL

X7684838L05

ZZZ2

X76_S4G_1CH_2666@

X76 SAMSUNG 4GB SINGEL

X7684838L02

ZZZ1

X76_S8G_2CH_2666@

X76 SAMSUNG 8GB DUAL

X7684838L01

VRAM

SA00009TI30

SA00009TI50

Hynix

UV21

VRAM_H2G@_R1@

H5GC8H24AJR-R2C

UV22

VRAM_H2G@_R1@

H5GC8H24AJR-R2C

UV21

VRAM_H2G@_R3@

H5GC8H24AJR-R2C

UV22

VRAM_H2G@_R3@

H5GC8H24AJR-R2C

SA0000C1710

SA0000C1730

Samsung

UV21

SA00009TA50

VRAM_S2G@_R1@

H5GC8H24AJR-R2C

UV22

SA00009TA50

VRAM_S2G@_R1@

H5GC8H24AJR-R2C

UV21

SA0000C1730

VRAM_S2G@_R3@

H5GC8H24AJR-R2C

UV22

SA0000C1730

VRAM_S2G@_R3@

H5GC8H24AJR-R2C

PCB FL535 LA-H105P

DA8001LE000

X4E

ZZZ14

X4E_DIS@

X4E S550- ICL DIS

X4EAJY38L01

ZZZ15

X4E_UMA@

X4E S550- ICL UMA

X4EAJY38L02

Micron

UV21

STATE

Full ON

S1(Power On Suspend)

D D

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SIGNAL

SLP_S1 #

LOW

HIGH HIGH HIGH

LOW

LOW LOW LOW

LOWLOW

SLP_S4 #SLP_S3 # +V+VALWSLP_S5 # Clock+VS

HIGH

ONONON

ON

LOWLOW

ON

OFF

ON

OFF

HIGHHIGHHIGH

HIGH

ONON

LOW

OFF

R1

R3

VRAM_M2G_R1@

MT51J256M32HF-80

UV22

VRAM_M2G_R1@

MT51J256M32HF-80

UV21

VRAM_M2G_R3@

MT51J256M32HF-80

UV22

VRAM_M2G_R3@

MT51J256M32HF-80

1

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

Compal Secret Data

Deciphered Date

4

Compal Electronics, Inc.

Title

Notes List

Size

Document Number Re v

Custom

LA-LJ551PR02

Date : Sheet o f

5

3 67Thursday, August 22, 2019

0.2

5

www.forums-fastunlock.com

4

3

2

1

[DQA04-Power Map_ICL-U4+2_DDR4_Volume_S0ix]

D D

C C

B B

A A

Security Classification

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

2019/05/15 2020/05/15

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Power MAP

Size

Document Number Re v

LA-LJ551PR02

Date : Sheet o f

1

4 67Thursday, August 22, 2019

0.2

5

www.forums-fastunlock.com

[ DQA04-PWR Sequence_ICL-U4+2_DDR4_Volume_S0iX ]

4

3

2

1

+3VL_RTC

SOC_RTCRST#

D D

C C

B B

A A

+3VALW_DS W/+3VALW

PCH_DPWROK

PM_BATLOW#

SLP_SUS#

+5VALW

EXT_PWR_GATE#

+3V_PRIM

+1.8V_ PRIM

+VCCIN_AUX

+1.05VO_OUT_PCH

+1.05V O_VNNBYPASS

+1.05VO_E XTBYPASS

EC_RSMRST#

ESPI_RST#

SUSCLK

AC_PRESENT_R

+1.05V_VCCST

+1.05VO_VCCPLL

PBTN_OUT#

PM_SLP_S5 #

PM_SLP_S4 #

PM_SLP_S3 #

PM_SLP_S0 #

CPU_C10_GATE#

VCCST_OVERRIDE

+2.5V

+1.2V_VDDQ

+1.2V_VCCPLL_ OC

+1.05VS_VCCST G

VCCSTPWRGOOD_ TGSS

EC_VCCST_PG

DDR_PG_CTRL

+0.6VS_VT T

VR_ON

+VCCIN

VR_PWRGD

PCH_PWROK

+1.05V_VCCIO_OUT

PCH_CLK_OUTPUTS

H_PROCPWRGD

SYS_PWROK

SOC_PLTRST#

H_THERMTRIP#

tPCH01_Min : 9 ms

tPCH04_Min : 9 ms

tPCH02_Min : 10 ms

tPCH05_Min : 1 us

tPCH32_Min : 95 ms

tPCH06_Min : 200 us

tPCH07_Min : 0 ms

tPCH31_Min : 105 ms

High_in_Sx_ if_TCSS_ wake_ena bled

tPCH03_Min : 10 ms

tPCH18_Min : 95 ms

tPLT02_Max : 90 ms

+1.05V_VCCST_Must_be_ON_anytime_VCC IN_AUX_is_ON

Min : 0 ms

tCPU01_Min : 1 ms

tCPU00_Min : 2 ms

tCPU16_Min : 0 ns

HONORED

G3->S0

S0->

S0iX

->S0

S0->S5

VCCST_Can_be_On_until_VC CINAUX_goes_L OW

VCCST and VCCSTG may remain powered duri ng Sx power states for Debug support and platform VR optimization.

Stabl e

HONORED Will_Track_V CCST_Rail

+3VL_RTC

SOC_RTCRST#

+3VALW_DS W

PCH_DPWROK

PM_BATLOW#

SLP_SUS#

+5VALW

EXT_PWR_GATE#

+3V_PRIM

+1.8V_ PRIM

+VCCIN_AUX

+1.05VO_OUT_PCH

+1.05V O_VNNBYPASS

+1.05VO_E XTBYPASS

EC_RSMRST#

ESPI_RST#

AC_PRESENT_R

+1.05V_VCCST

+1.05VO_VCCPLL

PBTN_OUT#

PM_SLP_S5 #

PM_SLP_S4 #

PM_SLP_S3 #

PM_SLP_S0 #

CPU_C10_GATE#

VCCST_OVERRIDE

+2.5V

+1.2V_VDDQ

+1.2V_VCCPLL_ OC

+1.05VS_VCCST G

VCCSTPWRGOOD_ TGSS

EC_VCCST_PG

DDR_PG_CTRL

+0.6VS_VT T

VR_ON

+VCCIN

VR_PWRGD

PCH_PWROK

+1.05V_VCCIO_OUT

PCH_CLK_OUTPUTS

H_PROCPWRGD

SYS_PWROK

SOC_PLTRST#

H_THERMTRIP#

5

4

Security Classification Compal Secret Data

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2019/05/15 2020/05/15

2

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Power Sequence

Size

Document Number Re v

Document Number Rev

LA-LJ551PR02

Date: Sheet of

1

5 67Thursday, August 22, 2019

0.2

A

www.forums-fastunlock.com

1 1

<eDP>

2 2

HDMI DDC (Port 2)

From eDP

From PD From HDMI

EDP_VDDEN: 100K PD on load swith side

3 3

EDP_TXN 034 EDP_TXP 034 EDP_TXN 134 EDP_TXP 134 EDP_TXN 234 EDP_TXP 234 EDP_TXN 334 EDP_TXP 334

EDP_AUX N34 EDP_AUX P34

CPU_DP2 _CTRL_CLK36 CPU_DP2 _CTRL_DATA36

EDP_HPD34

TCP0_PD _HPD37 CPU_DP2 _HPD36 USB_OC1 #45

PCH_ENV DD34 ENBKL41 INVPWM34

T303

T306

T301

TP@

SOC_GPP _A18

1

USB_OC1 # USB_OC2 # SOC_GPP _E17

1

ENBKL

RSVD_1

DISP_UTILS

1

DISP_RCOM P

12

RC350 150_040 2_1%

B

UC1A

Y5

DDIA_TXN_0

Y3

DDIA_TXP_0

Y1

DDIA_TXN_1

Y2

DDIA_TXP_1

V2

DDIA_TXN_2

V1

DDIA_TXP_2

V3

DDIA_TXN_3

V5

DDIA_TXP_3

W4

DDIA_AUX_N

W3

DDIA_AUX_P

AE3

DDIB_TXN_0

AE5

DDIB_TXP_0

AE2

DDIB_TXN_1

AE1

DDIB_TXP_1

AC5

DDIB_TXN_2

AC3

DDIB_TXP_2

AC1

DDIB_TXN_3

AC2

DDIB_TXP_3

AD3

DDIB_AUX_N

AD4

DDIB_AUX_P

DP15

GPP_E22/DDPA_CTRLCLK/PCIE_LNK_DOWN

DJ17

GPP_E23/DDPA_CTRLDATA/BK4/SBK4

DL40

GPP_H16/DDPB_CTRLCLK

DP42

GPP_H17/DDPB_CTRLDATA

DL17

GPP_E18/DDP1_CTRLCLK/TBT_LSX0_TXD

DK17

GPP_E19/DDP1_CTRLDATA/TBT_LSX0_RXD

DN17

GPP_E20/DDP2_CTRLCLK/TBT_LSX1_TXD

DP17

GPP_E21/DDP2_CTRLDATA/TBT_LSX1_RXD

DK34

GPP_D9/ISH_SPI_CS_N/DDP3_CTRLCLK/GSPI2_CS0_N/TBT_LSX2_TXD

DL34

GPP_D10/ISH_SPI_CLK/DDP3_CTRLDATA/GSPI2_CLK/TBT_LSX2_RXD

DN33

GPP_D11/ISH_SPI_MISO/DDP4_CTRLCLK/GSPI2_MISO/TBT_LSX3_TXD

DL33

GPP_D12/ISH_SPI_MOSI/DDP4_CTRLDATA/GSPI2_MOSI/TBT_LSX3_RXD

DW11

GPP_E14/DPPE_HPDA/DISP_MISCA

CV42

GPP_A18/DDSP_HPDB/DISP_MISCB

CV39

GPP_A19/DDSP_HPD1/DISP_MISC1

CY43

GPP_A20/DDSP_HPD2/DISP_MISC2

CR41

GPP_A14/USB_OC1_N/DDSP_HPD3/DISP_MISC3

CT41

GPP_A15/USB_OC2_N/DDSP_HPD4/DISP_MISC4

DV14

GPP_E17

DN21

EDP_VDDEN

DL19

EDP_BKLTEN

DU19

EDP_BKLTCTL

J3

RSVD_1

D2

DISP_UTILS

R2

DISP_RCOMP

ICL-U_BGA1 526

@

DDI

1 0f 19

C

GPP_A21 GPP_A22

BB5 BB6 AV6 AV5 BH2 BH1 BF1 BF2

AY5 AY6

AR5 AR6 AL5 AL3 BD2 BD1 BB1 BB2

AN3 AN5

BF6 BF5 BJ5 BJ6 BL1 BL2 BM2 BM1

BG6 BG5

BP6 BP5 BV5 BV6 BR1 BR2 BT2 BT1

BT6 BT5

AY1 AY2

CT38 CV43 CV41

TC_RCOM P_N TC_RCOM P_P

TBT / USB / DP

GPP_A17/DISP_MISCC

TCP0_TX_N0 TCP0_TX_P0 TCP0_TX_N1

TCP0_TX_P1 TCP0_TXRX_N0 TCP0_TXRX_P0 TCP0_TXRX_N1 TCP0_TXRX_P1

TCP0_AUX_N TCP0_AUX_P

TCP1_TX_N0

TCP1_TX_P0

TCP1_TX_N1

TCP1_TX_P1 TCP1_TXRX_N0 TCP1_TXRX_P0 TCP1_TXRX_N1 TCP1_TXRX_P1

TCP1_AUX_N TCP1_AUX_P

TCP2_TX_N0

TCP2_TX_P0

TCP2_TX_N1

TCP2_TX_P1 TCP2_TXRX_N0 TCP2_TXRX_P0 TCP2_TXRX_N1 TCP2_TXRX_P1

TCP2_AUX_N TCP2_AUX_P

TCP3_TX_N0

TCP3_TX_P0

TCP3_TX_N1

TCP3_TX_P1 TCP3_TXRX_N0 TCP3_TXRX_P0 TCP3_TXRX_N1 TCP3_TXRX_P1

TCP3_AUX_N TCP3_AUX_P

TC_RCOMP_N TC_RCOMP_P

D

TCP0_TT X_DRX_N1 37

TCP0_TT X_DRX_P1 37

TCP0_TT X_DRX_N2 37

TCP0_TT X_DRX_P2 37

TCP0_TR X_DTX_N1 37

TCP0_TR X_DTX_P1 37

TCP0_TR X_DTX_N2 37

TCP0_TR X_DTX_P2 37

TCP0_AU X_N 37

TCP0_AU X_P 37

CPU_DP2 _N0 36 CPU_DP2 _P0 36 CPU_DP2 _N1 36 CPU_DP2 _P1 36 CPU_DP2 _N2 36 CPU_DP2 _P2 36 CPU_DP2 _N3 36 CPU_DP2 _P3 36

1 2

RC351 150_040 2_1%

E

<TYPE-C> (USB3.1+ DP)

<HDMI>

RSVD _1: Follow 573129_ICL_U_DD R4_SODIMM_HW_SCH_ RN

1 2

RC348 100K_04 02_5%

1 2

RC422 100K_04 02_5%

+3VALW

1 2

RC164 10K_040 2_5%

1 2

4 4

RC165 10K_040 2_5%

A

USB_OC1 # USB_OC2 #

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

RSVD_1

ENBKL

Compal Secret Data

2019/05/ 15 2020/05/ 15

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Date : Sheet of

D

Date : Sheet of

Compal Electronics, Inc.

ICL-U(1/14)DDI,EDP

LA-LJ551PR02

6 67Thursday, August 2 2, 2019

E

0.2

A

www.forums-fastunlock.com

+1.05VS_VCCSTG_OUT_L GC

1 2

RC562

0_0402_5%

RC515 0_0201_5%@

RC514 0_0402_5%@

12

RC6 1K_0402_5%

1 2

RC7 499_0402_1%

+3VALW

12

RC371 100K_0402_5%

1 2

CATERR#

H_THERMTRIP#

ref 573129 RVP

EC_SLP_S0IX# SOC_GPP_H2

PROC_POPIRCOMP PCH_OPIRCOMP

1 1

H_PROCHOT#41

2 2

VCCIN_AUX_CORE_ALERT#_R17

VR_ALERT#37

TS_DISABLE#34,41

TS_EN#34,41

3 3

+1.05V_VCCST

+3VALW

H_PROCHOT# H_PROCHOT#_R

1 2

RC11 49.9_0402_1%

1 2

RC12 1K_0402_5%

1 2

RC370 100K_0402_5%

1 2

RC389 2.2K_0402_5%@

1 2

RC366 49.9_0402_1%

1 2

RC365 49.9_0402_1%

B

H_PECI41

TP_INT#41 ,42

DC10

1 2

RB751V-40_SOD323-2

SCS00000Z00

H_PROCHOT#

TS_DISABLE#_R

SOC_TS_EN#

EC_SLP_S0I X# JTAG ODT DISABLE NO INTERNAL PU/PD HIGH: JTAG ODT ENABLED LOW: JTAG ODT DISABLED

GPP_H2 MAF/SAF STRAP INTERNAL PD 20K HIGH: Slave Attached Flash Sharing (SAFS) is enabled. LOW: Master Attached Flash Sharing (MAFS) is enabled. (Default)

CATERR#

H_THERMTRIP#

PROC_POPIRCOMP PCH_OPIRCOMP

XDP_ITP_PMODE

SOC_TS_EN#

TS_DISABLE#_R

EC_SLP_S0IX# SOC_GPP_H2

UC1D

J4

CATERR#

CD5

PECI

C3

PROCHOT#

E3

THRMTRIP#

CJ41

PROC_POPIRCOMP

DU3

PCH_OPIRCOMP

A14

RSVD_25

B14

RSVD_26

DL15

DBG_PMODE

DV11

GPP_E3/CPU_GP0

DT11

GPP_E7/CPU_GP1

CR38

GPP_B3/CPU_GP2

CR39

GPP_B4/CPU_GP3

DT12

GPP_E6

DJ38

GPP_H2/CNV_BT_I2S_SDO

DL38

GPP_H19/TIME_SYNC0

ICL-U_BGA1526

@

C

JTAG

PROC_PRDY# PROC_PREQ#

4 of 19

PROC_TCK

PROC_TDI PROC_TDO PROC_TMS

PROC_TRST#

PCH_TRST#

PCH_TCK

PCH_TDI PCH_TDO PCH_TMS

PCH_JTAGX

D

check XDP /DCI

P3 K5 K3 P4 N1

N5 R5 K1 K2 N3 N2

P6 M6

SOC_XDP_TCK0 SOC_XDP_TDI SOC_XDP_TDO SOC_XDP_TMS SOC_XDP_TRST#

SOC_XDP_TRST# PCH_JTAG_TCK1

SOC_XDP_TDI

SOC_XDP_TDO SOC_XDP_TMS SOC_XDP_TCK0

XDP_PRDY# XDP_PREQ#

< PU/PD for DCI Debug >

SOC_XDP_TMS

SOC_XDP_TDI

SOC_XDP_TDO

XDP_PREQ#

T497TP@ T2TP@

SOC_XDP_TCK0

PCH_JTAG_TCK1

SOC_XDP_TRST#

+1.05VO_OUT_FET

RC18 1K_0402_5%@

RC19 1K_0402_5%@

XDP_ITP_PM ODE DFX TEST MODE INTERNAL PD 20K HIGH: DFX TEST MODE DISABLED(DEFAULT) LOW: DFX TES TMODE ENABLED

RC13 51_0402_5%@

RC14 51_0402_5%@

RC15 51_0402_5%DCI@

RC17 51_0402_5%@

RC20 51_0402_5%DCI@

RC22 51_0402_5%@

RC21 51_0402_5%@

1 2

E

+1.05VS_VCCSTG_OUT_L GC

XDP_ITP_PMODE

4 4

Security Classification

2019/05/15 2020/05/15

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2019/05/15 2020/05/15

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

Document Number Re v

Date : Sheet o f

D

Date : Sheet o f

Compal Electronics, Inc.

ICL-U(1/14)DDI,MSIC,XDP

LA-LJ551PR02

7 67Thursday, August 22, 2019

E

0.2

5

www.forums-fastunlock.com

4

3

2

1

Follow Intel DDR4 NIL

DDR4: Refer to 575034_ICL_U42_DDR4_T3_6L_Core_Schematics_Rev0p7

D D

DDR_A_D[0..15]22

DDR_A_D[16..31]22

DDR_A_D[32..47]22

C C

DDR_A_D[48..63]22

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

SM_RCOMP0

12

RC25100_0402_1%

SM_RCOMP1

12

RC26100_0402_1%

SM_RCOMP2

12

RC27100_0402_1%

UC1B

LP4(NIL) / DDR4(NIL) LP4(NIL) / DDR4(NIL)

CA48

DDRA_DQ0_0/DDR0_DQ0_0

CA47

DDRA_DQ0_1/DDR0_DQ0_1

CA49

DDRA_DQ0_2/DDR0_DQ0_2

BV49

DDRA_DQ0_3/DDR0_DQ0_3

CA45

DDRA_DQ0_4/DDR0_DQ0_4

BV47

DDRA_DQ0_5/DDR0_DQ0_5

BV45

DDRA_DQ0_6/DDR0_DQ0_6

BV48

DDRA_DQ0_7/DDR0_DQ0_7

CC42

DDRA_DQ1_0/DDR0_DQ1_0

CC39

DDRA_DQ1_1/DDR0_DQ1_1

CC43

DDRA_DQ1_2/DDR0_DQ1_2

CE38

DDRA_DQ1_3/DDR0_DQ1_3

CC38

DDRA_DQ1_4/DDR0_DQ1_4

CE39

DDRA_DQ1_5/DDR0_DQ1_5

CE42

DDRA_DQ1_6/DDR0_DQ1_6

CE43

DDRA_DQ1_7/DDR0_DQ1_7

BT48

DDRA_DQ2_0/DDR0_DQ2_0

BT47

DDRA_DQ2_1/DDR0_DQ2_1

BT49

DDRA_DQ2_2/DDR0_DQ2_2

BN49

DDRA_DQ2_3/DDR0_DQ2_3

BT45

DDRA_DQ2_4/DDR0_DQ2_4

BN47

DDRA_DQ2_5/DDR0_DQ2_5

BN45

DDRA_DQ2_6/DDR0_DQ2_6

BN48

DDRA_DQ2_7/DDR0_DQ2_7

BV42

DDRA_DQ3_0/DDR0_DQ3_0

BV39

DDRA_DQ3_1/DDR0_DQ3_1

BV43

DDRA_DQ3_2/DDR0_DQ3_2

BW38

DDRA_DQ3_3/DDR0_DQ3_3

BV38

DDRA_DQ3_4/DDR0_DQ3_4

BW39

DDRA_DQ3_5/DDR0_DQ3_5

BW42

DDRA_DQ3_6/DDR0_DQ3_6

BW43

DDRA_DQ3_7/DDR0_DQ3_7

AY48

DDRB_DQ0_0/DDR0_DQ4_0

AY47

DDRB_DQ0_1/DDR0_DQ4_1

AY49

DDRB_DQ0_2/DDR0_DQ4_2

AU45

DDRB_DQ0_3/DDR0_DQ4_3

AY45

DDRB_DQ0_4/DDR0_DQ4_4

AU47

DDRB_DQ0_5/DDR0_DQ4_5

AU48

DDRB_DQ0_6/DDR0_DQ4_6

AU49

DDRB_DQ0_7/DDR0_DQ4_7

AY42

DDRB_DQ1_0/DDR0_DQ5_0

AY38

DDRB_DQ1_1/DDR0_DQ5_1

AY43

DDRB_DQ1_2/DDR0_DQ5_2

BB39

DDRB_DQ1_3/DDR0_DQ5_3

AY39

DDRB_DQ1_4/DDR0_DQ5_4

BB38

DDRB_DQ1_5/DDR0_DQ5_5

BB42

DDRB_DQ1_6/DDR0_DQ5_6

BB43

DDRB_DQ1_7/DDR0_DQ5_7

AR48

DDRB_DQ2_0/DDR0_DQ6_0

AR47

DDRB_DQ2_1/DDR0_DQ6_1

AR49

DDRB_DQ2_2/DDR0_DQ6_2

AM45

DDRB_DQ2_3/DDR0_DQ6_3

AR45

DDRB_DQ2_4/DDR0_DQ6_4

AM47

DDRB_DQ2_5/DDR0_DQ6_5

AM48

DDRB_DQ2_6/DDR0_DQ6_6

AM49

DDRB_DQ2_7/DDR0_DQ6_7

AT42

DDRB_DQ3_0/DDR0_DQ7_0

AT39

DDRB_DQ3_1/DDR0_DQ7_1

AR43

DDRB_DQ3_2/DDR0_DQ7_2

AT38

DDRB_DQ3_3/DDR0_DQ7_3

AR38

DDRB_DQ3_4/DDR0_DQ7_4

AR39

DDRB_DQ3_5/DDR0_DQ7_5

AR42

DDRB_DQ3_6/DDR0_DQ7_6

AT43

DDRB_DQ3_7/DDR0_DQ7_7

D47

DDR_RCOMP_0

E46

DDR_RCOMP_1

C47

DDR_RCOMP_2

ICL-U_BGA1526

@

2 of 19

DDRA_CLK_N/DDR0_CLK_N_0

DDRA_CLK_P/DDR0_CLK_P_0

DDRB_CLK_N/DDR0_CLK_N_1

DDRB_CLK_P/DDR0_CLK_P_1

DDRA_CKE0/DDR0_CKE0

DDRA_CKE1/NC DDRB_CKE0/NC

DDRB_CKE1/DDR0_CKE1

DDRA_CS_0/DDR0_CS#0

DDRA_CS_1/NC DDRB_CS_0/NC

DDRB_CS_1/DDR0_CS#1

DDRB_CA4/DDR0_BA0

NC/DDR0_BA1

DDRA_CA5/DDR0_BG0

NC/DDR0_BG1

NC/DDR0_MA0 NC/DDR0_MA1

DDRB_CA5/DDR0_MA2

NC/DDR0_MA3

NC/DDR0_MA4 DDRA_CA0/DDR0_MA5 DDRA_CA2/DDR0_MA6 DDRA_CA4/DDR0_MA7 DDRA_CA3/DDR0_MA8 DDRA_CA1/DDR0_MA9

NC/DDR0_MA10 NC/DDR0_MA11 NC/DDR0_MA12

DDRB_CA0/DDR0_MA13

DDRB_CA2/DDR0_MA14WE# DDRB_CA1/DDR0_MA15CAS# DDRB_CA3/DDR0_MA16RAS#

NC/DDR0_ODT_0 NC/DDR0_ODT_1

DDRA_DQSN_0/DDR0_DQSN_0 DDRA_DQSP_0/DDR0_DQSP_0 DDRA_DQSN_1/DDR0_DQSN_1 DDRA_DQSP_1/DDR0_DQSP_1 DDRA_DQSN_2/DDR0_DQSN_2 DDRA_DQSP_2/DDR0_DQSP_2 DDRA_DQSN_3/DDR0_DQSN_3 DDRA_DQSP_3/DDR0_DQSP_3 DDRB_DQSN_0/DDR0_DQSN_4 DDRB_DQSP_0/DDR0_DQSP_4 DDRB_DQSN_1/DDR0_DQSN_5

DDRB_DQSP_1/DDR0_DQSP_5 DDRB_DQSN_2/DDR0_DQSN_6 DDRB_DQSP_2/DDR0_DQSP_6 DDRB_DQSN_3/DDR0_DQSN_7 DDRB_DQSP_3/DDR0_DQSP_7

NC/DDR0_PAR

NC/DDR0_ACT#

NC/DDR0_ALERT#

RSVD_73 DDR0_VREF_CA DDR1_VREF_CA

DDR_VTT_CTL

DRAM_RESET#

BL48 BL47 BF42 BF43

BG49 BJ47 BF38 BF41

BM38 BM42 BP42 BG42

BM43 BG39

BB49 BD47

BB48 BL49 BG38 BL45 BJ46 BG48 BE45 BG45 BG47 BE47 BJ38 BB47 BE48 BM39 BG43 BJ42 BM41

BJ39 BB45

BY47 BY46 CC41 CE41 BR47 BR46 BV41 BW41 AV46 AV47 AY41 BB41 AN46 AN47 AR41 AT41

BF39 BE49 BD46

M38 C44 B45 M39 DK47

DDR_PG_CTRL DDR_DRAMRST#

1

DDR_A_CLK#0 22 DDR_A_CLK0 22

DDR_A_CKE0 22

DDR_A_CS#0 22

DDR_A_BA0 22 DDR_A_BA1 22

DDR_A_BG0 22 DDR_A_BG1 22

DDR_A_MA0 22 DDR_A_MA1 22 DDR_A_MA2 22 DDR_A_MA3 22 DDR_A_MA4 22 DDR_A_MA5 22 DDR_A_MA6 22 DDR_A_MA7 22 DDR_A_MA8 22 DDR_A_MA9 22 DDR_A_MA10 22 DDR_A_MA11 22 DDR_A_MA12 22 DDR_A_MA13 22 DDR_A_MA14_WE# 22 DDR_A_MA15_CAS# 22 DDR_A_MA16_RAS# 22

DDR_A_ODT0 22

DDR_A_DQS#0 22 DDR_A_DQS0 22 DDR_A_DQS#1 22 DDR_A_DQS1 22 DDR_A_DQS#2 22 DDR_A_DQS2 22 DDR_A_DQS#3 22 DDR_A_DQS3 22 DDR_A_DQS#4 22 DDR_A_DQS4 22 DDR_A_DQS#5 22 DDR_A_DQS5 22 DDR_A_DQS#6 22 DDR_A_DQS6 22 DDR_A_DQS#7 22 DDR_A_DQS7 22

DDR_A_PAR 22 DDR_A_ACT# 22

DDR_A_ALERT# 22

T244TP@

+0.6V_A_VREFCA 22 +0.6V_B_VREFCA 24

DDR_DRAMRST# 22

DDR_B_D[0..15]24

DDR_B_D[16..31]24

DDR_B_D[32..47]24

DDR_B_D[48..63]24

Trace width/Spacing >= 20mils

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

UC1C

LP4(NIL) / DDR4(NIL)

AK48

DDRC_DQ0_0/DDR1_DQ0_0

AK45

DDRC_DQ0_1/DDR1_DQ0_1

AK49

DDRC_DQ0_2/DDR1_DQ0_2

AG47

DDRC_DQ0_3/DDR1_DQ0_3

AK47

DDRC_DQ0_4/DDR1_DQ0_4

AG45

DDRC_DQ0_5/DDR1_DQ0_5

AG48

DDRC_DQ0_6/DDR1_DQ0_6

AG49

DDRC_DQ0_7/DDR1_DQ0_7

AJ38

DDRC_DQ1_0/DDR1_DQ1_0

AL39

DDRC_DQ1_1/DDR1_DQ1_1

AJ39

DDRC_DQ1_2/DDR1_DQ1_2

AL43

DDRC_DQ1_3/DDR1_DQ1_3

AL38

DDRC_DQ1_4/DDR1_DQ1_4

AJ42

DDRC_DQ1_5/DDR1_DQ1_5

AL42

DDRC_DQ1_6/DDR1_DQ1_6

AJ43

DDRC_DQ1_7/DDR1_DQ1_7

AB49

DDRC_DQ2_0/DDR1_DQ2_0

AB48

DDRC_DQ2_1/DDR1_DQ2_1

AE49

DDRC_DQ2_2/DDR1_DQ2_2

AE47

DDRC_DQ2_3/DDR1_DQ2_3

AE48

DDRC_DQ2_4/DDR1_DQ2_4

AB47

DDRC_DQ2_5/DDR1_DQ2_5

AB45

DDRC_DQ2_6/DDR1_DQ2_6

AE45

DDRC_DQ2_7/DDR1_DQ2_7

AD38

DDRC_DQ3_0/DDR1_DQ3_0

AD39

DDRC_DQ3_1/DDR1_DQ3_1

AE39

DDRC_DQ3_2/DDR1_DQ3_2

AE43

DDRC_DQ3_3/DDR1_DQ3_3

AE38

DDRC_DQ3_4/DDR1_DQ3_4

AD43

DDRC_DQ3_5/DDR1_DQ3_5

AD42

DDRC_DQ3_6/DDR1_DQ3_6

AE42

DDRC_DQ3_7/DDR1_DQ3_7

J48

DDRD_DQ0_0/DDR1_DQ4_0

J45

DDRD_DQ0_1/DDR1_DQ4_1

J49

DDRD_DQ0_2/DDR1_DQ4_2

G47

DDRD_DQ0_3/DDR1_DQ4_3

J47

DDRD_DQ0_4/DDR1_DQ4_4

G45

DDRD_DQ0_5/DDR1_DQ4_5

G48

DDRD_DQ0_6/DDR1_DQ4_6

E48

DDRD_DQ0_7/DDR1_DQ4_7

J38

DDRD_DQ1_0/DDR1_DQ5_0

G39

DDRD_DQ1_1/DDR1_DQ5_1

G38

DDRD_DQ1_2/DDR1_DQ5_2

G42

DDRD_DQ1_3/DDR1_DQ5_3

J39

DDRD_DQ1_4/DDR1_DQ5_4

J42

DDRD_DQ1_5/DDR1_DQ5_5

G43

DDRD_DQ1_6/DDR1_DQ5_6

J43

DDRD_DQ1_7/DDR1_DQ5_7

B43

DDRD_DQ2_0/DDR1_DQ6_0

D43

DDRD_DQ2_1/DDR1_DQ6_1

A43

DDRD_DQ2_2/DDR1_DQ6_2

C40

DDRD_DQ2_3/DDR1_DQ6_3

C43

DDRD_DQ2_4/DDR1_DQ6_4

D40

DDRD_DQ2_5/DDR1_DQ6_5

B40

DDRD_DQ2_6/DDR1_DQ6_6

A40

DDRD_DQ2_7/DDR1_DQ6_7

B35

DDRD_DQ3_0/DDR1_DQ7_0

D35

DDRD_DQ3_1/DDR1_DQ7_1

A35

DDRD_DQ3_2/DDR1_DQ7_2

D38

DDRD_DQ3_3/DDR1_DQ7_3

C35

DDRD_DQ3_4/DDR1_DQ7_4

C38

DDRD_DQ3_5/DDR1_DQ7_5

B38

DDRD_DQ3_6/DDR1_DQ7_6

A38

DDRD_DQ3_7/DDR1_DQ7_7

ICL-U_BGA1526

@

DDRC_CLK_N/DDR1_CLK_N_0 DDRC_CLK_P/DDR1_CLK_P_0 DDRD_CLK_N/DDR1_CLK_N_1 DDRD_CLK_P/DDR1_CLK_P_1

DDRC_CKE0/DDR1_CKE0

DDRD_CKE1/DDR1_CKE1

DDRC_CS_0/DDR1_CS#0

DDRD_CS_1/DDR1_CS#1

DDRD_CA2/DDR1_MA14WE# DDRD_CA1/DDR1_MA15CAS# DDRD_CA3/DDR1_MA16RAS#

DDRC_DQSN_0/DDR1_DQSN_0 DDRC_DQSP_0/DDR1_DQSP_0 DDRC_DQSN_1/DDR1_DQSN_1 DDRC_DQSP_1/DDR1_DQSP_1 DDRC_DQSN_2/DDR1_DQSN_2 DDRC_DQSP_2/DDR1_DQSP_2 DDRC_DQSN_3/DDR1_DQSN_3 DDRC_DQSP_3/DDR1_DQSP_3 DDRD_DQSN_0/DDR1_DQSN_4 DDRD_DQSP_0/DDR1_DQSP_4 DDRD_DQSN_1/DDR1_DQSN_5 DDRD_DQSP_1/DDR1_DQSP_5 DDRD_DQSN_2/DDR1_DQSN_6 DDRD_DQSP_2/DDR1_DQSP_6 DDRD_DQSN_3/DDR1_DQSN_7 DDRD_DQSP_3/DDR1_DQSP_7

3 of 19

LP4(NIL) / DDR4(NIL)

DDRC_CKE1/NC DDRD_CKE0/NC

DDRC_CS_1/NC DDRD_CS_0/NC

DDRD_CA4/DDR1_BA0

NC/DDR1_BA1

DDRC_CA5/DDR1_BG0

NC/DDR1_BG1

NC/DDR1_MA0 NC/DDR1_MA1

DDRD_CA5/DDR1_MA2

NC/DDR1_MA3

NC/DDR1_MA4 DDRC_CA0/DDR1_MA5 DDRC_CA2/DDR1_MA6 DDRC_CA4/DDR1_MA7 DDRC_CA3/DDR1_MA8 DDRC_CA1/DDR1_MA9

NC/DDR1_MA10 NC/DDR1_MA11

NC/DDR1_MA12

DDRD_CA0/DDR1_MA13

NC/DDR1_ODT_0 NC/DDR1_ODT_1

NC/DDR1_PAR

NC/DDR1_ACT#

NC/DDR1_ALERT#

Y48 Y47 M43 M42

U45 V46 M41 P43

V42 V39 Y39 T39

T38 T42

R45 N47

P42 Y49 U48 Y45 U47 R49 U49 M47 M45 R47 P39 N46 R48 Y41 V41 Y42 V47

V43 V38

AH46 AH47 AJ41 AL41 AC47 AC46 AE41 AD41 H47 H46 G41 J41 C42 D42 D36 C36

P38 M48 M49

DDR_B_CLK#0 24 DDR_B_CLK0 24

DDR_B_CKE0 24

DDR_B_CS#0 24

DDR_B_BA0 24 DDR_B_BA1 24

DDR_B_BG0 24 DDR_B_BG1 24

DDR_B_MA0 24 DDR_B_MA1 24 DDR_B_MA2 24 DDR_B_MA3 24 DDR_B_MA4 24 DDR_B_MA5 24 DDR_B_MA6 24 DDR_B_MA7 24 DDR_B_MA8 24 DDR_B_MA9 24 DDR_B_MA10 24 DDR_B_MA11 24 DDR_B_MA12 24 DDR_B_MA13 24 DDR_B_MA14_WE# 24 DDR_B_MA15_CAS# 24 DDR_B_MA16_RAS# 24

DDR_B_ODT0 24

DDR_B_DQS#0 24 DDR_B_DQS0 24 DDR_B_DQS#1 24 DDR_B_DQS1 24 DDR_B_DQS#2 24 DDR_B_DQS2 24 DDR_B_DQS#3 24 DDR_B_DQS3 24 DDR_B_DQS#4 24 DDR_B_DQS4 24 DDR_B_DQS#5 24 DDR_B_DQS5 24 DDR_B_DQS#6 24 DDR_B_DQS6 24 DDR_B_DQS#7 24 DDR_B_DQS7 24

DDR_B_PAR 24 DDR_B_ACT# 24

DDR_B_ALERT# 24

B B

Buffer with Open Drai n Output

For VTT power control

12

CC6 0.1U_0201_10V6K

UC3

DDR_PG_CTRL

A A

5

4

NC1VCC

2

A

3

GND

74AUP1G07GW_TSSOP5

SA00005U600

+1.2V

+3VS

12

RC28

5

100K_0402_5%

4

Y

DDR_VTT_PG_CTRL 54

3

DDR_DRAMRST#

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+1.2V

12

RC30 470_0402_5%

1

CC9 100P_0402_50V8J

ESD@

2

ESD

Compal Secret Data

2019/05/15 2020/05/15

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

ICL-U(3/14)DDR4

Size

Document Number Re v

LA-LJ551PR02

Date : Sheet o f

1

8 67Thursday, August 22, 2019

0.2

5

www.forums-fastunlock.com

D D

SPI ROM

+3VALW

1 2

RC37 100K_04 02_5%

1 2

RC38 100K_04 02_5%

1 2

RC39 100K_04 02_5%

SOC_SPI_0_SO BOOT HALT NO INTERNAL PU/PD HIGH: DISABLE LOW: ENABLE

C C

SOC_SPI_0_IO2 CONSENT STRAP NO INTERNAL PU/PD HIGH: DISABLE LOW: ENABLE

SOC_SPI_0 _SI SOC_SPI_0 _IO2 SOC_SPI_0 _IO3

SOC_SPI_0_IO3 A0 PERSONALITY STRAP NO INTERNAL PU/PD HIGH: DISABLE LOW: ENABLE

4

SOC_SPI_0 _CLK SOC_SPI_0 _SI SOC_SPI_0 _SO SOC_SPI_0 _IO2 SOC_SPI_0 _IO3 SOC_SPI_0 _CS#0

UC1E

DB42

SPI0_CLK

DD43

SPI0_MOSI

DF43

SPI0_MISO

DF42

SPI0_IO2

DD41

SPI0_IO3

DB43

SPI0_CS0#

DF41

SPI0_CS1#

DB41

SPI0_CS2#

DV16

GPP_E11/SPI1_CLK/BK1/SBK1

DT16

GPP_E13/SPI1_MOSI/BK3/SBK3

DU18

GPP_E12/SPI1_MISO/BK2/SBK2

DT18

GPP_E1/SPI1_IO2

DW18

GPP_E2/SPI1_IO3

DW16

GPP_E10/SPI1_CS_N/BK0/SBK0

DU16

GPP_E8/SATALED#/SPI1_CS1#

DV19

CL_CLK

DW19

CL_DATA

DT19

CL_RST#

ICL-U_BGA1 526

@

3

SMBUS

SPI 0

SML 0

GPP_C6/SML1CLK/SUSWARN_N/SUSPWRDNACK

SPI 1

MLINK

SML1

eSPI

5 of 19

GPP_C7/SML1DATA/SUSACK#

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

GPP_A5/ESPI_CLK

GPP_A0/ESPI_IO0 GPP_A1/ESPI_IO1 GPP_A2/ESPI_IO2 GPP_A3/ESPI_IO3

GPP_A4/ESPI_CS#

GPP_A6/ESPI_RESET#

DK27 DP24 DL24

DK24 DJ24 DP22

DN22 DL22

CR47 CN45 CN48 CN49 CN47 CT45 CR46

2

GPP_C2 TLS CONFIDENTIALITY INTERNAL PD 20K HIGH: TLS CONFIDENTIALITY ENABLE LOW: TLS CONFIDENTIALITY DISABLE

SOC_SML0ALERT# ESPI OR EC LESS INTERNAL PD 20K HIGH: ESPI DISABLE LOW: ESPI ENABLE (Default)

SOC_SMB CLK SOC_SMB DATA SOC_GPP _C2

SOC_SML 0CLK SOC_SML 0DATA SOC_SML 0ALERT#

PD_SMB_ CK PD_SMB_ DA

ESPI_CLK ESPI_IO0 ESPI_IO1 ESPI_IO2 ESPI_IO3 ESPI_CS# ESPI_RST#

1

1 2

RC34 49 .9_0402_1%EMI@

1 2

RC32 10 _0402_1%

1 2

RC33 10 _0402_1%

1 2

RC35 10 _0402_1%

1 2

RC36 10 _0402_1%

ESPI_CS# 41 ESPI_RST# 41

T9

TP@

PD_SMB_ CK 37 PD_SMB_ DA 37

SOC_GPP _C2

1

+3VALW

1 2

RC86 4.7 K_0402_5%

SML1

(Link to GPU,EC,Thermal Sensor,PD)

ESPI_CLK_ R 41 ESPI_IO0_R 41 ESPI_IO1_R 41 ESPI_IO2_R 41 ESPI_IO3_R 41

ESP I Foll ow 57290 7_IC L_U Y_P DG

To EC

+3VALW

PD_SMB_ CK PD_SMB_ DA

1 2

close to SPI ROM

SOC_SPI_0 _SO SOC_SPI_0 _CLK SOC_SPI_0 _SI

B B

From SOC

SOC_SPI_0 _IO3

SOC_SPI_0 _IO2

< SPI ROM - 16M >

SOC_SPI_0 _CS#0 SOC_SPI_0 _SO_R SOC_SPI_0 _IO3_R

A A

5

1 2 3 4

1 2

RC2 49.9_0402_ 1%

1 2

RC3 49.9_0402_ 1%EMI@

1 2

RC4 49.9_0402_ 1%

1 2

RC5 49.9_0402_ 1%

1 2

RC1 49.9_0402_ 1%

+3VALW

UC2

CS# DO(IO1) IO2 GND

XM25QH1 28AHIG SOP 8P

SA0000B 8400

VCC

CLK

DI(IO0)

IO

8 7

SOC_SPI_0 _CLK_RSOC_SPI_0 _IO2_R

6

SOC_SPI_0 _SI_R

5

SOC_SPI_0 _SO_R SOC_SPI_0 _CLK_R SOC_SPI_0 _SI_R SOC_SPI_0 _IO3_R

SOC_SPI_0 _IO2_R

@

1 2

CC3 0.1U_020 1_10V6K

4

Follow 572907_ICL_UY_PDG for Glitch

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1 2 1 2

3

ESPI_CS#

RC44475K_040 2_5% @

SOC_SPI_0 _CLK

RC441100K_04 02_5%

ESPI_RST#

RC44375K_040 2_5% @

MAF - Master Attached Flash Single SPI Flash attached to SPI Bus EC FW access through eSPI Bus

Compal Secret Data

2019/05/ 15 2020/05/ 15

Compal Secret Data

Deciphered Date

2

SOC_SMB CLK SOC_SMB DATA

SOC_SML 0CLK SOC_SML 0DATA

Title

Size Document Number Re v

Date : Sheet of

1 2

RC381 1K_0402 _5%

1 2

RC382 1K_0402 _5%

+3VS

1 2

RC558 1K_0402 _5%

1 2

RC559 1K_0402 _5%

1 2

RC316 1K_0402 _5%

1 2

RC315 1K_0402 _5%

Compal Electronics, Inc.

ICL-U(3/12)SPI,ESPI,SMB,LPC

LA-LJ551PR02

9 67Thursday, August 2 2, 2019

1

0.2

5

www.forums-fastunlock.com

4

3

2

1

D D

HDA_SDIN040

CNV_RF_RESET#39

CLKREQ_CNV#39

C C

HDA_BIT_CLK HDA_SYNC HDA_SDOUT

HDA_RST#

CNV_RF_RESET#

< HD AUDIO >

12

@

HDA_BIT_CLK

HDA_SYNC

HDA_SDOUT

RC49 499_0402_1%

1 2

HDA_BIT_CLK_R40

HDA_SYNC_R40

HDA_SDOUT_R40

B B

RC46 33_0402_5%EMI@

1 2

RC48 33_0402_5%

1 2

RC47 33_0402_5%

UC1G

CY46

GPP_R0/HDA_BCLK/I2S0_SCLK

CV49

GPP_R1/HDA_SYNC/I2S0_SFRM

CY47

GPP_R2/HDA_SDO/I2S0_TXD

CV45

GPP_R3/HDA_SDI0/I2S0_RXD

DA47

GPP_R4/HDA_RST#

DP33

GPP_D19/I2S_MCLK

DC45

GPP_A23/I2S1_SCLK

DA49

GPP_R5/HDA_SDI1/I2S1_SFRM

DA45

GPP_R6/I2S1_TXD

DA48

GPP_R7/I2S1_RXD

CT49

GPP_A7/I2S2_SCLK

CT48

GPP_A8/I2S2_SFRM/CNV_RF_RESET#

CV47

GPP_A10/I2S2_RXD

CT47

GPP_A9/I2S2_TXD/MODEM_CLKREQ

CY39

GPP_S0/SNDW1_CLK

CY38

GPP_S1/SNDW1_DATA

DB39

GPP_S2/SNDW2_CLK

DD38

GPP_S3/SNDW2_DATA

DF38

GPP_S4/SNDW3_CLK/DMIC_CLK1

DD39

GPP_S5/SNDW3_DATA/DMIC_DATA1

ICL-U_BGA1526

@

RC307 75K_0402_5% RC448 100K_0402_5% RC449 33K_0402_5%

Follow 572907_ICL_UY_PDG for Glitch

1 2 1 2 1 2

Cost down plan

SD3.0

GPP_H1/SD_PWR_EN_N/CN V_BT_I2S_SDO

GPP_S6/SNDW4_CLK/DMIC_CLK0

GPP_S7/SNDW4_DATA/DMIC_DATA0

AUDIO

7 of 19

CNV_RF_RESET# HDA_BIT_CLK HDA_RST#

GPP_G6/SD_CLK GPP_G1/SD_DATA0 GPP_G2/SD_DATA1 GPP_G3/SD_DATA2 GPP_G4/SD_DATA3

GPP_G0/SD_CMD

GPP_G7/SD_WP

GPP_G5/SD_CD#

GPP_H0/CNV_BT_I2S_SDO

SD3_RCOMP

SNDW_RCOMP

CE46 CC48 CC49 CC47 CF45 CC45 CF49 CE47

DK38 DG38

CJ43

DG36 DG34

CV38

SD3_RCOMP

SOC_DMIC_CLK0 SOC_DMIC_DAT0

SNDW_RCOMP

1 2

RC358 200_0402_1%

SOC_DMIC_CLK0 3 4 SOC_DMIC_DAT0 34

1 2

RC359 200_0402_1%

To eDP

< To Enable ME Override >

1 2

ME_EN41

A A

5

RC51 0_0402_5%@

HDA_SDOUT

4

Security Classification

2019/05/15 2020/05/15

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2019/05/15 2020/05/15

3

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size

Document Number Re v

Date : Sheet o f

Compal Electronics, Inc.

ICL-U(4/12)HDA,SD

LA-LJ551PR02

10 67Thursday, August 22, 2019

1

0.2

5

www.forums-fastunlock.com

+3VS

1 2

RC523 10K_0402_5%DIS@

1 2

RC352 10K_0402_5%

1 2

RC353 10K_0402_5%

1 2

RC64 10K_0402_5 %

Remove, If PCB space not enough

1 2

RC524 10K_0402_5%@

1 2

RC68 10K_0402_5 %@

D D

Follow 573129_IC L_U_DD R4_SOD IMM_HW _SCH_R N & 572907_ICL_UY_PDG for Glitch

+3VALW

+3VL_RTC

C C

B B

1 2

RC553 100K_0402_5%S0iX@

1 2

RC394 100K_0402_5%

1 2

RC395 100K_0402_5%@

1 2

RC396 100K_0402_5%

1 2

RC397 100K_0402_5%

1 2

RC398 100K_0402_5%

1 2

RC399 100K_0402_5%

1 2

RC400 100K_0402_5%

RC428 10K_0402_5%

1 2

RC56 20K_0402_ 5%

1 2

CC13 1U_0201 _6.3V6M

1 2

CLRP1 SHORT PADS

1 2

RC58 20K_0402_ 5%

1 2

CC14 1U_0201 _6.3V6M

1 2

CLRP2 SHORT PADS

1 2

RC377 1M_0402_5%@

1 2

CC319 0.1 U_0201_10V6K@

RC427 10K_0402_5%

1 2

RC386 100K_0402_5%

1 2

RC78 10K_0402_5 %

CC20 100P_040 2_50V8J@ESD@

CC21 100P_040 2_50V8J@ESD@

CC22 100P_040 2_50V8J@ESD@

CC23 100P_040 2_50V8J@ESD@

VCCST_EN

VCCIN_AUX_CORE_VID0_R17,59

VCCIN_AUX_CORE_VID1_R17,59

EC_VCCST_EN41

+3VALW

A A

1 2 1 2 1 2

12

PM_SLP_S3#

PM_SLP_S4#

VCCST_OVERRIDE_LS

RC417100K_0402_ 5%

VCCST_OVERRIDE_N

RC418100K_0402_ 5%

VCCST_OVERRIDE_R

RC419100K_0402_ 5%

VCCST_OVERRIDE_R

5

CLKREQ_PEG#0 CLKREQ_PCIE#1 CLKREQ_PCIE#3 CLKREQ_PCIE#4

CLKREQ_PEG#0 CLKREQ_PCIE#4

PM_SLP_S0#

SLP_SUS# PM_SLP_S5# PM_SLP_S4# PM_SLP_S3#

PM_SLP_A# PM_SLP_LAN# PM_SLP_W LAN#

SYS_RESET#

SOC_SRTCRS T#

CLR ME

SOC_RTCRST #

CLR CMOS

SM_INTRUDER#

EC_RSMRST# PCH_PWR OK

SYS_RESET#

EC_RSMRST#

SYS_PWROK

SOC_PLTRST #

ESD

cost down plan

1 2

R345 0 _0402_5%@

D14

2

3

LRB715FT1G_ SOT323-3

SCS00008E0 0

1 2

R344 0 _0402_5%@

@

1 2

R342 0 _0402_5%

@

1 2

R343 0 _0402_5%

VCCST_OVERRIDE_N

VGS(Max) : 1.5 V

DGPU

SSD

WLAN

Card Reader

1 2

RC72 0_0402_5%@

SM_INTRUDER# NO INTERNAL PU/PD HIGH: SPI VOLTAGE IS 1.8V LOW: SPI VOLTAGE IS 3.3V

1

2

G

VGS(Max) : 1.5 V

13

D

2

QC2

G

BSS138W-7 -F_SOT323-3

SB00001GC00

S

VCCIN_AUX_CORE_VID 41

VCCST_EN_LS 16

13

D

S

4

CLK_PEG_N026 CLK_PEG_P026 CLKREQ_PEG#026

CLK_PCIE_N144 CLK_PCIE_P144 CLKREQ_PCIE#144

CLK_PCIE_N339 CLK_PCIE_P339 CLKREQ_PCIE#339

CLK_PCIE_N445 CLK_PCIE_P445 CLKREQ_PCIE#445

PM_SLP_S4#41,54 PM_SLP_S3#16,41,43

EC_RSMRST#41

PCH_PWROK41 SYS_PWROK41

EC_CLEAR_CMO S# 41

From EC (Open-Drain)

VCCST_PWR GD41

From EC to VCCST VR Power SW Enable

To EC

VCCST_OVERRIDE_LS 41

QC3 BSS138W-7 -F_SOT323-3

SB00001GC00

4

UC1J

CJ3

CLKOUT_PCIE_N0

CJ5

CLKREQ_PEG#0

CLKREQ_PCIE#1

CLKREQ_PCIE#3

CLKREQ_PCIE#4

SLP_SUS# PM_SLP_S5# PM_SLP_S4# PM_SLP_S3# PM_SLP_A# PM_SLP_S0#

PM_SLP_W LAN# PM_SLP_LAN#

EC_RSMRST# SYS_RESET# SOC_PLTRST #

EC_RSMRST# PCH_PWR OK SYS_PWROK

INPUT3VSEL SM_INTRUDER#

+1.05V_VCCST

VCCST_PWR GD EC_VCCST_PG

CLKOUT_PCIE_P0

DK33

GPP_D5/SRCCLKREQ0#

CL2

CLKOUT_PCIE_N1

CL1

CLKOUT_PCIE_P1

DN34

GPP_D6/SRCCLKREQ1#

CL3

CLKOUT_PCIE_N2

CL5

CLKOUT_PCIE_P2

DP34

GPP_D7/SRCCLKREQ2#

CK3

CLKOUT_PCIE_N3

CK4

CLKOUT_PCIE_P3

DP36

GPP_D8/SRCCLKREQ3#

CJ2

CLKOUT_PCIE_N4

CJ1

CLKOUT_PCIE_P4

DN40

GPP_H10/SRCCLKREQ4#

ICL-U_BGA1526

@

UC1K

DM49

SLP_SUS#

DF45

GPD10/SLP_S5#

DC48

GPD5/SLP_S4#

DF47

GPD4/SLP_S3#

DH47

GPD6/SLP_A#

CL45

GPP_B12/SLP_S0#

DE49

GPD9/SPL_WLAN#

DN48

SLP_LAN#

DG49

RSMRST#

DK19

SYS_RESET#

CM49

GPP_B13/PLTRST#

DR48

DSW_PWROK

DN47

PCH_PWROK

DP19

SYS_PWROK

DN49

INPUT3VSEL

DR47

INTRUDER#

ICL-U_BGA1526

@

12

RC76 1K_0402_5%

1 2

RC77 60.4_0402_1 %

1

CC15 100P_0402_ 50V8J

ESD@

2

ESD

To EC

Singal Name Inpu t

VCCI N_A UX_C ORE_ VID

VCCS T_O VERR IDE_ LS

PM_SLP_S3# (SUSP#)

EC_VCCST_EN Output H

VCCI N_A UX_C ORE_ VID

VCCS T_O VERR IDE_ LS

PM_SLP_S4# (SYSON)

Volu me Prem ium

EC_VCCST_EN Output H

3

Follow Check list NC for un-used

CLKOUT_PCIE_N5

CLKOUT_PCIE_P5

GPP_H11/SRCCLKREQ5#

RTCX1

RTC

RTCX2

RTCRST#

SRTCRST#

GPD8/SUSCLK

XTAL_IN

XTAL

XTAL_OUT

10 of 19

GPP_H3/SX_EXIT_HOLDOFF_N/CNV_BT_I2S_SDO

XCLK_BIASREF

GPD3/PWRBTN#

GPD1/ACPRESENT

GPD0/BATLOW#

GPP_B11/PMCALERT#

GPP_H18/CPU_C10_GATE#

WAKE#

GPD2/LAN_WAKE#

GPD11/LANPHYPC/DSWLDO_MON

VCCST_OVERRIDE

VCCST_PWRGD

VCCSTPWRGOOD_TCSS

PROCPWRGD

GPD7

11 of 19

H

DDD

D H

H H

H

D

H

D

H H

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

INPUT3VSEL 3V SELECT STRAP

CF5 CF3 DP40

DL48 DL49

DT47 DK46

DF49

DW8 DU8

DU6

CY42 DE46 DH48

CL39 DU40 DG40

DL45

DE47 DF48

CE4 CF2 CE3 CF1

DC47

SOC_RTCX1 SOC_RTCX2

SOC_RTCRST # SOC_SRTCRS T#

SUSCLK

SOC_XTAL38.4_IN SOC_XTAL38.4_OUT

XCLK_BIASREF

PBTN_OUT# AC_PRESENT_R PM_BATLOW#

PMCALERT#_R CPU_C10_GAT E#

WAKE#

LAN_WAKE#

VCCST_OVERRIDE EC_VCCST_PG VCCSTPWR GOOD_TCSS H_PROCPW RGD

GPD7

+3VALW

HIGH: 3.0V +/-5% LOW: 3.3V +/-5% Follow 573129_ICL_U_DDR4_SODIMM_HW_SCH_RN

573129 RVP reserve both side, but ORB only reserve on RTCX2

1 2

RC61 0_0402_5%@

1 2

RC376 0_0402_5%@

1 2

RC59 60.4_0402_ 1%

1 2

RC66 0_0402_5%@

1 2

RC563 0_0402_5%

1 2

RC388 0_0402_5%@

1 2

RC453 0_0402_5%@

T503TP@

T501TP@

VCCST_PWR GD#

1 2

RC568

100K_0402_ 5%

PM_SLP_S3#

5

SOC_XTAL38.4_IN SOC_XTAL38.4_IN_R

SOC_XTAL38.4_OUT SOC_XTAL38.4_OUT _R

Only For Power Sequence Debug

2

3

QC1B DMN63D8LD W-7_SOT363-6 -X

SB000013K0 0

4

EMI

L

HD D

L

D

L

D

H

L

Compal Secret Data

2019/05/15 2020/05/15

Compal Secret Data

Deciphered Date

SOC_PLTRST #

2

SOC_RTCX2_R

SUSCLK_R 39

PBTN_OUT# 41 AC_PRESENT 29,41

PMCALERT# 37

CPU_C10_GAT E# 16PM_SLP_S0#16

KBL_ID 42

VCCST_OVERRIDE_R

VCCST_PWR GD

61

QC1A DMN63D8LD W-7_SOT363-6 -X

SB000013K0 0

1 2

RC54 33_0402_5 %EMI@

1 2

RC55 33_0402_5 %EMI@

PCH PLTRST Buf f er

100K_0402_5%

12

RC312

For Glitch

stuff for CNVI check list

1 2

RC63 0_0402_5%@

+3VS

1

B

2

A

1

PMCALERT#_R PM_BATLOW#

WAKE# LAN_WAKE#

INPUT3VSEL

SUSCLK

Follow 573129_I CL_U_D DR4_SO DIMM_H W_SCH_ RN

SOC_RTCX2_R

SOC_RTCX1

RC62 10M_04 02_5%

32.768KHZ_12 .5PF_9H03200042

8.2P_0201_25V8D

1

CC17

2

tCPU22/ tPCH28b

VCCST_PWR GD

PCH_PWR OK

2

3

tPLT17

VR_ON41,56

12 12 12 12 12

12

1 2

YC2

1 2

SJ10000Q400

D15

@

1

LRB715FT1G_ SOT323-3

SCS00008E0 0

D32

@

12

RB751V-40_SOD 323-2

SCS00000Z00

RC53310K_0402_5 % RC698.2K_0402_1 % RC4511K_0402_5% RC45210K_0402_5 % RC4564.7K_0402_5 % @

RC457100K_0402_ 5%

RC375100K_0402_ 5% @

8.2P_0201_25V8D

1

CC18

2

PM_SLP_S3#

PM_SLP_S3#VR_ON

Remove, If PCB space not enough

1 2

RC57 200K_0402 _1%

YC3

123

CC162 12P_0201_5 0V8J

5

P

G

3

2

38.4MHZ_10PF_ 8Y38420005

1

CC19

@

1 2

0.1U_0201_ 10V6K

4

Y

UC4 74AHC1G08GW _SOT353-5

SA741080400

Title

Size Document Nu mber Re v

Size Document Nu mber R ev

Date : Sheet of

PCI_RST#

@

1

CC397 100P_0402_ 50V8J

@ESD@

2

Compal Electronics, Inc.

ICL-U(5/12)CLK,GPIO

LA-LJ551PR02

4

SJ10000VM00

PCI_RST# 26,39,41,44,45

1

11 67Thursday, August 22, 2 019

+3VALW

2

CC163 12P_0201_5 0V8J

1

0.2

+3VS

www.forums-fastunlock.com

5

4

3

2

F u

n c

t i

o n

M O

D E

G P

(

S 5

5 0

P_D 1

1

L_S E

T T

I N

G 1

M O

D E

L_S E

T T

I N

)

0

G P

(

G 0

P_D 0

)

1

1 2

RC459 49.9K_0402_1%

1 2

RC460 49.9K_0402_1%

1 2

RC106 2.2K_0402_5%

1 2

RC105 2.2K_0402_5%

1 2

RC520 10K_0402_5%DI S@

D D

C C

1 2

RC518 10K_0402_5%@

1 2

RC519 10K_0402_5%DI S@

UART_2_CRXD_DTXD UART_2_CTXD_DRXD

I2C_0_SDA I2C_0_SCL DGPU_PWR_EN

DGPU_HOLD_RST#

WL_OFF#39

WLBT_OFF#13,39

RC570 0_0201_5%

RC571 0_0201_5%

Touch Pad

EC Sensor Hub

SENSOR_EC_INT41

1 2

@

RC569 0_0201_5%

HDA_SPKR40

1 2

UART_2_CRXD_DTXD39 UART_2_CTXD_DRXD39

I2C_0_SDA42 I2C_0_SCL42

I2C_2_SDA41 I2C_2_SCL41

OBRAM_ID4 SOC_GPP_B18

SOC_GPP_B15 HDA_SPKR

OBRAM_ID1 OBRAM_ID3 OBRAM_ID2 OBRAM_ID0 SOC_GPP_B23

WL_OFF#_R

WLBT_OFF#_R

UART_2_CRXD_DTXD UART_2_CTXD_DRXD

I2C_0_SDA I2C_0_SCL

I2C_2_SDA I2C_2_SCL

UC1F

CH48

GPP_B16/GSPI0_CLK

CF48

GPP_B18/GSPI0_MOSI

CF47

GPP_B17/GSPI0_MISO

CH49

GPP_B15/GSPI0_CS0#

CH47

GPP_B14/SPKR/TIME_SYNC1/GSPI0_CS1#

CL47

GPP_B20/GSPI1_CLK

CK47

GPP_B22/GSPI1_MOSI

CK46

GPP_B21/GSPI1_MISO

CH45

GPP_B19/GSPI1_CS0#

CL48

GPP_B23/SML1ALERT#/PCHHOT#/GSPI1_CS1#

DP21

GPP_C8/UART0_RXD

DK21

GPP_C9/UART0_TXD

DL21

GPP_C10/UART0_RTS#

DJ22

GPP_C11/UART0_CTS#

DT22

GPP_C20/UART2_RXD

DW22

GPP_C21/UART2_TXD

DV22

GPP_C22/UART2_RTS#

DU22

GPP_C23/UART2_CTS#

DT24

GPP_C16/I2C0_SDA

DT23

GPP_C17/I2C0_SCL

DW23

GPP_C18/I2C1_SDA

DU23

GPP_C19/I2C1_SCL

DU41

GPP_H4/I2C2_SDA

DV41

GPP_H5/I2C2_SCL

DW41

GPP_H6/I2C3_SDA

DT41

GPP_H7/I2C3_SCL

DT40

GPP_H8/I2C4_SDA/CNV_MFUART2_RXD

DW40

GPP_H9/I2C4_SCL/CNV_MFUART2_TXD

ICL-U_BGA1526

@

GPP_D15/ISH_UART0_RTS_N/GSPI2_CS1_N/IMGCLKOUT5

GPP_D16/ISH_UART0_CTS_N/CNV_WCEN

UART

GSPI

UART

I2C

6 of 19

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_C15/UART1_CTS#/ISH_UART1_CTS#

I2C / ISH

ISH

GPP_D13/ISH_UART0_RXD GPP_D14/ISH_UART0_TXD

GPP_B5/ISH_I2C0_SDA GPP_B6/ISH_I2C0_SCL

GPP_B7/ISH_I2C1_SDA GPP_B8/ISH_I2C1_SCL

GPP_B9/I2C5_SDA/ISH_I2C2_SDA

GPP_B10/I2C5_SCL/ISH_I2C2_SCL

GPP_D0/ISH_GP0 GPP_D1/ISH_GP1 GPP_D2/ISH_GP2

GPP_D3/ISH_GP3 GPP_D17/ISH_GP4 GPP_D18/ISH_GP5

GPP_E15/ISH_GP6 GPP_E16/ISH_GP7

DV33 DW33 DT33 DU33

DK22 DW24 DV24 DU24

CN43 CN42

CN41 CL43

CL41 CJ39 DU36 DV36 DW36 DT36 DU34 DW34 DT14 DU14

ATTD#_R PLG_ORI#_R

With BIOS check

FP_RST

SOC_GPP_D16

DGPU_PWR_EN DGPU_HOLD_RST# DGPU_ALL_PGOOD DGPU_PRSNT

ATTD#_R PLG_ORI#_R MODEL_SETTING0 MODEL_SETTING1 MODEL_SETTING2

GPIO_Reserve DGPU_SEL1 DGPU_SEL0

RC564 0_0402_5%@ RC565 0_0402_5%@

1 2 1 2

FP_RST 43

DGPU_PWR_EN 31,41 DGPU_HOLD_RST# 26 DGPU_ALL_PGOOD 31

ATTD# 38 PLG_ORI# 38

Place the same side(TOP/BOT) with on board RAM IC

Strap Pin

+3VS

RC278

4.7K_0402_5%

12

@

+3VALW

RC277

4.7K_0402_5%

@

RC283

10K_0402_5%

RC279

4.7K_0402_5%

12

@

+3VS

1 2

RC98 10K_0402_5%@

1 2

RC99 10K_0402_5%

1 2

RC107 10K_0402_5%

1 2

RC108 10K_0402_5%@

F u

n c

t i

o n

A r

S i

*

D G

*

(

r a

r y

M

I C

n g

l e

M

I C

G P

I O

R

e s

e r

v e

1 2

RC168 10K_0402_5%@

1 2

RC169 10K_0402_5%@

P U

S

e l

e c

t

1 2

RC115 10K_0402_5%DIS@

1 2

RC116 10K_0402_5%

UMA@

F u

n c

t i

o n

N 1

7 S

- G

0

N 1

7 S

- G

2

N 1

7 S

- G

3

N 1

7 S

- G

5

N 1

7 S

- G

0 /

G 2

o

MODEL_SETTING1

MODEL_SETTING0

M O

D E

L_S E

T T

I N

G P

G 2

P_D 2

)

1 0

MODEL_SETTING2

DGPU_PRSNT

D G

P U_S E

L 1

D G

P U_S E

G P

P_D 1

8

(

)

0

L 0

G P

P_D 1

5

(

)

0

1

1 0

1 1

n l

y

f o

r

S D

V

p h

a s

e

SOC_GPP_B18

B B

+3VS+3VS +3VS

12

RC91 10K_0402_5%

@

12

RC94 10K_0402_5%

@

A A

5

12

RC92 10K_0402_5%

OBRAM_ID0 OBRAM_ID1 OBRAM_I D2

@

12

RC95 10K_0402_5%

@

12

RC93 10K_0402_5%

@

12

RC96 10K_0402_5%

@

+3VS +3VS

12

RC560 10K_0402_5%

@

OBRAM_ID3

12

RC561 10K_0402_5%

@

4

12

RC566 10K_0402_5%

@

12

RC567 10K_0402_5%

@

OBRAM_ID4

GPP_B18 No Reboot INTERNAL PD 20K HIGH: No Reboot LOW: Reboot Enable (Default)

SPKR TOP SWAP OVERRIDE INTERNAL PD 20K HIGH: Top swap enable LOW: Disable (Default)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

HDA_SPKR

RC281

20K_0402_5%

RC282

20K_0402_5%

12

@

GPP_B23 CPUNSSC CLOCK FREQ INTERNAL PD 20K HIGH: 19.2 MHz (form internal divider) LOW: 38.4 MHz (direct form crystal) (Default)

GPP_D16 MFR_MODE_DET_STRAP Follow 573129_ICL_U_DDR4_SODIMM_HW_SCH_RN_1P0

Compal Secret Data

2019/05/15 2020/05/15

Compal Secret Data

RC285

20K_0402_5%

12

@

Deciphered Date

SOC_GPP_B23

SOC_GPP_D16

RC280

100K_0402_5%

12

GPP_D16 Strap refer RV P

2

+3VS

1 2

RC119 10K_0402_5%

1 2

RC120 10K_0402_5%@

+3VS

1 2

RC159 10K_0402_5%@

1 2

RC160 10K_0402_5%@

RC159

N17S_G5@

10K_0402_5%

RC160

N17S_G3@

10K_0402_5%

G P

I O

R

e s

e r

v e

+3VS

1 2

RC527 10K_0402_5%@

1 2

RC528 10K_0402_5%@

Compal Electronics, Inc.

Title

Size

Date: Sheet

Compal Electronics, Inc.

ICL-U(6/12)GPIO

Document Number Re v

LA-LJ551PR02

DGPU_SEL1

DGPU_SEL0

GPIO_Reserve

1

0.2

of

12 67Thursday, August 22, 2019

of

12 67Thursday, August 22, 2019

of

12 67Thursday, August 22, 2019

5

www.forums-fastunlock.com

PCIE_CRX_ DTX_N726 PCIE_CRX_ DTX_P726 PCIE_CTX_ C_DRX_N726

GPU

D D

Card Reader

NGFF WLAN+BT

C C

B B

SSD

SATA SSD

+3VS

1 2

RC534 10K_040 2_5%@

+3VALW

USB_OC0# Strap refer RVP

1 2

RC401 10K_040 2_5%

1 2

RC403 10K_040 2_5%

PCIE_CTX_ C_DRX_P726

PCIE_CRX_ DTX_N826 PCIE_CRX_ DTX_P826 PCIE_CTX_ C_DRX_N826 PCIE_CTX_ C_DRX_P826

PCIE_CRX_ DTX_N945 PCIE_CRX_ DTX_P945 PCIE_CTX_ DRX_N945 PCIE_CTX_ DRX_P945

PCIE_CRX_ DTX_N1039 PCIE_CRX_ DTX_P1039 PCIE_CTX_ DRX_N1039 PCIE_CTX_ DRX_P1039

PCIE_CRX_ DTX_N1344 PCIE_CRX_ DTX_P1344 PCIE_CTX_ DRX_N1344 PCIE_CTX_ DRX_P1344

PCIE_CRX_ DTX_N1444 PCIE_CRX_ DTX_P1444 PCIE_CTX_ DRX_N1444 PCIE_CTX_ DRX_P1444

PCIE_CRX_ DTX_N1544 PCIE_CRX_ DTX_P1544 PCIE_CTX_ DRX_N1544 PCIE_CTX_ DRX_P1544

PCIE_CRX_ DTX_N1644 PCIE_CRX_ DTX_P1644 PCIE_CTX_ DRX_N1644 PCIE_CTX_ DRX_P1644

WLB T_OFF#12 ,39

BKOFF#34,41

NGFF_SS D_PEDET

USB_OC0 # USB_OC3 #

CC366 0.22U _0402_6.3V6KDIS@ CC367 0.22U _0402_6.3V6KDIS@

CC368 0.22U _0402_6.3V6KDIS@ CC369 0.22U _0402_6.3V6KDIS@

1 2 1 2

1 2

RC572 0_0201_ 5%@

NGFF_SS D_PEDET44

USB_OC0#45

1 2

RC516 0_0201_ 5%@

DEVSLP244

1 2

RC100 100_040 2_1%

check list needs stuff even un-use

Note : Please reference PCH EDS Tabel 1-2

4

PCIE_CTX_ DRX_N7 PCIE_CTX_ DRX_P7

PCIE_CTX_ DRX_N8 PCIE_CTX_ DRX_P8

SOC_GPP _E0

NGFF_SS D_PEDET

USB_OC0 # USB_OC3 #

BKOFF#_ R

PCIE_RCOM PN PCIE_RCOM PP

UC1H

CV7

PCIE7_RXN

CV6

PCIE7_RXP

DD3

PCIE7_TXN

DD5

PCIE7_TXP

CT6

PCIE8_RXN

CT7

PCIE8_RXP

DA3

PCIE8_TXN

DA5

PCIE8_TXP

CP7

PCIE9_RXN

CP6

PCIE9_RXP

DA2

PCIE9_TXN

DA1

PCIE9_TXP

CM7

PCIE10_RXN

CM6

PCIE10_RXP

CY3

PCIE10_TXN

CY4

PCIE10_TXP

CK7

PCIE11_RXN/SATA0_RXN

CK6

PCIE11_RXP/SATA0_RXP

CW2

PCIE11_TXN/SATA0_TXN

CW1

PCIE11_TXP/SATA0_TXP

CJ6

PCIE12_RXN/SATA1A_RXN

CJ7

PCIE12_RXP/SATA1A_RXP

CW5

PCIE12_TXN/SATA1A_TXN

CW3

PCIE12_TXP/SATA1A_TXP

CG7

PCIE13_RXN

CG6

PCIE13_RXP

CT3

PCIE13_TXN

CT5

PCIE13_TXP

CE6

PCIE14_RXN

CE7

PCIE14_RXP

CT2

PCIE14_TXN

CT1

PCIE14_TXP

CC5

PCIE15_RXN/SATA1B_RXN

CC6

PCIE15_RXP/SATA1B_RXP

CR3

PCIE15_TXN/SATA1B_TXN

CR4

PCIE15_TXP/SATA1B_TXP

CA6

PCIE16_RXN/SATA2_RXN

CA5

PCIE16_RXP/SATA2_RXP

CP1

PCIE16_TXN/SATA2_TXN

CP2

PCIE16_TXP/SATA2_TXP

DW1 2

GPP_E0/SATAXPCIE0/SATAGP0

CR42

GPP_A12/SATAXPCIE1/SATAGP1

CR43

GPP_A13/SATAXPCIE2/SATAGP2

DW1 4

GPP_E9/USB_OC0#

CT43

GPP_A16/USB_OC3#

DU12

GPP_E4/DEVSLP0

DU11

GPP_E5/DEVSLP1

CV48

GPP_A11 / DEVSLP2

DT38

GPP_H12/M2_SKT2_CFG0

DW3 8

GPP_H13/M2_SKT2_CFG1

DV38

GPP_H14/M2_SKT2_CFG2

DU38

GPP_H15/M2_SKT2_CFG3

DN1

PCIE_RCOMPN

DN3

PCIE_RCOMPP

ICL-U_BGA1 526

@

PCIe

PCIe / SATA

3

PCIe / USB3.1

PCIe / SATA

8 of 19

PCIE1_RXN/USB31_1_RXN

PCIE1_RXP/USB31_1_RXP PCIE1_TXN/USB31_1_TXN

PCIE1_TXP/USB31_1_TXP

PCIE2_RXN/USB31_2_RXN

PCIE2_RXP/USB31_2_RXP PCIE2_TXN/USB31_2_TXN

PCIE2_TXP/USB31_2_TXP

PCIE3_RXN/USB31_3_RXN

PCIE3_RXP/USB31_3_RXP PCIE3_TXN/USB31_3_TXN

PCIE3_TXP/USB31_3_TXP

PCIE4_RXN/USB31_4_RXN

PCIE4_RXP/USB31_4_RXP PCIE4_TXN/USB31_4_TXN

PCIE4_TXP/USB31_4_TXP

PCIE5_RXN/USB31_5_RXN

PCIE5_RXP/USB31_5_RXP PCIE5_TXN/USB31_5_TXN

PCIE5_TXP/USB31_5_TXP

PCIE6_RXN/USB31_6_RXN

PCIE6_RXP/USB31_6_RXP PCIE6_TXN/USB31_6_TXN

PCIE6_TXP/USB31_6_TXP

USB2.0

USB_VBUSSENSE

USB2N_1 USB2P_1

USB2N_2 USB2P_2

USB2N_3 USB2P_3

USB2N_4 USB2P_4

USB2N_5 USB2P_5

USB2N_6 USB2P_6

USB2N_7 USB2P_7

USB2N_8 USB2P_8

USB2N_9 USB2P_9

USB2N_10

USB2P_10

USB_ID

USB2_COMP

RSVD_81

DJ8 DJ6 DJ2 DJ1

DG9 DG7 DJ3 DJ5

DE7 DE9 DF3 DF5

DC7 DC9 DF2 DF1

DA6 DA7 DE4 DE3

CY7 CY6 DD1 DD2

DN8 DP8

DK11 DJ11

DP13 DN13

DK10 DJ10

DL5 DL3

DP11 DN11

DK13 DJ13

DN6 DP6

DL2 DL1

DP10 DN10

DL6

DL11

DN5

CD3

2

PCIE_CTX_ DRX_N5 PCIE_CTX_ DRX_P5

PCIE_CTX_ DRX_N6 PCIE_CTX_ DRX_P6

USB2_ID

USB2_VB USSENSE

USB2_CO MP

UFS_RES ET#

USB3_CR X_DTX_N1 45 USB3_CR X_DTX_P1 4 5 USB3_CT X_DRX_N1 45 USB3_CT X_DRX_P1 4 5

USB3_CR X_DTX_N2 45 USB3_CR X_DTX_P2 4 5 USB3_CT X_DRX_N2 45 USB3_CT X_DRX_P2 4 5

1 2

CC370 0.22U_04 02_6.3V6KDIS@

1 2

CC371 0.22U_04 02_6.3V6KDIS@

1 2

CC372 0.22U_04 02_6.3V6KDIS@

1 2

CC29 0.2 2U_0402_6.3V6KDIS@

USB20_N 1 45 USB20_P 1 45

USB20_N 2 45 USB20_P 2 45

USB20_N 3 37 USB20_P 3 37

USB20_N 4 34 USB20_P 4 34

USB20_N 6 34 USB20_P 6 34

USB20_N 7 43 USB20_P 7 43

USB20_N 10 3 9 USB20_P 10 39

1 2

RC355 10K_040 2_5%

1 2

RC354 10K_040 2_5%

1 2

RC356 113_040 2_1%

1

T328

TP@

From Max reply mail

1

USB2.0 / 3.0 Port (IO - 1)

USB2.0 / 3.0 Port (IO - 2)

PCIE_CRX_ DTX_N5 26 PCIE_CRX_ DTX_P5 26 PCIE_CTX_ C_DRX_N5 26 PCIE_CTX_ C_DRX_P5 26

PCIE_CRX_ DTX_N6 26 PCIE_CRX_ DTX_P6 26 PCIE_CTX_ C_DRX_N6 26 PCIE_CTX_ C_DRX_P6 26

USB2.0 / 3.0 Port (MB - 1)

USB2.0 / 3.0 Port (MB - 2)

USB2.0 / 3.0 Port (Type-C)

Touch Screen

Camera

FingerP rint

NGFF WLAN+BT

GPU

A A

Security Classification

5

4

Security Classification

2019/05/ 15 2020/05/ 15

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2019/05/ 15 2020/05/ 15

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

ICL-U(7/12)PCIE,USB,SATA

LA-LJ551PR02

13 67Thursday, Aug ust 22, 2019

1

0.2

5

www.forums-fastunlock.com

UC1I

D12

CSI_E_CLK_N

C12

CSI_E_CLK_P

B12

CSI_E_DN_0

A12

CSI_E_DP_0

G13

CSI_E_DN_1

F13

CSI_E_DP_1

K10

D D

C C

1 2

RC357 100_0402_1%

CSI_RCOMP

CSI_F_CLK_N

L10

CSI_F_CLK_P

L8

CSI_F_DN_0

M8

CSI_F_DP_0

M11

CSI_F_DN_1

L11

CSI_F_DP_1

D9

CSI_D_CLK_N

C9

CSI_D_CLK_P

A7

CSI_D_DN_0

B7

CSI_D_DP_0

B9

CSI_D_DN_1

A9

CSI_D_DP_1

D7

CSI_D_DN_2/CSI_C_DN_0

C7

CSI_D_DP_2/CSI_C_DP_0

D8

CSI_D_DN_3/CSI_C_CLK_N

C8

CSI_D_DP_3/CSI_C_CLK_P

G11

CSI_H_CLK_N

J11

CSI_H_CLK_P

F6

CSI_H_DN_0

G6

CSI_H_DP_0

G10

CSI_H_DN_1

F10

CSI_H_DP_1

G8

CSI_H_DN_2/CSI_G_DN_0

J8

CSI_H_DP_2/CSI_G_DP_0

K6

CSI_H_DN_3/CSI_G_CLK_N

L6

CSI_H_DP_3/CSI_G_CLK_P

B4

CSI_RCOMP

DT34

GPP_D4/IMGCLKOUT0

DP38

GPP_H20/IMGCLKOUT1

DK36

GPP_H21/IMGCLKOUT2

DL36

GPP_H22/IMGCLKOUT3

DN38

GPP_H23/IMGCLKOUT4

4

GPP_F8/EMMC_DATA0

GPP_F9/EMMC_DATA1 GPP_F10/EMMC_DATA2 GPP_F11/EMMC_DATA3 GPP_F12/EMMC_DATA4 GPP_F13/EMMC_DATA5

eMMC

1.8V

CSI2

CNVi

GPP_F3/CNV_RGI_RSP/UART0_CTS#

GPP_F14/EMMC_DATA6 GPP_F15/EMMC_DATA7

GPP_F7/EMMC_CMD

GPP_F16/EMMC_RCLK

GPP_F17/EMMC_CLK

GPP_F18/EMMC_RESET#

EMMC_RCOMP

CNV_WT_D0N CNV_WT_D0P CNV_WT_D1N

CNV_WT_D1P CNV_WT_CLKN CNV_WT_CLKP

CNV_WR_D0N

CNV_WR_D0P

CNV_WR_D1N

CNV_WR_D1P CNV_WR_CLKN CNV_WR_CLKP

CNV_WT_RCO MP

GPP_F1/CNV_BRI_RSP/UART0_RXD

GPP_F2/CNV_RGI_DT/UART0_T XD

GPP_F0/CNV_BRI_DT/UART0_RT S#

GPP_F4/CNV_RF_RESET#

GPP_F6/CNV_PA_BLANKING

GPP_F19/A4WP_PRESENT

GPP_F5/MODEM_CLKREQ

3

DP27 DU30 DT30 DT29 DV30 DU29 DW30 DW29 DV28 DW28 DN27 DT28 DU28

DV45 DU45 DU44 DT44 DL42 DK42

DP44 DN44 DG42 DG44 DK44 DJ44

DT45

DL29 DP31 DL31 DN29

DJ29 DP29 DL27 DK29

GC6_FB_EN1V8 GPU_EVENT#_1V8

EMMC_RCOMP

CNV_WT_RCO MP

CNV_BRI_CRX_DTX CNV_RGI_CTX_DRX CNV_BRI_CTX_DRX CNV_RGI_CRX_DTX

SOC_GPP_F4

SOC_GPP_F19 SOC_GPP_F5

GC6_FB_EN1V8 29,30 GPU_EVENT#_1V8 29

CNV_CTX_DRX_N0 39 CNV_CTX_DRX_P0 39 CNV_CTX_DRX_N1 39 CNV_CTX_DRX_P1 39 CLK_CNV_CTX_DRX_N 39 CLK_CNV_CTX_DRX_P 39

CNV_CRX_DTX_N0 39 CNV_CRX_DTX_P0 39 CNV_CRX_DTX_N1 39 CNV_CRX_DTX_P1 39 CLK_CNV_CRX_DTX_N 39 CLK_CNV_CRX_DTX_P 39

1 2

RC109 150_0402_1%

CNV_BRI_CRX_DTX 39 CNV_RGI_CTX_DRX 39 CNV_BRI_CTX_DRX 39 CNV_RGI_CRX_DTX 39

1

TP@

T340

2

EMMC_RCOMP

SOC_GPP_F19

RC104 200_0402_1%

1 2

RC432 75K_0402_5%

1

12

Follow 574200 MoW WW03

1.8V

ICL-U_BGA1526

@

B B

+1.8VALW

1 2

RC181 20K_0402_5%@

1 2

RC182 20K_0402_5%@

Follow check list reserve

A A

5

CNV_BRI_CRX_DTX

CNV_RGI_CRX_DTX

CNV_RGI_CTX_DRX (M.2 CNVI MODES)

0 = Integrated CNVi enable. 1 = Integrated CNVi disable.

NO INTERNAL PU/PD

WLAN side has PU, just reserve PU on CPU side for RMT test ?

CNV_RGI_CTX_DRX

4

9 of 19

CNV_BRI_CTX_DRX (XTAL SEL)

0 = 38.4/19.2MHZ (DEFAULT)

1 = 24MHZ (25 MHZ WHEN XTAL FREQ DIVIDER NON ZERO)

WEAK INTERNAL PD 20K

whether can remove?

+1.8VALW

1 2

RC373 100K_0402_5%RMT@

1 2

RC112 4.7K_0402_5%@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

this pin have internal PD already

CNV_BRI_CTX_DRX

Compal Secret Data

2019/05/15 2020/05/15

3

Compal Secret Data

Deciphered Date

1 2

RC374 4.7K_0402_5%@

1 2

RC111 20K_0402_5%@

+1.8VALW

2

Title

Size

Document Number Re v

Date : Sheet o f

SOC_GPP_F4

Follow 572907_ICL_UY_PDG PC glitch free,it is recommended that a pull-down resistor of 75K ohm on GPP_F4(CNV_RF_RESET#)

Compal Electronics, Inc.

ICL-U(8/13)CSI,CNV

LA-LJ551PR02

12

RC440 75K_0402_5%

@

1

14 67Thursday, August 22, 2019

0.2

5

www.forums-fastunlock.com

4

3

2

1

+1.05V_VCCST

12

D D

SVID DATA

SOC_SVID_DAT

1 2

RC362 0_0402_5%@

SVID ALERT

SOC_SVID_ALERT#

1 2

RC363 0_0402_5%@

RC148 100_0402_1%

+1.05V_VCCST

RC146 56_0402_5%

1 2

SOC_SVID_DAT_R 56

SOC_SVID_ALERT#_R 56

SVID CLOCK

C C

B B

SOC_SVID_CLK

1 2

RC364 0_0402_5%@

SOC_SVID_CLK_R 56

+VCCIN +VCCIN

UC1L

CPU POWER 1 OF 3

A19

SOC_SVID_ALERT# SOC_SVID_CLK SOC_SVID_DAT

AC12

V13

W12

Y13 K29 K31 B19 B23 B27

B29 BN10 BP11

BP9

BR10

BT11

A21

BT9 BU10 BV36

BV9 BW10 BW36

BW9

BY10

C19 C23 A23 C27 C29

CA36

CA9

CB10 CC11 CC36

CC9

CD10

CE11

A24 CE34 CE35 CF10 CF33

CG11 CG34 CG35 CH10

CJ11

A27

CJ34

J30

H1 H2 H3

VCCIN_1 VCCIN_2 VCCIN_3 VCCIN_4 VCCIN_5 VCCIN_6 VCCIN_7 VCCIN_8 VCCIN_9 VCCIN_10 VCCIN_11 VCCIN_12 VCCIN_13 VCCIN_14 VCCIN_15 VCCIN_16 VCCIN_17 VCCIN_18 VCCIN_19 VCCIN_20 VCCIN_21 VCCIN_22 VCCIN_23 VCCIN_24 VCCIN_25 VCCIN_26 VCCIN_27 VCCIN_28 VCCIN_29 VCCIN_30 VCCIN_31 VCCIN_32 VCCIN_33 VCCIN_34 VCCIN_35 VCCIN_36 VCCIN_37 VCCIN_38 VCCIN_39 VCCIN_40 VCCIN_41 VCCIN_42 VCCIN_43 VCCIN_44 VCCIN_45 VCCIN_46 VCCIN_47 VCCIN_48 VCCIN_49 VCCIN_50 VCCIN_51

VIDALERT# VIDSCK VIDSOUT

ICL-U_BGA1526

@

12 of 19

VCCIN_SENSE

VSSIN_SENSE

VCCIN_52 VCCIN_53 VCCIN_54 VCCIN_55 VCCIN_56 VCCIN_57 VCCIN_58 VCCIN_59 VCCIN_60 VCCIN_61 VCCIN_62 VCCIN_63 VCCIN_64 VCCIN_65 VCCIN_66 VCCIN_67 VCCIN_68 VCCIN_69 VCCIN_70 VCCIN_71 VCCIN_72 VCCIN_73 VCCIN_74 VCCIN_75 VCCIN_76 VCCIN_77 VCCIN_78 VCCIN_79 VCCIN_80 VCCIN_81 VCCIN_82 VCCIN_83 VCCIN_84 VCCIN_85 VCCIN_86 VCCIN_87 VCCIN_88 VCCIN_89 VCCIN_90 VCCIN_91 VCCIN_92 VCCIN_93 VCCIN_94 VCCIN_95 VCCIN_96 VCCIN_97 VCCIN_98

VCCIN_99 VCCIN_100 VCCIN_101 VCCIN_102 VCCIN_103 VCCIN_104

CJ35 CK10 J32 CL34 CL35 CN34 CN35 CP33 CR34 A29 CR35 CT33 CT34 CT35 CU33 D19 D21 D23 D24 D27 AA12 D29 F19 F21 F23 F24 F27 F29 G1 G19 G23 AB1 G27 G29 H19 H23 H27 H29 J18 J20 J22 J23 AB13 J26 J28 K17 K19 K21 K23 K24 K27 M1 U1

F17 G17

+VCCIN

CC375

100P_0402_50V8J

1

RF@

VCCIN_VCCSENSE 56 VCCIN_VSSSENSE 56

2

CC376

100P_0402_50V8J

@RF@

RF reserve

CC378

100P_0402_50V8J

CC377

100P_0402_50V8J

1

@RF@

2

A A

Security Classification

2019/05/15 2020/05/15

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2019/05/15 2020/05/15

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

Document Number Re v

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

ICL-U(9/13)Power, SVID

LA-LJ551PR02

15 67Thursday, August 22, 2019

1

0.2

5

www.forums-fastunlock.com

EMC CAPS-PLACE < 4mm from SOC VDDQ with each pair < 12mm Apart 12pF* 3 (EMI@) 2pF* 3 (EMI@)

D D

+1.2V +1.2V +1.2V

CC219

12P_0201_50V8J

CC218

2P_0201_25V8B

1

2

EMI@

CC220

2P_0201_25V8B

1

2

EMI@

Modern Standby

1 2

RC535 0_0402_5%S0iX@

@

1 2

RC536 0_0402_5%

@

1 2

RC537 0_0402_5%

1 2

S0iX@

0_0402_5%

RC538

VCCSTG

UC11

1

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

4

ON

1U_0201_6.3V6M

EM5201V_DFN8_3X3

S0iX@

I (Max) : 0.119 A(+1.05VS_VCCSTG) RDS(Typ) : 3.5 mohm V drop : 0.0004V

VIN1 VIN2

VIN thermal

VBIAS

ON

EM5201V_DFN8_3X3

S0iX@

VOUT

GND

VOUT

GND

6

5

+1.05VS_VCCSTG_P

6

5

+1.1VS_VCCSTG_P

+1.8VALW

VIN1 VIN2

VIN thermal

VBIAS

ON

EM5201V_DFN8_3X3

S0iX@

VOUT

GND

+1.8V_VALW_P

6

5

CC381

1

2

SUSP#

PM_SLP_S3#

PM_SLP_S0#

CPU_C10_GATE#

1U_0201_6.3V6M

CC384

1

@

2

SUSP#41,47,64

PM_SLP_S3#11,41,43

PM_SLP_S0#11

CPU_C10_GATE#11

C C

+1.05VO_OUT_FET

RC539 0_0402_5%S0iX@

Imax : 0.119 A

For Power consumption Measuremen t

CC382

0.1U_0201_16V6K

12

@

VCCSTG_EN_LS VCC STG_EN_LS_R

1 2

+5VALW

1 2

RC542 0_0201_5%

+1.05VO_OUT_FET_JP2

S0iX@

CPU_C10_GATE# stable to +1.05VS_VCCSTG <= 65us (tCPU26)

+1.2V

RC543 0_0402_5%S0iX@

Imax : 0.119 A

B B

For Power consumption Measuremen t

CC386

0.1U_0201_16V6K

12

@

VCCSTG_EN_LS VCC PLL_OC_EN_LS_R

+1.8VALW

RC548

0_0603_5%

Imax : 0.119 A

For Power consumption Measuremen t

CC393

0.1U_0201_16V6K

12

A A

@

CPU_C10_GATE# CPU_C10_GATE#_R

+1.2V_VDDQ_JP

1 2

S0iX@

+5VALW

1 2

RC546

S0iX@

0_0201_5%

CPU_C10_GATE# stable to +1.05VS_VCCSTG <= 65us (tCPU26)

+1.8VALW_JP

1 2

S0iX@

+5VALW

1 2

RC551

S0iX@

0_0201_5%

5

+1.2V TO +1.2V_VCCPLL_OC

1U_0201_6.3V6M

CC385

1

2

1

2

UC12

1 2

7

3

4

1U_0201_6.3V6M

CC388

1

@

2

I (Max) : 0.119 A(+1.05VS_VCCSTG)

RDS(Typ) : 3.5 mohm

V drop : 0.0004V

1U_0201_6.3V6M

CC390

UC14

1 2

7

3

4

1U_0201_6.3V6M

CC396

1

@

2

RDS(Typ) : 3.5 mohm

V drop : 0.0004V

4

CC221

12P_0201_50V8J

1

2

EMI@

+3VALW

5

UC10

1

P

B

Y

2

A

G

74AHC1G08GW_SOT353-5

3

S0iX@

1

2

+1.05V_VCCST +1.05VS_VCCSTG

RC530 0_0402_5%

RC545 0_0402_5%S0iX@

1

2

+1.2V

RC547 0_0402_5%NOS0iX@

1

S0iX@

2

RC552 0_0603_5%NOS0iX@

4

CC222

2P_0201_25V8B

1

2

EMI@

1

CC380

0.1U_0201_10V6K

S0iX@

2

VCCSTG_EN_LS

4

1 2

RC541 0_0402_5%S0iX@

CC383

0.1U_0201_10V6K

S0iX@

1 2

NOS0iX@

1 2

CC387

0.1U_0201_10V6K

S0iX@

1 2

RC550 0_0402_5%S0iX@

CC395

0.1U_0201_10V6K

1 2

CC223

12P_0201_50V8J

1

2

EMI@

+1.2V_VCCPLL_OC

Imax : 0.119 A

Imax : 0.7 A

+1.8V_PRIM_SOC+1.8VALW

+1.05VS_VCCSTG

Imax : 0.119 A

Imax : 0.152 A

+1.2V_VCCPLL_OC

+1.8V_PRIM_SOC

VCCST_EN_LS11

+1.05VS_VCCSTG_OUT_FUSE

+1.05VS_VCCSTG_OUT_LGC

Imax : 0.445 A

For Power consumption Measuremen t

CC315

0.1U_0201_10V6K

12

@

1 2

@

RC412 0_0402_5%

1U_0201_6.3V6M

CC391

@

0.1U_0201_16V6K

12

3

+1.2V +1.2V

+1.05V_VCCST

+1.05VS_VCCSTG

+1.05VO_OUT_FET

1U_0201_6.3V6M

CC314

1

2

+5VALW

VCCST_EN_LS_R

@

Place on CPU Side 22uF* 2 + 22uF* 1 (Reserved)

+1.2V +1.2V+1.2V

22U_0603_6.3V6K

CC189

+1.8VALW

1

CC389

2

+5VALW

SUSP#

CC394

@

1U_0201_6.3V6M

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

VCCST

UC9

1

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

4

ON

1U_0201_6.3V6M

CC317

1

EM5201V_DFN8_3X3

SA00008R600

2

I (Max) : 0.455 A(+1.05V_VCCST) RDS(Typ) : 3.5 mohm V drop : 0.0016V

22U_0603_6.3V6M

CC190

1

@

2

+1.8VALW TO +1.8VS

UC13

1

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

4

ON

1

EM5201V_DFN8_3X3

2

RDS(Typ) : 3.5 mohm V drop : 0.0004V

UC1M

VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 VDDQ_10 VDDQ_11 VDDQ_12 VDDQ_13 VDDQ_14 VDDQ_15 VDDQ_16 VDDQ_17 VDDQ_18 VDDQ_19 VDDQ_20 VDDQ_21 VDDQ_22 VDDQ_23 VDDQ_24 VDDQ_25 VDDQ_26 VDDQ_27 VDDQ_28 VDDQ_29 VDDQ_30

CB1

VCCST

BY1

VCCSTG

F33

VCCSTG_OUT_1

G33

VCCSTG_OUT_2

E5

VCCSTG_OUT_LGC

ICL-U_BGA1526

@

6

5

6

5

CPU POWER 2 OF 3

13 of 19

JPC11

112

JUMP_43X39

0.1U_0201_10V6K

+1.8VS

Compal Secret Data

AA37 AG36 AJ36 AL36 AL49 AN36 AP37 AR36 AR37 AT36 AT49 AA49 AV36

AW37

AY36 BA37 BA49 BB36 BD36 BE37 BF36 BF37 AB36 BF49 BG36 BJ36 BL37 BM49 BN37 BP38

VOUT

GND

22U_0603_6.3V6M

CC191

1

2

VOUT

GND

2019/05/15 2020/05/15

2

BP39

VDDQ_31

BR37

VDDQ_32

BT38

VDDQ_33

AC35

VDDQ_34

BU37

VDDQ_35

BU49

VDDQ_36

CA39

VDDQ_37

CB49

VDDQ_38

L38

VDDQ_39

L49

VDDQ_40

N36

VDDQ_41

T49

VDDQ_42

AC37

VDDQ_43

AD35

VDDQ_44

AD36

VDDQ_45

AE36

VDDQ_46

AF49

VDDQ_47

C33

RSVD_78

A33

RSVD_2

B33

RSVD_3

BG9

VCC1P8A_1

BJ9

VCC1P8A_2

BM9

VCC1P8A_3

BW1

VCC1P8A_4

BW2

VCC1P8A_5

VCCSTG_OUT_3 VCCSTG_OUT_4 VCCSTG_OUT_5 VCCSTG_OUT_6 VCCSTG_OUT_7

1

2

R35 V34 T34 U35 AB34 W35

RSVD_74

AA35

RSVD_75

Y34

RSVD_76

CD2

VCCPLL

CG38

VCCPLL_OC_1

CG41

VCCPLL_OC_2

CG42

VCCPLL_OC_3

CG49

VCCPLL_OC_4

AD7

VCCIO_OUT

Imax : 0.445 A

+1.05V_VCCST

JUMP@

2

close to package as possible

1

CC316

but PDG picture seems so far to CPU

2

close to package as possible but PDG picture seems so far to CPU

Place on opposite of CPU Side 1uF* 6 + 1uF*3 reserve 10uF* 2

10U_0402_6.3V6M

CC235

1

2

CC392

0.1U_0201_10V6K

Deciphered Date

2

1

1 1

+1.05V_VCCST

1U_0201_6.3V6M

1

2

+1.05VS_VCCSTG

1U_0201_6.3V6M

1

2

10U_0402_6.3V6M

CC236

1

2

1

+1.05VS_VCCSTG_OUT_FUSE

1U_0201_6.3V6M

CC267

1

@

2

Follow 573129 RVP reserve

T446TP@

T447TP@ T448TP@

1U_0201_6.3V6M

CC274

CC271

1

@

2

CC272

CC275

1U_0201_6.3V6M

1

2

@

1U_0201_6.3V6M

CC289

1

2

+1.05V_VCCIO_OUT

reserve more

1

2

CC35

10U_0402_6.3V6M

1

2

@

1U_0201_6.3V6M

CC290

1

2

+1.8V_PRIM_SOC

+1.05VS_VCCSTG_OUT_FUSE

+1.05VO_VCCPLL

+1.2V_VCCPLL_OC

+1.8V_PRIM_SOC

10U_0402_6.3V6M

CC34

@

CC291

10U_0402_6.3V6M

22U_0603_6.3V6K

1

CC207

2

close to BGA

1U_0201_6.3V6M

CC292

CC293

1

2

Title

Size

Date: Sheet o f

CC208

2

@

PWR gate path to BGA

close to package as possible

1U_0201_6.3V6M

1

2

Document Number Re v

1U_0201_6.3V6M

CC295

CC294

CC296

1

@

2

Compal Electronics, Inc.

ICL-U(10/13)Power

LA-LJ551PR02

+1.05VO_VCCPLL

1U_0201_6.3V6M

CC273

CC270

1

2

@

close to package as possible but PDG picture seems so far to CPU

+1.2V_VCCPLL_OC

1U_0201_6.3V6M

CC276

CC278

1

@

2

1U_0201_6.3V6M

CC297

1

@

2

16 67Thursday, August 22, 2019

1

16 67Thursday, August 22, 2019

0.2

5

www.forums-fastunlock.com

4

3

2

1

LC15

@

1 2

0.6UH_TMPC0412HP-R60MG-Z02_6A_20%

SH000019M00

1 2

@

RC246 0_0402_5%

D D

1

CC36 22U_0603_6.3V6K

2

+3VALW

135 4mA

+3VALW

1

CC106

4.7U_0402_6.3V6M

2

C C

+3VALW

+1.8VALW

3 mA

+3VALW

B B

+VCCIN_AUX

12

@

26000 mA

CC373

100P_0402_50V8J

CC374

100P_0402_50V8J

CC379

1

RF@

2

100P_0402_50V8J

1

RF@

@RF@

2

+VCCIN_AUX +3VALW

RF reserve

500 mA500 mA

12

@

100K_0402_5%

R3054

100K_0402_5%

R3053

VCCIN_AUX_VCCSENSE59 VCCIN_AUX_VSSSENSE59

+1.05VO_EXTBYPASS

+1.05VO_VNNBYPASS

NOT E: Need to follow SPI ROM Voltage

+1.8V_VCCA_CLKLDO+1.8VALW

RC248 needs stuff 100 ohm when stuff L15

RC248 0_0402_5%

@

1 2

1

2

AH1

AW10

AY11

AY9

BA10

BB9

CH1 CK11 CL10 CM11

CN1

AJ1 CN10 CP11 CR10 CT11 CU10

CV1

CV11

CW10

CY11

DC1

AL1

P13

R12

T13

U12 DC11 DE12 DF12

AM1 AN1

AT11

AT9

AU10

AV9

BF9

BD9

DJ15

CY34

DC33

DD35

DB34

1

CC298

1U_0201_6.3V6M

@

2

CC246 22U_0603_6.3V6K

use 22u x2 to replace 47ux1

UC1N

VCCIN_AUX_1 VCCIN_AUX_2 VCCIN_AUX_3 VCCIN_AUX_4 VCCIN_AUX_5 VCCIN_AUX_6 VCCIN_AUX_7 VCCIN_AUX_8 VCCIN_AUX_9 VCCIN_AUX_10 VCCIN_AUX_11 VCCIN_AUX_12 VCCIN_AUX_13 VCCIN_AUX_14 VCCIN_AUX_15 VCCIN_AUX_16 VCCIN_AUX_17 VCCIN_AUX_18 VCCIN_AUX_19 VCCIN_AUX_20 VCCIN_AUX_21 VCCIN_AUX_22 VCCIN_AUX_23 VCCIN_AUX_24 VCCIN_AUX_25 VCCIN_AUX_26 VCCIN_AUX_27 VCCIN_AUX_28 VCCIN_AUX_29 VCCIN_AUX_30 VCCIN_AUX_31 VCCIN_AUX_32 VCCIN_AUX_33 VCCIN_AUX_34 VCCIN_AUX_35 VCCIN_AUX_36

VCCIN_AUX_VCCSENSE VCCIN_AUX_VSSSENSE

VCC_V1P05EXT_1P05

VCC_VNNEXT_1P05

VCCPRIM_3P3_1

VCCPRIM_1P8_1

VCCSPI

ICL-U_BGA1526

@

CPU POWER 3 OF 3

14 of 19

For RF team cross mote

+VCCIN +VCCIN_AUX

1 2

CC398 0.1U_0201_10V6K

RF@

202 mA (Include UC1.DC33)

VCCDSW_1P05

VCC1P05_1 VCC1P05_2 VCC1P05_3

VCCPLL

VCCRTC

VCCDSW_3P3

VCCPGPPR

DF23 DG26 DG28

1300 mA (Include UC1.DD35)

+1.8VALW

DF15 DF17 DF18 DF20 DG17 DG18 DG20 DF34

+0.85VO_VCCLDOSTD

DW37

DW15

DW32

DD34

BY2 CB2 CC1

CD1

DG31

DG29

DF29

DF31

DG33

DE31

DF26

VCCIN_AUX_CORE_VID0

CL38

VCCIN_AUX_CORE_VID1

CJ38

VCCIN_AUX_CORE_ALERT#

CN38

165 mA

+1.8V_VCCA_CLKLDO

+1.24VO_VCCDPHY

1 2

RC216 0_0402_5%@

1 2

RC217 0_0402_5%@

1 2

RC218 0_0402_5%@

+1.05VO_VCCDSW

+1.05VO_OUT_FET

+1.05VO_VCCPLL

VCCIN_AUX_CORE_VID0_R 11,59 VCCIN_AUX_CORE_VID1_R 11,59 VCCIN_AUX_CORE_ALERT#_R 7

VCCPRIM_3P3_2 VCCPRIM_3P3_3 VCCPRIM_3P3_4

VCCPRIM_1P8_2 VCCPRIM_1P8_3 VCCPRIM_1P8_4 VCCPRIM_1P8_5 VCCPRIM_1P8_6 VCCPRIM_1P8_7 VCCPRIM_1P8_8 VCCPRIM_1P8_9

VCCLDOSTD_0P85

VCCA_CLKLDO_1P8

VCCDPHY_1P24

VCCPRIM_1P05_1

VCCPRIM_1P05_2

VCCPRIM_1P05_3

VCCPRIM_1P05_4

GPP_B0/CORE_VID0 GPP_B1/CORE_VID1

GPP_B2/VRALERT#

NOT E: 572631 _ICL_P CH_ LP_ EDS_ Vol _1_ Rev_ 1p0 VCCPGPPR: Audio Power 3.3V, 1.8V, or 1.5V Need to sync with codec VDDIO.

572907 _ICL _UY _PD G_Re v1p 1 When configured as 3.3V or 1.8V, VCCPGPPR can be merged directly with either VCCPRIM_1P8 or VCCPRIM_3P3 depending on their operating voltage.

+1.05VO_OUT_PCH

RF

+3VALW

RF request

2 mA

+3VL_RTC

LC2

SD028000080

0_0402_5%

LC2

@RF@

1 2

BLM15BB221SN1D_2P_0402

SM01000BV00

4 mA

+3VALW

5 mA

+3V_1.8V_HDA

1

2

CC76

0.1U_0201_10V6K

@RF@

+1.8VALW

1U_0201_6.3V6M

1

2

near DG20

4

CC304

@

CC299 1U_0201_6.3V6M

+0.85VO_VCCLDOSTD

1

CC249

2.2U_0402_6.3V6M

2

+3VALW

near DE31

A A

5

1

CC365 1U_0201_6.3V6M

@

2

+1.05VO_VCCDSW

1

2

+3VALW

1

2

near DG26

0.1U_0201_10V6K CC254

1

2

@

near DF23

1U_0201_6.3V6M

CC301

@

+1.24VO_VCCDPHY

4.7U_0402_6.3V6M

1

2

CC252

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2019/05/15 2020/05/15

+RTCBATT +3VL_RTC

Compal Secret Data

RC141 0_0402_5%@

Deciphered Date

2

W=20mils

12

1U_0201_6.3V6M

0.1U_0201_10V6K

CC258

CC129

1

2

Compal Electronics, Inc.

Title

Size

Date: Sheet o f

Compal Electronics, Inc.

ICL-U(11/13)Power

Document Number Re v

LA-LJ551PR02

0.2

17 67Thursday, August 22, 2019

1

17 67Thursday, August 22, 2019

0.2

5

www.forums-fastunlock.com

4

3

2

1

BT3 BT39 BT41 BT42 BT43

BT7 BU45 BU47

BV1

BV11

BV2 BV3 BV7

BW3

BW37

BW5 BW6

BW7 BY37 BY45 BY49

C11 C13 C14 C17 C21 C24 C31 C34 C39 C48 C49

CA3 CA38 CA41 CA42 CA43

CA7 CB37 CB45 CB47

CC3

CC7 CE37 CE45 CE49

CE9 CG37 CG39 CG43 CG45 CG47

CG9

CH3

CH5

CJ37 CJ42

CJ9 CK45 CK49

CK9 CL37 CL42 CL49

CM45 CM47

CM9

CN3 CN37 CN39

CN5

CP9 CR32

C6

UC1P

GND 2 OF 3

VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222

16 of 19

ICL-U_BGA1526

@

VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 VSS_244 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_253 VSS_254 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296

CR37 CR45 CR49 CT37 CT39 CT42 CT9 CU45 CU47 CU49 CV3 CV34 CV35 CV5 CV9 CY41 CY45 CY49 CY9 D13 D17 D31 D44 D49 DA10 DA33 DA9 DB32 DB35 DB38 DB45 DB47 DB49 DC3 DC49 DC5 DC6 DD37 DD42 DE10 DE13 DE17 DE18 DE20 DE22 DE23 DE26 DE28 DE29 DE33 DE45 DE6 DF13 DF22 DF28 DF33 DF35 DF39 DG10 DG12 DG13 DG15 DG22 DG23 DG47 DG6 DH1 DH3 DH45 DH5 DJ19 DJ21 DJ27 DJ31

DJ33 DJ36 DJ42

DK3 DK4

DK49

DK6

DK8 DL10 DL13 DL44 DL47

DM47 DN15 DN19 DN24 DN31 DN36 DN42

DP45

DR49

DT1 DT10 DT15 DT20 DT27

DT3 DT32 DT37 DT42 DT49

DT6

DT7

DT8

DU1

DU10 DU15

DU2

DU20 DU27 DU32 DU37 DU48 DU49

DU7

DV2 DV44 DV48

DV8

DW1

DW10

DW2 DW20 DW27 DW44 DW46 DW48 DW49

DW7

E11 E34 E36 E39 E42

E6

UC1Q

GND 3 OF 3

VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325 VSS_326 VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350 VSS_351 VSS_352 VSS_353 VSS_354 VSS_355 VSS_356 VSS_357 VSS_358 VSS_359 VSS_360 VSS_361

17 of 19

ICL-U_BGA1526

@

VSS_362 VSS_363 VSS_364 VSS_365 VSS_366 VSS_367 VSS_368 VSS_369 VSS_370 VSS_371 VSS_372 VSS_373 VSS_374 VSS_375 VSS_376 VSS_377 VSS_378 VSS_379 VSS_380 VSS_381 VSS_382 VSS_383 VSS_384 VSS_385 VSS_386 VSS_387 VSS_388 VSS_389 VSS_390 VSS_391 VSS_392 VSS_393 VSS_394 VSS_395 VSS_396 VSS_397 VSS_398 VSS_399 VSS_400 VSS_401 VSS_402 VSS_403 VSS_404 VSS_405 VSS_406 VSS_407 VSS_408 VSS_409 VSS_410 VSS_411 VSS_412 VSS_413 VSS_414 VSS_415 VSS_416 VSS_417 VSS_418 VSS_419 VSS_420 VSS_421 VSS_422 VSS_423 VSS_424 VSS_425 VSS_426 VSS_427

F11 F31 F45 F47 F8 G21 G24 G3 G31 G36 G49 G5 H17 H21 H24 H31 H33 H36 H45 H49 J10 J13 J16 J36 J6 K11 K33 K8 L36 L39 L41 L42 L43 L45 L47 M10 M3 M36 M5 N45 N49 P11 P41 P8 R3 R37 T11 T36 T41 T43 T45 T47 U3 U37 U5 V11 V36 V45 V49 V9 W37 Y36 Y38 Y43 Y9 DE15

UC1O

GND 1 OF 3

A11

VSS_1

A46

VSS_2

BA45

VSS_3

BA47

VSS_4

BB11

VSS_5

BB3

VSS_6

BB7

D D

C C

B B

A A

BC37

BD3 BD38 BD39 BD41

A48 BD42 BD43 BD45 BD49

BD5 BD6 BD7

BE1

BE2

BF3

A49

BF45 BF47

BF7

BG3

BG41

BG7

BH37

BJ1

BJ2

BJ3 AA45

BJ41 BJ43 BJ45 BJ49

BJ7 BM11

BM3 BM45 BM47

BM5 AA47

BM6

BM7

BP1 BP2 BP3

BP43

BP7 BR45 BR49 AB11

AB3 AB38 AB39 AB41

A17 AB42 AB43

AB5

AB6 AC45 AC49 AD10 AD11 AD34 AD37

AE6

AF37

A3

VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74

15 of 19

ICL-U_BGA1526

@

VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98

VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148

AF45 AF47 AG1 AG11 AG3 AG38 AG39 AG41 A31 AG42 AG43 AG5 AG9 AH2 AH37 AH45 AH49 AJ2 AJ3 A34 AK37 AL2 AL45 AL47 AL6 AM2 AM37 AN2 AN38 AN39 A36 AN41 AN42 AN43 AN45 AN49 AN6 AR1 AR11 AR2 AR3 A39 AR7 AR9 AT3 AT45 AT47 AT5 AT6 AT7 AU37 AV11 A42 AV3 AV38 AV39 AV41 AV42 AV43 AV45 AV49 AV7 AY3 A44 AY7 B17 B2 B21 B24 B3 B31 B48 BA1 BA2

5

4

Security Classification

2019/05/15 2020/05/15

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2019/05/15 2020/05/15

3

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size

Document Number Re v

Date : Sheet o f

Compal Electronics, Inc.

ICL-U(12/13)GND

LA-LJ551PR02

18 67Thursday, August 22, 2019

1

0.2

5

www.forums-fastunlock.com

D D

C C

1 2

RC344 1K_0402_5%

1 2

RC341 51_0402_5%

1 2

RC342 51_0402_5%

CFG 4 Display port presence strap 0 : Enable An external display port device is connected to the embedded displayport 1 : Disable

B B

No physical display port attached to embedded display port

CFG4

CFG16

CFG18

12

RC210

49.9_0402_1%

4

T494 TP@ T495 TP@ T291 TP@ T290 TP@

RVP To MIPI60

1 1 1 1

T288 TP@ T289 TP@

+1.05V_VCCIO_OUT

RC556

100_0402_1%

CFG4

CFG16

CFG18

CFG_RCOMP

BPM#0 BPM#1 BPM#2 BPM#3

1

SKTOCC# PROC_SELECT#

1

12

AG6 AE7 AG7 AD9 AE9 AB9

AJ6

AB7

V10 AJ5 Y10 AJ7

AB10

AL7 AL9 AJ9

AD6

T10

BJ11 BL10

AV1

AT2 AT1 AU1 AU2

AV2

DP3 DT2

AR10 AP10 BP36 BM36

J15 K15

V6 V7

Y6 Y7

T9 T7

T6

C5 D4 A5

UC1S

CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15

CFG_16 CFG_17

CFG_18 CFG_19

CFG_RCOMP

BPM#0 BPM#1 BPM#2 BPM#3

RSVD_62 RSVD_63

RSVD_TP_17

RSVD_TP_18 RSVD_TP_20 RSVD_TP_19 RSVD_TP_21

RSVD_TP_22

RSVD_67 RSVD_68

RSVD_69 RSVD_71 RSVD_70 RSVD_72

VSS_430 VSS_431

SKTOCC# RSVD_77 RSVD_64

ICL-U_BGA1526

@

3

RESERVED SIGNALS

19 of 19

RSVD_TP_1 RSVD_TP_2

RSVD_57 RSVD_58

RSVD_TP_10 RSVD_TP_11

RSVD_79 RSVD_80

RSVD_TP_5 RSVD_TP_6

VSS_428 VSS_429

RSVD_55 RSVD_56

RSVD_65 RSVD_66

RSVD_59 RSVD_60

RSVD_TP_13 RSVD_TP_14

RSVD_TP_24 RSVD_TP_25

RSVD_TP_15 RSVD_TP_16

TP_3 TP_4

RSVD_TP_12

RSVD_TP_7 RSVD_TP_8

RSVD_TP_9

RSVD_TP_23

TP_1 TP_2

VSS_432

RSVD_TP_26

A47 B47

C1 E1

CT32 CV32

G15 F15

BW11 CA11

C16 A16

C2 A4

DP5 DR5

D14 E16

DV6 DW6

DP2 DP1

DW4 DV4

CM33 DB10

R1

DW3 DV3

DH49

DL8

DW47 DV47 DU47

P10

2

UC1R

N34 AK10 BT36 AH10 BC10

CH33

CJ32

AM10

BH10

J34

Y11 L34

AJ11

CG32

CK33 BP41

AL11

BG11

AN11

M13

M34

DU42

DW42

D33

L13

K13

RSVD_TP_28 RSVD_TP_29 RSVD_7 RSVD_TP_30 RSVD_TP_31 RSVD_TP_32

RSVD_12 RSVD_TP_33 RSVD_TP_34 RSVD_TP_27

RSVD_9 RSVD_10

RSVD_17 RSVD_21

RSVD_22 RSVD_20 RSVD_23 RSVD_24 RSVD_16 RSVD_18 RSVD_19

RSVD_42 RSVD_43 RSVD_44 RSVD_45 RSVD_47

ICL-U_BGA1526

@

RESERVED SIGNALS

RSVD_TP_35 RSVD_TP_36 RSVD_TP_37

RSVD_32 RSVD_33 RSVD_34

IST_TP_0

IST_TP_1 IST_TRIG_0 IST_TRIG_1

PCH_IST_TP_0 PCH_IST_TP_1

RSVD_27

RSVD_28

RSVD_35

RSVD_46

RSVD_48

RSVD_49

RSVD_50

RSVD_51

RSVD_52

RSVD_53

RSVD_54

RSVD_36

RSVD_37

RSVD_38

RSVD_39

RSVD_40

RSVD_41

DA11 CL32 CN32 CY35 DB37 DF37

BF11 BD11 BE10 BF10

CW33 CY32

CY37 CV37

G34 H34 DJ34 DK31 DK15 CP3 CP5 AN9 AN7 AF10 AE11 H5 D1 DJ40 DK40

1

A A

Security Classification

2019/05/15 2020/05/15

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2019/05/15 2020/05/15

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

Document Number Re v

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

ICL-U(13/13)RSVD,CFG

LA-LJ551PR02

19 67Thursday, August 22, 2019

1

0.2

5

www.forums-fastunlock.com

D D

C C

4

3

2

1

B B

A A

Security Classification

2019/05/15 2020/05/15

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2019/05/15 2020/05/15

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

B

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

Reserve

Document Number Re v

LA-LJ551PR02

20 67Thursday, August 22, 2019

1

0.2

5

www.forums-fastunlock.com

D D

C C

4

3

2

1

B B

A A

Security Classification

2019/05/15 2020/05/15

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2019/05/15 2020/05/15

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

B

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

Reserve

Document Number Re v

LA-LJ551PR02

21 67Thursday, August 22, 2019

1

0.2

Lenovo Xiaoxin AIR-14IIL 2020 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual