Lenovo X380 Schematic

A

1 1

B

C

D

E

Compal Confidential

2 2

STORM3 M/B Schematic

LA-F421P

Rev: 1.0_ B

2017.10.23

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/11/04 2016/12/31

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

COVER PAGE

Size Document Number Rev

Custom

LA-F421P

Date: Sheet

E

of

1 73Monday, October 23, 2017

1.0

5

4

3

2

1

STORM 3 Block-Diagram

Two Channel

eDP Conn.

D D

P.26

2-Ch. SPK Conn.

4 Lane

P.39

DMIC

Audio Codec

P.35

eDP

HDA

USB2.0

USB3.0

Combo Jack Conn.

Sub/B

4 Lane TBT

Type C Conn.

C C

P.50

USB 2.0

HDMI Conn.

P.29

PD

P.51

USB 2.0

4 Lane

Intel Alpine Ridge

Mux

P.28

4 Lane

PCIEx2

P.47

DDI1

Intel Kabylake RU/U-Processor

P.4

I2C

DDI2

USB2.0

PCI-E

(A) DDR4 memory down 2400MHz

(B) DDR4 memory down 2400MHz

P.22

P.24

Maximum 16GB

USB 3.0 Conn AOU5

P.31

USB 3.0 Conn.

P.31

ALS

Sub board

WLAN & BT

M.2 Conn.

PCIEx1 USB 2.0(BT)

P.32

(WLAN)

SPI

LPC

SPI

BIOS ROM

WWAN

P.32

P.52

PCIEx1

USB 2.0

PCIEx1

B B

Mini RJ45

P.52

M.2 Conn.

Intel LAN

16M

P.21

I2C

EC

P.53

Int.KBD

M.2 Conn.

SSD [M.2 2280/2242]

Micro SD Card Reader

A A

Slot Conn.

P.33

Card Reader

SATA/PCIEx1

P.30

P.33

PCIEx3

PCIEx1

Click Pad

Track Point

P.43

P.42

Accelerometer(2)

P.41

5

4

3

USB2.0

FPR

TPM

P.45

P.42

LID

Sub/B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DMIC

2014/11/04 2016/12/31

P.34

Touch Panel

Smart Card

P.26

P.34

P.26

Camera & DMIC

DMIC

Compal Secret Data

Deciphered Date

2

IR Camera

Accelerometer & Gyro

eCompass

Accelerometer(1)

P.41

SMBUS

P.27

NFC

Option

Compal Electronics, Inc.

Title

BLOCK DIAGRAM

Size Document Number Rev

Custom

LA-F421P

Date: Sheet

1

P.43

1.0

of

2 73Monday, October 23, 2017

5

[Storm3 PWR Sequence_KBL-RU_DDR4_Non-Deep Sx]

4

3

2

1

D D

C C

B B

[AC Mode]

AC_IN

VINT12

VCC3SW

EN_3V

VCC3M/VCC5M

VCC1R0_SUS

SUS_ON1

VCC1R8_PRIM

-PWRSWITCH

-PWRSW_EC_R

-RSMRST

-SUSWARN

AC_PRESENT

moniter AC_IN (51_ON)

Moniter ON/OFFBTN# rising edge

20ms

-PCH_SLP_S5

-PCH_SLP_S4

-PCH_SLP_S3

A_ON

+VCC2R5A

+VCC1R2A

DDR_PG_CTRL

+VCC0R6B

B_ON After PM_SLP_S3# moniter SYSON rising edge.

VCC5B

VCC3B

EC_VCCST_PG

VR_ON

VCCCPUCORE

VGATE

BPWRG After VCCST_PG_EC assertion

-PLTRST

Montier PBTN_OUT# falling edge.

T=20ms

immediately, VCCST_PG_PWR & VCCST_PG_EC risign edge

[DC Mode]

BAT-PWR12

AC_PRESENT

VINT12

VCC3SW

-PWRSWITCH

SUS_ON2 Moniter ON/OFFBTN#

VCC3M/VCC5M

VCC1R0_SUS

SUS_ON1

VCC1R8_PRIM

-RSMRST

-SUSWARN

-PWRSW_EC_R

After SUSP# risign edge

Vboot

T=10ms

After VCCST_PG_EC rising edgePCH_PWROK

T=99ms

After CPUPWRGD/PCH_PWRGD/SYS_PWROK assertion

T=10ms

Moniter ON/OFFBTN# and EN_3/5V both of risgin edge

T=10ms

T=110ms

20ms

immediately, After PM_SLP_S4# falling edge

immediately, After PM_SLP_S3# falling edge

immediately, After SUSP# falling edge

Moniter ON/OFFBTN# rising edge

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

Compal Secret Data

Deciphered Date

2016/03/21 2017/03/01

Deciphered Date

Compal Electronics, Inc.

Title

Power Sequence

Size Document Number Rev

Size Document Number Rev D

D

LA-F421P

Date: Sheet

1

3 73Monday, October 23, 2017

of

1.0

5

D D

4

3

2

1

VCCCPUIO

DDIP1_0N[47] DDIP1_0P[47] DDIP1_1N[47]

C C

DDIP1_1P[47] DDIP1_2N[47] DDIP1_2P[47] DDIP1_3N[47] DDIP1_3P[47]

DDIP2_0N[28] DDIP2_0P[28] DDIP2_1N[28] DDIP2_1P[28] DDIP2_2N[28] DDIP2_2P[28] DDIP2_3N[28] DDIP2_3P[28]

DDIP1_0N DDIP1_0P DDIP1_1N DDIP1_1P DDIP1_2N DDIP1_2P DDIP1_3N DDIP1_3P

DDIP2_0N DDIP2_0P DDIP2_1N DDIP2_1P DDIP2_2N DDIP2_2P DDIP2_3N DDIP2_3P

TABLE : Functional Strap

DDPB_CTRLDATA

DDIP2_CTRLCLK[28]

DDIP2_CTRLDATA[28]

DDIP2_CTRLCLK DDIP2_CTRLDATA

HIGH Port B is detected.

LOW Port B is not detected.

DDPC_CTRLDATA

B B

HIGH Port C is detected.

R5

24.9_0201_1%

1 2

EDP_COMP

VCC3B

1 2

R9357

2.2K_0201_5%

E55

DDI1_TXN[0]

F55

DDI1_TXP[0]

E58

DDI1_TXN[1]

F58

DDI1_TXP[1]

F53

DDI1_TXN[2]

G53

DDI1_TXP[2]

F56

DDI1_TXN[3]

G56

DDI1_TXP[3]

C50

DDI2_TXN[0]

D50

DDI2_TXP[0]

C52

DDI2_TXN[1]

D52

DDI2_TXP[1]

A50

DDI2_TXN[2]

B50

DDI2_TXP[2]

D51

DDI2_TXN[3]

C51

DDI2_TXP[3]

L13

GPP_E18/DDPB_CTRLCLK

L12

GPP_E19/DDPB_CTRLDATA

N7

GPP_E20/DDPC_CTRLCLK

N8

GPP_E21/DDPC_CTRLDATA

N11

GPP_E22/DDPD_CTRLCLK

N12

GPP_E23/DDPD_CTRLDATA

E52

EDP_RCOMP

U58A

@

KBL-RU_BGA1356

SKL-U

DDI

DISPLAY SIDEBANDS

1 OF 20

EDP

EDP_TXN[0] EDP_TXP[0] EDP_TXN[1] EDP_TXP[1] EDP_TXN[2] EDP_TXP[2] EDP_TXN[3] EDP_TXP[3]

EDP_AUXN EDP_AUXP

EDP_DISP_UTIL

DDI1_AUXN DDI1_AUXP DDI2_AUXN DDI2_AUXP DDI3_AUXN DDI3_AUXP

GPP_E13/DDPB_HPD0 GPP_E14/DDPC_HPD1 GPP_E15/DDPD_HPD2 GPP_E16/DDPE_HPD3

GPP_E17/EDP_HPD

EDP_BKLTEN

EDP_BKLTCTL

EDP_VDDEN

C47 C46 D46 C45 A45 B45 A47 B47

E45 F45

B52

G50 F50 E48 F48 G46 F46

L9 L7 L6 N9 L10

R12 R11 U13

R433

100K_0201_5%

1 2

R138

100K_0201_5%

EDP_TXN0 EDP_TXP0 EDP_TXN1 EDP_TXP1 EDP_TXN2 EDP_TXP2 EDP_TXN3 EDP_TXP3

EDP_AUXN EDP_AUXP

DDIP1_AUXN DDIP1_AUXP

EDP_TXN0 [26] EDP_TXP0 [26] EDP_TXN1 [26] EDP_TXP1 [26] EDP_TXN2 [26] EDP_TXP2 [26] EDP_TXN3 [26] EDP_TXP3 [26]

EDP_AUXN [26] EDP_AUXP [26]

DDIP1_AUXN [47] DDIP1_AUXP [47]

FVT_C_EC010

DDIP1_HPD DDIP2_HPD

R8 100K_0201_5%

1 2

DDIP1_HPD [47] DDIP2_HPD [28]

EDP_HPD [26]

VGA_BLON [53] PANEL_BKLT_CTRL [26] PANEL_POWER_ON [26]

LOW Port C is not detected.

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/11/04 2016/12/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

CPU(1/16) : DDI/EDP

Size Document Number Rev

Custom

LA-F421P

Date: Sheet

1

of

4 73Monday, October 23, 2017

1.0

5

Storm3 Power tree

4

TPS51285B-1RUKR TI

3

VCC5M / 7A

VCC3M / 7A

RT8061AZQW Richtek

2

VCC2R5A / 0.8A

VCC1R8_SUS / 0.8A

1

D D

PU1

VINT20

C C

Charger (BQ25700)

VINT12

VCC5M

VINT12

PU41

B B

VCC3M

TPS51362RVER TI Converter

RT8207PGQW Richtek

NCP81218MNTXG + NCP302045MNTWG Dr-MOS On-semi

NCP81218MNTXG + NCP302035MNTWG Dr-MOS On-semi

VCCST

U143

VCC2R5A

PU151

VCC1R2A

PU118

VCC1R8_PRIM

PU145

USB_PWR_S2

U53

USB_PWR_S1

U88

VCC5M_BUTTON

R9570

VCC5M_PD

J9237

VCC3_SUS

PU154

VCC3M_PEN

F31

VCC3M_SENS_CN

F34

VCC3M_IR

F39

VCC3M_KEY_CONN

F25

VCC3M_BUTTON

R9309

VCC3M_PCH

R2485

VCC3_TBT

R9406

VCC3M_PD

RT9369

VCC3WLAN

U19

VCC3LAN

U153

U55

A A

5

4

VCC1R0_SUS_P / 7.12A

VCC1R2A / 6.4A

VCC0R6B / 0.8A

VCCCPUCORE U22: 21A U42: 42A

VCCGFXCORE_I / 18A

VCCSA / 4A

VCC5B

VCC3B

3

U110

F40

F35

F23

F4

F15

R2031

R2015

R2029

R2463

J9240

F24

F17

F8

F41

U9

R2472

2

VCC5B_HDMI

VCC5B_IR VCC5B_CN

VCC5_TP

VCC5B_F4

FUSEVCC5B VCC5B_CODEC VCC5BA

VCC3B_PS8337B

VCC3WAN VCC3B_TOUCH_CN

FUSEVCC3B

FUSEVCC3FP

VCC3B_IR VCC3B_CODEC

VCC3P

VCC3B_RTS5236S

Security Classification

2015/06/09 2016/12/31

2015/06/09 2016/12/31 Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Power MAP

Size Document Number Rev

Size Document Number Rev Custom

Custom

LA-F483P

Date: Sheet

Monday, October 23, 2017

1

of

4

of

4

of

4

0.1

44

5

DDR_A_D[63:0][6,22]

DDR_B_D[63:0][6,24]

D D

TABLE

4

3

2

1

Pin Interleave Non-Interleave

U58B

TABLE

AL71

AL68 AN68 AN69

AL70

AL69 AN70 AN71 AR70 AR68 AU71 AU68 AR71 AR69 AU70 AU69 BB65 AW65 AW63 AY63 BA65 AY65 BA63 BB63 BA61 AW61 BB59 AW59 BB61 AY61 BA59 AY59 AY39 AW39 AY37 AW37 BB39 BA39 BA37 BB37 AY35 AW35 AY33 AW33 BB35 BA35 BA33 BB33 AY31 AW31 AY29 AW29 BB31 BA31 BA29 BB29 AY27 AW27 AY25 AW25 BB27 BA27 BA25 BB25

Block 0

Block 2

Block 4

Block 6

@

DDR0_DQ[0] DDR0_DQ[1] DDR0_DQ[2] DDR0_DQ[3] DDR0_DQ[4] DDR0_DQ[5] DDR0_DQ[6] DDR0_DQ[7] DDR0_DQ[8] DDR0_DQ[9] DDR0_DQ[10] DDR0_DQ[11] DDR0_DQ[12] DDR0_DQ[13] DDR0_DQ[14] DDR0_DQ[15] DDR0_DQ[16]/DDR0_DQ[32] DDR0_DQ[17]/DDR0_DQ[33] DDR0_DQ[18]/DDR0_DQ[34] DDR0_DQ[19]/DDR0_DQ[35] DDR0_DQ[20]/DDR0_DQ[36] DDR0_DQ[21]/DDR0_DQ[37] DDR0_DQ[22]/DDR0_DQ[38] DDR0_DQ[23]/DDR0_DQ[39] DDR0_DQ[24]/DDR0_DQ[40] DDR0_DQ[25]/DDR0_DQ[41] DDR0_DQ[26]/DDR0_DQ[42] DDR0_DQ[27]/DDR0_DQ[43] DDR0_DQ[28]/DDR0_DQ[44] DDR0_DQ[29]/DDR0_DQ[45] DDR0_DQ[30]/DDR0_DQ[46] DDR0_DQ[31]/DDR0_DQ[47] DDR0_DQ[32]/DDR1_DQ[0] DDR0_DQ[33]/DDR1_DQ[1] DDR0_DQ[34]/DDR1_DQ[2] DDR0_DQ[35]/DDR1_DQ[3] DDR0_DQ[36]/DDR1_DQ[4] DDR0_DQ[37]/DDR1_DQ[5] DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQ[41]/DDR1_DQ[9] DDR0_DQ[42]/DDR1_DQ[10] DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQ[44]/DDR1_DQ[12] DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQ[46]/DDR1_DQ[14] DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQ[54]/DDR1_DQ[38] DDR0_DQ[55]/DDR1_DQ[39] DDR0_DQ[56]/DDR1_DQ[40] DDR0_DQ[57]/DDR1_DQ[41] DDR0_DQ[58]/DDR1_DQ[42] DDR0_DQ[59]/DDR1_DQ[43] DDR0_DQ[60]/DDR1_DQ[44] DDR0_DQ[61]/DDR1_DQ[45] DDR0_DQ[62]/DDR1_DQ[46] DDR0_DQ[63]/DDR1_DQ[47]

KBL-RU_BGA1356

Pin Interleave Non-Interleave

AM70 AM69 AT69 AT70

BA64 AY64 AY60 BA60

BA38 AY38 AY34 BA34

BA30 AY30 AY26 BA26

DDR0_DQ[0]

AL71

DDR0_DQ[1]

AL68

DDR0_DQ[2]

AN68

DDR0_DQ[3]

AN69

DDR0_DQ[4]

AL70

DDR0_DQ[5]

AL69

DDR0_DQ[6]

AN70

DDR0_DQ[7]

AN71

DDR0_DQ[8]

AR70

DDR0_DQ[9]

AR68

Block 0

C C

Block 2

Block 4

B B

Block 6

A A

AU71 AU68 AR71 AR69 AU70 AU69

BB65 AW65 AW63 AY63 BA65 AY65 BA63 BB63 BA61 AW61 BB59 AW59 BB61 AY61 BA59 AY59

AY39 AW39 AY37 AW37 BB39 BA39 BA37 BB37 AY35 AW35 AY33 AW33 BB35 BA35 BA33 BB33

AY31 AW31 AY29 AW29 BB31 BA31 BA29 BB29 AY27 AW27 AY25 AW25 BB27 BA27 BA25 BB25

DDR0_DQ[10] DDR0_DQ[11] DDR0_DQ[12] DDR0_DQ[13] DDR0_DQ[14] DDR0_DQ[15]

DDR0_DQ[16] DDR0_DQ[17] DDR0_DQ[18] DDR0_DQ[19] DDR0_DQ[20] DDR0_DQ[21] DDR0_DQ[22] DDR0_DQ[23] DDR0_DQ[24] DDR0_DQ[25] DDR0_DQ[26] DDR0_DQ[27] DDR0_DQ[28] DDR0_DQ[29] DDR0_DQ[30] DDR0_DQ[31]

DDR0_DQ[32] DDR0_DQ[33] DDR0_DQ[34] DDR0_DQ[35] DDR0_DQ[36] DDR0_DQ[37] DDR0_DQ[38] DDR0_DQ[39] DDR0_DQ[40] DDR0_DQ[41] DDR0_DQ[42] DDR0_DQ[43] DDR0_DQ[44] DDR0_DQ[45] DDR0_DQ[46] DDR0_DQ[47]

DDR0_DQ[48] DDR0_DQ[49] DDR0_DQ[50] DDR0_DQ[51] DDR0_DQ[52] DDR0_DQ[53] DDR0_DQ[54] DDR0_DQ[55] DDR0_DQ[56] DDR0_DQ[57] DDR0_DQ[58] DDR0_DQ[59] DDR0_DQ[60] DDR0_DQ[61] DDR0_DQ[62] DDR0_DQ[63]

DDR0_DQ[0] DDR0_DQ[1] DDR0_DQ[2] DDR0_DQ[3] DDR0_DQ[4] DDR0_DQ[5] DDR0_DQ[6] DDR0_DQ[7] DDR0_DQ[8] DDR0_DQ[9] DDR0_DQ[10] DDR0_DQ[11] DDR0_DQ[12] DDR0_DQ[13] DDR0_DQ[14] DDR0_DQ[15]

DDR0_DQ[32] DDR0_DQ[33] DDR0_DQ[34] DDR0_DQ[35] DDR0_DQ[36] DDR0_DQ[37] DDR0_DQ[38] DDR0_DQ[39] DDR0_DQ[40] DDR0_DQ[41] DDR0_DQ[42] DDR0_DQ[43] DDR0_DQ[44] DDR0_DQ[45] DDR0_DQ[46] DDR0_DQ[47]

DDR1_DQ[0] DDR1_DQ[1] DDR1_DQ[2] DDR1_DQ[3] DDR1_DQ[4] DDR1_DQ[5] DDR1_DQ[6] DDR1_DQ[7] DDR1_DQ[8] DDR1_DQ[9] DDR1_DQ[10] DDR1_DQ[11] DDR1_DQ[12] DDR1_DQ[13] DDR1_DQ[14] DDR1_DQ[15]

DDR1_DQ[32] DDR1_DQ[33] DDR1_DQ[34] DDR1_DQ[35] DDR1_DQ[36] DDR1_DQ[37] DDR1_DQ[38] DDR1_DQ[39] DDR1_DQ[40] DDR1_DQ[41] DDR1_DQ[42] DDR1_DQ[43] DDR1_DQ[44] DDR1_DQ[45] DDR1_DQ[46] DDR1_DQ[47]

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47

SKL-U

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]

DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]

DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]

DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]

DDR CH - A

2 OF 20

DDR0_DQSN[0] DDR0_DQSP[0] DDR0_DQSN[1] DDR0_DQSP[1]

DDR0_DQSN[2] DDR0_DQSP[2] DDR0_DQSN[3] DDR0_DQSP[3]

DDR0_DQSN[4] DDR0_DQSP[4] DDR0_DQSN[5] DDR0_DQSP[5]

DDR0_DQSN[6] DDR0_DQSP[6] DDR0_DQSN[7] DDR0_DQSP[7]

DDR0_CKN[0] DDR0_CKP[0] DDR0_CKN[1] DDR0_CKP[1]

DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3]

DDR0_CS#[0] DDR0_CS#[1] DDR0_ODT[0] DDR0_ODT[1]

DDR0_MA[3] DDR0_MA[4]

DDR0_DQSN[0] DDR0_DQSP[0] DDR0_DQSN[1]

DDR0_DQSP[1] DDR0_DQSN[2]/DDR0_DQSN[4] DDR0_DQSP[2]/DDR0_DQSP[4] DDR0_DQSN[3]/DDR0_DQSN[5] DDR0_DQSP[3]/DDR0_DQSP[5] DDR0_DQSN[4]/DDR1_DQSN[0] DDR0_DQSP[4]/DDR1_DQSP[0] DDR0_DQSN[5]/DDR1_DQSN[1] DDR0_DQSP[5]/DDR1_DQSP[1] DDR0_DQSN[6]/DDR1_DQSN[4] DDR0_DQSP[6]/DDR1_DQSP[4] DDR0_DQSN[7]/DDR1_DQSN[5] DDR0_DQSP[7]/DDR1_DQSP[5]

DDR0_ALERT#

DDR0_PAR

DDR_VREF_CA

DDR0_VREF_DQ DDR1_VREF_DQ

DDR_VTT_CNTL

DDR0_DQSN[0] DDR0_DQSP[0] DDR0_DQSN[1] DDR0_DQSP[1]

DDR0_DQSN[4] DDR0_DQSP[4] DDR0_DQSN[5] DDR0_DQSP[5]

DDR1_DQSN[0] DDR1_DQSP[0] DDR1_DQSN[1] DDR1_DQSP[1]

DDR1_DQSN[4] DDR1_DQSP[4] DDR1_DQSN[5] DDR1_DQSP[5]

AU53 AT53 AU55 AT55

BA56 BB56 AW56 AY56

AU45 AU43 AT45 AT43

BA51 BB54 BA52 AY52 AW52 AY55 AW54 BA54 BA55 AY54

AU46 AU48 AT46 AU50 AU52 AY51 AT48 AT50 BB50 AY50 BA50 BB52

AM70 AM69 AT69 AT70 BA64 AY64 AY60 BA60 BA38 AY38 AY34 BA34 BA30 AY30 AY26 BA26

AW50 AT52

AY67 AY68 BA67

AW67

DDR_PG_CTRL

-DDR_A_CLK0 DDR_A_CLK0

DDR_A_CKE0

-DDR_A_CS0

DDR_A_ODT0

DDR_A_MA5 DDR_A_MA9 DDR_A_MA6 DDR_A_MA8 DDR_A_MA7 DDR_A_BG0 DDR_A_MA12 DDR_A_MA11

-DDR_A_ACT DDR_A_BG1

DDR_A_MA13 DDR_A_MA15 DDR_A_MA14 DDR_A_MA16 DDR_A_BA0 DDR_A_MA2 DDR_A_BA1 DDR_A_MA10 DDR_A_MA1 DDR_A_MA0 DDR_A_MA3 DDR_A_MA4

-DDR_A_DQS0 DDR_A_DQS0

-DDR_A_DQS1 DDR_A_DQS1

-DDR_A_DQS4 DDR_A_DQS4

-DDR_A_DQS5 DDR_A_DQS5

-DDR_B_DQS0 DDR_B_DQS0

-DDR_B_DQS1 DDR_B_DQS1

-DDR_B_DQS4 DDR_B_DQS4

-DDR_B_DQS5 DDR_B_DQS5

-DDR_A_ALERT DDR_A_PAR

+0.6V_A_VREFDQ

+0.6V_B_VREFDQ

1 2

@

R1858 10K_0201_5%

VCC1R2A

2

-DDR_A_CLK0 [22,23] DDR_A_CLK0 [22,23]

DDR_A_CKE0 [22,23]

-DDR_A_CS0 [22,23]

DDR_A_ODT0 [22,23]

DDR_A_BG0 [22,23]

-DDR_A_ACT [22,23] DDR_A_BG1 [22]

DDR_A_BA0 [22,23]

DDR_A_BA1 [22,23]

-DDR_A_DQS0 [22] DDR_A_DQS0 [22]

-DDR_A_DQS1 [22] DDR_A_DQS1 [22]

-DDR_A_DQS4 [22] DDR_A_DQS4 [22]

-DDR_A_DQS5 [22] DDR_A_DQS5 [22]

-DDR_B_DQS0 [24] DDR_B_DQS0 [24]

-DDR_B_DQS1 [24] DDR_B_DQS1 [24]

-DDR_B_DQS4 [24] DDR_B_DQS4 [24]

-DDR_B_DQS5 [24] DDR_B_DQS5 [24]

-DDR_A_ALERT [22,23] DDR_A_PAR [22,23]

+0.6V_A_VREFDQ [23]

+0.6V_B_VREFDQ [25]

VCC3M

R1838 100K_0201_5%

1 2

DDR_VTT_PG_CTRL

13

Q170 DTC015TMT2L_VMT3

DDR_A_MA[16:0] [22,23]

DDR_VTT_PG_CTRL [69]

TABLE

BA51 BB54 BA52 AY52 AW52 AY55 AW54 BA54 BA55 AY54

AU46 AU48 AT46 AU50 AU52 AY51 AT48 AT50 BB50 AY50 BA50 BB52

DDR3L LPDDR3 DDR4

DDR0_MA[5] DDR0_MA[9] DDR0_MA[6] DDR0_MA[8] DDR0_MA[7] DDR0_BA[2] DDR0_MA[12] DDR0_MA[11] DDR0_MA[15] DDR0_MA[14]

DDR0_MA[13] DDR0_CAS# DDR0_WE# DDR0_RAS# DDR0_BA[0] DDR0_MA[2] DDR0_BA[1] DDR0_MA[10] DDR0_MA[1] DDR0_MA[0] DDR0_MA[3] DDR0_MA[4]

DDR0_CAA[0] DDR0_CAA[1] DDR0_CAA[2] DDR0_CAA[3] DDR0_CAA[4] DDR0_CAA[5] DDR0_CAA[6] DDR0_CAA[7] DDR0_CAA[8] DDR0_CAA[9]

DDR0_CAB[0] DDR0_CAB[1] DDR0_CAB[2] DDR0_CAB[3] DDR0_CAB[4] DDR0_CAB[5] DDR0_CAB[6] DDR0_CAB[7] DDR0_CAB[8] DDR0_CAB[9] Not Used Not Used

DDR0_MA[5] DDR0_MA[9] DDR0_MA[6] DDR0_MA[8] DDR0_MA[7] DDR0_BG[0] DDR0_MA[12] DDR0_MA[11] DDR0_ACT# DDR0_BG[1]

DDR0_MA[13] DDR0_MA[15] DDR0_MA[14] DDR0_MA[16] DDR0_BA[0] DDR0_MA[2] DDR0_BA[1] DDR0_MA[10] DDR0_MA[1] DDR0_MA[0] DDR0_MA[3] DDR0_MA[4]

LOGIC

5

LOGIC LOGIC

4

LOGIC

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/11/04 2016/12/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

CPU(2/16) : DDR CHANNEL-A

Size Document Number Rev

Custom

LA-F421P

Monday, October 23, 2017

Date: Sheet

1

73

of

5

1.0

5

DDR_A_D[63:0][5,22]

DDR_B_D[63:0][5,24]

D D

TABLE

Pin Interleave Non-Interleave

DDR1_DQ[0]

AF65

DDR1_DQ[1]

AF64

DDR1_DQ[2]

AK65

DDR1_DQ[3]

AK64

DDR1_DQ[4]

AF66

DDR1_DQ[5]

AF67

DDR1_DQ[6]

AK67

DDR1_DQ[7]

AK66

DDR1_DQ[8]

AF70

DDR1_DQ[9]

AF68

Block 1

C C

Block 3

Block 5

B B

Block 7

A A

AH71 AH68 AF71 AF69 AH70 AH69

AT66 AU66 AP65 AN65 AN66 AP66 AT65 AU65 AT61 AU61 AP60 AN60 AN61 AP61 AT60 AU60

AU40 AT40 AT37 AU37 AR40 AP40 AP37 AR37 AT33 AU33 AU30 AT30 AR33 AP33 AR30 AP30

AU27 AT27 AT25 AU25 AP27 AN27 AN25 AP25 AT22 AU22 AU21 AT21 AN22 AP22 AP21 AN21

DDR1_DQ[10] DDR1_DQ[11] DDR1_DQ[12] DDR1_DQ[13] DDR1_DQ[14] DDR1_DQ[15]

DDR1_DQ[16] DDR1_DQ[17] DDR1_DQ[18] DDR1_DQ[19] DDR1_DQ[20] DDR1_DQ[21] DDR1_DQ[22] DDR1_DQ[23] DDR1_DQ[24] DDR1_DQ[25] DDR1_DQ[26] DDR1_DQ[27] DDR1_DQ[28] DDR1_DQ[29] DDR1_DQ[30] DDR1_DQ[31]

DDR1_DQ[32] DDR1_DQ[33] DDR1_DQ[34] DDR1_DQ[35] DDR1_DQ[36] DDR1_DQ[37] DDR1_DQ[38] DDR1_DQ[39] DDR1_DQ[40] DDR1_DQ[41] DDR1_DQ[42] DDR1_DQ[43] DDR1_DQ[44] DDR1_DQ[45] DDR1_DQ[46] DDR1_DQ[47]

DDR1_DQ[48] DDR1_DQ[49] DDR1_DQ[50] DDR1_DQ[51] DDR1_DQ[52] DDR1_DQ[53] DDR1_DQ[54] DDR1_DQ[55] DDR1_DQ[56] DDR1_DQ[57] DDR1_DQ[58] DDR1_DQ[59] DDR1_DQ[60] DDR1_DQ[61] DDR1_DQ[62] DDR1_DQ[63]

LOGIC

DDR0_DQ[16] DDR0_DQ[17] DDR0_DQ[18] DDR0_DQ[19] DDR0_DQ[20] DDR0_DQ[21] DDR0_DQ[22] DDR0_DQ[23] DDR0_DQ[24] DDR0_DQ[25] DDR0_DQ[26] DDR0_DQ[27] DDR0_DQ[28] DDR0_DQ[29] DDR0_DQ[30] DDR0_DQ[31]

DDR0_DQ[48] DDR0_DQ[49] DDR0_DQ[50] DDR0_DQ[51] DDR0_DQ[52] DDR0_DQ[53] DDR0_DQ[54] DDR0_DQ[55] DDR0_DQ[56] DDR0_DQ[57] DDR0_DQ[58] DDR0_DQ[59] DDR0_DQ[60] DDR0_DQ[61] DDR0_DQ[62] DDR0_DQ[63]

DDR1_DQ[16] DDR1_DQ[17] DDR1_DQ[18] DDR1_DQ[19] DDR1_DQ[20] DDR1_DQ[21] DDR1_DQ[22] DDR1_DQ[23] DDR1_DQ[24] DDR1_DQ[25] DDR1_DQ[26] DDR1_DQ[27] DDR1_DQ[28] DDR1_DQ[29] DDR1_DQ[30] DDR1_DQ[31]

DDR1_DQ[48] DDR1_DQ[49] DDR1_DQ[50] DDR1_DQ[51] DDR1_DQ[52] DDR1_DQ[53] DDR1_DQ[54] DDR1_DQ[55] DDR1_DQ[56] DDR1_DQ[57] DDR1_DQ[58] DDR1_DQ[59] DDR1_DQ[60] DDR1_DQ[61] DDR1_DQ[62] DDR1_DQ[63]

LOGIC

DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

4

U58C

AF65

DDR1_DQ[0]/DDR0_DQ[16]

AF64

DDR1_DQ[1]/DDR0_DQ[17]

AK65

DDR1_DQ[2]/DDR0_DQ[18]

AK64

DDR1_DQ[3]/DDR0_DQ[19]

AF66

DDR1_DQ[4]/DDR0_DQ[20]

AF67

DDR1_DQ[5]/DDR0_DQ[21]

AK67

DDR1_DQ[6]/DDR0_DQ[22]

AK66

DDR1_DQ[7]/DDR0_DQ[23]

AF70

DDR1_DQ[8]/DDR0_DQ[24]

AF68

DDR1_DQ[9]/DDR0_DQ[25]

AH71

DDR1_DQ[10]/DDR0_DQ[26]

AH68

DDR1_DQ[11]/DDR0_DQ[27]

AF71

DDR1_DQ[12]/DDR0_DQ[28]

AF69

DDR1_DQ[13]/DDR0_DQ[29]

AH70

DDR1_DQ[14]/DDR0_DQ[30]

AH69

DDR1_DQ[15]/DDR0_DQ[31]

AT66

DDR1_DQ[16]/DDR0_DQ[48]

AU66

DDR1_DQ[17]/DDR0_DQ[49]

AP65

DDR1_DQ[18]/DDR0_DQ[50]

AN65

DDR1_DQ[19]/DDR0_DQ[51]

AN66

DDR1_DQ[20]/DDR0_DQ[52]

AP66

DDR1_DQ[21]/DDR0_DQ[53]

AT65

DDR1_DQ[22]/DDR0_DQ[54]

AU65

DDR1_DQ[23]/DDR0_DQ[55]

AT61

DDR1_DQ[24]/DDR0_DQ[56]

AU61

DDR1_DQ[25]/DDR0_DQ[57]

AP60

DDR1_DQ[26]/DDR0_DQ[58]

AN60

DDR1_DQ[27]/DDR0_DQ[59]

AN61

DDR1_DQ[28]/DDR0_DQ[60]

AP61

DDR1_DQ[29]/DDR0_DQ[61]

AT60

DDR1_DQ[30]/DDR0_DQ[62]

AU60

DDR1_DQ[31]/DDR0_DQ[63]

AU40

DDR1_DQ[32]/DDR1_DQ[16]

AT40

DDR1_DQ[33]/DDR1_DQ[17]

AT37

DDR1_DQ[34]/DDR1_DQ[18]

AU37

DDR1_DQ[35]/DDR1_DQ[19]

AR40

DDR1_DQ[36]/DDR1_DQ[20]

AP40

DDR1_DQ[37]/DDR1_DQ[21]

AP37

DDR1_DQ[38]/DDR1_DQ[22]

AR37

DDR1_DQ[39]/DDR1_DQ[23]

AT33

DDR1_DQ[40]/DDR1_DQ[24]

AU33

DDR1_DQ[41]/DDR1_DQ[25]

AU30

DDR1_DQ[42]/DDR1_DQ[26]

AT30

DDR1_DQ[43]/DDR1_DQ[27]

AR33

DDR1_DQ[44]/DDR1_DQ[28]

AP33

DDR1_DQ[45]/DDR1_DQ[29]

AR30

DDR1_DQ[46]/DDR1_DQ[30]

AP30

DDR1_DQ[47]/DDR1_DQ[31]

AU27

DDR1_DQ[48]

AT27

DDR1_DQ[49]

AT25

DDR1_DQ[50]

AU25

DDR1_DQ[51]

AP27

DDR1_DQ[52]

AN27

DDR1_DQ[53]

AN25

DDR1_DQ[54]

AP25

DDR1_DQ[55]

AT22

DDR1_DQ[56]

AU22

DDR1_DQ[57]

AU21

DDR1_DQ[58]

AT21

DDR1_DQ[59]

AN22

DDR1_DQ[60]

AP22

DDR1_DQ[61]

AP21

DDR1_DQ[62]

AN21

DDR1_DQ[63]

KBL-RU_BGA1356

TABLE

Block 1

Block 3

Block 5

Block 7

@

SKL-U

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]

DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]

DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]

DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]

DDR1_DQSN[0]/DDR0_DQSN[2] DDR1_DQSP[0]/DDR0_DQSP[2] DDR1_DQSN[1]/DDR0_DQSN[3] DDR1_DQSP[1]/DDR0_DQSP[3] DDR1_DQSN[2]/DDR0_DQSN[6] DDR1_DQSP[2]/DDR0_DQSP[6] DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQSP[3]/DDR0_DQSP[7] DDR1_DQSN[4]/DDR1_DQSN[2] DDR1_DQSP[4]/DDR1_DQSP[2] DDR1_DQSN[5]/DDR1_DQSN[3] DDR1_DQSP[5]/DDR1_DQSP[3]

DDR CH - B

3 OF 20

Pin Interleave Non-Interleave

AH66 AH65 AG69 AG70

AR66 AR65 AR61 AR60

AT38 AR38 AT32 AR32

AR25 AR27 AR22 AR21

DDR1_DQSN[0] DDR1_DQSP[0] DDR1_DQSN[1] DDR1_DQSP[1]

DDR1_DQSN[2] DDR1_DQSP[2] DDR1_DQSN[3] DDR1_DQSP[3]

DDR1_DQSN[4] DDR1_DQSP[4] DDR1_DQSN[5] DDR1_DQSP[5]

DDR1_DQSN[6] DDR1_DQSP[6] DDR1_DQSN[7] DDR1_DQSP[7]

DDR0_DQSN[2] DDR0_DQSP[2] DDR0_DQSN[3] DDR0_DQSP[3]

DDR0_DQSN[6] DDR0_DQSP[6] DDR0_DQSN[7] DDR0_DQSP[7]

DDR1_DQSN[2] DDR1_DQSP[2] DDR1_DQSN[3] DDR1_DQSP[3]

DDR1_DQSN[6] DDR1_DQSP[6] DDR1_DQSN[7] DDR1_DQSP[7]

LOGIC

DDR1_CKN[0] DDR1_CKN[1] DDR1_CKP[0] DDR1_CKP[1]

DDR1_CKE[0] DDR1_CKE[1] DDR1_CKE[2] DDR1_CKE[3]

DDR1_CS#[0]

DDR1_CS#[1] DDR1_ODT[0] DDR1_ODT[1]

DDR1_MA[3] DDR1_MA[4]

DDR1_DQSN[6] DDR1_DQSP[6] DDR1_DQSN[7] DDR1_DQSP[7]

DDR1_ALERT#

DDR1_PAR DRAM_RESET# DDR_RCOMP[0] DDR_RCOMP[1] DDR_RCOMP[2]

LOGIC

AN45 AN46 AP45 AP46

AN56 AP55 AN55 AP53

BB42 AY42 BA42 AW42

AY48 AP50 BA48 BB48 AP48 AP52 AN50 AN48 AN53 AN52

BA43 AY43 AY44 AW44 BB44 AY47 BA44 AW46 AY46 BA46 BB46 BA47

AH66 AH65 AG69 AG70 AR66 AR65 AR61 AR60 AT38 AR38 AT32 AR32 AR25 AR27 AR22 AR21

AN43 AP43 AT13 AR18 AT18 AU18

3

-DDR_B_CLK0

DDR_B_CLK0

DDR_B_CKE0

-DDR_B_CS0

DDR_B_ODT0

DDR_B_MA5 DDR_B_MA9 DDR_B_MA6 DDR_B_MA8 DDR_B_MA7 DDR_B_BG0 DDR_B_MA12 DDR_B_MA11

-DDR_B_ACT DDR_B_BG1

DDR_B_MA13 DDR_B_MA15 DDR_B_MA14 DDR_B_MA16 DDR_B_BA0 DDR_B_MA2 DDR_B_BA1 DDR_B_MA10 DDR_B_MA1 DDR_B_MA0 DDR_B_MA3 DDR_B_MA4

-DDR_A_DQS2 DDR_A_DQS2

-DDR_A_DQS3 DDR_A_DQS3

-DDR_A_DQS6 DDR_A_DQS6

-DDR_A_DQS7 DDR_A_DQS7

-DDR_B_DQS2 DDR_B_DQS2

-DDR_B_DQS3 DDR_B_DQS3

-DDR_B_DQS6 DDR_B_DQS6

-DDR_B_DQS7 DDR_B_DQS7

1 2

R7 200_0201_1%X76@

1 2

R84 80.6_0201_1%

1 2

R576 100_0201_1%

-DDR_B_CLK0 [24,25]

DDR_B_CLK0 [24,25]

DDR_B_CKE0 [24,25]

-DDR_B_CS0 [24,25]

DDR_B_ODT0 [24,25]

DDR_B_BG0 [24,25]

-DDR_B_ACT [24,25] DDR_B_BG1 [24]

DDR_B_BA0 [24,25]

DDR_B_BA1 [24,25]

-DDR_A_DQS2 [22] DDR_A_DQS2 [22]

-DDR_A_DQS3 [22] DDR_A_DQS3 [22]

-DDR_A_DQS6 [22] DDR_A_DQS6 [22]

-DDR_A_DQS7 [22] DDR_A_DQS7 [22]

-DDR_B_DQS2 [24] DDR_B_DQS2 [24]

-DDR_B_DQS3 [24] DDR_B_DQS3 [24]

-DDR_B_DQS6 [24] DDR_B_DQS6 [24]

-DDR_B_DQS7 [24] DDR_B_DQS7 [24]

-DDR_B_ALERT [24,25] DDR_B_PAR [24,25]

VCC1R2A

R7 200 1% 121 1%

1 2

R1726 470_0201_5%

-DRAMRST

DDPSDP

2

DDR_B_MA[16:0] [24,25]

-DRAMRST [22,24]

TABLE

AY48 AP50 BA48 BB48 AP48 AP52 AN50 AN48 AN53 AN52

BA43 AY43 AY44 AW44 BB44 AY47 BA44 AW46 AY46 BA46 BB46 BA47

DDR3L LPDDR3 DDR4

DDR1_MA[5] DDR1_MA[9] DDR1_MA[6] DDR1_MA[8] DDR1_MA[7] DDR1_BA[2] DDR1_MA[12] DDR1_MA[11] DDR1_MA[15] DDR1_MA[14]

DDR1_MA[13] DDR1_CAS# DDR1_WE# DDR1_RAS# DDR1_BA[0] DDR1_MA[2] DDR1_BA[1] DDR1_MA[10] DDR1_MA[1] DDR1_MA[0] DDR1_MA[3] DDR1_MA[4]

DDR1_CAA[0] DDR1_CAA[1] DDR1_CAA[2] DDR1_CAA[3] DDR1_CAA[4] DDR1_CAA[5] DDR1_CAA[6] DDR1_CAA[7] DDR1_CAA[8] DDR1_CAA[9]

DDR1_CAB[0] DDR1_CAB[1] DDR1_CAB[2] DDR1_CAB[3] DDR1_CAB[4] DDR1_CAB[5] DDR1_CAB[6] DDR1_CAB[7] DDR1_CAB[8] DDR1_CAB[9] Not Used Not Used

LOGIC

1

DDR1_MA[5] DDR1_MA[9] DDR1_MA[6] DDR1_MA[8] DDR1_MA[7] DDR1_BG[0] DDR1_MA[12] DDR1_MA[11] DDR1_ACT# DDR1_BG[1]

DDR1_MA[13] DDR1_MA[15] DDR1_MA[14] DDR1_MA[16] DDR1_BA[0] DDR1_MA[2] DDR1_BA[1] DDR1_MA[10] DDR1_MA[1] DDR1_MA[0] DDR1_MA[3] DDR1_MA[4]

LOGIC

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/11/04 2016/12/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

CPU(3/16) : DDR CHANNEL-B

Size Document Number Rev

Custom

LA-F421P

Monday, October 23, 2017

Date: Sheet

1

73

of

6

1.0

5

D D

4

3

2

1

C C

PECI[53]

-PROCHOT[53]

B B

A A

PECI

-PROCHOT

VCCSTG VCCST

R64 1K_0201_5%

1 2

R85 510_0402_5%

1 2

R2126 49.9_0201_1%

1 2

R2127 49.9_0201_1%

1 2

R2128 49.9_0201_1%

1 2

R2129 49.9_0201_1%

1 2

R9055 1K_0201_5%

AT16 AU16

D63 A54 C65 C63 A65

C55 D55 B54 C56

A6

A7 BA5 AY5

H66 H65

U58D

@

CATERR# PECI PROCHOT# THERMTRIP# SKTOCC#

CPU MISC

BPM#[0] BPM#[1] BPM#[2] BPM#[3]

GPP_E3/CPU_GP0 GPP_E7/CPU_GP1 GPP_B3/CPU_GP2 GPP_B4/CPU_GP3

PROC_POPIRCOMP PCH_OPIRCOMP OPCE_RCOMP OPC_RCOMP

KBL-RU_BGA1356

SKL-U

4 OF 20

JTAG

PROC_TCK

PROC_TDI PROC_TDO PROC_TMS

PROC_TRST#

PCH_JTAG_TCK

PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS

PCH_TRST#

JTAGX

R9397 51_0201_5%@

XDP_TCK0 XDP_TDI XDP_TDO XDP_TMS

-XDP_TRST

XDP_TCK0 [20] XDP_TDI [20] XDP_TDO [20] XDP_TMS [20]

-XDP_TRST [20]

PCH_TCK [20]

B61 D60 A61 C60 B59

B56 D59 A56 C59 C61 A59

R2 51_0201_5%

1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/11/04 2016/12/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

CPU(4/16) : MISC/JTAG

Size Document Number Rev

Custom

LA-F421P

Monday, October 23, 2017

Date: Sheet

1

73

of

7

1.0

5

D D

TABLE : Functional Strap

SPI0_MOSI (Boot Halt)

Disabled (Default)

HIGH

LOW Enabled

TABLE : Functional Strap

SPI0_MISO (JTAG ODT Diable)

Enabled (Default)

HIGH

LOW Disabled

VCC3_SUS

C C

@

1 2

R9310 1K_0201_5%

R9311 1K_0201_5%

SPI_CLK[21,45] SPI_MISO_IO1[21,45] SPI_MOSI_IO0[21,45] SPI_IO2[21] SPI_IO3[21]

-SPI_CS0[21]

-SPI_CS2[45]

CL_CLK_WLAN[32] CL_DATA_WLAN[32]

-CL_RST_WLAN[32]

B B

-KBRC[53]

IRQSER[46,53]

CL_CLK_WLAN CL_DATA_WLAN

-CL_RST_WLAN

2

@RF@

C264 33P_0201_25V8J

1

VCC3B

8.2K_0201_5%

@

R9308 1K_0201_5%

1 2

4

TABLE : Functional Strap

GPP_C5/SML0ALERT # (LPC or eSPI)

HIGH

eSPI is selected

LOW

LPC is selected (Default) LOGIC

TABLE : Functional Strap

GPP_C2/SMBALERT# (TLS Confidentiality)

Enable ME Crypto TLS with Confidentiality

HIGH

LOW

Disable ME Crypto TLS (Default)

1 2

R860

AV2

AW3

AV3

AW2

AU4 AU3 AU2 AU1

AW13

AY11

@

R9305 1K_0201_5%

1 2

U58E

SPI0_CLK SPI0_MISO SPI0_MOSI SPI0_IO2 SPI0_IO3 SPI0_CS0# SPI0_CS1# SPI0_CS2#

M2

GPP_D1/SPI1_CLK

M3

GPP_D2/SPI1_MISO

J4

GPP_D3/SPI1_MOSI

V1

GPP_D21/SPI1_IO2

V2

GPP_D22/SPI1_IO3

M1

GPP_D0/SPI1_CS#

G3

CL_CLK

G2

CL_DATA

G1

CL_RST#

GPP_A0/RCIN#

GPP_A6/SERIRQ

KBL-RU_BGA1356

@

SPI - FLASH

SPI - TOUCH

C LINK

SKL-U

LPC

5 OF 20

3

SMBUS, SMLINK

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_B23/SML1ALERT#/PCHHOT#

GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

GPP_A8/CLKRUN#

2

FVT_C_EC016

EC_SMB_CK2[41,51,53]

EC_SMB_DA2[41,51,53]

LOGIC

VCC3_SUS VCC3B

R7 R8 R10

R9 W2 W1

W3 V3 AM7

AY13 BA13 BB13 AY12 BA12 BA11

AW9 AY9 AW11

R226 1K_0201_5%

1 2

LPCCLK_0 LPCCLK_1

R394

4.7K_0201_5%

1 2

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

R193 27_0402_1%RF@ R220 0_0402_5%

FVT_C_EC002

R397

4.7K_0201_5%

1 2

1 2 1 2

VCC3_SUS

C8609

18P_0201_50V8J

1 2

RF@

R106 499_0201_1%

2

1

2

C8610 18P_0201_50V8J

1

EC_SMB_CK2 SMB_CK2

R107 499_0201_1%

1 2

LPC_AD[3:0] [46,53]

-LPC_FRAME [46,53]

-SUS_STAT [46]

LPCCLK_EC_24M [53] LPCCLK_DEBUG_24M [46]

@RF@

2

6 1

Q211A SSM6N48FU 2N SC-88-6 ET88

3 4

Q211B SSM6N48FU 2N SC-88-6 ET88

@

8.2K_0201_5%

1 2

R28

SMB_CLK SMB_DATA

SMB0_CLK SMB0_DATA

SMB_CK2 SMB_DA2

VCC3M

1

5

SMB_DA2EC_SMB_DA2

SMB_CLK [46] SMB_DATA [46]

SMB0_CLK [52] SMB0_DATA [52]

SMB_CK2 [41] SMB_DA2 [41]

-CLKRUN [46]

TABLE : Functional Strap

SPI0_IO2 (Consent Strap)

Enabled (Default)

HIGH

LOW Disabled

TABLE : Functional Strap

SPI0_IO3 (A0 Personality Strap)

Disabled (Default)

A A

5

4

HIGH

LOW Enabled

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/11/04 2016/12/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

CPU(5/16) : LPC/SPI/SMBUS/C-LINK

Size Document Number Rev

Custom

LA-F421P

Date: Sheet

1

of

8 73Monday, October 23, 2017

1.0

5

10K_0201_5%

1 2

VCC1R8_SUS

@

10K_0201_5%

1 2

R2748

R2749

D D

NFC_DLREQ[43]

-WWAN_PWROFF[32]

-WWAN_DISABLE[32]

C C

BDC_ON[32]

-TBT_PLUG_EVENT[48] TBT_FORCE_PWR[48]

-EC_SCI[53]

-EC_WAKE[53]

I2C0_DATA[43]

I2C0_CLK[43]

-WWAN_RESET[32]

-INT_MIC_DTCT[26,27]

WWAN_CFG0[32] WWAN_CFG1[32]

VCC3B

4

TABLE : Functional Strap

VCC3_SUS

1K_0201_5%

10K_0201_5%

1 2

R2340

GPP_B22/GSPI1_MOSI (Boot BIOS Destination)

HIGH

Boot BIOS from LPC

LOW

Boot BIOS from SPI (Default) LOGIC

TABLE : Functional Strap

GPP_B18/GSPI0_MOSI (No Reboot)

@

HIGH

Enable "No Reboot" Mode

LOW

R65

AN8 AP7 AP8 AR7

AM5 AN7 AP5 AN5

AB1 AB2

W4

AB3

AD1 AD2 AD3 AD4

U7 U6

U8 U9

AH9

AH10

AH11 AH12

AF11 AF12

GPP_B15/GSPI0_CS# GPP_B16/GSPI0_CLK GPP_B17/GSPI0_MISO GPP_B18/GSPI0_MOSI

GPP_B19/GSPI1_CS# GPP_B20/GSPI1_CLK GPP_B21/GSPI1_MISO GPP_B22/GSPI1_MOSI

GPP_C8/UART0_RXD GPP_C9/UART0_TXD GPP_C10/UART0_RTS# GPP_C11/UART0_CTS#

GPP_C20/UART2_RXD GPP_C21/UART2_TXD GPP_C22/UART2_RTS# GPP_C23/UART2_CTS#

GPP_C16/I2C0_SDA GPP_C17/I2C0_SCL

GPP_C18/I2C1_SDA GPP_C19/I2C1_SCL

GPP_F4/I2C2_SDA GPP_F5/I2C2_SCL

GPP_F6/I2C3_SDA GPP_F7/I2C3_SCL

GPP_F8/I2C4_SDA GPP_F9/I2C4_SCL

Disable "No Reboot" Mode (Default)

U58F

@

LPSS ISH

KBL-RU_BGA1356

SKL-U

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_C15/UART1_CTS#/ISH_UART1_CTS#

6 OF 20

3

GPP_D9 GPP_D10 GPP_D11 GPP_D12

GPP_D5/ISH_I2C0_SDA GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA GPP_D8/ISH_I2C1_SCL

GPP_F10/I2C5_SDA/ISH_I2C2_SDA GPP_F11/I2C5_SCL/ISH_I2C2_SCL

GPP_D15/ISH_UART0_RTS#

GPP_C12/UART1_RXD/ISH_UART1_RXD GPP_C13/UART1_TXD/ISH_UART1_TXD

GPP_A18/ISH_GP0 GPP_A19/ISH_GP1 GPP_A20/ISH_GP2 GPP_A21/ISH_GP3 GPP_A22/ISH_GP4 GPP_A23/ISH_GP5

GPP_A12/BM_BUSY#/ISH_GP6

P2 P3 P4 P1

M4 N3

N1 N2

AD11 AD12

U1 U2 U3 U4

AC1 AC2 AC3 AB4

AY8 BA8 BB7 BA7 AY7 AW7 AP13

VCC3B VCC3B

1K_0201_5%

1 2

R9261

R9257

VCC3B VCC3B

R154

4.7K_0201_5%

1 2

ISH_GP0_R ISH_GP1_R ISH_GP2_R ISH_GP3 ISH_GP4 ISH_GP5 ISH_GP6

2

VCC1R8_SUSVCC3B

@

1K_0201_5%

1 2

R9263

R9262

R155

R156

4.7K_0201_5%

1 2

@

10K_0201_5%

1 2

R9375

R9565

R9259

R9260

4.7K_0201_5%

1 2

@

10K_0201_5%

1 2

R2750

R2751

1 2

R9419 0_0201_5%RF@

1 2

R9420 0_0201_5%RF@

1 2

R9421 0_0201_5%RF@

FVT_C_EC018

TP922 @ TP923 @

-NFC_DTCT [43]

-INT_IR_DTCT [27]

-TS_RESET [26]

ISH_I2C0_SDA [26,27,41]

ISH_I2C0_SCL [26,27,41]

I2C_DATA_GSENSE_SH [53]

I2C_CLK_GSENSE_SH [53]

WWAN_CFG2 [32] WWAN_CFG3 [32]

2 1

D801 RB521CM-30T2R_SOD923-2

2 1

D802 RB521CM-30T2R_SOD923-2

C86500.1U_0201_6.3V6K

C86510.1U_0201_6.3V6K

C86490.1U_0201_6.3V6K

2

1

RF@

-LID_CLOSE

-TABLET_MODE

1

ISH_GP0 [26,27] ISH_GP1 [26,27] ISH_GP2 [26,27,41]

-LID_CLOSE [26,43,53]

-TABLET_MODE [43,53]

FVT_C_EC018

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

For ISH debug

ISH_I2C0_SCL ISH_I2C0_SDA I2C_CLK_GSENSE_SH I2C_DATA_GSENSE_SH ISH_GP0 ISH_GP1 ISH_GP2 ISH_GP3

Compal Secret Data

2014/11/04 2016/12/31

Compal Secret Data

2

Deciphered Date

TP924 @ TP925 @ TP926 @ TP927 @ TP928 @ TP929 @ TP930 @ TP931 @

Compal Electronics, Inc.

Title

CPU(6/16) : LPSS/ISH

Size Document Number Rev

Custom

LA-F421P

Date: Sheet

1

of

9 73Monday, October 23, 2017

1.0

5

D D

C C

1 2

2

C38

RF@

47P_0201_25V8J

1

R423 33_0201_5%

1 2

R60 33_0201_5%

1 2

R74 33_0201_5%

1 2

R456 33_0201_5%

1 2

R9380 0_0201_5%@

PCH_SPKR

R60, C38 close to CPU

HDA_SYNC[35] HDA_BCLK[35] HDA_SDO[35] HDA_SDIN0[35]

-HDA_RST[35]

NFC_ACTIVE[43]

PCH_SPKR[40]

B B

4

VCC3_SUS

@

1 2

R1009 1K_0201_5%

3

TABLE : Functional Strap

HDA_SDO/I2S0_TXD

1 2

ME_FLASH[53]

R9564 0_0201_5%@

HDA_SDOUT

Flash Descriptor Security Override

HIGH

Disable Flash Descriptor Security (Override)

LOW

Enable Flash Descriptor Security (Default)

U58G

@

AUDIO

BA22

HDA_SYNC/I2S0_SFRM

AY22

HDA_BLK/I2S0_SCLK

BB22

HDA_SDO/I2S0_TXD

BA21

HDA_SDI0/I2S0_RXD

AY21

HDA_SDI1/I2S1_RXD

AW22

HDA_RST#/I2S1_SCLK

J5

GPP_D23/I2S_MCLK

AY20

I2S1_SFRM

AW20

I2S1_TXD

AK7

GPP_F1/I2S2_SFRM

AK6

GPP_F0/I2S2_SCLK

AK9

GPP_F2/I2S2_TXD

AK10

GPP_F3/I2S2_RXD

H5

GPP_D19/DMIC_CLK0

D7

GPP_D20/DMIC_DATA0

D8

GPP_D17/DMIC_CLK1

C8

GPP_D18/DMIC_DATA1

AW5

GPP_B14/SPKR

KBL-RU_BGA1356

TABLE : Functional Strap

GPP_B14/SPKR (Top Swap Override)

HIGH

Enable "Top Swap" Mode

LOW

Disable "Top Swap" Mode (Default) LOGIC

SKL-U

7 OF 20

SDIO/SDXC

GPP_G0/SD_CMD GPP_G1/SD_DATA0 GPP_G2/SD_DATA1 GPP_G3/SD_DATA2 GPP_G4/SD_DATA3

GPP_G5/SD_CD# GPP_G6/SD_CLK

GPP_G7/SD_WP

GPP_A17/SD_PWR_EN#/ISH_GP7

GPP_A16/SD_1P8_SEL

SD_RCOMP

GPP_F23

2

AB11 AB13 AB12 W12 W11 W10 W8 W7

BA9 BB9

AB7

AF13

-SC_DTCT [34]

1

VCC3M

1 2

R54 1K_0201_5%@

HDA_SDOUT

ME debug mode,this signal has a weak internal PD Low = Disabled (Default)

*

High = Enabled [Flash Descriptor Security Overide]

A A

HDA_SDOUT

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/11/04 2016/12/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

CPU : AUDIO/SDXC

Size Document Number Rev

Custom

LA-F421P

Date: Sheet

1

of

10 73Monday, October 23, 2017

1.0

5

4

3

2

1

D D

C C

B B

A A

I/O High Speed Signals Configuration Net Name

Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port 10 Port 11 Port 12 Port 13 Port 14 Port 15 Port 16

Flexible I/O Configuration PCIe Port Assignment

R8964

0 2 3 4 (x4) 8 11

0 1A 1B 2

100_0201_1%

1 2

SATA Port Assignment

(PCIE 7) SATA SSD NA (PCIE 11)

USB3 1 USB3 2/SSIC USB3 3 USB3 4 USB3 5/PCIE 1 USB3 6/PCIE 2 PCIE 3 (GbE) PCIE 4 (GbE) PCIE 5 (GbE) PCIE 6 PCIE 7/SATA 0 PCIE 8/SATA 1A PCIE 9 (GbE) PCIE 10 (GbE) PCIE 11/SATA 1B PCIE 12/SATA 2

USB3 1 SSIC USB3 3 USB3 4 PCIE 1 USB3 6 PCIE 3 PCIE 4 PCIE 5 (x4) PCIE 6 (x4) PCIE 7 (x4) GPIO STRAP PCIE 9 (x4) PCIE 10 (x4) PCIE 11 (x4) PCIE 12 (x4)

PCIE4_L0_SATA1_RXN[30] PCIE4_L0_SATA1_RXP[30] PCIE4_L0_SATA1_TXN[30] PCIE4_L0_SATA1_TXP[30]

USB3P0 SSIC USB3P2 USB3P3 PCIE0 USB3P5 PCIE2 PCIE3 PCIE4_L3 PCIE4_L2 PCIE4_L1 PCIE4_L0_SATA1 PCIE5_L0 NA NA NA

PCIE0_RXN[33] PCIE0_RXP[33] PCIE0_TXN[33] PCIE0_TXP[33]

PCIE2_RXN[32] PCIE2_RXP[32] PCIE2_TXN[32] PCIE2_TXP[32]

PCIE3_RXN[52] PCIE3_RXP[52] PCIE3_TXN[52] PCIE3_TXP[52]

PCIE4_L3_RXN[30] PCIE4_L3_RXP[30] PCIE4_L3_TXN[30] PCIE4_L3_TXP[30]

PCIE4_L2_RXN[30] PCIE4_L2_RXP[30] PCIE4_L2_TXN[30] PCIE4_L2_TXP[30]

PCIE4_L1_RXN[30] PCIE4_L1_RXP[30] PCIE4_L1_TXN[30] PCIE4_L1_TXP[30]

PCIE8_L0_RXN[49] PCIE8_L0_RXP[49] PCIE8_L0_TXN[49] PCIE8_L0_TXP[49]

PCIE8_L1_RXN[49] PCIE8_L1_RXP[49] PCIE8_L1_TXN[49] PCIE8_L1_TXP[49]

-XDP_PRDY[20]

-XDP_PREQ[20]

-TPM_IRQ[45]

PCIE11_RXN[32] PCIE11_RXP[32] PCIE11_TXN[32] PCIE11_TXP[32]

-XDP_PRDY

-XDP_PREQ

-TPM_IRQ

VCC3_SUS

1 2

R2341 10K_0201_5%

MEDIA CARD M.2 WLAN Slot Port 0 for WLAN GbE PHY PCIe SSD Thunder bolt WWAN

U58H

@

PCIE/USB3/SATA

H13

PCIE1_RXN/USB3_5_RXN

G13

PCIE1_RXP/USB3_5_RXP

B17

PCIE1_TXN/USB3_5_TXN

A17

PCIE1_TXP/USB3_5_TXP

G11

PCIE2_RXN/USB3_6_RXN

F11

PCIE2_RXP/USB3_6_RXP

D16

PCIE2_TXN/USB3_6_TXN

C16

PCIE2_TXP/USB3_6_TXP

H16

PCIE3_RXN

G16

PCIE3_RXP

D17

PCIE3_TXN

C17

PCIE3_TXP

G15

PCIE4_RXN

F15

PCIE4_RXP

B19

PCIE4_TXN

A19

PCIE4_TXP

F16

PCIE5_RXN

E16

PCIE5_RXP

C19

PCIE5_TXN

D19

PCIE5_TXP

G18

PCIE6_RXN

F18

PCIE6_RXP

D20

PCIE6_TXN

C20

PCIE6_TXP

F20

PCIE7_RXN/SATA0_RXN

E20

PCIE7_RXP/SATA0_RXP

B21

PCIE7_TXN/SATA0_TXN

A21

PCIE7_TXP/SATA0_TXP

G21

PCIE8_RXN/SATA1A_RXN

F21

PCIE8_RXP/SATA1A_RXP

D21

PCIE8_TXN/SATA1A_TXN

C21

PCIE8_TXP/SATA1A_TXP

E22

PCIE9_RXN

E23

PCIE9_RXP

B23

PCIE9_TXN

A23

PCIE9_TXP

F25

PCIE10_RXN

E25

PCIE10_RXP

D23

PCIE10_TXN

C23

PCIE10_TXP

F5

PCIE_RCOMPN

E5

PCIE_RCOMPP

D56

PROC_PRDY#

D61

PROC_PREQ#

BB11

GPP_A7/PIRQA#

E28

PCIE11_RXN/SATA1B_RXN

E27

PCIE11_RXP/SATA1B_RXP

D24

PCIE11_TXN/SATA1B_TXN

C24

PCIE11_TXP/SATA1B_TXP

E30

PCIE12_RXN/SATA2_RXN

F30

PCIE12_RXP/SATA2_RXP

A25

PCIE12_TXN/SATA2_TXN

B25

PCIE12_TXP/SATA2_TXP

KBL-RU_BGA1356

SKL-U

8 OF 20

SSIC / USB3

USB3_2_RXN/SSIC_1_RXN USB3_2_RXP/SSIC_1_RXP

USB3_2_TXN/SSIC_1_TXN USB3_2_TXP/SSIC_1_TXP

USB3_3_RXN/SSIC_2_RXN USB3_3_RXP/SSIC_2_RXP

USB3_3_TXN/SSIC_2_TXN USB3_3_TXP/SSIC_2_TXP

USB2

USB2_VBUSSENSE

GPP_E9/USB2_OC0# GPP_E10/USB2_OC1# GPP_E11/USB2_OC2# GPP_E12/USB2_OC3#

GPP_E4/DEVSLP0 GPP_E5/DEVSLP1 GPP_E6/DEVSLP2

GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2

GPP_E8/SATALED#

USB3_1_RXN USB3_1_RXP USB3_1_TXN USB3_1_TXP

USB3_4_RXN USB3_4_RXP USB3_4_TXN USB3_4_TXP

USB2N_1 USB2P_1

USB2N_2 USB2P_2

USB2N_3 USB2P_3

USB2N_4 USB2P_4

USB2N_5 USB2P_5

USB2N_6 USB2P_6

USB2N_7 USB2P_7

USB2N_8 USB2P_8

USB2N_9 USB2P_9

USB2N_10 USB2P_10

USB2_COMP

USB2_ID

H8 G8 C13 D13

J6 H6 B13 A13

J10 H10 B15 A15

E10 F10 C15 D15

AB9 AB10

AD6 AD7

AH3 AJ3

AD9 AD10

AJ1 AJ2

AF6 AF7

AH1 AH2

AF8 AF9

AG1 AG2

AH7 AH8

AB6 AG3 AG4

A9 C9 D9 B9

J1 J2 J3

H2 H3 G4

H1

1K_0201_5%

R72

USBCOMP

1 2

R648 10K_0201_5%

@

R77 0_0201_5%

VCC3_SUS

1 2

R248 10K_0201_5%

@

1 2

R2308 10K_0201_5%

R2307 10K_0201_5%

USB3P0_RXN [31] USB3P0_RXP [31] USB3P0_TXN [31] USB3P0_TXP [31]

USB Port Assignment

0

-PE_DTCT

USB 3.0 System Port (AOU)

1

M.2 WWAN Slot

2

USB 3.0 System Port

3

RGB camera

4

SMART CARD

5

IR CAMERA

6

M.2 WLAN Slot for BT

7

USB Camera

8

Fingerprint Reader

9

Touch Panel

USB 3.0 Port Assignment

0

USB 3.0 System Port (AOU)

1

NA

2

USB 3.0 System Port

3

NA

4

(PCIE 1)

5

(RESERVED)

SATA1_DEVSLP [30]

-PE_DTCT [30]

113_0201_1%

1 2

R564

USB3P2_RXN [31] USB3P2_RXP [31] USB3P2_TXN [31] USB3P2_TXP [31]

USBP0- [31] USBP0+ [31]

USBP1- [32] USBP1+ [32]

USBP2- [31] USBP2+ [31]

USBP3- [27] USBP3+ [27]

USBP4- [34] USBP4+ [34]

USBP5- [27] USBP5+ [27]

USBP6- [32] USBP6+ [32]

USBP7- [26] USBP7+ [26]

USBP8- [34] USBP8+ [34]

USBP9- [26] USBP9+ [26]

-USB_PORT0_OC0 [31]

-USB_PORT1_OC1 [31]

NFC_INT [43]

NFC_ON [43]

VCC3_SUS

1 2

R44 10K_0201_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/11/04 2016/12/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

CPU : PCIE/USB/SATA

Size Document Number Rev

Custom

LA-F421P

Date: Sheet

1

of

11 73Monday, October 23, 2017

1.0

5

D D

C C

4

SKL_ULT

U58I

@

CSI-2

A36 B36 C38 D38 C36 D36 A38 B38

C31 D31 C33 D33 A31 B31 A33 B33

A29 B29 C28 D28 A27 B27 C27 D27

CSI2_DN0 CSI2_DP0 CSI2_DN1 CSI2_DP1 CSI2_DN2 CSI2_DP2 CSI2_DN3 CSI2_DP3

CSI2_DN4 CSI2_DP4 CSI2_DN5 CSI2_DP5 CSI2_DN6 CSI2_DP6 CSI2_DN7 CSI2_DP7

CSI2_DN8 CSI2_DP8 CSI2_DN9 CSI2_DP9 CSI2_DN10 CSI2_DP10 CSI2_DN11 CSI2_DP11

KBL-RU_BGA1356

9 OF 20

CSI2_CLKN0 CSI2_CLKP0 CSI2_CLKN1 CSI2_CLKP1 CSI2_CLKN2 CSI2_CLKP2 CSI2_CLKN3 CSI2_CLKP3

CSI2_COMP

GPP_D4/FLASHTRIG

EMMC

GPP_F13/EMMC_DATA0 GPP_F14/EMMC_DATA1 GPP_F15/EMMC_DATA2 GPP_F16/EMMC_DATA3 GPP_F17/EMMC_DATA4 GPP_F18/EMMC_DATA5 GPP_F19/EMMC_DATA6 GPP_F20/EMMC_DATA7

GPP_F21/EMMC_RCLK

GPP_F22/EMMC_CLK

GPP_F12/EMMC_CMD

EMMC_RCOMP

3

C37 D37 C32 D32 C29 D29 B26 A26

E13 B7

AP2 AP1 AP3 AN3 AN1 AN2 AM4 AM1

AM2 AM3 AP4

AT1

MEMORYID0 MEMORYID1 MEMORYID2 MEMORYID3 DDR_CH_SEL

-TAMPER_SW_DTCT

-TAMPER_SW_DTCT [14]

2

1

B B

TABLE

MEMORY[3..0]

1111B

1110B

1101B

1011B

0111B

1100B

A A

U125, U126, U127, U128, U129, U130, U131, U132

Samsung K4AAG165WB-MCRC 16Gbit DDP 8GB

Hynix H5AN8G6NAFR-UHC 8Gbit SDP 4GB 200 1%

Hynix H5ANAG6NAMR-UHC 16Gbit DDP 8GB 121 1%

Micron MT40A512M16JY-083E:B 200 1%8Gbit SDP 4GB

5

16Gbit DDP 8GB 121 1%Micron MT40A1G16WBU-083E:B

R7 (Rcomp)

200 1%Samsung K4A8G165WC-BCRC 8Gbit SDP 4GB

121 1%

1CH2CH

MEMORYID0

R2331 NC Mount

R2332 0_0201_5%

X76@

1 2

4

3

R2333 0_0201_5%

X76@

1 2

R2334 0_0201_5%

X76@

MEMORYID1 MEMORYID2 MEMORYID3

R2335 0_0201_5%

X76@

1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/11/04 2016/12/31

DDR_CH_SEL

R2331 0_0201_5%

X76@

1 2

Compal Secret Data

2

Deciphered Date

Custom

Date: Sheet

Compal Electronics, Inc.

Title

CPU : CSI-2/EMMC

Size Document Number Rev

LA-F421P

1

of

12 73Monday, October 23, 2017

1.0

5

D D

4

3

2

1

XTAL24_IN_U22

FLJ20

@EMI@

MCF12102G900-T_4P

XTAL24_OUT_U22

C C

-PCIE0_CLK_100M[33]

Media Card

WWAN

WLAN

LAN

2280 SSD

TBT

B B

PCIE0_CLK_100M[33]

-CLKREQ_PCIE0[33]

-PCIE11_CLK_100M[32] PCIE11_CLK_100M[32]

-CLKREQ_PCIE11[32]

-PCIE2_CLK_100M[32] PCIE2_CLK_100M[32]

-CLKREQ_PCIE2[32]

-PCIE3_CLK_100M[52] PCIE3_CLK_100M[52]

-CLKREQ_PCIE3[52]

-PCIE4_CLK_100M[30] PCIE4_CLK_100M[30]

-CLKREQ_PCIE4[30]

-PCIE8_CLK_100M[49] PCIE8_CLK_100M[49]

-CLKREQ_PCIE8[49]

U58J

D42

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0

AR10

GPP_B5/SRCCLKREQ0#

B42

CLKOUT_PCIE_N1

A42

CLKOUT_PCIE_P1

AT7

GPP_B6/SRCCLKREQ1#

D41

CLKOUT_PCIE_N2

C41

CLKOUT_PCIE_P2

AT8

GPP_B7/SRCCLKREQ2#

D40

CLKOUT_PCIE_N3

C40

CLKOUT_PCIE_P3

AT10

GPP_B8/SRCCLKREQ3#

B40

CLKOUT_PCIE_N4

A40

CLKOUT_PCIE_P4

AU8

GPP_B9/SRCCLKREQ4#

E40

CLKOUT_PCIE_N5

E38

CLKOUT_PCIE_P5

AU7

GPP_B10/SRCCLKREQ5#

KBL-RU_BGA1356

@

XTAL24_OUT_U42

CLOCK SIGNALS

AW69 AW68

AU56

AW48

C7 U12 U11 H11

SKL_ULT

10 OF 20

U58T

@

RSVD_AW69 RSVD_AW68 RSVD_AU56 RSVD_AW48 RSVD_C7 RSVD_U12 RSVD_U11 RSVD_H11

KBL-RU_BGA1356

SKL-U

SPARE

20 OF 20

CLKOUT_ITPXDP_N

CLKOUT_ITPXDP_P

GPD8/SUSCLK

XTAL24_IN

XTAL24_OUT

XCLK_BIASREF

RTCX1 RTCX2

SRTCRST#

RTCRST#

RSVD_F6 RSVD_E3

RSVD_C11

RSVD_B11

RSVD_A11 RSVD_D12 RSVD_C12

RSVD_F52

VCC1R0_SUS

F43 E43

BA17

XTAL24_IN_U22

E37

XTAL24_OUT_U22

E35

E42

AM18 AM20

AN18 AM16

F6 E3 C11 B11 A11 D12 C12 F52

R609

XTAL24_IN_U42

2.74K_0201_1%

1 2

RTCX1 RTCX2

-SRTCRST [61]

-RTCRST [61]

XTAL24_IN_U42 XTAL24_OUT_U42

SUSCLK_32K [32]

TXC 9H03280012 KDS 1TJF090DJ1A000B

R9567 33_0201_5%U42@ R9568 33_0201_5%

1 2

R9463 33_0201_5%U22@

2

1

R9464 33_0201_5%

R351 10M_0402_5%

1 2

1 2 1 2

U42@

2

1

1 2

U22@

3

4

6.8P_0201_25V8B

Y6

32.768KHZ_9PF_9H03280012

1 2

6.8P_0201_25V8B

C348

1 2

C326

1 2

U42@

1 2

U22@

1 2

R9569 1M_0201_1%

R308 1M_0201_1%

U42@

2

C8785

8.2P_0201_25V8D

1

2

U22@

C205

8.2P_0201_25V8D

1

2

1

24MHZ_8PF_8Y24080002

G

X'tal

U42@

Y7

X'tal

G

Y5

2

G

X'tal

1

X'tal

G

24MHZ_8PF_8Y24080002

U22@

TXC 8Y24080002

3

4

3

4

2

U42@

1

C8784

8.2P_0201_25V8D

2

U22@

C206

8.2P_0201_25V8D

1

TXC 8Y24080002

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/11/04 2016/12/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

CPU : CLOCK SIGNALS

Size Document Number Rev

Custom

LA-F421P

Date: Sheet

1

of

13 73Monday, October 23, 2017

1.0

5

4

3

2

1

Change to SN74LVC1G17DRLRG4 (SA00006DR00)

VCC3M

U73

5

D D

-PLTRST_FAR[30,32,33,45,46,49,52,53]

2

1

-RSMRST

R993

C46 100P_0201_25V8J

33_0201_5%

1 2

VCC

4

OUT_Y

SN74LVC1G17DRLRG4_SOT5

1 2

R9505 0_0201_5%@

1

NC

2

-PLTRST

IN_A

3

GND

2

C8523

@ESD@

100P_0201_25V8J

1

C C

VCC3M_PCH

B B

AC_PRESENT[53]

-PWRSW_EC[53]

-RSMRST[20,53]

R9481 100K_0201_5%@

R9487 10K_0201_5%@

R9587 8.2K_0201_5%@

R9578 10K_0201_5%

R9469 10K_0201_5%

R9470 100K_0201_5%@

AC_PRESENT AC_PRESENT_R

-RSMRST

BPWRG

2

C8525

@ESD@

100P_0201_25V8J

1

12

@

R9486 0_0201_5%

R9480 0_0201_5%

R9471 0_0201_5%

12

@

12

@

12

-XDP_DBR[20]

BPWRG[53] PCH_PWROK[53]

-PCIE_WAKE[32,48]

-LANWAKE[52] LANPHYPC[52]

-PWRSW_EC_R

AC_PRESENT_R

-BATLOW

AC_PRESENT_R

-RSMRST

PCH_DPWROK

-PWRSW_EC_R-PWRSW_EC

PCH_DPWROK

-RSMRST

PCH_DPWROK

Removed will cause KB/TP can't work after scan 8's code in shell mode

VCC3M

4.7K_0201_5%

1 2

R19

VCC3B

1K_0201_5%

10K_0201_5%

1 2

R491

R612

Can not remove

EC_VCCST_PG

-SUSWARN

1 2

R1884

0_0201_5% @

-SUSACK

U58K

@

SYSTEM POWER MANAGEMENT

AN10

GPP_B13/PLTRST#

B5

SYS_RESET#

AY17

RSMRST#

A68

PROCPWRGD

B65

VCCST_PWRGD

B6

SYS_PWROK

BA20

PCH_PWROK

BB20

DSW_PWROK

AR13

GPP_A13/SUSWARN#/SUSPWRDNACK

AP11

GPP_A15/SUSACK#

BB15

WAKE#

AM15

GPD2/LAN_WAKE#

AW17

GPD11/LANPHYPC

AT15

GPD7/RSVD

KBL-RU_BGA1356

-TAMPER_SW_DTCT[12]

SKL-U

11 OF 20

-TAMPER_SW_DTCT

GPP_B12/SLP_S0#

GPD4/SLP_S3# GPD5/SLP_S4#

GPD10/SLP_S5#

SLP_SUS#

SLP_LAN#

GPD9/SLP_WLAN#

GPD6/SLP_A#

GPD3/PWRBTN#

GPD1/ACPRESENT

GPD0/BATLOW#

GPP_A11/PME#

INTRUDER#

GPP_B11/EXT_PWR_GATE#

GPP_B2/VRALERT#

S3

1

3

2

4

SPVR310100_4P

AT11 AP15 BA16 AY16

AN15 AW15 BB17 AN16

BA15 AY15 AU13

AU11 AP16

AM10 AM11

R646

1M_0201_5%

TP196

@

PAD

-PCH_SLP_WLAN

-INTRUDER

1000P_0201_25V7K

1 2

@

C7

@

1 2

VCC3MRTCVCC

@

10K_0201_5%

1 2

R614

-PWRSW_EC_R AC_PRESENT_R

-BATLOW

2

1

R100_0201_5%

-PCH_SLP_S3 [48,53]

-PCH_SLP_S4 [53]

-PCH_SLP_S5 [53]

-PCH_SLP_LAN [58]

-PCH_SLP_WLAN [58]

-PCH_SLP_M [53,58]

-BATLOW [48,53]

A A

From EC(open-drain)

VCCST_PG_EC[53]

VCCST

12

R95 1K_0201_5%

R96 60.4_0201_1%

5

1 2

EC_VCCST_PG

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/11/04 2016/12/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

CPU : SYSTEM PM

Size Document Number Rev

Custom

LA-F421P

Date: Sheet

1

of

14 73Monday, October 23, 2017

1.0

5

D D

4

VCC I (Max) : 32A (Dual Core) 64A (Qual Core)

3

2

1

VCCCPUCORE VCCCPUCORE

@

SKL-U

CPU POWER 1 OF 4

12 OF 20

VCC_G32 VCC_G33 VCC_G35 VCC_G37 VCC_G38 VCC_G40 VCC_G42

VCC_J30 VCC_J33 VCC_J37

VCC_J40 VCC_K33 VCC_K35 VCC_K37 VCC_K38 VCC_K40 VCC_K42 VCC_K43

VCC_SENSE VSS_SENSE

VIDALERT#

VIDSCK

VIDSOUT

VCCSTG_G20

G32 G33 G35 G37 G38 G40 G42 J30 J33 J37 J40 K33 K35 K37 K38 K40 K42 K43

E32 E33

B63 A63 D64

G20

VCCSTG

VCCCPUCORE

12

1 2

R9 100_0201_1%

R781 R9387 22_0201_5%RF@

R70 100_0201_1%

220_0201_5%

1 2 1 2

U58L

A30

VCC_A30

A34

VCC_A34

A39

VCC_A39

A44

VCC_A44

AK33

VCC_AK33

AK35

VCC_AK35

AK37

VCC_AK37

AK38

VCC_AK38

AK40

VCC_AK40

AL33

VCC_AL33

AL37

VCC_AL37

AL40

VCC_AL40

C C

B B

AM32 AM33 AM35 AM37 AM38

AC63

AG62

G30

K32

AK32

AB62

P62 V62

H63

G61

AE63

AE62

AL63 AJ62

VCC_AM32 VCC_AM33 VCC_AM35 VCC_AM37 VCC_AM38 VCC_G30

RSVD_K32

RSVD_AK32

VCCOPC_AB62 VCCOPC_P62 VCCOPC_V62

VCC_OPC_1P8_H63

VCC_OPC_1P8_G61

VCCOPC_SENSE VSSOPC_SENSE

VCCEOPIO VCCEOPIO

VCCEOPIO_SENSE VSSEOPIO_SENSE

KBL-RU_BGA1356

R374 56_0201_5%

1 2

VCCST

1 2

2

@RF@

C8601 12P_0201_25V8J

1

@

R782 100_0201_5%

R9319 100_0201_5%

1 2

VCC_SENSE VSS_SENSE

-SVID_ALERT SVID_CLK SVID_DATA

VCC_SENSE [64] VSS_SENSE [64]

-SVID_ALERT [64] SVID_CLK [64]

SVID_DATA [64]

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/11/04 2016/12/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

CPU : CPU POWER (1/2)

Size Document Number Rev

Custom

LA-F421P

Date: Sheet

1

of

15 73Monday, October 23, 2017

1.0

5

4

3

2

1

2

1

22U_0603_6.3V6M

VCCCPUIO

2

1

1U_0402_6.3V6K

R2154 100_0201_1%

VCCQC VCCPLL_OCVCCPLL

2

1

10U_0402_6.3V6M

C844

C2426

@

2

1

1U_0402_6.3V6K

C8646

C8645

2

1

1U_0402_6.3V6K

C8647

VSSSA_SENSE [64]

VCCSA_SENSE [64]

2

1

1U_0201_6.3V6M

0.1U_0201_6.3V6K

C8648

C8536

C2427

D D

VCCGFXCORE_I_VCCCPUCORE

C C

B B

VCCGT_SENSE[64] VSSGT_SENSE[64]

VCCGT_SENSE VSSGT_SENSE

VCCGFXCORE_I

R2152 100_0201_1%

1 2

R2153 100_0201_1%

1 2

VCCGFXCORE_I VCCGFXCORE_I

VCCGFXCORE_I

2

1

0.1U_0201_6.3V6K

A48 A53 A58 A62

A66 AA63 AA64 AA66 AA67 AA69 AA70 AA71 AC64 AC65 AC66 AC67 AC68 AC69 AC70 AC71

K48

K50

K52

12

R95810_0201_5%

K53

@

K55

K56

K58

K60

M62

N63

N64

N66

N67

N69

C8570

J43 J45 J46 J48 J50 J52 J53 J55 J56 J58 J60

L62 L63 L64 L65 L66 L67 L68 L69 L70 L71

J70 J69

2

1

0.1U_0201_6.3V6K C8571

U58M

@

CPU POWER 2 OF 4

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

VCCGT_SENSE VSSGT_SENSE

KBL-RU_BGA1356

2

1

0.1U_0201_6.3V6K

0.1U_0201_6.3V6K C8573

C8572

VCCGT I (Max) :31A

SKL-U

N70

VCCGT

N71

VCCGT

R63

VCCGT

R64

VCCGT

R65

VCCGT

R66

VCCGT

R67

VCCGT

R68

VCCGT

R69

VCCGT

R70

VCCGT

R71

VCCGT

T62

VCCGT

U65

VCCGT

U68

VCCGT

U71

VCCGT

W63

VCCGT

W64

VCCGT

W65

VCCGT

W66

VCCGT

W67

VCCGT

W68

VCCGT

W69

VCCGT

W70

VCCGT

W71

VCCGT

Y62

VCCGT

AK42

VCCGTX_AK42

AK43

VCCGTX_AK43

AK45

VCCGTX_AK45

AK46

VCCGTX_AK46

AK48

VCCGTX_AK48

AK50

VCCGTX_AK50

AK52

VCCGTX_AK52

AK53

VCCGTX_AK53

AK55

VCCGTX_AK55

AK56

VCCGTX_AK56

AK58

VCCGTX_AK58

AK60

VCCGTX_AK60

AK70

VCCGTX_AK70

AL43

VCCGTX_AL43

AL46

VCCGTX_AL46

AL50

VCCGTX_AL50

AL53

VCCGTX_AL53

AL56

VCCGTX_AL56

AL60

VCCGTX_AL60

AM48

VCCGTX_AM48

AM50

VCCGTX_AM50

AM52

VCCGTX_AM52

AM53

VCCGTX_AM53

AM56

VCCGTX_AM56

AM58

VCCGTX_AM58

AU58

VCCGTX_AU58

AU63

VCCGTX_AU63

BB57

VCCGTX_BB57

BB66

VCCGTX_BB66

AK62 AL61

13 OF 20

VCCGTX_SENSE VSSGTX_SENSE

VCCST VCCSTG VCCST VCC1R2A VCC1R2A VCC1R2AVCC1R2A

2

1

1U_0402_6.3V6K

VCCGFXCORE_X_VCCCPUCORE

2

1

1U_0402_6.3V6K

C2422

20mA

2

1

0.1U_0201_6.3V6K

C2423

C2424

2800mA

VCC1R2A

VCCSTVCCSTG

130mA

2

1

10U_0402_6.3V6M

C835

C2425

U58N

AU23

VDDQ_AU23

AU28

VDDQ_AU28

AU35

VDDQ_AU35

AU42

VDDQ_AU42

BB23

VDDQ_BB23

BB32

VDDQ_BB32

BB41

VDDQ_BB41

BB47

VDDQ_BB47

BB51

VDDQ_BB51

AM40

VDDQC

A18

VCCST

A22

VCCSTG_A22

AL23

VCCPLL_OC

K20

VCCPLL_K20

K21

VCCPLL_K21

KBL-RU_BGA1356

2

1

10U_0402_6.3V6M

C1184

@

CPU POWER 3 OF 4

10U_0402_6.3V6M

SKL-U

14 OF 20

2

1

C1829

VCCIO_SENSE

VSSSA_SENSE

VCCSA_SENSE

2

1

10U_0402_6.3V6M

VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO

VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA

VSSIO_SENSE

2

1

10U_0402_6.3V6M

C1831

C1830

@

AK28 AK30 AL30 AL42 AM28 AM30 AM42

AK23 AK25 G23 G25 G27 G28 J22 J23 J27 K23 K25 K27 K28 K30

AM23 AM22

H21 H20

2

1

10U_0402_6.3V6M

C1832

@

3400mA

VCCCPUIO

VCCIO_SENSE VSSIO_SENSE

2

1

10U_0402_6.3V6M

4000mA

VCCSA

C838

@

2

1

22U_0603_6.3V6M

C840

C842

@

VCCSA

1 2

T101@ T102@

VSSSA_SENSE VCCSA_SENSE

R2155 100_0201_1%

1 2

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/11/04 2016/12/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

CPU : CPU POWER (2/2)

Size Document Number Rev

Custom

LA-F421P

Date: Sheet

1

of

16 73Monday, October 23, 2017

1.0

5

4

3

2

1

D D

C C

VCC1R0_SUS

RF@

2

C8615

0.1U_0201_6.3V6K

1

Close to L1

MURATA BLM15EG221SN1D

0.1U_0201_6.3V6K

B B

VCC3M VCC3M_PCH

VCC1R0_SUS VCC1R0_SUS_PRIM

VCCMPHY_GATE VCCMPHY_GATE_OUT

VCCMPHY_GATE

1 2

VCC1R0_SUS

1 2

BLM15EG221SN1D_2P

VCC3_SUS

1 2

SM01000HC00

R_0402

RF@

2

C8613

1

@

0_0603_5%

1 2

R2485

@

0_0603_5%

1 2

R2486

@

0_0603_5%

1 2

R2487

FVT_C_EC013

@

R2302

0_0603_5%

L2

RF@

L1

VCCMPHY_GATE_PLL

VCC1R0_SUS_PLL

RF@

2

C2449

0.1U_0201_6.3V6K

1

RF@

2

C8612

0.1U_0201_6.3V6K

1

FVT_C_EC017

@

2

C2447 1U_0402_6.3V6K

1

88mA

2

RF@

C2437

0.1U_0402_16V4Z

1

NEAR K15

26mA

40mA

2

1

VCC3_SUS

VCCMPHY_GATE_OUT

C620 1U_0402_6.3V6K

VCC3M_PCH

11mA

75mA

2574mA

118mA

2

C8530

0.1U_0201_6.3V6K

1

1870mA

642mA

33mA

22mA

VCC1R0_SUS_PRIMVCC1R0_SUSVCCPCHCORE

696mA

U58O

AB19

VCCPRIM_1P0

AB20

VCCPRIM_1P0

P18

VCCPRIM_1P0

AF18

VCCPRIM_CORE

AF19

VCCPRIM_CORE

V20

VCCPRIM_CORE

V21

VCCPRIM_CORE

AL1

DCPDSW_1P0

K17

VCCMPHYAON_1P0

L1

VCCMPHYAON_1P0

N15

VCCMPHYGT_1P0_N15

N16

VCCMPHYGT_1P0_N16

N17

VCCMPHYGT_1P0_N17

P15

VCCMPHYGT_1P0_P15

P16

VCCMPHYGT_1P0_P16

K15

VCCAMPHYPLL_1P0

L15

VCCAMPHYPLL_1P0

V15

VCCAPLL_1P0

AB17

VCCPRIM_1P0_AB17

Y18

VCCPRIM_1P0_Y18

AD17

VCCDSW_3P3_AD17

AD18

VCCDSW_3P3_AD18

AJ17

VCCDSW_3P3_AJ17

AJ19

VCCHDA

AJ16

VCCSPI

AF20

VCCSRAM_1P0

AF21

VCCSRAM_1P0

T19

VCCSRAM_1P0

T20

VCCSRAM_1P0

AJ21

VCCPRIM_3P3_AJ21

AK20

VCCPRIM_1P0_AK20

N18

VCCAPLLEBB

KBL-RU_BGA1356

@

CPU POWER 4 OF 4

SKL-U

15 OF 20

VCCPGPPA VCCPGPPB VCCPGPPC VCCPGPPD VCCPGPPE VCCPGPPF VCCPGPPG

VCCPRIM_3P3_V19

VCCPRIM_1P0_T1

VCCATS_1P8

VCCRTCPRIM_3P3

VCCRTC_AK19 VCCRTC_BB14

DCPRTC

VCCCLK1

VCCCLK2

VCCCLK3

VCCCLK4

VCCCLK5

VCCCLK6

GPP_B0/CORE_VID0 GPP_B1/CORE_VID1

VCCMPHY_GATE

R9325

AK15

20mA

AG15

4mA

Y16

6mA

Y15

8mA

T16

6mA

AF16

161mA

AD15

41mA

V19

200mA

T1

AA1

6mA

AK17

AK19 BB14

BB10

A14

K19

L21

N20

L19

A10

AN11 AN13

VCC3_SUS

@

0_0603_5%

1 2

VCC1R8_SUS

VCC1R0_SUS

VCC1R0_SUS_PRIM

696mA

VCC1R0_SUS

35mA

24mA

39mA

1 2

C795

0.1U_0201_6.3V6K

VCC3_SUS VCC1R8_SUS VCC1R0_SUS VCCPCHCORE

2

C763

0.1U_0201_6.3V6K

1

200mA

2

1

2

1

RTCVCC

2

1

C2428 47U_0805_6.3V6M

VCC3_SUS

2

@RF@

C8622 68P_0201_25V8

1

200mA

C832

0.1U_0201_6.3V6K

C731 1U_0402_6.3V6K

VCC3_SUS

2

1

2

1

2

@RF@

C8623 2200P_0201_50V7K

1

C380 1U_0402_6.3V6K

@

C2429 47U_0805_6.3V6M

29mA

2

1

2

@RF@

C8624 68P_0201_25V8

1

33mA

2

1

2

1

4mA

2

1

C2430 47U_0805_6.3V6M

@

C2450 22U_0603_6.3V6M

@

C2452 22U_0603_6.3V6M

@

C2454 22U_0603_6.3V6M

2

1

2

@RF@

C8625 2200P_0201_50V7K

1

R2304

@

2

C2451 22U_0603_6.3V6M

1

R2305

@

2

C2453 22U_0603_6.3V6M

1

@

2

C2455 22U_0603_6.3V6M

1

C2431 47U_0805_6.3V6M

@

0_0603_5%

1 2

@

0_0603_5%

1 2

@

R2306 0_0603_5%

1 2

VCC1R0_SUS

FVT_C_EC013

VCC1R0_SUS_PRIM VCC1R0_SUS VCCPCHCORE VCC3_SUS VCCMPHY_GATE_OUT VCCMPHY_GATE_OUT VCC3_SUS VCC1R8_SUS VCC1R0_SUS

@

2

C2432 1U_0402_6.3V6K

1

2

C2433 1U_0402_6.3V6K

1

@

2

C2434 1U_0402_6.3V6K

1

@

2

C821 1U_0402_6.3V6K

1

2

C2435 1U_0402_6.3V6K

1

@

2

C2436 47U_0805_6.3V6M

1

@

2

C2438 1U_0402_6.3V6K

1

2

C2439 1U_0402_6.3V6K

1

Reserved for RF

A A

VCC3B VCC5M VCC3M VCC3MVCC3M VCC1R8_SUS VCC1R8_SUS VCC1R8_SUS VCC1R8_SUS

2

RF@

C8799

0.1U_0201_6.3V6K

1

5

2

RF@

C8800

0.1U_0201_6.3V6K

1

2

RF@

C8801

0.1U_0402_16V4Z

1

@RF@

2

C8802 1U_0402_6.3V6K

1

2

RF@

C8803

0.1U_0402_16V4Z

1

4

@RF@

2

C8804 1U_0402_6.3V6K

1

@RF@

2

C8805 1U_0402_6.3V6K

1

@RF@

2

C8806 1U_0402_6.3V6K

1

@RF@

2

C8807 1U_0402_6.3V6K

1

VCC5M

2

@RF@

C8809

0.1U_0201_6.3V6K

1

3

@

2

C2440 1U_0402_6.3V6K

1

VCC3M VCC5M

VCC3M VCC5M VCC3M VCC5M

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C8808

0.1U_0402_16V4Z

RF@

C8811

1U_0402_6.3V6K

@RF@

Issued Date

@

2

C2441 1U_0402_6.3V6K

1

12

@

2

C2442 1U_0402_6.3V6K

1

VCC3M VCC5M

2014/11/04 2016/12/31

@

2

C2443 1U_0402_6.3V6K

1

C8810

12

0.1U_0402_16V4Z

RF@

C8812

12

1U_0402_6.3V6K

@RF@

Compal Secret Data

2

VCC3M VCC5M

C8813

12

1U_0402_6.3V6K

@RF@

VCC3B VCC5M

C8814

12

1U_0402_6.3V6K

@RF@

Deciphered Date

2

C2444 1U_0402_6.3V6K

1

VCCGFXCORE_I VCC5M

VCC3M VCCGFXCORE_I

@

2

C2445 1U_0402_6.3V6K

1

NEAR A10NEAR AA1NEAR V19NEAR T16NEAR Y16NEAR AG15NEAR N18NEAR AF20NEAR N15NEAR N15NEAR AJ19NEAR AF18NEAR K17NEAR AB19

C8815

12

1U_0402_6.3V6K

@RF@

C8816

12

1U_0402_6.3V6K

@RF@

Compal Electronics, Inc.

Title

CPU : PCH POWER

Size Document Number Rev

Custom

LA-F421P

Date: Sheet

1

of

17 73Monday, October 23, 2017

1.0

5

D D

4

3

2

1

SKL-U

U58P

A5

VSS

A67

VSS

A70

VSS

AA2

VSS

AA4

VSS

AA65

VSS

AA68

VSS

AB15

VSS

AB16

VSS

AB18

VSS

AB21

VSS

AB8

VSS

C C

B B

AD13 AD16 AD19 AD20 AD21 AD62

AE64 AE65 AE66 AE67 AE68 AE69

AG16 AG17 AG18 AG19 AG20 AG21 AG71 AH13

AH63 AH64 AH67

AK11 AK16 AK18 AK21 AK22 AK27 AK63 AK68 AK69

AD8

AF1 AF10 AF15 AF17

AF2

AF4 AF63

AH6

AJ15 AJ18 AJ20

AJ4

AK8

AL2 AL28 AL32 AL35 AL38

AL4 AL45 AL48 AL52 AL55 AL58 AL64

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

KBL-RU_BGA1356

GND 1 OF 3

16 OF 20

@

AL65

VSS

AL66

VSS

AM13

VSS

AM21

VSS

AM25

VSS

AM27

VSS

AM43

VSS

AM45

VSS

AM46

VSS

AM55

VSS

AM60

VSS

AM61

VSS

AM68

VSS

AM71

VSS

AM8

VSS

AN20

VSS

AN23

VSS

AN28

VSS

AN30

VSS

AN32

VSS

AN33

VSS

AN35

VSS

AN37

VSS

AN38

VSS

AN40

VSS

AN42

VSS

AN58

VSS

AN63

VSS

AP10

VSS

AP18

VSS

AP20

VSS

AP23

VSS

AP28

VSS

AP32

VSS

AP35

VSS

AP38

VSS

AP42

VSS

AP58

VSS

AP63

VSS

AP68

VSS

AP70

VSS

AR11

VSS

AR15

VSS

AR16

VSS

AR20

VSS

AR23

VSS

AR28

VSS

AR35

VSS

AR42

VSS

AR43

VSS

AR45

VSS

AR46

VSS

AR48

VSS

AR5

VSS

AR50

VSS

AR52

VSS

AR53

VSS

AR55

VSS

AR58

VSS

AR63

VSS

AR8

VSS

AT2

VSS

AT20

VSS

AT23

VSS

AT28

VSS

AT35

VSS

AT4

VSS

AT42

VSS

AT56

VSS

AT58

VSS

AT63 AT68 AT71 AU10 AU15 AU20 AU32 AU38

AV68 AV69 AV70

AV71 AW10 AW12 AW14 AW16 AW18 AW21 AW23 AW26 AW28 AW30 AW32 AW34 AW36 AW38 AW41 AW43 AW45 AW47 AW49 AW51 AW53 AW55 AW57

AW60 AW62 AW64 AW66

AY66

BA10

BA14

BA18

BA23

BA28

BA32

BA36

BA45

AV1

AW6

AW8

BA1

BA2

B10 B14 B18 B22 B30 B34 B39 B44 B48 B53 B58 B62 B66 B71

F68

U58Q

GND 2 OF 3

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

KBL-RU_BGA1356

SKL-U

17 OF 20

@

BA49

VSS

BA53

VSS

BA57

VSS

BA6

VSS

BA62

VSS

BA66

VSS

BA71

VSS

BB18

VSS

BB26

VSS

BB30

VSS

BB34

VSS

BB38

VSS

BB43

VSS

BB55

VSS

BB6

VSS

BB60

VSS

BB64

VSS

BB67

VSS

BB70

VSS

C1

VSS

C25

VSS

C5

VSS

D10

VSS

D11

VSS

D14

VSS

D18

VSS

D22

VSS

D25

VSS

D26

VSS

D30

VSS

D34

VSS

D39

VSS

D44

VSS

D45

VSS

D47

VSS

D48

VSS

D53

VSS

D58

VSS

D6

VSS

D62

VSS

D66

VSS

D69

VSS

E11

VSS

E15

VSS

E18

VSS

E21

VSS

E46

VSS

E50

VSS

E53

VSS

E56

VSS

E6

VSS

E65

VSS

E71

VSS

F1

VSS

F13

VSS

F2

VSS

F22

VSS

F23

VSS

F27

VSS

F28

VSS

F32

VSS

F33

VSS

F35

VSS

F37

VSS

F38

VSS

F4

VSS

F40

VSS

F42

VSS

BA41

VSS

G10 G22 G43 G45 G48

G52 G55 G58

G60 G63 G66 H15 H18 H71

K16 K18 K22 K61 K63 K64 K65 K66 K67 K68 K70 K71

U58R

F8

G5

G6

J11 J13 J25 J28 J32 J35 J38 J42

J8

L11 L16 L17

GND 3 OF 3

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

KBL-RU_BGA1356

SKL-U

18 OF 20

@

L18

VSS

L2

VSS

L20

VSS

L4

VSS

L8

VSS

N10

VSS

N13

VSS

N19

VSS

N21

VSS

N6

VSS

N65

VSS

N68

VSS

P17

VSS

P19

VSS

P20

VSS

P21

VSS

R13

VSS

R6

VSS

T15

VSS

T17

VSS

T18

VSS

T2

VSS

T21

VSS

T4

VSS

U10

VSS

U63

VSS

U64

VSS

U66

VSS

U67

VSS

U69

VSS

U70

VSS

V16

VSS

V17

VSS

V18

VSS

W13

VSS

W6

VSS

W9

VSS

Y17

VSS

Y19

VSS

Y20

VSS

Y21

VSS

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/11/04 2016/12/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

CPU : GND

Size Document Number Rev

Custom

LA-F421P

Date: Sheet

1

of

18 73Monday, October 23, 2017

1.0

5

D D

4

3

2

1

TABLE

CFG0 : Stall Reset Sequence after PCU PLL Lock until de-asserted 1 : No Stall 0 : Stall

CFG3 : MSR Privacy Bit Feature 1 : MSR (C80h) bit[0] setting 0 : MSR (C80h) bit[0] overridden

CFG4 : eDP Enable 1 : Disabled 0 : Enabled

CFG9 : SVID Bus Communication 1 : Enabled 0 : Disabled

RESERVED SIGNALS-1

SKL-U

19 OF 20

RSVD_TP_BB68 RSVD_TP_BB69

RSVD_TP_AK13 RSVD_TP_AK12

RSVD_BB2 RSVD_BA3

RSVD_D5 RSVD_D4 RSVD_B2 RSVD_C2

RSVD_B3 RSVD_A3

RSVD_AW1

RSVD_E1 RSVD_E2

RSVD_BA4 RSVD_BB4

RSVD_A4 RSVD_C4

RSVD_A69 RSVD_B69

RSVD_AY3

RSVD_D71 RSVD_C70

RSVD_C54 RSVD_D54

VSS_AY71

ZVM#

RSVD_TP_AW71 RSVD_TP_AW70

MSM#

PROC_SELECT#

BB68 BB69

AK13 AK12

BB2 BA3

AU5

TP5

AT5

TP6

D5 D4 B2 C2

B3 A3

AW1

E1 E2

BA4 BB4

A4 C4

BB5

TP4

A69 B69

AY3

D71 C70

C54 D54

AY4

TP1

BB3

TP2

AY71 AR56

AW71 AW70

AP56 C64

@

R2287 0_0201_5%

R2288 0_0201_5%

12

@

12

1 2

@

R2289 100K_0201_5%

FVT_C_EC010

VCCST

U58S

@

E68

CFG[0]

49.9_0201_1%

1 2

B67 D65 D67

E70 C68 D68 C67

F71 G69

F70 G68 H70 G71 H69 G70

E63

F63

E66

F66

E60

E8

AY2 AY1

D1 D3

K46

K45

AL25 AL27

C71

B70

F60

A52

BA70 BA68

J71

J68

F65 G65

F61

E61

CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15]

CFG[16] CFG[17]

CFG[18] CFG[19]

CFG_RCOMP

ITP_PMODE

RSVD_AY2 RSVD_AY1

RSVD_D1 RSVD_D3

RSVD_K46 RSVD_K45

RSVD_AL25 RSVD_AL27

RSVD_C71 RSVD_B70

RSVD_F60

RSVD_A52

RSVD_TP_BA70 RSVD_TP_BA68

RSVD_J71 RSVD_J68

VSS_F65 VSS_G65

RSVD_F61 RSVD_E61

KBL-RU_BGA1356

C C

B B

CFG3[20]

1K_0201_5%

1 2

@

R1892

ITP_PMODE[20]

1 2

@

R1891

R8965

R8898

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/11/04 2016/12/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

CPU : CFG/RESERVED

Size Document Number Rev

Custom

LA-F421P

Date: Sheet

1

of

19 73Monday, October 23, 2017

1.0

5

D D

VCC1R0_SUS VCCST VCC1R0_SUS

XDP@

R588

R594 1K_0201_5%

51_0201_5%

XDP@

1 2

1.5K_0201_5%

1 2

XDP_TCK0[7]

PCH_TCK[7] XDP_TMS[7] XDP_TDI[7]

-XDP_TRST[7]

XDP_TDO[7]

-XDP_DBR[14]

ITP_PMODE[19]

C C

-RSMRST[14,53]

XDP_TCK0

PCH_TCK XDP_TMS XDP_TDI

-XDP_TRST XDP_TDO

-XDP_DBR ITP_PMODE

-RSMRST

CFG3[19]

R9385 0_0201_5%XDP@

-XDP_PRDY[11]

-XDP_PREQ[11]

1 2

-XDP_PRDY

-XDP_PREQ

4

2

XDP@

1 2

1

C8320

R475

0.1U_0201_6.3V6K

JXDP1

28

GND

27

GND

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

ACES_51522-02601-001

ME@

3

2

1

TABLE

Ref Des

Logic

Page 7

Page 18

Page 19

R1982

J8

C8320

R475

R491

R588

R594

B B

R2494

A A

5

Merged DCI 2.0

ASMR2559

ASM

4

NO_ASM

ASM

NO_ASM

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/11/04 2016/12/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

XDP CONNECTOR

Size Document Number Rev

Custom

LA-F421P

Date: Sheet

1

of

20 73Monday, October 23, 2017

1.0

5

D D

C C

-SPI_CS0[8]

SPI_MISO_IO1[8,45]

4

-SPI_CS0 -SPI_CS0_R SPI_MISO_IO1 SPI_MISO_IO1_0_R

1 2

R322 33_0201_5%

1 2

R694 33_0201_5%

VCC3_SUS

1 2

10K_0201_5%

@

R2342

U49

1

/CS

2

DO(IO1)

3

/WP(IO2) GND4DI(IO0)

W25Q128JVSIQ_SO8

3

0.1U_0201_6.3V6K

/HOLD(IO3)

2

16MB SOIC8 WINBOND W25Q128JVSIQ

2

C629

1

8

VCC

7 6

CLK

5

1 2

3.3K_0201_5%

R703

R706

SPI_IO3_0_R

SPI_IO2_0_R

R8981 33_0201_5% R681 33_0201_5% R674 33_0201_5%

R8980 33_0201_5%

MACRONIX MX25L12873FM2I-10G

1 2

12 12

1 2

SPI_MOSI_IO0SPI_MOSI_IO0_0_R

SPI_IO3 SPI_CLKSPI_CLK_0_R

SPI_IO2

SPI_IO3 [8] SPI_CLK [8,45] SPI_MOSI_IO0 [8,45]

SPI_IO2 [8]

1

Change to W25Q128JVSIQ (SA00005VV20)

TABLE

B B

A A

5

4

SF100 PIN HEADER INTERFACE (TOP VIEW)

1 VCC D12.1

3 CS# R322.2

5 MISO R694.2

7 (KEY) N/A

GND GND 2

R681.2 CLK 4

R674.2 MOSI 6

N/A (RESET) 8

3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/11/04 2016/12/31

Compal Secret Data

Deciphered Date

2

Custom

Date: Sheet

Compal Electronics, Inc.

Title

SPI FLASH

Size Document Number Rev

LA-F421P

1

of

21 73Monday, October 23, 2017

1.0

A

B

C

VCC2R5A M_A_VREF_CA

D

E

DDR_A_D[63:0][5,6]

-DDR_A_DQS[7:0][5,6]

DDR_A_DQS[7:0][5,6]

1 1

2 2

3 3

DDR_A_MA[16:0][5,23]

VCC1R2A VCC2R5A

DDR_A_D18 DDR_A_D17 DDR_A_D23 DDR_A_D16 DDR_A_D19 DDR_A_D21 DDR_A_D22 DDR_A_D20

DDR_A_DQS2

-DDR_A_DQS2

DDR_A_D14 DDR_A_D13 DDR_A_D15 DDR_A_D8 DDR_A_D10 DDR_A_D9 DDR_A_D11 DDR_A_D12

DDR_A_DQS1

-DDR_A_DQS1

DDR_A_CLK0

-DDR_A_CLK0

DDR_A_CKE0[5,23]

-DDR_A_CS0[5,23]

DDR_A_ODT0[5,23]

-DDR_A_ACT[5,23]

DDR_A_BG0[5,23]

DDR_A_BA1[5,23] DDR_A_BA0[5,23]

DDR_A_CKE0

-DDR_A_CS0

DDR_A_ODT0

-DDR_A_ACT

DDR_A_BG1_R DDR_A_BG0

DDR_A_BA1 DDR_A_BA0

DDR_A_MA16 DDR_A_MA15 DDR_A_MA14

DDR_A_MA13 DDR_A_MA12 DDR_A_MA11 DDR_A_MA10 DDR_A_MA9 DDR_A_MA8 DDR_A_MA7 DDR_A_MA6 DDR_A_MA5 DDR_A_MA4 DDR_A_MA3 DDR_A_MA2 DDR_A_MA1 DDR_A_MA0

X76@

U125

D7 D3 C8 C2 C7 C3

B8 A3

B7 A7

E2

J7

J3 H8 H2 H7 H3

F7 G2

G3

F3

K7

K8

K2

L7

K3

L3

M9 M2

N8 N2

L8 M8

L2

T8 M7

T2 M3 R7 R2 R8

P2

P8 N3 N7 R3

P7

P3

MT40A1G16HBA-083E-A_FBGA96

X76@

R2549 0_0201_5%

1 2

DQU7 DQU6 DQU5 DQU4 DQU3 DQU2 DQU1 DQU0

DQSU_T DQSU_C

DMU#/DBIU#

DQL7 DQL6 DQL5 DQL4 DQL3 DQL2 DQL1 DQL0

DQSL_T DQSL_C

DML#/DBIL#E7VSSQ_A2

CK_T CK_C

CKE

CS#

ODT

ACT#

BG1_VSS BG0

BA1 BA0

A16/RAS# A15/CAS# A14/WE#

A13 A12/BC# A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

VREFCA

VDDQ_A1 VDDQ_A9 VDDQ_C1 VDDQ_D9 VDDQ_F2 VDDQ_F8 VDDQ_G1 VDDQ_G9

VDDQ_J2 VDDQ_J8

VSSQ_A8 VSSQ_C9 VSSQ_D2 VSSQ_D8

VSSQ_E3

VSSQ_E8

VSSQ_F1 VSSQ_H1

ZQU_VSS

96-BALL

SDRAM DDR4

VPP_B1 VPP_R9

VDD_B3 VDD_B9 VDD_D1 VDD_G7 VDD_J1 VDD_J9 VDD_L1 VDD_L9 VDD_R1 VDD_T9

VSS_H9

VSS_B2

VSS_E1 VSS_G8 VSS_K1 VSS_K9 VSS_N1 VSS_T1

VSS_NC

RESET#

PARITY

ALERT#

ZQL_ZQ

TEN

2

C2552

0.1U_0201_6.3V6K

1

B1 R9

M1

B3 B9 D1 G7 J1 J9 L1 L9 R1 T9

A1 A9 C1 D9 F2 F8 G1 G9 J2 J8

A2 A8 C9 D2 D8 E3 E8 F1 H1 H9

B2 E1 G8 K1 K9 N1 T1

T7

P1

T3

P9

E9

F9

N9

243_0201_1%

R9009

2

0.1U_0201_6.3V6K

1

M_A_VREF_CA

-DRAMRST

DDR_A_PAR

-DDR_A_ALERT

1 2

C2553

VCC1R2A

R9010 243_0201_1%

X76@

1 2

2

C2554

0.1U_0201_6.3V6K

1

2

1

DDR_A_D24 DDR_A_D26 DDR_A_D25 DDR_A_D30 DDR_A_D28 DDR_A_D29 DDR_A_D31 DDR_A_D27

DDR_A_DQS3

-DDR_A_DQS3

DDR_A_D5 DDR_A_D2 DDR_A_D1 DDR_A_D3 DDR_A_D4 DDR_A_D7 DDR_A_D0 DDR_A_D6

DDR_A_DQS0

-DDR_A_DQS0

DDR_A_CLK0

-DDR_A_CLK0

DDR_A_CKE0

-DDR_A_CS0

DDR_A_ODT0

-DDR_A_ACT

DDR_A_BG1_R DDR_A_BG0

DDR_A_BA1 DDR_A_BA0

DDR_A_MA16 DDR_A_MA15 DDR_A_MA14

DDR_A_MA13 DDR_A_MA12 DDR_A_MA11 DDR_A_MA10 DDR_A_MA9 DDR_A_MA8 DDR_A_MA7 DDR_A_MA6 DDR_A_MA5 DDR_A_MA4 DDR_A_MA3 DDR_A_MA2 DDR_A_MA1 DDR_A_MA0

C2555

0.1U_0201_6.3V6K

2

C2619

0.1U_0201_6.3V6K

1

VCC1R2A VCC2R5A

U126

D7

DQU7

D3

DQU6

C8

DQU5

C2

DQU4

C7

DQU3

C3

DQU2

B8

DQU1

A3

DQU0

B7

DQSU_T

A7

DQSU_C

E2

DMU#/DBIU#

J7

DQL7

J3

DQL6

H8

DQL5

H2

DQL4

H7

DQL3

H3

DQL2

F7

DQL1

G2

DQL0

G3

DQSL_T

F3

DQSL_C

DML#/DBIL#E7VSSQ_A2

K7

CK_T

K8

CK_C

K2

CKE

L7

CS#

K3

ODT

L3

ACT#

M9

BG1_VSS

M2

BG0

N8

BA1

N2

BA0

L8

A16/RAS#

M8

A15/CAS#

L2

A14/WE#

T8

A13

M7

A12/BC#

T2

A11

M3

A10/AP

R7

A9

R2

A8

R8

A7

P2

A6

P8

A5

N3

A4

N7

A3

R3

A2

P7

A1

P3

A0

MT40A1G16HBA-083E-A_FBGA96

X76@

R2550

X76@

0_0201_5%

1 2

VDDQ_A1 VDDQ_A9 VDDQ_C1 VDDQ_D9 VDDQ_F2 VDDQ_F8 VDDQ_G1 VDDQ_G9

VDDQ_J2 VDDQ_J8

VSSQ_A8 VSSQ_C9 VSSQ_D2 VSSQ_D8

VSSQ_E3

VSSQ_E8

VSSQ_F1 VSSQ_H1

ZQU_VSS

96-BALL

SDRAM DDR4

VPP_B1 VPP_R9

VREFCA

VDD_B3 VDD_B9 VDD_D1 VDD_G7 VDD_J1 VDD_J9 VDD_L1 VDD_L9 VDD_R1 VDD_T9

VSS_H9

VSS_B2 VSS_E1 VSS_G8 VSS_K1 VSS_K9 VSS_N1 VSS_T1

VSS_NC

RESET#

PARITY

ALERT#

ZQL_ZQ

2

1

TEN

C2620

0.1U_0201_6.3V6K

B1 R9

M1

B3 B9 D1 G7 J1 J9 L1 L9 R1 T9

A1 A9 C1 D9 F2 F8 G1 G9 J2 J8

A2 A8 C9 D2 D8 E3 E8 F1 H1 H9

B2 E1 G8 K1 K9 N1 T1

T7

P1

T3

P9

E9

F9

N9

R9011

243_0201_1%

2

C2621

0.1U_0201_6.3V6K

1

M_A_VREF_CA

DDR_A_PAR

-DDR_A_ALERT

1 2

2

C2622

0.1U_0201_6.3V6K

1

VCC1R2A VCC1R2A VCC2R5A

-DRAMRST

R9012 243_0201_1%

X76@

1 2

2

C2623 10U_0402_6.3V6M

1

DDR_A_D52 DDR_A_D55 DDR_A_D53 DDR_A_D51 DDR_A_D49 DDR_A_D54 DDR_A_D48 DDR_A_D50

DDR_A_DQS6

-DDR_A_DQS6

DDR_A_D32 DDR_A_D33 DDR_A_D35 DDR_A_D34 DDR_A_D37 DDR_A_D39 DDR_A_D36 DDR_A_D38

DDR_A_DQS4

-DDR_A_DQS4

DDR_A_CLK0

-DDR_A_CLK0

DDR_A_CKE0

-DDR_A_CS0

DDR_A_ODT0

-DDR_A_ACT

DDR_A_BG1_R DDR_A_BG0

DDR_A_BA1 DDR_A_BA0

DDR_A_MA16 DDR_A_MA15 DDR_A_MA14

DDR_A_MA13 DDR_A_MA12 DDR_A_MA11 DDR_A_MA10 DDR_A_MA9 DDR_A_MA8 DDR_A_MA7 DDR_A_MA6 DDR_A_MA5 DDR_A_MA4 DDR_A_MA3 DDR_A_MA2 DDR_A_MA1 DDR_A_MA0

X76@

1 2

2

C2624 10U_0402_6.3V6M

1

U127

D7

DQU7

D3

DQU6

C8

DQU5

C2

DQU4

C7

DQU3

C3

DQU2

B8

DQU1

A3

DQU0

B7

DQSU_T

A7

DQSU_C

E2

DMU#/DBIU#

J7

DQL7

J3

DQL6

H8

DQL5

H2

DQL4

H7

DQL3

H3

DQL2

F7

DQL1

G2

DQL0

G3

DQSL_T

F3

DQSL_C

DML#/DBIL#E7VSSQ_A2

K7

CK_T

K8

CK_C

K2

CKE

L7

CS#

K3

ODT

L3

ACT#

M9

BG1_VSS

M2

BG0

N8

BA1

N2

BA0

L8

A16/RAS#

M8

A15/CAS#

L2

A14/WE#

T8

A13

M7

A12/BC#

T2

A11

M3

A10/AP

R7

A9

R2

A8

R8

A7

P2

A6

P8

A5

N3

A4

N7

A3

R3

A2

P7

A1

P3

A0

96-BALL

SDRAM DDR4

MT40A1G16HBA-083E-A_FBGA96

X76@

R2551 0_0201_5%

1

C2556

0.047U_0201_10V6K

2

VPP_B1 VPP_R9

VREFCA

VDD_B3

VDD_B9 VDD_D1 VDD_G7

VDD_J1

VDD_J9

VDD_L1

VDD_L9 VDD_R1

VDD_T9

VDDQ_A1 VDDQ_A9 VDDQ_C1 VDDQ_D9

VDDQ_F2

VDDQ_F8 VDDQ_G1 VDDQ_G9

VDDQ_J2

VDDQ_J8

VSSQ_A8

VSSQ_C9

VSSQ_D2

VSSQ_D8

VSSQ_E3

VSSQ_E8

VSSQ_F1

VSSQ_H1

VSS_H9

VSS_B2 VSS_E1 VSS_G8 VSS_K1 VSS_K9 VSS_N1 VSS_T1

VSS_NC

RESET#

PARITY

ALERT#

ZQU_VSS

ZQL_ZQ

TEN

B1 R9

M1

B3 B9 D1 G7 J1 J9 L1 L9 R1 T9

A1 A9 C1 D9 F2 F8 G1 G9 J2 J8

A2 A8 C9 D2 D8 E3 E8 F1 H1 H9

B2 E1 G8 K1 K9 N1 T1

T7

P1

T3

P9

E9

F9

N9

R9013

243_0201_1%

DDR_A_D59 DDR_A_D57 DDR_A_D58 DDR_A_D60 DDR_A_D63 DDR_A_D56 DDR_A_D62 DDR_A_D61

DDR_A_DQS7

-DDR_A_DQS7

DDR_A_D46 DDR_A_D40 DDR_A_D47 DDR_A_D41 DDR_A_D43 DDR_A_D45 DDR_A_D42 DDR_A_D44

DDR_A_DQS5

-DDR_A_DQS5

DDR_A_CLK0

-DDR_A_CLK0

DDR_A_CKE0

-DDR_A_CS0

DDR_A_ODT0

-DDR_A_ACT

DDR_A_BG1_R DDR_A_BG0

DDR_A_BA1 DDR_A_BA0

DDR_A_MA16 DDR_A_MA15 DDR_A_MA14

DDR_A_MA13 DDR_A_MA12 DDR_A_MA11 DDR_A_MA10 DDR_A_MA9 DDR_A_MA8 DDR_A_MA7 DDR_A_MA6 DDR_A_MA5 DDR_A_MA4 DDR_A_MA3 DDR_A_MA2 DDR_A_MA1 DDR_A_MA0

1

C2559

0.047U_0201_10V6K

2

X76@

1 2

U128

D7

DQU7

D3

DQU6

C8

DQU5

C2

DQU4

C7

DQU3

C3

DQU2

B8

DQU1

A3

DQU0

B7

DQSU_T

A7

DQSU_C

E2

DMU#/DBIU#

J7

DQL7

J3

DQL6

H8

DQL5

H2

DQL4

H7

DQL3

H3

DQL2

F7

DQL1

G2

DQL0

G3

DQSL_T

F3

DQSL_C

DML#/DBIL#E7VSSQ_A2

K7

CK_T

K8

CK_C

K2

CKE

L7

CS#

K3

ODT

L3

ACT#

M9

BG1_VSS

M2

BG0

N8

BA1

N2

BA0

L8

A16/RAS#

M8

A15/CAS#

L2

A14/WE#

T8

A13

M7

A12/BC#

T2

A11

M3

A10/AP

R7

A9

R2

A8

R8

A7

P2

A6

P8

A5

N3

A4

N7

A3

R3

A2

P7

A1

P3

A0

96-BALL

SDRAM DDR4

MT40A1G16HBA-083E-A_FBGA96

X76@

R2552 0_0201_5%

1

C2557

0.047U_0201_10V6K

2

M_A_VREF_CA

-DRAMRST

DDR_A_PAR

-DDR_A_ALERT

1 2

1

C2558

0.047U_0201_10V6K

2

VCC1R2A VCC1R2A VCC2R5A

R9014 243_0201_1%

X76@

1 2

VPP_B1 VPP_R9

VREFCA

VDD_B3

VDD_B9 VDD_D1 VDD_G7

VDD_J1

VDD_J9

VDD_L1

VDD_L9 VDD_R1

VDD_T9

VDDQ_A1

VDDQ_A9 VDDQ_C1 VDDQ_D9

VDDQ_F2

VDDQ_F8 VDDQ_G1 VDDQ_G9

VDDQ_J2

VDDQ_J8

VSSQ_A8

VSSQ_C9

VSSQ_D2

VSSQ_D8

VSSQ_E3

VSSQ_E8

VSSQ_F1

VSSQ_H1

VSS_H9

VSS_B2 VSS_E1 VSS_G8 VSS_K1 VSS_K9 VSS_N1 VSS_T1

VSS_NC

RESET#

PARITY

ALERT#

ZQU_VSS

ZQL_ZQ

TEN

B1 R9

M1

B3 B9 D1 G7 J1 J9 L1 L9 R1 T9

A1 A9 C1 D9 F2 F8 G1 G9 J2 J8

A2 A8 C9 D2 D8 E3 E8 F1 H1 H9

B2 E1 G8 K1 K9 N1 T1

T7

P1

T3

P9

E9

F9

N9

R9015

243_0201_1%

M_A_VREF_CA

-DRAMRST

DDR_A_PAR

-DDR_A_ALERT

1 2

VCC1R2A

R9016 243_0201_1%

X76@

1 2

DDR_A_CLK0[5,23]

-DDR_A_CLK0[5,23]

DDR_A_BG1[5] DDR_A_BG1_R [23]

4 4

-DRAMRST[6,24]

DDR_A_PAR[5,23]

-DDR_A_ALERT[5,23]

DDR_A_CLK0

-DDR_A_CLK0

DDR_A_BG1 DDR_A_BG1_R

-DRAMRST

DDR_A_PAR

-DDR_A_ALERT

A

R2553

2

1

0_0201_5%

1 2

X76@

@

C1063

0.1U_0201_6.3V6K

B

R2549 R2550 R2551 R2552

R2553

R9041

R9010 R9012 R9014 R9016

SDP DDP

ASM

NA

ASM

NA

ASM

NA

ASM

NA

ASM

NA

ASM

243_1%

0_5%

243_1%

0_5%

243_1%

0_5%

243_1%

0_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

TABLE

For RF shielding case

CLIP2

CLIP3

CLIP1

HOLEA

ME@

1

CLIP13

CLIP14

HOLEA

ME@

1

2014/11/04 2016/12/31

CLIP4

HOLEA

ME@

1

CLIP15

CLIP16

HOLEA

ME@

1

Compal Secret Data

Deciphered Date

D

CLIP5 HOLEA

1

CLIP17 HOLEA

1

ME@

CLIP6 HOLEA

CLIP18 HOLEA

ME@

1

ME@

1

CLIP7 HOLEA

1

CLIP19 HOLEA

1

ME@

CLIP9

CLIP8 HOLEA

1

CLIP20 HOLEA

1

ME@

CLIP10

HOLEA

ME@

1

CLIP21

CLIP22

HOLEA

ME@

1

Title

Size Document Number Rev

Custom

Date: Sheet

CLIP12

CLIP11

HOLEA

ME@

1

CLIP23

CLIP24

HOLEA

ME@

1

Compal Electronics, Inc.

DDR4 BASE MEMORY CH-A (1/2)

LA-F421P

E

1.0

of

22 73Monday, October 23, 2017

Lenovo X380 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual