Lenovo V310-14ISK, V310-15ISK Schematic

1

2

3

4

5

6

7

8

Intel Skylake-U Platform Block Diagram (Windows)

01

DDR4 Memory Down MA

A A

DDR4 SO-DIMM X1 MB

1866-2133 MT/s

PCIE Gen3*4

AMD dGPU

R16M-M1-30

S3

eDP Conn(30pin)
FHD support

HD Camera

eDP 2 Lanes

USB2.0 (480Mb/s)

DMIC

HDMI Conn

HDD

B B

ODD

HDMI (1.65Gb/s)

SATA Gen3 (6Gb/s)

SATA Gen3 (6Gb/s)

Skylake-U SoC

SATA Gen3 (6Gb/s)

M.2 NGFF SSD

PCIE Gen3 * 4

Intel

15W

BGA 1356

Size : 42x24(mm)

HP/Mic Audio

HDA

USB3.0 (5Gb/s)*2

USB2.0 (480Mb/s)*2

PCIE Gen2 *1(5Gb/s)

USB2.0 (480Mb/s)

USB2.0 (480Mb/s)

PCIE Gen2 (5Gb/s)

DP 4 Lanes

1G Ethernet

RTL8111H

Card Reader

RTS5170

4-in-1(SD/SDHC/SDXC/MMC) CONN

NGFF Slot WLAN+BT

Module

M.2 2230

DP SW

PS8338B

VRAM DDR3L

2Gb/4Gb *4

USB 3.0 Port*2

DP to VGA

RTD2166-CG

Combo Jack

AUDIO CODEC

Speaker L/R

ALC3240

USB3.0 (5Gb/s)

USB2.0 (480Mb/s)

Lenovo
Onelink+
Connector

C C

USB2.0 (480Mb/s)

Finger print Sensor

USB2.0 (480Mb/s)

SPI

SPI Flash(16MB)

W25Q128FWSSIG

USB2.0 (480Mb/s)

AOU5 Charger

TPS2546RTER

(Cable
Docking)

USB 2.0 Port*2

24MHz

SMBus

32.768KHz

Synaptics

4

T/P

PS/2

Hall Sensor

EM-1791

5

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

6

7

Date: Sheet of

PROJECT :

RV310 Block Diagram

RV310 Block Diagram

RV310 Block Diagram

LV6

LV6

LV6

8

1A

1A

1A

1 61Friday, March 11, 2016

1 61Friday, March 11, 2016

1 61Friday, March 11, 2016

TPM 1.2

ST33HTPM2E32AAB9

K/B

D D

Thermal Sensor
( 1local +2 remote)

W83773G

SCAN MATRIX

SMBus

WRST#

CPU PTC Circuit

Place near CPU

1

2

3

LPC

EC(ITE)

IT8886

BatteryCharger

5

IN_D2#{26}

D D

HDMI

DOCK DP

+VCCIO

C C

eDP_COMPIO and ICOMPO signals should be shorted near
balls and routed with typical impedance <25 mohms

IN_D2{26}
IN_D1#{26}
IN_D1{26}
IN_D0#{26}
IN_D0{26}
IN_CLK#{26}
IN_CLK{26}

DOCK_DDI2_TXN0{40}
DOCK_DDI2_TXP0{40}
DOCK_DDI2_TXN1{40}
DOCK_DDI2_TXP1{40}
DOCK_DDI2_TXN2{40}
DOCK_DDI2_TXP2{40}
DOCK_DDI2_TXN3{40}
DOCK_DDI2_TXP3{40}

SDVO_CLK{26}
SDVO_DATA{26}

R175 24.9/F_4

+3V

TP7

4

IN_D2#
IN_D2
IN_D1#
IN_D1
IN_D0#
IN_D0
IN_CLK#
IN_CLK

DOCK_DDI2_TXN0
DOCK_DDI2_TXP0
DOCK_DDI2_TXN1
DOCK_DDI2_TXP1
DOCK_DDI2_TXN2
DOCK_DDI2_TXP2
DOCK_DDI2_TXN3
DOCK_DDI2_TXP3

R203 2.2K_4

EDP_RCOMP

U38A

E55

DDI1_TXN[0]

F55

DDI1_TXP[0]

E58

DDI1_TXN[1]

F58

DDI1_TXP[1]

F53

DDI1_TXN[2]

G53

DDI1_TXP[2]

F56

DDI1_TXN[3]

G56

DDI1_TXP[3]

C50

DDI2_TXN[0]

D50

DDI2_TXP[0]

C52

DDI2_TXN[1]

D52

DDI2_TXP[1]

A50

DDI2_TXN[2]

B50

DDI2_TXP[2]

D51

DDI2_TXN[3]

C51

DDI2_TXP[3]

L13

GPP_E18/DDPB_CTRLCLK

L12

GPP_E19/DDPB_CTRLDATA

N7

GPP_E20/DDPC_CTRLCLK

N8

GPP_E21/DDPC_CTRLDATA

N11

GPP_E22/DDPD_CTRLCLK

N12

GPP_E23/DDPD_CTRLDATA

E52

EDP_RCOMP

SKL_ULT

REV = 1

SKL_ULT

DDI

DISPLAY SIDEBANDS

3

?

Need apply PN

EDP

GPP_E13/DDPB_HPD0
GPP_E14/DDPC_HPD1
GPP_E15/DDPD_HPD2
GPP_E16/DDPE_HPD3

EDP_TXN[0]
EDP_TXP[0]
EDP_TXN[1]
EDP_TXP[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]

EDP_AUXN
EDP_AUXP

EDP_DISP_UTIL

DDI1_AUXN
DDI1_AUXP
DDI2_AUXN
DDI2_AUXP
DDI3_AUXN
DDI3_AUXP

GPP_E17/EDP_HPD

EDP_BKLTEN

EDP_BKLTCTL

EDP_VDDEN

?1 OF 20

INT_EDP_TXN0

C47

INT_EDP_TXP0

C46

INT_EDP_TXN1

D46

INT_EDP_TXP1

C45
A45
B45
A47
B47

INT_EDP_AUXN

E45

INT_EDP_AUXP

F45
B52
G50

F50

DOCK_DDI2_AUXN

E48

DOCK_DDI2_AUXP

F48
G46
F46

PCH_HDMI_HPD

L9

PCH_DOCK_DP_HPD

L7
L6
N9

EDP_HPD

L10

PCH_LVDS_BLON

R12

PCH_DPST_PWM

R11

PCH_LCDVCC_EN

U13

2

INT_EDP_TXN0 {25}
INT_EDP_TXP0 {25}
INT_EDP_TXN1 {25}
INT_EDP_TXP1 {25}

INT_EDP_AUXN {25}
INT_EDP_AUXP {25}

DOCK_DDI2_AUXN {40}
DOCK_DDI2_AUXP {40}

PCH_HDMI_HPD {26}
PCH_DOCK_DP_HPD {40}

EDP_HPD {25}
PCH_LVDS_BLON {25}

PCH_DPST_PWM {25}
PCH_LCDVCC_EN {25}

1

+3V{4,10,11,12,13,14,15,17,18,25,26,27,29,30,31,34,36,37,38,40,41,42,45,49,52,53,54}

+VCCIO{4,6,53,56}

+VCCSTPLL{4,5,6,9,45,53,56}

Reserve EDP_HPD opposites circuit!

+3V

R200

*10K_4

R199

100K_4

+VCCSTPLL

+VCCSTPLL

H_PROCHOT#

PM_THRMTRIP#_R

EDP_HPD

R590 1K_4

R583 1K_4

02

B2A

U38D

EC_PECI{36}

TP34
TP36

R601 *51_4

H_PROCHOT#{36,42,43,45}

PM_THRMTRIP#{36}

B B

H_PROCHOT#

+VCCIO

R596 499/F_4
R762 100/F_4

B2A

R278 49.9/F_4
R277 49.9/F_4
R620 GT3@49.9/F_4
R626 GT3@49.9/F_4

CATERR#

EC_PECI

PROCHOT#

PM_THRMTRIP#_R

TP49

PROC_POPIRCOMP
PCH_OPI_RCOMP
EDRAM_OPIO_RCOMP
EOPIO_RCOMP

D63

CATERR#

A54

PECI

C65

PROCHOT#

C63

THERMTRIP#

A65

SKTOCC#

C55

BPM#[0]

D55

BPM#[1]

B54

BPM#[2]

C56

BPM#[3]

A6

GPP_E3/CPU_GP0

A7

GPP_E7/CPU_GP1

BA5

GPP_B3/CPU_GP2

AY5

GPP_B4/CPU_GP3

AT16

PROC_POPIRCOMP

AU16

PCH_OPIRCOMP

H66

OPCE_RCOMP

H65

OPC_RCOMP

SKL_ULT

REV = 1

SKL_ULT

CPU MISC

4 OF 20

JTAG

PROC_TCK

PROC_TDI
PROC_TDO
PROC_TMS

PROC_TRST#

PCH_JTAG_TCK

PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS

PCH_TRST#

JTAGX

PDC

?

B61
D60
A61
C60
B59

B56
D59
A56
C59
C61
A59

XDP_TCK0
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#

XDP_TCK1
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
XDP_TCK0

TP35

XDP_TMS
XDP_TDO
XDP_TDI
XDP_TCK0
XDP_TCK1
EC_PECI

R576 *51_4
R588 51_4
R581
R602 51_4
R603 *51_4
R792 KBY@330_4

*51_4

+VCCIO

PLACE NEAR CPU

Need apply PN

?

D3A

A A

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

SKYLAKE 1/15 eDP/DDI/MISC

SKYLAKE 1/15 eDP/DDI/MISC

SKYLAKE 1/15 eDP/DDI/MISC

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

PROJECT :

LV6

LV6

LV6

1A

1A

2 61Friday, March 11, 2016

2 61Friday, March 11, 2016

1

2 61Friday, March 11, 2016

1A

5

4

3

2

1

SkyLake ULT Processor (DDR4)

Interleave

D D

?

U38B

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14

M_A_DQ15
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7

C C

B B

M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15

M_A_DQ16

M_A_DQ17

M_A_DQ18

M_A_DQ19

M_A_DQ20

M_A_DQ21

M_A_DQ22

M_A_DQ23

M_A_DQ24

M_A_DQ25

M_A_DQ26

M_A_DQ27

M_A_DQ28

M_A_DQ29

M_A_DQ30

M_A_DQ31
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31

AL71

DDR0_DQ[0]

AL68

DDR0_DQ[1]

AN68

DDR0_DQ[2]

AN69

DDR0_DQ[3]

AL70

DDR0_DQ[4]

AL69

DDR0_DQ[5]

AN70

DDR0_DQ[6]

AN71

DDR0_DQ[7]

AR70

DDR0_DQ[8]

AR68

DDR0_DQ[9]

AU71

DDR0_DQ[10]

AU68

DDR0_DQ[11]

AR71

DDR0_DQ[12]

AR69

DDR0_DQ[13]

AU70

DDR0_DQ[14]

AU69

DDR0_DQ[15]

AF65

DDR1_DQ[0]/DDR0_DQ[16]

AF64

DDR1_DQ[1]/DDR0_DQ[17]

AK65

DDR1_DQ[2]/DDR0_DQ[18]

AK64

DDR1_DQ[3]/DDR0_DQ[19]

AF66

DDR1_DQ[4]/DDR0_DQ[20]

AF67

DDR1_DQ[5]/DDR0_DQ[21]

AK67

DDR1_DQ[6]/DDR0_DQ[22]

AK66

DDR1_DQ[7]/DDR0_DQ[23]

AF70

DDR1_DQ[8]/DDR0_DQ[24]

AF68

DDR1_DQ[9]/DDR0_DQ[25]

AH71

DDR1_DQ[10]/DDR0_DQ[26]

AH68

DDR1_DQ[11]/DDR0_DQ[27]

AF71

DDR1_DQ[12]/DDR0_DQ[28]

AF69

DDR1_DQ[13]/DDR0_DQ[29]

AH70

DDR1_DQ[14]/DDR0_DQ[30]

AH69

DDR1_DQ[15]/DDR0_DQ[31]

BB65

DDR0_DQ[16]/DDR0_DQ[32]

AW65

DDR0_DQ[17]/DDR0_DQ[33]

AW63

DDR0_DQ[18]/DDR0_DQ[34]

AY63

DDR0_DQ[19]/DDR0_DQ[35]

BA65

DDR0_DQ[20]/DDR0_DQ[36]

AY65

DDR0_DQ[21]/DDR0_DQ[37]

BA63

DDR0_DQ[22]/DDR0_DQ[38]

BB63

DDR0_DQ[23]/DDR0_DQ[39]

BA61

DDR0_DQ[24]/DDR0_DQ[40]

AW61

DDR0_DQ[25]/DDR0_DQ[41]

BB59

DDR0_DQ[26]/DDR0_DQ[42]

AW59

DDR0_DQ[27]/DDR0_DQ[43]

BB61

DDR0_DQ[28]/DDR0_DQ[44]

AY61

DDR0_DQ[29]/DDR0_DQ[45]

BA59

DDR0_DQ[30]/DDR0_DQ[46]

AY59

DDR0_DQ[31]/DDR0_DQ[47]

AT66

DDR1_DQ[16]/DDR0_DQ[48]

AU66

DDR1_DQ[17]/DDR0_DQ[49]

AP65

DDR1_DQ[18]/DDR0_DQ[50]

AN65

DDR1_DQ[19]/DDR0_DQ[51]

AN66

DDR1_DQ[20]/DDR0_DQ[52]

AP66

DDR1_DQ[21]/DDR0_DQ[53]

AT65

DDR1_DQ[22]/DDR0_DQ[54]

AU65

DDR1_DQ[23]/DDR0_DQ[55]

AT61

DDR1_DQ[24]/DDR0_DQ[56]

AU61

DDR1_DQ[25]/DDR0_DQ[57]

AP60

DDR1_DQ[26]/DDR0_DQ[58]

AN60

DDR1_DQ[27]/DDR0_DQ[59]

AN61

DDR1_DQ[28]/DDR0_DQ[60]

AP61

DDR1_DQ[29]/DDR0_DQ[61]

AT60

DDR1_DQ[30]/DDR0_DQ[62]

AU60

DDR1_DQ[31]/DDR0_DQ[63]

SKL_ULT

REV = 1

SKL_ULT

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]

DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#
DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]

DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]

DDR1_DQSN[0]/DDR0_DQSN[2]

DDR1_DQSP[0]/DDR0_DQSP[2]

DDR1_DQSN[1]/DDR0_DQSN[3]

DDR1_DQSP[1]/DDR0_DQSP[3]

DDR0_DQSN[2]/DDR0_DQSN[4]

DDR0_DQSP[2]/DDR0_DQSP[4]

DDR0_DQSN[3]/DDR0_DQSN[5]

DDR0_DQSP[3]/DDR0_DQSP[5]

DDR1_DQSN[2]/DDR0_DQSN[6]

DDR1_DQSP[2]/DDR0_DQSP[6]

DDR1_DQSN[3]/DDR0_DQSN[7]

DDR1_DQSP[3]/DDR0_DQSP[7]

NIL-DDR CH ­A

2 OF 20

DDR0_CKN[0]
DDR0_CKP[0]
DDR0_CKN[1]
DDR0_CKP[1]

DDR0_CKE[0]
DDR0_CKE[1]
DDR0_CKE[2]
DDR0_CKE[3]

DDR0_CS#[0]
DDR0_CS#[1]
DDR0_ODT[0]
DDR0_ODT[1]

DDR0_MA[3]
DDR0_MA[4]

DDR0_DQSN[0]
DDR0_DQSP[0]
DDR0_DQSN[1]
DDR0_DQSP[1]

DDR0_ALERT#

DDR0_PAR

DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ

DDR_VTT_CNTL

AU53
AT53
AU55
AT55

BA56
BB56
AW56
AY56

AU45
AU43
AT45
AT43

BA51
BB54
BA52
AY52
AW52
AY55
AW54
BA54
BA55
AY54

AU46
AU48
AT46
AU50
AU52
AY51
AT48
AT50
BB50
AY50
BA50
BB52

M_A_DQSN0

AM70

M_A_DQSP0

AM69

M_A_DQSN1

AT69

M_A_DQSP1

AT70

M_B_DQSN0

AH66

M_B_DQSP0

AH65

M_B_DQSN1

AG69

M_B_DQSP1

AG70

M_A_DQSN2

BA64

M_A_DQSP2

AY64

M_A_DQSN3

AY60

M_A_DQSP3

BA60

M_B_DQSN2

AR66

M_B_DQSP2

AR65

M_B_DQSN3

AR61

M_B_DQSP3

AR60

M_A_ALERT#

AW50

M_A_PARITY M_B_ALERT#

AT52
AY67

AY68
BA67

AW67

?

M_A_CLKN0 {16}

M_A_CLKP0 {16}

TP21
TP16

M_A_CKE0 {16}

TP20

M_A_CS#0 {16}

TP18

M_A_ODT0_CPU {16}

TP12

M_A_A5 {16}

M_A_A9 {16}

M_A_A6 {16}

M_A_A8 {16}

M_A_A7 {16}

M_A_BG#0 {16}

M_A_A12 {16}

M_A_A11 {16}

M_A_ACT# {16}

TP52

M_A_A13 {16}

M_A_CAS# {16}

M_A_WE# {16}

M_A_RAS# {16}

M_A_BA#0 {16}

M_A_A2 {16}

M_A_BA#1 {16}

M_A_A10 {16}

M_A_A1 {16}

M_A_A0 {16}

M_A_A3 {16}

M_A_A4 {16}

M_A_ALERT# {16}

M_A_PARITY {16}

SM_VREF_CA {16}

TP55

SM_VREF_DQ1 {17}

DDR_PG_CTRL {17}

M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46

M_A_DQ47
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47

M_A_DQ48

M_A_DQ49

M_A_DQ50

M_A_DQ51

M_A_DQ52

M_A_DQ53

M_A_DQ54

M_A_DQ55

M_A_DQ56

M_A_DQ57

M_A_DQ58

M_A_DQ59

M_A_DQ60

M_A_DQ61

M_A_DQ62

M_A_DQ63
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51 M_B_DQSN6
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

U38C

AY39

DDR0_DQ[32]/DDR1_DQ[0]

AW39

DDR0_DQ[33]/DDR1_DQ[1]

AY37

DDR0_DQ[34]/DDR1_DQ[2]

AW37

DDR0_DQ[35]/DDR1_DQ[3]

BB39

DDR0_DQ[36]/DDR1_DQ[4]

BA39

DDR0_DQ[37]/DDR1_DQ[5]

BA37

DDR0_DQ[38]/DDR1_DQ[6]

BB37

DDR0_DQ[39]/DDR1_DQ[7]

AY35

DDR0_DQ[40]/DDR1_DQ[8]

AW35

DDR0_DQ[41]/DDR1_DQ[9]

AY33

DDR0_DQ[42]/DDR1_DQ[10]

AW33

DDR0_DQ[43]/DDR1_DQ[11]

BB35

DDR0_DQ[44]/DDR1_DQ[12]

BA35

DDR0_DQ[45]/DDR1_DQ[13]

BA33

DDR0_DQ[46]/DDR1_DQ[14]

BB33

DDR0_DQ[47]/DDR1_DQ[15]

AU40

DDR1_DQ[32]/DDR1_DQ[16]

AT40

DDR1_DQ[33]/DDR1_DQ[17]

AT37

DDR1_DQ[34]/DDR1_DQ[18]

AU37

DDR1_DQ[35]/DDR1_DQ[19]

AR40

DDR1_DQ[36]/DDR1_DQ[20]

AP40

DDR1_DQ[37]/DDR1_DQ[21]

AP37

DDR1_DQ[38]/DDR1_DQ[22]

AR37

DDR1_DQ[39]/DDR1_DQ[23]

AT33

DDR1_DQ[40]/DDR1_DQ[24]

AU33

DDR1_DQ[41]/DDR1_DQ[25]

AU30

DDR1_DQ[42]/DDR1_DQ[26]

AT30

DDR1_DQ[43]/DDR1_DQ[27]

AR33

DDR1_DQ[44]/DDR1_DQ[28]

AP33

DDR1_DQ[45]/DDR1_DQ[29]

AR30

DDR1_DQ[46]/DDR1_DQ[30]

AP30

DDR1_DQ[47]/DDR1_DQ[31]

AY31

DDR0_DQ[48]/DDR1_DQ[32]

AW31

DDR0_DQ[49]/DDR1_DQ[33]

AY29

DDR0_DQ[50]/DDR1_DQ[34]

AW29

DDR0_DQ[51]/DDR1_DQ[35]

BB31

DDR0_DQ[52]/DDR1_DQ[36]

BA31

DDR0_DQ[53]/DDR1_DQ[37]

BA29

DDR0_DQ[54]/DDR1_DQ[38]

BB29

DDR0_DQ[55]/DDR1_DQ[39]

AY27

DDR0_DQ[56]/DDR1_DQ[40]

AW27

DDR0_DQ[57]/DDR1_DQ[41]

AY25

DDR0_DQ[58]/DDR1_DQ[42]

AW25

DDR0_DQ[59]/DDR1_DQ[43]

BB27

DDR0_DQ[60]/DDR1_DQ[44]

BA27

DDR0_DQ[61]/DDR1_DQ[45]

BA25

DDR0_DQ[62]/DDR1_DQ[46]

BB25

DDR0_DQ[63]/DDR1_DQ[47]

AU27

DDR1_DQ[48]

AT27

DDR1_DQ[49]

AT25

DDR1_DQ[50]

AU25

DDR1_DQ[51]

AP27

DDR1_DQ[52]

AN27

DDR1_DQ[53]

AN25

DDR1_DQ[54]

AP25

DDR1_DQ[55]

AT22

DDR1_DQ[56]

AU22

DDR1_DQ[57]

AU21

DDR1_DQ[58]

AT21

DDR1_DQ[59]

AN22

DDR1_DQ[60]

AP22

DDR1_DQ[61]

AP21

DDR1_DQ[62]

AN21

DDR1_DQ[63]

SKL_ULT

REV = 1

?

SKL_ULT

Need apply PN

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]

DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#
DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]

DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]

DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]

DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]

DDR0_DQSN[4]/DDR1_DQSN[0]
DDR0_DQSP[4]/DDR1_DQSP[0]
DDR0_DQSN[5]/DDR1_DQSN[1]
DDR0_DQSP[5]/DDR1_DQSP[1]
DDR1_DQSN[4]/DDR1_DQSN[2]
DDR1_DQSP[4]/DDR1_DQSP[2]
DDR1_DQSN[5]/DDR1_DQSN[3]
DDR1_DQSP[5]/DDR1_DQSP[3]
DDR0_DQSN[6]/DDR1_DQSN[4]
DDR0_DQSP[6]/DDR1_DQSP[4]
DDR0_DQSN[7]/DDR1_DQSN[5]
DDR0_DQSP[7]/DDR1_DQSP[5]

NIL-DDR CH ­B

3 OF 20

PDC

DDR1_CKN[0]
DDR1_CKN[1]
DDR1_CKP[0]
DDR1_CKP[1]

DDR1_CKE[0]
DDR1_CKE[1]
DDR1_CKE[2]
DDR1_CKE[3]

DDR1_CS#[0]
DDR1_CS#[1]
DDR1_ODT[0]
DDR1_ODT[1]

DDR1_MA[3]
DDR1_MA[4]

DDR1_DQSN[6]
DDR1_DQSP[6]
DDR1_DQSN[7]
DDR1_DQSP[7]

DDR1_ALERT#

DDR1_PAR
DRAM_RESET#
DDR_RCOMP[0]
DDR_RCOMP[1]
DDR_RCOMP[2]

M_A_DQSN[7:0]{16}

M_A_DQSP[7:0]{16}

M_A_DQ[63:0]{16}

AN45
AN46
AP45
AP46

AN56
AP55
AN55
AP53

BB42
AY42
BA42
AW42

AY48
AP50
BA48
BB48
AP48
AP52
AN50
AN48
AN53
AN52

BA43
AY43
AY44
AW44
BB44
AY47
BA44
AW46
AY46
BA46
BB46
BA47

M_A_DQSN4

BA38

M_A_DQSP4

AY38

M_A_DQSN5

AY34

M_A_DQSP5

BA34

M_B_DQSN4

AT38

M_B_DQSP4

AR38

M_B_DQSN5

AT32

M_B_DQSP5

AR32

M_A_DQSN6

BA30

M_A_DQSP6

AY30

M_A_DQSN7

AY26

M_A_DQSP7

BA26
AR25

M_B_DQSP6

AR27

M_B_DQSN7

AR22

M_B_DQSP7

AR21
AN43

M_B_PARITY

AP43

SM_DRAMRST#

AT13

SM_RCOMP_0

AR18

SM_RCOMP_1

AT18

SM_RCOMP_2

AU18

?

M_B_DQSN[7:0]{17}

M_B_DQSP[7:0]{17}

M_B_DQ[63:0]{17}

+1.2V_SUS{6,16,17,50}

M_B_CLKN0 {17}
M_B_CLKN1 {17}
M_B_CLKP0 {17}
M_B_CLKP1 {17}

M_B_CKE0 {17}
M_B_CKE1 {17}

M_B_CS#0 {17}
M_B_CS#1 {17}
M_B_ODT0_CPU {17}
M_B_ODT1_CPU {17}

M_B_A5 {17}
M_B_A9 {17}
M_B_A6 {17}
M_B_A8 {17}
M_B_A7 {17}
M_B_BG#0 {17}
M_B_A12 {17}
M_B_A11 {17}
M_B_ACT# {17}
M_B_BG#1 {17}

M_B_A13 {17}
M_B_CAS# {17}
M_B_WE# {17}
M_B_RAS# {17}
M_B_BA#0 {17}
M_B_A2 {17}
M_B_BA#1 {17}
M_B_A10 {17}
M_B_A1 {17}
M_B_A0 {17}
M_B_A3 {17}
M_B_A4 {17}

M_B_ALERT# {17}
M_B_PARITY {17}

R274 121/F_4
R276 80.6/F_4
R275 100/F_4

+1.2V_SUS

R358
470/F_4

03

DDR4_DRAMRST# {16,17}

A A

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

PROJECT :

SKYLAKE 2/15(DDR4 I/F)

SKYLAKE 2/15(DDR4 I/F)

SKYLAKE 2/15(DDR4 I/F)

LV6

LV6

LV6

3 61Friday, March 11, 2016

3 61Friday, March 11, 2016

1

3 61Friday, March 11, 2016

1A

1A

1A

5

D D

PLTRST#
SYS_RESET#

RSMRST#{36}

EC_PWROK{29,36,37}

PCIE_WAKE#{19,30,33}

RSMRST#

C C

SYS_RESET#
PLTRST#

EC13
*E@220P/50V_4

R595 10K_4

C276 *0.1U/16V/X7R_4

R295*0_4_S

TP50 R692 10K_4

B2A

TP15

EC9
*E@220P/50V_4

EC38
*E@220P/50V_4

RSMRST#

PROCPWRGD

H_VCCST_PWRGD
SYS_PWROK

EC_PWROK
DSWROK_EC_R

SUSWARN#
SUSACK#

PCIE_WAKE#
GPD2

4

?

U38K

AN10

GPP_B13/PLTRST#

B5

SYS_RESET#

AY17

RSMRST#

A68

PROCPWRGD

B65

VCCST_PWRGD

B6

SYS_PWROK

BA20

PCH_PWROK

BB20

DSW_PWROK

AR13

GPP_A13/SUSWARN#/SUSPWRDNACK

AP11

GPP_A15/SUSACK#

BB15

WAKE#

AM15

GPD2/LAN_WAKE#

AW17

GPD11/LANPHYPC

AT15

GPD7/RSVD

SKL_ULT

REV = 1

SKL_ULT

SYSTEM POWER MANAGEMENT

11 OF 20

3

GPP_B12/SLP_S0#

GPD4/SLP_S3#
GPD5/SLP_S4#

GPD10/SLP_S5#

SLP_SUS#
SLP_LAN#

GPD9/SLP_WLAN#

GPD6/SLP_A#

GPD3/PWRBTN#

GPD1/ACPRESENT

GPD0/BATLOW#

GPP_A11/PME#

INTRUDER#

GPP_B11/EXT_PWR_GATE#

GPP_B2/VRALERT#

2

+3V_DEEP_SUS{10,11,14,15,17}

+VCCSTPLL{2,5,6,9,45,53,56}

+3V_RTC_2{13,15}

AT11
AP15
BA16
AY16

AN15
AW15
BB17
AN16

BA15
AY15
AU13

AU11
AP16

AM10
AM11

PCH_SLP_S0#

SLP_S5#

SLP_LAN#

DNBSWON#
AC_PRESENT_EC
PM_BATLOW_N_EC

INTRUDER#_R

EXT_PWR_GATE#
PCH_VRALERT#

R287 1M_4

PCH_SLP_S0# {36}
SUSB# {18,36}
SUSC# {36}

TP53

TP51

SLP_WLAN# {33}

TP13

DNBSWON# {36}
AC_PRESENT_EC {36}
PM_BATLOW_N_EC {36}

+3V_RTC_2

C3A

B2A

?

PCH Pull-high/low(CLG)

SUSWARN#
SUSACK#
PM_BATLOW_N_EC
GPD2

B2A

PCIE_WAKE#
AC_PRESENT_EC
DNBSWON#

SYS_RESET#
PCH_VRALERT#

B2A

RSMRST#
DSWROK_EC_R

EXT_PWR_GATE#

R297 10K_4
R293 *10K_4
R302 10K_4
R763 10K_4

R687 10K_4

R780 *10K_4

R196 10K_4
R764 10K_4

R688 10K_4
R288 100K_4

R251 1K_4

+3VS5{10,12,15,26,28,30,32,33,35,36,41,42,44,49,51,53,54,56}

+3V{2,10,11,12,13,14,15,17,18,25,26,27,29,30,31,34,36,37,38,40,41,42,45,49,52,53,54}

+5VS5{34,35,38,39,41,42,44,45,48,50,51,53,54,56}

+VCCIO{2,6,53,56}

+3V_DEEP_SUS

+3VS5

+3V

1

04

C3A

+3VS5

RSMRST#

B B

R285 *0_4_S

PLTRST#{18,28,30,31,33,36,37}

PLTRST#(CLG)

SYS_PWROK{36}

R189
100K_4

A A

System PWR_OK(CLG)

5

DSWROK_EC_R

PLTRST#

R190 *0_4

+VCCIO +3VS5+5VS5

+VCCIO

+VCCSTPLL

R591
1K_4

R437
100K_4

HWPG{36,49,50}

EC_PWROKSYS_PWROK

R192
100K_4

4

HWPG

21

D17 DB2J40600L

H_VCCST_PWRGD_R

C688
*10P/50V_4

3

R582
*1K_4

R597 60.4_4

H_VCCST_PWRGD

R569
15K_4

+1.0V_PWRGD_G1

C665

0.1U/16V/X7R_4

2

R565
100K_4

R559
100K_4

+1.0V_PWRGD_G2

2

Q38
METR3904-G

1 3

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

R558
10K_4

3

2

1

SKYLAKE 3/15(PowerManger)

SKYLAKE 3/15(PowerManger)

SKYLAKE 3/15(PowerManger)

HWPG

Q39
2N7002K

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

R557
100K_4

1

LV6

LV6

LV6

1A

1A

4 61Friday, March 11, 2016

4 61Friday, March 11, 2016

4 61Friday, March 11, 2016

1A

5

Under CPU

C274

C256

C366
10U/6.3V_4

C333
22U/6.3V/X5R_6

C245
GT3@10U/6.3V_4

C661

C670

C329

22U/6.3V/X5R_6

C353
10U/6.3V_4

C158
22U/6.3V/X5R_6

Close CPU

C660

47U/6.3V_8

C666

10U/6.3V_4

22U/6.3V/X5R_6

47U/6.3V_8

10U/6.3V_4

10U/6.3V_4

10U/6.3V_4

C337
22U/6.3V/X5R_6

C673

47U/6.3V_8

C181

10U/6.3V_4

22U/6.3V/X5R_6

47U/6.3V_8

10U/6.3V_4

D D

+1.8V_DEEP_SUS +1.8V_PRIM

R163 GT3@0_6

C C

B B

C255
GT3@10U/6.3V_4

+VCC_CORE

+VCC_CORE

C317

C365
10U/6.3V_4

C150
22U/6.3V/X5R_6

+VCCOPC

+VCCOPC_SRC{49}

681_AGND{49}

C667

C169

C296

22U/6.3V/X5R_6

C367
10U/6.3V_4

C154
22U/6.3V/X5R_6

C657

47U/6.3V_8

C675

10U/6.3V_4

4

C292

22U/6.3V/X5R_6

C188
10U/6.3V_4

C319
22U/6.3V/X5R_6

+VCCOPC_SRC
681_AGND

+VCCOPC_SRC
681_AGND

C663

47U/6.3V_8

C656

10U/6.3V_4

C325

22U/6.3V/X5R_6

C207
10U/6.3V_4

R244 GT3@100/F_4
R246 GT3@0_4
R239 GT3@0_4
R237 GT3@100/F_4

R247 GT3@0_4
R248 GT3@0_4

C678

47U/6.3V_8

C671

10U/6.3V_4

+VCCOPC

+1.8V_PRIM

+VCCEOPIO

C684

47U/6.3V_8

C677
10U/6.3V_4

C270

22U/6.3V/X5R_6

3

?

SKL_ULT

AK33
AK35
AK37
AK38
AK40
AL33
AL37

AL40
AM32
AM33
AM35
AM37
AM38

AK32

AB62

AC63

AE63

AE62
AG62

AL63

AJ62

A30
A34
A39
A44

G30
K32

P62
V62

H63
G61

U38L

CPU POWER 1 OF 4

VCC_A30
VCC_A34

33A

VCC_A39
VCC_A44
VCC_AK33
VCC_AK35
VCC_AK37
VCC_AK38
VCC_AK40
VCC_AL33
VCC_AL37
VCC_AL40
VCC_AM32
VCC_AM33
VCC_AM35
VCC_AM37
VCC_AM38
VCC_G30

RSVD_K32
RSVD_AK32
VCCOPC_AB62

VCCOPC_P62
VCCOPC_V62

VCC_OPC_1P8_H63
VCC_OPC_1P8_G61
VCCOPC_SENSE

VSSOPC_SENSE
VCCEOPIO

VCCEOPIO
VCCEOPIO_SENSE

VSSEOPIO_SENSE

SKL_ULT

REV = 1

+VCCEOPIO

+VCCOPC

VCC_SENSE
VSS_SENSE

VIDALERT#

VCCSTG_G20

12 OF 20

C340 GT3@22U/6.3V/X5R_6

C322 GT3@1U/6.3V_4X
C323 GT3@1U/6.3V_4X
C324 GT3@22U/6.3V/X5R_6

VCC_G32
VCC_G33
VCC_G35
VCC_G37
VCC_G38
VCC_G40
VCC_G42

VCC_J30
VCC_J33
VCC_J37

VCC_J40
VCC_K33
VCC_K35
VCC_K37
VCC_K38
VCC_K40
VCC_K42
VCC_K43

VIDSCK

VIDSOUT

PDC

G32
G33
G35
G37
G38
G40
G42
J30
J33
J37
J40
K33
K35
K37
K38
K40
K42
K43

E32
E33

B63
A63
D64

G20

?

+VCC_CORE +VCC_CORE

C705
1U/6.3V_4X

C253
1U/6.3V_4X

H_CPU_SVIDALRT#
VR_SVID_CLK_R
H_CPU_SVIDDAT

H_CPU_SVIDALRT#

VR_SVID_CLK_R

C235
1U/6.3V_4X

C195
1U/6.3V_4X

C194
1U/6.3V_4X

C208
1U/6.3V_4XC246

2

C344

C229

1U/6.3V_4X

1U/6.3V_4X

C383

C222

1U/6.3V_4X

1U/6.3V_4X

R187 100/F_4

R188 100/F_4

R599 220/F_4

R600 *0_4_S

C368
1U/6.3V_4X

C362
1U/6.3V_4X

+VCCSTPLL

+VCCSTPLL

R587
*54.9/F_4

+VCCSTPLL

R579

56.2/F_4

C689
*0.1U/16V/X7R_4

Under CPU

C219
1U/6.3V_4X

C261
1U/6.3V_4X

C819
1U/6.3V_4X

+VCC_CORE{46}

+VCCSTG{6}

+VCCSTPLL{2,4,6,9,45,53,56}

+VCCOPC{49}

C241
1U/6.3V_4X

+VCC_CORE

VCC_SENSE {45}
VSS_SENSE {45}

+VCCSTG

B2A

SVID ALERT

VR_SVID_ALERT# {45}

SVID CLK

VR_SVID_CLK {45}

1

+VCCSTPLL

05

100- ±1%
pull-up to VCC
near processor.

C682

0.1U/16V/X7R_4

R577
100/F_4

H_CPU_SVIDDAT

A A

5

4

3

2

R578 *0_4_S

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

SVID DATA

VR_SVID_DATA {45}

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

SKYLAKE 4/15 (POWER-1)

SKYLAKE 4/15 (POWER-1)

SKYLAKE 4/15 (POWER-1)

1

LV6

LV6

LV6

1A

1A

5 61Friday, March 11, 2016

5 61Friday, March 11, 2016

5 61Friday, March 11, 2016

1A

5

D D

Under CPU

C409

C413

10U/6.3V_4

10U/6.3V_4

Close CPU

C431

C424

10U/6.3V_4

10U/6.3V_4

C C

+VCCIO

C420

10U/6.3V_4

R158 *0_4_S

R280 *0_6_S

R149 *0_6_S

C417

10U/6.3V_4

+VCCSTG

+VCCPLL_OC+1.2V_SUS

+VCCPLL+VCCSTPLL

+1.2V_SUS

C406
1U/6.3V_4X

+1.2V_SUS

*1U/6.3V_4X

C433
1U/6.3V_4X

C412
1U/6.3V_4X

Close CPU Under CPU

C387

10U/6.3V_4

4

C416
1U/6.3V_4X

+VCCSTPLL

+VCCSTG

+VCCPLL_OC

+VCCPLL

AU23
AU28
AU35
AU42
BB23
BB32
BB41
BB47
BB51

AM40

AL23

A18
A22

K20
K21

SKL_ULT

U38N

CPU POWER 3 OF 4

VDDQ_AU23
VDDQ_AU28
VDDQ_AU35
VDDQ_AU42
VDDQ_BB23
VDDQ_BB32
VDDQ_BB41
VDDQ_BB47
VDDQ_BB51

VDDQC

0.12A

VCCST
VCCSTG_A22
VCCPLL_OC
VCCPLL_K20

VCCPLL_K21

SKL_ULT

REV = 1

2A

0.04A

0.12A

14 OF 20

?

VCCIO

3.1A

VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO

VCCSA

4.5A

VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA

VCCIO_SENSE
VSSIO_SENSE

VSSSA_SENSE
VCCSA_SENSE

3

+VCCSA

Under CPU

C371
1U/6.3V_4X

C299
1U/6.3V_4X

C312
10U/6.3V_4

C348
1U/6.3V_4X

C668
1U/6.3V_4X

C239
10U/6.3V_4

C350
1U/6.3V_4X

C343
1U/6.3V_4X

C330
10U/6.3V_4

VSSSA_SENSE {45}
VCCSA_SENSE {45}
+VCCSA

C351
10U/6.3V_4

C662
1U/6.3V_4X

C352
10U/6.3V_4

AK28
AK30
AL30
AL42

C349

AM28

1U/6.3V_4X

AM30
AM42

AK23
AK25
G23
G25
G27

C237

G28

1U/6.3V_4X

J22
J23
J27
K23
K25
K27
K28
K30

AM23
AM22

R153 100/F_4

H21
H20

R154 100/F_4

?

C369
10U/6.3V_4

C658
1U/6.3V_4XC407

C659
10U/6.3V_4

2

C382
1U/6.3V_4X

C332
1U/6.3V_4X

C275
10U/6.3V_4

Close CPU

C347
1U/6.3V_4X

Under CPU

C290
10U/6.3V_4

Close CPU

C370
1U/6.3V_4X

C318
10U/6.3V_4

+VCCIO

C346
1U/6.3V_4X

C321
10U/6.3V_4

+VCCIO{2,4,53,56}
+VCCSA{48}

+1.2V_SUS{3,16,17,50}

+VCCSTPLL{2,4,5,9,45,53,56}

+VCCSTG{5}

C238
10U/6.3V_4

C262
10U/6.3V_4

1

C669
10U/6.3V_4

C297
10U/6.3V_4

06

Close CPUUnder CPU

+VCCSTG +VCCPLL_OC +VCCPLL+VCCSTPLL

B B

C203
1U/6.3V_4X

C379
1U/6.3V_4X

C187
1U/6.3V_4X

C293
1U/6.3V_4X

Close A18 Ball

+VCCSTPLL

C186
*1U/6.3V_4X

A A

5

C182
*22U/6.3V/X5R_6

+1.2V_SUS

C432
10U/6.3V/X5R_6X

C428
10U/6.3V/X5R_6X

4

C425
10U/6.3V/X5R_6X

C427
10U/6.3V/X5R_6X

C429
10U/6.3V/X5R_6X

Close to CPU

C430
10U/6.3V/X5R_6X

C386
1U/6.3V_4X

C421
1U/6.3V_4X

3

C408
1U/6.3V_4X

C414
1U/6.3V_4X

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

SKYLAKE 5/15 (POWER-2)

SKYLAKE 5/15 (POWER-2)

SKYLAKE 5/15 (POWER-2)

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

PROJECT :

LV6

LV6

LV6

1A

1A

6 61Friday, March 11, 2016

6 61Friday, March 11, 2016

1

6 61Friday, March 11, 2016

1A

5

4

3

2

1

+VCCGT {47}

?

SKL_ULT

AA63
AA64
AA66
AA67
AA69
AA70
AA71
AC64
AC65
AC66
AC67
AC68
AC69
AC70
AC71

M62
N63
N64
N66
N67
N69

A48
A53
A58
A62
A66

J43
J45
J46
J48
J50
J52
J53
J55
J56
J58
J60
K48
K50
K52
K53
K55
K56
K58
K60
L62
L63
L64
L65
L66
L67
L68
L69
L70
L71

J70
J69

U38M

CPU POWER 2 OF 4

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

VCCGT_SENSE
VSSGT_SENSE

SKL_ULT

REV = 1

31A

PDC

13 OF 20

VCCGTX_AK42
VCCGTX_AK43
VCCGTX_AK45
VCCGTX_AK46
VCCGTX_AK48
VCCGTX_AK50
VCCGTX_AK52
VCCGTX_AK53
VCCGTX_AK55
VCCGTX_AK56
VCCGTX_AK58
VCCGTX_AK60
VCCGTX_AK70
VCCGTX_AL43
VCCGTX_AL46
VCCGTX_AL50
VCCGTX_AL53
VCCGTX_AL56

VCCGTX_AL60
VCCGTX_AM48
VCCGTX_AM50
VCCGTX_AM52
VCCGTX_AM53
VCCGTX_AM56
VCCGTX_AM58
VCCGTX_AU58
VCCGTX_AU63

VCCGTX_BB57

VCCGTX_BB66

VCCGTX_SENSE
VSSGTX_SENSE

+VCCGT

C729
10U/6.3V_4

C750
10U/6.3V_4

C724
1U/6.3V_4X

C304
1U/6.3V_4X

+VCCGT

C726
10U/6.3V_4

C307
10U/6.3V_4

C752
1U/6.3V_4X

C302
1U/6.3V_4X

C306

C373
1U/6.3V_4X

C374
1U/6.3V_4X

C309
10U/6.3V_4

C372
10U/6.3V_4

C301
1U/6.3V_4X

C378
1U/6.3V_4X

VCCGT_SENSE{45}
VSSGT_SENSE{45}

10U/6.3V_4

C376
10U/6.3V_4

C375
1U/6.3V_4X

C308
1U/6.3V_4X

D D

C C

B B

C377
10U/6.3V_4

C731
10U/6.3V_4

C303
1U/6.3V_4X

C305
1U/6.3V_4X

R634 100/F_4

R642 100/F_4

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

+VCCGT

Close CPUUnder CPU

N70
N71
R63
R64
R65
R66
R67
R68
R69
R70
R71
T62
U65
U68
U71
W63
W64
W65
W66
W67
W68
W69
W70
W71
Y62

AK42
AK43
AK45
AK46
AK48
AK50
AK52
AK53
AK55
AK56
AK58
AK60
AK70
AL43
AL46
AL50
AL53
AL56
AL60
AM48
AM50
AM52
AM53
AM56
AM58
AU58
AU63
BB57
BB66

AK62
AL61

?

C758
47U/6.3V_8

C171
22U/6.3V/X5R_6

C338
22U/6.3V/X5R_6

+VCCGT

C743
GT3@22U/6.3V/X5R_6

C744
GT3@22U/6.3V/X5R_6

C277
GT3@10U/6.3V_4

C240
GT3@10U/6.3V_4

C759
47U/6.3V_8

C185
22U/6.3V/X5R_6

C342
22U/6.3V/X5R_6

C180
GT3@22U/6.3V/X5R_6

C209
GT3@22U/6.3V/X5R_6

C278
GT3@10U/6.3V_4

C674
GT3@10U/6.3V_4

C760
47U/6.3V_8

C298
22U/6.3V/X5R_6

C751
22U/6.3V/X5R_6

C761
47U/6.3V_8

C331

C316

22U/6.3V/X5R_6

22U/6.3V/X5R_6

C749
22U/6.3V/X5R_6

C193
GT3@22U/6.3V/X5R_6

C721
GT3@22U/6.3V/X5R_6

C676
GT3@10U/6.3V_4

C260
GT3@10U/6.3V_4

C722
47U/6.3V_8

C345
22U/6.3V/X5R_6

C748
GT3@22U/6.3V/X5R_6

C179
GT3@22U/6.3V/X5R_6

C273
GT3@10U/6.3V_4

C252
GT3@10U/6.3V_4

C762
47U/6.3V_8

C341
22U/6.3V/X5R_6

C227
22U/6.3V/X5R_6

07

A A

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

SKYLAKE 6/15 (POWER-3)

SKYLAKE 6/15 (POWER-3)

SKYLAKE 6/15 (POWER-3)

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

PROJECT :

LV6

LV6

LV6

1A

1A

7 61Friday, March 11, 2016

7 61Friday, March 11, 2016

1

7 61Friday, March 11, 2016

1A

5

4

3

2

1

08

D D

U38R

?

SKL_ULT

GND 3 OF 3

F8

VSS

G10

VSS

G22

VSS

G43

VSS

G45

VSS

G48

VSS

G5

VSS

G52

VSS

C C

B B

G55

VSS

G58

VSS

G6

VSS

G60

VSS

G63

VSS

G66

VSS

H15

VSS

H18

VSS

H71

VSS

J11

VSS

J13

VSS

J25

VSS

J28

VSS

J32

VSS

J35

VSS

J38

VSS

J42

VSS

J8

VSS

K16

VSS

K18

VSS

K22

VSS

K61

VSS

K63

VSS

K64

VSS

K65

VSS

K66

VSS

K67

VSS

K68

VSS

K70

VSS

K71

VSS

L11

VSS

L16

VSS

L17

VSS

18 OF 20

SKL_ULT

REV = 1

L18

VSS

L2

VSS

L20

VSS

L4

VSS

L8

VSS

N10

VSS

N13

VSS

N19

VSS

N21

VSS

N6

VSS

N65

VSS

N68

VSS

P17

VSS

P19

VSS

P20

VSS

P21

VSS

R13

VSS

R6

VSS

T15

VSS

T17

VSS

T18

VSS

T2

VSS

T21

VSS

T4

VSS

U10

VSS

U63

VSS

U64

VSS

U66

VSS

U67

VSS

U69

VSS

U70

VSS

V16

VSS

V17

VSS

V18

VSS

W13

VSS

W6

VSS

W9

VSS

Y17

VSS

Y19

VSS

Y20

VSS

Y21

VSS

?

AA65
AA68
AB15
AB16
AB18
AB21

AD13
AD16
AD19
AD20
AD21
AD62

AE64
AE65
AE66
AE67
AE68
AE69

AF10
AF15
AF17

AF63
AG16
AG17
AG18
AG19
AG20
AG21
AG71
AH13

AH63
AH64
AH67

AJ15

AJ18

AJ20
AK11

AK16
AK18
AK21
AK22
AK27
AK63
AK68
AK69

AL28

AL32

AL35

AL38

AL45

AL48

AL52

AL55

AL58

AL64

U38P

?

SKL_ULT

GND 1 OF 3

A5

VSS

A67

VSS

A70

VSS

AA2

VSS

AA4

VSS
VSS
VSS
VSS
VSS
VSS
VSS

AB8

VSS
VSS
VSS
VSS
VSS
VSS
VSS

AD8

VSS
VSS
VSS
VSS
VSS
VSS
VSS

AF1

VSS
VSS
VSS
VSS

AF2

VSS

AF4

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AH6

VSS
VSS
VSS
VSS
VSS
VSS
VSS

AJ4

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AK8

VSS

AL2

VSS
VSS
VSS
VSS
VSS

AL4

VSS
VSS
VSS
VSS
VSS
VSS
VSS

16 OF 20

SKL_ULT

REV = 1

AL65

VSS

AL66

VSS

AM13

VSS

AM21

VSS

AM25

VSS

AM27

VSS

AM43

VSS

AM45

VSS

AM46

VSS

AM55

VSS

AM60

VSS

AM61

VSS

AM68

VSS

AM71

VSS

AM8

VSS

AN20

VSS

AN23

VSS

AN28

VSS

AN30

VSS

AN32

VSS

AN33

VSS

AN35

VSS

AN37

VSS

AN38

VSS

AN40

VSS

AN42

VSS

AN58

VSS

AN63

VSS

AP10

VSS

AP18

VSS

AP20

VSS

AP23

VSS

AP28

VSS

AP32

VSS

AP35

VSS

AP38

VSS

AP42

VSS

AP58

VSS

AP63

VSS

AP68

VSS

AP70

VSS

AR11

VSS

AR15

VSS

AR16

VSS

AR20

VSS

AR23

VSS

AR28

VSS

AR35

VSS

AR42

VSS

AR43

VSS

AR45

VSS

AR46

VSS

AR48

VSS

AR5

VSS

AR50

VSS

AR52

VSS

AR53

VSS

AR55

VSS

AR58

VSS

AR63

VSS

AR8

VSS

AT2

VSS

AT20

VSS

AT23

VSS

AT28

VSS

AT35

VSS

AT4

VSS

AT42

VSS

AT56

VSS

AT58

VSS

?

AT63
AT68
AT71
AU10
AU15
AU20
AU32
AU38

AV68
AV69
AV70

AV71
AW10
AW12
AW14
AW16
AW18
AW21
AW23
AW26
AW28
AW30
AW32
AW34
AW36
AW38
AW41
AW43
AW45
AW47
AW49
AW51
AW53
AW55
AW57

AW6
AW60
AW62
AW64
AW66

AW8

AY66

BA10
BA14
BA18

BA23
BA28
BA32
BA36

BA45

U38Q

?

SKL_ULT

GND 2 OF 3

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AV1

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

B10

VSS

B14

VSS

B18

VSS

B22

VSS

B30

VSS

B34

VSS

B39

VSS

B44

VSS

B48

VSS

B53

VSS

B58

VSS

B62

VSS

B66

VSS

B71

VSS

BA1

VSS
VSS
VSS
VSS

BA2

VSS
VSS
VSS
VSS
VSS

F68

VSS
VSS

17 OF 20

SKL_ULT

REV = 1

PDC

BA49

VSS

BA53

VSS

BA57

VSS

BA6

VSS

BA62

VSS

BA66

VSS

BA71

VSS

BB18

VSS

BB26

VSS

BB30

VSS

BB34

VSS

BB38

VSS

BB43

VSS

BB55

VSS

BB6

VSS

BB60

VSS

BB64

VSS

BB67

VSS

BB70

VSS

C1

VSS

C25

VSS

C5

VSS

D10

VSS

D11

VSS

D14

VSS

D18

VSS

D22

VSS

D25

VSS

D26

VSS

D30

VSS

D34

VSS

D39

VSS

D44

VSS

D45

VSS

D47

VSS

D48

VSS

D53

VSS

D58

VSS

D6

VSS

D62

VSS

D66

VSS

D69

VSS

E11

VSS

E15

VSS

E18

VSS

E21

VSS

E46

VSS

E50

VSS

E53

VSS

E56

VSS

E6

VSS

E65

VSS

E71

VSS

F1

VSS

F13

VSS

F2

VSS

F22

VSS

F23

VSS

F27

VSS

F28

VSS

F32

VSS

F33

VSS

F35

VSS

F37

VSS

F38

VSS

F4

VSS

F40

VSS

F42

VSS

BA41

VSS

?

A A

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

SKYLAKE 7/15 (GND)

SKYLAKE 7/15 (GND)

SKYLAKE 7/15 (GND)

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

PROJECT :

LV6

LV6

LV6

1A

1A

8 61Friday, March 11, 2016

8 61Friday, March 11, 2016

1

8 61Friday, March 11, 2016

1A

5

D D

R174 49.9/F_4

+1.0V_DEEP_SUS

C C

B B

R195 1K_4

4

CFG3
CFG4

CFG_RCOMP

R173*0_4_S

AL25
AL27

BA70
BA68

E68
B67
D65
D67
E70
C68
D68
C67
F71
G69
F70
G68
H70
G71
H69
G70

E63
F63

E66
F66

E60

E8

AY2
AY1

D1
D3

K46
K45

C71
B70

F60
A52

J71
J68

F65

G65
F61

E61

U38S

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]

CFG[16]
CFG[17]

CFG[18]
CFG[19]

CFG_RCOMP
ITP_PMODE
RSVD_AY2

RSVD_AY1
RSVD_D1

RSVD_D3
RSVD_K46

RSVD_K45
RSVD_AL25

RSVD_AL27
RSVD_C71

RSVD_B70
RSVD_F60
RSVD_A52
RSVD_TP_BA70

RSVD_TP_BA68
RSVD_J71

RSVD_J68
VSS_F65

VSS_G65
RSVD_F61

RSVD_E61

SKL_ULT

REV = 1

SKL_ULT

RESERVED SIGNALS-1

PDC

?

19 OF 20

3

RSVD_TP_BB68
RSVD_TP_BB69

RSVD_TP_AK13
RSVD_TP_AK12

RSVD_BB2
RSVD_BA3

RSVD_D5
RSVD_D4
RSVD_B2
RSVD_C2

RSVD_B3
RSVD_A3

RSVD_AW1

RSVD_E1
RSVD_E2

RSVD_BA4
RSVD_BB4

RSVD_A4
RSVD_C4

RSVD_A69
RSVD_B69

RSVD_AY3
RSVD_D71

RSVD_C70
RSVD_C54

RSVD_D54

VSS_AY71

ZVM#

RSVD_TP_AW71
RSVD_TP_AW70

MSM#

PROC_SELECT#

2

+1.0V_DEEP_SUS{13,15,51,53,54,56}

+VCCSTPLL{2,4,5,6,45,53,56}

+1.8V_DEEP_SUS{5,15,42,53,56}

BB68
BB69

AK13
AK12

BB2
BA3

AU5

TP5

AT5

TP6

D5
D4
B2
C2

B3
A3

AW1
E1

E2
BA4

BB4
A4

C4
BB5

TP4

A69
B69

AY3
D71

C70
C54

D54
AY4

TP1

BB3

TP2

AY71

R700 *0_4_S

AR56

R238 *GT3@0_4

AW71
AW70

AP56
C64

?

R674 *0_4_S

Connon-U use, SKL-U
un-install.

+1.8V_DEEP_SUS

R211 *0_6

C314

Close to CPU

Placement are required for future platform
compatibility purpose only.

LPM_ZVM_N {49}

R598 *100K_4

+VCCSTPLL

*1U/6.3V_4X

AW69
AW68

AU56

AW48

U12
U11
H11

C7

U38T

RSVD_AW69
RSVD_AW68
RSVD_AU56
RSVD_AW48
RSVD_C7
RSVD_U12
RSVD_U11
RSVD_H11

SKL_ULT

REV = 1

SKL_ULT

SPARE

?

20 OF 20

RSVD_F6

RSVD_E3
RSVD_C11
RSVD_B11
RSVD_A11
RSVD_D12
RSVD_C12
RSVD_F52

1

09

F6
E3
C11
B11
A11
D12
C12
F52

?

Processor Strapping

CFG3
(Physcial Debug Enable)
DFX Privacy

CFG4
(DP Presence Strap)

A A

5

The CFG signals have a default value of '1' if not terminated on the board.

1 0

Disable: Enable: Set DFX Enable in DFX interface MSR

Disable; No physical DP attached to eDP

4

Enable; An ext DP device is connected to eDP

3

CFG3

CFG4

Circuit

R611 *1K_4

R617 1K_4

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

SKYLAKE 8/15 (RSV)

SKYLAKE 8/15 (RSV)

SKYLAKE 8/15 (RSV)

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

PROJECT :

LV6

LV6

LV6

1A

1A

9 61Friday, March 11, 2016

9 61Friday, March 11, 2016

1

9 61Friday, March 11, 2016

1A

5

PCH_SPI1_CLK{28}
PCH_SPI1_SO{28}

D D

C C

PCH_SPI1_SI{28}

PCH_SPI_CS2#_TPM{28}

SIO_EXT_SMI#{36}

CL_CLK{33}
CL_DATA{33}
CL_RST#{33}

EC_RCIN#{36}

EC_IRQ_SERIRQ{36}

4

PCH_SPI1_CLK
PCH_SPI1_SO
PCH_SPI1_SI
PCH_SPI_IO2
PCH_SPI_IO3
PCH_SPI_CS0#

PCH_SPI_CS2#_TPM

SIO_EXT_SMI#
PCI_SERR#

AW3
AW2

AW13

AY11

AV2
AV3
AU4

AU3
AU2
AU1

M2
M3

J4
V1
V2

M1

G3
G2
G1

U38E

SPI - FLASH

SPI0_CLK
SPI0_MISO
SPI0_MOSI
SPI0_IO2
SPI0_IO3
SPI0_CS0#
SPI0_CS1#
SPI0_CS2#

SPI - TOUCH

GPP_D1/SPI1_CLK
GPP_D2/SPI1_MISO
GPP_D3/SPI1_MOSI
GPP_D21/SPI1_IO2
GPP_D22/SPI1_IO3
GPP_D0/SPI1_CS#

C LINK

CL_CLK
CL_DATA
CL_RST#

GPP_A0/RCIN#
GPP_A6/SERIRQ

SKL_ULT

REV = 1

SKL_ULT

LPC

3

?

SMBUS, SMLINK

GPP_A14/SUS_STAT#/ESPI_RESET#

PDC

5 OF 20

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_B23/SML1ALERT#/PCHHOT#

GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

GPP_A8/CLKRUN#

2

+3V_DEEP_SUS{4,11,14,15,17}

SMB_PCH_CLK

R7

SMB_PCH_DAT

R8
R10

SMLALERT#

SMB_ME0_CLK

R9

SMB_ME0_DAT

W2
W1

SML0ALERT#

SMB_ME1_CLK

W3

SMB_ME1_DAT

V3

GPP_B23

AM7

AY13
BA13
BB13
AY12
BA12
BA11

CLK_PCI_EC_R

AW9

CLK_PCI_LPC_R

AY9
AW11

CLKRUN#

?

R679 22/F_4
R676 22/F_4

D3A

EC_LPCCLK
DEBUG_LCLKOUT

TP11

SMLALERT# {11}

SML0ALERT# {11}

LPC_LAD0 {33,36}
LPC_LAD1 {33,36}
LPC_LAD2 {33,36}
LPC_LAD3 {33,36}
LPC_LFRAME# {33,36}

EC_LPCCLK {36}
DEBUG_LCLKOUT {33}
CLKRUN# {36}

+3V{2,4,11,12,13,14,15,17,18,25,26,27,29,30,31,34,36,37,38,40,41,42,45,49,52,53,54}

+3VS5{4,12,15,26,28,30,32,33,35,36,41,42,44,49,51,53,54,56}

EMI(near PCH)

DEBUG_LCLKOUT
EC_LPCCLK

1

EC37

*E@18P/50V_4

10

EC36

*E@18P/50V_4

GPIO Pull UP

EC_IRQ_SERIRQ
CLKRUN#

SIO_EXT_SMI#
EC_RCIN#
PCI_SERR#

B B

R714 10K_4
R695 8.2K_4
R625 10K_4
R691 10K_4
R624 10K_4

+3V +3V_DEEP_SUS

SMB_PCH_CLK
SMB_PCH_DAT
SMB_ME1_CLK
SMB_ME1_DAT
SMB_ME0_CLK
SMB_ME0_DAT

R650 2.2K_4
R654 2.2K_4
R646 1K_4
R635 1K_4
R647 1K_4
R649 1K_4

SMBus/Pull-up(CLG)

+3V_DEEP_SUS

MBCLK_THRM{19,36,37,42}

MBDATA_THRM{19,36,37,42}

R648 4.7K_4

+3V

SMB_RUN_DAT{17,27}

A A

SMB_RUN_CLK{17,27}

5

+3V

R656 4.7K_4

Q41

5

2
6

*2N7002DW

Q42

4 3

1

SSM6N48FU

SMB_ME1_CLK

43

SMB_ME1_DAT

1

+3V

5

SMB_PCH_DAT

2

SMB_PCH_CLK

6

4

PCH SPI ROM(CLG)

R684 10K_4

+3VS5

C773 *1U/10V_4

Vender P/N
EON

Socket

3

Size

TP70
TP67
TP68
TP69
TP22
TP23

AKE3DZNKQ00(EN25QH128AHIP)16MB
AKE3DF00Q00 (GD25B128CSIGR)GGD 16MB

DFHS08FS023

PCH_SPI_CS0#_R
PCH_SPI1_CLK_R
PCH_SPI1_SI_R

PCH_SPI1_SO_R

BIOS_WP#
HOLD#

PCH_SPI_CS0# PCH_SPI_CS0#_R
PCH_SPI1_CLK

PCH_SPI1_SO

+3VSPI

PCH_SPI_IO2

R693 33_4
R690 33_4
R699 33_4
R694 33_4

R697 1K_4

R685 33_4

2

PCH_SPI1_CLK_R
PCH_SPI1_SI_RPCH_SPI1_SI
PCH_SPI1_SO_R

C769
22P/50V/NPO_4

PCH_SPI_CS0#_R {36}
PCH_SPI1_CLK_R {36}

PCH_SPI1_SI_R {36}

PCH_SPI1_SO_R {36}

R713 *0_4_S

U46

1

CE#

6

SCK

5

SI

2

SO

3

WP#

W25Q128FVSIQ

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

+3VS5

8

+3VSPI

VDD

7

HOLD#

4

VSS

SKYLAKE 9/15(SPI/LPC/SM)

SKYLAKE 9/15(SPI/LPC/SM)

SKYLAKE 9/15(SPI/LPC/SM)

R698 1K_4
R689 33_4

HOLD#

PCH_SPI_IO3BIOS_WP#

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

LV6

LV6

LV6

10 61Friday, March 11, 2016

10 61Friday, March 11, 2016

1

10 61Friday, March 11, 2016

C772

0.1U/16V/X7R_4

1A

1A

1A

5

4

3

2

+3V_DEEP_SUS{4,10,14,15,17}

1

+3V{2,4,10,12,13,14,15,17,18,25,26,27,29,30,31,34,36,37,38,40,41,42,45,49,52,53,54}

11

D D

Functional Strap Definitions

DESIGN NOTE:
WEAK PULL UP RESISTOR PRESENT ON THIS NET

ACZ_SPKR{14,29}

C C

B B

GSPI1_MOSI{14}

ACZ_SPKR

SMLALERT#

GSPI1_MOSI

R683
*20K/F_4

TOP SWAP OVERRIDE
HIGH - TOP SWAP ENABLE
LOW-DISABLED
HIGH: LPC SELECTED FOR SYSTEM FLASH
WEAK INTERNAL PD

+3V_DEEP_SUS

R657
1K/F_4

R653
*20K_4

No Boot:
The signal has a weak internal pull-down.
0 = Disable Intel ME Crypto Transport Layer Security
(TLS) cipher suite (no confidentiality).
1 = Enable Intel ME Crypto Transport Layer Security
(TLS) cipher suite (with confidentiality). Must be
pulled up to support Intel AMT with TLS and Intel
SBA (Small Business Advantage) with TLS.

ACZ_SDOUT{14}

EN_OVERRIDE{36}

GPP_B18{14}SMLALERT#{10}

SML0ALERT#{10}

R710 1K_4

ACZ_SDOUT

ACZ_SDOUT

GPP_B18

SML0ALERT#

+3V_DEEP_SUS

R702
*4.7K_4

+3V

R291
*4.7K_4

+3V_DEEP_SUS

R290
10K_4

R651
*10K_4

No Boot:
The signal has a weak internal pull-down.
0 = Enable security measures defined in the Flash
Descriptor.
1 = Disable Flash Descriptor Security (override). This
strap should only be asserted high using external
pull-up in manufacturing/debug environments ONLY.
This function is useful when running ITP/XDP.

No Boot:
The signal has a weak internal pull-down.
0 = Disable No Reboot mode.
1 = Enable No Reboot mode
(PCH will disable the TCO
Timer system reboot feature).
This function is useful when running ITP/XDP.

R670
*20K_4

No Boot:
The signal has a weak internal pull-down.
This field determines the destination of accesses to the
BIOS memory range. Also controllable using Boot BIOS
Destination bit (Chipset Configuration Registers: Offset
3410h:Bit 10). This strap is used in conjunction with Boot
BIOS Destination Selection 0 strap.
Bit 10 Boot BIOS Destination
0 SPI
1 LPC

A A

5

4

3

R652
20K_4

No Boot:
The signal has a weak internal pull-down.
0 = LPC Is selected for EC.
1 = eSPI Is selected for EC.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

SKYLAKE 10/15(Strip)

SKYLAKE 10/15(Strip)

SKYLAKE 10/15(Strip)

1

LV6

LV6

LV6

1A

1A

11 61Friday, March 11, 2016

11 61Friday, March 11, 2016

11 61Friday, March 11, 2016

1A

5

+3V

PEG_RXN0
PEG_RXP0
PEG_TXN0
PEG_TXP0

PEG_RXN1
PEG_RXP1
PEG_TXN1
PEG_TXP1

PEG_RXN2
PEG_RXP2
PEG_TXN2
PEG_TXP2

PEG_RXN3
PEG_RXP3
PEG_TXN3
PEG_TXP3

C3A

R608 100/F_4

R696 10K_4

C694 EV@0.22U/10V_4X
C693 EV@0.22U/10V_4X

C690 EV@0.22U/10V_4X
C698 EV@0.22U/10V_4X

C696 EV@0.22U/10V_4X
C697 EV@0.22U/10V_4X

C685 EV@0.22U/10V_4X
C691 EV@0.22U/10V_4X

C702 0.1U/16V/X7R_4
C703 0.1U/16V/X7R_4

C679 0.1U/16V/X7R_4
C683 0.1U/16V/X7R_4

TP4
TP6
TP40
TP37

TP74
TP77
TP76
TP75

PCIE_TXN5_LAN_C
PCIE_TXP5_LAN_C

PCIE_TXN6_WLAN_C
PCIE_TXP6_WLAN_C

PCIE_RCOMPN
PCIE_RCOMPP

PIRQA#

PEG_RXN0{18}
PEG_RXP0{18}
PEG_TXN0{18}

D D

PEG

LAN

WLAN

C C

ODD

HDD

B B

SSD

PEG_TXP0{18}
PEG_RXN1{18}

PEG_RXP1{18}
PEG_TXN1{18}
PEG_TXP1{18}

PEG_RXN2{18}
PEG_RXP2{18}
PEG_TXN2{18}
PEG_TXP2{18}

PEG_RXN3{18}
PEG_RXP3{18}
PEG_TXN3{18}
PEG_TXP3{18}

PCIE_RXN5_LAN#{30}
PCIE_RXP5_LAN{30}
PCIE_TXN5_LAN#{30}
PCIE_TXP5_LAN{30}

PCIE_RXN6_WLAN#{33}
PCIE_RXP6_WLAN{33}
PCIE_TXN6_WLAN#{33}
PCIE_TXP6_WLAN{33}

SATA_RXN7_ODD#{31}
SATA_RXP7_ODD{31}
SATA_TXN7_ODD#{31}
SATA_TXP7_ODD{31}

SATA_RXN8_HDD#{31}
SATA_RXP8_HDD{31}
SATA_TXN8_HDD#{31}
SATA_TXP8_HDD{31}

PCIE_RXN11_SSD{31}
PCIE_RXP11_SSD{31}
PCIE_TXN11_SSD{31}
PCIE_TXP11_SSD{31}
SATA_RXN_SSD#{31}
SATA_RXP_SSD{31}
SATA_TXN_SSD#{31}
SATA_TXP_SSD{31}

PCI-E Port Mapping Table

PCI-E Port

Function

Port1

Port2

Port3

dGPU

Port4

Port5

Port6

Port7

A A

Port8

Port9

Port10

Port11

Port12

LAN
WLAN
ODD
HDD

Un-used

DOCK

SSD
if Pcie Bus will lane reverse.
if SATA BUS is SATA2.

5

CLK RQ Port

Port0

Port1

Port2

Port3

Port4

Port5

Function

dGPU

LAN

WLAN

DOCK

Un-used

SSD

PEG_TXN0_C
PEG_TXP0_C

PEG_TXN1_C
PEG_TXP1_C

PEG_TXN2_C
PEG_TXP2_C

PEG_TXN3_C
PEG_TXP3_C

4

U38H

H13

PCIE1_RXN/USB3_5_RXN

G13

PCIE1_RXP/USB3_5_RXP

B17

PCIE1_TXN/USB3_5_TXN

A17

PCIE1_TXP/USB3_5_TXP

G11

PCIE2_RXN/USB3_6_RXN

F11

PCIE2_RXP/USB3_6_RXP

D16

PCIE2_TXN/USB3_6_TXN

C16

PCIE2_TXP/USB3_6_TXP

H16

PCIE3_RXN

G16

PCIE3_RXP

D17

PCIE3_TXN

C17

PCIE3_TXP

G15

PCIE4_RXN

F15

PCIE4_RXP

B19

PCIE4_TXN

A19

PCIE4_TXP

F16

PCIE5_RXN

E16

PCIE5_RXP

C19

PCIE5_TXN

D19

PCIE5_TXP

G18

PCIE6_RXN

F18

PCIE6_RXP

D20

PCIE6_TXN

C20

PCIE6_TXP

F20

PCIE7_RXN/SATA0_RXN

E20

PCIE7_RXP/SATA0_RXP

B21

PCIE7_TXN/SATA0_TXN

A21

PCIE7_TXP/SATA0_TXP

G21

PCIE8_RXN/SATA1A_RXN

F21

PCIE8_RXP/SATA1A_RXP

D21

PCIE8_TXN/SATA1A_TXN

C21

PCIE8_TXP/SATA1A_TXP

E22

PCIE9_RXN

E23

PCIE9_RXP

B23

PCIE9_TXN

A23

PCIE9_TXP

F25

PCIE10_RXN

E25

PCIE10_RXP

D23

PCIE10_TXN

C23

PCIE10_TXP

F5

PCIE_RCOMPN

E5

PCIE_RCOMPP

D56

PROC_PRDY#

D61

PROC_PREQ#

BB11

GPP_A7/PIRQA#

E28

PCIE11_RXN/SATA1B_RXN

E27

PCIE11_RXP/SATA1B_RXP

D24

PCIE11_TXN/SATA1B_TXN

C24

PCIE11_TXP/SATA1B_TXP

E30

PCIE12_RXN/SATA2_RXN

F30

PCIE12_RXP/SATA2_RXP

A25

PCIE12_TXN/SATA2_TXN

B25

PCIE12_TXP/SATA2_TXP

SKL_ULT

REV = 1

4

PCIE/USB3/SATA

3

?

SKL_ULT

PDC

SSIC / USB3

USB2

GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2

8 OF 20

USB3_1_RXN

USB3_1_RXP
USB3_1_TXN
USB3_1_TXP

USB3_2_RXN/SSIC_1_RXN
USB3_2_RXP/SSIC_1_RXP

USB3_2_TXN/SSIC_1_TXN
USB3_2_TXP/SSIC_1_TXP

USB3_3_RXN/SSIC_2_RXN
USB3_3_RXP/SSIC_2_RXP

USB3_3_TXN/SSIC_2_TXN
USB3_3_TXP/SSIC_2_TXP

USB3_4_RXN

USB3_4_RXP
USB3_4_TXN
USB3_4_TXP

USB2_COMP

USB2_VBUSSENSE

GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#

GPP_E4/DEVSLP0
GPP_E5/DEVSLP1
GPP_E6/DEVSLP2

GPP_E8/SATALED#

?

USB3.0 Port Mapping Table

USB3.0 Function
PORT-1
PORT-2
PORT-3

USB3.0_R1
USB3.0_R2
USB3.0_DOCK

PORT-4

3

USB2N_1
USB2P_1

USB2N_2
USB2P_2

USB2N_3
USB2P_3

USB2N_4
USB2P_4

USB2N_5
USB2P_5

USB2N_6
USB2P_6

USB2N_7
USB2P_7

USB2N_8
USB2P_8

USB2N_9
USB2P_9

USB2N_10
USB2P_10

USB2_ID

H8
G8
C13
D13

J6
H6
B13
A13

J10
H10
B15
A15

E10
F10
C15
D15

AB9
AB10

AD6
AD7

AH3
AJ3

AD9
AD10

AJ1
AJ2

AF6
AF7

AH1
AH2

AF8
AF9

AG1
AG2

AH7
AH8

AB6
AG3
AG4

A9
C9
D9
B9

J1
J2
J3

H2
H3
G4

H1

USB30_RX1-_R1
USB30_RX1+_R1
USB30_TX1-_R1
USB30_TX1+_R1

USB30_RX2-_R2
USB30_RX2+_R2
USB30_TX2-_R2
USB30_TX2+_R2

USB30_RX3-_DOCK
USB30_RX3+_DOCK
USB30_TX3-_DOCK
USB30_TX3+_DOCK

USBP1-_R1
USBP1+_R1

USBP2-_R2
USBP2+_R2

USBP3-_DOCK
USBP3+_DOCK

USBP4-_L1
USBP4+_L1

USBP5-_L2
USBP5+_L2

USBP6-_FP
USBP6+_FP

USBP7-_Card
USBP7+_Card

USBP8-_BT
USBP8+_BT

USBP9-_CCD
USBP9+_CCD

USB2_COMP

R227 113/F_4
R236 *0_4_S

USB_Normal_OC0#_R
USB_Normal_OC1#
USB_SC_OC2#
USB_Normal_OC3#_L2

WLAN_OFF#
DEVSLP1_HDD
DEVSLP2_SSD

TPM_INT#

SSD_PEDET#
SATA_LED#_R

2

USB30_RX1-_R1 {34}
USB30_RX1+_R1 {34}
USB30_TX1-_R1 {34}
USB30_TX1+_R1 {34}

USB30_RX2-_R2 {34}
USB30_RX2+_R2 {34}
USB30_TX2-_R2 {34}
USB30_TX2+_R2 {34}

USB30_RX3-_DOCK {39}
USB30_RX3+_DOCK {39}
USB30_TX3-_DOCK {39}
USB30_TX3+_DOCK {39}

USBP1-_R1 {34}
USBP1+_R1 {34}

USBP2-_R2 {34}
USBP2+_R2 {34}

USBP3-_DOCK {39}
USBP3+_DOCK {39}

USBP4-_L1 {35}
USBP4+_L1 {35}

USBP5-_L2 {35}
USBP5+_L2 {35}

USBP6-_FP {38}
USBP6+_FP {38}

USBP7-_Card {32}
USBP7+_Card {32}

USBP8-_BT {33}
USBP8+_BT {33}

USBP9-_CCD {25}
USBP9+_CCD {25}

USB_Normal_OC0#_R {34}
USB_SC_OC2# {35}

USB_Normal_OC3#_L2 {35}

WLAN_OFF# {33}
DEVSLP1_HDD {31}
DEVSLP2_SSD {31}

TPM_INT# {28}
SSD_PEDET# {31}

SATA_LED#_R {38}

USB3.0_R1

USB3.0_R2

Onelink+_USB3.0

USB2.0_R1
USB2.0_R2
Onelink+_USB2.0
USB2.0_L1&SC
USB2.0_L2
Figure Printer
Cardreader
BT
CCD

HDD Device Sleep
SSD Device Sleep

USB2.0 Port Mapping Table

USB2.0 Function
PORT-1
PORT-2
PORT-3
PORT-4
PORT-5
PORT-6
PORT-7
PORT-8
PORT-9
PORT-10

2

USB2.0_R1
USB2.0_R2
USB2.0_DOCK
USB2.0_L1_S&C
USB2.0_L2
Figure Printer
Cardreader
BT
CCD

NC

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

+3V{2,4,10,11,13,14,15,17,18,25,26,27,29,30,31,34,36,37,38,40,41,42,45,49,52,53,54}

+3VS5{4,10,15,26,28,30,32,33,35,36,41,42,44,49,51,53,54,56}

SATA_LED#_R
DEVSLP1_HDD
DEVSLP2_SSD
SSD_PEDET#

USB_Normal_OC0#_R
USB_Normal_OC1#
USB_SC_OC2#
USB_Normal_OC3#_L2
WLAN_OFF#

SKYLAKE 11/15 (PCIE/USB)

SKYLAKE 11/15 (PCIE/USB)

SKYLAKE 11/15 (PCIE/USB)

R606 10K_4
R618 *10K_4
R614 *10K_4
R180 10K_4

R586 10K_4
R580 10K_4
R594 10K_4
R592 10K_4
R619 10K_4

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

LV6

LV6

LV6

1

12 61Friday, March 11, 2016

12 61Friday, March 11, 2016

12 61Friday, March 11, 2016

12

+3V

+3VS5

1A

1A

1A

5

C3A

CLK_PCIE_VGAN{18}
CLK_PCIE_VGAP{18}

PCIE_CLK_VGA_REQ#{19}

CLK_PCIE_LAN#{30}
CLK_PCIE_LAN{30}
PCIE_CLK_LAN_REQ#{30}

CLK_PCIE_WLANN{33}
CLK_PCIE_WLANP{33}

PCIE_CLK_WLAN_REQ#{33}

TP72
TP73

TP38
TP39

CLK_PCIE_SSDN{31}
CLK_PCIE_SSDP{31}

PCIE_CLK_SSD_REQ#{31}

D D

PEG

LAN

WLAN

DOCK

SSD

CLK_REQ/Strap Pin(CLG)

C C

+3V

4

R28910K_4
R71210K_4

R70610K_4

R71510K_4
R70410K_4
R70510K_4

PCIE_CLK_VGA_REQ#

PCIE_CLK_LAN_REQ#

PCIE_CLK_WLAN_REQ#

PCIE_CLK_LAN_REQ#_DOCK

PCIE_CLKREQ4#

R568 *SSD@0_2_S
R570 *SSD@0_2_S

PCIE_CLK_SSD_REQ#

PCIE_CLK_LAN_REQ#_DOCK
PCIE_CLK_WLAN_REQ#
PCIE_CLK_LAN_REQ#
PCIE_CLK_VGA_REQ#
PCIE_CLKREQ4#
PCIE_CLK_SSD_REQ#

U38J

D42

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0

AR10

GPP_B5/ SRCCLKREQ 0#

B42

CLKOUT_PCIE_N1

A42

CLKOUT_PCIE_P1

AT7

GPP_B6/ SRCCLKREQ 1#

D41

CLKOUT_PCIE_N2

C41

CLKOUT_PCIE_P2

AT8

GPP_B7/ SRCCLKREQ 2#

D40

CLKOUT_PCIE_N3

C40

CLKOUT_PCIE_P3

AT10

GPP_B8/ SRCCLKREQ 3#

B40

CLKOUT_PCIE_N4

A40

CLKOUT_PCIE_P4

AU8

GPP_B9/ SRCCLKREQ 4#

E40

CLKOUT_PCIE_N5

E38

CLKOUT_PCIE_P5

AU7

GPP_B10 /SRCCLKRE Q5#

SKL_ULT

REV = 1

A36

B36
C38
D38
C36
D36

A38

B38
C31

D31
C33
D33

A31

B31

A33

B33

A29

B29
C28
D28

A27

B27
C27
D27

U38I

CSI-2

CSI2_DN0
CSI2_DP0
CSI2_DN1
CSI2_DP1
CSI2_DN2
CSI2_DP2
CSI2_DN3
CSI2_DP3

CSI2_DN4
CSI2_DP4
CSI2_DN5
CSI2_DP5
CSI2_DN6
CSI2_DP6
CSI2_DN7
CSI2_DP7

CSI2_DN8
CSI2_DP8
CSI2_DN9
CSI2_DP9
CSI2_DN10
CSI2_DP10
CSI2_DN11
CSI2_DP11

SKL_ULT

REV = 1

SKL_ULT

CLOCK SIGNALS

SKL_ULT

?

10 OF 20

?

PDC

9 OF 20

3

CLKOUT_ITPXD P_N
CLKOUT_ITPXD P_P

GPD8/SUSCLK

XTAL24_IN

XTAL24_OUT

XCLK_BIA SREF

SRTCRST#

TBT

CSI2_CLK N0
CSI2_CLK P0
CSI2_CLK N1
CSI2_CLK P1
CSI2_CLK N2
CSI2_CLK P2
CSI2_CLK N3
CSI2_CLK P3

CSI2_COMP

GPP_D4/FLASHTRIG

EMMC

GPP_F13 /EMMC_DATA0
GPP_F14 /EMMC_DATA1
GPP_F15 /EMMC_DATA2
GPP_F16 /EMMC_DATA3
GPP_F17 /EMMC_DATA4
GPP_F18 /EMMC_DATA5
GPP_F19 /EMMC_DATA6
GPP_F20 /EMMC_DATA7

GPP_F21 /EMMC_RCLK

GPP_F22 /EMMC_CLK

GPP_F12 /EMMC_CMD

EMMC_RCOMP

?

RTCX1
RTCX2

RTCRST#

2

+3V_RTC_2{4,15}

+3V{2,4,10,11,12,14,15,17,18,25,26,27,29,30,31,34,36,37,38,40,41,42,45,49,52,53, 54}

+1.0V_DEEP_SUS{9,15,51,53,54,56}

VSTBY_FSPI{25,29,36,38,39}

F43
E43

PCH_SUSCLK_R

BA17
E37

E35
E42
AM18

AM20
AN18

AM16

?

C37
D37
C32
D32
C29
D29
B26
A26

E13
B7

AP2
AP1
AP3
AN3
AN1
AN2
AM4
AM1

AM2
AM3
AP4

AT1

XTAL24_IN
XTAL24_OUT

XCLK_BIASREF

RTC_X1
RTC_X2

SRTC_RST#
RTC_RST#

CSI2_COMP

EMMC_RCOMP

R242 *SSD@0_4_S

R169 2.7K/F_4
R176 *60.4/F_4

R182 100/F_4

R672 200/F_4

PCH_SUSCLK {31}

+1.0V_DEEP_SUS

Co-lay 60ohm 1% to GND
for Connonlake-U use

1

13

B B

RTC Clock 32.768KHz (RTC)

<RTC>

B2B

C763 15P/50V/NPO_4

Y5

32.768KHz

C755 15P/50V/NPO_4

A A

5

RTC_X1

12

R669
10M_4

RTC_X2

RTC Circuitry (RTC)

+3V_RTC

R441 45.3K_4

R434 1K_4

12

CN21

94-0013-01

<RTC>

+3V_RTC_1 EC_RTC_RST

R436
*45.3K_4

4

RTC Power trace width 20mils.

R442

1.5K_4

2 1

D14 DB2J40600L

2 1

D13 DB2J40600L

C548
1U/6.3V_4X

+3V_RTC_2VSTBY_FSPI

R294

20K/F_4

R300
20K/F_4

C415
1U/6.3V_4X

SRTC_RST#

C423
1U/6.3V_4X

EC14
*E@220P/50V_4

RTC_RST#

12

*JUMP

RTC_RST#

GRTC1

3

3

2

Q25

2N7002K

1

RTC_RST#

R309
10K_4

EC_RTC_RST {36}

External Crystal and Green Clock

C242 12P/50V_4

1

XTAL24_IN
XTAL24_OUT

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

2

R177

24MHZ +-30PPM

1M_4

Y1

4

3

C243 12P/50V_4

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

SKYLAKE 12/15 (CLK/EMMC)

SKYLAKE 12/15 (CLK/EMMC)

SKYLAKE 12/15 (CLK/EMMC)

1

LV6

LV6

LV6

1A

1A

13 61Friday, March 11, 2016

13 61Friday, March 11, 2016

13 61Friday, March 11, 2016

1A

5

4

3

2

1

DGPU <VGA>

<CPU>

+3V

DGPU_PWR_EN

R281EV@10K_4

DGPU_HOLD_RST#

R282EV@10K_4

DGPU_PWROK

R680*EV@10K_4

D D

+3V_DEEP_SUS

BT_RADIO_DIS#

R63210K_4

PCH_TEMPALERT#

R63110K_4

SIO_EXT_SCI#

R65910K_4

UART2_TXD

R66049.9K/F_4

UART2_RXD

+3V_DEEP_SUS

C C

Model

Sku

E42(R310_14)

0

E52(R310_15)

1

V310_14

2

V310_15

3

Tianyi310_14

B B

4

5

6

7

Tianyi310_15

Reserved

Reserved

BOARD_ID3

BOARD_ID4

BOARD_ID5

BOARD_ID6

BOARD_ID7

On Board Memory

A A

BOARD_ID10
BOARD_ID9
BOARD_ID8

BOARD_ID11 Hi = Skylake Lo = Kaby lake

R66449.9K/F_4

BOARD_ID0

R661SKU@10K_2

BOARD_ID1

R658SKU@10K_2

BOARD_ID2

R666SKU@10K_2

BOARD_ID3

R222IV@10K_2

BOARD_ID4

R218NDK@10K_2

BOARD_ID5

R217N2B@10K_2

BOARD_ID6

R304NFP@10K_2

BOARD_ID7

R303NSSD@10K_2

BOARD_ID8

R305ONB@10K_2

BOARD_ID9

R306ONB@10K_2

BOARD_ID10

R766ONB@10K_2

BOARD_ID11

R768SKL@10K_2

R662SKU@10K_2
R663SKU@10K_2
R665SKU@10K_2
R223EV@10K_2
R216DK@10K_2
R2122B@10K_2
R312FP@10K_2
R311SSD@10K_2
R313ONB@10K_2
R314ONB@10K_2
R765ONB@10K_2
R767KBY@10K_2

BOARD_ID1BOARD_ID0 BOARD_ID2

0 0 0

00

0

0

1

1

1

1

1

1

0

0

1

1

Hi = UMA Lo = Discrete

Hi = wo Prolink Lo = w Prolink

Hi = wo 2nd Battery Lo = w 2nd Battery

Hi = wo Figure Printer Lo = w Figure Printer

Hi = wo SSD Lo = w SSD

[ 1, 1, 1 ] = Samsung K4A8G165WB-BCRC
[ 1, 1, 0 ] = Micro MT40A512M16JY-083E:B
[ 1, 0, 1 ] = SMART
[ 1, 0, 0 ] = Teikon
[ 0, 1, 1 ] = Samsung K4A8G165WB-BCPB
[ 0, 1, 0 ] = Micro MT40A512M16HA-083E:A
[ 0, 0, 1 ] = Hynix H5AN8G6NAFR-TFC
[ 0, 0, 0 ] = No Memory Down

5

1

0

1

0

1

0

1

D3A

B2A

C3A

B2A

CR_EN#{32}
DGPU_PWR_EN{18,56}

DGPU_HOLD_RST#{18}

GPP_B18{11}

DGPU_PWROK{52}

GSPI1_MOSI{11}

LCD_BK_OFF{25}
CCD_EN{25}

UART2_RXD{34}
UART2_TXD{34}

SIO_EXT_SCI#{36}

ACZ_SDOUT{11}

ACZ_SDIN0{29}

TP54

ACZ_SPKR{11,29}

4

TP48

DGPU_PWR_EN
DGPU_HOLD_RST#

GPP_B18

DGPU_PWROK

GSPI1_MOSI

UART2_RXD
UART2_TXD

SIO_EXT_SCI#

ACZ_SYNC
ACZ_BCLK
ACZ_SDOUT

ACZ_SDIN0
ACZ_RST#

ACZ_SPKR

U38F

AN8

GPP_B15/GSPI0_CS#

AP7

GPP_B16/GSPI0_CLK

AP8

GPP_B17/GSPI0_MISO

AR7

GPP_B18/GSPI0_MOSI

AM5

GPP_B19/GSPI1_CS#

AN7

GPP_B20/GSPI1_CLK

AP5

GPP_B21/GSPI1_MISO

AN5

GPP_B22/GSPI1_MOSI

AB1

GPP_C8/UART0_RXD

AB2

GPP_C9/UART0_TXD

W4

GPP_C10/UART0_RTS#

AB3

GPP_C11/UART0_CTS#

AD1

GPP_C20/UART2_RXD

AD2

GPP_C21/UART2_TXD

AD3

GPP_C22/UART2_RTS#

AD4

GPP_C23/UART2_CTS#

U7

GPP_C16/I2C0_SDA

U6

GPP_C17/I2C0_SCL

U8

GPP_C18/I2C1_SDA

U9

GPP_C19/I2C1_SCL

AH9

GPP_F4/I2C2_SDA

AH10

GPP_F5/I2C2_SCL

AH11

GPP_F6/I2C3_SDA

AH12

GPP_F7/I2C3_SCL

AF11

GPP_F8/I2C4_SDA

AF12

GPP_F9/I2C4_SCL

SKL_ULT

REV = 1

LPSS ISH

U38G

BA22

HDA_SYNC/I2S0_SFRM

AY22

HDA_BLK/I2S0_SCLK

BB22

HDA_SDO/I2S0_TXD

BA21

HDA_SDI0/I2S0_RXD

AY21

HDA_SDI1/I2S1_RXD

AW22

HDA_RST#/I2S1_SCLK

J5

GPP_D23/I2S_MCLK

AY20

I2S1_SFRM

AW20

I2S1_TXD

AK7

GPP_F1/I2S2_SFRM

AK6

GPP_F0/I2S2_SCLK

AK9

GPP_F2/I2S2_TXD

AK10

GPP_F3/I2S2_RXD

H5

GPP_D19/DMIC_CLK0

D7

GPP_D20/DMIC_DATA0

D8

GPP_D17/DMIC_CLK1

C8

GPP_D18/DMIC_DATA1

AW5

GPP_B14/SPKR

SKL_ULT

3

Skylake (GPIO)

?

SKL_ULT

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL

6 OF 20

?

SKL_ULT

AUDIO

REV = 1

7 OF 20

ACZ_SYNC
ACZ_SYNC

ACZ_SDOUT
ACZ_BCLK

GPP_D9
GPP_D10
GPP_D11
GPP_D12

GPP_D5/ISH_I2C0_SDA
GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA
GPP_D8/ISH_I2C1_SCL

GPP_F10/I2C5_SDA/ISH_I2C2_SDA
GPP_F11/I2C5_SCL/ISH_I2C2_SCL

GPP_D15/ISH_UART0_RTS#

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
GPP_C15/UART1_CTS#/ISH_UART1_CTS#

SDIO/SDXC

GPP_A17/SD_PWR_EN#/ISH_GP7

R703*1K_4
R70933_4

R71133_4

R70133_4

GPP_A18/ISH_GP0
GPP_A19/ISH_GP1
GPP_A20/ISH_GP2
GPP_A21/ISH_GP3
GPP_A22/ISH_GP4
GPP_A23/ISH_GP5

GPP_A12/BM_BUSY#/ISH_GP6

GPP_G0/SD_CMD
GPP_G1/SD_DATA0
GPP_G2/SD_DATA1
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3

GPP_G5/SD_CD#
GPP_G6/SD_CLK

GPP_G7/SD_WP

GPP_A16/SD_1P8_SEL

SD_RCOMP

GPP_F23

?

+3V_DEEP_SUS

ACZ_SYNC_AUDIO {29}

ACZ_SDOUT_AUDIO {29}

BIT_CLK_AUDIO {29}

C770

*10P/50V_4

2

?

AB11
AB13
AB12
W12
W11
W10
W8
W7

BA9
BB9

AB7

AF13

P2
P3
P4
P1

M4
N3

N1
N2

AD11
AD12

U1
U2
U3
U4

AC1
AC2
AC3
AB4

AY8
BA8
BB7
BA7
AY7
AW7
AP13

+3V_DEEP_SUS{4,10,11,15,17}

+3V{2,4,10,11,12,13,15,17,18,25,26,27,29,30,31,34,36,37,38,40,41,42,45,49,52,53,54}

14

TP47
TP46
TP45

BT_RADIO_DIS# {33}

PCH_TEMPALERT#

BOARD_ID6
BOARD_ID7
BOARD_ID8
BOARD_ID9
BOARD_ID10
BOARD_ID11

B2A

BOARD_ID0
BOARD_ID1
BOARD_ID2
BOARD_ID3
BOARD_ID4
BOARD_ID5

R322 *0_4_S
R636 *0_4_S

GPP_A16
SD_RCOMP

R220 200/F_4

TP9

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

SKYLAKE 13/15 (HDA/GPIO)

SKYLAKE 13/15 (HDA/GPIO)

SKYLAKE 13/15 (HDA/GPIO)

Date: Sheet of

Date: Sheet of

Date: Sheet of

PROJECT :

GPP_A16 {34}

1

NUM_LED# {38}
CAP_LOCK_LED# {38}

LV6

LV6

LV6

14 61Friday, March 11, 2016

14 61Friday, March 11, 2016

14 61Friday, March 11, 2016

1A

1A

1A

5

D D

C334 1U/6.3V_4X

+1.0V_DEEP_SUS

+VCCDSW_1.0V

+1.0V_DEEP_SUS

+1.0V_DEEP_SUS

+1.0V_DEEP_SUS

C C

B B

+1.0V_DEEP_SUS

+1.0V_DEEP_SUS

+3VS5

+V3.3DX_1.5DX_ADO

+3V_DEEP_SUS

+1.0V_DEEP_SUS

+3V_DEEP_SUS

+1.0V_DEEP_SUS

+1.0V_DEEP_SUS

R226 *0_4_S

C326 *1U/6.3V_4X

C754 1U/6.3V_4X

R627 *0_6_S

C202 1U/6.3V_4X
C177 47U/6.3V_8

R202 *0_4_S

L12 HCB1608KF-221T20_2A

R221 *0_6_S
R215 *0_6_S

C354 *1U/6.3V_4X
C389 0.1U/16V/X7R_4
C388 *0.1P/50V_4

R260 *0_6_S

R232 *0_6_S

R258 *0_6_S
R682 *0_6_S
R198 *0_6_S

C315 *1U/6.3V_4X

C2791U/6.3V_4X

4

+VCCPRIM

+VCCMPHYAON_1P0

+VCCAMPHYPLL_1P0

C285 *1U/6.3V_4X

+VCCAPLL_1.0V

C289 0.1U/16V/X7R_4

+VCCPRIM

+V3.3DX_1.5DX_ADO_R
+VCCSPI

+VCCSRAM_1.0V

+VCCPRIM_3.3V
+VCCPRIM_1.0V
+VCCAPLLEBB

U38O

AB19

VCCPRIM_1P0

AB20

VCCPRIM_1P0

P18

VCCPRIM_1P0

AF18

VCCPRIM_CORE

AF19

VCCPRIM_CORE

V20

VCCPRIM_CORE

V21

VCCPRIM_CORE

AL1

DCPDSW_1P0

K17

VCCMPHYAON_1P0

L1

VCCMPHYAON_1P0

N15

VCCMPHYGT_1P0_N15

N16

VCCMPHYGT_1P0_N16

N17

VCCMPHYGT_1P0_N17

P15

VCCMPHYGT_1P0_P15

P16

VCCMPHYGT_1P0_P16

K15

VCCAMPHYPLL_1P0

L15

VCCAMPHYPLL_1P0

V15

VCCAPLL_1P0

AB17

VCCPRIM_1P0_AB17

Y18

VCCPRIM_1P0_Y18

AD17

VCCDSW_3P3_AD17

AD18

VCCDSW_3P3_AD18

AJ17

VCCDSW_3P3_AJ17

AJ19

VCCHDA

AJ16

VCCSPI

AF20

VCCSRAM_1P0

AF21

VCCSRAM_1P0

T19

VCCSRAM_1P0

T20

VCCSRAM_1P0

AJ21

VCCPRIM_3P3_AJ21

AK20

VCCPRIM_1P0_AK20

N18

VCCAPLLEBB

SKL_ULT

REV = 1

SKL_ULT

CPU POWER 4 OF 4

2.899A

2.57A

1.714A

0.03A

0.09A

?

15 OF 20

3

VCCPGPPA
VCCPGPPB
VCCPGPPC
VCCPGPPD
VCCPGPPE
VCCPGPPF
VCCPGPPG

VCCPRIM_3P3_V19

VCCPRIM_1P0_T1

VCCATS_1P8

VCCRTCPRIM_3P3

VCCRTC_AK19
VCCRTC_BB14

DCPRTC
VCCCLK1
VCCCLK2
VCCCLK3
VCCCLK4
VCCCLK5
VCCCLK6

GPP_B0/CORE_VID0
GPP_B1/CORE_VID1

2

+3V_DEEP_SUS{4,10,11,14,17}
+1.0V_DEEP_SUS{9,13,51,53,54,56}
+1.8V_DEEP_SUS{5,9,42,53,56}

AK15
AG15
Y16
Y15
T16
AF16
AD15

V19
T1
AA1
AK17
AK19

BB14
BB10
A14
K19
L21
N20
L19
A10
AN11

AN13

?

+VCCPGPPA
+VCCPGPPB
+VCCPGPPC
+VCCPGPPD
+VCCPGPPE

+VCCPGPPF

+VCCPGPPG

+VCCPRIM_1.0V_T1
+VCCATS_1.8V
+VCCRTCPRIM_3.3V
+VCCRTC

DCPRTC
+VCCCLK1

+VCCCLK2

+VCCCLK3

+VCCCLK4
+VCCCLK5

+VCCCLK6
CORE_VID0

CORE_VID1

C404 *1U/6.3V_4X

R633 *0_6_S
R655 *0_6_SC269 1U/6.3V_4X
R259 *0_6_S
R286 *0_4_S

C768 0.1U/16V/X7R_4
R150 *0_6_S
R161 *0_4_S
R673 *0_6_S
R201 *0_4_S

R157 *0_6_S

C196 *1U/6.3V_4X

+3V_DEEP_SUS
+1.0V_DEEP_SUS
+1.8V_DEEP_SUS
+3V_DEEP_SUS
+3V_RTC_2

+1.0V_DEEP_SUS

TP14
TP10

+VCCPGPPA
+VCCPGPPB
+VCCPGPPC
+VCCPGPPD
+VCCPGPPE
+VCCPGPPG

+VCCPGPPF

+VCCRTCPRIM_3.3V+VCCATS_1.8V +VCCRTC

+VCCCLK2
+VCCCLK4
+VCCCLK5
+VCCAMPHYPLL_1P0

1

+3VS5{4,10,12,26,28,30,32,33,35,36,41,42,44,49,51,53,54,56}

+3V_RTC_2{4,13}

+3V{2,4,10,11,12,13,14,17,18,25,26,27,29,30,31,34,36,37,38,40,41,42,45,49,52,53,54}

R234 *0_4_S
R266 *0_4_S
R671 *0_4_S
R207 *0_4_S
R205 *0_4_S
R229 *0_4_S

R681 *0_4_S

C220 *10U/6.3V_4
C295 *10U/6.3V_4R167 *0_4_S
C247 *10U/6.3V_4
C286 *10U/6.3V_4

15

+3V_DEEP_SUS

+1.8V_DEEP_SUS

+V3.3DX_1.5DX_ADO +1.0V_DEEP_SUS

L13 HCB1608KF-221T20_2A

A A

5

+3V

C213

*1U/6.3V_4X

4

C190
*22U/6.3V/X5R_6

R194 *0_6_S
R230 *0_6_S

3

+3V_DEEP_SUS+3VS5

C745

1U/6.3V_4X

+VCCPGPPB +VCCPGPPC +VCCPGPPE

C398

*1U/6.3V_4X

2

C405

0.1U/16V/X7R_4

C756

*1U/6.3V_4X

C411
1U/6.3V_4X

C396

1U/6.3V_4X

1U/6.3V_4X

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

C395

0.1U/16V/X7R_4

C291

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

SKYPAKE 14/15(PCH POWER)

SKYPAKE 14/15(PCH POWER)

SKYPAKE 14/15(PCH POWER)

1

LV6

LV6

LV6

1A

1A

15 61Friday, March 11, 2016

15 61Friday, March 11, 2016

15 61Friday, March 11, 2016

1A

<DDR>

5

(Memory Down)

4

3

2

1

16

+1.2V_SUS{3,6,17,50}

+2.5V_SUS{17,50}

+0.6V_DDR_VTT{17,50}

M_A_DQ[63:0]{3}
M_A_A[13:0]{3}

D D

M_A_BA#0{3}
M_A_BA#1{3}
M_A_BG#0{3}

M_A_CLKP0{3}
M_A_CLKN0{3}

C C

DDR4_DRAMRST#{3,17}

B B

M_A_CKE0{3}

M_A_ODT0_CPU{3}

M_A_CS#0{3}
M_A_DQSP7{3}

M_A_DQSP6{3} M_A_DQSP4{3}
M_A_DQSN7{3}

M_A_DQSN6{3}

M_A_ALERT#{3}

M_A_ACT#{3}

M_A_PARITY{3}

+SMDDR_VREF_DIMM

+2.5V_SUS

M_A_WE#{3}
M_A_CAS#{3}
M_A_RAS#{3}

DDR4_DRAMRST#

R377 240/F_4

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13

M_A_WE#
M_A_CAS#
M_A_RAS#

M_A_BS#0
M_A_BS#1
M_A_BG#0 M_A_BG#0 M_A_BG#0 M_A_BG#0

M_A_CLKP0
M_A_CLKN0
M_A_CKE0

M_A_ODT0
M_A_CS#0

M_A_DQSP7
M_A_DQSP6

M_A_DQSN7
M_A_DQSN6

DDR0_ALERT# DDR0_ALERT# DDR0_ALERT# DDR0_ALERT#

DDR0_PAR DDR0_PAR DDR0_PAR DDR0_PAR

M_A1_ZQ0

U19

M1

VREFCA

B1

VPP

R9

VPP

P3

A0

P7

A1

R3

A2

N7

A3

N3

A4

P8

A5

P2

A6

R8

A7

R2

A8

R7

A9

M3

A10/AP

T2

A11

M7

A12/BC

T8

A13

L2

WE_n/A14

M8

CAS_n/A15

L8

RAS_n/A16

N2

BA0

N8

BA1

M2

BG0

K7

CK_t

K8

CK_c

K2

CKE

K3

ODT

L7

CS

G3

DQSL_t

B7

DQSU_t

F3

DQSL_c

A7

DQSU_c

E7

DML_n/DBIL_n

E2

DMU_n/DBIU_n

P1

RESET_n

F9

ZQ

N9

TEN

P9

ALERT_n

L3

ACT_n

T3

PAR

T7

NC

96-BALL
DDR4

MT40A512M16HA-083E:A

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B3
VDD#B9
VDD#D1
VDD#G7
VDD#J1
VDD#J9
VDD#L1
VDD#L9
VDD#R1
VDD#T9

VDDQ#A1
VDDQ#A9
VDDQ#C1
VDDQ#D9
VDDQ#F2
VDDQ#F8
VDDQ#G1
VDDQ#G9

VDDQ#J2
VDDQ#J8

VSS#B2
VSS#E1
VSS#E9
VSS#G8
VSS#K1
VSS#K9
VSS#M9
VSS#N1

VSS#T1

VSSQ#A2
VSSQ#A8
VSSQ#C9
VSSQ#D2
VSSQ#D8
VSSQ#E3
VSSQ#E8

VSSQ#F1
VSSQ#H1
VSSQ#H9

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

M_A_DQ59

F7

M_A_DQ56

H3

M_A_DQ63

H7

M_A_DQ60

H2

M_A_DQ62

H8

M_A_DQ57

J3

M_A_DQ58

J7

M_A_DQ48

A3

M_A_DQ54

B8

M_A_DQ53

C3

M_A_DQ55

C7

M_A_DQ49

C2

M_A_DQ51

C8

M_A_DQ52

D3

M_A_DQ50

D7

B3
B9
D1
G7
J1
J9
L1
L9
R1
T9

A1
A9
C1
D9
F2
F8
G1
G9
J2
J8

B2
E1
E9
G8
K1
K9
M9
N1
T1

A2
A8
C9
D2
D8
E3
E8
F1
H1
H9

+1.2V_SUS

M_A_DQSP3{3}
M_A_DQSN2{3}

M_A_DQSN3{3}

M_A_DQ61

G2

+SMDDR_VREF_DIMM

+2.5V_SUS

R380 240/F_4

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13

M_A_WE#
M_A_CAS#
M_A_RAS#

M_A_BS#0
M_A_BS#1

M_A_CLKP0
M_A_CLKN0
M_A_CKE0

M_A_ODT0
M_A_CS#0

M_A_DQSP2
M_A_DQSP3

M_A_DQSN2
M_A_DQSN3

DDR4_DRAMRST#

M_A2_ZQ0

DDRA_ACT# DDRA_ACT# DDRA_ACT#DDRA_ACT#

U17

M1

VREFCA

B1

VPP

R9

VPP

P3

A0

P7

A1

R3

A2

N7

A3

N3

A4

P8

A5

P2

A6

R8

A7

R2

A8

R7

A9

M3

A10/AP

T2

A11

M7

A12/BC

T8

A13

L2

WE_n/A14

M8

CAS_n/A15

L8

RAS_n/A16

N2

BA0

N8

BA1

M2

BG0

K7

CK_t

K8

CK_c

K2

CKE

K3

ODT

L7

CS

G3

DQSL_t

B7

DQSU_t

F3

DQSL_c

A7

DQSU_c

E7

DML_n/DBIL_n

E2

DMU_n/DBIU_n

P1

RESET_n

F9

ZQ

N9

TEN

P9

ALERT_n

L3

ACT_n

T3

PAR

T7

NC

96-BALL
DDR4

MT40A512M16HA-083E:A

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B3

VDD#B9
VDD#D1
VDD#G7

VDD#J1

VDD#J9

VDD#L1

VDD#L9
VDD#R1

VDD#T9

VDDQ#A1

VDDQ#A9
VDDQ#C1
VDDQ#D9

VDDQ#F2

VDDQ#F8
VDDQ#G1
VDDQ#G9

VDDQ#J2

VDDQ#J8

VSS#B2
VSS#E1
VSS#E9
VSS#G8
VSS#K1
VSS#K9

VSS#M9

VSS#N1
VSS#T1

VSSQ#A2

VSSQ#A8

VSSQ#C9

VSSQ#D2

VSSQ#D8

VSSQ#E3

VSSQ#E8

VSSQ#F1

VSSQ#H1

VSSQ#H9

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

M_A_DQ18

F7

M_A_DQ17

H3

M_A_DQ22

H7

M_A_DQ20

H2

M_A_DQ23

H8

M_A_DQ21

J3

M_A_DQ19

J7

M_A_DQ25

A3

M_A_DQ31

B8

M_A_DQ24

C3

M_A_DQ26

C7

M_A_DQ28

C2

M_A_DQ27

C8

M_A_DQ29

D3

M_A_DQ30

D7

B3
B9
D1
G7
J1
J9
L1
L9
R1
T9

A1
A9
C1
D9
F2
F8
G1
G9
J2
J8

B2
E1
E9
G8
K1
K9
M9
N1
T1

A2
A8
C9
D2
D8
E3
E8
F1
H1
H9

+1.2V_SUS

M_A_DQSP5{3}

M_A_DQSN5{3}
M_A_DQSN4{3}

M_A_DQ16

G2

+SMDDR_VREF_DIMM

+2.5V_SUS

R376 240/F_4

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13

M_A_WE#
M_A_CAS#
M_A_RAS#

M_A_BS#0
M_A_BS#1

M_A_CLKP0
M_A_CLKN0
M_A_CKE0

M_A_ODT0
M_A_CS#0

M_A_DQSP5
M_A_DQSP4

M_A_DQSN5
M_A_DQSN4

DDR4_DRAMRST#

M_A3_ZQ0

U18

M1

VREFCA

B1

VPP

R9

VPP

P3

A0

P7

A1

R3

A2

N7

A3

N3

A4

P8

A5

P2

A6

R8

A7

R2

A8

R7

A9

M3

A10/AP

T2

A11

M7

A12/BC

T8

A13

L2

WE_n/A14

M8

CAS_n/A15

L8

RAS_n/A16

N2

BA0

N8

BA1

M2

BG0

K7

CK_t

K8

CK_c

K2

CKE

K3

ODT

L7

CS

G3

DQSL_t

B7

DQSU_t

F3

DQSL_c

A7

DQSU_c

E7

DML_n/DBIL_n

E2

DMU_n/DBIU_n

P1

RESET_n

F9

ZQ

N9

TEN

P9

ALERT_n

L3

ACT_n

T3

PAR

T7

NC

96-BALL
DDR4

MT40A512M16HA-083E:A

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B3
VDD#B9
VDD#D1

VDD#G7

VDD#J1

VDD#J9
VDD#L1
VDD#L9
VDD#R1
VDD#T9

VDDQ#A1
VDDQ#A9
VDDQ#C1
VDDQ#D9
VDDQ#F2
VDDQ#F8
VDDQ#G1
VDDQ#G9

VDDQ#J2
VDDQ#J8

VSS#B2

VSS#E1

VSS#E9

VSS#G8
VSS#K1
VSS#K9
VSS#M9
VSS#N1

VSS#T1

VSSQ#A2
VSSQ#A8
VSSQ#C9
VSSQ#D2
VSSQ#D8
VSSQ#E3
VSSQ#E8

VSSQ#F1
VSSQ#H1
VSSQ#H9

M_A_DQ45

G2

M_A_DQ43

F7

M_A_DQ41

H3

M_A_DQ47

H7

M_A_DQ44

H2

M_A_DQ46

H8

M_A_DQ40

J3

M_A_DQ42

J7

M_A_DQ36

A3

M_A_DQ34

B8

M_A_DQ37

C3

M_A_DQ38

C7

M_A_DQ33

C2

M_A_DQ39

C8

M_A_DQ32

D3

M_A_DQ35

D7

B3
B9
D1
G7
J1
J9
L1
L9
R1
T9

A1
A9
C1
D9
F2
F8
G1
G9
J2
J8

B2
E1
E9
G8
K1
K9
M9
N1
T1

A2
A8
C9
D2
D8
E3
E8
F1
H1
H9

+1.2V_SUS

M_A_DQSP0{3}M_A_DQSP2{3}
M_A_DQSP1{3}

M_A_DQSN0{3}
M_A_DQSN1{3}

+SMDDR_VREF_DIMM

+2.5V_SUS

+1.2V_SUS+1.2V_SUS+1.2V_SUS+1.2V_SUS

R375 240/F_4

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13

M_A_WE#
M_A_CAS#
M_A_RAS#

M_A_BS#0
M_A_BS#1

M_A_CLKP0
M_A_CLKN0
M_A_CKE0

M_A_ODT0
M_A_CS#0

M_A_DQSP0
M_A_DQSP1

M_A_DQSN0
M_A_DQSN1

DDR4_DRAMRST#

M_A4_ZQ0

U16

M1

VREFCA

B1

VPP

R9

VPP

P3

A0

P7

A1

R3

A2

N7

A3

N3

A4

P8

A5

P2

A6

R8

A7

R2

A8

R7

A9

M3

A10/AP

T2

A11

M7

A12/BC

T8

A13

L2

WE_n/A14

M8

CAS_n/A15

L8

RAS_n/A16

N2

BA0

N8

BA1

M2

BG0

K7

CK_t

K8

CK_c

K2

CKE

K3

ODT

L7

CS

G3

DQSL_t

B7

DQSU_t

F3

DQSL_c

A7

DQSU_c

E7

DML_n/DBIL_n

E2

DMU_n/DBIU_n

P1

RESET_n

F9

ZQ

N9

TEN

P9

ALERT_n

L3

ACT_n

T3

PAR

T7

NC

96-BALL
DDR4

MT40A512M16HA-083E:A

BYTE2_16-23
BYTE3_24-31

G2

DQL0

F7

DQL1

H3

DQL2

H7

DQL3

H2

DQL4

H8

DQL5

J3

DQL6

J7

DQL7

A3

DQU0

B8

DQU1

C3

DQU2

C7

DQU3

C2

DQU4

C8

DQU5

D3

DQU6

D7

DQU7

B3

VDD#B3

B9

VDD#B9

D1

VDD#D1

G7

VDD#G7

J1

VDD#J1

J9

VDD#J9

L1

VDD#L1

L9

VDD#L9

R1

VDD#R1

T9

VDD#T9

A1

VDDQ#A1

A9

VDDQ#A9

C1

VDDQ#C1

D9

VDDQ#D9

F2

VDDQ#F2

F8

VDDQ#F8

G1

VDDQ#G1

G9

VDDQ#G9

J2

VDDQ#J2

J8

VDDQ#J8

B2

VSS#B2

E1

VSS#E1

E9

VSS#E9

G8

VSS#G8

K1

VSS#K1

K9

VSS#K9

M9

VSS#M9

N1

VSS#N1

T1

VSS#T1

A2

VSSQ#A2

A8

VSSQ#A8

C9

VSSQ#C9

D2

VSSQ#D2

D8

VSSQ#D8

E3

VSSQ#E3

E8

VSSQ#E8

F1

VSSQ#F1

H1

VSSQ#H1

H9

VSSQ#H9

M_A_DQ5
M_A_DQ3
M_A_DQ0
M_A_DQ6
M_A_DQ4
M_A_DQ7
M_A_DQ1
M_A_DQ2

M_A_DQ13
M_A_DQ15
M_A_DQ8
M_A_DQ14
M_A_DQ12
M_A_DQ10
M_A_DQ9
M_A_DQ11

+1.2V_SUS

+0.6V_DDR_VTT

+DDR_VTT_RUN_AM_A_A0

4

+0.6V_DDR_VTT

M_A_CLKN0M_A_CLKP0

+1.2V_SUS

R413

49.9/F_4

DDR4_DRAMRST#

0.01U/50V/X7R_4

M_A_BS#0

R393 36/F_4

M_A_BS#1

R396 36/F_4

M_A_BG#0

R391 36/F_4

M_A_CKE0

R364 36/F_4

M_A_CS#0

R369 36/F_4
R397 36/F_4

M_A_A1

R402 36/F_4

M_A_A2

R415 36/F_4

M_A_A3

R388 36/F_4

M_A_A4

R384 36/F_4

M_A_A5

R409 36/F_4

M_A_A6

R405 36/F_4

M_A_A7

R416 36/F_4

M_A_A8

R420 36/F_4

M_A_A9

R414 36/F_4

M_A_A10

R385 36/F_4

M_A_A11

5

M_A_A12
M_A_A13

M_A_WE#
M_A_CAS#
M_A_RAS#

M_A_ODT0
DDR0_PAR
DDRA_ACT#

R424 36/F_4
R387 36/F_4
R426 36/F_4
R370 36/F_4
R389 36/F_4
R373 36/F_4
R363 36/F_4
R411 36/F_4
R367 36/F_4

A A

M_A_CLKP0
M_A_CLKN0

1023 change cap from

0.2pF to 3.3pF

R362 36/F_4
R361 36/F_4

C477 3.3p/50V_4

DDR0_ALERT#

C529 *0.1U/16V/X7R_4

Place these Caps near Channel A

+1.2V_SUS

C487 1U/6.3V_4X
C481 1U/6.3V_4X
C478 1U/6.3V_4X
C488 1U/6.3V_4X
C506 1U/6.3V_4X
C482 1U/6.3V_4X
C504 1U/6.3V_4X
C503 1U/6.3V_4X
C480 10U/6.3V/X5R_6X

C502 10U/6.3V/X5R_6X
C492 10U/6.3V/X5R_6X

C501 10U/6.3V/X5R_6X
C510 10U/6.3V/X5R_6X

C505 10U/6.3V/X5R_6X
C483 10U/6.3V/X5R_6X

C484 10U/6.3V/X5R_6X

+0.6V_DDR_VTT

EC28 E @120P/50V_4N
EC29 E @120P/50V_4N

+0.6V_DDR_VTT

+SMDDR_VREF_DIMM

+1.2V_SUS

3

C516 1U/6.3V_4X
C530 1U/6.3V_4XC479
C522 1U/6.3V_4X
C531 1U/6.3V_4X
C514 10U/6.3V/X5R_6X

C511 *0.1U/16V/X7R_4
C494 *2.2U/6.3V_4

EC22 E @120P/50V_4N
EC23 E @120P/50V_4N
EC26 E @120P/50V_4N
EC20 E @120P/50V_4N
EC25 E @120P/50V_4N
EC27 E @120P/50V_4N
EC24 E @120P/50V_4N
EC21 E @120P/50V_4N

+2.5V_SUS

C528 1U/6.3V_4X
C533 1U/6.3V_4X
C527 10U/6.3V_4
C526 10U/6.3V_4

+1.2V_SUS

R371

1.8K/F_4

SM_VREF_CA{3}

2

R372 2.7/F_6

C486

0.022U/16V/X7R_4

2 1

R366

24.9/F_4

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

DDR4 MEMORY DOWN

DDR4 MEMORY DOWN

DDR4 MEMORY DOWN

Date: Sheet of

Date: Sheet of

Date: Sheet of

+SMDDR_VREF_DIMM

R382

1.8K/F_4

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

1

LV6

LV6

LV6

16 61Friday, March 11, 2016

16 61Friday, March 11, 2016

16 61Friday, March 11, 2016

1A

1A

1A

5

<DDR>

D D

C C

B B

A A

(STD)

+3V

R359

R352

R351
*10K_4

CHB_SA0 CHB_SA1 CHB_SA2

R350
10K_4

DDR4 SODIMM ODT GENERATION

DDR_PG_CTRL{3}

10K_4

R353
*10K_4

1.2V Level

*10K_4

R360
10K_4

R686 *0_4_S

5

DDR4_DRAMRST#{3,16}

M_B_ODT0_CPU{3}
M_B_ODT1_CPU{3}

SMB_RUN_CLK{10,27}

SMB_RUN_DAT{10,27}

M_B_A[13:0]{3}

M_B_WE#{3}
M_B_CAS#{3}
M_B_RAS#{3}

M_B_ACT#{3}
M_B_PARITY{3}
M_B_ALERT#{3}

M_B_BA#0{3}
M_B_BA#1{3}
M_B_BG#0{3}
M_B_BG#1{3}

M_B_CS#0{3}
M_B_CS#1{3}
M_B_CKE0{3}
M_B_CKE1{3}

M_B_CLKP0{3}
M_B_CLKN0{3}
M_B_CLKP1{3}
M_B_CLKN1{3}

+1.2V_SUS

+1.2V_SUS

NC1VCC

2

A

GND3Y

74AUP1G07GW

TP25
TP24

+1.2V_SUS

U45

(to power on VTT)

R341 240/F_4

+1.2V_SUS

5

12

4

R344 240/F_4
R333 240/F_4
R346 240/F_4
R347 240/F_4
R345 240/F_4
R332 240/F_4
R348 240/F_4
R349 240/F_4

+3V_DEEP_SUS

C771

0.1U/16V/X7R_4

R708

*2M_4

R707
10K_4

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13

M_B_EVENT#

M_B_EVENT#

CHB_SA0
CHB_SA1
CHB_SA2

M_B_CB0
M_B_CB1
M_B_CB2
M_B_CB3
M_B_CB4
M_B_CB5
M_B_CB6
M_B_CB7

4

144
133
132
131
128
126
127
122
125
121
146
120
119
158
151
156
152

162
165

114
143
116
134
108

150
145
115
113

149
157
109
110

137
139
138
140

155
161

253
254

256
260
166

92

91
101
105

88

87
100
104

12

33

54

75
178
199
220
241

96

SM_VREF_DQ1{3}

DDR_PG {50}

4

CON1A

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14/WE#
A15/CAS#
A16/RAS#

S2#/C0
S3#/C1

ACT#
PARITY
ALERT#
EVENT#
RESET#

BA0
BA1
BG0
BG1

S0#
S1#
CKE0
CKE1

CK0
CK0#
CK1
CK1#

ODT0
ODT1

SCL
SDA

SA0
SA1
SA2

CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8

8

DQ0

7

DQ1

20

DQ2

21

DQ3

4

DQ4

3

DQ5

16

DQ6

17

DQ7

28

DQ8

29

DQ9

41

DQ10

42

DQ11

24

DQ12

25

DQ13

38

DQ14

37

DQ15

50

DQ16

49

DQ17

62

DQ18

63

DQ19

46

DQ20

45

DQ21

58

DQ22

59

DQ23

70

DQ24

71

DQ25

83

DQ26

84

DQ27

66

DQ28

67

DQ29

79

DQ30

80

DQ31

174

DQ32

173

DQ33

187

DQ34

186

DQ35

170

DQ36

169

DQ37

183

DQ38

182

DQ39

195

DQ40

194

DQ41

207

DQ42

208

DQ43

191

DQ44

190

DQ45

203

DQ46

204

DQ47

216

DQ48

(260P)

215

DDR4 SODIMM 260 PIN

DQ49

228

DQ50

229

DQ51

211

DQ52

212

DQ53

224

DQ54

225

DQ55

237

DQ56

236

DQ57

249

DQ58

250

DQ59

232

DQ60

233

DQ61

245

DQ62

246

DQ63

13

DQS0

34

DQS1

55

DQS2

76

DQS3

179

DQS4

200

DQS5

221

DQS6

242

DQS7

97

DQS8

11

DQS#0

32

DQS#1

53

DQS#2

74

DQS#3

177

DQS#4

198

DQS#5

219

DQS#6

240

DQS#7

95

DQS#8

VREF CA DIMM1 Solution

R357
*0_4_S

R356 2/F _4

C455

0.022U/16V/X7R_4

1 2

R343

24.9/F_4

M_B_DQ12
M_B_DQ8
M_B_DQ11
M_B_DQ15
M_B_DQ13
M_B_DQ9
M_B_DQ10
M_B_DQ14
M_B_DQ1
M_B_DQ4
M_B_DQ7
M_B_DQ2
M_B_DQ0
M_B_DQ5
M_B_DQ3
M_B_DQ6
M_B_DQ21
M_B_DQ19
M_B_DQ23
M_B_DQ17
M_B_DQ16
M_B_DQ20
M_B_DQ22
M_B_DQ18
M_B_DQ24
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ25
M_B_DQ28
M_B_DQ26
M_B_DQ27
M_B_DQ33
M_B_DQ32
M_B_DQ34
M_B_DQ35
M_B_DQ37
M_B_DQ36
M_B_DQ39
M_B_DQ38
M_B_DQ41
M_B_DQ40
M_B_DQ42
M_B_DQ47
M_B_DQ44
M_B_DQ45
M_B_DQ43
M_B_DQ46
M_B_DQ48
M_B_DQ53
M_B_DQ54
M_B_DQ50
M_B_DQ52
M_B_DQ49
M_B_DQ51
M_B_DQ55
M_B_DQ56
M_B_DQ61
M_B_DQ58
M_B_DQ63
M_B_DQ60
M_B_DQ57
M_B_DQ59
M_B_DQ62

M_B_DQSP1
M_B_DQSP0
M_B_DQSP2
M_B_DQSP3
M_B_DQSP4
M_B_DQSP5
M_B_DQSP6
M_B_DQSP7
M_B_DQSP8

M_B_DQSN1
M_B_DQSN0
M_B_DQSN2
M_B_DQSN3
M_B_DQSN4
M_B_DQSN5
M_B_DQSN6
M_B_DQSN7
M_B_DQSN8

+1.2V_SUS

1K/F_4

VREF_CA_DIMM1

R355
1K/F_4

3

M_B_DQ[63:0] {3}

M_B_DQSP[7:0] {3}

M_B_DQSN[7:0] {3}

+1.2V_SUS

3

+1.2V_SUS

R335

240/F_4

M_B_DQSP8

+1.2V_SUS

R334

240/F_4

M_B_DQSN8

EC19 *E@3.3P/50V/C0G_4
C442 1U/6.3V_4X
C441 1U/6.3V_4X
C458 1U/6.3V_4X
C463 1U/6.3V_4X
C443 10U/6.3V_4
C440 10U/6.3V_4
C444 10U/6.3V_4
C457 10U/6.3V_4
C449 E@100P/50V_4
C462 10U/6.3V_4
C439 E@100P/50V_4
C461 10U/6.3V_4
C459 10U/6.3V_4
C460 1U/6.3V_4X
C445 1U/6.3V_4X
C438 1U/6.3V_4X
C456 1U/6.3V_4X

2250mA

+1.2V_SUS

Place these Caps near So-Dimm1

+0.6V_DDR_VTT

C470 *3.3P/50V/C0G_4
C475 *10U/6.3V_4
C469 *10U/6.3V_4
C471 1U/6.3V_4X
C472 1U/6.3V_4XR354
C473 1U/6.3V_4X
C474 1U/6.3V_4X

VREF_CA_DIMM1

C464 *0.047U/10V_4
C466 0.1U/16V/X7R_4
C465 2.2U/6.3V/X5R_4

2

+1.2V_SUS{3,6,16,50}

+3V{2,4,10,11,12,13,14,15,18,25,26,27,29,30,31,34,36,37,38,40,41,42,45,49,52,53, 54}

+2.5V_SUS{16,50}
+0.6V_DDR_VTT{16,50}
+3V_DEEP_SUS{4,10,11,14,15}

CON1B

111

VDD1

112

VDD2

117

VDD3

118

VDD4

123

VDD5

124

VDD6

129

VDD7

130

VDD8

135

VDD9

136

VDD10

141

VDD11

142

VDD12

147

VDD13

148

VDD14

153

VDD15

154

VDD16

159

VDD17

160

VDD18

163

VDD19

1

VSS1

5

VSS2

9

VSS3

15

VSS4

19

VSS5

23

VSS6

27

VSS7

31

VSS8

35

VSS9

39

VSS10

43

VSS11

47

VSS12

51

VSS13

57

VSS14

61

VSS15

65

VSS16

69

VSS17

73

VSS18

77

VSS19

81

VSS20

85

VSS21

89

VSS22

93

VSS23

99

VSS24

103

VSS25

107

VSS26

167

VSS27

171

VSS28

175

VSS29

181

VSS30

185

VSS31

189

VSS32

193

VSS33

197

VSS34

201

VSS35

205

VSS36

209

VSS37

213

VSS38

217

VSS39

223

VSS40

227

VSS41

231

VSS42

235

VSS43

239

VSS44

243

VSS45

247

VSS46

251

VSS47

2

255

VDDSPD

257

VPP1

259

VPP2

258

VTT

164

VREF_CA

2

VSS48

6

VSS49

10

VSS50

14

VSS51

18

VSS52

22

VSS53

26

VSS54

30

VSS55

36

VSS56

40

VSS57

44

VSS58

48

VSS59

52

VSS60

56

VSS61

60

VSS62

64

VSS63

68

VSS64

72

VSS65

78

VSS66

82

VSS67

86

VSS68

90

(260P)

DDR4 SODIMM 260 PIN

VSS69

94

VSS70

98

VSS71

102

VSS72

106

VSS73

168

VSS74

172

VSS75

176

VSS76

180

VSS77

184

VSS78

188

VSS79

192

VSS80

196

VSS81

202

VSS82

206

VSS83

210

VSS84

214

VSS85

218

VSS86

222

VSS87

226

VSS88

230

VSS89

234

VSS90

238

VSS91

244

VSS92

248

VSS93

252

VSS94

261

GND

262

GND

VREF_CA_DIMM1

+2.5V_SUS

+3V

+3V

0.5A

+2.5V_SUS

600mA

+0.6V_DDR_VTT

C437 1U/6.3V_4X
C447 1U/6.3V_4X
C446 10U/6.3V_4
C448 10U/6.3V_4

EC18 *E@3.3P/50V/C0G_4
C450 0.1U/16V/X7R_4
C467 2.2U/6.3V/X5R_4

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

DDR4 DIMM1-RVS

DDR4 DIMM1-RVS

DDR4 DIMM1-RVS

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

17

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

LV6

LV6

LV6

17 61Friday, March 11, 2016

17 61Friday, March 11, 2016

1

17 61Friday, March 11, 2016

1A

1A

1A

U34A

18

PEG_TXP0{12}
PEG_TXN0{12}

PEG_TXP1{12}
PEG_TXN1{12}

PEG_TXP2{12}
PEG_TXN2{12}

PEG_TXP3{12}
PEG_TXN3{12}

CLK_PCIE_VGAP{13}
CLK_PCIE_VGAN{13}

R164 EV@1K_4

DGPU_HOLD_RST#{14}

PLTRST#{4,28,30,31,33,36,37}

PEG_TXP0
PEG_TXN0

PEG_TXP1
PEG_TXN1

PEG_TXP2
PEG_TXN2

PEG_TXP3
PEG_TXN3

TEST_PG

PERST#_BUF

C294 EV@100P/50V_4

AF30
AE31

AE29
AD28

AD30
AC31

AC29
AB28

AB30
AA31

AA29

Y28

Y30

W31

W29

V28

V30
U31

U29
T28

T30
R31

R29
P28

P30
N31

N29
M28

M30

L31

L29

K30

AK30
AK32

N10

AL27

+3V

C339 E@0.1U/16V/X7R_4

U8

2
1

EV@TC7SH08FU(F)

3 5

PCIE_RX0P
PCIE_RX0N

PCIE_RX1P
PCIE_RX1N

PCIE_RX2P
PCIE_RX2N

PCIE_RX3P
PCIE_RX3N

PCIE_RX4P
PCIE_RX4N

PCIE_RX5P
PCIE_RX5N

PCIE_RX6P
PCIE_RX6N

PCIE_RX7P
PCIE_RX7N

NC#V30
NC#U31

NC#U29
NC#T28

NC#T30
NC#R31

NC#R29
NC#P28

NC#P30
NC#N31

NC#N29
NC#M28

NC#M30
NC#L31

NC#L29
NC#K30

CLOCK

PCIE_REFCLKP
PCIE_REFCLKN

TEST_PG

PERSTB

EV@100-CG2633(216-0867030)

PERST#_BUF

4

PCI EXPRESS INTERFACE

PCIE_TX0P
PCIE_TX0N

PCIE_TX1P
PCIE_TX1N

PCIE_TX2P
PCIE_TX2N

PCIE_TX3P
PCIE_TX3N

PCIE_TX4P
PCIE_TX4N

PCIE_TX5P
PCIE_TX5N

PCIE_TX6P
PCIE_TX6N

PCIE_TX7P
PCIE_TX7N

NC#W24
NC#W23

NC#V27
NC#U26

NC#U24
NC#U23

NC#T26
NC#T27

NC#T24
NC#T23

NC#P27
NC#P26

NC#P24
NC#P23

NC#M27
NC#N26

CALIBRATION

PCIE_CALR_TX
PCIE_CALR_RX

R209
*EV@100K_4

AH30
AG31

AG29
AF28

AF27
AF26

AD27
AD26

AC25
AB25

Y23
Y24

AB27
AB26

Y27
Y26

W24
W23

V27
U26

U24
U23

T26
T27

T24
T23

P27
P26

P24
P23

M27
N26

Y22
AA22

C_PEG_RXP0
C_PEG_RXN0

C_PEG_RXP1
C_PEG_RXN1

C_PEG_RXP2
C_PEG_RXN2

C_PEG_RXP3
C_PEG_RXN3

SUN_PCIE_CALRP
SUN_PCIE_CALRN

SUSB#{4,36}

C716 EV@0.22U/10V_4X
C713 EV@0.22U/10V_4X

C712 EV@0.22U/10V_4X
C710 EV@0.22U/10V_4X

C699 EV@0.22U/10V_4X
C704 EV@0.22U/10V_4X

C707 EV@0.22U/10V_4X
C709 EV@0.22U/10V_4X

R162 EV@1.69K/F_4
R168 EV@1K/F_4

D7 *EV@DB2J40600L

+0.95V_VGA

C3A

R208 *EV@0_4

PEG_RXP0 {12}

PEG_RXN0 {12}

PEG_RXP1 {12}

PEG_RXN1 {12}

PEG_RXP2 {12}

PEG_RXN2 {12}

PEG_RXP3 {12}

PEG_RXN3 {12}

dGPU power enable

+3V

R214
*EV@1K_4

DGPU_PWR_EN

DGPU_PWR_EN {14,56}

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

PROJECT :

JET_S3_PCIE_Interface

JET_S3_PCIE_Interface

JET_S3_PCIE_Interface

LV6

LV6

LV6

18 61Friday, March 11, 2016

18 61Friday, March 11, 2016

18 61Friday, March 11, 2016

1A

1A

1A

The SMBus slave ID is default 0x41

+3V_VGA

R191
EV@47K_4

DGPUT_DATA

1

Q19A

+3V_VGA

R186
EV@47K_4

DGPUT_CLK

Q19B

PU/PD

R185

*EV@10K_4

R155

EV@1K_4

3

Q14
*EV@2N7002K

2

1

+3V_VGA

3

Q16

*EV@2N7002K

R623
EV@1M/F_4

C311
M1@10U/6.3V/X5R_6X

M1 MLPS setting
M2 no mount

M1 ONLY: stuff Ra=> disable MLPS

MBDATA_THRM{10,36,37,42}

MBCLK_THRM{10,36,37,42}

+3V_VGA

R184 EV@10K_4
R178 *EV@10K_4
R562 *EV@10K_4
R560 *EV@10K_4
R556 *EV@10K_4
R156 *EV@10K_4
R567 EV@10K_4
R171 EV@10K_4
R159 *EV@5.1K/F_4

R563
R561 *EV@10K_4

SYS_SHDN#{36,37,55}

PCIE_CLK_VGA_REQ#{13}

C728 EV@8.2P/50V_4

C717 EV@8.2P/50V_4

+3V_VGA

6

EV@2N7002KDW

+3V_VGA

3 4

EV@2N7002KDW

DGPU_OPP#
OCP_L
DGPU_TDI
DGPU_TMS
DGPU_TDO
DGPU_TRSTB
PEX_CLKREQ#
VGA_ALERT

TESTEN

EV@10K_4

TEMP_FAIL
DGPU_TCK

EVGA-XTALI

23

Y4
EV@27MHZ_10

4 1

EVGA-XTALO

L11 EV@HCB1608KF-121T20_2A

+1.8V_VGA

1.8V(5mA TSVDD)

2

5

DGPU_OPP{36}

EV@2N7002K

R179 *EV@1K/F_4

OCP_L{52}

2

1

Ra

R575 *M1@10K_4

+3V_VGA

Rb

R574 M1@10K_4

C271

M1@0.1U/16V/X7R_4

stuff Rb=> enable MLPS

DGPU_OPP#

DGPU_OPP

+1.8V_VGA

+3V_VGA

C264

*EV@0.1U/16V/X7R_4

PEX_CLKREQ#

C283
M2@1U/10V/X5R_4

3

Q17

2

1

R585 M2@10K_4
R584 M2@10K_4

R571 *EV@10K_4
R572 *EV@10K_4

DGPUT_DATA
DGPUT_CLK
DGPU_OPP#

GPU_GPIO6

GPU_GPIO15
VGA_ALERT
TEMP_FAIL

GPU_GPIO20

DGPU_TRSTB

DGPU_TDI
DGPU_TCK
DGPU_TMS
DGPU_TDO
TESTEN

TP5

R170 EV@10K_4
R165 EV@10K_4

GPU_THERMDA

TP32

GPU_THERMDC

TP33

GPU_GPIO28

+1.8V_TSVDD

D3A

EVGA-XTALI

EVGA-XTALO

U34B

DVO

N9

DBG_DATA16

L9

DBG_DATA15

AE9

DBG_DATA14

Y11

DBG_DATA13

AE8

DBG_DATA12

AD9

DBG_DATA11

AC10

DBG_DATA10

AD7

DBG_DATA9

AC8

DBG_DATA8

AC7

DBG_DATA7

AB9

DBG_DATA6

AB8

DBG_DATA5

AB7

DBG_DATA4

AB4

DBG_DATA3

AB2

DBG_DATA2

Y8

DBG_DATA1

Y7

DBG_DATA0

W6

NC#W6

V6

NC#V6

AC5

NC#AC5

AC6

N#CAC6

AA5

NC#AA5

AA6

NC#AA6

U1

NC#U1/BP_0

U3

NC#U3/BP_1

Y6

NC#Y6

R1

SCL

R3

SDA

GENERAL PURPOSE I/O

U6

GPIO_0

U8

SMBDATA

U7

SMBCLK

T9

GPIO_5_AC_BATT

T8

PCC/GPIO_6

T7

NC_GPIO_7

P10

GPIO_8_ROMSO

P4

GPIO_9_ROMSI

P2

GPIO_10_ROMSCK

N6

NC_GPIO_11

N5

NC_GPIO_12

N3

NC_GPIO_13

N1

GPIO_15_PWRCNTL_0

M4

GPIO_16

R6

GPIO_17_THERMAL_INT

M2

GPIO_19_CTF

P8

GPIO_20_PWRCNTL_1

P7

GPIO_21

N8

GPIO_22_ROMCSB

AK10

GPIO_29

AM10

GPIO_30

N7

CLKREQB

L6

JTAG_TRSTB

L5

JTAG_TDI

L3

JTAG_TCK

L1

JTAG_TMS

K4

JTAG_TDO

K7

TESTEN

AF24

NC#AF24

W8

NC_GENERICB

W7

NC_GENERICD

AD10

NC_GENERICE_HPD4

AJ9

NC#AJ9

AL9

DBG_CNTL0

AB16

PX_EN

AC16

NC_DBG_VREFG

PLL/CLOCK

AM28

XTALIN

AK28

XTALOUT

AC22

XO_IN

AB22

XO_IN2

T4

DPLUS

T2

DMINUS

R5

GPIO28_FDO

AD17

TSVDD

AC17

TSVSS

EV@100-CG2633(216-0867030)

I2C

THERMAL

NC#AF2
NC#AF4

NC#AG3

DPA

NC#AG5
NC#AH3

NC#AH1
NC#AK3

NC#AK1
NC#AK5

NC#AM3
NC#AK6

NC#AM5

DPB

NC#AJ7
NC#AH6

NC#AK8
NC#AL7

DPC

NC#V4
NC#U5

NC#V2
NC#Y4

NC#W5

NC#Y2

NC#J8

NC#AA1/PLL_ANALOG_IN

NC#AA3/PLL_ANALOG_OUT

DCM/NC_R

NC_AVSSN#AK26

NC_G

NC_AVSSN#AJ25

NC_B

NC_AVSSN#AG25

DAC1

NC_HSYNC

NC_VSYNC/WAKEb

NC_RSET

NC_AVDD

NC_AVSSQ

NC_VDD1DI

NC_VSS1DI

NC_SVI2#1/GPIO_SVD

NC_SVI2#2/GPIO_SVT

NC_SVI2#3/GPIO_SVC

NC_GENLK_CLK

NC_GENLK_VSYNC

DAC2

NC_SWAPLOCKA

NC_SWAPLOCKB

DDC/AUX

NC_DDC1CLK

NC_DDC1DATA

NC_AUX1P

NC_AUX1N

NC_AUX2P

NC_AUX2N

NC#AE16
NC#AD16

NC_DDCVGACLK

NC_DDCVGADATA

U34G

AG15

NC_DP_VDDR#1

AG16
AF2
AF4

AG3
AG5

AH3
AH1

AK3
AK1

AK5
AM3

AK6
AM5

AJ7
AH6

AK8
AL7

V4
U5

V2
Y4

W5

Y2
J8

AA1
AA3

AM26
AK26

AL25
AJ25

AH24
AG25

AH26
AJ27

AD22
AG24

AE22
AE23

AD23

AM12

NC

AK12
AL11
AJ11

AL13
AJ13

AG13
AH12

AC19

PS_0

AD19

PS_1

AE17

PS_2

AE20

PS_3

AE19

TS_A

AE6
AE5

AD2
AD4

AD13
AD11

AE16
AD16

AC1
AC3

+0.95V_VGA

TP41

R604
M2@16.2K/F_4

PLL_ANALOG_OUT: Provide a pull-down
resistor on the PCB (DNI).FOR TOPAZ ONLY

+3V_VGA

R644
*M2@10K_4

PCIE_WAKE#_GPU

R616 M2@0_4
R621 M2@0_4

PS_0
PS_1
PS_2
PS_3

R630
*EV@0_4

+1.8V_VGA +1.8V_VGA

TP43
TP42

+1.8V_VGA

Q20

PCIE_WAKE#

3

*EV@2N7002K

+1.8V_VGA

+3V_VGA

C284
EV@1U/10V/X5R_4

C259
EV@0.1U/16V/X7R_4

+1.8V_VGA

C230
M1@0.1U/16V/X7R_4

C258
M1@0.1U/16V/X7R_4

1

GPU_SVD_R
GPU_SVT
GPU_SVC_R

C300
EV@10U/6.3V/X5R_6X

C272
EV@1U/10V/X5R_4

2

C265
M1@0.1U/16V/X7R_4

C664
M1@10U/10V_8X

PCIeR Optimized Buffer Flush/Fill (OBFF)
on WAKEB FOR TOPAZ ONLY

R645
EV@4.7K_4

R639
*EV@10K_4

R16M-M2-50R16M-M1-30
PS0[5:1] 11001
PS1[5:1]
PS2[5:1]
PS3[5:1]

R641
EV@8.45K/F_4

PS_0 PS_1

R640
EV@2K/F_4

11001
11001
11000
11xxx

C733

*EV@0.082U/16V_4X

11001

11000

11xxx

NC_DP_VDDR#2

AF16

NC_DP_VDDR#3

AG17

NC_DP_VDDR#4

AG18

NC_DP_VDDR#5

AG19

NC_DP_VDDR#6

AF14

DP_PVDD

AG20

NC_DP_VDDC#1

AG21

NC_DP_VDDC#2

AF22

NC_DP_VDDC#3

AG22

NC_DP_VDDC#4

AD14

DP_VDDC

AG14

NC_DP_VSSR#1

AH14

NC_DP_VSSR#2

AM14

NC_DP_VSSR#3

AM16

NC_DP_VSSR#4

AM18

NC_DP_VSSR#5

AF23

NC_DP_VSSR#6

AG23

NC_DP_VSSR#7

AM20

NC_DP_VSSR#8

AM22

NC_DP_VSSR#9

AM24

NC_DP_VSSR#10

AF19

NC_DP_VSSR#11

AF20

NC_DP_VSSR#12

AE14

DP_VSSR

AF17

NC_UPHYAB_DP_CALR

EV@100-CG2633(216-0867030)

PCIE_WAKE# {4,30,33}

R610
*M2@10K_4

R605
M2@10K_4

SVC SVD

0 0

001

1

1 1

R197
M2@10K_4

GPU_SVD_R

GPU_SVC_R

R193
*M2@10K_4

PS_3[3:1]

011

100 Hynix- 2G 256Mx16 *4, 900Mhz H5TC4G63CFR-N0C 4.53K 4.99K

101

R638
EV@8.45K/F_4

R637
EV@2K/F_4

GPU_SVT

C730
*EV@0.01U/50V_4X

NC/DP POWERDP POWER

AE11

NC#AE11

AF11

NC#AF11

AE13

NC#AE13

AF13

NC#AF13

AG8

NC#AG8

AG10

NC#AG10

AF6

NC#AF6

AF7

NC#AF7

AF8

NC#AF8

AF9

NC#AF9

AE1

NC#AE1

AE3

NC#AE3

AG1

NC#AG1

AG6

NC#AG6

AH5

NC#AH5

AF10

NC#AF10

AG9

NC#AG9

AH8

NC#AH8

AM6

NC#AM6

AM8

NC#AM8

AG7

NC#AG7

AG11

NC#AG11

AE10

NC#AE10

Output Voltage

1.1 Volts

1.0 Volts

0.9 Volts

R16M Boot

0.8 Volts

Level Shift

+3V_VGA

R573

R166

*M1@10K_4

M1@10K_4

GPU_GPIO15

GPU_GPIO20

R172

R566
M1@10K_4

*M1@10K_4

R622 *M2@SHORT_4

GPU_SVD_R
GPU_SVC_R

GPU_SVT_R {52}
GPU_SVD_R {52}
GPU_SVC_R {52}

Vendor Type Vendor P/N

Samsung- 2G

Micro- 2G

256Mx16 *4, 900Mhz

256Mx16 *4, 900Mhz

+1.8V_VGA

R629
*EV@0_4

PS_2

R628
EV@4.75K/F_4

+1.8V_VGA

GPU_SVD_R

+1.8V_VGA

GPU_SVC_R

C725
*EV@0.082U/16V_4X

1

VCCA

3

A

2

GND

M1@G2129TL1U

1

VCCA

3

A

2

GND

M1@G2129TL1U

K4W4G1646E-BC1A

VCCB

VCCB

B

OE

B

OE

U37

6

4

5

U7

6

4

5

19

+3V_VGA

GPU_GPIO15

R607 M1@10K_4

+3V_VGA

GPU_GPIO20

R3pu R3pd

6.98K 4.99K

3.24K 5.62KMT41J256M16LY-091G:N

00

01

10

11

+1.8V_VGA

C ( nF)BIT[5:4]

680

82

10

NC

Rpu RpdBIT[3:1]

000

+1.8V_VGA +1.8V_VGA

R210
S2G@6.98K/F_4

PS_3 PS_3

R204
S2G@4.99K/F_4

R213
M2G@3.24K/F_4

R206
M2G@5.62K/F_4

C282
*EV@680P/50V_4X

+1.8V_VGA

R219
H2G@4.53K/F_4

PS_3

R224
H2G@4.99K/F_4

NC 4750

001

8450 2000

010

4530 2000

011

6980 4990

100

4530 4990

101

3240 5620

110

3400 10000

111

4750 NC

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

PROJECT :

JET_S3_Main/DP PWR/Strap

JET_S3_Main/DP PWR/Strap

JET_S3_Main/DP PWR/Strap

LV6

LV6

LV6

19 61Friday, March 11, 2016

19 61Friday, March 11, 2016

19 61Friday, March 11, 2016

1A

1A

1A