Lenovo U460 Schematics

1 1

Compal Confidential

NIMUA/UB

2 2

Schematics Document

Arrandale

with Intel IBEX PEAK-M core logic

3 3

REV:0.3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

2010/01/13 2011/01/13

Compal Secret Data

Deciphered Date

Compal Electronics,Ltd.

Title

Cover Sheet

Size Document Num ber Rev

Custom

LA-5941P

Date: Sheet of

1 50Thursday, April 08, 2010

0.3

Compal confidential

File Name :

ZZZ

14.1W_PCB_LA5941P

DAZ0D500102

1 1

VRAM 64*16

DDR3*4

page20

PCI-E X16

Intel Arrandale (UMA/SG)

NVidia N11M-LP1

page19~23

level shift IC HDMI CONN

page24

CRT Connector

page26

2 2

LVDS Connector

page27

ASM1442

page25

SW1

SW2

100MHz

2.7GT/s

PCI Express Mini card Slot 2

page28

6*PCI-E BUS

Socket-rPGA989

37.5mm*37.5mm

page5~9

FDI *8

DMI *4

Intel Ibex Peak M

FCBGA 951

25mm*25mm

Thermal-sensor EMC1403

Clock Generator

SLG8LV597VTR

Dual Channel

DDR3-800(1.5V) DDR3-1067(1.5V)

AZALIA

14*USB2.0

page38

page12

DDR3-SO-DIMM X2

BANK 0, 1, 2, 3

Audio Codec

ALC259

CMOS Camera

POWER BD: LS-5941P POWER BT

SW BD: LS-5942P NOVO BT

UP TO 8G

page33

page 10,11

2Channel Speaker

DMIC_Int

Audio Jack CONN.

page27

CR BD: LS-5944P

Body-Detect BD: LS-5947P

Finger Print BD: LS-5943P U-pek TCS5D

page33

page37

USB(WLAN)

PCI Express Mini card Slot 3

3 3

page28

SPI ROM BIOS+ME

Atheros 8131/32

SIM Card

page28

USB(WWAN)

CAP SENSOR BD:

4 4

LS-5946P USER/SG MUTE Power Saving BUTTON & LED

10/100/1G LAN

RJ45 CONN

page30

USB/JACK BD: LS-5945P USB PORT1,2,3 HP JACK MIC JACK KILL SW

SPI

page29

page13

Touch Pad

page35

G-sensor

page38

page 13~18

LPC BUS

ENE KB926E0

page34

Int.KBD

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

SPI ROM EC

6*SATA serial

BlueTooth CONN

USB1 CONN.

USB2 CONN

USB3 CONN

WWAN/3G

page35

ESATA AND USB CONN

page36

SATA HDD CONN

Mini card Slot 1

SSD

Compal Secret Data

2010/01/13 2011/01/13

Compal Secret Data

Deciphered Date

page37

page32

page28

page37

page28

Card Reader CONN

page38

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

MB Block Diagram

LA-5941P

2 50Thursday, April 08, 2010

0.3

DDR3 Voltage Rails

SMBUS Control Table

+5VS

+3VS

+1.5VS

plane

1 1

State

+5VALW

+3VALW

+1.5V

+VCCPpower

+CPU_CORE

+VGA_CORE

+1.8VS

+0.75VS

+1.05VS

For SG

+3VS_DELAY

+1.8VS_VGA

+1.5VS_VGA

SMB_EC_CK1

SMB_EC_DA1

SMB_EC_CK2

SMB_EC_DA2

SMBCLK

SMBDATA

SML0CLK

SML0DATA

SML1CLK

SML1DATA

SOURCE

KB926

+3VALW

KB926

+3VALW

PCH

+3VALW

PCH

+3VALW

PCH

+3VALW

RAM M2

X V

+3VALW

BATT KB926 SODIMM CLK CHIP

+3VALW

V V

+3VS

WLAN WWAN

N11x Thermal Sensor

+3VS

Cap sensor

EMC1403

board

+3VS

XX X X X X X

ALS

+3VS

PCH

+3VALW

2 2

S5 S4/AC

S5 S4/ Bat tery only

S5 S4/AC & Battery don't exis t

X X

X X X

@ FUNCTION

PVT NON-USE

45@

(45 BOM) 100@ 10/100 LAN GIGA@

UMA_HDMI@

HDMI@

3 3

3G@ X76@ ESATA@ CMOS@

GIGA LAN

FOR UMA HDMI components

FOR HDMI components

3G(WWAN) function

(X76 BOM)

ESATA function

Camera function SSD@ SSD w/ miniPCIE socket 10M@ 11M@ UMA@ DIS@

FOR 10M CHIP

FOR 11M CHIP

UMA only (Arranddale)

DIS only (Arranddale) VGA@ FOR NVIDIA PART

HYBRID@ FOR SWITCHABLE

HU@ HD@

SWITCHABLE or UMA only

SWITCHABLE or DIS only

SKU

PCH, I2C / SMBUS ADDRESSING

DEVICE

DDR SO-DIMM 0

DDR SO-DIMM 1

CLOCK GENERATOR (EXT.)

HEX

ADDRESS

1 0 1 0 0 0 0 0

1 0 1 0 0 1 0 0A4

1 1 0 1 0 0 1 0

PCIE PORT LIST

NEW CARD

1 2

LAN

4 5 6 7 8

SATA PORT LIST

HDD

0 1

SSD

HM55 disabled

2,3 4

E-SATA

DEVICEPORT

EC, I2C / SMBUS ADDRESSING

DEVICE

PCH

EMC1403 Thermal sensor

N-vidia Thermal sensor

ALS

HEX

96/98,R/W

9A 1 0 0 1 1 0 1 X

70/72,R/W

USB PORT LIST

DEVICEPORT

USB 10

1WLAN

USB/ESATA CMOS

2 3

USB 2 4 5

CARD READER 6 7

9 10 11 12 13

HM55 disabled

WIRELESS8

USB 3

FigerPrinter

ADDRESS

1 0 0 1 0 1 1 X

1 0 0 1 1 1 1 X

0 1 1 1 0 0 0 X 0 1 1 1 0 0 1 X

1 0 0 1 1 0 0 X

Arrandale(dGPU)

4 4

DIS only

Arrandale(iGPU)

UMA only

Arrandale(iGPU+dGPU)

SWITCHABLE

DIS@ / 100@ for EVT

UMA@ / 100@ for EVT

HYBRID@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/01/13 2011/01/13

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

MB Notes List

LA-5941P

3 50Thursday, April 08, 2010

0.3

VGA and DDR3 Voltage Rails (N11M GPIO)

GPIO I/O ACTIVE Function Description

GPIO0

GPIO1

GPIO2

1 1

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

GPIO8

GPIO9

GPIO10

GPIO11

GPIO12

GPIO13

2 2

GPIO14

GPIO15

GPIO16

GPIO17

GPIO18

GPIO19

GPIO20

GPIO21

GPIO22

GPIO23

3 3

N/A

OUT

I/O

OUT

I/O

OUT

I/O

N/A

HDMI_DETECT_VGA

NV_INVTPWM

VGA_ENVDD_R

VGA_ENABLT

GPU VID0

GPU VID1

Power Sequence

(+3VS)

(1.05VS)

(+VGA_CORE)

VDD33

PEX_VDD

NVVDD

(1.8VS)IFPAB_IOVDD

(1.5VS)

FBVDDQ

The ramp time for any rail must be more than 40us

PEX_VDD can ramp up any time

tNVVDD

tNV-IFPAB_IOVDD

tNV-FBVDDQ

GPIO6GPIO5

Device ID

N11M-LP1 (40nm)

0x0A6E

4 4

VGA_COREGPU_VID00GPU_VID1

0.8V

0.85V

0.86V

P-State

Deep P12

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/01/13 2011/01/13

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

VGA Notes List

LA-5941P

4 50Thursday, April 08, 2010

0.3

D D

C C

VCCP_POK46

FROM POWER VTT POWER GOOD SIGNAL

B B

R184

1K_0402_1%

Layout rule：10mil width trace length < 0.5", spacing 20mil

+VCCP

H_PROCHOT#34,48

H_THERMTRIP#16

+VCCP

H_PM_SYNC15

H_CPUPWRGD16

PM_DRAM_PWRGD15

R183

R183 560_0402_5%

560_0402_5%

1 2

BUF_PLT_RST#16,28,29

R564 0_0402_5%R564 0_0402_5%

H_PECI16

+VCCP

SVT

1.5K_0402_5%

1 2

TP_SKTOCC#

R16349.9_0402_1% R16349.9_0402_1%

H_PECI_ISO

1 2

R569 68_0402_5%R569 68_0402_5%

H_PROCHOT#

H_THERMTRIP#

H_CPURST#_R

R13568_0402_5%

H_PM_SYNC_R

R187

1 2

0_0402_5%

VCCPWRGOOD_1

R190

1 2

0_0402_5%

VCCPWRGOOD_0

R139

1 2

0_0402_5%

VDDPWRGOOD_R

R191

1 2

0_0402_5%

R185

PLT_RST#_R

1 2

R56020_0402_1% R56020_0402_1%

R55820_0402_1% R55820_0402_1%

R54849.9_0402_1% R54849.9_0402_1%

R55749.9_0402_1% R55749.9_0402_1%

H_CATERR#

VTT_POK

R186

R186 750_0402_1%

750_0402_1%

COMP3

COMP2

COMP1

COMP0

JCPU1B

AT23

COMP3

AT24

COMP2

G16

COMP1

AT26

COMP0

AH24

SKTOCC#

AK14

CATERR#

AT15

PECI

AN26

PROCHOT#

AK15

THERMTRIP#

AP26

RESET_OBS#

AL15

PM_SYNC

AN14

VCCPWRGOOD_1

AN27

VCCPWRGOOD_0

AK13

SM_DRAMPWROK

AM15

VTTPWRGOOD

AM26

TAPPWRGOOD

AL14

RSTIN#

IC,AUB_CFD_rPGA,R1P0

ME@

CLK_CPU_BCLK

MISC THERMAL

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

CLOCKS

SM_DRAMRST#

SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]

PM_EXT_TS#[0] PM_EXT_TS#[1]

DDR3

MISC

DDR3

MISC

PWR MANAGEMENT

JTAG & BPM

BCLK

BCLK#

BCLK_ITP

BCLK_ITP#

PEG_CLK

PEG_CLK#

PRDY# PREQ#

TRST#

TDI_M

TDO_M

DBR#

BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]

A16 B16

AR30 AT30

E16 D16

A18 A17

AL1 AM1 AN1

AN15 AP15

AT28 AP27

AN28

TCK

AP28

TMS

AT27

AT29

TDI

AR27

TDO

AR29 AP29

AN25

AJ22 AK22 AK24 AJ24 AJ25 AH22 AK23 AH23

CLK_CPU_BCLK#

CLK_CPU_ITP CLK_CPU_ITP#

CLK_EXP CLK_EXP#

SM_DRAMRST#

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

PM_EXTTS#0 PM_EXTTS#1

XDP_PRDY# XDP_PREQ#

XDP_TCK XDP_TMS XDP_TRST#

XDP_TDI XDP_TDO

R555 0_0402_5%R555 0_0402_5%

XDP_DBRESET#

XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 XDP_BPM#5 XDP_BPM#6 XDP_BPM#7

T17 PADT17 PAD T18 PADT18 PAD

1 2

R563 0_0402_5%R563 0_0402_5%

T19 PADT19 PAD

CLK_CPU_BCLK 16 CLK_CPU_BCLK# 16

CLK_EXP 14 CLK_EXP# 14

only for Arrandale

without EDP

PM_EXTTS#1_R 10,11

DDR3 Compensation Signals

SM_RCOMP0

SM_RCOMP1

SM_RCOMP2

PM_EXTTS#0

PM_EXTTS#1

XDP_PREQ#

XDP_TMS

XDP_TDI

XDP_TDO

XDP_TCK

XDP_TRST#

XDP_DBRESET#

1 2

R567 100_0402_1%R567 100_0402_1%

1 2

R566 24.9_0402_1%R566 24.9_0402_1%

1 2

R565 130_0402_1%R565 130_0402_1%

Layout Note:Please these resistors near Processor

1 2

R561 10K_0402_5%R561 10K_0402_5%

1 2

R562 10K_0402_5%R562 10K_0402_5%

R136 51_0402_1%@R136 51_0402_1%@

1 2

R138 51_0402_1%@R138 51_0402_1%@

1 2

R556 51_0402_1%@R556 51_0402_1%@

1 2

R134 51_0402_5%R134 51_0402_5%

1 2

R57 51_0402_1%@R57 51_0402_1%@

1 2

R133 51_0402_5%R133 51_0402_5%

1 2

R137

1K_0402_5%@

1 2

+VCCP

+3VS

CHECK INTEL DOCUMENT #385422 Debug Port Design Guide Rev1.3

For Intel S3 Power Reduction.

+3VALW

VCCP_POK

+5VALW

A A

VCCP_POK

R416

R416 10K_0402_5%

10K_0402_5%

1 2

Q61

2N7002_SOT23

S3_0.75V_EN 44

NC7SZ08P5X_NL_SC70-5

R195

1 2

1.5K_0402_1%

750_0402_1%

+1.5V +1.5V

R193

1.1K_0402_1%

VDDPWRGOOD_RDRAM_PWRGD

R194

R192

R192 3K_0402_1%

3K_0402_1%

DDR3 CONNECTER

PCH GPIO CONTROL

DRAMRST_CNTRL_PCH16

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

For Intel S3 Power Reduction.

R301

R301 1K_0402_1%

1K_0402_1%

1 2

DRAMRST#10,11

DRAMRST_CNTRL_R

1 2

R281 0_0402_5%R281 0_0402_5%

Compal Secret Data

2010/01/13 2011/01/13

Compal Secret Data

1 2

R3000_0402_5%@R3000_0402_5%

DRAMRST# SM_DRAMRST#

1 3

Q27

2N7002_SOT23

Deciphered Date

C338

0.047U_0402_16V7K

R283 100K_0402_5%R283 100K_0402_5%

SVT

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Arrandale(1/5)-Thermal/XDP

LA-5941P

5 50Thursday, April 08, 2010

0.3

JCPU1A

DMI_CRX_PTX_N015 DMI_CRX_PTX_N115 DMI_CRX_PTX_N215 DMI_CRX_PTX_N315

DMI_CRX_PTX_P015 DMI_CRX_PTX_P115

D D

DMI_CRX_PTX_P215 DMI_CRX_PTX_P315

DMI_CTX_PRX_N015 DMI_CTX_PRX_N115 DMI_CTX_PRX_N215 DMI_CTX_PRX_N315

DMI_CTX_PRX_P015 DMI_CTX_PRX_P115 DMI_CTX_PRX_P215 DMI_CTX_PRX_P315

FDI_CTX_PRX_N015 FDI_CTX_PRX_N115 FDI_CTX_PRX_N215 FDI_CTX_PRX_N315 FDI_CTX_PRX_N415 FDI_CTX_PRX_N515 FDI_CTX_PRX_N615 FDI_CTX_PRX_N715

FDI_CTX_PRX_P015 FDI_CTX_PRX_P115 FDI_CTX_PRX_P215 FDI_CTX_PRX_P315 FDI_CTX_PRX_P415 FDI_CTX_PRX_P515

C C

FDI_CTX_PRX_P615 FDI_CTX_PRX_P715

FDI_FSYNC015 FDI_FSYNC115

FDI_INT15

FDI_LSYNC015 FDI_LSYNC115

B B

A A

FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7

FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7

FDI_FSYNC0 FDI_FSYNC1

FDI_INT

FDI_LSYNC0 FDI_LSYNC1

FDI_FSYNC0

FDI_FSYNC1

FDI_INT

FDI_LSYNC0

FDI_LSYNC1

A24

DMI_RX#[0]

C23

DMI_RX#[1]

B22

DMI_RX#[2]

A21

DMI_RX#[3]

B24

DMI_RX[0]

D23

DMI_RX[1]

B23

DMI_RX[2]

A22

DMI_RX[3]

D24

DMI_TX#[0]

G24

DMI_TX#[1]

F23

DMI_TX#[2]

H23

DMI_TX#[3]

D25

DMI_TX[0]

F24

DMI_TX[1]

E23

DMI_TX[2]

G23

DMI_TX[3]

E22

FDI_TX#[0]

D21

FDI_TX#[1]

D19

FDI_TX#[2]

D18

FDI_TX#[3]

G21

FDI_TX#[4]

E19

FDI_TX#[5]

F21

FDI_TX#[6]

G18

FDI_TX#[7]

D22

FDI_TX[0]

C21

FDI_TX[1]

D20

FDI_TX[2]

C18

FDI_TX[3]

G22

FDI_TX[4]

E20

FDI_TX[5]

F20

FDI_TX[6]

G19

FDI_TX[7]

F17

FDI_FSYNC[0]

E17

FDI_FSYNC[1]

C17

FDI_INT

F18

FDI_LSYNC[0]

D17

FDI_LSYNC[1]

IC,AUB_CFD_rPGA,R1P0

ME@

R532 1K_0402_5%HYBRID@R532 1K_0402_5%HYBRID@

1 2

R536 1K_0402_5%HYBRID@R536 1K_0402_5%HYBRID@

1 2

R534 1K_0402_5%HYBRID@R534 1K_0402_5%HYBRID@

1 2

R533 1K_0402_5%HYBRID@R533 1K_0402_5%HYBRID@

1 2

R535 1K_0402_5%HYBRID@R535 1K_0402_5%HYBRID@

1 2

PEG_RCOMPO

DMI Intel(R) FDI

PCI EXPRESS -- GRAPHICS

PEG_ICOMPI

PEG_ICOMPO

PEG_RBIAS

PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8]

PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]

PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8]

PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15]

PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9]

PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15]

B26 A26 B27 A25

K35 J34 J33 G35 G32 F34 F31 D35 E33 C33 D32 B32 C31 B28 B30 A31

J35 H34 H33 F35 G33 E34 F32 D34 F33 B33 D31 A32 C30 A28 B29 A30

L33 M35 M33 M30 L31 K32 M29 J31 K29 H30 H29 F29 E28 D29 D27 C26

L34 M34 M32 L30 M31 K31 M28 H31 K28 G30 G29 F28 E27 D28 C27 C25

EXP_ICOMPI

1 2

EXP_RBIAS

1 2

PCIE_CRX_GTX_N15 PCIE_CRX_GTX_N14 PCIE_CRX_GTX_N13 PCIE_CRX_GTX_N12 PCIE_CRX_GTX_N11 PCIE_CRX_GTX_N10

PCIE_CRX_GTX_N9 PCIE_CRX_GTX_N8 PCIE_CRX_GTX_N7 PCIE_CRX_GTX_N6 PCIE_CRX_GTX_N5 PCIE_CRX_GTX_N4 PCIE_CRX_GTX_N3 PCIE_CRX_GTX_N2 PCIE_CRX_GTX_N1 PCIE_CRX_GTX_N0

PCIE_CRX_GTX_P15 PCIE_CRX_GTX_P14 PCIE_CRX_GTX_P13 PCIE_CRX_GTX_P12 PCIE_CRX_GTX_P11 PCIE_CRX_GTX_P10 PCIE_CRX_GTX_P9 PCIE_CRX_GTX_P8 PCIE_CRX_GTX_P7 PCIE_CRX_GTX_P6 PCIE_CRX_GTX_P5 PCIE_CRX_GTX_P4 PCIE_CRX_GTX_P3 PCIE_CRX_GTX_P2 PCIE_CRX_GTX_P1 PCIE_CRX_GTX_P0

PCIE_CTX_GRX_C_N15 PCIE_CTX_GRX_C_N14 PCIE_CTX_GRX_C_N13 PCIE_CTX_GRX_C_N12 PCIE_CTX_GRX_C_N11 PCIE_CTX_GRX_C_N10 PCIE_CTX_GRX_C_N9 PCIE_CTX_GRX_C_N8 PCIE_CTX_GRX_C_N7 PCIE_CTX_GRX_C_N6 PCIE_CTX_GRX_C_N5 PCIE_CTX_GRX_C_N4 PCIE_CTX_GRX_C_N3 PCIE_CTX_GRX_C_N2 PCIE_CTX_GRX_C_N1 PCIE_CTX_GRX_C_N0

PCIE_CTX_GRX_C_P15 PCIE_CTX_GRX_C_P14 PCIE_CTX_GRX_C_P13 PCIE_CTX_GRX_C_P12 PCIE_CTX_GRX_C_P11 PCIE_CTX_GRX_C_P10 PCIE_CTX_GRX_C_P9 PCIE_CTX_GRX_C_P8 PCIE_CTX_GRX_C_P7 PCIE_CTX_GRX_C_P6 PCIE_CTX_GRX_C_P5 PCIE_CTX_GRX_C_P4 PCIE_CTX_GRX_C_P3 PCIE_CTX_GRX_C_P2 PCIE_CTX_GRX_C_P1 PCIE_CTX_GRX_C_P0

Layout rule：trace length < 0.5"

R544 49.9_0402_1%R544 49.9_0402_1%

R545 750_0402_1%R545 750_0402_1%

PCIE_CRX_GTX_N[0..15] 19

PCIE_CRX_GTX_P[0..15] 19

PCIE Lane Numbers Reversed CFG3-PCI Express Static Lane Reversal

HYBRID@

C527 0.1U_0402_10V6KC527 0.1U_0402_10V6K

1 2

C540 0.1U_0402_10V6KC540 0.1U_0402_10V6K

1 2

C529 0.1U_0402_10V6KC529 0.1U_0402_10V6K

1 2

C542 0.1U_0402_10V6KC542 0.1U_0402_10V6K

1 2

C531 0.1U_0402_10V6KC531 0.1U_0402_10V6K

1 2

C544 0.1U_0402_10V6KC544 0.1U_0402_10V6K

1 2

C533 0.1U_0402_10V6KC533 0.1U_0402_10V6K

1 2

C546 0.1U_0402_10V6KC546 0.1U_0402_10V6K

1 2

C535 0.1U_0402_10V6KC535 0.1U_0402_10V6K

1 2

C562 0.1U_0402_10V6KC562 0.1U_0402_10V6K

1 2

C564 0.1U_0402_10V6KC564 0.1U_0402_10V6K

1 2

C555 0.1U_0402_10V6KC555 0.1U_0402_10V6K

1 2

C557 0.1U_0402_10V6KC557 0.1U_0402_10V6K

1 2

C561 0.1U_0402_10V6KC561 0.1U_0402_10V6K

1 2

C548 0.1U_0402_10V6KC548 0.1U_0402_10V6K

1 2

C559 0.1U_0402_10V6KC559 0.1U_0402_10V6K

1 2

C528 0.1U_0402_10V6KC528 0.1U_0402_10V6K

1 2

C541 0.1U_0402_10V6KC541 0.1U_0402_10V6K

1 2

C530 0.1U_0402_10V6KC530 0.1U_0402_10V6K

1 2

C543 0.1U_0402_10V6KC543 0.1U_0402_10V6K

1 2

C532 0.1U_0402_10V6KC532 0.1U_0402_10V6K

1 2

C545 0.1U_0402_10V6KC545 0.1U_0402_10V6K

1 2

C534 0.1U_0402_10V6KC534 0.1U_0402_10V6K

1 2

C547 0.1U_0402_10V6KC547 0.1U_0402_10V6K

1 2

C536 0.1U_0402_10V6KC536 0.1U_0402_10V6K

1 2

C563 0.1U_0402_10V6KC563 0.1U_0402_10V6K

1 2

C565 0.1U_0402_10V6KC565 0.1U_0402_10V6K

1 2

C556 0.1U_0402_10V6KC556 0.1U_0402_10V6K

1 2

C558 0.1U_0402_10V6KC558 0.1U_0402_10V6K

1 2

C560 0.1U_0402_10V6KC560 0.1U_0402_10V6K

1 2

C549 0.1U_0402_10V6KC549 0.1U_0402_10V6K

1 2

C550 0.1U_0402_10V6KC550 0.1U_0402_10V6K

1 2

PCIE_CTX_GRX_N15 PCIE_CTX_GRX_N14 PCIE_CTX_GRX_N13 PCIE_CTX_GRX_N12 PCIE_CTX_GRX_N11 PCIE_CTX_GRX_N10 PCIE_CTX_GRX_N9 PCIE_CTX_GRX_N8 PCIE_CTX_GRX_N7 PCIE_CTX_GRX_N6 PCIE_CTX_GRX_N5 PCIE_CTX_GRX_N4 PCIE_CTX_GRX_N3 PCIE_CTX_GRX_N2 PCIE_CTX_GRX_N1 PCIE_CTX_GRX_N0

PCIE_CTX_GRX_P15 PCIE_CTX_GRX_P14 PCIE_CTX_GRX_P13 PCIE_CTX_GRX_P12 PCIE_CTX_GRX_P11 PCIE_CTX_GRX_P10 PCIE_CTX_GRX_P9 PCIE_CTX_GRX_P8 PCIE_CTX_GRX_P7 PCIE_CTX_GRX_P6 PCIE_CTX_GRX_P5 PCIE_CTX_GRX_P4 PCIE_CTX_GRX_P3 PCIE_CTX_GRX_P2 PCIE_CTX_GRX_P1 PCIE_CTX_GRX_P0

PCIE_CTX_GRX_N[0..15] 19

PCIE_CTX_GRX_P[0..15] 19

R59

@R59

1 2

3.01K_0402_1%

FOR ES1 SAMPLE ONLY

R547

R547 0_0402_5%

0_0402_5%

1 2 1 2

R546

R546 0_0402_5%

0_0402_5%

CFG Straps for PROCESSOR

CFG0

PCI-Express Configuration Select

CFG0

Not applicable for Clarksfield Processor

CFG[1:0] 11=1*16 PEG

CFG3

CFG3-PCI Express Static Lane Reversal

CFG4

CFG4-Display Port Presence

CFG4

1 2

R58 3.01K_0402_1%

1: Single PEG 0: Bifurcation enabled

10=2*8 PEG

1 2

R61 3.01K_0402_1%R61 3.01K_0402_1%

1: Normal Operation

0: Lane Numbers Reversed

CFG3

15 -> 0, 14 ->1, .....

1 2

R60 3.01K_0402_1%

1: Disabled; No Physical Display Port attached to Embedded Display Port

0: Enabled; An external Display Port device is connected to the Embedded Display Port

JCPU1E

AP25

RSVD1

AL25

RSVD2

AL24

RSVD3

AL22

RSVD4

AJ33

RSVD5

AG9

RSVD6

M27

RSVD7

L28

RSVD8

J17

SA_DIMM_VREF

H17

SB_DIMM_VREF

G25

RSVD11

G17

RSVD12

E31

RSVD13

E30

RSVD14

CFG0

AM30

CFG[0]

AM28

CFG[1]

AP31

CFG3 CFG4

CFG7

H_RSVD17_R

H_RSVD18_R

CFG[2]

AL32

CFG[3]

AL30

CFG[4]

AM31

CFG[5]

AN29

CFG[6]

AM32

CFG[7]

AK32

CFG[8]

AK31

CFG[9]

AK28

CFG[10]

AJ28

CFG[11]

AN30

CFG[12]

AN32

CFG[13]

AJ32

CFG[14]

AJ29

CFG[15]

AJ30

CFG[16]

AK30

CFG[17]

H16

RSVD_TP_86

B19

RSVD15

A19

RSVD16

A20

RSVD17

B20

RSVD18

RSVD19

RSVD20

AC9

RSVD21

AB9

RSVD22

RSVD_NCTF_23

RSVD_NCTF_24

J29

RSVD26

J28

RSVD27

A34

RSVD_NCTF_28

A33

RSVD_NCTF_29

C35

RSVD_NCTF_30

B35

RSVD_NCTF_31

IC,AUB_CFD_rPGA,R1P0

ME@

RESERVED

RSVD_NCTF_37

RSVD_NCTF_40 RSVD_NCTF_41

RSVD_NCTF_42 RSVD_NCTF_43

RSVD_NCTF_54 RSVD_NCTF_55 RSVD_NCTF_56 RSVD_NCTF_57

RSVD32 RSVD33

RSVD34 RSVD35

RSVD36

RSVD38 RSVD39

RSVD45 RSVD46 RSVD47 RSVD48 RSVD49 RSVD50 RSVD51 RSVD52 RSVD53

RSVD58

RSVD_TP_59 RSVD_TP_60

RSVD62 RSVD63 RSVD64 RSVD65

RSVD_TP_66 RSVD_TP_67 RSVD_TP_68 RSVD_TP_69 RSVD_TP_70 RSVD_TP_71 RSVD_TP_72 RSVD_TP_73 RSVD_TP_74 RSVD_TP_75

RSVD_TP_76 RSVD_TP_77 RSVD_TP_78 RSVD_TP_79 RSVD_TP_80 RSVD_TP_81 RSVD_TP_82 RSVD_TP_83 RSVD_TP_84 RSVD_TP_85

AJ13 AJ12

AH25 AK26

AL26 AR2

AJ26 AJ27

AP1 AT2

AT3 AR1

AL28 AL29 AP30 AP32 AL27 AT31 AT32 AP33 AR33 AT33 AT34 AP35 AR35 AR32

E15 F15 A2

KEY

D15 C15 AJ15 AH15

AA5 AA4 R8 AD3 AD2 AA2 AA1 R9 AG7 AE3

V4 V5 N2 AD5 AD7 W3 W2 N3 AE5 AD9

AP34

VSS

RSVD64_R RSVD65_R

R189

R189 0_0402_5%

0_0402_5%

R188

R188 0_0402_5%

0_0402_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/01/13 2011/01/13

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Arrandale(2/5)-DMI/PEG/FDI

LA-5941P

6 50Thursday, April 08, 2010

0.3

JCPU1C

JCPU1D

D D

DDR_A_D[0..63]10

C C

B B

DDR_A_BS010 DDR_A_BS110 DDR_A_BS210

DDR_A_CAS#10 DDR_A_RAS#10 DDR_A_WE#10

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

AJ10

AL10

AK12

AK11

AM10 AR11 AL11

AT11 AP12 AM12 AN12 AM13 AT14 AT12 AL13 AR14 AP14

A10

SA_DQ[0]

C10

SA_DQ[1]

SA_DQ[2]

SA_DQ[3]

B10

SA_DQ[4]

D10

SA_DQ[5]

E10

SA_DQ[6]

SA_DQ[7]

SA_DQ[8]

F10

SA_DQ[9]

SA_DQ[10]

SA_DQ[11]

SA_DQ[12]

SA_DQ[13]

SA_DQ[14]

SA_DQ[15]

H10

SA_DQ[16]

SA_DQ[17]

SA_DQ[18]

SA_DQ[19]

SA_DQ[20]

G10

SA_DQ[21]

SA_DQ[22]

J10

SA_DQ[23]

SA_DQ[24]

SA_DQ[25]

SA_DQ[26]

SA_DQ[27]

SA_DQ[28]

SA_DQ[29]

SA_DQ[30]

SA_DQ[31]

AH5

SA_DQ[32]

AF5

SA_DQ[33]

AK6

SA_DQ[34]

AK7

SA_DQ[35]

AF6

SA_DQ[36]

AG5

SA_DQ[37]

AJ7

SA_DQ[38]

AJ6

SA_DQ[39] SA_DQ[40]

AJ9

SA_DQ[41] SA_DQ[42] SA_DQ[43]

AK8

SA_DQ[44]

AL7

SA_DQ[45] SA_DQ[46]

AL8

SA_DQ[47]

AN8

SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51]

AM9

SA_DQ[52]

AN9

SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]

AC3

SA_BS[0]

AB2

SA_BS[1]

SA_BS[2]

AE1

SA_CAS#

AB3

SA_RAS#

AE9

SA_WE#

DDR SYSTEM MEMORY A

SA_CK[0] SA_CK#[0] SA_CKE[0]

SA_CK[1] SA_CK#[1] SA_CKE[1]

SA_CS#[0] SA_CS#[1]

SA_ODT[0] SA_ODT[1]

SA_DM[0]

SA_DM[1]

SA_DM[2]

SA_DM[3]

SA_DM[4]

SA_DM[5]

SA_DM[6]

SA_DM[7]

SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]

SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]

SA_MA[0]

SA_MA[1]

SA_MA[2]

SA_MA[3]

SA_MA[4]

SA_MA[5]

SA_MA[6]

SA_MA[7]

SA_MA[8]

SA_MA[9]

SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]

AA6 AA7 P7

Y6 Y5 P6

AE2 AE8

AD8 AF9

B9 D7 H7 M7 AG6 AM7 AN10 AN13

C9 F8 J9 N9 AH7 AK9 AP11 AT13

C8 F9 H9 M9 AH8 AK10 AN11 AR13

Y3 W1 AA8 AA3 V1 AA9 V8 T1 Y9 U6 AD4 T2 U3 AG8 T3 V9

DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7

DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

M_CLK_DDR0 10 M_CLK_DDR#0 10 DDR_CKE0_DIMMA 10

M_CLK_DDR1 10 M_CLK_DDR#1 10 DDR_CKE1_DIMMA 10

DDR_CS0_DIMMA# 10 DDR_CS1_DIMMA# 10

M_ODT0 10 M_ODT1 10

DDR_A_DM[0..7] 10

DDR_A_DQS#[0..7] 10

DDR_A_DQS[0..7] 10

DDR_A_MA[0..15] 10

DDR_B_D[0..63]11

DDR_B_BS011 DDR_B_BS111 DDR_B_BS211

DDR_B_CAS#11 DDR_B_RAS#11 DDR_B_WE#11

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

AR10

AT10

SB_DQ[0]

SB_DQ[1]

SB_DQ[2]

SB_DQ[3]

SB_DQ[4]

SB_DQ[5]

SB_DQ[6]

SB_DQ[7]

SB_DQ[8]

SB_DQ[9]

SB_DQ[10]

SB_DQ[11]

SB_DQ[12]

SB_DQ[13]

SB_DQ[14]

SB_DQ[15]

SB_DQ[16]

SB_DQ[17]

SB_DQ[18]

SB_DQ[19]

SB_DQ[20]

SB_DQ[21]

SB_DQ[22]

SB_DQ[23]

SB_DQ[24]

SB_DQ[25]

SB_DQ[26]

SB_DQ[27]

SB_DQ[28]

SB_DQ[29]

SB_DQ[30]

SB_DQ[31]

AF3

SB_DQ[32]

AG1

SB_DQ[33]

AJ3

SB_DQ[34]

AK1

SB_DQ[35]

AG4

SB_DQ[36]

AG3

SB_DQ[37]

AJ4

SB_DQ[38]

AH4

SB_DQ[39]

AK3

SB_DQ[40]

AK4

SB_DQ[41]

AM6

SB_DQ[42]

AN2

SB_DQ[43]

AK5

SB_DQ[44]

AK2

SB_DQ[45]

AM4

SB_DQ[46]

AM3

SB_DQ[47]

AP3

SB_DQ[48]

AN5

SB_DQ[49]

AT4

SB_DQ[50]

AN6

SB_DQ[51]

AN4

SB_DQ[52]

AN3

SB_DQ[53]

AT5

SB_DQ[54]

AT6

SB_DQ[55]

AN7

SB_DQ[56]

AP6

SB_DQ[57]

AP8

SB_DQ[58]

AT9

SB_DQ[59]

AT7

SB_DQ[60]

AP9

SB_DQ[61] SB_DQ[62] SB_DQ[63]

AB1

SB_BS[0]

SB_BS[1]

SB_BS[2]

AC5

SB_CAS#

SB_RAS#

AC6

SB_WE#

DDR SYSTEM MEMORY - B

SB_CK[0]

SB_CK#[0]

SB_CKE[0]

SB_CK[1]

SB_CK#[1]

SB_CKE[1]

SB_CS#[0] SB_CS#[1]

SB_ODT[0] SB_ODT[1]

SB_DM[0] SB_DM[1] SB_DM[2] SB_DM[3] SB_DM[4] SB_DM[5] SB_DM[6] SB_DM[7]

SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]

SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7]

SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8]

SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]

W8 W9 M3

V7 V6 M2

AB8 AD6

AC7 AD1

D4 E1 H3 K1 AH1 AL2 AR4 AT8

D5 F4 J4 L4 AH2 AL4 AR5 AR8

C5 E3 H4 M5 AG2 AL5 AP5 AR7

U5 V2 T5 V3 R1 T8 R2 R6 R4 R5 AB5 P3 R3 AF7 P5 N1

DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7

DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15

M_CLK_DDR2 11 M_CLK_DDR#2 11 DDR_CKE2_DIMMB 11

M_CLK_DDR3 11 M_CLK_DDR#3 11 DDR_CKE3_DIMMB 11

DDR_CS2_DIMMB# 11 DDR_CS3_DIMMB# 11

M_ODT2 11 M_ODT3 11

DDR_B_DM[0..7] 11

DDR_B_DQS#[0..7] 11

DDR_B_DQS[0..7] 11

DDR_B_MA[0..15] 11

IC,AUB_CFD_rPGA,R1P0

ME@

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

IC,AUB_CFD_rPGA,R1P0

ME@

Compal Secret Data

2010/01/13 2011/01/13

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Arrandale(3/5)-DDR III

LA-5941P

0.3

7 50Thursday, April 08, 2010

0.3

+CPU_CORE

JCPU1F

D D

C C

B B

A A

48A 15A18A

AG35

VCC1

AG34

VCC2

AG33

VCC3

AG32

VCC4

AG31

VCC5

AG30

VCC6

AG29

VCC7

AG28

VCC8

AG27

VCC9

AG26

VCC10

AF35

VCC11

AF34

VCC12

AF33

VCC13

AF32

VCC14

AF31

VCC15

AF30

VCC16

AF29

VCC17

AF28

VCC18

AF27

VCC19

AF26

VCC20

AD35

VCC21

AD34

VCC22

AD33

VCC23

AD32

VCC24

AD31

VCC25

AD30

VCC26

AD29

VCC27

AD28

VCC28

AD27

VCC29

AD26

VCC30

AC35

VCC31

AC34

VCC32

AC33

VCC33

AC32

VCC34

AC31

VCC35

AC30

VCC36

AC29

VCC37

AC28

VCC38

AC27

VCC39

AC26

VCC40

AA35

VCC41

AA34

VCC42

AA33

VCC43

AA32

VCC44

AA31

VCC45

AA30

VCC46

AA29

VCC47

AA28

VCC48

AA27

VCC49

AA26

VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

IC,AUB_CFD_rPGA,R1P0

ME@

CPU CORE SUPPLY

POWER

1.1V RAIL POWER

CPU VIDS

SENSE LINES

VTT0_1 VTT0_2 VTT0_3 VTT0_4 VTT0_5 VTT0_6 VTT0_7 VTT0_8

VTT0_9 VTT0_10 VTT0_11 VTT0_12 VTT0_13 VTT0_14 VTT0_15 VTT0_16 VTT0_17 VTT0_18 VTT0_19 VTT0_20 VTT0_21 VTT0_22 VTT0_23 VTT0_24 VTT0_25 VTT0_26 VTT0_27 VTT0_28 VTT0_29 VTT0_30 VTT0_31 VTT0_32

VTT0_33 VTT0_34 VTT0_35 VTT0_36 VTT0_37 VTT0_38 VTT0_39 VTT0_40 VTT0_41 VTT0_42 VTT0_43 VTT0_44

PSI#

VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]

PROC_DPRSLPVR

VTT_SELECT

ISENSE

VCC_SENSE VSS_SENSE

VTT_SENSE

VSS_SENSE_VTT

AH14

10U_0805_6.3V6M

C201

10U_0805_6.3V6M

C271

H_PSI#_R

10U_0805_6.3V6M

C199

10U_0805_6.3V6M

C270

10U_0805_6.3V6M

C219

10U_0805_6.3V6M

C208

H_VID0 48 H_VID1 48 H_VID2 48 H_VID3 48 H_VID4 48 H_VID5 48 H_VID6 48

1 2

R56 0_0402_5%R56 0_0402_5%

C217

+VCCP

C209

AH12 AH11 AH10 J14 J13 H14 H12 G14 G13 G12 G11 F14 F13 F12 F11 E14 E12 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11

AF10 AE10 AC10 AB10 Y10 W10 U10 T10 J12 J11 J16 J15

AN33

AK35 AK33 AK34 AL35 AL33 AM33 AM35 AM34

G15

H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID6 PM_DPRSLPVR_R

VTT_SELECT

H_VTTVID1 = Low, 1.1V FOR Clarksfiel

H_VTTVID1 = High, 1.05V FOR Auburndale

AN35

AJ34 AJ35

B15 A15

VCCSENSE VSSSENSE

IMVP_IMON 48

VTT_SENSE 46

T15PAD@T15PAD

10U_0805_6.3V6M

C198

10U_0805_6.3V6M

C216

10U_0805_6.3V6M

C181

10U_0805_6.3V6M

C182

10U_0805_6.3V6M

C274

C207

SVT STRIP PIN

R551

1K_0402_1%

PSI_ON#34

Lenovo Request

VCCSENSE 48 VSSSENSE 48

+VCCP

330U_D2E_2.5VM_LESR9M

C554

C554 330U_D2E_2.5VM_LESR9M

330U_D2E_2.5VM_LESR9M

10U_0805_6.3V6M

C200

+VCCP

H_PSI#_R

Q18

MMBT3906_SOT23-3

R182

1 2

10K_0402_5%

PROC_DPRSLPVR 48

VTT_SELECT 46

+GFX_CORE

C673

R282 0_0402_5%R282 0_0402_5%

123

CPU

22U_0805_6.3V6M

C161

C160

22U_0805_6.3V6M

R550

R550 1K_0402_1%

1K_0402_1%

1 2

Q51

Q51 MMST3904-7-F_SOT323-3

MMST3904-7-F_SOT323-3

3 1

C191

22U_0805_6.3V6M

SUSP39,44,45

PSI# 48

SVT,timing

22U_0805_6.3V6M

C190

+5VALW

22U_0805_6.3V6M

C159

C591

C189

C591

10U_0805_6.3V6M

+VCCP

10U_0805_6.3V6M

C214

+1.5V +1.5V_DDR3

8 7 6 5

R268

SI4800BDY-T1-E3_SO8

47K_0402_1%

R267 0_0402_5%R267 0_0402_5%

1.5_SUS- 1.5V_DDR3_GATE

Q23

Q23 2N7002_SOT23

2N7002_SOT23

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

10U_0805_6.3V6M

C592

+VCCP

10U_0805_6.3V6M

C215

112

JUMP_43X118

112

JUMP_43X118

U11

Issued Date

AS NO CONNECT

BUT A SMALL AMOUNT OF POWER

(~15MW) MAYBE WASTED

JCPU1G

AT21

VAXG1

AT19

VAXG2

10U_0805_6.3V6M

C210

10U_0805_6.3V6M

C272

AT18

VAXG3

AT16

VAXG4

AR21

VAXG5

AR19

VAXG6

AR18

VAXG7

AR16

VAXG8

AP21

VAXG9

AP19

VAXG10

AP18

VAXG11

AP16

VAXG12

AN21

VAXG13

AN19

VAXG14

AN18

VAXG15

AN16

VAXG16

AM21

VAXG17

AM19

VAXG18

AM18

VAXG19

AM16

VAXG20

AL21

VAXG21

AL19

VAXG22

AL18

VAXG23

AL16

VAXG24

AK21

VAXG25

AK19

VAXG26

AK18

VAXG27

AK16

VAXG28

AJ21

VAXG29

AJ19

VAXG30

AJ18

VAXG31

AJ16

VAXG32

AH21

VAXG33

AH19

VAXG34

AH18

VAXG35

AH16

VAXG36

J24

10U_0805_6.3V6M

C211

C240

VTT1_45

J23

VTT1_46

H25

VTT1_47

K26

VTT1_48

J27

VTT1_49

J26

VTT1_50

J25

VTT1_51

H27

VTT1_52

G28

VTT1_53

G27

VTT1_54

G26

VTT1_55

F26

VTT1_56

E26

VTT1_57

E25

VTT1_58

IC,AUB_CFD_rPGA,R1P0

ME@

GRAPHICS

FDI PEG & DMI

VAXG_SENSE

VSSAXG_SENSE

SENSE

LINES

SENSE

LINES

GFX_VID[0] GFX_VID[1] GFX_VID[2] GFX_VID[3] GFX_VID[4] GFX_VID[5] GFX_VID[6]

GFX_VR_EN

GFX_DPRSLPVR

GRAPHICS VIDs

POWER

DDR3 - 1.5V RAILS

1.1V1.8V

0.6A

DESIGN GUIDE REV1.1

AR22 AT22

AM22 AP22 AN22 AP23 AM23 AP24 AN24

GFX_VR_EN

AR25 AT25

GFX_IMON_R

AM24

GFX_IMON

AJ1

VDDQ1

AF1

VDDQ2

AE7

VDDQ3

AE4

VDDQ4

AC1

VDDQ5

AB7

VDDQ6

AB4

VDDQ7

VDDQ8

VDDQ9

VDDQ10

VDDQ11

VDDQ12

VDDQ13

VDDQ14

VDDQ15

VDDQ16

VDDQ17

VDDQ18

P10

VTT0_59

N10

VTT0_60

L10

VTT0_61

K10

VTT0_62

J22

VTT1_63

J20

VTT1_64

J18

VTT1_65

H21

VTT1_66

H20

VTT1_67

H19

VTT1_68

L26

VCCPLL1

L27

VCCPLL2

M26

VCCPLL3

VCC_AXG_SENSE 47 VSS_AXG_SENSE 47

GFXVR_VID_0 47 GFXVR_VID_1 47 GFXVR_VID_2 47 GFXVR_VID_3 47 GFXVR_VID_4 47 GFXVR_VID_5 47 GFXVR_VID_6 47

R141 0_0402_5%R141 0_0402_5%

1 2

1U_0603_10V6K

C254

220U_B2_2.5VM_R35

10U_0805_6.3V6M

C268

1U_0603_10V6K

C149

C167

T16PAD@T16PAD

+1.5V_DDR3

1U_0603_10V6K

C255

C253

C256

C252

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K C168

C168

10U_0805_6.3V6M

C258

+VCCP

10U_0805_6.3V6M

C212

C273

+VCCP

10U_0805_6.3V6M

C213

C218

+1.8VS

4.7U_0603_6.3V6K

10U_0805_6.3V6M

C169

GFX_IMON_R

1U_0603_10V6K

C257

C170

R132

HYBRID@

DGPU_SELECT

GFX_VR_EN

GFXVR_EN 47

GFXVR_IMON 47

1K_0402_5%

R140

330_0402_5%

1 2

HYBRID@

Q58

2N7002_SOT23

For Intel S3 Power Reduction.

+1.5V

1 2 3 4

+1.5V_DDR3

C325

0.1U_0603_25V7K

2010/01/13 2011/01/13

0.1U_0402_10V6K

C289

C288

Compal Secret Data

0.1U_0402_10V6K

C287

Deciphered Date

C286

SUSP

For Intel S3 Power Reduction.

+1.5V_DDR3

C269

0.1U_0402_10V6K@C269

0.1U_0402_10V6K

R233

R233 220_0402_5%

220_0402_5%

Q19

2N7002_SOT23

Title

Size Document Number Rev

Custom

Date: Sheet of

PVT

Compal Electronics, Inc.

Arrandale(4/5)-PWR

LA-5941P

0.3

8 50Thursday, April 08, 2010

0.3

JCPU1H

AT20

VSS1

AT17

VSS2

AR31

VSS3

AR28

VSS4

AR26

VSS5

AR24

VSS6

AR23

VSS7

AR20

D D

C C

B B

AR17 AR15 AR12

AP20 AP17 AP13 AP10

AN34 AN31 AN23 AN20

AN17 AM29 AM27 AM25 AM20 AM17 AM14 AM11

AL34

AL31

AL23

AL20

AL17

AL12

AK29 AK27 AK25 AK20 AK17

AJ31

AJ23

AJ20

AJ17

AJ14

AJ11

AH35 AH34 AH33 AH32 AH31 AH30 AH29 AH28 AH27 AH26 AH20 AH17 AH13

AG10

AE35

VSS8 VSS9 VSS10 VSS11

AR9

VSS12

AR6

VSS13

AR3

VSS14 VSS15 VSS16 VSS17 VSS18

AP7

VSS19

AP4

VSS20

AP2

VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33

AM8

VSS34

AM5

VSS35

AM2

VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42

AL9

VSS43

AL6

VSS44

AL3

VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56

AJ8

VSS57

AJ5

VSS58

AJ2

VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72

AH9

VSS73

AH6

VSS74

AH3

VSS75 VSS76

AF8

VSS77

AF4

VSS78

AF2

VSS79 VSS80

VSS

VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98

VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160

AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE6 AD10 AC8 AC4 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 AB6 AA10 Y8 Y4 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 W6 V10 U8 U4 U2 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 T6 R10 P8 P4 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 N6 M10 L35 L32 L29 L8 L5 L2 K34 K33 K30

JCPU1I

K27

VSS161

VSS162

VSS163

VSS164

J32

VSS165

J30

VSS166

J21

VSS167

J19

VSS168

H35

VSS169

H32

VSS170

H28

VSS171

H26

VSS172

H24

VSS173

H22

VSS174

H18

VSS175

H15

VSS176

H13

VSS177

H11

VSS178

VSS179

VSS180

VSS181

G34

VSS182

G31

VSS183

G20

VSS184

VSS185

VSS186

VSS187

F30

VSS188

F27

VSS189

F25

VSS190

F22

VSS191

F19

VSS192

F16

VSS193

E35

VSS194

E32

VSS195

E29

VSS196

E24

VSS197

E21

VSS198

E18

VSS199

E13

VSS200

E11

VSS201

VSS202

VSS203

VSS204

D33

VSS205

D30

VSS206

D26

VSS207

VSS208

VSS209

VSS210

C34

VSS211

C32

VSS212

C29

VSS213

C28

VSS214

C24

VSS215

C22

VSS216

C20

VSS217

C19

VSS218

C16

VSS219

B31

VSS220

B25

VSS221

B21

VSS222

B18

VSS223

B17

VSS224

B13

VSS225

B11

VSS226

VSS227

VSS228

VSS229

A29

VSS230

A27

VSS231

A23

VSS232

VSS233

VSS

VSS_NCTF1 VSS_NCTF2 VSS_NCTF3 VSS_NCTF4 VSS_NCTF5 VSS_NCTF6 VSS_NCTF7

NCTF

AT1 AR34 B34 B2 B1 A35

VSS_NCTF2_R VSS_NCTF3_R VSS_NCTF4_R VSS_NCTF5_R VSS_NCTF6_R VSS_NCTF7_R

VSS_NCTF1_R

AT35

+CPU_CORE

CPU CORE

22U_0805_6.3V6M

C568

10U_0805_6.3V6M

C147

10U_0805_6.3V6M

C195

22U_0805_6.3V6M

C585

C580

10U_0805_6.3V6M

C163

C162

10U_0805_6.3V6M

C88

C192

22U_0805_6.3V6M

C579

10U_0805_6.3V6M

C179

10U_0805_6.3V6M

C196

C573

C574

10U_0805_6.3V6M

C193

C166

10U_0805_6.3V6M

C180

C89

Under cavity

22U_0805_6.3V6M

C578

C584

10U_0805_6.3V6M

C165

C148

10U_0805_6.3V6M

C197

22U_0805_6.3V6M

C583

10U_0805_6.3V6M

C194

between Inductor and socket

330U_D2E_2.5VM_LESR9M

C75

PVT, change from 470uF 4.5mohm to 330uF 6mohm and 2nd 470uF 7 mohm by power; '10 1/8 update main to 330uF 9 m ohm

22U_0805_6.3V6M

C577

330U_D2E_2.5VM_LESR9M

C76

22U_0805_6.3V6M

C572

C571

Inside cavity

330U_D2E_2.5VM_LESR9M

C92

C164

22U_0805_6.3V6M

C91

22U_0805_6.3V6M

C129

C90

C129

C87

IC,AUB_CFD_rPGA,R1P0

ME@

A A

IC,AUB_CFD_rPGA,R1P0

ME@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/01/13 2011/01/13

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Arrandale(5/5)-GND/Bypass

LA-5941P

9 50Thursday, April 08, 2010

0.3

+VREF_DQ_DIMMA

0.1U_0402_10V6K

2.2U_0603_6.3V6K

C303

D D

C C

B B

A A

DDR_CKE0_DIMMA7

DDR_A_BS27

M_CLK_DDR07 M_CLK_DDR#07

DDR_A_BS07

DDR_A_WE#7 DDR_A_CAS#7

DDR_CS1_DIMMA#7

+3VS

DDR_A_D0

C347

DDR_A_D1

DDR_A_DM0

DDR_A_D2 DDR_A_D3

DDR_A_D8 DDR_A_D9

DDR_A_DQS#1 DDR_A_DQS1

DDR_A_D10 DDR_A_D11

DDR_A_D16 DDR_A_D17

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D18 DDR_A_D19

DDR_A_D24 DDR_A_D25

DDR_A_DM3

DDR_A_D26 DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS2

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8 DDR_A_MA5

DDR_A_MA3 DDR_A_MA1

M_CLK_DDR0 M_CLK_DDR#0

DDR_A_MA10 DDR_A_BS0

DDR_A_WE# DDR_A_CAS# M_ODT0

DDR_A_MA13 DDR_CS1_DIMMA#

DDR_A_D32 DDR_A_D33

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_DM5

DDR_A_D42 DDR_A_D43

DDR_A_D48 DDR_A_D49

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D50 DDR_A_D51

DDR_A_D56 DDR_A_D57

DDR_A_DM7

DDR_A_D58 DDR_A_D59

1 2

10K_0402_5%

2.2U_0603_6.3V6K

0.1U_0402_10V6K

C608

C617

+1.5V +1.5V

3A@1.5V

3A@1.5V3A@1.5V

DDR3 SO-DIMM A

JDIMM1

VREF_DQ1VSS1

VSS2

DQ0

DQ1

VSS4

DM0

VSS5

DQ2

DQ3

VSS7

DQ8

DQ9

VSS9

DQS#1 DQS129RESET# VSS1131VSS12

DQ10

DQ11 VSS1337VSS14

DQ16

DQ17 VSS1543VSS16

DQS#2

DQS2

VSS18

DQ18

DQ19

VSS20

DQ24

DQ25 VSS2261DQS#3

DM3 VSS2365VSS24

DQ26

DQ27 VSS2571VSS26

CKE0

VDD1

NC1

BA2

VDD3

A12/BC#

VDD5

VDD7

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

R570

10K_0402_5%

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

R571

VTT1

205

DQ4 DQ5

VSS3

DQS#0

DQS0 VSS6

DQ6

DQ7 VSS8 DQ12 DQ13

VSS10

DM1

DQ14 DQ15

DQ20 DQ21

DM2

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

DQ30 DQ31

CKE1 VDD2

A15 A14

VDD4

A11

VDD6

A6 A4

VDD8

A2 A0

VDD10

CK1

CK1#

VDD12

BA1

RAS#

VDD14

S0#

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

DM4

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35 DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

DM6

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47 DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

SDA

SCL

VTT2

FOX_AS0A626-U4SN-7F

FOX_AS0A626-U4SN-7F ME@

ME@

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

DDR_A_D4 DDR_A_D5

DDR_A_DQS#0 DDR_A_DQS0

DDR_A_D6 DDR_A_D7

DDR_A_D12 DDR_A_D13

DDR_A_DM1 DRAMRST#

DDR_A_D14 DDR_A_D15

DDR_A_D20 DDR_A_D21

DDR_A_DM2

DDR_A_D22 DDR_A_D23

DDR_A_D28 DDR_A_D29

DDR_A_DQS#3 DDR_A_DQS3

DDR_A_D30 DDR_A_D31

DDR_CKE1_DIMMA

DDR_A_MA15 DDR_A_MA14

DDR_A_MA11 DDR_A_MA7

DDR_A_MA6 DDR_A_MA4

DDR_A_MA2 DDR_A_MA0

M_CLK_DDR1 M_CLK_DDR#1

DDR_A_BS1 DDR_A_RAS#

DDR_CS0_DIMMA#

M_ODT1

DDR_A_D36 DDR_A_D37

DDR_A_DM4

DDR_A_D38 DDR_A_D39

DDR_A_D44 DDR_A_D45

DDR_A_DQS#5 DDR_A_DQS5

DDR_A_D46 DDR_A_D47

DDR_A_D52 DDR_A_D53

DDR_A_DM6

DDR_A_D54 DDR_A_D55

DDR_A_D60 DDR_A_D61

DDR_A_DQS#7 DDR_A_DQS7

DDR_A_D62 DDR_A_D63

PM_EXTTS#1_R SMB_DATA_S3 SMB_CLK_S3

+0.75VS

0.65A@0.75V

0.65A@0.75V0.65A@0.75V

DRAMRST# 5,11

DDR_CKE1_DIMMA 7

M_CLK_DDR1 7 M_CLK_DDR#1 7

DDR_A_BS1 7 DDR_A_RAS# 7

DDR_CS0_DIMMA# 7 M_ODT0 7

M_ODT1 7

0.1U_0402_10V6K

0.1U_0402_10V6K C346

C346

VDDQ(1.5V) =

3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)

6*0603 10uf (PER CONNECTOR)

VTT(0.75V) =

3*0805 10uf

VREF =

1*0402 0.1uf

VDDSPD (3.3V)=

1*0402 0.1uf 1*0402 2.2uf

PM_EXTTS#1_R 5,11

SMB_DATA_S3 11,12,14,28 SMB_CLK_S3 11,12,14,28

+VREF_DQ_DIMMA

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K C355

C355

DDR_A_D[0..63]7

DDR_A_DM[0..7]7

DDR_A_DQS[0..7]7

DDR_A_DQS#[0..7]7

DDR_A_MA[0..15]7

4*0402 1uf

1*0402 2.2uf

Layout Note: Place near DIMM

+1.5V

10U_0603_6.3V6M

C589

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C586

C588

2010/01/13 2011/01/13

+0.75VS

C607

C605

1U_0603_10V6K

C605

1U_0603_10V6K

Compal Secret Data

C581

1U_0603_10V6K

10U_0603_6.3V6M

C310

C606

C300

1U_0603_10V6K

Deciphered Date

10U_0603_6.3V6M

C570

C309

C301

10U_0603_6.3V6M

C301

10U_0603_6.3V6M

1U_0603_10V6K

+1.5V

R297

1K_0402_1%

For Arranale only +VREF_DQ_DIMMA supply from a external 1.5V voltage divide circuit. 07/17/2009

10U_0603_6.3V6M

0.1U_0402_10V6K

C314

C308

C314

0.1U_0402_10V6K

C315

C317

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

DDRIII-SODIMM SLOT1

0.1U_0402_10V6K

R305

C316

+VREF_DQ_DIMMA

C569

C569 220U_B2_2.5VM_R35

220U_B2_2.5VM_R35

LA-5941P

0.3

10 50Thursday, April 08, 2010

0.3

+VREF_DQ_DIMMB

0.1U_0402_10V6K

2.2U_0603_6.3V6K

C382

+3VS

DDR_CKE2_DIMMB7

DDR_B_BS27

M_CLK_DDR27 M_CLK_DDR#27

DDR_B_BS07

DDR_B_WE#7 DDR_B_CAS#7

DDR_CS3_DIMMB#7

2.2U_0603_6.3V6K

D D

C C

B B

A A

+VREF_DQ_DIMMB

DDR_B_D0 DDR_B_D1

C384

DDR_B_DM0

DDR_B_D2 DDR_B_D3

DDR_B_D8 DDR_B_D9

DDR_B_DQS#1 DDR_B_DQS1

DDR_B_D10 DDR_B_D11

DDR_B_D16 DDR_B_D17

DDR_B_DQS#2 DDR_B_DQS2

DDR_B_D19

DDR_B_D24 DDR_B_D25

DDR_B_DM3

DDR_B_D26 DDR_B_D27

DDR_CKE2_DIMMB

DDR_B_BS2

DDR_B_MA12

DDR_B_MA8 DDR_B_MA5

DDR_B_MA3 DDR_B_MA1

M_CLK_DDR2 M_CLK_DDR#2

DDR_B_MA10 DDR_B_BS0

DDR_B_WE# DDR_B_CAS#

DDR_B_MA13 DDR_CS3_DIMMB#

DDR_B_D32 DDR_B_D33

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D34 DDR_B_D35

DDR_B_D40 DDR_B_D41

DDR_B_DM5

DDR_B_D42 DDR_B_D43

DDR_B_D48 DDR_B_D49

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D50 DDR_B_D51

DDR_B_D56 DDR_B_D57

DDR_B_DM7

DDR_B_D58 DDR_B_D59

1 2

10K_0402_5%

0.1U_0402_10V6K

C618

C616

+1.5V +1.5V

3A@1.5V

3A@1.5V3A@1.5V

JDIMM2

VREF_DQ1VSS1

VSS2

DQ0

DQ1 VSS49DQS#0

DM0

VSS5

DQ2

DQ3

VSS7

DQ8

DQ9

VSS9

DQS#1 DQS129RESET# VSS1131VSS12

DQ10

DQ11 VSS1337VSS14

DQ16

DQ17 VSS1543VSS16

DQS#2

DQS2

VSS18

DQ18

DQ19

VSS20

DQ24

DQ25 VSS2261DQS#3

DM3 VSS2365VSS24

DQ26

DQ27 VSS2571VSS26

CKE0

VDD1

NC1

BA2

VDD3

DDR_B_MA9

R572

1 2

R573 10K_0402_5%R573 10K_0402_5%

A12/BC#

VDD5

VDD7

A1 VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

FOX_AS0A626-U4RN-7F

ME@

VSS3

DQS0

VSS6

VSS8 DQ12 DQ13

VSS10

DQ14 DQ15

DQ20 DQ21

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

VTT2

2 4

DQ4

DQ5

8 10 12 14 16

DQ6

DQ7

20 22 24 26 28

DM1

30 32 34 36 38 40 42 44 46

DM2

48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78

A15

A14

82 84

A11

88 90

94 96

100 102

CK1

104 106 108

BA1

110 112 114

S0#

116 118 120 122

NC2

124 126 128 130 132 134 136

DM4

138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170

DM6

172 174 176 178 180 182 184 186 188 190 192 194 196 198 200

SDA

202

SCL

204

206

DDR_B_D4 DDR_B_D5

DDR_B_DQS#0 DDR_B_DQS0

DDR_B_D6 DDR_B_D7

DDR_B_D12 DDR_B_D13

DDR_B_DM1 DRAMRST#

DDR_B_D14 DDR_B_D15

DDR_B_D20 DDR_B_D21

DDR_B_DM2

DDR_B_D22 DDR_B_D23DDR_B_D18

DDR_B_D28 DDR_B_D29

DDR_B_DQS#3 DDR_B_DQS3

DDR_B_D30 DDR_B_D31

DDR_CKE3_DIMMB

DDR_B_MA15 DDR_B_MA14

DDR_B_MA11 DDR_B_MA7

DDR_B_MA6 DDR_B_MA4

DDR_B_MA2 DDR_B_MA0

M_CLK_DDR3 M_CLK_DDR#3

DDR_B_BS1 DDR_B_RAS#

DDR_CS2_DIMMB# M_ODT2

M_ODT3

DDR_B_D36 DDR_B_D37

DDR_B_DM4

DDR_B_D38 DDR_B_D39

DDR_B_D44 DDR_B_D45

DDR_B_DQS#5 DDR_B_DQS5

DDR_B_D46 DDR_B_D47

DDR_B_D52 DDR_B_D53

DDR_B_DM6

DDR_B_D54 DDR_B_D55

DDR_B_D60 DDR_B_D61

DDR_B_DQS#7 DDR_B_DQS7

DDR_B_D62 DDR_B_D63

PM_EXTTS#1_R SMB_DATA_S3 SMB_CLK_S3

0.65A@0.75V

0.65A@0.75V0.65A@0.75V

DDR_B_DQS#[0..7]7

DDR_B_D[0..63]7

DDR_B_DM[0..7]7

DDR_B_DQS[0..7]7

DDR_B_MA[0..15]7

DRAMRST# 5,10

DDR_CKE3_DIMMB 7

M_CLK_DDR3 7 M_CLK_DDR#3 7

DDR_B_BS1 7 DDR_B_RAS# 7

DDR_CS2_DIMMB# 7 M_ODT2 7

M_ODT3 7

0.1U_0402_10V6K

C385

+VREF_DQ_DIMMB

2.2U_0603_6.3V6K

C383

Layout Note: Place near DIMM

10U_0603_6.3V6M

C582

1K_0402_1%

For Arranale only +VREF_DQ_DIMMB supply from a external 1.5V voltage divide circuit. 07/17/2009

+1.5V

10U_0603_6.3V6M

C587

10U_0603_6.3V6M

C576

C311

10U_0603_6.3V6M

C590

C313

10U_0603_6.3V6M

C575

C312

0.1U_0402_10V6K

0.1U_0402_10V6K C304

C304

C307

0.1U_0402_10V6K

0.1U_0402_10V6K C306

C306

C305

R341

R340

+1.5V

+VREF_DQ_DIMMB

VDDQ(1.5V) =

3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)

6*0603 10uf (PER CONNECTOR)

VTT(0.75V) =

3*0805 10uf

1*0402 0.1uf

4*0402 1uf

1*0402 2.2uf

VDDSPD (3.3V)=

1*0402 0.1uf 1*0402 2.2uf

PM_EXTTS#1_R 5,10

SMB_DATA_S3 10,12,14,28 SMB_CLK_S3 10,12,14,28

+0.75VS

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Layout Note: Place near DIMM

+0.75VS

1U_0603_10V6K

C596

1U_0603_10V6K

2010/01/13 2011/01/13

1U_0603_10V6K

C299

C598

Compal Secret Data

Deciphered Date

C595

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

DDRIII-SODIMM SLOT2

LA-5941P

11 50Thursday, April 08, 2010

0.3

Reserve for Low Power CLK GEN. RTM890N-632 SLG8LV597VTR

VDD_3V3_1V5+3VS_CK505

1 2

R2780_0603_5%@R2780_0603_5%

D D

+1.5VS

1 2

R2690_0603_5% R2690_0603_5%

1 PCS CAP(0.1u) BY 1 INPUT PIN

VDD_3V3_1V5

10U_0805_6.3V6M

0.1U_0402_10V6K

C336

0.1U_0402_10V6K

0.1U_0402_10V6K C330

C366

C330

C334

CLK GEN TO PCH

1. CLK_DMI

2. CLK_BUF_BCLK

3. CLK_BUF_CKSSCD

4. CLK_BUF_DOT96

5. CLK_14M_PCH

C C

CLK GEN TO VGA

1. 27M_CLK

1. 27M_CLK_SS

+1.05VS_CK505+1.05VS

1 2

R2770_0603_5% R2770_0603_5%

CLK_BUF_DOT9614

CLK_BUF_DOT96#14

CLK_BUF_CKSSCD14

CLK_BUF_CKSSCD#14

CLK_DMI14

CLK_DMI#14

CLK_BUF_DOT96 CLK_BUF_DOT96#

CLK_BUF_CKSSCD CLK_BUF_CKSSCD#

CLK_DMI CLK_DMI#

+3VS_CK505

R318 0_0402_5%R318 0_0402_5%

1 2 1 2

R319 0_0402_5%R319 0_0402_5%

CLOSE U27

R324 0_0402_5%R324 0_0402_5%

1 2

R308

1 2

R307 0_0402_5%R307 0_0402_5%

1 2

R306

1 2

R299

1 2

1 PCS CAP(0.1u) BY 1 INPUT PIN

10U_0805_6.3V6M

0.1U_0402_10V6K

C331

C333

C332

0.1U_0402_10V6K

0.1U_0402_10V6K C335

C335

C343

C1212

C1212 47P_0402_50V8J

47P_0402_50V8J

0_0402_5%

10K_0402_5%

VDD_3V3_1V5

L_CLK_BUF_DOT96 L_CLK_BUF_DOT96#

CLK_48M_CR_R

CLK_BUF_CKSSCD_R CLK_BUF_CKSSCD#_R

L_CLK_DMI L_CLK_DMI#

CPU_STOP#

VDD_REF

XTAL_IN

XTAL_OUT

VSS_REF

VDD_CPU

CPU_0

CPU_0#

VSS_CPU

CPU_1

CPU_1#

VDD_SRC

+3VS_CK505 +1.05VS_CK505+3VS_CK505 +1.05VS_CK505

SCL

SDA

30 29 28 27 26 25

24 23 22 21 20 19 18 17

SMB_CLK_S3 SMB_DATA_S3 REF_0/CPU_SEL

CLK_XTAL_IN CLK_XTAL_OUT

CK_PWRGD

VDD_3V3_1V5 R_CLK_BUF_BCLK CLK_BUF_BCLK R_CLK_BUF_BCLK# CLK_BUF_BCLK#

VDD_3V3_1V5

R275 0_0402_5%R275 0_0402_5%

R276 0_0402_5%R276 0_0402_5%

U14

VDD_USB_48

VSS_48M

DOT_96

DOT_96#

VDD_27

27MHZ

27MHZ_SS

USB_48

VSS_27M

SATA

SATA#

VSS_SRC

SRC_1

SRC_1#

VDD_SRC_IO

CPU_STOP#

TGND

RTM890N-631-VB-GRT_QFN32_5X5

REF_0/CPU_SEL

CKPWRGD/PD#

VDD_CPU_IO

SA00003HQ10 S IC RTM890N-631-VB-GRT QFN 32P CLK GEN

(SA00003HR00)S IC ICS9LVS3199AKLFT MLF 32P CLK GEN S IC SLG8SP587VTR QFN 32P CLK GEN (SA00002XY00)

CLK_48M_CR_R

R3230_0402_5%@R3230_0402_5%

1 2 1 2

R315

33_0402_1%

CLK_14M_PCH

CK_PWRGD

2N7002_SOT23-3

SMB_CLK_S3 10,11,14,28 SMB_DATA_S3 10,11,14,28

CLK_14M_PCH 14

CLK_BUF_BCLK 14 CLK_BUF_BCLK# 14

R298

1 2

10K_0402_5%

Q25

+3VS_CK505

CLK_EN# 48

PIN8 IS GND FOR ICS3197

RF 10/22

B B

+3VS

1 2

R2790_0603_5% R2790_0603_5%

+3VS_CK505

1 PCS CAP(0.1u) BY 1 INPUT PIN

0.1U_0402_10V6K

10U_0805_6.3V6M

C344

0.1U_0402_10V6K

C350

C342

C367

C1213

C1213 47P_0402_50V8J

47P_0402_50V8J

C364

C365

EMI Capacitor

RF 10/22

+1.05VS

CPU_1PIN 30 CPU_0

(Default)

0 133MHz

A A

133MHz

100MHz 100MHz

1 2

R317 10K_0402_5%@R317 10K_0402_5%@

1 2

R316 10K_0402_5%R316 10K_0402_5%

PIN8 IS 48MHz FOR ICS3199

CLK_14M_PCH

10P_0402_50V8J@

REF_0/CPU_SEL

10P_0402_50V8J

SVT RF

REF_0/CPU_SEL

27P_0402_50V8J

14.318MHZ_20PF_7A14300003

C348

CLK_XTAL_OUT

CLK_XTAL_IN

C349

C349 27P_0402_50V8J

27P_0402_50V8J

PVT, resize 5032, CL27pF

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/01/13 2011/01/13

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

CLOCK GENERATOR

LA-5941P

12 50Thursday, April 08, 2010

0.3

PCH_RTCX1

1 2

R154 10M_0402_5%R154 10M_0402_5%

PCH_RTCX2

1 4

2 3

D D

+RTCVCC

R144

1 2

100_0603_1%

C441

0.1U_0402_16V4Z

RF 1103 add

C1221

C C

C1221 12P_0402_50V8J

12P_0402_50V8J

+RTCBATT

15P_0402_50V8J

HDA_BITCLK_CODEC

HDA_SDOUT_CODEC

C1222

C1222 12P_0402_50V8J

12P_0402_50V8J

C171

EPSON Q13MC1461005000

6.9x1.4x1.3mm

+RTCVCC

R421

1 2

R420

1 2

H：Integrated VRM enable

L：Integrated VRM disable

+3VS

R452 1K_0402_5%@R452 1K_0402_5%@

PVT

1M_0402_5%

330K_0402_5%

1 2

GPIO33 = GPO , internal pull-u p,should not be pulled low

flash ME core of strap pin pul l down

+3VALW+3VALW +3VALW +3VALW +3VS

RefDesPCH Pin

R591

R590

R584

R583

R586

R580

R595

R594

R72

R72 200_0402_5%

200_0402_5%

PCH_JTAG_TMS PCH_JTAG_RST#PCH_JTAG_TDO PCH_JTAG_TDI

R115

R115 100_0402_1%

100_0402_1%

PCH JTAG Pre-Production

ES1 MPES2

No Install

200ohm

100ohm 100ohm

200ohm

100ohm 100ohm

51ohm

20Kohm 20Kohm

10Kohm 10Kohm

R74

R74 200_0402_5%

200_0402_5%

B B

R117

R117 100_0402_1%

100_0402_1%

A A

PCH_JTAG_TDI

PCH_JTAG_TCK

PCH_JTAG_RST#

R73

R73 200_0402_5%

200_0402_5%

R116

R116 100_0402_1%

100_0402_1%

PCH JTAG Production

200ohm

No Install

100ohm

No InstallPCH_JTAG_TDO

200ohm

No Install

No InstallPCH_JTAG_TMS

200ohm

No InstallR587

No Install

51ohm 51ohm

No Install

32.768KHZ_12.5P_MC-146

C183

C183 15P_0402_50V8J

15P_0402_50V8J

SM_INTRUDER#

PCH_INTVRMEN

PCH_SPKR

+RTCVCC

HDA_BITCLK_CODEC33

HDA_SYNC_CODEC33

HDA_SDOUT_CODEC33

R419 20K_0402_1%R419 20K_0402_1%

R422 20K_0402_1%R422 20K_0402_1%

PCH_SPKR33

HDA_RST_CODEC#33

HDA_SDIN133

ME_FLASH34

1U_0603_10V6K

1 2

1U_0603_10V6K

+3VALW

C184

C202

R168 33_0402_5%R168 33_0402_5%

R167 33_0402_5%R167 33_0402_5%

R169 33_0402_5%R169 33_0402_5%

R166 33_0402_5%R166 33_0402_5%

(2009,07,07)

R75

R75 20K_0402_5%

20K_0402_5%

1 2

R118

R118 10K_0402_5%

10K_0402_5%

PCH_JTAG_TCK

R114 51_0402_5%R114 51_0402_5%

1 2

SPI_CLK_PCH

(2009,05,04)

FOR INTEL DPDG REV1.6 (MAY 2009)

CLRP3

SHORT PADS

CLRP2

SHORT PADS

1 2

R676 0_0402_5%

1 2

R677 0_0402_5%R677 0_0402_5%

1 2

SVT

1 2

R409 1K_0402_5%@R409 1K_0402_5%@

1 2

R425 0_0402_5%R425 0_0402_5%

1 2

R424 10K_0402_5%

1 2

GPIO13 = GPI,3.3V,SUS

R99

1 2

0_0402_5%

PCH_RTCX1 PCH_RTCX2

PCH_RTCRST#

PCH_SRTCRST#

SM_INTRUDER#

PCH_INTVRMEN

BITCLK

HDA_SYNC

PCH_SPKR

HDA_RST#

HDA_SDIN0

HDA_SDIN1_RHDA_SDIN1

HDA_SDOUT

PCH_JTAG_TCK

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

SPI_CLK_PCH_R

SPI_SB_CS0#

SPI_SI

SPI_SO_R

GPIO13

B13 D13

C14

D17

A16

A14

A30

D29

C30

G30

F30

E32

F32

B29

H32

J30

BA2

AV3

AY3

AY1

AV1

U7A

RTCX1 RTCX2

RTCRST#

SRTCRST#

INTRUDER#

INTVRMEN

HDA_BCLK

HDA_SYNC

SPKR

HDA_RST#

HDA_SDIN0

HDA_SDIN1

HDA_SDIN2

HDA_SDIN3

HDA_SDO

HDA_DOCK_EN# / GPIO33

HDA_DOCK_RST# / GPIO13

JTAG_TCK

JTAG_TMS

JTAG_TDI

JTAG_TDO

TRST#

SPI_CLK

SPI_CS0#

SPI_CS1#

SPI_MOSI

SPI_MISO

IBEXPEAK-M_FCBGA1071

RTCIHDA

SPI JTAG

FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3

FWH4 / LFRAME#

LDRQ1# / GPIO23

LPC

SATA0RXN SATA0RXP SATA0TXN

SATA0TXP

SATA1RXN SATA1RXP SATA1TXN

SATA1TXP

SATA2RXN SATA2RXP SATA2TXN

SATA2TXP

SATA3RXN SATA3RXP SATA3TXN

SATA3TXP

SATA4RXN SATA4RXP SATA4TXN

SATA

SATA4TXP

SATA5RXN SATA5RXP SATA5TXN

SATA5TXP

SATAICOMPO

SATAICOMPI

SATALED#

SATA0GP / GPIO21

SATA1GP / GPIO19

LDRQ0#

SERIRQ

D33 B33 C32 A32

C34

A34 F34

AB9

AK7 AK6 AK11 AK9

AH6 AH5 AH9 AH8

AF11 AF9 AF7 AF6

AH3 AH1 AF3 AF1

AD9 AD8 AD6 AD5

AD3 AD1 AB3 AB1

AF16

AF15

GPIO23

T7 PADT7 PAD

GPIO23 = NATIVE,3.3V,CORE

SERIRQ

SATA_ITX_C_DRX_N0 SATA_ITX_C_DRX_P0

SATA_ITX_C_DRX_N1 SATA_ITX_C_DRX_P1

SATA_DTX_C_IRX_N4 SATA_DTX_C_IRX_P4

SATA_ITX_C_DRX_N4 SATA_ITX_C_DRX_P4

SATAICOMPPCH_JTAG_RST#

1 2

37.4_0402_1%

1 2

R453 10K_0402_5%R453 10K_0402_5%

GPIO21

GPIO19

LPC_AD0 28,34 LPC_AD1 28,34 LPC_AD2 28,34 LPC_AD3 28,34

LPC_FRAME# 28,34

SERIRQ 34

R500

+1.05VS

+3VS

HDD_LED# 38

GPIO21 = GPI,3.3V,CORE

GPIO19 = GPI,3.3V,CORE

SA00003N7A0 (MP)

+3VS

1 2

R101

15_0402_5%

SPI_WP#

3.3K_0402_5%

SPI_HOLD#

3.3K_0402_5%

R62

R102

R103

15_0402_5%

SPI_SB_CS0#

1 2

SPI_SO_R SPI_SO_L

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/01/13 2011/01/13

Compal Secret Data

Deciphered Date

R47910K_0402_5% R47910K_0402_5%

SPI_WP#

+3VS

C1400.01U_0402_16V7K C1400.01U_0402_16V7K

C1410.01U_0402_16V7K C1410.01U_0402_16V7K

12 12

SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_P0

SATA_ITX_DRX_N0

SATA_ITX_DRX_P0

SATA_DTX_C_IRX_N1 SATA_DTX_C_IRX_P1

SATA_ITX_DRX_N4_CONN

C1420.01U_0402_16V7K C1420.01U_0402_16V7K

SATA_ITX_DRX_P4_CONN

C1430.01U_0402_16V7K C1430.01U_0402_16V7K

R447

10K_0402_5%

GPIO21

GPIO19

1 2

SATA_DTX_C_IRX_N0 32

SATA_DTX_C_IRX_P0 32 SATA_ITX_DRX_N0 32 SATA_ITX_DRX_P0 32

SATA_DTX_C_IRX_N1 28

SATA_DTX_C_IRX_P1 28 SATA_ITX_C_DRX_N1 28

SATA_ITX_C_DRX_P1 28

R482

R482 10K_0402_5%

10K_0402_5%

1 2

4M SPI ROM FOR HM55 (ME code & BIOS code) SA000021A00 MXIC SA00003K800 Winbond SA00003IN00 E-ON

CS#

WP#

GND

MX25L3205DM2I-12G_SO8

+3VS

C460

1 2

0.1U_0402_16V4Z

VCC

HOLD#

SCLK

Title

Size Document Number Rev

Custom

Date: Sheet of

0.1U_0402_16V4Z

SPI_HOLD# SPI_CLK_PCH

SPI_SI

Compal Electronics, Inc.

IBEX-M(1/6)-HDA/JTAG/SATA

HDD

SSD

SATA_DTX_C_IRX_N4 37 SATA_DTX_C_IRX_P4 37 SATA_ITX_DRX_N4_CONN 37 SATA_ITX_DRX_P4_CONN 37

LA-5941P

E-SATA

SPI_CLK_PCH

R100

33_0402_5%

22P_0402_50V8J

13 50Thursday, April 08, 2010

C138

0.3

PCIE PORT LIST

DEVICEPORT

NEW CARD

WLAN

LAN

3 4

D D

WLAN

LAN

C C

WLAN

B B

LAN

A A

10/6 Remove Express card

PCIE_PRX_DTX_N228 PCIE_PRX_DTX_P228 PCIE_PTX_C_DRX_N228 PCIE_PTX_C_DRX_P228

PCIE_PRX_DTX_N329 PCIE_PRX_DTX_P329 PCIE_PTX_C_DRX_N329 PCIE_PTX_C_DRX_P329

PCIE_PRX_DTX_N428 PCIE_PRX_DTX_P428 PCIE_PTX_C_DRX_N428 PCIE_PTX_C_DRX_P428

C230 0.1U_0402_10V6KC230 0.1U_0402_10V6K

1 2

C229 0.1U_0402_10V6KC229 0.1U_0402_10V6K

1 2

C223 0.1U_0402_10V6KC223 0.1U_0402_10V6K

1 2

C222 0.1U_0402_10V6KC222 0.1U_0402_10V6K

1 2

C231 0.1U_0402_10V6K

1 2

C232 0.1U_0402_10V6K

1 2

3G@

3G@ 3G@

3G@

10/6 Remove Express card CLK

R431 10K_0402_5%R431 10K_0402_5%

+3VALW

CLK_PCIE_WLAN1#28 CLK_PCIE_WLAN128

WLAN_CLKREQ1#28

CLK_PCIE_LAN#29 CLK_PCIE_LAN29

CLKREQ_LAN#29

CLK_PCIE_CARD_PCH#28 CLK_PCIE_CARD_PCH28

PCIECLKREQ3#28

+3VALW

1 2

R196 0_0402_5%R196 0_0402_5%

1 2

R197 0_0402_5%R197 0_0402_5%

1 2

R454 10K_0402_5%R454 10K_0402_5%

1 2

+3VS

R220 0_0402_5%R220 0_0402_5%

1 2

R221 0_0402_5%R221 0_0402_5%

1 2

R113 10K_0402_5%R113 10K_0402_5%

1 2

+3VS

R223 0_0402_5%3G@R223 0_0402_5%3G@

1 2

R222 0_0402_5%3G@R222 0_0402_5%3G@

1 2

R120 10K_0402_5%R120 10K_0402_5%

1 2

R435 10K_0402_5%R435 10K_0402_5%

1 2

R434 10K_0402_5%R434 10K_0402_5%

1 2

R457 10K_0402_5%R457 10K_0402_5%

1 2

PCIE_PRX_DTX_N2 PCIE_PRX_DTX_P2 PCIE_PTX_DRX_N2 PCIE_PTX_DRX_P2

PCIE_PRX_DTX_N3 PCIE_PRX_DTX_P3 PCIE_PTX_DRX_N3 PCIE_PTX_DRX_P3

PCIE_PRX_DTX_N4 PCIE_PRX_DTX_P4 PCIE_PTX_DRX_N4 PCIE_PTX_DRX_P4

GPIO73 = NATIVE,3.3V,SUS

CLK_PCIE_WLAN1#_R CLK_PCIE_WLAN1_R

GPIO18 = NATIVE,3.3V,CORE

CLK_PCIE_LAN#_R CLK_PCIE_LAN_R

GPIO20 = NATIVE,3.3V,CORE

CLK_PCIE_CARD_PCH#_R CLK_PCIE_CARD_PCH_R

GPIO25 = NATIVE,3.3V,SUS

GPIO26 = NATIVE,3.3V,SUS

GPIO44 = NATIVE,3.3V,SUS

GPIO56 = NATIVE,3.3V,SUS

GPIO73

GPIO26

GPIO44

GPIO56

U7B

BG30

PERN1

BJ30

PERP1

BF29

PETN1

BH29

PETP1

AW30

PERN2

BA30

PERP2

BC30

PETN2

BD30

PETP2

AU30

PERN3

AT30

PERP3

AU32

PETN3

AV32

PETP3

BA32

PERN4

BB32

PERP4

BD32

PETN4

BE32

PETP4

BF33

PERN5

BH33

PERP5

BG32

PETN5

BJ32

PETP5

BA34

PERN6

AW34

PERP6

BC34

PETN6

BD34

PETP6

AT34

PERN7

AU34

PERP7

AU36

PETN7

AV36

PETP7

BG34

PERN8

BJ34

PERP8

BG36

PETN8

BJ36

PETP8

AK48

CLKOUT_PCIE0N

AK47

CLKOUT_PCIE0P

PCIECLKRQ0# / GPIO73

AM43

CLKOUT_PCIE1N

AM45

CLKOUT_PCIE1P

PCIECLKRQ1# / GPIO18

AM47

CLKOUT_PCIE2N

AM48

CLKOUT_PCIE2P

PCIECLKRQ2# / GPIO20

AH42

CLKOUT_PCIE3N

AH41

CLKOUT_PCIE3P

PCIECLKRQ3# / GPIO25

AM51

CLKOUT_PCIE4N

AM53

CLKOUT_PCIE4P

PCIECLKRQ4# / GPIO26

AJ50

CLKOUT_PCIE5N

AJ52

CLKOUT_PCIE5P

PCIECLKRQ5# / GPIO44

AK53

CLKOUT_PEG_B_N

AK51

CLKOUT_PEG_B_P

P13

PEG_B_CLKRQ# / GPIO56

IBEXPEAK-M_FCBGA1071

NEW CARD

WLAN

LAN

MINI1

SML0ALERT# / GPIO60

SML1ALERT# / GPIO74

SMBus

PCI-E*

Link

Controller

PEG_A_CLKRQ# / GPIO47

PEG

CLKOUT_DP_N / CLKOUT_BCLK1_N CLKOUT_DP_P / CLKOUT_BCLK1_P

From CLK BUFFER

CLKIN_SATA_N / CKSSCD_N CLKIN_SATA_P / CKSSCD_P

CLKIN_PCILOOPBACK

CLKOUTFLEX0 / GPIO64

CLKOUTFLEX1 / GPIO65

CLKOUTFLEX2 / GPIO66

CLKOUTFLEX3 / GPIO67

Clock Flex

SMBALERT# / GPIO11

SMBCLK

SMBDATA

SML0CLK

SML0DATA

SML1CLK / GPIO58

SML1DATA / GPIO75

CL_CLK1

CL_DATA1

CL_RST1#

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_BCLK_N CLKIN_BCLK_P

CLKIN_DOT_96N CLKIN_DOT_96P

REFCLK14IN

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

LID_OUT#

H14

J14

M14

E10

G12

T13

T11

AD43 AD45

AN4 AN2

AT1 AT3

AW24 BA24

AP3 AP1

F18 E18

AH13 AH12

P41

J42

AH51 AH53

AF38

T45

P43

T42

N50

GPIO11 = NATIVE,3.3V,SUS

SMBCLK

SMBDATA

GPIO60 = NATIVE,3.3V,SUS

GPIO60

SML0CLK

SML0DATA

GPIO74 = NATIVE,3.3V,SUS

GPIO74

SML1CLK

R79

SML1DATA

R80

PEG_CLKREQ#

GPIO47 = 10Kohm PULL DOWN

CLKOUT_DP_N CLKOUT_DP_P

CLK_14M_PCH

CLK_PCI_FB

XTAL25_IN XTAL25_OUT

CLK_PCI_DB_R

GPIO67

1 2

CLK_PCIE_VGA#_R CLK_PCIE_VGA_R

CLK_EXP#_R CLK_EXP_R

R491 90.9_0402_1%R491 90.9_0402_1%

1 2

For CR 48M CLK

EC_LID_OUT# 34

R407

R407 0_0402_5%

0_0402_5%

DTS , read from EC

PEG_CLKREQ# 19

R41210K_0402_5% @R41210K_0402_5% @

R524 0_0402_5%R524 0_0402_5%

1 2

R525 0_0402_5%R525 0_0402_5%

1 2

R105 0_0402_5%R105 0_0402_5%

1 2

R106 0_0402_5%R106 0_0402_5%

1 2

T24 PADT24 PAD T25 PADT25 PAD

CLK_DMI# 12 CLK_DMI 12

CLK_BUF_BCLK# 12 CLK_BUF_BCLK 12

CLK_BUF_DOT96# 12 CLK_BUF_DOT96 12

CLK_BUF_CKSSCD# 12 CLK_BUF_CKSSCD 12

CLK_14M_PCH 12

CLK_PCI_FB 16

+1.05VS

R198

22_0402_5%

T9 PADT9 PAD

EC_SMB_CK2

EC_SMB_DA2

CLK_PCIE_VGA# CLK_PCIE_VGA

CLK_PCI_DB 28

SMB_CLK_S3

SMB_DATA_S3

Q8B

EC_SMB_CK2 31,34

EC_SMB_DA2 31,34

CLK_PCIE_VGA# 19

2N7002DW-T/R7_SOT363-6

CLK_EXP# 5 CLK_EXP 5

EMI REQUEST 0303

1 2

R121 10K_0402_5%R121 10K_0402_5%

1 2

R406 10K_0402_5%R406 10K_0402_5%

+3VS

6 1

2N7002DW-T/R7_SOT363-6

Q8A

EC_THERMAL

CLK_PCIE_VGA 19

Q7B

2N7002DW-T/R7_SOT363-6

R209

R209 22_0402_5%

22_0402_5%

1 2 2

C263

C263 10P_0402_50V8J

10P_0402_50V8J

HYBRID@

CLK_14M_PCHCLK_PCI_FB

SMB_CLK_S3

SMB_DATA_S3

SMBCLK

+3VS +3VALW

SMBDATA

SML0CLK

SML0DATA

SML1CLK

SML1DATA

GPIO74

LID_OUT#

GPIO60

SMB_CLK_S3 10,11,12,28

SMB_DATA_S3 10,11,12,28

SMBDATA

+3VS_DELAY

2.2K_0402_5%

HYBRID@

Q7A

6 1

2N7002DW-T/R7_SOT363-6

R413

R413 22_0402_5%

22_0402_5%

SVT

1 2

C439

C439 10P_0402_50V8J

10P_0402_50V8J

1 2

R123 2.2K_0402_5%R123 2.2K_0402_5%

1 2

R78 2.2K_0402_5%R78 2.2K_0402_5%

1 2

R148 2.2K_0402_5%R148 2.2K_0402_5%

1 2

R147 2.2K_0402_5%R147 2.2K_0402_5%

1 2

R404 2.2K_0402_5%R404 2.2K_0402_5%

1 2

R403 2.2K_0402_5%R403 2.2K_0402_5%

1 2

R399 10K_0402_5%R399 10K_0402_5%

1 2

R145 10K_0402_5%R145 10K_0402_5%

1 2

R400 10K_0402_5%R400 10K_0402_5%

R122

R122 0_0402_5%

0_0402_5%

1 2

0_0402_5%

0_0402_5% R119

R119

+3VS_DELAY

R124

HYBRID@

XTAL25_IN

XTAL25_OUT

Nvidia Thermal sensor

R82

2.2K_0402_5%

HYBRID@

SMB_EC_DA2_REC_SMB_DA2

SMB_EC_CK2_REC_SMB_CK2

DDR3*2 AND CLK GEN

SMB_CLK_S3SMBCLK

SMB_DATA_S3

SMB_EC_DA2_R 19

SMB_EC_CK2_R 19

1 2

R598 1M_0402_5%R598 1M_0402_5%

1 2

25MHZ_20PF_7A25000012

C630

C630 27P_0402_50V8J

27P_0402_50V8J

18->27pF, PVT Y4 resize 5032

C631

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/01/13 2011/01/13

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

IBEX-M(2/6)-PCI-E/SMBUS/CLK

LA-5941P

14 50Thursday, April 08, 2010

0.3

D D

DMI_CTX_PRX_N06 DMI_CTX_PRX_N16 DMI_CTX_PRX_N26 DMI_CTX_PRX_N36

DMI_CTX_PRX_P06 DMI_CTX_PRX_P16 DMI_CTX_PRX_P26 DMI_CTX_PRX_P36

DMI_CRX_PTX_N06 DMI_CRX_PTX_N16 DMI_CRX_PTX_N26 DMI_CRX_PTX_N36

DMI_CRX_PTX_P06 DMI_CRX_PTX_P16 DMI_CRX_PTX_P26 DMI_CRX_PTX_P36

+1.05VS

1 2

R520 49.9_0402_1%R520 49.9_0402_1%

4mil width and place within 500mil of the PCH

C C

Checklist0.8：MEPWROK can be connect to PWROK if iAMT d isable

VGATE34,48

ICH_POK34

R396 0.01U_0402_16V7KR396 0.01U_0402_16V7K

R398 0_0402_5%@R398 0_0402_5%@

R397 0_0402_5%@R397 0_0402_5%@

1 2

(2009,05,04)

PM_DRAM_PWRGD5

R401

+3VALW

SUS_PWR_DN_ACK34

+3VALW

R450 10K_0402_5%R450 10K_0402_5%

1 2

AC_PRESENT34

B B

+3VALW

R401

R437 10K_0402_5%R437 10K_0402_5%

1 2

R599 0_0402_5%R599 0_0402_5%

PBTN_OUT#34

GPIO31 = GPI,3. 3V,SUS

R77 8.2K_0402_1%R77 8.2K_0402_1%

1 2

GPIO30 = GPI,3. 3V,SUS

R165 10K_0402_5%R165 10K_0402_5%

1 2

DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3

DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3

DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3

DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3

DMI_IRCOMP

+3VS

R448

10K_0402_5%

SYS_RST#

1 2

SYS_PWROK

R455

0_0402_5%

1 2

R146 10K_0402_5%R146 10K_0402_5%

1 2

PM_DRAM_PWRGD

PM_RSMRST#

10K_0402_5%

SUS_PWR_DN_ACK_R

PBTN_OUT#

AC_PRESENT_R

1 2

R451 0_0402_5%R451 0_0402_5%

GPIO72

U7C

BC24

DMI0RXN

BJ22

DMI1RXN

AW20

DMI2RXN

BJ20

DMI3RXN

BD24

DMI0RXP

BG22

DMI1RXP

BA20

DMI2RXP

BG20

DMI3RXP

BE22

DMI0TXN

BF21

DMI1TXN

BD20

DMI2TXN

BE18

DMI3TXN

BD22

DMI0TXP

BH21

DMI1TXP

BC20

DMI2TXP

BD18

DMI3TXP

BH25

DMI_ZCOMP

BF25

DMI_IRCOMP

SYS_RESET#

SYS_PWROK

B17

PWROK

MEPWROK

A10

LAN_RST#

DRAMPWROK

C16

RSMRST#

SUS_PWR_ DN_ACK / GPIO30

PWRBTN#

ACPRESENT / GPIO31

BATLOW# / GPIO72

F14

RI#

IBEXPEAK-M_FCBGA1071

DMI

FDI

DMI

FDI

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SLP_S5# / GPIO63

System Power Management

SLP_LAN# / GPIO29

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

WAKE#

SUSCLK / GPIO62

SLP_S4#

SLP_S3#

SLP_M#

TP23

PMSYNCH

FDI_CTX_PRX_N0

BA18

FDI_CTX_PRX_N1

BH17

FDI_CTX_PRX_N2

BD16

FDI_CTX_PRX_N3

BJ16

FDI_CTX_PRX_N4

BA16

FDI_CTX_PRX_N5

BE14

FDI_CTX_PRX_N6

BA14

FDI_CTX_PRX_N7

BC12

FDI_CTX_PRX_P0

BB18

FDI_CTX_PRX_P1

BF17

FDI_CTX_PRX_P2

BC16

FDI_CTX_PRX_P3

BG16

FDI_CTX_PRX_P4

AW16

FDI_CTX_PRX_P5

BD14

FDI_CTX_PRX_P6

BB14

FDI_CTX_PRX_P7

BD12

FDI_INT

BJ14

FDI_FSYNC0

BF13

FDI_FSYNC1

BH13

FDI_LSYNC0

BJ12

FDI_LSYNC1

BG14

1K_0402_5%

1 2

R436

PCIE_WAKE#

J12

GPIO32 = GPO,3. 3V,CORE

GPIO61

SUSCLK

P12

BJ10

GPIO29 = GPO,3. 3V,SUS

R436

1 2

R108 10K_0402_5% @R108 10K_0402_5% @

1 2

R180 0_0402_5%R180 0_0402_5%

GPIO61 = NATIVE ,3.3V,SUS

GPIO62 = NATIVE ,3.3V,SUS

Can be left NC when IAMT is not support on the platfrom

If not using in tegrated LAN,signal may be left as NC.

FDI_CTX_PRX_N0 6 FDI_CTX_PRX_N1 6 FDI_CTX_PRX_N2 6 FDI_CTX_PRX_N3 6 FDI_CTX_PRX_N4 6 FDI_CTX_PRX_N5 6 FDI_CTX_PRX_N6 6 FDI_CTX_PRX_N7 6

FDI_CTX_PRX_P0 6 FDI_CTX_PRX_P1 6 FDI_CTX_PRX_P2 6 FDI_CTX_PRX_P3 6 FDI_CTX_PRX_P4 6 FDI_CTX_PRX_P5 6 FDI_CTX_PRX_P6 6 FDI_CTX_PRX_P7 6

FDI_INT 6

FDI_FSYNC0 6

FDI_FSYNC1 6

FDI_LSYNC0 6

FDI_LSYNC1 6

+3VALW

PCIE_WAKE# 28

SVT

+3VS

CLKRUN# 34

PVT

SUSCLK 34

PM_SLP_S5# 34

PM_SLP_S4# 34

PM_SLP_S3# 34

H_PM_SYNC 5

PCH_ENBKL27 PCH_ENVDD27

PCH_EDID_CLK27 PCH_EDID_DATA27

+3VS

12P_0402_50V8J

CRT_HSYNC26 CRT_VSYNC26

PCH_PWM27

R502

2.37K_0402_1%

LVDS_ACLK#27 LVDS_ACLK27

LVDS_A0#27 LVDS_A1#27 LVDS_A2#27

LVDS_A027 LVDS_A127 LVDS_A227

C1214

RF 10/22

DAC_BLU26 DAC_GRN26 DAC_RED26

CRT_DDC_CLK26 CRT_DDC_DATA26

R688

22_0402_5%

HYBRID@

HYBRID@ SD028220A80

SD028220A80

PCH_ENBKL PCH_ENVDD

EDID_CLK EDID_DATA

R497

1 2 1 2

R496 10K_0402_5%R496 10K_0402_5%

T10 PADT10 PAD

R688 33_0402_1%UMA@R688 33_0402_1%UMA@

R687 33_0402_1%UMA@R687 33_0402_1%UMA@

SVT

R687

22_0402_5%

HYBRID@

HYBRID@ SD028220A80

SD028220A80

10K_0402_5%

LVDS_ACLK# LVDS_ACLK

C1215

C1215 12P_0402_50V8J

12P_0402_50V8J

DAC_BLU DAC_GRN DAC_RED

CRT_DDC_CLK CRT_DDC_DATA

12 12

HSYNC VSYNC

CRT_IREF

1K_0402_0.5%

R492

U7D

T48

L_BKLTEN

T47

L_VDD_EN

Y48

L_BKLTCTL

AB48

L_DDC_CL K

Y45

L_DDC_DATA

AB46

L_CTRL_C LK

V48

L_CTRL_D ATA

AP39

LVD_IBG

AP41

LVD_VBG

AT43

LVD_VREFH

AT42

LVD_VREFL

AV53

LVDSA_CLK#

AV51

LVDSA_CLK

BB47

LVDSA_DATA#0

BA52

LVDSA_DATA#1

AY48

LVDSA_DATA#2

AV47

LVDSA_DATA#3

BB48

LVDSA_DATA0

BA50

LVDSA_DATA1

AY49

LVDSA_DATA2

AV48

LVDSA_DATA3

AP48

LVDSB_CLK#

AP47

LVDSB_CLK

AY53

LVDSB_DATA#0

AT49

LVDSB_DATA#1

AU52

LVDSB_DATA#2

AT53

LVDSB_DATA#3

AY51

LVDSB_DATA0

AT48

LVDSB_DATA1

AU50

LVDSB_DATA2

AT51

LVDSB_DATA3

AA52

CRT_BLUE

AB53

CRT_GREEN

AD53

CRT_RED

V51

CRT_DDC_ CLK

V53

CRT_DDC_ DATA

Y53

CRT_HSYNC

Y51

CRT_VSYNC

AD48

DAC_IREF

AB51

CRT_IRTN

IBEXPEAK-M_FCBGA1071

LVDS

CRT

If CRT DAC is not used then a 5% resistor can be used. (checklist 1.6)

SDVO_TVCLKINN

SDVO_TVCLKINP

SDVO_STALLN SDVO_STALLP

SDVO_CTRLCL K

SDVO_CTRLDATA

DDPC_CTR LCLK

DDPC_CTR LDATA

Digital Display Interface

DDPD_CTR LCLK

DDPD_CTR LDATA

SDVO_INTN SDVO_INTP

DDPB_AUXN DDPB_AUXP

DDPB_HPD

DDPB_0N

DDPB_0P

DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

DDPC_AUXN DDPC_AUXP

DDPC_HPD

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

DDPD_AUXN DDPD_AUXP

DDPD_HPD

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

BJ46 BG46

BJ48 BG48

BF45 BH45

T51 T53

BG44 BJ44 AU38

BD42 BC42 BJ42 BG42 BB40 BA40

2.2K_0402_5%

AW38 BA38

HDMICLK_NB

Y49

HDMIDAT_NB

AB49

BE44 BD44 AV40

TMDS_B_DATA2#_PCH

BE40

TMDS_B_DATA2_PCH

BD40

TMDS_B_DATA1#_PCH

BF41

TMDS_B_DATA1_PCH

BH41

TMDS_B_DATA0#_PCH

BD38

TMDS_B_DATA0_PCH

BC38

TMDS_B_CLK#_PCH

BB36

TMDS_B_CLK_PCH

BA36

U50 U52

BC46 BD46 AT38

BJ40 BG40 BJ38 BG38 BF37 BH37 BE36 BD36

R510 100K_0402_5%R510 100K_0402_5%

+3VS

R504

R503

2.2K_0402_5%

UMA@

C638 0.1U_0402_10V6KUMA@C638 0.1U_0402_10V6KUMA@ C639 0.1U_0402_10V6KUMA@C639 0.1U_0402_10V6KUMA@ C640 0.1U_0402_10V6KUMA@C640 0.1U_0402_10V6KUMA@ C641 0.1U_0402_10V6KUMA@C641 0.1U_0402_10V6KUMA@ C642 0.1U_0402_10V6KUMA@C642 0.1U_0402_10V6KUMA@ C643 0.1U_0402_10V6KUMA@C643 0.1U_0402_10V6KUMA@ C644 0.1U_0402_10V6KUMA@C644 0.1U_0402_10V6KUMA@ C645 0.1U_0402_10V6KUMA@C645 0.1U_0402_10V6KUMA@

R675 100K_0402_5%R675 100K_0402_5%

HDMICLK_NB 25 HDMIDAT_NB 25

TMDS_B_HPD 25

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

SVT

HDMI

TMDS_B_DATA2# 25 TMDS_B_DATA2 25 TMDS_B_DATA1# 25 TMDS_B_DATA1 25 TMDS_B_DATA0# 25 TMDS_B_DATA0 25 TMDS_B_CLK# 25 TMDS_B_CLK 25

NC7SZ08P5X_NL_SC70-5

VGATE

ICH_POK

A A

+3VS

Reserved (2009,09,08)

SYS_PWROK

U28

EC_RSMRST#34

RSMRST circuit

R402

@R402

0_0402_5%

1 2

BAV99DW-7_SOT363

D8B

R175

1 2

4.7K_0402_5%

PVT, Common design

PM_RSMRST#

123

Q14

Q14 MMBT3906_SOT23-3

MMBT3906_SOT23-3

1 2

R176 4.7K_0402_5%R176 4.7K_0402_5%

D8A

D8A BAV99DW-7_SOT363

BAV99DW-7_SOT363

+3VALW

Security Classification

THIS SHEET OF ENGINEERING DR AWING IS THE PR OPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PR OPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CON FIDENTIAL AND TRAD E SECRET INFOR MATION. THIS SHEET M AY NOT BE TRANSF ERED FROM T HE CUSTODY OF THE COMPETEN T DIVISION OF R&D

AND TRAD E SECRET INFOR MATION. THIS SHEET M AY NOT BE TRANSF ERED FROM T HE CUSTODY OF THE COMPETEN T DIVISION OF R&D

AND TRAD E SECRET INFOR MATION. THIS SHEET M AY NOT BE TRANSF ERED FROM T HE CUSTODY OF THE COMPETEN T DIVISION OF R&D DEPARTMEN T EXCEPT AS AUT HORIZED BY COMPA L ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INF ORMATION IT CONT AINS

DEPARTMEN T EXCEPT AS AUT HORIZED BY COMPA L ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INF ORMATION IT CONT AINS

DEPARTMEN T EXCEPT AS AUT HORIZED BY COMPA L ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INF ORMATION IT CONT AINS MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, IN C.

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, IN C.

Issued Date

DAC_BLU

DAC_GRN

DAC_RED

EDID_CLK

EDID_DATA

CRT OUT

R493 150_0402_1%R493 150_0402_1%

1 2

R495 150_0402_1%R495 150_0402_1%

1 2

R494 150_0402_1%R494 150_0402_1%

1 2

LVDS EDID

R458 2.2K_0402_5%R458 2.2K_0402_5%

R498 2.2K_0402_5%R498 2.2K_0402_5%

2010/01/13 2011/01/13

+3VS

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

IBEX-M(3/6)-DMI/LVDS/DP/PM

Size Document Number Rev

Custom

Date: Sheet of

LA-5941P

15 50Thursday, April 08, 2010

0.3

+ 35 hidden pages

Lenovo U460 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual