Lenovo Thinkpad X390 Yoga Bumblebee Schematic

5

D D

4

3

2

1

Bumblebee (LBB-1)

Whiskeylake-U Schematics

C C

Project Code: 4PD0G1010001
PCB(Raw Card): 18729-1

Properties of DUMMY: (BOM Control Parts)

Value

B B

(No Value) ASM, assemble

DY

ZZ (No Need to Display)

PCBID

SKUID

DDR4_CTRL

SDP / DDP

APS / ISH / LPC / XDP

A A

NON_PSL / PSL

WLAN_PCIe / WLAN_CNVi

CHARGER_HS / CHARGER_LS

VCCSA_HS / VCCSA_LS

5

Description

DUMMY, NOT ASM, not assemble

ZZ parts for testpoint / shortpad / hole

PCB ID for SW Team (PCB number)

SKU ID for SW Team (CPU Type: non-vPro / vPro)

Memory ID for SW Team (0 = Low / 1 = High Level)MEM_IDx_0 / MEM_IDx_1 (x = 0~4)

Memory Packaging Technology setting (SDP / DDP)

Number of identical die in package (1 = SDP, 2 = DDP)

Debug Connectors (Assemble in 1st build only)

Follow EMC Team requestedEMC

Support / Non Support KBC Power Switched Logic

Support WLAN type (PCIe or CNVi interface)

Charger High / Low Side MOSFET

VCCSA High / Low Side MOSFET

4

2019-05-30

3

LBB-1

LBB-1

LBB-1

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

COVER PAGE

COVER PAGE

COVER PAGE

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A4

A4

A4

Thursday, May 30, 2019

Thursday, May 30, 2019

Thursday, May 30, 2019

Date: Sheet of

Date: Sheet of

Date: Sheet of

2

Bumblebee-1

Bumblebee-1

Bumblebee-1

1 99

1 99

1 99

1

-1

-1

-1

5

Bumblebee-1 Whiskeylake Block Diagram

Project Code: 4PD0G1010001
PCB(Raw Card): 18729-1

Touch Panel

D D

LCD

13.3” FHD/HD

HDMI 1.4b

USB TYPE-C

USB1

USB TYPE-C (CS18 Docking)

DK1

C C

Smart Card Reader

USB TYPE-C

USB1

USB TYPE-A (AOU)

USB3

USB TYPE-A

USB4

USB TYPE-C (CS18 Docking)

DK1

Touch Panel

M.2 WWAN Slot

B B

RBG Camera / IR Camera
DMIC Module

FingerPrint (Optional)

Bluetooth



CNVi WLAN's BT

Reserved

USB TYPE-A (AOU) GEN1

USB3

USB TYPE-A GEN1

USB4

RTC Battery

A A

Active Pen

Power Button

External Connector/Socket
Internal Connector/Socket
Internal Switch

Port 6

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

Port 8

Port 9

Port 10

Port 1

Port 2

Port 3

Port 4

USB 2.0 480Mb/s

55

DP/HDMI Mux
PS8337B

DP

DP/USB Mux
PS8747

Thunderbolt
Alpine Ridge

eDP 1.3 (2 Lanes)

DDI 5.4GT/s

56

Port 2

USB3.1

58

DDI 5.4GT/s

71

25MHz

(X7101)

USB2.0 x10 Ports

USB3.0 x4 Ports

SPI Flash 32MB

TPM 2.0

G-Sensor
Angle Calculate Control
LIS2DH12TR

G-Sensor
Thermal Control
LIS2DWLTR

NFC (Optional)

SM Bus_3B

I2C (PCH_I2C0)

SM Bus_3B

I2C (ISH_I2C0) ISH

25

91

I2C (ISH_I2C0)

70

I2C

70

I2C

90

KBC_PWRBTN#

55

57

75

74

94

75

36

36

74

55

62

66

92

61

36

36

25

93

64

5

Power (3.3V)

KBC_PWRBTN#

ClickPad

65

4

SPI

24MHz

Keyboard/Backlight
TrackPoint

4

CPU

Intel
Whiskeylake-U
Series

vPro/Non-vPro

Clock

PCH-LP

SMBus

65

Generator

4~11,15~23

LPC Bus 24MHz

24

ME

PECI 3.0

Embedded
Controller
NPCE388

DDR4-Memory Down 1

DDR4-Memory Down 2

C-Link 66MHz(Vpro only)

PCI Express x4 Ports

SATA 6Gb/s x1

IHDA

32.768KHz

(X1802)(X1801)

Thermal Sensor
NCT7717U+NCT7718W

FAN

DDR4*2

26

26

3

RESISTOR

Symbol name Size

10KR3

33D3R5

1KR3F

CAPACITOR

Symbol name

SCD1U10V2MX-1

SC10U6D3V5MX

SC2D2U16V5ZY

Value

33.3 Ohm

1K Ohm

Value

10uF

2.2uF

Tolerance

(J: 5%, F: 1%, D: 0.5%, B: 0.1 %)

If no letter, it means J: 5%

F: 1%

Tolerance

(M: +/-20, K: +/-10, Z: +80/-20)

M/X5R

M/X5R

Z/Y5V

Rating The naming rule is value + R + size + tolerance

0402=> 1/16W, 25V
0603 => 1/16W, 75V
0805 => 1/10W, 100V

1/16W, 75V

1/10W, 100V

1/16W, 75V

Rating

10V

6.3V

16V

DESCRIPTION

BOM control parts :
TEXT with PURPLE color near part reference

BOM control name

Part reference
Symbol name

Wireless LAN
Antenna

12

13

2400MT/s

Stereo
Speaker

3

HDA CODEC
Realtek
ALC3287-CG

29

WLAN on board
Jefferson Peak

M.2 1216

Type M M.2 2280-S3

SSD

Internal Mic

27

HP/MIC

30

Audio Jack
(Microphone
/Headphone)

USB Type-C
Adapter

Bluetooth

USB 2.0

Port 10 (BT)

Port 13 (1x)
(Gen 2)
(WLAN)

Port 9 (4x)
(Gen 3)
(SSD)

63

DMIC Module

61

25MHz

(X3101)

66

Battery Charger

2

2=>0402, 3=>0603,
5=>0805, 6=>1206,
0=>1210

060310K Ohm

0805If no letter, it means J: 5%

0603

Size

2=>0402, 3=>0603,
5=>0805, 6=>1206,
0=>1210

04020.1uF

0805

0805

Wireless WAN
Antenna

WWAN

Type B M.2 3042

Port 15 (1x)
(Gen 2)
(WWAN)

Port 14 (1x)
(Gen 2)
(GbE)

GbE PHY
Intel 219LM/V

31 33

SMB Bus

44

3D3V_AUX_S5

2

For the value, it can be read by the number before R. (R means resistor)
For the tolerance, it can be read from the last letter.
For the rating, we don't show on the symbol name.

For the size, R2=>0402, R3=>0603, R5=>0805,....

The naming rule is
Capacitor type + value + rating + size + tolerance + material
SCD1U10V2MX-1
SC=> SMT Ceremic, TC=> POS cap or SP cap
D1U => 0.1uF
10V => the voltage rating is 10V
2=> 0402, 3=>0603, 5=>0805
M=>tolerance M, K, Z
X=> X7R/X5R, Y=> Y5V

-1 => symbol version, nonsense to EE characteristic

Micro SIM Slot

62

USB 2.0

Port 7 (WWAN)

Card Reader
RTS5232S-GR

Micro SD Slot

Port 1 (1x)
(Gen 2)
(Card)

63

33

Main Battery

43

DC/DC
Converter

45

LBB-1

LBB-1

LBB-1

RTC Battery

Title

Title

Title

25

BLOCK DIAGRAM

BLOCK DIAGRAM

BLOCK DIAGRAM

Size Document Num ber Rev

Size Document Num ber Rev

Size Document Num ber Rev

A2

A2

A2

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

PCB Layer Stackup

L1:Component
L2:GND
L3:Signal 1
L4:VCC
L5:Signal 2
L6:Signal 3
L7:GND
L8:Signal 4
L9:GND
L10:Component

Battery Charger/Selector

BQ25700ARSNR

VINT20_IN 19V_DCBATOUT

System DC/DC

TPS51285B

19V_DCBATOUT

DC/DC IMVP8

NCP81218MNTXG

DC/DC VCCCPUCORE

NCP302045LMNTXG

19V_DCBATOUT

DC/DC VCCGT

NCP302045LMNTXG

19V_DCBATOUT

DC/DC VCCSA

NCP81253MNTBG

19V_DCBATOUT

DC/DC 1D2V_S3

NB687GQ-C669-Z

19V_DCBATOUT 1D2V_S3

DC/DC 0D6V_VREF_S0

NB687GQ-C669-Z

1D2V_S3

DC/DC 2D5V_S3

NB687GQ-C669-Z

3D3V_S5

DC/DC 1D05V_SUS

RT8237CZQW

19V_DCBATOUT

DC/DC 1D8V_SUS

RT5797ALGQW

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
Taipei Hsie n 221, Taiwan, R.O. C.

Taipei Hsie n 221, Taiwan, R.O. C.

Taipei Hsie n 221, Taiwan, R.O. C.

Bumblebee-1

Bumblebee-1

Bumblebee-1

1

BT+

5V_S5
3D3V_S5

1V_CPU_CORE

1V_VCCGT

1V_VCCSA

0D6V_VREF_S0

2D5V_S3

1D05V_SUS

1D8V_SUS3D3V_S5

2 99Thursday, May 30, 2019

2 99Thursday, May 30, 2019

2 99Thursday, May 30, 2019

44

45

46

47

48

50

51

51

51

52

53

-1

-1

-1

5

Main Func = CPU

D D

PECI_CPU24
PROCHOT#_CPU24,44,46

[PECI] and [PROCHOT#]
Impedance control: 50 ohm

C C

-TBT_PLUG_EVENT71

4

PROCHOT#_CPU

1D05V_VCCSTG

12

R301

Rb

1KR2J-1-GP

Ra

1 2

R302 499R2F-2-GP

1 2

R328 0R2-PT5-LILY-GP-U

TPAD14-OP-GP
TPAD14-OP-GP
TPAD14-OP-GP
TPAD14-OP-GP

1 2

R319 0R2J-2-GP

1 2

R320 0R2J-2-GP
R304 49D9R2F-GP

R305 49D9R2F-GP

12
12

TP304
TP305
TP302
TP303

1D05V_VCCST

12

R329
49D9R2F-GP

1
1
1
1

3

CATERR#_CPU
PECI_CPU
PROCHOT#_CPU_R
THERMTRIP#_CPUTHERMTRIP#_EC

BPM_CPU_N0
BPM_CPU_N1
BPM_CPU_N2
BPM_CPU_N3

GPP_E3-TBT_PLUG_EVENT

GPP_B4
CPU_POPIRCOMP

PCH_POPIRCOMP

AA4

AR1
BJ1

CE9

CN3
CB34
CC35

BP27

BW25

Y4

U1
U2
U3
U4

CATERR#
PECI
PROCHOT#
THRMTRIP#

BPM#0
BPM#1
BPM#2
BPM#3

GPP_E3/CPU_GP0
GPP_E7/CPU_GP1
GPP_B3/CPU_GP2
GPP_B4/CPU_GP3

PROC_POPIRCOMP
PCH_OPIRCOMP

4 OF 20CPU1D

PROC_TCK

PROC_TDI
PROC_TDO
PROC_TMS

PROC_TRST#

PCH_TCK

PCH_TDI
PCH_TDO
PCH_TMS

PCH_TRST#
PCH_JTAGX

PROC_PREQ#
PROC_PRDY#

T6
U6
Y5
T5
AB6

W6
U5
W5
P5
Y6
P6

W2
W1

2

THERMTRIP#_CPU

PROC_PREQ#
PROC_PRDY#

1D05V_VCCST

PROC_TCK
PROC_TDI
PROC_TDO
PROC_TMS
PROC_TRST#

PCH_JTAG_TCK

12

R308
1KR2J-1-GP

1

BB1_EVT_MAIN_W015

BB1_SVT_MAIN_W008

1D05V_VCCSTG

PROC_TDO

If PCH_TDO is set to Termination, R321 is 100ohm.
If PROC_TDO uesd, R321 is 51ohm.

PROC_TCK
PCH_JTAG_TCK

1 2

R321 100R2J-2-GP

1 2

R322 51R2J-2-GP

1 2

R326 51R2J-2-GP

DY

PROC_TCK99

PROC_TDI99

PROC_TMS99

PROC_TRST#99
PCH_JTAG_TCK99
PROC_TDO99

PROC_PREQ#99
PROC_PRDY#99

THERMTRIP#_EC40

CPU1 will use BOM control to Whiskeylake-U

WHISKEY-LAKE-GP

ZZ.00CPU.271

(#543016) PROCHOT# Routing Guidelines

B B

M1,2,3,4,5: <3 inches
M6: 1-11 inches
MCPU: 0.3-1.5 inches
Mt <0.3 mils
Main route(M1+M2+M3+M4+M5+M6+MCPU): 1-12 inches

A A

5

4

3

2

LBB-1

LBB-1

LBB-1

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

CPU (THML/JTAG)

CPU (THML/JTAG)

CPU (THML/JTAG)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A3

A3

A3

Thursday, May 30, 2019

Thursday, May 30, 2019

Thursday, May 30, 2019

Date: Sheet of

Date: Sheet of

Date: Sheet of

Bumblebee-1

Bumblebee-1

Bumblebee-1

1

3 99

3 99

3 99

-1

-1

-1

Main Func = CPU

5

DP1_DDI_TX_N071
DP1_DDI_TX_P071
DP1_DDI_TX_N171
DP1_DDI_TX_P171
DP1_DDI_TX_N271

DOCK

D D

USBC

C C

DP1_DDI_TX_P271
DP1_DDI_TX_N371

DP1_DDI_TX_P371
DP1_AUX_CPU _N71
DP1_AUX_CPU _P71

DP1_HPD_CP U71

DP2_DDI_TX_N056

DP2_DDI_TX_P056

DP2_DDI_TX_N156

DP2_DDI_TX_P156

DP2_DDI_TX_N256

DP2_DDI_TX_P256

DP2_DDI_TX_N356

DP2_DDI_TX_P356
DP2_AUX_CPU _N56
DP2_AUX_CPU _P56

DP2_HPD_CP U56

eDP_TX_CPU _N055

eDP_TX_CPU _P055

eDP_TX_CPU _N155

eDP_TX_CPU _P155

eDP_AUX_CPU _N55
eDP_AUX_CPU _P55

eDP_HPD_CP U55

Port Strap Enable Port Disable Port

Port 1

L_BKLT_EN24

L_BKLT_CTRL55

EDP_VDD_EN55

GPP_H17_STRA P15

EC_SMI#24

DP2_SCL_CPU56

DP2_SDA_CPU56

WWA N_PERST#62

DDPB_CTRLDATA

Port 2

DDPC_CTRLDATA

TABLE: Functional Strap

DDPB_CTRLDATA
HIGH Port B is detected.
LOW Port B is not detected.

DDPC_CTRLDATA
HIGH Port C is detected.
LOW Port C is not detected.

4

3D3V_SUS

1 2

R407 2K2R2J-2-GP

3D3V_S0

RN402

1
2 3

SRN2K2J-1-G P

1 2

R404 10KR2J-3-GP

DP1_SDA_CPU

DP2_SDA_CPU

4

DP2_SCL_CPU

EC_SMI#

PU to 3.3 V with 2.2-k
±5% resistor

PU to 3.3 V with 2.2-k
±5% resistor

DDI2

SOC

DDI1

3

DP1_DDI_TX_N0
DP1_DDI_TX_P0
DP1_DDI_TX_N1
DP1_DDI_TX_P1
DP1_DDI_TX_N2
DP1_DDI_TX_P2
DP1_DDI_TX_N3
DP1_DDI_TX_P3

DP2_DDI_TX_N0
DP2_DDI_TX_P0
DP2_DDI_TX_N1
DP2_DDI_TX_P1
DP2_DDI_TX_N2
DP2_DDI_TX_P2
DP2_DDI_TX_N3
DP2_DDI_TX_P3

Design Guideline:
Skylake processor signal eDP_RCOMP should be connected to the VCCIO rail via a single 24.9 ±1% Ω resistor.

CHECK WHL design guide: DISP_RCOMP

1D05V_VCCIO

R401
24D9R2F-L-G P

1 2

TPAD14-OP-G P

TP402

eDP_RCOMP_C PU

DP1_SDA_CPU
DP2_SCL_CPU

DP2_SDA_CPU

GPP_E23_STRAP

1

GPP_H17_STRA P

reserved for strap

NC

NC

DEMUX
PS8337B

DP

TMDS

SWITCH
PS8747B

USB TYPE-C

HDMI CONN

For TBT Display

2

AL5

DDI1_TXN0

AL6

DDI1_TXP0

AJ5

DDI1_TXN1

AJ6

DDI1_TXP1

AF6

DDI1_TXN2

AF5

DDI1_TXP2

AE5

DDI1_TXN3

AE6

DDI1_TXP3

AC4

DDI2_TXN0

AC3

DDI2_TXP0

AC1

DDI2_TXN1

AC2

DDI2_TXP1

AE4

DDI2_TXN2

AE3

DDI2_TXP2

AE1

DDI2_TXN3

AE2

DDI2_TXP3

GPP_E13/DDPB_HPD0/DISP_MISC0
GPP_E14/DDPC_HPD1/DISP_MISC1
GPP_E15/DPPD_HPD2/DISP_MISC2
GPP_E16/DPPE_HPD3/DISP_MISC3

GPP_E17/EDP_HPD/DISP_MISC4

AM6

DISP_RCOMP

CC8

GPP_E18/DPPB_CTRLCLK/CNV_BT_HOST_WAKE#

CC9

GPP_E19/DPPB_CTRLDATA

CH4

GPP_E20/DPPC_CTRLCLK

CH3

GPP_E21/DPPC_CTRLDATA

CP4

GPP_E22/DPPD_CTRLCLK

CN4

GPP_E23/DPPD_CTRLDATA

CR26

GPP_H16/DDPF_CTRLCLK

CP26

GPP_H17/DDPF_CTRLDATA

CPU1 will use BOM control to Whiskeylake-U

ZZ.00CPU.271

WHISKEY-LAKE- GP

1 OF 20CPU1A

EDP_TXN0
EDP_TXP0
EDP_TXN1
EDP_TXP1
EDP_TXN2
EDP_TXP2
EDP_TXN3
EDP_TXP3

EDP_AUX_N
EDP_AUX_P

DISP_UTILS

DDI1_AUX_N
DDI1_AUX_P
DDI2_AUX_N
DDI2_AUX_P
DDI3_AUX_N
DDI3_AUX_P

EDP_BKLTEN

EDP_VDDEN

EDP_BKLTCTL

AG4
AG3
AG2
AG1
AJ4
AJ3
AJ2
AJ1

AH4
AH3

AM7
AC7

AC6
AD4
AD3
AG7
AG6

CN6
CM6
CP7
CP6
CM7

CK11
CG11
CH11

eDP_TX_CPU _N0
eDP_TX_CPU _P0
eDP_TX_CPU _N1
eDP_TX_CPU _P1

eDP_AUX_CPU _N
eDP_AUX_CPU _P

EDP_DISP_UTILS
DP1_AUX_CPU _N

DP1_AUX_CPU _P
DP2_AUX_CPU _N
DP2_AUX_CPU _P

DP1_HPD_CP U
DP2_HPD_CP U
WWA N_PERST#
EC_SMI#
eDP_HPD_CP U

L_BKLT_EN
EDP_VDD_EN
L_BKLT_CTRL

1

BB1_EVT_MAIN_W008
BB1_EVT_MAIN_W024

BB1_SIT_MAIN_W026

1

TP401

TPAD14-OP-G P

R406

1 2

100KR2J-1-GP

R403

R402

1 2

1 2

100KR2J-1-GP

R405

1 2

100KR2J-1-GP

100KR2J-1-GP

B B

A A

LBB-1

LBB-1

LBB-1

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
Taipei Hsie n 221, Taiwan, R.O. C.

Taipei Hsie n 221, Taiwan, R.O. C.

Title

Title

Title

CPU (DDI/EDP)

CPU (DDI/EDP)

CPU (DDI/EDP)

Size Document Num ber Rev

Size Document Num ber Rev

Size Document Num ber Rev
A2

A2

A2

Thursday, May 30, 2019

Thursday, May 30, 2019

Thursday, May 30, 2019

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O. C.

Bumblebee-1

Bumblebee-1

Bumblebee-1

1

4 99

4 99

4 99

-1

-1

-1

Main Func = CPU

M_A_DQS_DN0
M_A_DQS_DN1
M_A_DQS_DN2
M_A_DQS_DN3 M_B_DQS_DN3
M_A_DQS_DN4
M_A_DQS_DN5
M_A_DQS_DN6
M_A_DQS_DN7

M_A_DQS_DP0
M_A_DQS_DP1
M_A_DQS_DP2
M_A_DQS_DP3
M_A_DQS_DP4
M_A_DQS_DP5
M_A_DQS_DP6

M_A_DQ[0:7]

M_A_DQ[8:15]

M_A_DQ[16:23]

M_A_DQ[24:31]

M_A_DQ[32:39]

M_A_DQ[40:47]

M_A_DQ[48:55]

M_A_DQ[56:63]

M_A_DQS_DP7

M_A_DQ012
M_A_DQ112
M_A_DQ212
M_A_DQ312
M_A_DQ412
M_A_DQ512
M_A_DQ612
M_A_DQ712
M_A_DQ812
M_A_DQ912
M_A_DQ1012
M_A_DQ1112
M_A_DQ1212
M_A_DQ1312
M_A_DQ1412
M_A_DQ1512
M_A_DQ1612
M_A_DQ1712
M_A_DQ1812
M_A_DQ1912
M_A_DQ2012
M_A_DQ2112
M_A_DQ2212
M_A_DQ2312
M_A_DQ2412
M_A_DQ2512
M_A_DQ2612
M_A_DQ2712
M_A_DQ2812
M_A_DQ2912
M_A_DQ3012
M_A_DQ3112
M_A_DQ3212
M_A_DQ3312
M_A_DQ3412
M_A_DQ3512
M_A_DQ3612
M_A_DQ3712
M_A_DQ3812
M_A_DQ3912
M_A_DQ4012
M_A_DQ4112
M_A_DQ4212
M_A_DQ4312
M_A_DQ4412
M_A_DQ4512
M_A_DQ4612
M_A_DQ4712
M_A_DQ4812
M_A_DQ4912
M_A_DQ5012
M_A_DQ5112
M_A_DQ5212
M_A_DQ5312
M_A_DQ5412
M_A_DQ5512
M_A_DQ5612
M_A_DQ5712
M_A_DQ5812
M_A_DQ5912
M_A_DQ6012
M_A_DQ6112
M_A_DQ6212
M_A_DQ6312

D D

C C

5

M_A_DQS_DN[7:0] 12 M_B_DQS_DN[7:0] 13

M_A_DQS_DP[7:0] 12

M_A_CS#0 12
M_A_ACT_N 12
M_A_ALERT_N 12

M_A_CLK#0 12
M_A_CLK0 12
M_A_CKE0 12

M_A_BA0 12
M_A_BA1 12

M_A_ODT0 12
V_SM_VREF_CNTA 12 V_SM_VREF_CNTB 13
M_A_BG0 12
M_A_PARITY 12
M_A_BG1 12

SM_DRAMRST# 12,13
VTT_CNTL 51

M_B_DQS_DN0
M_B_DQS_DN1
M_B_DQS_DN2

M_B_DQS_DN4
M_B_DQS_DN5
M_B_DQS_DN6
M_B_DQS_DN7

M_B_DQS_DP0
M_B_DQS_DP1
M_B_DQS_DP2
M_B_DQS_DP3
M_B_DQS_DP4
M_B_DQS_DP5
M_B_DQS_DP6
M_B_DQS_DP7

M_B_DQ013
M_B_DQ113
M_B_DQ213
M_B_DQ313
M_B_DQ413
M_B_DQ513
M_B_DQ613
M_B_DQ713
M_B_DQ813
M_B_DQ913
M_B_DQ1013
M_B_DQ1113
M_B_DQ1213
M_B_DQ1313
M_B_DQ1413
M_B_DQ1513
M_B_DQ1613
M_B_DQ1713
M_B_DQ1813
M_B_DQ1913
M_B_DQ2013
M_B_DQ2113
M_B_DQ2213
M_B_DQ2313
M_B_DQ2413
M_B_DQ2513
M_B_DQ2613
M_B_DQ2713
M_B_DQ2813
M_B_DQ2913
M_B_DQ3013
M_B_DQ3113
M_B_DQ3213
M_B_DQ3313
M_B_DQ3413
M_B_DQ3513
M_B_DQ3613
M_B_DQ3713
M_B_DQ3813
M_B_DQ3913
M_B_DQ4013
M_B_DQ4113
M_B_DQ4213
M_B_DQ4313
M_B_DQ4413
M_B_DQ4513
M_B_DQ4613
M_B_DQ4713
M_B_DQ4813
M_B_DQ4913
M_B_DQ5013
M_B_DQ5113
M_B_DQ5213
M_B_DQ5313
M_B_DQ5413
M_B_DQ5513
M_B_DQ5613
M_B_DQ5713
M_B_DQ5813
M_B_DQ5913
M_B_DQ6013
M_B_DQ6113
M_B_DQ6213
M_B_DQ6313

M_B_DQS_DP[7:0] 13

M_B_CS#0 13
M_B_ACT_N 13
M_B_ALERT_N 13

M_B_CLK#0 13
M_B_CLK0 13
M_B_CKE0 13

M_B_BA0 13
M_B_BA1 13

M_B_ODT0 13
M_B_BG0 13

M_B_PARITY 13
M_B_BG1 13

M_B_DQ[63:0] 13M_A_DQ[63:0] 12

4

DDR4 ball type: Non-Interleaved Type

DDR4(IL) / LPDDR3-DDR4(NIL)

DDR0_D QSN0/DDR 0_DQSN0
DDR0_D QSP0/DD R0_DQS P0
DDR0_D QSN1/DDR 0_DQSN1
DDR0_D QSP1/DD R0_DQS P1
DDR0_D QSN2/DDR 0_DQSN4
DDR0_D QSP2/DD R0_DQS P4
DDR0_D QSN3/DDR 0_DQSN5
DDR0_D QSP3/DD R0_DQS P5
DDR0_D QSN4/DDR 1_DQSN0
DDR0_D QSP4/DD R1_DQS P0
DDR0_D QSN5/DDR 1_DQSN1
DDR0_D QSP5/DD R1_DQS P1
DDR0_D QSN6/DDR 1_DQSN4
DDR0_D QSP6/DD R1_DQS P4
DDR0_D QSN7/DDR 1_DQSN5
DDR0_D QSP7/DD R1_DQS P5

ZZ.00CPU.271

2 OF 20CPU1B

DDR0_C KN0/DDR0 _CKN0
DDR0_C KP0/DDR 0_CKP0
DDR0_C KN1/DDR0 _CKN1
DDR0_C KP1/DDR 0_CKP1

DDR0_C KE0/DDR 0_CKE0
DDR0_C KE1/DDR 0_CKE1

DDR0_C KE2/NC
DDR0_C KE3/NC

DDR0_C S#0/DDR 0_CS#0
DDR0_C S#1/DDR 0_CS#1
DDR0_O DT0/DDR 0_ODT0

NC/DDR0_ ODT1

LPDDR3 / DDR4

DDR0_C AB9/DDR 0_MA0
DDR0_C AB8/DDR 0_MA1
DDR0_C AB5/DDR 0_MA2

NC/DDR0_ MA3

NC/DDR0_ MA4
DDR0_C AA0/DDR 0_MA5
DDR0_C AA2/DDR 0_MA6
DDR0_C AA4/DDR 0_MA7
DDR0_C AA3/DDR 0_MA8
DDR0_C AA1/DDR 0_MA9

DDR0_C AB7/DDR 0_MA10
DDR0_C AA7/DDR 0_MA11
DDR0_C AA6/DDR 0_MA12
DDR0_C AB0/DDR 0_MA13

DDR0_C AB2/DDR 0_MA14
DDR0_C AB1/DDR 0_MA15
DDR0_C AB3/DDR 0_MA16

DDR0_C AB4/DDR 0_BA0
DDR0_C AB6/DDR 0_BA1
DDR0_C AA5/DDR 0_BG0

DDR0_C AA8/DDR 0_ACT#

DDR0_C AA9/DDR 0_BG1

LPDDR3 / DDR4

NC/DDR0_ ALERT#

NC/DDR0_ PAR

DDR_VR EF_CA
DDR0_V REF_DQ 0
DDR0_V REF_DQ 1

DDR1_V REF_DQ

DDR_VT T_CTL

WHISKEY-LAKE-GP

DDR4(IL) / LPDDR3-DDR4(NIL) LPDDR3 / DDR4

M_A_DQ0

A26

DDR0_D Q0/DDR0 _DQ0

M_A_DQ1

D26

DDR0_D Q1/DDR0 _DQ1

M_A_DQ2

D28

DDR0_D Q2/DDR0 _DQ2

M_A_DQ3

C28

DDR0_D Q3/DDR0 _DQ3

M_A_DQ4

M_A_DQ[0:7]

M_A_DQ[8:15]

M_A_DQ[32:39]

M_A_DQ[40:47]

M_B_DQ[0:7]

M_B_DQ[8:15]

M_B_DQ[32:39]

M_B_DQ[40:47]

DQ Bit Swapping is allowed within the same byte, and Byte Swapping is allowed within the same channel.
Clock (CLK and CLK#) and Strobe (DQS and DQS#) differential signal swapping within a pair is not allowed. Also differential
clock pair to clock pair swapping within a channel is not allowed.

M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47

B26
C26
B28
A28
B30
D30
B33
D32
A30
C30
B32
C32
H37
H34
K34
K35
H36
H35
K36
K37
N36
N34
R37
R34
N37
N35
R36

R35
AN35
AN34
AR35
AR34
AN37
AN36
AR36
AR37
AU35
AU34

AW35
AW34

AU37
AU36

AW36
AW37

BA35
BA34
BC35
BC34
BA37
BA36
BC36
BC37
BE35
BE34
BG35
BG34
BE37
BE36
BG36
BG37

DDR0_D Q4/DDR0 _DQ4
DDR0_D Q5/DDR0 _DQ5
DDR0_D Q6/DDR0 _DQ6
DDR0_D Q7/DDR0 _DQ7
DDR0_D Q8/DDR0 _DQ8
DDR0_D Q9/DDR0 _DQ9
DDR0_D Q10/DDR 0_DQ10
DDR0_D Q11/DDR 0_DQ11
DDR0_D Q12/DDR 0_DQ12
DDR0_D Q13/DDR 0_DQ13
DDR0_D Q14/DDR 0_DQ14
DDR0_D Q15/DDR 0_DQ15
DDR0_D Q16/DDR 0_DQ32
DDR0_D Q17/DDR 0_DQ33
DDR0_D Q18/DDR 0_DQ34
DDR0_D Q19/DDR 0_DQ35
DDR0_D Q20/DDR 0_DQ36
DDR0_D Q21/DDR 0_DQ37
DDR0_D Q22/DDR 0_DQ38
DDR0_D Q23/DDR 0_DQ39
DDR0_D Q24/DDR 0_DQ40
DDR0_D Q25/DDR 0_DQ41
DDR0_D Q26/DDR 0_DQ42
DDR0_D Q27/DDR 0_DQ43
DDR0_D Q28/DDR 0_DQ44
DDR0_D Q29/DDR 0_DQ45
DDR0_D Q30/DDR 0_DQ46
DDR0_D Q31/DDR 0_DQ47
DDR0_D Q32/DDR 1_DQ0
DDR0_D Q33/DDR 1_DQ1
DDR0_D Q34/DDR 1_DQ2
DDR0_D Q35/DDR 1_DQ3
DDR0_D Q36/DDR 1_DQ4
DDR0_D Q37/DDR 1_DQ5
DDR0_D Q38/DDR 1_DQ6
DDR0_D Q39/DDR 1_DQ7
DDR0_D Q40/DDR 1_DQ8
DDR0_D Q41/DDR 1_DQ9
DDR0_D Q42/DDR 1_DQ10
DDR0_D Q43/DDR 1_DQ11
DDR0_D Q44/DDR 1_DQ12
DDR0_D Q45/DDR 1_DQ13
DDR0_D Q46/DDR 1_DQ14
DDR0_D Q47/DDR 1_DQ15
DDR0_D Q48/DDR 1_DQ32
DDR0_D Q49/DDR 1_DQ33
DDR0_D Q50/DDR 1_DQ34
DDR0_D Q51/DDR 1_DQ35
DDR0_D Q52/DDR 1_DQ36
DDR0_D Q53/DDR 1_DQ37
DDR0_D Q54/DDR 1_DQ38
DDR0_D Q55/DDR 1_DQ39
DDR0_D Q56/DDR 1_DQ40
DDR0_D Q57/DDR 1_DQ41
DDR0_D Q58/DDR 1_DQ42
DDR0_D Q59/DDR 1_DQ43
DDR0_D Q60/DDR 1_DQ44
DDR0_D Q61/DDR 1_DQ45
DDR0_D Q62/DDR 1_DQ46
DDR0_D Q63/DDR 1_DQ47

CPU1 will use BOM control to Whiskeylake-U

V32
V31
T32
T31

U36
U37
U34
U35

AE32
AF32
AE31
AF31

AC37
AC36
AC34
AC35
AA35
AB35
AA37
AA36
AB34
W36
Y31
W34
AA34
AC32

AC31
AB32
Y32

W32
AB31
V34

V35
W35

C27
D27
D31
C31
J35
J34
P34
P35
AP35
AP34
AV34
AV35
BB35
BB34
BF34
BF35

W37
W31
F36
D35
D37
E36
C35

M_A_CLK#0
M_A_CLK0

M_A_CKE0

M_A_CS#0
M_A_ODT0

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13

M_A_A14
M_A_A15
M_A_A16

M_A_BA0
M_A_BA1
M_A_BG0

M_A_ACT_N
M_A_BG1

M_A_DQS_DN0
M_A_DQS_DP0
M_A_DQS_DN1
M_A_DQS_DP1
M_A_DQS_DN4
M_A_DQS_DP4
M_A_DQS_DN5
M_A_DQS_DP5
M_B_DQS_DN0
M_B_DQS_DP0
M_B_DQS_DN1
M_B_DQS_DP1
M_B_DQS_DN4
M_B_DQS_DP4
M_B_DQS_DN5
M_B_DQS_DP5

M_A_ALERT_N
M_A_PARITY
V_SM_VREF_CNTA

V_SM_VREF_CNTB
SM_PGCNTL

M_A_DQS0

M_A_DQS1

M_A_DQS4

M_A_DQS5

M_B_DQS0

M_B_DQS1

M_B_DQS4

M_B_DQS5

3

common part

SM_PGCNTL

Q501
PJA138KA-GP

G

S

084.00138.0A31

D

M_A_DQ[16:23]

M_A_DQ[24:31]

M_A_DQ[48:55]

M_A_DQ[56:63]

M_B_DQ[16:23]

M_B_DQ[24:31]

M_B_DQ[48:55]

M_B_DQ[56:63]

3D3V_S01D2V_S3

12

R506
220KR2F-GP

VTT_CNTL

M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

J22
H25
G22
H22
F25

J25
G25
F22
D22
C22
C24
D24
A22
B22
A24
B24
G31
G32
H29
H28
G28
G29
H31
H32

L31

L32
N29
N28

L28

L29
N31
N32

AJ29
AJ30
AM32
AM31
AM30
AM29
AJ31
AJ32
AR31
AR32
AV30
AV29
AR30
AR29
AV32
AV31
BA32
BA31
BD31
BD32
BA30
BA29
BD29
BD30
BG31
BG32
BK32
BK31
BG29
BG30
BK30
BK29

2

3 OF 20CPU1C

DDR1_D Q0/DDR0 _DQ16
DDR1_D Q1/DDR0 _DQ17
DDR1_D Q2/DDR0 _DQ18
DDR1_D Q3/DDR0 _DQ19
DDR1_D Q4/DDR0 _DQ20
DDR1_D Q5/DDR0 _DQ21
DDR1_D Q6/DDR0 _DQ22
DDR1_D Q7/DDR0 _DQ23
DDR1_D Q8/DDR0 _DQ24
DDR1_D Q9/DDR0 _DQ25
DDR1_D Q10/DDR 0_DQ26
DDR1_D Q11/DDR 0_DQ27
DDR1_D Q12/DDR 0_DQ28
DDR1_D Q13/DDR 0_DQ29
DDR1_D Q14/DDR 0_DQ30
DDR1_D Q15/DDR 0_DQ31
DDR1_D Q16/DDR 0_DQ48
DDR1_D Q17/DDR 0_DQ49
DDR1_D Q18/DDR 0_DQ50
DDR1_D Q19/DDR 0_DQ51
DDR1_D Q20/DDR 0_DQ52
DDR1_D Q21/DDR 0_DQ53
DDR1_D Q22/DDR 0_DQ54
DDR1_D Q23/DDR 0_DQ55
DDR1_D Q24/DDR 0_DQ56
DDR1_D Q25/DDR 0_DQ57
DDR1_D Q26/DDR 0_DQ58
DDR1_D Q27/DDR 0_DQ59
DDR1_D Q28/DDR 0_DQ60
DDR1_D Q29/DDR 0_DQ61
DDR1_D Q30/DDR 0_DQ62
DDR1_D Q31/DDR 0_DQ63
DDR1_D Q32/DDR 1_DQ16
DDR1_D Q33/DDR 1_DQ17
DDR1_D Q34/DDR 1_DQ18
DDR1_D Q35/DDR 1_DQ19
DDR1_D Q36/DDR 1_DQ20
DDR1_D Q37/DDR 1_DQ21
DDR1_D Q38/DDR 1_DQ22
DDR1_D Q39/DDR 1_DQ23
DDR1_D Q40/DDR 1_DQ24
DDR1_D Q41/DDR 1_DQ25
DDR1_D Q42/DDR 1_DQ26
DDR1_D Q43/DDR 1_DQ27
DDR1_D Q44/DDR 1_DQ28
DDR1_D Q45/DDR 1_DQ29
DDR1_D Q46/DDR 1_DQ30
DDR1_D Q47/DDR 1_DQ31
DDR1_D Q48/DDR 1_DQ48
DDR1_D Q49/DDR 1_DQ49
DDR1_D Q50/DDR 1_DQ50
DDR1_D Q51/DDR 1_DQ51
DDR1_D Q52/DDR 1_DQ52
DDR1_D Q53/DDR 1_DQ53
DDR1_D Q54/DDR 1_DQ54
DDR1_D Q55/DDR 1_DQ55
DDR1_D Q56/DDR 1_DQ56
DDR1_D Q57/DDR 1_DQ57
DDR1_D Q58/DDR 1_DQ58
DDR1_D Q59/DDR 1_DQ59
DDR1_D Q60/DDR 1_DQ60
DDR1_D Q61/DDR 1_DQ61
DDR1_D Q62/DDR 1_DQ62
DDR1_D Q63/DDR 1_DQ63

CPU1 will use BOM control to Whiskeylake-U

DDR1_C KN0/DDR1 _CKN0
DDR1_C KP0/DDR 1_CKP0
DDR1_C KN1/DDR1 _CKN1
DDR1_C KP1/DDR 1_CKP1

DDR1_C KE0/DDR 1_CKE0
DDR1_C KE1/DDR 1_CKE1

DDR1_C S#0/DDR 1_CS#0
DDR1_C S#1/DDR 1_CS#1

DDR1_O DT0/DDR 1_ODT0

DDR1_C AB9/DDR 1_MA0
DDR1_C AB8/DDR 1_MA1
DDR1_C AB5/DDR 1_MA2

DDR1_C AA0/DDR 1_MA5
DDR1_C AA2/DDR 1_MA6
DDR1_C AA4/DDR 1_MA7
DDR1_C AA3/DDR 1_MA8

DDR1_C AA1/DDR 1_MA9
DDR1_C AB7/DDR 1_MA10
DDR1_C AA7/DDR 1_MA11
DDR1_C AA6/DDR 1_MA12
DDR1_C AB0/DDR 1_MA13

DDR1_C AB2/DDR 1_MA14
DDR1_C AB1/DDR 1_MA15
DDR1_C AB3/DDR 1_MA16

DDR1_C AB4/DDR 1_BA0

DDR1_C AB6/DDR 1_BA1

DDR1_C AA5/DDR 1_BG0

DDR1_C AA9/DDR 1_BG1
DDR1_C AA8/DDR 1_ACT#

DDR4(IL) / LPDDR3-DDR4(NIL)

DDR1_D QSN0/DDR 0_DQSN2
DDR1_D QSP0/DD R0_DQS P2
DDR1_D QSN1/DDR 0_DQSN3
DDR1_D QSP1/DD R0_DQS P3
DDR1_D QSN2/DDR 0_DQSN6
DDR1_D QSP2/DD R0_DQS P6
DDR1_D QSN3/DDR 0_DQSN7
DDR1_D QSP3/DD R0_DQS P7
DDR1_D QSN4/DDR 1_DQSN2
DDR1_D QSP4/DD R1_DQS P2
DDR1_D QSN5/DDR 1_DQSN3
DDR1_D QSP5/DD R1_DQS P3
DDR1_D QSN6/DDR 1_DQSN6
DDR1_D QSP6/DD R1_DQS P6
DDR1_D QSN7/DDR 1_DQSN7
DDR1_D QSP7/DD R1_DQS P7

ZZ.00CPU.271

LPDDR3 / DDR4DDR4(IL) / LPDDR3-DDR4(NIL)

DDR1_C KE2/NC
DDR1_C KE3/NC

LPDDR3 / DDR4

NC/DDR1_ ODT1

NC/DDR1_ MA3
NC/DDR1_ MA4

NC/DDR1_ ALERT#

NC/DDR1_ PAR

DRAM_RE SET#

DDR_RC OMP0
DDR_RC OMP1
DDR_RC OMP2

WHISKEY-LAKE-GP

M_B_CLK#0

AF28

M_B_CLK0

AF29
AE28
AE29

M_B_CKE0

T28
T29
V28
V29

M_B_CS#0

AL37
AL35

M_B_ODT0

AL36
AL34

M_B_A0

AG36

M_B_A1

AG35

M_B_A2

AF34

M_B_A3

AG37

M_B_A4

AE35

M_B_A5

AF35

M_B_A6

AE37

M_B_A7

AC29

M_B_A8

AE36

M_B_A9

AB29

M_B_A10

AG34

M_B_A11

AC28

M_B_A12

AB28

M_B_A13

AK35

M_B_A14

AJ35

M_B_A15

AK34

M_B_A16

AJ34

M_B_BA0

AJ37

M_B_BA1

AJ36

M_B_BG0

W29

M_B_BG1

Y28

M_B_ACT_N

W28

M_A_DQS_DN2

H24

M_A_DQS_DP2

G24
C23
D23
G30
H30
L30
N30
AL31
AL30
AU31
AU30
BC31
BC30
BH31
BH30

Y29
AE34
BU31

BN28
BN27
BN29

Layout Note:

M_A_DQS2

M_A_DQS_DN3
M_A_DQS_DP3

M_A_DQS3

M_A_DQS_DN6
M_A_DQS_DP6

M_A_DQS6

M_A_DQS_DN7
M_A_DQS_DP7

M_A_DQS7

M_B_DQS_DN2
M_B_DQS_DP2

M_B_DQS2

M_B_DQS_DN3
M_B_DQS_DP3

M_B_DQS3

M_B_DQS_DN6
M_B_DQS_DP6

M_B_DQS6

M_B_DQS_DN7
M_B_DQS_DP7

M_B_DQS7

M_B_ALERT_N
M_B_PARITY
SM_DRAMRST#_CPU SM_DRAMRST#

SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2

#575412 Rev 1.5
Table 4-8. WHL-U/CFL-U DDR4 x16 Memory Down Routing Guideline (mils)

Design Guideline:
SM_RCOMP_0/1/2 keep routing length less than 500 mils.

#575412 Rev 1.5
Table 4-8. WHL-U/CFL-U DDR4 x16 Memory Down Routing Guideline (mils)

DDR - DDR4 X 16 Memory Down
DDR_RCOMP[0]: 121Ω ±1% on pkg to VSS
DDR_RCOMP[1]: 80.6Ω ±1% on pkg to VSS
DDR_RCOMP[2]: 100Ω ±1% on pkg to VSS

1 2

R501 121R2F-GP

1 2

R502 80D6R2F-L-GP

1 2

R503 100R2F-L1-GP-U

1D2V_S3

12

R505
470R2F-GP

R504
0R2J-2-GP

1 2

1

BB1_EVT_MAIN_W032
BB1_EVT_MAIN_W044

BB1_FVT_MAIN_W017

12

DY

C501

SCD1U6D3V1KX-GP

M_A_A012
M_A_A112
M_A_A212
M_A_A312
M_A_A412
M_A_A512
M_A_A612
M_A_A712
M_A_A812
M_A_A912

B B

A A

M_A_A1012
M_A_A1112
M_A_A1212
M_A_A1312
M_A_A1412
M_A_A1512
M_A_A1612

M_A_A[16:0] 12 M_B_A[16:0] 13

M_B_A013
M_B_A113
M_B_A213
M_B_A313
M_B_A413
M_B_A513
M_B_A613
M_B_A713
M_B_A813

M_B_A913
M_B_A1013
M_B_A1113
M_B_A1213
M_B_A1313
M_B_A1413
M_B_A1513
M_B_A1613

5

LBB-1

LBB-1

LBB-1

Title

Title

Title

CPU(CFG/IST)

CPU(CFG/IST)

CPU(CFG/IST)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A1

A1

A1

Thursday, May 30, 2019

Thursday, May 30, 2019

Thursday, May 30, 2019

Date: Sheet of

Date: Sheet of

4

3

2

Date: Sheet of

1

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Bumblebee-1

Bumblebee-1

Bumblebee-1

5 99

5 99

5 99

-1

-1

-1

5

4

3

2

1

Main Func = CPU

PCH strap pin:

CFG315,99
CFG415

D D

ITP_PMODE99

C C

CFG3
CFG4

CFG3 CFG4

WHL QS/CFL/WHL_ES1_CNL U

T4

CFG0

R4

CFG1

T3

CFG2

AB5

CG2
CG1

BV24
BV25

BK36
BK35

AM4
AM3

R3

J4

M4

J3

M3

R2
N2
R1
N1

J2

L2

J1

L1
L3

N3
L4
N4

W4

H4
H3

W3

CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15

CFG16
CFG18
CFG17
CFG19

CFG_RCOMP
ITP_PMODE
RSVD#CG2

RSVD#CG1

RSVD#H4
RSVD#H3

RSVD#BV24
RSVD#BV25

RSVD#BK36
RSVD#BK35

RSVD#W3
RSVD#AM4

RSVD_TP#AM3

CFG3
CFG4

CFG_RCOM P

12

R60149D9R2F-G P

ITP_PMODE

17 OF 20CPU1Q

RSVD_TP#F37
RSVD_TP#F34

IST_TRIG

RSVD_TP#CN36

RSVD_TP#BJ36
RSVD_TP#BJ34

TP#BK34
TP#BR18

RSVD_TP#BT9
RSVD_TP#BT8

RSVD_TP#BP8
RSVD_TP#BP9

RSVD#CR4
RSVD#CP3

RSVD#CR3

RSVD_TP#AT3
RSVD_TP#AU3

RSVD#AN1
RSVD#AN2

RSVD#AN4
RSVD#AN3

IST_TP0
IST_TP1

IST_TRIG0
IST_TRIG1

TP#BP34
TP#BP35

RSVD_TP#CR35

F37
F34

IST_TRIG

CP36
CN36

BJ36
BJ34

BK34
BR18

BT9
BT8

BP8
BP9

CR4
CP3

CR3

AT3
AU3

AN1
AN2

AN4
AN3

AL2
AL1

AL4
AL3

BP34
BP36

VSS

BP35

RVSD_TP

CR35

1

TP620

1

TP621 TPAD14-OP-G P

TPAD14-OP-G P

E1

SKTOCC#

WHISKEY-LAKE- GP

ZZ.00CPU.271

CPU1 will use BOM control to Whiskeylake-U

B B

A A

5

4

3

SKTOCC#

1

TP619 TPAD14-OP-G P

2

LBB-1

LBB-1

LBB-1

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
Taipei Hsie n 221, Taiwan, R.O. C.

Taipei Hsie n 221, Taiwan, R.O. C.

Title

Title

Title

CPU(CFG/IST)

CPU(CFG/IST)

CPU(CFG/IST)

Size Document Num ber Rev

Size Document Num ber Rev

Size Document Num ber Rev
A2

A2

A2

Thursday, May 30, 2019

Thursday, May 30, 2019

Thursday, May 30, 2019

Date: Sheet of

Date: Sheet of

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O. C.

Bumblebee-1

Bumblebee-1

Bumblebee-1

1

6 99

6 99

6 99

-1

-1

-1

Main Func = CPU

VCCCORE_SENSE46
VSSCORE_SENSE46

SVID_DATA_CPU46
SVID_CLK_CPU46

SVID_ALERT#_CPU46

D D

C C

5

1V_CPU_CORE 1V_CPU_CORE

AN9

VCCCOR E

AN10

VCCCOR E

AN24

VCCCOR E

AN26

VCCCOR E

AN27

VCCCOR E

AP2

VCCCOR E

AP9

VCCCOR E

AP24

VCCCOR E

AP26

VCCCOR E

AR5

VCCCOR E

AR6

VCCCOR E

AR7

VCCCOR E

AR8

VCCCOR E

AR10

VCCCOR E

AR25

VCCCOR E

AR27

VCCCOR E

AT9

VCCCOR E

AT24

VCCCOR E

AT26

VCCCOR E

AU5

VCCCOR E

AU6

VCCCOR E

AU7

VCCCOR E

AU8

VCCCOR E

AU9

VCCCOR E

AU24

VCCCOR E

AU25

VCCCOR E

AU26

VCCCOR E

AU27

VCCCOR E

AV2

VCCCOR E

AV5

VCCCOR E

AV7

VCCCOR E

AV10

VCCCOR E

AV27

VCCCOR E

AW5

VCCCOR E

AW6

VCCCOR E

AW7

VCCCOR E

AW8
AW9

AW10

BB9

BC24

AY9

BB24

CPU1 will use BOM control to Whiskeylake-U

VCCCOR E
VCCCOR E
VCCCOR E

RSVD#B B9
RSVD#B C24
RSVD#A Y9
RSVD#B B24

WHISKEY-LAKE-GP

ZZ.00CPU.271

VCC_SE NSE
VSS_SE NSE

12 OF 20CPU1L

VCCCOR E
VCCCOR E
VCCCOR E
VCCCOR E
VCCCOR E
VCCCOR E
VCCCOR E
VCCCOR E
VCCCOR E
VCCCOR E
VCCCOR E
VCCCOR E
VCCCOR E
VCCCOR E
VCCCOR E
VCCCOR E
VCCCOR E
VCCCOR E
VCCCOR E
VCCCOR E
VCCCOR E
VCCCOR E
VCCCOR E
VCCCOR E
VCCCOR E
VCCCOR E
VCCCOR E
VCCCOR E
VCCCOR E
VCCCOR E
VCCCOR E
VCCCOR E
VCCCOR E
VCCCOR E
VCCCOR E

VIDALE RT#

VIDSCK
VIDSOUT
RSVD#Y3
VCCSTG

AW24
AW25
AW26
AW27
AY24
AY26
BA5
BA7
BA8
BA25
BA27
BB2
BB26
BC5
BC6
BC7
BC9
BC10
BC26
BC27
BD5
BD8
BD10
BD25
BD27
BE9
BE24
BE25
BE26
BE27
BF2
BF9
BF24
BF26
BG27

AN6
AN5

AA3
AA1
AA2
Y3
BG3

4

VCCCORE_SENSE
VSSCORE_SENSE

SVID_ALERT#_CPU_R

SVID_CLK_CPU_R
SVID_DATA_CPU_R

1D05V_VCCSTG

Layout Note:
The total Length of Data and Clock (from CPU to each VR) mu st be equal (±0.1 inch).
Route the Alert signal betwee n the Clock and the Data signa ls.

R709
0R2-PT5-LILY-GP-U

SVID_DATA_CPU_R

SVID_CLK_CPU_R

SVID_ALERT#_CPU_R

1 2

R732
0R2-PT5-LILY-GP-U

1 2

R728
220R2J-L2-GP

12

SVID DATA

SVID CLOCK

SVID ALERT

1D05V_VCCST

1D05V_VCCST

1D05V_VCCST

12

R726
100R2F-L1-GP-U

12

DY

R723
54D9R2F-L1-GP

12

R727
56R2J-4-GP

3

#544669
CLOSE TO CPU

SVID_DATA_CPU

#544669
CLOSE TO VR

SVID_CLK_CPU

#544669
CLOSE TO CPU

SVID_ALERT#_CPU

2

1V_CPU_CORE

12

R719
100R2F-L1-GP-U

VCCCORE_SENSE
VSSCORE_SENSE

12

R720
100R2F-L1-GP-U

Layout Note:

1. Place close to CPU

2. VCC_SENSE/ VSS_SENSE
impedance=50 ohm

3. Length match<25mil

1

BB1_SVT_MAIN_W008

B B

A A

LBB-1

LBB-1

LBB-1

Title

Title

Title

CPU(VCC_CORE)

CPU(VCC_CORE)

CPU(VCC_CORE)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A1

A1

A1

Thursday, May 30, 2019

Thursday, May 30, 2019

Thursday, May 30, 2019

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

1

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Bumblebee-1

Bumblebee-1

Bumblebee-1

7 99

7 99

7 99

-1

-1

-1

Main Func = CPU

5

4

3

2

1

BB1_EVT_MAIN_W032

BB1_FVT_MAIN_W017

BB1_SIT_MAIN_W014

D D

VCCGT_SEN SE46
VSSGT_SENSE46

VSSSA_SENSE46
VCCSA_SENS E46

C C

B B

1V_VCCGT

WHL QS/CFL/WHL_ES1_CNL U

A5

VCCGT

A6

VCCGT

A8

VCCGT

A11

VCCGT

A12

VCCGT

A14

VCCGT

A15

VCCGT

A17

VCCGT

A18

VCCGT

A20

VCCGT

B3

VCCGT

B4

VCCGT

B6

VCCGT

B8

VCCGT

B11

VCCGT

B14

VCCGT

B17

VCCGT

B20

VCCGT

C2

VCCGT

C3

VCCGT

C6

VCCGT

C7

VCCGT

C8

VCCGT

C11

VCCGT

C12

VCCGT

C14

VCCGT

C15

VCCGT

C17

VCCGT

C18

VCCGT

C20

VCCGT

D4

VCCGT

D7

VCCGT

D11

VCCGT

D12

VCCGT

D14

VCCGT

D15

VCCGT

D17

VCCGT

D18

VCCGT

D20

VCCGT

E4

VCCGT

F5

VCCGT

F6

VCCGT

F7

VCCGT

F8

VCCGT

F11

VCCGT

F14

VCCGT

F17

VCCGT

F20

VCCGT

G11

VCCGT

G12

VCCGT

G14

VCCGT

G15

VCCGT

G17

VCCGT

G18

VCCGT

G20

VCCGT

H5

VCCGT

H6

VCCGT

H7

VCCGT

H8

VCCGT

H11

VCCGT

VCCGT_SENSE
VSSGT_SENSE

WHISKEY-LAKE- GP

ZZ.00CPU.271

CPU1 will use BOM control to Whiskeylake-U

VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE

13 OF 20CPU1M

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

H12
H14
H15
H17
H18
H20
J7
J8
J11
J14
J17
J20
K2
K11
L7
L8
L10
M9
N7
N8
N9
N10
P2
P8
R9
T8
T9
T10
U8
U10
V9
W8
W9
AA9
AB2
AB8
AB9
AB10
AC8
AD9
AE8
AE9
AE10
AF2
AF8
AF10
AG8
AG9
AH9
AJ8
AJ10
AK2
AK9
AL8
AL9
AL10
AM8
V2
Y8
Y10
E3
D2

1V_VCCGT

VCCGT_SEN SE
VSSGT_SENSE

1V_CPU_COR E

1V_VCCGT

12

12

R807
100R2F-L1-GP- U

VSSGT_SENSE VSSSA_SENSE

R808
100R2F-L1-GP- U

1D2V_S3

14 OF 20CPU 1N

VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA

1V_VCCIO (ICCMAX.=2.73A

1D05V_VCCIO

AK24
AK26
AL24
AL25
AL26
AL27
AM25
AM27
BH24
BH25
BH26
BH27
BJ24
BJ26
BP16
BP18

BG8
BG10
BH9
BJ8
BJ9
BJ10
BK8
BK25
BK27
BL8
BL9
BL10
BL24
BL26
BM24
BN25

BP28
BP29

VSSSA_SENSE

BE7

VCCSA_SENS E

BG7

1V_VCCSA

12

DY

C804

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

RSVD#BC28
VCCST

VCCST

VCCSTG
VCCSTG

VCCPLL_OC
VCCPLL_OC

VCCPLL
VCCPLL

ZZ.00CPU.271

VCCIO_OUT
VCCIO_OUT
VCCIO_OUT
VCCIO_OUT
VCCIO_OUT
VCCIO_OUT
VCCIO_OUT
VCCIO_OUT
VCCIO_OUT
VCCIO_OUT
VCCIO_OUT
VCCIO_OUT
VCCIO_OUT
VCCIO_OUT
VCCIO_OUT
VCCIO_OUT

VCCIO_SENSE
VSSIO_SENSE

VSSSA_SENSE
VCCSA_SENSE

WHISKEY-LAKE- GP

AD36
AH32
AH36
AM36
AN32

AW32

AY36
BE32
BH36

BC28
BP11

BL27

BM26

BR11
BT11

R32

Y36

BP2

BG1
BG2

1D05V_VCCST

12

C801 SC1U6D3V1MX- GP

1D05V_VCCST G

12

C802 SC1U6D3V1MX- GP

1D2V_VCCSF R_OC

12

C803 SC1U6D3V1MX- GP

1D05V_VCCST

SC1U6D3V1MX-GP

0.04 A

0.12 A

12

12

C808

C805

C807

SC22U6D3V2MX-GP-U

SC22U6D3V2MX-GP-U

WHL VCCPLL Power CAPs:
Intel PDG recommended
1 x 22uF/47uF 0805

=> LBB-1 Layout impact:
2 x 22uF 0402

1V_VCCSA

12

R810
100R2F-L1-GP- U

VCCSA_SENS EVCCGT_SEN SE

12

R809
100R2F-L1-GP- U

C806

1 2

1 2

SC1U6D3V1MX-GP

SCD1U6D3V1KX-GP

CPU1 will use BOM control to Whiskeylake-U

A A

LBB-1

LBB-1

LBB-1

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
Taipei Hsie n 221, Taiwan, R.O. C.

Taipei Hsie n 221, Taiwan, R.O. C.

Title

Title

Title

CPU(VDDQ/VCC/VCCST/VCCSTG)

CPU(VDDQ/VCC/VCCST/VCCSTG)

CPU(VDDQ/VCC/VCCST/VCCSTG)

Size Document Num ber Rev

Size Document Num ber Rev

Size Document Num ber Rev
A2

A2

A2

Thursday, May 30, 2019

Thursday, May 30, 2019

Thursday, May 30, 2019

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O. C.

Bumblebee-1

Bumblebee-1

Bumblebee-1

1

8 99

8 99

8 99

-1

-1

-1

5

D D

C C

4

3

2

1

BLANK

B B

LBB-1

LBB-1

LBB-1

Wistron Corporation

Wistron Corporation

A A

Title

Title

Title

CPU (RSVD)

CPU (RSVD)

CPU (RSVD)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A4

A4

A4

Thursday, May 30, 2019

Thursday, May 30, 2019

Thursday, May 30, 2019

Date: Sheet of

Date: Sheet of

5

4

3

Date: Sheet of

2

Bumblebee-1

Bumblebee-1

Bumblebee-1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

-1

-1

9 99

9 99

9 99

1

-1

5

4

3

2

1

Main Func = CPU

1V_CPU_COR E

12

PC1007

DY

SC22U6D3V3MX- 1-GP

12

PC1037
SC22U6D3V3MX- 1-GP

12

PC1008

DY

SC22U6D3V3MX- 1-GP

12

PC1040
SC22U6D3V3MX- 1-GP

12

DY

PC1009
SC22U6D3V3MX- 1-GP

12

DY

PC1048

SC22U6D3V3MX- 1-GP

12

PC1004
SC22U6D3V3MX- 1-GP

12

PC1034
SC22U6D3V3MX- 1-GP

12

PC1044

DY

SC22U6D3V3MX- 1-GP

12

DY

PC1049
SC22U6D3V3MX- 1-GP

12

PC1005
SC22U6D3V3MX- 1-GP

12

PC1035
SC22U6D3V3MX- 1-GP

12

PC1006

DY

SC22U6D3V3MX- 1-GP

12

PC1036
SC22U6D3V3MX- 1-GP

12

PC1001
SC22U6D3V3MX- 1-GP

D D

1V_VCCSA

12

PC1045
SC22U6D3V3MX- 1-GP

1V_VCCGT

12

PC1031
SC22U6D3V3MX- 1-GP

1V_VCCGT

12

C C

PC1041
SC22U6D3V3MX- 1-GP

12

PC1002
SC22U6D3V3MX- 1-GP

12

PC1046

SC22U6D3V3MX- 1-GP

12

PC1032
SC22U6D3V3MX- 1-GP

12

PC1042
SC22U6D3V3MX- 1-GP

12

12

PC1047
SC22U6D3V3MX- 1-GP

12

12

DY

PC1003
SC22U6D3V3MX- 1-GP

PC1033
SC22U6D3V3MX- 1-GP

PC1043
SC22U6D3V3MX- 1-GP

1D05V_VCCIO1D05V_SUS1D05V_SUS 1D2V_S31D05V_SUS 1D 05V_SUS

+VCCIO(ICCMAX.=2.73A)

12

C1001

SC22U6D3V3MX-L1-GP

B B

A A

12

12

C1002

SC22U6D3V3MX-L1-GP

12

12

DY

C1003

C1004

C1005

SC22U6D3V3MX-L1-GP

SC22U6D3V3MX-L1-GP

SC22U6D3V3MX-L1-GP

5

12

12

C1006

C1007

SC22U6D3V3MX-L1-GP

SC22U6D3V3MX-L1-GP

4

12

12

DY

C1009

C1008

SC22U6D3V3MX-L1-GP

SC22U6D3V3MX-L1-GP

LBB-1

LBB-1

LBB-1

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
Taipei Hsie n 221, Taiwan, R.O. C.

Taipei Hsie n 221, Taiwan, R.O. C.

Title

Title

Title

CPU (POWER CAP1)

CPU (POWER CAP1)

CPU (POWER CAP1)

Size Document Num ber Rev

Size Document Num ber Rev

Size Document Num ber Rev
A2

A2

A2

Thursday, May 30, 2019

Thursday, May 30, 2019

Thursday, May 30, 2019

Date: Sheet of

Date: Sheet of

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O. C.

Bumblebee-1

Bumblebee-1

Bumblebee-1

1

10 99

10 99

10 99

-1

-1

-1

5

VCORE WHL U42

1V_CPU_CORE

12

12

12

D D

C1101

C1102

C1103

12

C1104

12

12

C1105

C1106

4

12

C1107

12

12

C1109

12

C1110

C1108

3

2

BB1_EVT_MAIN_W032

BB1_FVT_MAIN_W017

1

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

VCCGT WHL U42

1V_VCCGT

12

12

SC1U6D3V1MX-GP

C C

C1112

12

C1113

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

C1114

12

SC1U6D3V1MX-GP

C1115

12

12

C1116

SC1U6D3V1MX-GP

C1117

SC1U6D3V1MX-GP

VCCSA WHL U42

1V_VCCSA

12

SC1U6D3V1MX-GP

B B

C1118

12

12

C1119

SC1U6D3V1MX-GP

C1120

SC1U6D3V1MX-GP

1D2V_S3

1D05V_VCCIO1D05V_SUS 1D05V_SUS1D05V_SUS1D05V_SUS

+VCCIO (ICCMAX.=2.73A)

12

C1121

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

A A

12

12

C1122

SC1U6D3V1MX-GP

5

C1123

12

SC1U6D3V1MX-GP

C1124

12

12

C1125

SC1U6D3V1MX-GP

DY

C1126

SC10U6D3V3MX-GP

4

12

SCD1U6D3V1KX-GP

C1130

12

SCD1U6D3V1KX-GP

C1131

12

SCD1U6D3V1KX-GP

3

C1132

12

C1133

SCD1U6D3V1KX-GP

12

SC1U6D3V1MX-GP

C1134

12

12

C1135

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

C1136

12

DY

C1137

SC1U6D3V1MX-GP

LBB-1

LBB-1

LBB-1

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

CPU (POWER CAP2)

CPU (POWER CAP2)

CPU (POWER CAP2)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A3

A3

A3

Thursday, May 30, 2019

Thursday, May 30, 2019

Thursday, May 30, 2019

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Bumblebee-1

Bumblebee-1

Bumblebee-1

1

11 99

11 99

11 99

-1

-1

-1

M_A_DQS_DN[7:0] 5

M_A_DQS_DP[7:0] 5

M_A_DQ[63:0] 5

M_A_A[16:0] 5

5

TEST_MODE_1
TEST_MODE_2
TEST_MODE_3
TEST_MODE_4

1D2V_S3

1
1
1
1

1D2V_S3

2D5V_S3

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_A16

M_A_CS#0
SM_DRAMRST#
M_A_ACT_N
M_A_ALERT_N

M_A_CLK0
M_A_CLK#0

M_A_CKE0

M_A_BA0
M_A_BA1

1 2

R1222 1K8R2F-GP

1 2

R1223 1K8R2F-GP

TP1201TPAD14-OP-GP
TP1202TPAD14-OP-GP
TP1203TPAD14-OP-GP
TP1204TPAD14-OP-GP

RAM1

B3

VDD

B9

VDD

D1

VDD

G7

VDD

J1

VDD

J9

VDD

L1

VDD

L9

VDD

R1

VDD

T9

VDD

A1

VDDQ

A9

VDDQ

C1

VDDQ

D9

VDDQ

F2

VDDQ

F8

VDDQ

G1

VDDQ

G9

VDDQ

J2

VDDQ

J8

VDDQ

B1

VPP

R9

VPP

NF/LDM#/LDB I#

P3

A0

NF/UDM#/UDBI#

P7

A1

R3

A2

N7

A3

N3

A4

P8

A5

P2

A6

R8

A7

R2

A8

R7

A9

M3

A10/AP

T2

A11

M7

A12/BC#

T8

A13

L2

WE#/A1 4

M8

CAS#/A1 5

L8

RAS#/A1 6

L7

CS#

P1

RESET#

L3

ACT#

P9

ALERT#

K7

CK_T

K8

CK_C

K2

CKE

N2

BA0

N8

BA1

MT40A512M16HA-083EA-GP

072.40512.0A0U

M_A_VREF_CA V_SM_VREF_CNTA

G2

DQ0

F7

DQ1

H3

DQ2

H7

DQ3

H2

DQ4

H8

DQ5

J3

DQ6

J7

DQ7

A3

DQ8

B8

DQ9

C3

DQ10

C7

DQ11

C2

DQ12

C8

DQ13

D3

DQ14

D7

DQ15

B7

UDQS_T

A7

UDQS_C

G3

LDQS_T

F3

LDQS_C

E7
E2

K3

ODT

F9

ZQ

M1

VREFCA

M2

BG0

N9

TEN

T3

PAR

T7

NC#T7

B2

VSS

E1

VSS

E9

VSS

G8

VSS

K1

VSS

K9

VSS

M9

VSS

N1

VSS

T1

VSS

A2

VSSQ

A8

VSSQ

C9

VSSQ

D2

VSSQ

D8

VSSQ

E3

VSSQ

E8

VSSQ

F1

VSSQ

H1

VSSQ

H9

VSSQ

R1202 2D7R2F-1-GP

M_A_DQ59
M_A_DQ61
M_A_DQ62
M_A_DQ56
M_A_DQ58
M_A_DQ57
M_A_DQ63
M_A_DQ60
M_A_DQ53
M_A_DQ50
M_A_DQ48
M_A_DQ54
M_A_DQ52
M_A_DQ51
M_A_DQ49
M_A_DQ55

M_A_DQS_DP6
M_A_DQS_DN6

M_A_DQS_DP7
M_A_DQS_DN7

M_A_ODT0
DDR4_ZQ_RAM1
M_A_VREF_CA
M_A_BG0
TEST_MODE_1
M_A_PARITY

M_A_BG1_E9_1

M_A_BG1_M9_R

1 2

Main Func = DIMM1

M_A_DQS_DN0
M_A_DQS_DN1
M_A_DQS_DN2
M_A_DQS_DN3
M_A_DQS_DN4
M_A_DQS_DN5
M_A_DQS_DN6
M_A_DQS_DN7

M_A_DQS_DP0
M_A_DQS_DP1
M_A_DQS_DP2
M_A_DQS_DP3

D D

M_A_DQS_DP4
M_A_DQS_DP5
M_A_DQS_DP6
M_A_DQS_DP7

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48

C C

M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_A16

M_A_CS#05
SM_DRAMRST#5,13
M_A_ACT_N5
M_A_ALERT_N5

M_A_CLK05
M_A_CLK#05
M_A_CKE05

M_A_BA05
M_A_BA15

M_A_ODT05
V_SM_VREF_CNTA5
M_A_BG05
M_A_PARITY5

B B

M_A_BG15

1D2V_S3

SCD047U25V2KX-GP

12

C1202
SCD022U16V2KX-3GP

V_VREF_PATHA

12

R1203
24D9R2F-L-GP

4

1D2V_S3

RAM2

B3

VDD

B9

VDD

D1

VDD

G7

VDD

J1

VDD

J9

VDD

L1

VDD

L9

VDD

R1

VDD

T9

VDD

A1

VDDQ

A9

VDDQ

C1

VDDQ

D9

VDDQ

F2

VDDQ

F8

VDDQ

G1

VDDQ

G9

VDDQ

J2

VDDQ

J8

2D5V_S3

12

12

C1236

R1205

240R2D-GP

VDDQ

B1

VPP

R9

VPP

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_A16

M_A_CS#0
SM_DRAMRST#
M_A_ACT_N
M_A_ALERT_N

M_A_CLK0
M_A_CLK#0

M_A_CKE0

M_A_BA0
M_A_BA1

SDP & DDP SETTING

R1212~R1215:
DDP: 240 ohm (64.24005.6DL)
SDP: 0 ohm (63.R0034.1DL)

NF/LDM#/LDB I#

P3

A0

NF/UDM#/UDBI#

P7

A1

R3

A2

N7

A3

N3

A4

P8

A5

P2

A6

R8

A7

R2

A8

R7

A9

M3

A10/AP

T2

A11

M7

A12/BC#

T8

A13

L2

WE#/A1 4

M8

CAS#/A1 5

L8

RAS#/A1 6

L7

CS#

P1

RESET#

L3

ACT#

P9

ALERT#

K7

CK_T

K8

CK_C

K2

CKE

N2

BA0

N8

BA1

MT40A512M16HA-083EA-GP

072.40512.0A0U

DDR4_CTRL

M_A_BG1_E9_1

1 2

R1212 240R2F-1-GP

DDR4_CTRL

M_A_BG1_E9_2

1 2

R1213 240R2F-1-GP

DDR4_CTRL

M_A_BG1_E9_3

1 2

R1214 240R2F-1-GP

DDR4_CTRL

M_A_BG1_E9_4

1 2

R1215 240R2F-1-GP

M_A_BG1 M_A_BG1_M9_R

1 2

R1220 0R2J-2-GP

1 2

R1221 0R2J-2-GP

M_A_DQ42

G2

DQ0

M_A_DQ41

F7

DQ1

M_A_DQ46

H3

DQ2

M_A_DQ44

H7

DQ3

M_A_DQ43

H2

DQ4

M_A_DQ40

H8

DQ5

M_A_DQ47

J3

DQ6

M_A_DQ45

J7

DQ7

M_A_DQ37

A3

DQ8

M_A_DQ36

B8

DQ9

M_A_DQ34

C3

DQ10

M_A_DQ38

C7

DQ11

M_A_DQ32

C2

DQ12

M_A_DQ33

C8

DQ13

M_A_DQ39

D3

DQ14

M_A_DQ35

D7

DQ15

M_A_DQS_DP4

B7

UDQS_T

M_A_DQS_DN4

A7

UDQS_C

M_A_DQS_DP5

G3

LDQS_T

M_A_DQS_DN5

F3

LDQS_C

E7
E2

M_A_ODT0

K3

ODT

DDR4_ZQ_RAM2

F9

ZQ

M_A_VREF_CA

M1

VREFCA

M_A_BG0

M2

BG0

TEST_MODE_2

N9

TEN

M_A_PARITY

T3

PAR

T7

NC#T7

B2

VSS

E1

VSS

M_A_BG1_E9_2

E9

VSS

G8

VSS

K1

VSS

K9

VSS

M_A_BG1_M9_R

M9

VSS

N1

VSS

T1

VSS

A2

VSSQ

A8

VSSQ

C9

VSSQ

D2

VSSQ

D8

VSSQ

E3

VSSQ

E8

VSSQ

F1

VSSQ

H1

VSSQ

H9

VSSQ

DDP
SDP

1D2V_S3

3

1D2V_S3

RAM3

B3

VDD

B9

VDD

D1

VDD

G7

VDD

J1

VDD

J9

VDD

L1

VDD

L9

VDD

R1

VDD

T9

VDD

A1

VDDQ

A9

VDDQ

C1

VDDQ

D9

VDDQ

F2

VDDQ

F8

VDDQ

G1

VDDQ

G9

VDDQ

J2

VDDQ

J8

2D5V_S3

12

12

C1286

R1234

240R2D-GP

SCD047U25V2KX-GP

M_A_BG1_M9_R

R1224 36R2F-1-GP

M_A_A16

R1211 36R2F-1-GP

M_A_A5
M_A_BA1
M_A_A3
M_A_A10

M_A_A12
M_A_BG0
M_A_A15
M_A_ACT_N

M_A_CS#0
M_A_A14
M_A_CKE0
M_A_ODT0

M_A_A11
M_A_A8
M_A_A9
M_A_A2

M_A_A13
M_A_PARITY
M_A_A7
M_A_A0

M_A_BA0
M_A_A1
M_A_A4
M_A_A6

VDDQ

B1

VPP

R9

VPP

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_A16

M_A_CS#0
SM_DRAMRST#
M_A_ACT_N
M_A_ALERT_N

M_A_CLK0
M_A_CLK#0

M_A_CKE0

M_A_BA0
M_A_BA1

DDP

1 2
1 2

RN1202

1
2
3
4 5

SRN36J-GP

RN1203

1
2
3
4 5

SRN36J-GP

RN1204

1
2
3
4 5

SRN36J-GP

RN1205

1
2
3
4 5

SRN36J-GP

RN1206

1
2
3
4 5

SRN36J-GP

RN1207

1
2
3
4 5

SRN36J-GP

NF/LDM#/LDB I#

P3

A0

NF/UDM#/UDBI#

P7

A1

R3

A2

N7

A3

N3

A4

P8

A5

P2

A6

R8

A7

R2

A8

R7

A9

M3

A10/AP

T2

A11

M7

A12/BC#

T8

A13

L2

WE#/A1 4

M8

CAS#/A1 5

L8

RAS#/A1 6

L7

CS#

P1

RESET#

L3

ACT#

P9

ALERT#

K7

CK_T

K8

CK_C

K2

CKE

N2

BA0

N8

BA1

MT40A512M16HA-083EA-GP

072.40512.0A0U

0D6V_VREF_S0 1D2V_S3

8
7
6

8
7
6

8
7
6

8
7
6

8
7
6

8
7
6

M_A_DQ17

G2

DQ0

M_A_DQ19

F7

DQ1

M_A_DQ22

H3

DQ2

M_A_DQ23

H7

DQ3

M_A_DQ21

H2

DQ4

M_A_DQ18

H8

DQ5

M_A_DQ20

J3

DQ6

M_A_DQ16

J7

DQ7

M_A_DQ25

A3

DQ8

M_A_DQ29

B8

DQ9

M_A_DQ27

C3

DQ10

M_A_DQ31

C7

DQ11

M_A_DQ28

C2

DQ12

M_A_DQ24

C8

DQ13

M_A_DQ26

D3

DQ14

M_A_DQ30

D7

DQ15

M_A_DQS_DP3

B7

UDQS_T

M_A_DQS_DN3

A7

UDQS_C

M_A_DQS_DP2

G3

LDQS_T

M_A_DQS_DN2

F3

LDQS_C

E7
E2

M_A_ODT0

K3

ODT

DDR4_ZQ_RAM3

F9

ZQ

M_A_VREF_CA

M1

VREFCA

M_A_BG0

M2

BG0

TEST_MODE_3

N9

TEN

M_A_PARITY

T3

PAR

T7

NC#T7

B2

VSS

E1

VSS

M_A_BG1_E9_3

E9

VSS

G8

VSS

K1

VSS

K9

VSS

M_A_BG1_M9_R

M9

VSS

N1

VSS

T1

VSS

A2

VSSQ

A8

VSSQ

C9

VSSQ

D2

VSSQ

D8

VSSQ

E3

VSSQ

E8

VSSQ

F1

VSSQ

H1

VSSQ

H9

VSSQ

M_A_CLK#0

R1226 33R2F-3-GP

M_A_CLK0

R1225 33R2F-3-GP

M_A_ALERT_N

R1208 49D9R2F-GP

Close to CPU1

M_A_CLK0 M_A_CLK#0

C1247 SC3D3P50V2CN-GP

SDP and DDP BOM Control Table

R1212

DDR4_CTRL

R1213
R1214
R1215

R1221

SDP

R1220

DDP

R1224

2

1D2V_S3

RAM4

B3

VDD

B9

VDD

D1

VDD

G7

VDD

J1

VDD

J9

VDD

L1

VDD

L9

VDD

R1

VDD

T9

VDD

A1

VDDQ

A9

VDDQ

C1

VDDQ

D9

VDDQ

F2

VDDQ

F8

VDDQ

G1

VDDQ

G9

VDDQ

J2

VDDQ

J8

2D5V_S3

12

12

C1203

R1204

240R2D-GP

SCD047U25V2KX-GP

1 2
1 2
1 2

DY

1 2

SDPx16 8Gb DDPx16 16Gb

SM30N76502AA SM30N76518AA SM30N76490AA SM30N76504AA SM30E51324AA

Samsung
K4A8G165WC-BCTD

0R
0R
0R
0R

ASM

DY
DY

M_A_CLK

SK Hynix
H5AN8G6NCJR-VKC

0R
0R
0R
0R

ASM

DY
DY

VDDQ

B1

VPP

R9

VPP

M_A_A0

P3

A0

M_A_A1

P7

A1

M_A_A2

R3

A2

M_A_A3

N7

A3

M_A_A4

N3

A4

M_A_A5

P8

A5

M_A_A6

P2

A6

M_A_A7

R8

A7

M_A_A8

R2

A8

M_A_A9

R7

A9

M_A_A10

M3

A10/AP

M_A_A11

T2

A11

M_A_A12

M7

A12/BC#

M_A_A13

T8

A13

M_A_A14

L2

WE#/A1 4

M_A_A15

M8

CAS#/A1 5

M_A_A16

L8

RAS#/A1 6

M_A_CS#0

L7

CS#

SM_DRAMRST#

P1

RESET#

M_A_ACT_N

L3

ACT#

M_A_ALERT_N

P9

ALERT#

M_A_CLK0

K7

CK_T

M_A_CLK#0

K8

CK_C

M_A_CKE0

K2

CKE

M_A_BA0

N2

BA0

M_A_BA1

N8

BA1

MT40A512M16HA-083EA-GP

072.40512.0A0U

1 2

C1256 SCD01U50V2KX-1GP

Micron
MT40A512M16LY-075:E

0R
0R
0R
0R

ASM

DY
DY

NF/LDM#/LDB I#
NF/UDM#/UDBI#

UDQS_T
UDQS_C

LDQS_T
LDQS_C

VREFCA

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

ODT

ZQ

BG0

TEN

PAR

NC#T7

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS
VSSQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

M_A_DQ11

G2

M_A_DQ13

F7

M_A_DQ15

H3

M_A_DQ12

H7

M_A_DQ10

H2

M_A_DQ8

H8

M_A_DQ14

J3

M_A_DQ9

J7

M_A_DQ4

A3

M_A_DQ5

B8

M_A_DQ6

C3

M_A_DQ3

C7

M_A_DQ0

C2

M_A_DQ1

C8

M_A_DQ7

D3

M_A_DQ2

D7

M_A_DQS_DP0

B7

M_A_DQS_DN0

A7

M_A_DQS_DP1

G3

M_A_DQS_DN1

F3

E7
E2

M_A_ODT0

K3

DDR4_ZQ_RAM4

F9

M_A_VREF_CA

M1

M_A_BG0

M2

TEST_MODE_4

N9

M_A_PARITY

T3
T7

B2
E1

M_A_BG1_E9_4

E9
G8
K1
K9

M_A_BG1_M9_R

M9
N1
T1

A2
A8
C9
D2
D8
E3
E8
F1
H1
H9

Samsung
K4AAG165WB-MCTD

240R 1%
240R 1%
240R 1%
240R 1%

DY

ASM
ASM

1D2V_S31D2V_S3

12

C1201

SCD047U25V2KX-GP

SM30N07785AA

SK Hynix
H5ANAG6NAMR-VKC

240R 1%
240R 1%
240R 1%
240R 1%

DY

ASM
ASM

12

240R2D-GP

R1201

1

Micron
MT40A1G16KNR-075:E

240R 1%
240R 1%
240R 1%
240R 1%

DY

ASM
ASM

BB1_EVT_MAIN_W009
BB1_EVT_MAIN_W032
BB1_EVT_MAIN_W044

VDDQ/VDD 1uF x16

1D2V_S3 1D2V_S3

12

12

12

SC1U6D3V1MX-GP

VPP 1uF x8

2D5V_S3

12

SC1U6D3V1MX-GP

A A

VTT 1uF x8

0D6V_VREF_S0

12

SC1U6D3V1MX-GP

5

12

12

DY

C1206

C1204

C1205

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

12

12

DY

C1260

C1259

C1261

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

12

12

DY

C1258

C1257

C1255

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

12

12

DY

C1207

SC1U6D3V1MX-GP

12

12

DY

C1262

SC1U6D3V1MX-GP

12

12

DY

C1280

SC1U6D3V1MX-GP

12

DY

C1209

C1208

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

12

12

DY

C1264

C1263

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

12

12

DY

C1282

C1281

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

12

12

DY

C1211

C1210

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

12

DY

C1266

C1265

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

12

DY

C1284

C1283

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

12

DY

C1213

C1212

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

12

12

12

DY

C1267

C1268

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

12

12

12

DY

C1292

C1293

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

4

12

12

C1214

SC1U6D3V1MX-GP

12

C1269

SC1U6D3V1MX-GP

12

C1294

SC1U6D3V1MX-GP

12

DY

C1216

C1215

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

12

12

DY

C1270

C1271

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

12

12

DY

C1295

C1296

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

12

12

DY

C1217

C1218

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

12

DY

C1272

C1273

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

12

DY

C1298

C1297

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

12

12

DY

C1219

SC1U6D3V1MX-GP

12

DY

C1274

12

DY

C1299

12

DY

C1221

C1220

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

12

12

12

12

DY

C1224

C1223

C1222

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

3

12

12

12

DY

C1225

DY

C1226

C1227

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

12

DY

C1229

C1228

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

12

12

DY

C1231

C1230

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

12

12

DY

C1232

C1234

C1233

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

12

DY

C1235

SC1U6D3V1MX-GP

2

VDDQ/VDD 10uF x5

12

12

DY

C1237

C1238

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

VPP 10uF x2

2D5V_S3

12

12

DY

C1276

C1275

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

VTT 10uF x2

0D6V_VREF_S0

12

12

DY

C1288

C1289

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

12

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

12

12

12

DY

C1239

C1241

C1240

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

12

12

12

12

DY

DY

C1277

C1290

C1279

C1278

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

12

DY

C1291

SC10U6D3V3MX-GP

12

12

DY

C1242

SC10U6D3V3MX-GP

12

12

DY

DY

C1244

C1245

C1243

SC10U6D3V3MX-GP

C1246

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

LBB-1

LBB-1

LBB-1

Title

Title

Title

DDR (DDR4-CHA)

DDR (DDR4-CHA)

DDR (DDR4-CHA)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A1

A1

A1

Thursday, May 30, 2019

Thursday, May 30, 2019

Thursday, May 30, 2019

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Bumblebee-1

Bumblebee-1

Bumblebee-1

12 99

12 99

12 99

-1

-1

-1

M_B_DQS_DN[7:0] 5

M_B_DQS_DP[7:0] 5

M_B_DQ[63:0] 5

M_B_A[16:0] 5

5

TEST_MODE_5
TEST_MODE_6
TEST_MODE_7
TEST_MODE_8

1D2V_S3

1
1
1
1

1D2V_S3

2D5V_S3

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
M_B_A16

M_B_CS#0
SM_DRAMRST#
M_B_ACT_N
M_B_ALERT_N

M_B_CLK0
M_B_CLK#0

M_B_CKE0

M_B_BA0
M_B_BA1

1 2

R1320 1K8R2F-GP

1 2

R1321 1K8R2F-GP

TP1301TPAD14-OP-GP
TP1302TPAD14-OP-GP
TP1303TPAD14-OP-GP
TP1304TPAD14-OP-GP

RAM5

B3

VDD

B9

VDD

D1

VDD

G7

VDD

J1

VDD

J9

VDD

L1

VDD

L9

VDD

R1

VDD

T9

VDD

A1

VDDQ

A9

VDDQ

C1

VDDQ

D9

VDDQ

F2

VDDQ

F8

VDDQ

G1

VDDQ

G9

VDDQ

J2

VDDQ

J8

VDDQ

B1

VPP

R9

VPP

NF/LDM#/LDB I#

P3

A0

NF/UDM#/UDBI#

P7

A1

R3

A2

N7

A3

N3

A4

P8

A5

P2

A6

R8

A7

R2

A8

R7

A9

M3

A10/AP

T2

A11

M7

A12/BC#

T8

A13

L2

WE#/A1 4

M8

CAS#/A1 5

L8

RAS#/A1 6

L7

CS#

P1

RESET#

L3

ACT#

P9

ALERT#

K7

CK_T

K8

CK_C

K2

CKE

N2

BA0

N8

BA1

MT40A512M16HA-083EA-GP

072.40512.0A0U

M_B_VREF_CA V_SM_VREF_CNTB

M_B_DQ27

G2

DQ0

M_B_DQ29

F7

DQ1

M_B_DQ30

H3

DQ2

M_B_DQ28

H7

DQ3

M_B_DQ26

H2

DQ4

M_B_DQ25

H8

DQ5

M_B_DQ31

J3

DQ6

M_B_DQ24

J7

DQ7

M_B_DQ23

A3

DQ8

M_B_DQ17

B8

DQ9

M_B_DQ18

C3

DQ10

M_B_DQ20

C7

DQ11

M_B_DQ22

C2

DQ12

M_B_DQ16

C8

DQ13

M_B_DQ19

D3

DQ14

M_B_DQ21 M_B_DQ2

D7

DQ15

M_B_DQS_DP2

B7

UDQS_T

M_B_DQS_DN2

A7

UDQS_C

M_B_DQS_DP3

G3

LDQS_T

M_B_DQS_DN3

F3

LDQS_C

E7
E2

M_B_ODT0

K3

ODT

DDR4_ZQ_RAM5

F9

ZQ

M_B_VREF_CA

M1

VREFCA

M_B_BG0

M2

BG0

TEST_MODE_5

N9

TEN

M_B_PARITY

T3

PAR

T7

NC#T7

B2

VSS

E1

VSS

M_B_BG1_E9_5

E9

VSS

G8

VSS

K1

VSS

K9

VSS

M_B_BG1_M9_R

M9

VSS

N1

VSS

T1

VSS

A2

VSSQ

A8

VSSQ

C9

VSSQ

D2

VSSQ

D8

VSSQ

E3

VSSQ

E8

VSSQ

F1

VSSQ

H1

VSSQ

H9

VSSQ

1 2

R1302 2D7R2F-1-GP

Main Func = DIMM2

M_B_DQS_DN0
M_B_DQS_DN1
M_B_DQS_DN2
M_B_DQS_DN3
M_B_DQS_DN4
M_B_DQS_DN5
M_B_DQS_DN6
M_B_DQS_DN7

M_B_DQS_DP0
M_B_DQS_DP1
M_B_DQS_DP2
M_B_DQS_DP3

D D

M_B_DQS_DP4
M_B_DQS_DP5
M_B_DQS_DP6
M_B_DQS_DP7

M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48

C C

M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
M_B_A16

M_B_CS#05
SM_DRAMRST#5,12
M_B_ACT_N5
M_B_ALERT_N5

M_B_CLK05
M_B_CLK#05
M_B_CKE05

M_B_BA05
M_B_BA15

M_B_ODT05
V_SM_VREF_CNTB5
M_B_BG05
M_B_PARITY5

B B

M_B_BG15

1D2V_S3

SCD047U25V2KX-GP

12

C1302
SCD022U16V2KX-3GP

V_VREF_PATHB

12

R1303
24D9R2F-L-GP

4

1D2V_S3

RAM6

B3

VDD

B9

VDD

D1

VDD

G7

VDD

J1

VDD

J9

VDD

L1

VDD

L9

VDD

R1

VDD

T9

VDD

A1

VDDQ

A9

VDDQ

C1

VDDQ

D9

VDDQ

F2

VDDQ

F8

VDDQ

G1

VDDQ

G9

VDDQ

J2

VDDQ

J8

2D5V_S3

12

12

R1304

C1303

240R2D-GP

VDDQ

B1

VPP

R9

VPP

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
M_B_A16

M_B_CS#0
SM_DRAMRST#
M_B_ACT_N
M_B_ALERT_N

M_B_CLK0
M_B_CLK#0

M_B_CKE0

M_B_BA0
M_B_BA1

SDP & DDP SETTING

R1331~R1334:
DDP: 240 ohm (64.24005.6DL)
SDP: 0 ohm (63.R0034.1DL)

NF/LDM#/LDB I#

P3

A0

NF/UDM#/UDBI#

P7

A1

R3

A2

N7

A3

N3

A4

P8

A5

P2

A6

R8

A7

R2

A8

R7

A9

M3

A10/AP

T2

A11

M7

A12/BC#

T8

A13

L2

WE#/A1 4

M8

CAS#/A1 5

L8

RAS#/A1 6

L7

CS#

P1

RESET#

L3

ACT#

P9

ALERT#

K7

CK_T

K8

CK_C

K2

CKE

N2

BA0

N8

BA1

MT40A512M16HA-083EA-GP

072.40512.0A0U

DDR4_CTRL

M_B_BG1_E9_5

1 2

R1331 240R2F-1-GP

DDR4_CTRL

M_B_BG1_E9_6

1 2

R1332 240R2F-1-GP

DDR4_CTRL

M_B_BG1_E9_7

1 2

R1333 240R2F-1-GP

DDR4_CTRL

M_B_BG1_E9_8

1 2

R1334 240R2F-1-GP

M_B_BG1 M_B_BG1_M9_R

1 2

R1339 0R2J-2-GP

1 2

R1340 0R2J-2-GP

M_B_DQ14

G2

DQ0

M_B_DQ11

F7

DQ1

M_B_DQ15

H3

DQ2

M_B_DQ13

H7

DQ3

M_B_DQ10

H2

DQ4

M_B_DQ9

H8

DQ5

M_B_DQ12

J3

DQ6

M_B_DQ8

J7

DQ7

M_B_DQ0

A3

DQ8

M_B_DQ1

B8

DQ9

M_B_DQ3

C3

DQ10

M_B_DQ7

C7

DQ11

M_B_DQ5

C2

DQ12

M_B_DQ4

C8

DQ13

M_B_DQ6

D3

DQ14

D7

DQ15

M_B_DQS_DP0

B7

UDQS_T

M_B_DQS_DN0

A7

UDQS_C

M_B_DQS_DP1

G3

LDQS_T

M_B_DQS_DN1

F3

LDQS_C

E7
E2

M_B_ODT0

K3

ODT

DDR4_ZQ_RAM6

F9

ZQ

M_B_VREF_CA

M1

VREFCA

M_B_BG0

M2

BG0

TEST_MODE_6

N9

TEN

M_B_PARITY

T3

PAR

T7

NC#T7

B2

VSS

E1

VSS

M_B_BG1_E9_6

E9

VSS

G8

VSS

K1

VSS

K9

VSS

M_B_BG1_M9_R

M9

VSS

N1

VSS

T1

VSS

A2

VSSQ

A8

VSSQ

C9

VSSQ

D2

VSSQ

D8

VSSQ

E3

VSSQ

E8

VSSQ

F1

VSSQ

H1

VSSQ

H9

VSSQ

DDP
SDP

1D2V_S3

3

1D2V_S3

B3
B9
D1
G7

J1

J9
L1
L9
R1
T9

A1
A9
C1
D9
F2
F8
G1
G9

J2

J8

2D5V_S3

B1
R9

M_B_A0

P3

M_B_A1

P7

M_B_A2

R3

M_B_A3

N7

M_B_A4

N3

M_B_A5

P8

M_B_A6

P2

M_B_A7

R8

M_B_A8

R2

M_B_A9

R7

M_B_A10

M3

M_B_A11

T2

M_B_A12

M7

M_B_A13

T8

M_B_A14

L2

M_B_A15

M8

M_B_A16

L8

M_B_CS#0

L7

SM_DRAMRST#

P1

M_B_ACT_N

L3

M_B_ALERT_N

P9

M_B_CLK0

12

12

R1301

C1301

240R2D-GP

SCD047U25V2KX-GP

M_B_BG1_M9_R M_B_CLK#0

R1312 36R2F-1-GP

M_B_ODT0

R1311 36R2F-1-GP

M_B_CS#0
M_B_A16
M_B_ACT_N
M_B_A15

M_B_BG0
M_B_CKE0
M_B_A4
M_B_BA1

M_B_A0
M_B_A7
M_B_A6
M_B_A5

M_B_A10
M_B_A3
M_B_A14
M_B_A12

M_B_A9
M_B_A8
M_B_A11
M_B_PARITY

M_B_BA0
M_B_A2
M_B_A1
M_B_A13

M_B_CLK#0
M_B_CKE0

M_B_BA0
M_B_BA1

DDP

1 2
1 2

RN1302

1
2
3
4 5

SRN36J-GP

RN1303

1
2
3
4 5

SRN36J-GP

RN1304

1
2
3
4 5

SRN36J-GP

RN1305

1
2
3
4 5

SRN36J-GP

RN1306

1
2
3
4 5

SRN36J-GP

RN1307

1
2
3
4 5

SRN36J-GP

K7
K8

K2

N2
N8

8
7
6

8
7
6

8
7
6

8
7
6

8
7
6

8
7
6

2

2D5V_S3

M_B_CLK

C1370 SCD01U50V2KX-1GP

SK Hynix
H5AN8G6NCJR-VKC

0R
0R
0R
0R

ASM

DY
DY

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
M_B_A16

M_B_CS#0
SM_DRAMRST#
M_B_ACT_N
M_B_ALERT_N

M_B_CLK0
M_B_CLK#0

M_B_CKE0

M_B_BA0
M_B_BA1

1D2V_S3

1 2

RAM8

B3

VDD

B9

VDD

D1

VDD

G7

VDD

J1

VDD

J9

VDD

L1

VDD

L9

VDD

R1

VDD

T9

VDD

A1

VDDQ

A9

VDDQ

C1

VDDQ

D9

VDDQ

F2

VDDQ

F8

VDDQ

G1

VDDQ

G9

VDDQ

J2

VDDQ

J8

VDDQ

B1

VPP

R9

VPP

P3

A0

P7

A1

R3

A2

N7

A3

N3

A4

P8

A5

P2

A6

R8

A7

R2

A8

R7

A9

M3

A10/AP

T2

A11

M7

A12/BC#

T8

A13

L2

WE#/A1 4

M8

CAS#/A1 5

L8

RAS#/A1 6

L7

CS#

P1

RESET#

L3

ACT#

P9

ALERT#

K7

CK_T

K8

CK_C

K2

CKE

N2

BA0

N8

BA1

MT40A512M16HA-083EA-GP

072.40512.0A0U

Micron
MT40A512M16LY-075:E

0R
0R
0R
0R

ASM

DY
DY

RAM7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VPP
VPP

NF/LDM#/LDB I#

A0

NF/UDM#/UDBI#
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
WE#/A1 4
CAS#/A1 5
RAS#/A1 6

CS#
RESET#
ACT#
ALERT#

CK_T
CK_C

CKE

BA0
BA1

MT40A512M16HA-083EA-GP

072.40512.0A0U

0D6V_VREF_S0 1D2V_S3

M_B_DQ63

G2

DQ0

M_B_DQ60

F7

DQ1

M_B_DQ59

H3

DQ2

M_B_DQ56

H7

DQ3

M_B_DQ62

H2

DQ4

M_B_DQ61

H8

DQ5

M_B_DQ58

J3

DQ6

M_B_DQ57

J7

DQ7

M_B_DQ53

A3

DQ8

M_B_DQ49

B8

DQ9

M_B_DQ51

C3

DQ10

M_B_DQ55

C7

DQ11

M_B_DQ52

C2

DQ12

M_B_DQ48

C8

DQ13

M_B_DQ50

D3

DQ14

M_B_DQ54

D7

DQ15

M_B_DQS_DP6

B7

UDQS_T

M_B_DQS_DN6

A7

UDQS_C

M_B_DQS_DP7

G3

LDQS_T

M_B_DQS_DN7

F3

LDQS_C

E7
E2

M_B_ODT0

K3

ODT

DDR4_ZQ_RAM7

F9

ZQ

M_B_VREF_CA

M1

VREFCA

M_B_BG0

M2

BG0

TEST_MODE_7

N9

TEN

M_B_PARITY

T3

PAR

T7

NC#T7

B2

VSS

E1

VSS

M_B_BG1_E9_7

E9

VSS

G8

VSS

K1

VSS

K9

VSS

M_B_BG1_M9_R

M9

VSS

N1

VSS

T1

VSS

A2

VSSQ

A8

VSSQ

C9

VSSQ

D2

VSSQ

D8

VSSQ

E3

VSSQ

E8

VSSQ

F1

VSSQ

H1

VSSQ

H9

VSSQ

R1313 33R2F-3-GP

M_B_CLK0

R1314 33R2F-3-GP

M_B_ALERT_N

R1330 49D9R2F-GP

Close to CPU1

M_B_CLK0 M_B_CLK#0

C1388 SC3D3P50V2CN-GP

SDP and DDP BOM Control Table

R1331

DDR4_CTRL

R1332
R1333
R1334

R1340

SDP

R1339

DDP

R1312

12

12

C1336

R1306

240R2D-GP

SCD047U25V2KX-GP

1 2
1 2
1 2

DY

1 2

SDPx16 8Gb DDPx16 16Gb

SM30N76502AA SM30N76518AA SM30N76490AA SM30N76504AA SM30E51324AA

Samsung
K4A8G165WC-BCTD

0R
0R
0R
0R

ASM

DY
DY

UDQS_T
UDQS_C

LDQS_T
LDQS_C

NF/LDM#/LDB I#
NF/UDM#/UDBI#

VREFCA

G2

DQ0

F7

DQ1

H3

DQ2

H7

DQ3

H2

DQ4

H8

DQ5

J3

DQ6

J7

DQ7

A3

DQ8

B8

DQ9

C3

DQ10

C7

DQ11

C2

DQ12

C8

DQ13

D3

DQ14

D7

DQ15

B7
A7

G3
F3

E7
E2

K3

ODT

F9

ZQ

M1
M2

BG0

N9

TEN

T3

PAR

T7

NC#T7

B2

VSS

E1

VSS

E9

VSS

G8

VSS

K1

VSS

K9

VSS

M9

VSS

N1

VSS

T1

VSS

A2

VSSQ

A8

VSSQ

C9

VSSQ

D2

VSSQ

D8

VSSQ

E3

VSSQ

E8

VSSQ

F1

VSSQ

H1

VSSQ

H9

VSSQ

Samsung
K4AAG165WB-MCTD

240R 1%
240R 1%
240R 1%
240R 1%

DY

ASM
ASM

M_B_DQ46
M_B_DQ41
M_B_DQ47
M_B_DQ44
M_B_DQ42
M_B_DQ45
M_B_DQ43
M_B_DQ40
M_B_DQ35
M_B_DQ36
M_B_DQ39
M_B_DQ34
M_B_DQ32
M_B_DQ37
M_B_DQ38
M_B_DQ33

M_B_DQS_DP4
M_B_DQS_DN4

M_B_DQS_DP5
M_B_DQS_DN5

M_B_ODT0
DDR4_ZQ_RAM8
M_B_VREF_CA
M_B_BG0
TEST_MODE_8
M_B_PARITY

M_B_BG1_E9_8

M_B_BG1_M9_R

1D2V_S31D2V_S3

12

C1343

240R2D-GP

SCD047U25V2KX-GP

SM30N07785AA

SK Hynix
H5ANAG6NAMR-VKC

240R 1%
240R 1%
240R 1%
240R 1%

DY

ASM
ASM

12

R1305

1

BB1_EVT_MAIN_W009
BB1_EVT_MAIN_W032
BB1_EVT_MAIN_W044

Micron
MT40A1G16KNR-075:E

240R 1%
240R 1%
240R 1%
240R 1%

DY

ASM
ASM

VDDQ/VDD 1uF x16 VDDQ/VDD 10uF x5

1D2V_S3 1D2V_S3

12

12

12

12

DY

C1306

C1305

C1304

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

VPP 1uF x8

2D5V_S3

12

SC1U6D3V1MX-GP

A A

VTT 1uF x8

0D6V_VREF_S0

12

SC1U6D3V1MX-GP

5

12

12

DY

C1339

C1337

C1338

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

12

12

DY

C1354

C1355

C1356

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

12

12

DY

C1307

SC1U6D3V1MX-GP

12

12

DY

C1340

SC1U6D3V1MX-GP

12

12

DY

C1357

SC1U6D3V1MX-GP

12

C1308

C1341

C1358

C1310

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

12

SC1U6D3V1MX-GP

12

SC1U6D3V1MX-GP

12

12

DY

C1342

C1344

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

12

12

DY

C1360

C1359

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

12

DY

C1309

12

12

DY

C1311

C1312

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

12

DY

C1345

C1346

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

12

DY

C1361

C1362

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

12

12

DY

C1313

SC1U6D3V1MX-GP

12

12

DY

C1347

SC1U6D3V1MX-GP

12

12

DY

C1363

SC1U6D3V1MX-GP

4

12

12

DY

C1315

C1314

C1348

C1364

C1316

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

12

12

SC1U6D3V1MX-GP

12

SC1U6D3V1MX-GP

12

DY

C1350

C1349

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

12

12

DY

C1365

C1366

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

12

12

DY

C1318

C1317

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

12

DY

C1352

C1351

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

12

DY

C1367

C1368

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

12

12

DY

C1319

SC1U6D3V1MX-GP

12

DY

C1353

12

DY

C1369

12

DY

C1321

C1320

C1322

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

12

12

12

12

12

12

DY

DY

C1325

C1323

C1324

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

3

12

DY

C1326

C1327

C1328

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

12

12

DY

C1329

SC1U6D3V1MX-GP

12

DY

C1331

C1330

C1332

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

12

12

12

DY

C1333

DY

C1335

C1334

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

2

12

C1390

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

VPP 10uF x2

2D5V_S3

12

C1371

SC10U6D3V3MX-GP

VTT 10uF x2

0D6V_VREF_S0

12

C1376

SC10U6D3V3MX-GP

12

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

12

12

DY

C1391

SC10U6D3V3MX-GP

12

DY

C1372

SC10U6D3V3MX-GP

12

DY

C1377

SC10U6D3V3MX-GP

12

12

12

DY

C1393

C1392

C1394

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

12

12

12

C1373

12

C1378

DY

DY

C1375

C1374

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

12

DY

C1379

SC10U6D3V3MX-GP

12

DY

C1396

C1395

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

12

12

DY

DY

C1399

C1398

C1397

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

LBB-1

LBB-1

LBB-1

Title

Title

Title

DDR (DDR4-CHB)

DDR (DDR4-CHB)

DDR (DDR4-CHB)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A1

A1

A1

Thursday, May 30, 2019

Thursday, May 30, 2019

Thursday, May 30, 2019

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Bumblebee-1

Bumblebee-1

Bumblebee-1

13 99

13 99

13 99

-1

-1

-1

5

D D

C C

4

3

2

1

BLANK

B B

LBB-1

LBB-1

LBB-1

Wistron Corporation

Wistron Corporation

A A

Title

Title

Title

DDR (RSVD)

DDR (RSVD)

DDR (RSVD)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A4

A4

A4

Thursday, May 30, 2019

Thursday, May 30, 2019

Thursday, May 30, 2019

Date: Sheet of

Date: Sheet of

5

4

3

Date: Sheet of

2

Bumblebee-1

Bumblebee-1

Bumblebee-1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

-1

-1

14 99

14 99

14 99

1

-1

Main Func = PCH

5

4

3

2

1

HW Strap

HDA_SPKR19,27
NRB_BIT20

SPI_SI_CPU18,24,25,91
SPI_WP_CPU18,2 5
SPI_HOLD_C PU18,25

HDA_SDOUT_C PU19

CNV_RGI_DT2 0,61

CFG36,99
CFG46

CPU_SMB_ALER T#18

CPU_SMB_ALER T#_P118

CPU_SMB_ALER T#_P018

GPP_B22_GSP I1_MOSI20

GPP_H2121

GPP_H2321

GPP_H17_ST RAP4

D D

INPUT3VSEL17

GPD_721

GPP_D1220

GPP_B14

R1501
20KR2J-L2 -GP

1 2

DY

HDA_SPKR

GPP_B18 GPP_C2

3D3V_SUS

12

DY

R1502
1KR2J-1-GP

NRB_BIT

12

DY

R1503
1KR2J-1-GP

3D3V_SUS

12

R1551
4K7R2J-2-GP

CPU_SMB_ALER T#

12

DY

R1552
20KR2J-L2 -GP

GPP_B22

GPP_B22_GSP I1_MOSI

3D3V_SUS

12

DY

R1557
20KR2J-L2 -GP

12

DY

R1553
20KR2J-L2 -GP

12

12

DY

R1556
1KR2J-1-GP

DY

R1527
1KR2J-1-GP

GPP_H17_ST RAP

3D3V_SUS

12

R1554
100KR2F-L2 -GP

12

DY

R1519
10KR2J-3-GP

RVP 20K PH; #566439 EDS 100K

GPP_D12

GPP_B23

on page 71

1D8V_SUS

3D3V_SUS

12

12

DY

DY

R1528

R1512

4K7R2J-2-GP

4K7R2J-2-GP

HDA_SDOUT_C PU

GPP_H21

GPP_C5

C C

SPI0_IO2

B B

3D3V_SUS

12

DY

R1504
4K7R2J-L-GP

CPU_SMB_ALER T#_P0

LBB-1 uses LPC interface

12

R1505
20KR2J-L2 -GP

3D3V_SPI

12

R1508
100KR2F-L2 -GP

SPI_WP_CPU SPI_HOLD_C PU

DY

R1509
4K7R2J-L-GP

1 2

SPI0_MOSI

SPI0_IO3

on page 4

RO13_CFLU_20180130
follow RO13 no GPP_E23 strap (remove R1528)

3D3V_SUS

12

R1506
100KR2F-L2 -GP

SPI_SI_CPU

12

DY

R1507
1KR2J-1-GP

3D3V_SPI

12

R1510
100KR2F-L2 -GP

DY

R1511
4K7R2J-L-GP

1 2

GPP_D12

GPP_R2 / HDA_SDO /
I2S0_TXD / HDACPU_SDO

3D3V_SUS

CPU_SMB_ALER T#_P1

3D3V_SUS

12

R1522
4K7R2J-L-GP

GPP_H21

12

DY

R1523
20KR2J-L2 -GP

12

DY

R1555
20KR2J-L2 -GP

GPP_F6 /
CNV_RGI_DT / UART0_TXD

A A

[BDW Only]PHYSICAL_DEBUG_ENABLED (DFX PRIVACY)

0 : ENABLED

CFG[3]

SET DFX ENABLED BIT IN DEBUG INTERFACE MSR

1 : DISABLED

PCH strap pin:

5

1D8V_SUS

12

DY

R1515
20KR2J-L2 -GP

CNV_RGI_DT

12

DY

R1516
4K7R2J-2-GP

PDG datasheet. #575418

CFG3

12

DY

R1517
1KR2J-1-GP

(#543016)

DISPLAY PORT PRESENCE STRAP

0 : ENABLED

CFG[4]

An external Display Port device is connected to the Embedded Display Port.

1 : DISABLED (Default)
No Physical Display Port attached to Embedded DisplayPort*. No connect for disable.

3D3V_SUS

12

DY

R1520
4K7R2J-L-GP

INPUT3VSEL

12

R1521
4K7R2J-L-GP

CFG4

12

R1518
1KR2J-1-GP

4

3

3D3V_S51D8V_SUS

12

12

DY

R1526
10KR2F-2-GP

GPD_7

12

R1524
100KR2F-L2 -GP

DY

R1525
20K5R2F-GP

2

3D3V_SUS

12

DY

R1513
4K7R2J-L-GP

GPP_H23

12

DY

R1514
4K7R2J-L-GP

LBB-1

LBB-1

LBB-1

Wistron Corporatio n

Wistron Corporatio n

Wistron Corporatio n

21F, 88, Sec.1, Hs in Tai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hs in Tai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hs in Tai Wu Rd ., Hsichih,
Taipei Hsi en 221, Taiw an, R.O.C.

Taipei Hsi en 221, Taiw an, R.O.C.

Taipei Hsi en 221, Taiw an, R.O.C.

Title

Title

Title

CPU(STRAP)

CPU(STRAP)

CPU(STRAP)

Size Document Num ber Rev

Size Document Num ber Rev

Size Document Num ber Rev
A0

A0

A0

Bumblebee-1

Bumblebee-1

Bumblebee-1

Thursday, May 30, 20 19

Thursday, May 30, 20 19

Thursday, May 30, 20 19

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

15 106

15 106

15 106

-1

-1

-1

Main Func = PCH

D D

C C

5

WLAN_PCIE_RX_N61
WLAN_PCIE_RX_P61
WLAN_PCIE_TX_N61
WLAN_PCIE_TX_P61

LAN_PCIE_RX_N31
LAN_PCIE_RX_P31
LAN_PCIE_TX_N31
LAN_PCIE_TX_P31

SSD_PCIE_RX_N363
SSD_PCIE_RX_P363
SSD_PCIE_TX_N363
SSD_PCIE_TX_P363

SSD_PCIE_RX_N263
SSD_PCIE_RX_P263
SSD_PCIE_TX_N263
SSD_PCIE_TX_P263

SSD_PCIE_RX_N163
SSD_PCIE_RX_P163
SSD_PCIE_TX_N163
SSD_PCIE_TX_P163

SSD_SATA_RX_N63
SSD_SATA_RX_P63
SSD_SATA_TX_N63
SSD_SATA_TX_P63

CARD1_PCIE_RX_N33
CARD1_PCIE_RX_P33
CARD1_PCIE_TX_N33
CARD1_PCIE_TX_P33

USB1_USB30_RX_N58
USB1_USB30_RX_P58
USB1_USB30_TX_N58
USB1_USB30_TX_P58

USB3_USB30_RX_N36
USB3_USB30_RX_P36
USB3_USB30_TX_N36
USB3_USB30_TX_P36

USB4_USB30_RX_N36
USB4_USB30_RX_P36
USB4_USB30_TX_N36
USB4_USB30_TX_P36

TBT_PCIE_RX_N071
TBT_PCIE_RX_P071
TBT_PCIE_TX_N071
TBT_PCIE_TX_P071

TBT_PCIE_RX_N171
TBT_PCIE_RX_P171
TBT_PCIE_TX_N171
TBT_PCIE_TX_P171

TBT AR-LP

M.2 PCIe SSD

WLAN

GbE PHY

WWAN_PCIE_RX_N62
WWAN_PCIE_RX_P62
WWAN_PCIE_TX_N62
WWAN_PCIE_TX_P62

USB1_USB20_N75
USB1_USB20_P75

DK1_USB20_N74
DK1_USB20_P74

USB3_USB20_N35
USB3_USB20_P35

USB4_USB20_N36
USB4_USB20_P36

CCD_USB20_N66
CCD_USB20_P66

TOUCH_USB20_N55
TOUCH_USB20_P55

FP_USB20_N92
FP_USB20_P92

SMARTCAD_USB20_N94
SMARTCAD_USB20_P94

BT_USB20_N61
BT_USB20_P61

WWAN_USB20_N62

B B

WWAN_USB20_P62

USB_OC2#35
USB_OC3#35

SSD_DEVSLP63
M2_SSD_PEDET63

WWAN

4

TBT_PCIE_RX_N0
TBT_PCIE_RX_P0
TBT_PCIE_TX_N0
TBT_PCIE_TX_P0

TBT_PCIE_RX_N1
TBT_PCIE_RX_P1
TBT_PCIE_TX_N1
TBT_PCIE_TX_P1

SSD_PCIE_RX_N3
SSD_PCIE_RX_P3
SSD_PCIE_TX_N3
SSD_PCIE_TX_P3

SSD_PCIE_RX_N2
SSD_PCIE_RX_P2
SSD_PCIE_TX_N2
SSD_PCIE_TX_P2

SSD_PCIE_RX_N1
SSD_PCIE_RX_P1
SSD_PCIE_TX_N1
SSD_PCIE_TX_P1

SSD_SATA_RX_N
SSD_SATA_RX_P
SSD_SATA_TX_N
SSD_SATA_TX_P

WLAN_PCIE_RX_N
WLAN_PCIE_RX_P
WLAN_PCIE_TX_N
WLAN_PCIE_TX_P

LAN_PCIE_RX_N
LAN_PCIE_RX_P
LAN_PCIE_TX_N
LAN_PCIE_TX_P

WWAN_PCIE_RX_N
WWAN_PCIE_RX_P
WWAN_PCIE_TX_N
WWAN_PCIE_TX_P

R1604 100R2F-L1-GP-U

SATA Configuration

DevicePair

0

NC

1A

M.2 SATA SSD

1B

NC

2

NC

1 2

BW9
BW8
BW4
BW3

BU6
BU5
BU4
BU3

BT7
BT6
BU2
BU1

BU9
BU8
BT4
BT3

BP5
BP6
BR2
BR1

BN6
BN5
BR4
BR3

BN10

BN8
BN4
BN3

BL6
BL5
BN2
BN1

BK6
BK5
BM4
BM3

BJ6
BJ5
BL2
BL1

BG5
BG6
BL4
BL3

BE5
BE6
BJ4

PCIE_RCOMPN
PCIE_RCOMPP

Layout Note:

1. Trace Width: 4 mils min (breakout) 12-15 mils (trace)
Note: Must maintain low DC resistance routing (<0.1 ohm).

2. Isolation Spacing: At least 12 mils to any adjacent
high speed I/O.

PCIe Configuration

DevicePair

1

Media Card Reader

2

NC

3

NC

4

NC

5

TBT (AR-LP)

6

TBT (AR-LP)

7

NC

8

NC

9

M.2 PCIe SSD

10

M.2 PCIe SSD

11

M.2 PCIe SSD

12

M.2 PCIe SSD

13

WLAN

14

GbE

15

NC

16

WWAN

BJ3

CE6
CE5

CR28
CP28
CN28
CM28

PCIE5_ RXN/USB31 _5_RXN
PCIE5_ RXP/USB3 1_5_RX P
PCIE5_ TXN/USB31 _5_TXN
PCIE5_ TXP/USB3 1_5_TX P

PCIE6_ RXN/USB31 _6_RXN
PCIE6_ RXP/USB3 1_6_RX P
PCIE6_ TXN/USB31 _6_TXN
PCIE6_ TXP/USB3 1_6_TX P

PCIE7_ RXN
PCIE7_ RXP
PCIE7_ TXN
PCIE7_ TXP

PCIE8_ RXN
PCIE8_ RXP
PCIE8_ TXN
PCIE8_ TXP

PCIE9_ RXN
PCIE9_ RXP
PCIE9_ TXN
PCIE9_ TXP

PCIE10 _RXN
PCIE10 _RXP
PCIE10 _TXN
PCIE10 _TXP

PCIE11 _RXN/SAT A0_RXN
PCIE11 _RXP/SA TA0_RX P
PCIE11 _TXN/SAT A0_TXN
PCIE11 _TXP/SA TA0_TX P

PCIE12 _RXN/SAT A1A_RX N
PCIE12 _RXP/SA TA1A_R XP
PCIE12 _TXN/SAT A1A_TX N
PCIE12 _TXP/SA TA1A_T XP

PCIE13 _RXN
PCIE13 _RXP
PCIE13 _TXN
PCIE13 _TXP

PCIE14 _RXN
PCIE14 _RXP
PCIE14 _TXN
PCIE14 _TXP

PCIE15 _RXN/SAT A1B_RX N
PCIE15 _RXP/SA TA1B_R XP
PCIE15 _TXN/SAT A1B_TX N
PCIE15 _TXP/SA TA1B_T XP

PCIE16 _RXN/SAT A2_RXN
PCIE16 _RXP/SA TA2_RX P
PCIE16 _TXN/SAT A2_TXN
PCIE16 _TXP/SA TA2_TX P

PCIE_R COMP_N
PCIE_R COMP_P

GPP_H12 /M2_SKT2 _CFG0
GPP_H13 /M2_SKT2 _CFG1
GPP_H14 /M2_SKT2 _CFG2
GPP_H15 /M2_SKT2 _CFG3

USB3.0 Configuration

1
2
3
4
5
6

PCIE2_ RXN/USB31 _2_RXN/S SIC_1_ RXN
PCIE2_ RXP/USB3 1_2_RX P/SSIC_ 1_RXP

PCIE2_ TXN/USB31 _2_TXN/S SIC_1_ TXN
PCIE2_ TXP/USB3 1_2_TX P/SSIC_ 1_TXP

GPP_E9 /USB2_OC 0#/GP_B SSB_CL K

GPP_E1 0/USB2_O C1#/GP_ BSSB_D I

ZZ.00CPU.271

CPU1 will use BOM control to Whiskeylake-U

DevicePair

NC
USB3 Type-C Port1
USB3 Type-A Port3 (AOU)
USB3 Type-A Port4
NC
NC

3

8 OF 20CPU1H

PCIE1_ RXN/USB31 _1_RXN
PCIE1_ RXP/USB3 1_1_RX P

PCIE1_ TXN/USB31 _1_TXN
PCIE1_ TXP/USB3 1_1_TX P

PCIE3_ RXN/USB31 _3_RXN
PCIE3_ RXP/USB3 1_3_RX P

PCIE3_ TXN/USB31 _3_TXN
PCIE3_ TXP/USB3 1_3_TX P

PCIE4_ RXN/USB31 _4_RXN
PCIE4_ RXP/USB3 1_4_RX P

PCIE4_ TXN/USB31 _4_TXN
PCIE4_ TXP/USB3 1_4_TX P

USB2N_1
USB2P_1

USB2N_2
USB2P_2

USB2N_3
USB2P_3

USB2N_4
USB2P_4

USB2N_5
USB2P_5

USB2N_6
USB2P_6

USB2N_7
USB2P_7

USB2N_8
USB2P_8

USB2N_9
USB2P_9

USB2N_10

Support CNVi

USB2P_1 0

USB2_CO MP

USB_ID

USB_VBUS SENSE

GPP_E1 1/USB2_O C2#
GPP_E1 2/USB2_O C3#

GPP_E4 /DEVSLP 0
GPP_E5 /DEVSLP 1
GPP_E6 /DEVSLP 2

GPP_E0 /SATAXP CIE0/SA TAGP0
GPP_E1 /SATAXP CIE1/SA TAGP1
GPP_E2 /SATAXP CIE2/SA TAGP2

GPP_E8 /SATALE D#/SPI1 _CS1#

RSVD#A R3

WHISKEY-LAKE-GP

USB2.0 Configuration

Pair Device

1

Smart Card Reader

2

USB3 Type-C Port1

3

USB3 Type-A Port3 (AOU)

4

USB3 Type-A Port4

5

USB3 Type-C (CS18 Docking) Port2 / DK1

6

Touch Screen

7

WWAN Card

8

RGB/IR Hybrid Camera

9

Fingerprint

10

Bluetooth (CNVi)

CB5
CB6
CA4
CA3

BY8
BY9
CA2
CA1

BY7
BY6
BY4
BY3

BW6
BW5
BW2
BW1

CE3
CE4

CE1
CE2

CG3
CG4

CD3
CD4

CG5
CG6

CC1
CC2

CG8
CG9

CB8
CB9

CH5
CH6

BT_USB20_N

CC3

BT_USB20_P

CC4
CC5

USBCOMP
USB2_ID

CE8

USB2_VBUSSENSE

CC6

USB_OC0#

CK6

USB_OC1#

CK5

USB_OC2#

CK8

USB_OC3#

CK9
CP8

SSD_DEVSLP

CR8

SIO_EXT_SCI#

CM8

M2_OPT_PEDET

CN8

M2_SSD_PEDET

CM10

GPP_E1/SATAXPCIE1/SATAGP1

CP10
CN7
AR3

CNVi Bluetooth

1 2

R1603 113R2F-GP

2

CARD1_PCIE_RX_N
CARD1_PCIE_RX_P
CARD1_PCIE_TX_N
CARD1_PCIE_TX_P

USB1_USB30_RX_N
USB1_USB30_RX_P
USB1_USB30_TX_N
USB1_USB30_TX_P

USB3_USB30_RX_N
USB3_USB30_RX_P
USB3_USB30_TX_N
USB3_USB30_TX_P

USB4_USB30_RX_N
USB4_USB30_RX_P
USB4_USB30_TX_N
USB4_USB30_TX_P

SMARTCAD_USB20_N
SMARTCAD_USB20_P

USB1_USB20_N
USB1_USB20_P

USB3_USB20_N
USB3_USB20_P

USB4_USB20_N
USB4_USB20_P

DK1_USB20_N
DK1_USB20_P

TOUCH_USB20_N
TOUCH_USB20_P

WWAN_USB20_N
WWAN_USB20_P

CCD_USB20_N
CCD_USB20_P

FP_USB20_N
FP_USB20_P

Intel Checklist #575179 Note:
Support CNVi WLAN's Bluetooth: Please connect to CPU USB2N/P_10 (WHLU)

Media Card Reader

USB3.1 Type-C X-bar switch (PS8747)

USB TYPE-A (AOU) GEN1 / USB3

USB TYPE-A GEN1 / USB4

Smart Card Reader

USB TYPE-C / USB1

USB TYPE-A (AOU) / USB3

USB TYPE-A / USB4

USB TYPE-C (CS18 Docking) / DK1

Touch Panel

M.2 WWAN Slot

RGB Camera & IR Camera

Fingerprint

USB2_ID
USB2_VBUSSENSE

USB_OC0#
USB_OC1#

USB_OC2#
USB_OC3#

SIO_EXT_SCI#

(#571021_CFLU) When used as DEVSLP, no external pull-up or pull-down
termination required from SATA Host DEVSLP.

M2_OPT_PEDET
GPP_E1/SATAXPCIE1/SATAGP1
M2_SSD_PEDET

1 2

R1601 0R2J-2-GP

DY

1 2

R1602 0R2J-2-GP

DY

RN1601

1

4

2 3

SRN10KJ-5-GP

RN1602

1

4

2 3

SRN10KJ-5-GP

12

R1608 10KR2J-3-GP

1 2

R1613 10KR2J-3-GP

1 2

R1614 10KR2J-3-GP

1 2

R1615 10KR2J-3-GP

3D3V_SUS

3D3V_S0

3D3V_SUS

1

BB1_EVT_MAIN_W008
BB1_EVT_MAIN_W016
BB1_EVT_MAIN_W018
BB1_EVT_MAIN_W032

BB1_FVT_MAIN_W009
BB1_FVT_MAIN_W017
BB1_FVT_MAIN_W027

BB1_SVT_MAIN_W015

BB1_FVT_MAIN_L005

A A

LBB-1

LBB-1

LBB-1

Title

Title

Title

CPU (PCIE/SATA/USB)

CPU (PCIE/SATA/USB)

CPU (PCIE/SATA/USB)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A1

A1

A1

Thursday, May 30, 2019

Thursday, May 30, 2019

Thursday, May 30, 2019

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

1

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Bumblebee-1

Bumblebee-1

Bumblebee-1

16 99

16 99

16 99

-1

-1

-1

Main Func = PCH

SYS_PWROK24,56
RESET_OUT#40

VCCST_PWRGD17,24,40

RSMRST#_KBC24
3V_5V_PWRGD40,45,52,53
PM_SLP_S0#40,99
PM_SLP_S3#24,40,71,99
PM_SLP_S4#24,40,51,99
PM_SLP_S5#99

D D

C C

PM_SLP_SUS#24,40,52,53
PM_SLP_LAN#24
PM_SLP_WLAN#24,61
PM_PWRBTN#24,63,99

PLTRST#_CPU24,31,33,40,61,62,63,68,71,89,91

AC_PRESENT24

PCIE_WAKE#_CPU33,61,62,71

PCH_BATLOW#24,71

INPUT3VSEL15

LAN_WAKE#31

LANPHYPC31

XDP_DBRESET#99

PM_RSMRST#99

H_THERMTRIP_EN40

PM_SLP_M#24,99

5

4

3D3V_S5

1 2

R1752 10KR2J-3-GP

1 2

R1753 1KR2J-1-GP

1 2

R1746 10KR2J-3-GP

3D3V_SUS

1 2

R1731 100KR2J-1-GP

3D3V_S5

1 2

R1738 10KR2J-3-GP

DY

1 2

R1739 10KR2J-3-GP

12

R1740 10KR2J-3-GP

DY

12

R1717 10KR2J-3-GP

DY

AOZ Power switch, P/N: 074.01334.0093
Low Rds(on)= 5m Ohm
Turn on rise time = 10us

AC_PRESENT
PCIE_WAKE#_CPU

PCH_BATLOW#

EXT_PWR_GATE#

PM_RSMRST#
PM_PCH_PWROK

SYS_PWROK

H_CPUPWRGD

12

DY

R1714
10KR2J-3-GP

1 2

R1708 0R2-PT5-LILY-GP-U

VCCST_PWRGD17,24,40

3

XDP_DBRESET#

12

DY

EC1706
SC1KP50V2KX-1GP

ME_SUS_PWR_ACK_R
SUSACK#_R

Dis-wire with XDP_PM_RSMRST_PWRGD_XDP

3D3V_SUS 1D05V_VCCST 1D05V_SUS

U1701

1

5

NC#1

VCC

2

A

DY

H_VCCST_PWRGD

4

GND3Y

74LVC1G07GW-GP

1 2

R1749 100KR2F-L2-GP

2

RTC_AUX_S5

#575412, v0.9, p.30: 1M-ohm PU and 330K-ohm is used on the CRB

12

R1730

1

TP1708 TPAD14-OP-GP

1MR2J-1-GP

12

DY

C1712

SC1KP50V2KX-1GP

D1701
RB530SM-30T2R-GP-U

K A

PDG #575412 p128

PM_SLP_S0#

PM_SLP_LAN#

PM_PWRBTN#

PLTRST#_CPU

100KR2J-1-GP

3D3V_S0

3D3V_SUS

12

12

DY

R1747

R1701
1KR2J-1-GP

1KR2J-1-GP

PCH_PLTRST#

BJ35

GPP_B1 3/PLTRS T#

CN10

SYS_RES ET#

BR36

RSMRST#

AR2

PROCPW RGD

BJ2

VCCST_ PWRGO OD

CR10

SYS_PW ROK

BP31

PCH_PW ROK

BP30

DSW_P WROK

BV34

GPP_A1 3/SUSWA RN#/SUSPW RDACK

BY32

GPP_A1 5/SUSACK #

BU30

WAKE#

BU32

GPD2/LA N_WAKE #

BU34

GPD11/L ANPHYPC

ZZ.00CPU.271

CPU1 will use BOM control to Whiskeylake-U

3D3V_S5

XDP_DBRESET#

H_VCCST_PWRGD

RESET_OUT#
3V_5V_PWRGD
PM_RSMRST#

1 2

R1750 0R2J-2-GP

DY

1 2

R1734 0R2J-2-GP

1 2

R1706 0R2-PT5-LILY-GP-U

1 2

R1704 0R2J-2-GP

1 2

R1755 0R2J-2-GP

DY

1 2

R1707 10KR2J-3-GP

PM_RSMRST#
H_CPUPWRGDH_THERMTRIP_EN

VCCST_PWRGD_R

Follow Wistron ORB design.

SYS_PWROK
PM_PCH_PWROK
PCH_DPWROK

ME_SUS_PWR_ACK_R
SUSACK#_R

PCIE_WAKE#_CPU
LAN_WAKE#
LANPHYPC

LCASE BTN2

-TAMPER_SW_DTCT21

12

12

SCD1U6D3V1KX-GP

12

DY

DY

R1722
1KR2J-1-GP

DY

R1723
1KR2J-1-GP

C1702

GPP_B1 2/SLP_S 0#

GPD9/SP L_WLA N#

GPD1/AC PRESENT

GPP_B1 1/EXT_P WR_GA TE#

GPP_B2 /VRALER T#

WHISKEY-LAKE-GP

12

NP1NP2

BTN2
SW-4P-9-GP

062.40003.0011

3 4

SPVR310200

11 OF 20CPU1K

GPD4/SL P_S3#
GPD5/SL P_S4#

GPD10/S LP_S5#

SLP_SUS #
SLP_LA N#

GPD6/SL P_A#
GPD3/PW RBTN#
GPD0/BA TLOW#

INTRUDER #

INPUT3VS EL

INTRUDER_SW

BJ37
BU36
BU27
BT29

BU29
BT31
BT30
BU37

BU28
BU35
BV36

BR35
CC37

CC36
BT27

PM_SLP_S0#
PM_SLP_S3#
PM_SLP_S4#
PM_SLP_S5#

PM_SLP_SUS#
PM_SLP_LAN#
PM_SLP_WLAN#
PM_SLP_M#

PM_PWRBTN#
AC_PRESENT
PCH_BATLOW#

SM_INTRUDER#
EXT_PWR_GATE#

VRALERT#
INPUT3VSEL

R1745
0R2-PT5-LILY-GP-U

1 2

1

BB1_EVT_MAIN_W006
BB1_EVT_MAIN_W015
BB1_EVT_MAIN_W032
BB1_EVT_MAIN_W037
BB1_EVT_MAIN_W040
BB1_EVT_MAIN_W042

BB1_FVT_MAIN_W013
BB1_FVT_MAIN_W017
BB1_FVT_MAIN_W034

BB1_SVT_MAIN_W008

1 2

R1703 100KR2J-1-GP

DY

1 2

R1705 100KR2J-1-GP

DY

1 2

R1721 100KR2J-1-GP

BATLOW#:
Pull-up required even if not implemented.

AC_PRESENT

-INTRUDER_EC 24

R1713
0R2-PT5-LILY-GP-U

PCH_PLTRST#

1 2

12

12

DY

R1715

C1701
SC220P50V2KX-3GP

BB1_FVT_MAIN_L015

BB1_SIT_MAIN_L006

3D3V_S5

3D3V_S5

12

DY

EC1707

SCD1U6D3V1KX-GP

R1715 PD for CNVI

12

R1748
47KR2F-GP

#543016 Rev0.7

1. VCCST_PWRGD is only 1.0 V tolerant.

2. VCCST_PWRGD must go low du ring Sx pwr states, regardless of the voltage level of VCCS T

Q1701

6

Note:ZZ.27002.F7C01

2N7002KDW-1-GP

75.27002.F7C

2345
1

3D3V_AUX_S5

12

R1727
100KR2J-1-GP

PM_RSMRST#
3V_5V_POK_C

1 2

R1702 1KR2J-1-GP

1 2

R1728 0R2-PT5-LILY-GP-U

RSMRST#_KBC
3V_5V_PWRGD

12

C1710

SCD22U10V2KX-1GP

12

DY

EC1712

SCD1U6D3V1KX-GP

LBB-1

LBB-1

LBB-1

Title

Title

Title

PCH (PMU)

PCH (PMU)

PCH (PMU)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A1

A1

A1

Thursday, May 30, 2019

Thursday, May 30, 2019

Thursday, May 30, 2019

Date: Sheet of

Date: Sheet of

3

2

Date: Sheet of

1

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Bumblebee-1

Bumblebee-1

Bumblebee-1

17 99

17 99

17 99

-1

-1

-1

3D3V_AUX_S53D3V_S5

D1702

D1703

K A

K A

RB530SM-30T2R-GP-U

RB530SM-30T2R-GP-U

3V_5V_POK_R#

R1726
10KR2J-3-GP

1 2

B B

A A

5

3V_5V_POK#

4

Main Func = PCH

SPI_CLK_CPU24,25,91
SPI_SO_CPU24,25,91
SPI_SI_CPU15,24,25,91

SPI_WP_CPU15,25
SPI_HOLD_CPU15,25
SPI_CS_CPU_N024,25
SPI_CS_CPU_N291

D D

CPU_SMB_ALERT#15

SIO_RCIN#24

CPU_SMB_SCL_P124
CPU_SMB_SDA_P124

CPU_SMB_SCL_P031
CPU_SMB_SDA_P031

CPU_SMB_ALERT#_P015
CPU_SMB_ALERT#_P115

LPC_AD_CPU_P024,68
LPC_AD_CPU_P124,68
LPC_AD_CPU_P224,68
LPC_AD_CPU_P324,68

LPC_SERIRQ_CPU24,68
LPC_FRAME#_CPU24,68

LPC_CLKRUN#_CPU24

LPC_CLK_KBC24
LPC_CLK_DB68

C C

TP_SMB_SCL65

TP_SMB_SDA65

CPU_CL_CLK_WLAN61
CPU_CL_DATA_WLAN61

CPU_CL_RST#_WLAN61

5

3D3V_S5

1 2

R1823 1KR2J-1-GP

DY

1 2

R1824 1KR2J-1-GP

DY

3D3V_S0

1 2

R1820 10KR2J-3-GP

1 2

R1821 10KR2J-3-GP

R1801 100KR2J-1-GP

RCIN#:
Frequency to Avoid: 33 MHz

SERIRQ PH:
PDG: 8.2k
CRB: 10k

1 2

DY

SPI_HOLD_CPU
SPI_WP_CPU

SIO_RCIN#
LPC_SERIRQ_CPU_R

CPU_CL_RST#_WLAN CPU_CL_RST#_WLAN_R

SPI_CLK_CPU

4

SPI_SO_CPU

PCH strap pin:

BOOT HALT

0 = ENABLED

SPI0_MOSI

1 = DISABLED
WEAK INTERNAL PU

This signal has a weak internal pull-up.

1 2

R1870 0R2-PT5-LILY-GP-U

1 2

R1804 0R2-PT5-LILY-GP-U

3D3V_SUS

12

DY

R1871
10KR2J-3-GP

TP1804
TP1805
TP1806

SPI_CLK_CPU
SPI_SO_CPU
SPI_SI_CPU
SPI_WP_CPU
SPI_HOLD_CPU
SPI_CS_CPU_N0

SPI_CS_CPU_N2

CPU_GPP_D21

1

CPU_GPP_D22

1

CPU_GPP_D0

1

CPU_CL_CLK_WLAN
CPU_CL_DATA_WLAN

SIO_RCIN#
LPC_SERIRQ_CPU_RLPC_SERIRQ_CPU

CH37

SPI0_C LK

CF37

SPI0_MI SO

CF36

SPI0_MO SI

/strap

CF34

SPI0_I O2

/strap

CG34

SPI0_I O3

/strap

CG36

SPI0_C S0#

CG35

SPI0_C S1#

CH34

SPI0_C S2#

CF20

GPP_D1 /SPI1_C LK/BK1/S BK1

CG22

GPP_D2 /SPI1_MI SO_IO1 /BK2/SBK 2

CF22

GPP_D3 /SPI1_MO SI_IO0 /BK3/SBK 3

CG23

GPP_D2 1/SPI1_ IO2

CH23

GPP_D2 2/SPI1_ IO3

CG20

GPP_D0 /SPI1_C S0#/BK0 /SBK0

CH7

CL_CLK

CH8

CL_DAT A

CH9

CL_RST #

BV29

GPP_A0 /RCIN#/TI ME_SYNC1

BV28

GPP_A6 /SERIRQ

CPU1 will use BOM control to Whiskeylake-U

strap/

GPP_B2 3/SML1AL ERT#/PC HHOT#

strap/

GPP_A5 /LFRAME# /ESPI_C S#

GPP_A1 4/SUS_ST AT#/ESP I_RESE T#

GPP_A9 /CLKOUT_ LPC0/ES PI_CLK

ZZ.00CPU.271

3

5 OF 20CPU1E

GPP_C0 /SMBCLK

GPP_C1 /SMBDATA

GPP_C2 /SMBALER T#

GPP_C3 /SML0CLK

GPP_C4 /SML0DAT A

GPP_C5 /SML0ALE RT#

GPP_C6 /SML1CLK

GPP_C7 /SML1DAT A

GPP_A1 /LAD0/ES PI_IO0
GPP_A2 /LAD1/ES PI_IO1
GPP_A3 /LAD2/ES PI_IO2
GPP_A4 /LAD3/ES PI_IO3

GPP_A1 0/CLKOUT _LPC1

GPP_A8 /CLKRUN#

WHISKEY-LAKE-GP

CPU_SMB_ALERT#_P0

PCH strap pin:

Sampled at rising edge of RSMRST#

eSPI or LPC

This signal has a weak internal pull-down.

SML0ALERT# /

0 = LPC Is selected for EC.

GPP_C5

1 = eSPI Is selected for EC.

This signal has a weak internal pull-down.

CPU_SMB_SCL

CK14

CPU_SMB_SDA

CH15

CPU_SMB_ALERT#

CJ15

CPU_SMB_SCL_P0

CH14

CPU_SMB_SDA_P0

CF15
CG15

CN15
CM15
CC34

CA29
BY29
BY27
BV27
CA28
CA27

BV32
BV30
BY30

To Gbe

CPU_SMB_ALERT#_P0
CPU_SMB_SCL_P1

CPU_SMB_SDA_P1

To KBC

CPU_SMB_ALERT#_P1

LPC_AD_CPU_P0_R
LPC_AD_CPU_P1_R
LPC_AD_CPU_P2_R
LPC_AD_CPU_P3_R

LPCPD#_SUS_STAT#
LPC_CLK_CPU_P0 LPC_CLK_KBC

LPC_CLKRUN#_CPU_R

1 2

R1854 0R2J-2-GP

1 2

R1855 0R2J-2-GP

1 2

R1856 0R2J-2-GP

1 2

R1857 0R2J-2-GP

1 2

R1853 0R2J-2-GP

1 2

R1842 22R2F-1-GP

1 2

R1843 22R2F-1-GP

LPC_ASM

Close CPU1 R1843: LPC Debug Port for Security (Page 68)

1 2

R1819 0R2-PT5-LILY-GP-U

LPC_AD_CPU_P0
LPC_AD_CPU_P1
LPC_AD_CPU_P2
LPC_AD_CPU_P3
LPC_FRAME#_CPULPC_FRAME#_CPU_R

LPC_CLKRUN#_CPU

2

3D3V_SUS

R1873 499R2F-2-GP
R1874 499R2F-2-GP

R1837 150KR2J-GP

R1814 10KR2J-3-GP

R1858 8K2R2F-1-GP

Q1803

2345
1

6

Note:ZZ.27002.F7C01

RN1801

1
2 3

SRN2K2J-1-GP

RN1810

1
2 3

SRN2K2J-1-GP

DY

DY

12
12

12

12

12

4

4

TP_SMB_SCL
TP_SMB_SDA

3D3V_SUS

3D3V_S0

CPU_SMB_SDA
CPU_SMB_SCL

CPU_SMB_SDA_P0
CPU_SMB_SCL_P0

CPU_SMB_SDA_P1
CPU_SMB_SCL_P1

CPU_SMB_ALERT#_P1

LPCPD#_SUS_STAT#

LPC_CLKRUN#_CPU

3D3V_S0

LPC_CLK_DBLPC_CLK_CPU_P1

12

12

DY

DY

EC1808

EC1807

SC22P50V2JN-L-GP

SC22P50V2JN-L-GP

CPU_SMB_SCL

CPU_SMB_SDA

2N7002KDW-1-GP

75.27002.F7C

RN1811

2 3
1

SRN10KJ-5-GP

4

1

3D3V_S0

BB1_EVT_MAIN_W006
BB1_EVT_MAIN_W015
BB1_EVT_MAIN_W024

BB1_FVT_MAIN_W020
BB1_FVT_MAIN_W021
BB1_FVT_MAIN_W022

BB1_SVT_MAIN_W008

SUS_CLK_CPU61

SRTC_RST#25
RTC_RST#25,99

B B

PULSAR_38P4M_REF_CLK61

WLAN_CLK_CPU_N61
WLAN_CLK_CPU_P61
WLAN_CLKREQ_CPU_N61

SSD_CLK_CPU_N63
SSD_CLK_CPU_P63
SSD_CLKREQ_CPU_N63

LAN_CLK_CPU_N31
LAN_CLK_CPU_P31
LAN_CLKREQ_CPU_N31

CARD1_CLK_CPU_N33
CARD1_CLK_CPU_P33
CARD1_CLKREQ_CPU_N33

TBT_CLK_CPU_N71
TBT_CLK_CPU_P71
TBT_CLKREQ_CPU_N71

WWAN_CLK_CPU_N62
WWAN_CLK_CPU_P62

WWAN_CLKREQ_CPU_N62

PH on WWAN Conn

A A

5

3D3V_S0

SRN10KJ-5-GP

3D3V_SUS

SRN10KJ-5-GP

R1867 10KR2J-3-GP

RN1803

1
2 3

RN1804

1
2 3

1 2

WLAN_CLKREQ_CPU_N

4

SSD_CLKREQ_CPU_N

CARD1_CLKREQ_CPU_N

4

LAN_CLKREQ_CPU_N

TBT_CLKREQ_CPU_N

Media Card Reader

TBT

M.2 PCIe SSD

WWAN

GbE PHY

WLAN

CARD1_CLK_CPU_N
CARD1_CLK_CPU_P
CARD1_CLKREQ_CPU_N

TBT_CLK_CPU_N
TBT_CLK_CPU_P
TBT_CLKREQ_CPU_N

SSD_CLK_CPU_N
SSD_CLK_CPU_P
SSD_CLKREQ_CPU_N

WWAN_CLK_CPU_N
WWAN_CLK_CPU_P
WWAN_CLKREQ_CPU_N

LAN_CLK_CPU_N
LAN_CLK_CPU_P
LAN_CLKREQ_CPU_N

WLAN_CLK_CPU_N
WLAN_CLK_CPU_P
WLAN_CLKREQ_CPU_N

AW2

CLKOUT_ PCIE_N0

AY3

CLKOUT_ PCIE_P 0

CF32

GPP_B5 /SRCCLK REQ0#

BC1

CLKOUT_ PCIE_N1

BC2

CLKOUT_ PCIE_P 1

CE32

GPP_B6 /SRCCLK REQ1#

BD3

CLKOUT_ PCIE_N2

BC3

CLKOUT_ PCIE_P 2

CF30

GPP_B7 /SRCCLK REQ2#

BH3

CLKOUT_ PCIE_N3

BH4

CLKOUT_ PCIE_P 3

CE31

GPP_B8 /SRCCLK REQ3#

BA1

CLKOUT_ PCIE_N4

BA2

CLKOUT_ PCIE_P 4

CE30

GPP_B9 /SRCCLK REQ4#

BE1

CLKOUT_ PCIE_N5

BE2

CLKOUT_ PCIE_P 5

CF31

GPP_B1 0/SRCCL KREQ5#

CPU1 will use BOM control to Whiskeylake-U

4

ZZ.00CPU.271

10 OF 20CPU1J

CLKOUT_ ITPXDP _N
CLKOUT_ ITPXDP _P

GPD8/SUS CLK

XTAL_I N

XTAL_O UT

XCLK_B IASREF

CLKIN_X TAL

RTCX1
RTCX2

SRTCRS T#

RTCRST #

WHISKEY-LAKE-GP

XDP_CLK_CPU_N

AU1
AU2

BT32
CK3

CK2
CJ1

CM3
BN31

BN32
BR37

BR34

1

XDP_CLK_CPU_P

XTL_24M_X1_CPU
XTL_24M_X2_CPU

XCLK_BIASREF
CLK_IN_XTAL_CPU PULSAR_38P4M_REF_CLK

XTL_32K_X1_CPU
XTL_32K_X2_CPU

SRTC_RST#
RTC_RST#

TP1807 TPAD14-OP-GP

1

TP1808 TPAD14-OP-GP

SUS_CLK_CPU

1 2

R1818 0R2-PT5-LILY-GP-U

12

12

DY

R1872

C1809

10KR2J-3-GP

SC3D3P50V2CN-GP

3

12

R1803
60D4R2F-GP

XTL_24M_X1_CPU

XTL_24M_X2_CPU

XTL_32K_X2_CPU

XTL_32K_X1_CPU

R1839 0R2J-2-GP

12

R1841
200KR2F-L-GP

R1840 0R2J-2-GP

1 2

1 2

2

1 2

R1815 10MR2J-L-GP

1 2

X1802
XTAL-32D768KHZ-88-GP

082.30003.0191

12

C1804

SC12P50V2JN-3GP

XTL_24M_X1_R

XTL_24M_X2_R

23

4 1

12

C1803

SC12P50V2JN-3GP

12

C1807 SC12P50V2JN-3GP

X1801
XTAL-24MHZ-189-GP

082.30006.0571

12

C1808 SC15P50V2JN-2-GP

24MHz (X1801)
TXC 7V24000023
HARMONY X3G024000BC1HA-HU

32.768KHz (X1802)
EPSON EP.FC-135R 32.768K12.5+-20 (X1A000141000300)
SEIKO Q-SC32P03220C5AAAF
TXC 9H03200042

082.30006.0571

082.30006.0531

LBB-1

LBB-1

LBB-1

Title

Title

Title

CPU_(SPI/ESPI/SMBUS/XTAL/CLK)

CPU_(SPI/ESPI/SMBUS/XTAL/CLK)

CPU_(SPI/ESPI/SMBUS/XTAL/CLK)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A1

A1

A1

Thursday, May 30, 2019

Thursday, May 30, 2019

Thursday, May 30, 2019

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

082.30003.0191

082.30003.0301

082.30003.0231

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Bumblebee-1

Bumblebee-1

Bumblebee-1

18 99

18 99

18 99

-1

-1

-1

Main Func = PCH

5

HDA_SDIN0_CP U27
HDA_SYNC_C ODEC27
HDA_BITCLK_C ODEC27
HDA_SDOU T_CODEC27
HDA_SDOU T_CPU15
RTC_TEST25

D D

C C

ME_FWP_EC24

CLKREQ0_CN VI61

RF_RESET_B _CNVI61

HDA_SPKR15,27

BLUETOOTH _EN_CPU61

TBT_RTD3_P WR_EN71

TBT_FORC E_USB_PW R71

-TBT_PERST71

-TBT_PCIE_W AKE71

TOP_SWAP _EN24

WWA N_ANTENN A#62

4

PCH strap pin:

Flash Descriptor Security Overide/
Intel ME Debug Mode

HDA_SDOUT

The internal pull-down is disabled after
PLTRST# deasserts

RF_RESET_B _CNVI GPP_H1_SFRM

CLKREQ0_CN VI

TOP_SWAP _EN

PCH strap pin:

SPKR

HDA_SDOUT_CPU

Low = Default
High = Enable

TPAD14-OP-G P

1 2

R1913 33R2J-2-GP

1 2

R1912 33R2J-2-GP

1 2

R1902 0R2-PT5-LILY-GP-U

TOP SWAP OVERRIDE

High = TOP SWAP ENABLED

HDA_SPKR

*

Low = DISABLED (WEAK INTERNAL PD)

The internal pull-up

HDA_SYNC_C ODEC

HDA_BITCLK_C ODEC HDA_BITCLK_C PU
HDA_SDOU T_CODEC

ME_FWP_EC

1 2

R1908 33R2J-2-GP

1 2

R1920 33R2J-2-GP

1 2

R1921 33R2J-2-GP

1 2

R1909 1KR2J-1-GP

1 2

R1914 10KR2J-3-GP

DY

3

*

7 OF 20CPU 1G

GPP_G0/SD_CMD
GPP_G1/SD_DATA0
GPP_G2/SD_DATA1
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3

GPP_G5/SD_CD#

GPP_G6/SD_CLK

GPP_G7/SD_WP

GPP_A16/SD_1P8_SEL

SD_1P8_RCOMP
SD_3P3_RCOMP

WHISKEY-LAKE- GP

TP1903

HDA_SYNC_C PU
HDA_BITCLK_C PU
HDA_SDOU T_CPU
HDA_SDIN0_CP U

HDA_RST_N _CPU

1

GPP_H2_CLKR EQ0

HDA_SPKR

HDA_SYNC_C PU

HDA_SDOU T_CPU

TOP_SWAP _EN

BN34

HDA_SYNC/I2S0_SFRM

BN37

HDA_BCLK/I2S0_SCLK

BN36

HDA_SDO/I2S0_TXD

BN35

HDA_SDI0/I2S0_RXD

BL36

HDA_SDI1/I2S1_RXD/SNDW1_DATA

BL35

HDA_RST#/I2S1_SCLK/SNDW1_CLK

CK23

GPP_D23/I2S_MCLK

BL37

I2S1_SFRM/SNDW2_CLK

BL34

I2S1_TXD/SNDW2_DATA

CJ32

GPP_H1/I2S2_SFRM/CNV_BT_I2S_BCLK/CNV_RF_RESET#

CH32

GPP_H0/I2S2_SCLK/CNV_BT_I2S_SCLK

CH29

GPP_H2/I2S2_TXD/CNV_BT_I2S_SDI/MODEM_CLKREQ

CH30

GPP_H3/I2S2_RXD/CNV_BT_I2S_SDO

CP24

GPP_D19/DMIC_CLK0/SNDW4_CLK

CN24

GPP_D20/DMIC_DATA0/SNDW4_DATA

CK25

GPP_D17/DMIC_CLK1/SNDW3_CLK

CJ25

GPP_D18/DMIC_DATA1/SNDW3_DATA

CF35

GPP_B14/SPKR

/strap

GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7

/strap

ZZ.00CPU.271

CPU1 will use BOM control to Whiskeylake-U

2

SW Control : HW Control :

CH36
CL35
CL36
CM35
CN35
CH35
CK36
CK34

BW36
BY31

CK33
CM34

GPP_G1

SD_MMC_ID

BLUETOOTH _EN_CPU
SD_MMC_ID
RTC_TEST

TBT_RTD3_P WR_EN
TBT_FORC E_USB_PW R

-TBT_PERST

-TBT_PCIE_W AKE

WWA N_ANTENN A_CPU

SD_RCOMP

Low = REALTEK [RTS5232S]

High = GENESYS [GL9750]

200R2F-L-GP

1 2

R1901

R1903 1MR2J-1-GP
R1904 1KR2J-1-GP

G

R1903 R1904

1M-ohm

SDID

1 2

SDID

1 2

WWA N_ANTENN A#

DS

DY

Q1901
LSK3541G1ET2L-GP

1K-ohm

1M-ohm1K-ohm

*

3D3V_SUS

BB1_SIT_MAIN_W015
BB1_SIT_MAIN_W028

BB1_SVT_MAIN_W002
BB1_SVT_MAIN_W008

<-- Default

1

BB1_EVT_MAIN_L020

BB1_FVT_MAIN_L009

BB1_SIT_MAIN_L002

B B

A A

LBB-1

LBB-1

LBB-1

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
Taipei Hsie n 221, Taiwan, R.O. C.

Taipei Hsie n 221, Taiwan, R.O. C.

Title

Title

Title

CPU_(HDA/I2S/SD/DMIC)

CPU_(HDA/I2S/SD/DMIC)

CPU_(HDA/I2S/SD/DMIC)

Size Document Num ber Rev

Size Document Num ber Rev

Size Document Num ber Rev
A2

A2

A2

Thursday, May 30, 2019

Thursday, May 30, 2019

Thursday, May 30, 2019

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O. C.

Bumblebee-1

Bumblebee-1

Bumblebee-1

1

19 99

19 99

19 99

-1

-1

-1

Main Func = PCH

CNVi

NFC

ISH

D D

-FULL_CARD _POWER _OFF_CON N62

C C

LID_CLOSE#24,66
SENSOR_LID_OPE N#24,66

B B

EPRIVACY_CONT ROL55

CPU_I2C_SDA_P090
CPU_I2C_SCL_P090

CPU_I2C_SDA_ISH066,70
CPU_I2C_SCL_ISH066,70

TBT_FORC E_PWR71

GPP_B22_GSPI1_MOSI15

WWA N_PEWAKE #62

DDI_PRIORITY156

-KBD_BL_DTC T65

-ISH_GYRO_INT66

-ISH_ACCEL_INT66,70
NFC_ON90

-NFC_DT CT90
NFC_INT90

NFC_DLRE Q90
FAN_ID26
CNV_EN#61

WWA N_DISABLE#62

SMARTCAD_ DTCT#94

-UART_W AKE61

PAD_DISABLE65

TOUCH_ST OP#55

5

CNV_BRI_DT61

CNV_RGI_RSP61

CNV_RGI_DT15,61

CNV_BRI_RSP61

NRB_BIT15

PDG #575412 p128

3D3V_SUS

R2053 10KR2J-3-GP

R2068 4K7R2J-2-GP

3D3V_SUS

R2041 10KR2J-3-GP

PCH strap pin:

No Reboot

GSPI0_MOSI /
GPP_B18

1 2

1 2

1 2

NRB_BIT

Sampled at rising edge of PCH_PWROK

0 = Disable “No Reboot” mode.
1 = Enable “No Reboot” mode (PCH will disable the TCO
Timer system reboot feature). This function is useful
when running ITP/XDP.

The signal has a weak internal pull-down.

3D3V_S0

PIRQA#91

3D3V_S0

RTC_DET#25
GPP_D1215

1D8V_SUS

EVT/FVT/SIT/SVT:

Memory Configuration

00: 8Gb
01: 4Gb (Reserve)
10: 16Gb
11: 32Gb (Reserve)

GPP_H8

SDRAM_ID4

0

0

1 1

0

0

0

0

0=L, 1=H

1 2

R2067 10KR2J-3-GP

1 2

R2066 10KR2J-3-GP

DY

1 2

R2065 100KR2J-1-GP

1 2

R2071 10KR2J-3-GP

1 2

R2072 10KR2J-3-GP

DY

Bumblebee: GPP_H[0:23] is 1.8V.

12

MEM_ID0_1

R2015
10KR2J-3-GP

12

MEM_ID0_0

R2016
10KR2J-3-GP

1

01

0

0

01

11

0

1

01

01

12

MEM_ID1_1

R2017
10KR2J-3-GP

12

MEM_ID1_0

R2018
10KR2J-3-GP

Memory Supplier

00: Samsung
01: Micron
10: SK Hynix
11: (Reserve)

0

0

0

0

0

0

0

0

1

1

1

1

SOVP: (The Alternation of Memory Supplier SAMSUNG, MICRON and SK HYNIX)

R2011
R2012

DY
10K

DY
10K

DY

DY
10K10K

DY
10K

DY
10K10K

DY
10K

DY
10K

R2022
R2029

1.2M 1.0M

1.2K

1.2K

2.2K

2.2M

2.2K

2.2M

2.2K

4.3K

4.3K

4.3M

4.3K 10K

4.3M

R2073
R2074

DY
10K

10K

A A

5

DY

DY
10K 10K

DY 8GB (8Gb*8)

10K
DY

DY

10K
DY

10K
DY

4

PIRQA#

-UART_W AKE

SIO_EXT_WAKE #

FAN_ID

-KBD_BL_DTC T

PAD_DISABLE
TOUCH_ST OP#

12

MEM_ID2_1

R2022
10KR2J-3-GP

12

MEM_ID2_0

R2029
10KR2J-3-GP

Die Revision

GPP_H5GPP_H6GPP_H7

0

0

0

0

1

1

1

1

0

0

0

0

R2017

R2015

R2018

R2016

6.2M

1.0K

6.2K

1.0M1.2M

6.2M

1.0K

6.2K

2.0K2.2M

8.2M

2.0M

8.2K

2.0K 8.2K

2.0M

8.2M

2.0K

8.2M

2.0M

8.2K

2.7M

10M

2.7K4.3M

10K

2.7M

10M

2.7K

10K

2.7M

2.7K

10M

4

12

MEM_ID3_1

R2011
10KR2J-3-GP

12

MEM_ID3_0

R2012
10KR2J-3-GP

GPP_H4

0

0

0

0

1

0

0

0

0

0

1

CNV_RGI_DT CNV_RGI_DT_R

Strap pin

CNV_BRI_DT CNV_BRI_DT_R

1 2

R2069 33R2J-2-GP

1 2

R2070 33R2J-2-GP

WLAN_CNVi

NFC

Bumblebee: GPP_H[0:23] is 1.8V.

12

MEM_ID4_1

R2073
10KR2J-3-GP

12

MEM_ID4_0

R2074
10KR2J-3-GP

Memory ID

00 0

8

16

24

2

3

18

26

4

12

20

21

Memory IDSDRAM_ID0SDRAM_ID3SDRAM_ID4

16 16GB (16Gb*8)SAMSUNG K4AAG165WB-MCTD

2

18

4

20

SDRAM_ID0
SDRAM_ID1
SDRAM_ID2
SDRAM_ID3
SDRAM_ID4

Density

Supplier

SAMSUNG 8GB (8Gb*8)

16GB (16Gb*8)

SAMSUNG

MICRON

8GB (8Gb*8)

MICRON 8GB (8Gb*8) MT40A512M16TB-062E:J

16GB (16Gb*8)

MICRON

SK HYNIX H5AN8G6NCJR-VKC

8GB (8Gb*8)

16GB (16Gb*8)

SK HYNIX

16GB (16Gb*8)SK HYNIX H5ANAG6NCMR-VKC

DensitySDRAM_ID1 Vendor PNSDRAM_ID2 Supplier

8GB (8Gb*8)

MICRON MT40A512M16TB-062E:J3

16GB (16Gb*8)

MICRON

SK HYNIX H5AN8G6NCJR-VKC

8GB (8Gb*8)

16GB (16Gb*8)

SK HYNIX

16GB (16Gb*8)SK HYNIX H5ANAG6NCMR-VKC21

NFC_DLRE Q
PIRQA#

NFC_INT
NRB_BIT
CNV_EN#

WWA N_PEWAKE #
FAN_ID

GPP_B22_GSPI1_MOSI

CNV_BRI_RSP

CNV_RGI_RSP

-NFC_DT CT
TBT_FORC E_PWR
SIO_EXT_WAKE #

NFC_ON

CPU_I2C_SDA_P0
CPU_I2C_SCL_P0

DDI_PRIORITY1

SDRAM_ID0
SDRAM_ID1

SDRAM_ID2
SDRAM_ID3

SDRAM_ID4

Vendor PNSDRAM_ID0SDRAM_ID1SDRAM_ID2SDRAM_ID3

K4A8G165WC-BCTD

K4AAG165WB-MCTD

MT40A512M16LY-075:E

MT40A1G16KNR-075:E

H5ANAG6NAMR-UHC

K4A8G165WC-BCTD 8GB (8Gb*8)SAMSUNG0

MT40A512M16LY-075:EMICRON

MT40A1G16KNR-075:E

H5ANAG6NAMR-UHC

3

CC27

GPP_B15/GSPI0_CS0#

CC32

GPP_A7/PIRQA#/GSPI0_CS1#

CE28

GPP_B16/GSPI0_CLK

CE27

GPP_B17/GSPI0_MISO

CE29

GPP_B18/GSPI0_MOSI

CA31

GPP_B19/GSPI1_CS0#

CA32

GPP_A11/PME#/GSPI1_CS1#/SD_VDD2_PWR_EN#

CC29

GPP_B20/GSPI1_CLK

CC30

GPP_B21/GSPI1_MISO

CA30

GPP_B22/GSPI1_MOSI

CK20

GPP_F5/CNV_BRI_RSP

CG19

GPP_F6/CNV_RGI_DT

CJ20

GPP_F4/CNV_BRI_DT

CH19

GPP_F7/CNV_RGI_RSP

CR12

GPP_C20/UART2_RXD

CP12

GPP_C21/UART2_TXD

CN12

GPP_C22/UART2_RTS#

CM12

GPP_C23/UART2_CTS#

CM11

GPP_C16/I2C0_SDA

CN11

GPP_C17/I2C0_SCL

CK12

GPP_C18/I2C1_SDA

CJ12

GPP_C19/I2C1_SCL

CF27

GPP_H4/I2C2_SDA

CF29

GPP_H5/I2C2_SCL

CH27

GPP_H6/I2C3_SDA

CH28

GPP_H7/I2C3_SCL

CJ30

GPP_H8/I2C4_SDA

CJ31

GPP_H9/I2C4_SCL

/strap

/strap

CPU1 will use BOM control to Whiskeylake-U

Sensors Debug Hooks_543016:

Sensors Debug Hooks

ISH

DB2

ACES-CON 18-3-GP

20.K0698.018

3

GPP_D9/ISH_SPI_CS#/GSPI2_CS0#

GPP_D10/ISH_SPI_CLK/GSPI2_CLK
GPP_D11/ISH_SPI_MISO/GSPI2_MISO
GPP_D12/ISH_SPI_MOSI/GSPI2_MOSI

strap/

GPP_H10/I2C5_SDA/ISH_I2C2_SDA

GPP_H11/I2C5_SCL/ISH_I2C2_SCL

GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
GPP_C15/UART1_CTS#/ISH_UART1_CTS#

GPP_A12/ISH_GP6/BM_BUSY#/SX_EXIT_HOLDOFF#

ZZ.00CPU.271

-ISH_DEBUG_INT

-ISH_GYRO_INT

-ISH_ACCEL_INT
LID_CLOSE#_D
SENSOR_LID_OPE N#_D
SENSOR_BRD _ID

-GYRO_PRESEN CE

-ISH_GYRO_INT
SENSOR_BRD _ID

19
1

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
20

R2046 10KR2J-L-GP
R2047 10KR2J-L-GP
R2063 10KR2J-L-GP
R2064 10KR2J-L-GP
R2056 10KR2J-L-GP
R2054 10KR2J-L-GP
R2055 10KR2J-L-GP

R2057 10KR2J-L-GP
R2058 10KR2J-L-GP

CPU_I2C_SCL_ISH0
CPU_I2C_SDA_ISH0

CPU_I2C_SCL_ISH1
CPU_I2C_SDA_ISH1

-ISH_DEBUG_INT

-ISH_GYRO_INT

-ISH_ACCEL_INT
LID_CLOSE#_D

-GYRO_PRESEN CE

SENSOR_LID_OPE N#_D
SENSOR_BRD _ID

6 OF 20CPU1F

GPP_D5/ISH_I2C0_SDA

GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA

GPP_D8/ISH_I2C1_SCL

GPP_D13/ISH_UART0_RXD
GPP_D14/ISH_UART0_TXD

GPP_A18/ISH_GP0
GPP_A19/ISH_GP1
GPP_A20/ISH_GP2
GPP_A21/ISH_GP3
GPP_A22/ISH_GP4
GPP_A23/ISH_GP5

WHISKEY-LAKE- GP

1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2

DY

1 2

DY

3D3V_S0

2

3D3V_S0

2

CN22
CR22
CM22
CP22

CK22
CH20

CH22
CJ22

CJ27
CJ29

CM24
CN23
CM23
CR24

CG12
CH12
CF12
CG14

BW35
BW34
CA37
CA36
CA35
CA34
BW37

RTC_DET#
GPP_D12

CPU_I2C_SDA_ISH0
CPU_I2C_SCL_ISH0

CPU_I2C_SDA_ISH1
CPU_I2C_SCL_ISH1

-FULL_CARD _POWER _OFF_CON N
EPRIVACY_CONT ROL

-KBD_BL_DTC T
PAD_DISABLE

TOUCH_ST OP#
WWA N_DISABLE#
SMARTCAD_ DTCT#

-UART_W AKE

-GYRO_PRESEN CE

Bumblebee: GPP_H[0:23] is 1.8V.

SENSOR_LID_OPE N#_D

CPU_I2C_SCL_ISH1

CPU_I2C_SDA_ISH1

CPU_I2C_SDA_ISH0
CPU_I2C_SCL_ISH0

CPU_I2C_SDA_ISH1
CPU_I2C_SCL_ISH1

D2001 RB530SM-30T2R -GP-U
D2002 RB530SM-30T2R -GP-U

R2006 0R2J-L-GP

R2007 0R2J-L-GP

KA
KA

3D3V_S0

1 2

DY

Q2001

3 4
2

5

1

6

Note:ZZ.27002.F7C01

2N7002KDW -1-GP

75.27002.F7C

1 2

DY

LBB-1

LBB-1

LBB-1

Title

Title

Title

CPU_(UART/I2C/ISH)

CPU_(UART/I2C/ISH)

CPU_(UART/I2C/ISH)

Size Document Num ber Rev

Size Document Num ber Rev

Size Document Num ber Rev
A2

A2

A2

Thursday, May 30, 2019

Thursday, May 30, 2019

Thursday, May 30, 2019

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

BB1_EVT_MAIN_W008
BB1_EVT_MAIN_W009
BB1_EVT_MAIN_W011
BB1_EVT_MAIN_W012
BB1_EVT_MAIN_W021
BB1_EVT_MAIN_W046

BB1_FVT_MAIN_W020

BB1_SVT_MAIN_W016

(PDG#543016) Ensure that all I2C interface
on-board terminations are pulled up
to the same voltage rail as the device/end point.

-ISH_DEBUG_INT

-ISH_GYRO_INT

-ISH_ACCEL_INT
LID_CLOSE#LID_CLOSE#_D

SENSOR_LID_OPE N#
SENSOR_BRD _ID

CPU_I2C_SCL_ISH1_ EC 24

CPU_I2C_SDA_ISH1 _EC 24

Bumblebee-1

Bumblebee-1

Bumblebee-1

1

BB1_FVT_MAIN_L002

RN2007

1

4

2 3

SRN1KJ-7-G P

RN2008

1

4

2 3

SRN1KJ-7-G P

1

TP2001

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
Taipei Hsie n 221, Taiwan, R.O. C.

Taipei Hsie n 221, Taiwan, R.O. C.

Taipei Hsie n 221, Taiwan, R.O. C.

20 99

20 99

20 99

3D3V_S0

3D3V_S0

TPAD14-OP-G P

-1

-1

-1

5

Main Func = PCH

CNVi

D D

C C

CNV_WT_DN061
CNV_WT_DP061

CNV_WT_DN161
CNV_WT_DP161

CNV_WT_CLK_DN61
CNV_WT_CLK_DP61

CNV_WR_DN061
CNV_WR_DP061

CNV_WR_DN161
CNV_WR_DP161

CNV_WR_CLK_DN61
CNV_WR_CLK_DP61

WIFI_RF_EN_CPU61

CPU_UARTx_RXD68

CPU_UARTx_TXD68

CPU_C10_GATE#40
GPP_H2115
GPD_715
GPP_H2315

-WWAN_RESET62
WWAN_CFG062
WWAN_CFG162
WWAN_CFG262
WWAN_CFG362
NFC_ACTIVE65,90
IR_CAM_DET#66
DMIC_DET#66

-TAMPER_SW_DTCT17

4

R2101 150R2F-1-GP

Debug Card

3D3V_S0

1 2

R2122 10KR2J-3-GP

1 2

R2123 10KR2J-3-GP

CNVi

12

R2120
0R2J-2-GP

1 2

DY

CNV_WR_DN0
CNV_WR_DP0

CNV_WR_DN1
CNV_WR_DP1

CNV_WT_DN0
CNV_WT_DP0

CNV_WT_DN1
CNV_WT_DP1

CNV_WR_CLK_DN
CNV_WR_CLK_DP

CNV_WT_CLK_DN
CNV_WT_CLK_DP

CNV_WT_RCOMP
WWAN_CFG2

-WWAN_RESET
NFC_ACTIVE_CPUNFC_ACTIVE

CPU_UARTx_RXD
CPU_UARTx_TXD
IR_CAM_DET#
DMIC_DET#

WWAN_CFG0
WWAN_CFG1

GPP_F23

12

R2102
100KR1J-GP

IR_CAM_DET#
DMIC_DET#

3

CR30

CNV_WR_D0N

CP30

CNV_WR_D0P

CM30

CNV_WR_D1N

CN30

CNV_WR_D1P

CN32

CNV_WT_D0N

CM32

CNV_WT_D0P

CP33

CNV_WT_D1N

CN33

CNV_WT_D1P

CN31

CNV_WR_CLKN

CP31

CNV_WR_CLKP

CP34

CNV_WT_CLKN

CN34

CNV_WT_CLKP

CP32

CNV_WT_RCOMP#CP32

CR32

CNV_WT_RCOMP#CR32

CP20

GPP_F0/CNV_PA_BLANKING

CK19

GPP_F1

CG17

GPP_F2

CR14

GPP_C8/UART0_RXD

CP14

GPP_C9/UART0_TXD

CN14

GPP_C10/UART0_RTS#

CM14

GPP_C11/UART0_CTS#

CJ17

GPP_F8/CNV_MFUART2_RXD

CH17

GPP_F9/CNV_MFUART2_TXD

CF17

GPP_F23/A4WP_PRESENT

CPU1 will use BOM control to Whiskeylake-U

GPP_H18/CPU_C10_GATE#

GPP_D4/IMGCLKOUT0/BK4/SBK4

ZZ.00CPU.271

9 OF 20CPU1I

GPP_H19/TIMESYNC0

GPP_H21
GPP_H22
GPP_H23

GPP_F10

GPD7

GPP_F3

GPP_H20/IMGCLKOUT1
GPP_F12/EMMC_DATA0

GPP_F13/EMMC_DATA1
GPP_F14/EMMC_DATA2
GPP_F15/EMMC_DATA3
GPP_F16/EMMC_DATA4
GPP_F17/EMMC_DATA5
GPP_F18/EMMC_DATA6
GPP_F19/EMMC_DATA7

GPP_F20/EMMC_RCLK

GPP_F21/EMMC_CLK

GPP_F11/EMMC_CMD

GPP_F22/EMMC_RESET#

EMMC_RCOMP

WHISKEY-LAKE-GP

2

R2119
0R2J-2-GP

CN27
CM27

GPP_H21

CF25
CN26

GPP_H23

CM26
CK17

GPD_7

BV35
CN20

WIFI_RF_EN_CPU

CG25
CH25

CR20
CM20
CN19
CM19
CN18
CR18
CP18

GPP_F: VCCPGPPF = 1.8V Only

CM18
CM16

CP16

WWAN_CFG3

CR16

-TAMPER_SW_DTCT_CPU -TAMPER_SW _DTCT

CN16

EMMC_RCOMP

CK15

1 2

DY

R2108 200R2F-L-GP

CPU_C10_GATE#GPPC_H18_BOOTMPC

R2121
0R2-PT5-LILY-GP-U

1 2

1 2

1

BB1_SIT_MAIN_W002

BB1_SVT_MAIN_W008

BB1_EVT_MAIN_L001BB1_EVT_MAIN_W009

B B

A A

5

4

3

2

LBB-1

LBB-1

LBB-1

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

CPU_(CSI/EMMC/CNVI)

CPU_(CSI/EMMC/CNVI)

CPU_(CSI/EMMC/CNVI)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A3

A3

A3

Thursday, May 30, 2019

Thursday, May 30, 2019

Thursday, May 30, 2019

Date: Sheet of

Date: Sheet of

Date: Sheet of

Bumblebee-1

Bumblebee-1

Bumblebee-1

1

21 99

21 99

21 99

-1

-1

-1

Main Func = PCH

5

1D05V_SUS

1D8V_SUS

D D

VCCDSW_1P05 (BT24): PCH internal VRM

1D05V_VCCPR IM_MPHY

C C

R2206:
For DEEP Sx leakage debug

3D3V_SUS

3D3V_S5

R2206
0R0402-PAD-1- GP

1 2

1D05V_VCCPR IM_MPHY

12

EC2201

SCD1U6D3V1KX-GP

1D05V_SUS

1D05V_VCCAMP HYPLL

1D05V_SUS

1D05V_SUS

3D3V_SUS

2.57A

1D05V_SUS

12

DY

C2223

SC1U6D3V1MX-GP

1D05V_VCCD SW

12

C2224

SC1U6D3V1MX-GP

3D3V_SUS_VCC HDA

BP20

VCCPRIM_1P05

BW16

VCCPRIM_1P05

BW18

VCCPRIM_1P05

BW19

VCCPRIM_1P05

BY16

VCCPRIM_1P05

CA14

VCCPRIM_1P05

CC15

VCCPRIM_1P8

CD15

VCCPRIM_1P8

CD16

VCCPRIM_1P8

CP17

VCCPRIM_1P8

CB22

VCCPRIM_3P3

CB23

VCCPRIM_3P3

CC22

VCCPRIM_3P3

CC23

VCCPRIM_3P3

CD22

VCCPRIM_3P3

CD23

VCCPRIM_3P3

CP29

VCCPRIM_3P3

BU15

VCCPRIM_CORE

BU22

VCCPRIM_CORE

BV15

VCCPRIM_CORE

BV16

VCCPRIM_CORE

BV18

VCCPRIM_CORE

BV19

VCCPRIM_CORE

BV20

VCCPRIM_CORE

BV22

VCCPRIM_CORE

BW20

VCCPRIM_CORE

BW22

VCCPRIM_CORE

CA12

VCCPRIM_CORE

CA16

VCCPRIM_CORE

CA18

VCCPRIM_CORE

CA19

VCCPRIM_CORE

CA20

VCCPRIM_CORE

CB12

VCCPRIM_CORE

CB14

VCCPRIM_CORE

CB15

VCCPRIM_CORE

BT24

VCCDSW_1P05

BU14

VCCAPLL_1P05

BV12

VCCPRIM_MPHY_1P05

BW12

VCCPRIM_MPHY_1P05

BW14

VCCPRIM_MPHY_1P05

BY12

VCCPRIM_MPHY_1P05

BY14

VCCPRIM_MPHY_1P05

BV2

VCCAMPHYPLL_1P05

BR15

VCCAPLL_1P05

CC12

VCCDUSB_1P05

BR24

VCCDSW_3P3

BT20

VCCHDA

BV23

VCCSPI

BT18

VCCPRIM_1P05

BT19

VCCPRIM_1P05

BU18

VCCPRIM_1P05

BU19

VCCPRIM_1P05

BT22

VCCPRIM_1P05

BP22

VCCPRIM_1P05

BV14

VCCPRIM_MPHY_1P05

ZZ.00CPU.271

CPU1 will use BOM control to Whiskeylake-U

16 OF 20CPU 1P

VCCPRIM_3P3

VCCRTC

VCCPRIM_1P05

DCPRTC

VCCPRIM_1P05
VCCAPLL_1P05

VCCA_BCLK_1P05

VCCAPLL_1P05

VCCA_SRC_1P05

VCCA_XTAL_1P05

VCCDPHY_1P24
VCCDPHY_1P24

VCCDPHY_1P24
VCCDPHY_1P24
VCCDPHY_1P24

VCCDSW_3P3

VCCA_19P2_1P05

VCCPRIM_1P8
VCCPRIM_1P8
VCCPRIM_1P8
VCCPRIM_1P8
VCCPRIM_1P8

VCCPRIM_3P3

VCCPRIM_3P3

GPP_B0/CORE_VID0
GPP_B1/CORE_VID1

WHISKEY-LAKE- GP

4

3D3V_SUS

3D3V_VCCPR TC

3D3V_S5

1D8V_SUS

V0.85A_VID0
V0.85A_VID1

1D05V_SUS

1D05V_SUS

3D3V_SUS

1
1

VCCRTCE XT

1D05V_VCCA_XT AL

1D24V_VCCD PHY_EC

TPAD14-OP-G P

TP2201

TPAD14-OP-G P

TP2202

1 2

C2201 SCD1U6D 3V1KX-GP

1D24V_VCCD PHY

VCCDPHY_1P24 (BY23 CA23 CP25 BY24 CA24): PCH internal VRM

CB16

BR23
BY20

BP24

BR20
BT12
BP14
BR14
BU12
CP5
BY24

CA24
BY23

CA23
CP25

BT23
BR12

CC18
CC19
CD18
CD19
CP23

BW23

BP23
CB36

CB35

3

VCCRTCEXT (BP24): PCH internal VRM

2

WHL QS/CFL U/WHL ES1_CNL U22

K12

RSVD#K12

K14

RSVD#K14

K15

RSVD#K15

K17

RSVD#K17

K18

RSVD#K18

K20

RSVD#K20

L25

RSVD#L25

M24

RSVD#M24

M26

RSVD#M26

P24

RSVD#P24

P26

RSVD#P26

R24

RSVD#R24

R25

RSVD#R25

R26

RSVD#R26

V24

RSVD#V24

W25

RSVD#W25

Y24

RSVD#Y24

Y25

RSVD#Y25

G2

RSVD#G2

G1

RSVD#G1

C34

RSVD#C34

G3

RSVD#G3

G4

RSVD#G4

A34

RSVD#A34

B35

RSVD#B35

AJ27

RSVD#AJ27

AH26

RSVD#AH26

L5

RSVD#L5

ZZ.00CPU.271

CPU1 will use BOM control to Whiskeylake-U

15 OF 20CPU1O

RSVD#AA24
RSVD#AA26
RSVD#AB25
RSVD#AC24
RSVD#AC25
RSVD#AC26
RSVD#AD24
RSVD#AD26

RSVD#V25
RSVD#T25
RSVD#A35
RSVD#D34

RSVD#N5

WHISKEY-LAKE- GP

AA24
AA26
AB25
AC24
AC25
AC26
AD24
AD26
V25
T25
A35
D34
N5

1

BB1_FVT_MAIN_W016
BB1_FVT_MAIN_W017
BB1_FVT_MAIN_W020

BB1_SVT_MAIN_W008

BB1_EVT_MAIN_L007BB1_EVT_MAIN_W032

C2224 close to BR24

12

SCD1U6D3V1KX-GP

C2207

3D3V_SUS

12

SCD1U6D3V1KX-GP

TBD

Layout Note:

1uF:
C2105 near V19
C2106 near AK17
C2107 near AG15
C2109 near Y16
C2110 near T16
C2111 near AJ19

Layout Note:

0.1uF:
C2225 near BT20

C2225

12

12

DY

C2210

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

TBD TBD

1D05V_SUS

12

C2214

SC1U6D3V1MX-GP

4

B B

SC1U6D3V1MX-GP

SC22U6D3V3MX-L1-GP

12

C2203

12

DY

C2208

12

SC1U6D3V1MX-GP

5

C2204

Layout Note:

C2208 near BV2
C2209 near BV2

12

C2202

SC1U6D3V1MX-GP

1D05V_VCCAMP HYPLL

12

C2209

SC1U6D3V1MX-GP

A A

12

12

C2206

C2205

SCD1U6D3V1KX-GP

SC1U6D3V1MX-GP

1D05V_VCCD SW1D8V_SUS3D3V_S5

1D05V_SUS

12

C2212

C2211

SC1U6D3V1MX-GP

Layout Note:

22uF:
C2113 near K15

1 2

12

C2213

SC1U6D3V1MX-GP

1D05V_SUS

1D05V_SUS

1D24V_VCCD PHY_EC

1 2

1 2

12

12

C2215

SC1U6D3V1MX-GP

SC1U6D3V1MX-GP

12

C2218

SC4D7U6D3V3KX-GP

R2202
0R0603-PAD-1- GP-U

R2203
0R0603-PAD-1- GP-U

R2205
0R0603-PAD-1- GP-U

12

C2216

C2217

SC1U6D3V1MX-GP

1D05V_VCCA_XT AL

12

C2219

SC1U6D3V1MX-GP

3

1D05V_VCCA_XT AL1D05V_SUS

1D05V_VCCPR IM_MPHY1D05V_SUS

1D05V_VCCAMP HYPLL

Layout Note:

1uF:
C2101 near AB19
C2104 near K17
C2116 near A10
C2121 near AL1

1D05V_VCCPR IM_MPHY

SC22U6D3V3MX-L1-GP

3D3V_VCCPR TCRTC_A UX_S5

R2204
0R0603-PAD-1- GP-U

1 2

3D3V_VCCPR TC

C2221

1 2

SC1U6D3V1MX-GP

SCD1U6D3V1KX-GP

TBD

Layout Note:

1uF:
C2116 near A10

12

C2220

22uF:
C2115 near K19
C2119 near N20
C2122 near L19

12

C2222

Layout Note:

C2221 near BR23
C2222 near BR23

2

LBB-1

LBB-1

LBB-1

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
Taipei Hsie n 221, Taiwan, R.O. C.

Taipei Hsie n 221, Taiwan, R.O. C.

Title

Title

Title

CPU(PCH-LP PWR&CAPS)

CPU(PCH-LP PWR&CAPS)

CPU(PCH-LP PWR&CAPS)

Size Document Num ber Rev

Size Document Num ber Rev

Size Document Num ber Rev
A2

A2

A2

Thursday, May 30, 2019

Thursday, May 30, 2019

Thursday, May 30, 2019

Date: Sheet of

Date: Sheet of

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O. C.

Bumblebee-1

Bumblebee-1

Bumblebee-1

1

22 99

22 99

22 99

-1

-1

-1

5

Main Func = PCH

4

3

2

1

18 OF 20CPU1R

CR34

VSS

D D

C C

B B

BT5

VSS

BY5

VSS

CP35

VSS

CM37

VSS

CK37

VSS

AW1

VSS

CM1

VSS

BD6

VSS

AY4

VSS

B34

VSS

E35

VSS

A4

VSS

AE24

VSS

AE26

VSS

AF25

VSS

AG24

VSS

AG26

VSS

AH24

VSS

AH25

VSS

B2

VSS

B36

VSS

C36

VSS

C37

VSS

CN1

VSS

CN2

VSS

CN37

VSS

CP2

VSS

D1

VSS

A32

VSS

F33

VSS

A3

VSS

BJ7

VSS

CJ36

VSS

A36

VSS

BK10

VSS

CJ4

VSS

AB27

VSS

BK2

VSS

CK1

VSS

AB3

VSS

BK28

VSS

AB30

VSS

BK3

VSS

CK4

VSS

AB33

VSS

BK33

VSS

CK7

VSS

AB36

VSS

BK4

VSS

CL2

VSS

AB4

VSS

BK7

VSS

CM13

VSS

AB7

VSS

BL25

VSS

CM17

VSS

AC10

VSS

BL28

VSS

CM21

VSS

AC27

VSS

BL29

VSS

CM25

VSS

AC30

VSS

BL30

VSS

CM29

VSS

BL31

VSS

CM31

VSS

AD33

VSS

BL32

VSS

CM33

VSS

AD35

VSS

WHISKEY-LAKE-GP

CPU1 will use BOM control to Whiskeylake-U CPU1 will use BOM control to Whiskeylake-U CPU1 will use BOM control to Whiskeylake-U

ZZ.00CPU.271

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

BL7
AE25
BM33
CM5
AE27
BM35
CM9
AE30
BM36
CN13
AE7
BM9
CN17
AF27
BN30
CN21
AF3
BN7
CN25
AF30
CN29
AF33
BP15
AF36
AF4
CN5
AF7
BP25
CN9
AG10
BP3
CP1
BP32
CP11
AH27
BP33
CP13
AH28
BP4
CP15
AH29
BP7
CP19
AH30
CP21
AH31
BR19
CP27
AH33
BR25
AH35
CP37
AJ25
BT15
AJ28
BT16
CP9
AJ7
CR2
AK3
CR36
AK33
D21
AK36
BT25
D25
AK4
BT28
AL28
BT33
D5
AL29

BT35
AL32

BT36

AM10

BU11

E23

AM28

E27
AM33
BU23

E29
AM35
BU24

BU25
AN25

BU7

AN28

BV11

F12
AN29

AN30
AN31

BV3
AN7

BV31

F21

AN8

BV33

BV4
AP3

BW11

AP33

BW15

G21

AP36

G27
AP4
G33

AR28

G35
G36

AT33

BW24

AT35

H21

AT36

BW7

H27

AT4

BY11

AU10

BY15

AU28

BY22

AU29

AL7

E31
E33

F15
F18

F24

J12
J15

D6

D8
D9

E9

F2

F3

F4

G9

H9

19 OF 20CPU1S

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

WHISKEY-LAKE-GP

ZZ.00CPU.271

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

BY25
J18
AU32
BY28
J21
AV25
BY33
J24
AV28
BY35
J33
AV3
BY36
J36
AV33
J6
AV36
C1
K21
AV4
C21
K22
AV6
C25
K24
AV8
C29
K25
AW28
C33
K27
AW29
C4
K28
AW3
C9
K29
AW30
CA11
K3
AW31
CA15
K30
AY33
CA22
K31
AY35
K32
B12
K4
B15
CA25
K9
B18
CB11
L27
B21
L33
B23
L35
B25
CB18
L36
B27
CB19
L6
B29
CB2
N25
B31
CB20
N27
CB25

B37

CB3

P10

CB33

CB4

P33

CB7

P36
BA10
CC11

BA28

BA3
CC20

R27

BB3
CC25

R28
BB33
CC28

R29
BB36
CC31

R30

BB4

CC7

R31
BC25
CD11

CD12
BC29

CD14

BC32
CD24

CD25

BC8

CE33

U26
BD28
CE35

BD33
CE36

V26
BD35

CE7

V27
BD36
CF11

BE10
CF14

V30
BE28
CF19

V33
BE29

CF2

V36

BE3

N6

B5
P3

B7

B9

P4
P7

T27
T30

T33
T35

T36

T7

U7

V3

20 OF 20CPU1T

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

WHISKEY-LAKE-GP

ZZ.00CPU.271

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

CF23
V4
BE30
CF28
W10
BE31
CF3
W27
CF4
W30
BF3
CG33
W7
BF33
CG7
BF36
Y26
BF4
CH31
Y27
BG25
Y30
BG28
CJ11
Y33
CJ14
Y35
BH28
CJ19
Y7
BH29
CJ23
BH32
CJ28
BH33
CJ33
BH35
CJ35
BP19
BR16
BY18
BY19
CC16
BU16
CC14
BR22
BU20
CD20
BT14
BP12
CB24
CC24
J5
U24
BD7
AR4
AU4
AW4
BA6
BC4
BE4
BE8
BA4
BD4
BG4
CJ2
CJ3
AM5
CM4
AC5
AG5
CR6

A A

5

4

3

2

LBB-1

LBB-1

LBB-1

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

CPU_(VSS)

CPU_(VSS)

CPU_(VSS)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A3

A3

A3

Thursday, May 30, 2019

Thursday, May 30, 2019

Thursday, May 30, 2019

Date: Sheet of

Date: Sheet of

Date: Sheet of

Bumblebee-1

Bumblebee-1

Bumblebee-1

1

23 99

23 99

23 99

-1

-1

-1

Main Func = KBC

D D

C C

1 2

R2421 0R0402-PAD-1-GP

1 2

R2417 0R0402-PAD-1-GP

THINK_A_LED#66

B B

5

3D3V_LDO_PD 3D3V_AUX_S53D3V_AUX_KBC

D2401
RB530SM-30T2R-GP-U

KA

DY

EC_AGND

VCCST_PWRGD is ALL_SYS_PWRGD

NOTE:
place all the ADC input capacitors close to the ADC pins.

PSL

3D3V_AUX_S5

AC_IN#44

KBC_PWRBTN_EC#

LID_CLOSE#20,66

AOU_IFLG#35

3D3V_AUX_KBC

1 2

R2420 100KR2J-1-GP

DY

3D3V_AUX_S5

1 2

R2414 10KR2J-3-GP

1 2

R2456 10KR2J-3-GP

3D3V_S5

1 2

R2450 100KR2J-1-GP

1 2

R2423 3K3R2J-3-GP

1 2

R2425 3K3R2J-3-GP

3D3V_S0

1 2

R2454 100KR2J-1-GP

3D3V_LDO_PD

1 2

R2496 3K3R2J-3-GP

DY

1 2

R2497 3K3R2J-3-GP

DY

EC_THINKA_PWRLED_Q

Q2406

DS

LSK3541G1ET2L-GP

EC_THINKA_PWRLED

G

1D05V_VCCIO

NOTE:
E51_RxD for debug card detestion
When using debug card,ASM R2451 and flash KBC code

PROCHOT_EC

12

G

R2422
100KR2J-1-GP

SC10U6D3V3MX-GP

SENSOR_LID_OPEN#20,66

USBC_USB2_BUS_EN#74,75

TOP_SWAP_EN19
AC_PRESENT17

HDD_DTCT#_EC

SENSOR_LID_OPEN#

AOU_IFLG#

USB3_PORT2_ON
EC_I2C_SCL_PD
EC_I2C_SDA_PD

EC_GSENSOR_INT#

EC_I2C_SCL_PD
EC_I2C_SDA_PD

EC_THINKA_PWRLED89

Q2402
LSK3541G1ET2L-GP

DS

1 2

12

RSMRST_PWRGD#40

LCD_SELF_TEST_ON55

R2438
2D2R3J-2-GP

C2401

PM_SLP_SUS#17,40,52,53
PCH_BATLOW#17,71

RTCRST_ON25
PD_I2C_INT#73

-HOTKEY65
HP_JACK_IN30

VCCST_PWRGD17,40

PM_PWRBTN#17,63,99

TP4_RESET65

USB_AO_SEL235

USB3_PORT2_ON35

PM_SLP_WLAN#17,61
SPK_MUTE#27

PECI_CPU3

NON_PSL

1 2

R2424 0R5J-5-GP

1 2

R2427 0R0603-PAD-1-GP-U

12

C2404

SCD1U6D3V1KX-GP

Close to KBC

AD_IA44

SSD_DTCT#63

BAT_IN#43

-INTRUDER_EC17

-TBT_RESET_EC71

NOTE:
PWM Signal :

1. If unused, select altrnative GPIO function and enable internal pull-down.

2. Please measure and make sure that the rise time of VCC_POR is less than 10us.

THERM_TACH26
PAD_RESET#65
PM_SLP_S3#17,40,71,99

FAN_PWM26PWRLED#64

KBC_BEEP27

KBD_BL_PWM65

EC_THINKA_PWRLED

-LED_ESC65

-LED_F165

BEEP_ENABLE#27

RSMRST#_KBC17
L_BKLT_EN4

-LED_F465
CHARGE_LED64

EC_E51_TXD68

EC_E51_RXD68

R2465 75R2J-1-GP

3D3V_AUX_KBC_AVCC

12

C2409

SC10U6D3V3MX-GP

Close to KBC

3D3V_AUX_KBC_VCC

12

12

12

DY

C2405

C2406

SCD1U6D3V1KX-GP

DY

1 2

1 2

1 2
1 2

DY

1 2

1 2

1 2

1 2

DY
DY

1 2

C2407

SCD1U6D3V1KX-GP

12

12
12

PWR_KBC_VCORF_OUT

C2412

1 2

SC1U6D3V1MX-GP

NOTE:
C2412 must place close to VCORF pin.

KA

12
12

12

12

SCD1U6D3V1KX-GP

SCD1U6D3V1KX-GP

C2413 SCD1U6D3V1KX-GP

R2480 0R2-PT5-LILY-GP-U
R2473 0R2-PT5-LILY-GP-U

R2476 0R2-PT5-LILY-GP-U
R2434 0R2J-2-GP

R2436 0R2-PT5-LILY-GP-U

R2479 0R2-PT5-LILY-GP-U

R2405 100KR2J-1-GP
R2481 0R2-PT5-LILY-GP-U

R2471 0R2-PT5-LILY-GP-U
D2402 RB530SM-30T2R-GP-U

R2445 0R2J-2-GP
R2451 0R2J-2-GP
R2484 0R2J-2-GP

R2416 43R2J-L-GP
R2477 0R0402-PAD-1-GP

R2477 and C2415
Need very close to EC

1 2

SCD1U6D3V1KX-GP

EC_AGND

SCD1U6D3V1KX-GP

EC_E51_TXD_R
PM_SLP_WLAN#_R

ECRST#

C2415

PROCHOT#_CPU 3,44,46

12

C2410

12

C2408

PCB_ID
PM_SLP_SUS#_R
BATLOW#_KBC_R

SKU_ID

HP_JACK_IN_R

HDD_DTCT#_EC

BAT_IN#_R
EC_ENABLE#

AC_IN_KBC#

PANEL_BLEN

EC_GPIO67

PECI
1D05V_EC_VTT

4

E7

U2401A

VCCK9VCCF9VCC

D2

GPIO90 /AD0

D1

GPIO91 /AD1

E4

GPIO92 /AD2

E2

GPIO93 /AD3

G2

GPIO05 /AD4

D4

GPIO04 /AD5

C1

GPIO03 /EXT_PUR ST#/AD6

E1

GPIO94 /DA0

F1

GPIO95 /DA1

G5

GPIO96 /DA2

G4

GPIO97 /DA3

K10

GPIO51 /TA3

K1

GPIO20 /TA2

F2

GPIO80 /VD_IN1

C2

GPIO07 /AD7/VD_ IN2

H1

GPIO82 /VD_OUT1

J1

GPIO84 /VD_OUT2

B6

GPIO41 /F_WP/P SL_GPI O41

E8

PSL_OUT /GPIO71

E9

PSL_IN1 /GPI70

B1

PSL_IN2 /GPI06/E XT_PURS T#

J8

GPIO42 /PSL_IN3 /GPI42

M9

GPIO43 /PSL_IN4 /GPI43

A5

GPIO76 /SPI_MOS I

D6

GPIO02 /SPI_MIS O

B5

GPIO75 /SPI_SC K

D7

GPIO00 /32KCLK IN

G10

VCORF

U2401B

L12

GPIO56 /TA1

A11

GPIO14 /TB1

B10

GPIO01 /TB2

L13

GPIO15 /A_PWM

K2

GPIO21 /B_PWM

B11

GPIO13 /C_PWM

A10

GPIO32 /D_PWM

A6

GPIO66 /G_PWM/P SL_GPI O66

D9

GPO33/H_ PWM/VD1 _EN#

G1

GPIO30 /F_WP# /RTS1

M8

GPIO36 /TB3/CTS 1

N8

GPIO34 /SIN1/CIR RXL

N1

GPIO67 /SOUT1/LP C_ESPI _STRAP 1

M10

GPIO45 /E_PWM/D TR1_BO UT1

K8

GPIO40 /F_PWM/1 _WIRE /RI1

H2

GPIO83 /SOUT_CR

J2

GPIO87 /CIRRXM/S IN_CR

M13

GPIO55 /CLKOUT

A4

EXT_RS T#

J7

PECI

K7

VTT

D5

J4

F4

K5

VCC

AVCC

VCCSPI

VDD/VESPI

GPIO65 /SMI/LPC_ ESPI_S TRAP0

GPIO47 /SCL4A/N2 TCK/DPW ROK

GPIO53 /SDA4A/N2 TMS/RSMRS T#

GNDJ9GNDG9GNDE6GNDE5GNDH5GNDJ5AGND

R2410
0R0402-PAD-1-GP

1 2

KBSOUT0 /GPOB0/S OUT_CR/J ENK#

CPU_SMB_SCL_P1

CPU_SMB_SDA_P1H_PROCHOT#_EC

3D3V_S0

12

C2402

SC10U6D3V3MX-GP

SCD1U6D3V1KX-GP

Close to KBC

3D3V_KBC_VBKUP

3D3V_KBC_VSTBY_S5

D8

H4

VSBY

VBKUP

GPIO24 /ESPI_A LERT

LRESET #/GPIOF 7/PLTRS T#

LCLK/GP IOF5/ES PI_CLK

LFRAME/G PIOF6/E SPI_CS

LAD3/GP IOF4/ES PI_IO3
LAD2/GP IOF3/ES PI_IO2
LAD1/GP IOF2/ES PI_IO1
LAD0/GP IOF1/ES PI_IO0

SERIRQ /GPIOF0 /ESPI_R ST

GPIO11 /CLKRUN#/E SPI_CS 2

ECSCI# /GPIO54

GPIO10 /LPCPD#

GPIO85 /GA20/N2T CK

KBRST/G PIO86/N2 TMS

GPIO52 /PSDAT3

GPIO50 /PSCLK3

GPIO27 /PSDAT2

GPIO26 /PSCLK2

GPIO35 /PSDAT1

GPIO37 /PSCLK1

GPIO17 /SCL1/N2T CK

GPIO22 /SDA1/N2T MS

GPIO73 /SCL2/N2T CK

GPIO74 /SDA2/N2T MS

GPIO23 /SCL3/N2T CK

GPIO31 /SDA3/N2T MS

GPIO44 /SCL4B

GPIO46 /SDA4B/C IRRXM

F_CS0/G PIOC6

F_SCK/G PIOC7

F_SDIO /F_SDIO 0/GPIOC 5

F_SDI/F _SDIO1 /GPIOC4

GPIO81 /F_WP# /F_SDIO 2

GPIO77 /F_SDIO 3

NPCE388PB0BX-GP

F5

071.00388.000U

NOTE:
Pleae place R2410 close to AGND pin.

EC_AGND

NOTE:
Connect GND and AGND planes via either
0R resistor or one point layout connection.

KBSOUT1 /GPIOB1 /TCK
KBSOUT2 /GPIOB2 /TMS

KBSOUT3 /GPIOB3 /TDI

KBSOUT4 /GPOB4/J EN0#

KBSOUT5 /GPIOB5 /TDO

KBSOUT6 /GPIOB6 /RDY#

KBSOUT7 /GPIOB7

KBSOUT8 /GPIOC0
KBSOUT9 /GPOC1/S DP_VIS #
KBSOUT1 0/P80_C LK/GPIO C2
KBSOUT1 1/P80_D AT/GPIO C3

KBSOUT1 2/GPO64 /TEST#

KBSOUT1 3/GP(I)O6 3/TRIST #

KBSOUT1 4/GP(I)O6 2/XORTR #

KBSOUT1 5/GPIO6 1/XOR_O UT

GPIO60 /KBSOUT1 6/DSR1#
GPIO57 /KBSOUT1 7/DCD1#

KBSIN0/G PIOA0/N2 TCK
KBSIN1/G PIOA1/N2 TMS

KBSIN2/G PIOA2
KBSIN3/G PIOA3
KBSIN4/G PIOA4
KBSIN5/G PIOA5
KBSIN6/G PIOA6
KBSIN7/G PIOA7

NPCE388PB0BX-GP

071.00388.000U

3D3V_S0

6

2N7002KDW-1-GP

75.27002.F7C

12

C2403

KBC PWR supply at PSL mode

R2483 0R0402-PAD-1-GP

R2482 0R0402-PAD-1-GP

1 OF 2

N6
M6
N5
M5
M4
N4
M3
N3
M2
K6
J6
N13
N2
L2
M1

M12
M11
M7
N7
B7
A7

A8
B8
B9
A9
K4
L1
N11
N12
N9
N10

B2
A1
A3
B3
A2
B4

2 OF 2

D10
E13
E12
E10
F13
F12
F10
G12
G13
H13
H12
H10
H9
J13
J12
J10
K13
K12

D12
D13
C12
C13
B12
B13
A13
A12

3D3V_S0

Q2403

2345
1

Note:ZZ.27002.F7C01

1 2

1 2

PLTRST#_EC

-LED_CAPSLOCK_R
S5_ENABLE_R
ECSCI#_KBC

CAM_FW_WR_EN_EC

PROCHOT_EC

SPI_CS_EC_N0
SPI_CLK_EC
SPI_SI_EC
SPI_SO_EC

KCOL1
KCOL0
KCOL15
KCOL10
KCOL11
KCOL14
KCOL13
KCOL12
KCOL3
KCOL6
KCOL8
KCOL7
KCOL4
KCOL2
KCOL5
KCOL9

KROW3
KROW2
KROW0
KROW5
KROW4
KROW6
KROW7
KROW1

RTC_AUX_S5

GPIO10 :

CAM_FW_WR_EN

3D3V_AUX_S5

1 2

C2411 SC220P50V2KX-3GP

DY

1 2

R2478 0R2-PT5-LILY-GP-U

1 2

R2460 0R2-PT5-LILY-GP-U

1 2

R2485 0R2-PT5-LILY-GP-U

1 2

R2411 0R2-PT5-LILY-GP-U

1 2

R2413 0R2-PT5-LILY-GP-U

1 2

R2400 0R2J-2-GP

1 2

R2415 0R2-PT5-LILY-GP-U

NOTE:
Locate resistors R2415 and R2417 close to the KBC.

NOTE:
Please be aware that the SPI interface trace length between
PCH and EC should not exceed 6500mils,. The mismatch
of SPI interface signals between EC and SPI flash should not exceed 500mils.

KCOL[15:0] 65

DC_BATFULL 64
EC_SLP_LAN# 40

KROW[7:0] 65

CPU_SMB_SCL_THERM

1

CPU_SMB_SDA_THERM

2 3

SRN10KJ-5-GP

CPU_SMB_SCL_THERM 26,70

CPU_SMB_SDA_THERM 26,70

RN2402

4

R2435 0R2J-2-GP
D2403 RB530SM-30T2R-GP-U
R2430 0R2-PT5-LILY-GP-U

R2431 0R2J-2-GP

3D3V_S0

3

1 2

R2441 10KR2J-3-GP

DY

1 2

R2442 10KR2J-3-GP

DY

12

DY

K A
1 2

1 2

DY

PURE_HW_SHUTDOWN#26,40,42

KBC_PWRBTN#64,74,89

3D3V_S0

PM_SLP_M# 17,99

PLTRST#_CPU 17,31,33,40,61,62,63,68,71,89,91
PLTRST#_EC 89

LPC_CLK_KBC 18

LPC_FRAME#_CPU 18,68

LPC_AD_CPU_P3 18,68
LPC_AD_CPU_P2 18,68
LPC_AD_CPU_P1 18,68
LPC_AD_CPU_P0 18,68
LPC_SERIRQ_CPU 18,68

LPC_CLKRUN#_CPU 18

-LED_CAPSLOCK 65
S5_ENABLE 40

EC_SMI# 4
CAM_FW_WR_EN 66
EC_GSENSOR_INT# 70
PM_SLP_LAN# 17

SIO_RCIN# 18

BLON_OUT 55

-RJ45_LINKUP 31,74
USB_AO_SEL 35
IPD_DATA_TPAD 65
IPD_CLK_TPAD 65

BAT_SCL_EC 26,43,44
BAT_SDA_EC 26,43,44

CPU_SMB_SCL_P1 18
CPU_SMB_SDA_P1 18
CPU_I2C_SCL_ISH1_EC 20
CPU_I2C_SDA_ISH1_EC 20
EC_I2C_SCL_PD 56,58,73

EC_I2C_SDA_PD 56,58,73
PM_SLP_S4# 17,40,51,99
ME_FWP_EC 19

SPI_CS_CPU_N0 18,25
SPI_CLK_CPU 18,25,91
SPI_SI_CPU 15,18,25,91

SPI_SO_CPU 18,25,91
USB_PWR_EN2 35
SYS_PWROK 17,56

Nuvoton KBC PSL Power Switched Logic

PSL

R2409
1KR2F-3-GP

1 2

1. Enter PSL mode (Entry S5 after 10sec) :
3D3V_AUX_KBC : OFF (KBC PWR supply)

2. At PSL mode (SPEC: S5<10mW)

PSL Mode (AC or DC)

PSL Wake (AC or DC):

EC_ENABLE#_G S5_ENABLE 3D3V_AUX_KBC

HIGH LOW OFF

RN2405

1
2 3

SRN10KJ-5-GP

3D3V_AUX_S5

12

R2403
10KR2J-3-GP

R2402 470R2J-2-GP

12

G2401

R2439

GAP-OPEN

100KR2J-1-GP

2 1

3D3V_AUX_KBC

SKU_ID

3D3V_AUX_KBC

PCB_ID

<---- Click PAD

<---- BATTERY / CHARGER / Thermal 7718 / P-Sensor
<---- PCH / Thermal 7717 & 7718 /G-sensor
<---- Intel Sensor Hub
<---- PD 65988 / MUX8747*2

SKU_ID (PIN D4)

12

SKUID

R2448
10KR2F-2-GP

12

R2449
100KR2F-L1-GP

12

PCBID

R2418
47KR2F-GP

12

R2419
100KR2F-L1-GP

3D3V_AUX_S5 3D3V_AUX_S53D3V_AUX_KBC

12

PSL

R2494
330KR2J-L-GP

PSL

R2495
20KR2J-L2-GP

1 2

vPro

non-vPro

vPro

non-vPro

vPro

non-vPro

vPro

non-vPro

18729-SA

18729-SB

18729-SC

18729-1

LID_CLOSE#

S5_ENABLE_R
S5_ENABLE
EC_GPIO67

BAT_SCL_EC
BAT_SDA_EC

BAT_IN#_R
ECRST#

CPU_I2C_SDA_ISH1_EC
CPU_I2C_SCL_ISH1_EC

CPU_SMB_SCL_P1
CPU_SMB_SDA_P1

-INTRUDER_EC

EC_ENABLE#_GEC_ENABLE# EC_ENABLE#_G_1

PSL

1 2

C2417 SCD1U6D3V1KX-GP

ONLOW HIGH

NOTE:
EXT_RST# has 110K internal pull-up,
however an additional external pull-up may be
required to meet 60u sec timing requiremen

KBC_PWRBTN_EC#

C2416
SC220P50V2KX-3GP

ECRST#

B

E

Q2401
MMBT3906LT1-1GPU

C

3D3V_AUX_S5

4

PURE_HW_SHUTDOWN#_B

NOTE:
EXT_PURST# has a 110K internal PU to Vcc power plane.
Thus R2403 can be eliminated.

12

12

DY

2

Pull Down (R2449)

100.0KLBB-1

100.0K

100.0K

100.0K

Pull Down (R2419)PCB_ID (PIN D1) Pull High (R2418)

100.0K

100.0K

100.0K

100.0K

100.0K

100.0K

100.0K 100.0K 1.650V

100.0K

1 2

R2412 10KR2J-3-GP

1 2

R2490 100KR2J-1-GP

1 2

R2493 100KR2J-1-GP

1 2

R2499 100KR2J-1-GP

1

4

RN2403 SRN4K7J-8-GP

2 3

12

R2401 100KR2J-1-GP

12

R2408 10KR2J-3-GP

1

4

RN2404 SRN4K7J-8-GP

2 3

1

4

RN2406 SRN2K2J-1-GP

DY

2 3

12

R2498 100KR2J-1-GP

DS

PSL

Q2405
SSM3J327R-GP

G

84.03327.031

S5_ENABLE

DS

PSL

Q2404
LSK3541G1ET2L-GP

G

84.03541.F31

12

DY

C2414

SC1U6D3V1MX-GP

Pull High (R2448)

10.0K

20.0K

33.0K

47.0K

64.9K

76.8K

100.0K 1.650V

143.0K

10.0K 3V

20.0K

33.0K

47.0K

64.9K

76.8K

143.0K 1.358V

3D3V_AUX_S5

3D3V_AUX_KBC

3D3V_AUX_KBC

3D3V_S5

3D3V_S5

3D3V_AUX_KBC

Voltage

3V

LOGIC

2.75V

2.481V

2.245V

2.001V

1.867V

1.358V

Voltage

2.75V

2.481V

2.245V

LOGIC

2.001V

1.867V

Nuvoton KBC NPCE388PB0BX

LPC or eSPI Strapping BIOS Function Selection:

LPC_ESPI_STRAP1
(Pin U2401.N1)

EC_GPIO67 S5_ENABLE_R

LPC_ESPI_STRAP0
(Pin U2401.J6)

LOW

HIGH

1

BB1_EVT_MAIN_W010
BB1_EVT_MAIN_W012
BB1_EVT_MAIN_W014
BB1_EVT_MAIN_W032
BB1_EVT_MAIN_W039

BB1_FVT_MAIN_W004
BB1_FVT_MAIN_W012
BB1_FVT_MAIN_W017
BB1_FVT_MAIN_W020
BB1_FVT_MAIN_W029
BB1_FVT_MAIN_W042

BB1_SIT_MAIN_W003
BB1_SIT_MAIN_W004
BB1_SIT_MAIN_W009
BB1_SIT_MAIN_W017
BB1_SIT_MAIN_W019
BB1_SIT_MAIN_W028
BB1_SIT_MAIN_W029

BB1_SVT_MAIN_W003
BB1_SVT_MAIN_W007
BB1_SVT_MAIN_W008

BB1_FVT_MAIN_L001

BB1_SIT_MAIN_L005

Bus Interface

eSPI

HIGH

LPC

HIGH

LOGIC

A A

LBB-1

LBB-1

LBB-1

Title

Title

Title

ECIO (NUVOTON NPCE388)

ECIO (NUVOTON NPCE388)

ECIO (NUVOTON NPCE388)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A1

A1

A1

Thursday, May 30, 2019

Thursday, May 30, 2019

Thursday, May 30, 2019

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

1

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Bumblebee-1

Bumblebee-1

Bumblebee-1

24 99

24 99

24 99

-1

-1

-1

5

Main Func = SPI Flash

SPI_CS_CPU_N018,24
SPI_CLK_CPU18,24,91
SPI_SI_CPU15,18,24,91
SPI_SO_CPU18,24,91

SPI_WP_CPU15,18

D D

C C

SPI_HOLD_CPU15,18

4

3D3V_SPI3D3V_SPI3D3V_SUS

1 2

R2510 0R0603-PAD-1-GP-U

SPI_CS_CPU_N0
SPI_SO_CPU
SPI_WP_CPU SPI_HOLD_CPU

1 2

R2506 0R2J-2-GP

1 2

R2507 0R2J-2-GP

SPI_SO_ROM
SPI_WP_ROM

3

12

DY

R2519
4K7R2J-2-GP

BIOS1 will use BOM control by co-lay symbol issue

SPI ROM (BIOS1)

BIOS1

1

S#

2

DQ1

3

W#/VPP

4

VSS

LILY-BIOS-COLAY-GP-U

ZZ.00PAD.M41

GND

VCC

HOLD#

DQ0

SPI ROM Socket (SSKT1)

SPI_CS_CPU_N0
SPI_SO_ROM
SPI_WP_ROM

SSKT1

1

8

2

7
3 6
4

5

SKT-50960-0084L-001-GP

62.10076.051

Co-Layout Design on BIOS1

SPI socket mount in SA stage

9
8
7
6

C

5

SPI_HOLD_ROM
SPI_CLK_ROM
SPI_SI_ROM

2

3D3V_SPI

SPI_HOLD_ROM
SPI_CLK_ROM
SPI_SI_ROM

1 2

R2503 0R2J-2-GP

1 2

R2508 0R2J-2-GP

1 2

R2509 0R2J-2-GP

208MIL SOIC8 (BIOS1) WSON8 / SOP8:

MX25L25673GM2I-08G
GD25B256DYIGR
MT25QL256ABA1EW9-0SIT

12

C2502

SCD1U6D3V1KX-GP

3D3V_SPI

MACRONIX
GIGADEVICE
MICRON

3D3V_SPI

SPI_CLK_CPU
SPI_SI_CPU

BB1_EVT_MAIN_W032
BB1_EVT_MAIN_W039
BB1_EVT_MAIN_W043

BB1_FVT_MAIN_W011
BB1_FVT_MAIN_W017
BB1_FVT_MAIN_W020

BB1_SVT_MAIN_W008
BB1_SVT_MAIN_W011
BB1_SVT_MAIN_W012

32MB (256Mb)
non-vPro

072.25256.0N01 072.25256.0S01 (WSON8)W25Q256JVEIQWINBOND(WINBOND had load code issue)

072.25673.0001

072.25256.0B03

072.25256.0E03

1

BB1_SVT_MAIN_L001

32MB (256Mb)
vPro

072.25673.0C01

072.25256.0C03

072.25256.0D03

(SOP8)
(WSON8)
(WPDFN8)

SOP 8 package only

Main Func = RTC

3D3V_AUX_S5

1
1

12

R2514
100R2J-2-GP

3D3V_AUX_R

12

DY

R2515
33K2R2F-GP

R2501
1KR2J-1-GP

1 2

4

RTCVCC_D

RTCVCC_CONN

D2502
RB530SM-30T2R-GP-U

KA

D2501
RB530SM-30T2R-GP-U

KA

RTC_AUX_S5

12

DY

C2504
SC1U6D3V1MX-GP

RN2501

1
2 3

4

SRN20KJ-1-GP

RTC_RST# RTC_RST#
SRTC_RST# SRTC_RST#

12

C2501
SC1U10V2KX-1GP

8
3
1

2
4
5

3

12

ED2501

DY

10
9
7
6

AZ1043-04F-R7G-GP

C2503
SC1U10V2KX-1GP

Test High

R2511
10KR2J-L-GP

1 2

SRTC_RST#

Q2503

DS

21

G2501
GAP-OPEN

(#514849)
Layout: Place at the open door area.

LSK3541G1ET2L-GP

G

2

3D3V_S0

12

R2520
10KR2J-3-GP

RTC_RST#18,99
SRTC_RST#18

RTC_DET#20

RTC_TEST19

RTCRST_ON24

B B

RTC CONN

RTC1

ACES-CON2-20-GP-U

20.F1639.002

3
1

2
4

RTCVCC_CONN

Near RTC CONN (RTC1)

AFTP2501
AFTP2502

A A

5

RTCVCC_D

5V_S0

12

G

Q2501
LSK3541G1ET2L-GP

LBB-1

LBB-1

LBB-1

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A3

A3

A3
Date: Sheet of

Date: Sheet of

Date: Sheet of

R2512
100KR2J-1-GP

DS

RTC_RST#

RTCRST_ON

FLASH/RTC

FLASH/RTC

FLASH/RTC

Thursday, May 30, 2019

Thursday, May 30, 2019

Thursday, May 30, 2019

Q2502
LSK3541G1ET2L-GP

D S

RTC_DET#_GRTC_TEST

Bumblebee-1

Bumblebee-1

Bumblebee-1

Detect Low

RTC_DET#

G

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

R2513
100KR2J-1-GP

1 2

25 99

25 99

25 99

-1

-1

-1

Main Func = Thermal Sensor

5

Thermal Sensor

TABLE:

Sensor Target

U2603

DIMM

U2604

Charger

U2601

SSD

Q2603

D D

Ch2

Ch1

C C

B B

CPU DCDC

Q2605

FAN

Close to CPU DCDC

C

TMBT3904-GP

E

Q2603

B

12

C2602

SC100P50V2JN-3GP

Close to FAN

1 2
1 2
1 2
1 2

PURE_HW _SHUTDO WN#24,40,42

DY
DY
DY
DY
DY

75
90
100
105
110

12

C2608

SC100P50V2JN-3GP

12
12

R2627 \ R2639
R2635 \ R2640R2641

2.0K

7.5K

10.5K

14.0K

18.7K

THERM_SYS_SHD N#
NTC7717_ALER T#
NTC7718_CR IT#
NTC7718_2_CR IT#
NTC7718_ALER T#
NTC7718_2_ALER T#

2.0K 7.5K

77
79
81
83
85

C

B

TMBT3904-GP

E

Q2605

3D3V_S0

R2637 10KR2J-3-GP
R2641 14KR2F-GP
R2639 10K5R2F-GP
R2640 10K5R2F-GP
R2627 18K7R2F-GP
R2635 18K7R2F-GP

ALERT# /T_CRIT# Pull-up Resistor v.s. Alert temperature ( )

NCT7717U Table: NCT7718W Table:

2.0K

7.5K

10.5K

14.0K

18.7K

THERM_SYS_SHD N# NTC7718_CR IT#

12

SC2K2P50V2KX-L-GP

12

SC2K2P50V2KX-L-GP

THERM_DA2

C2613

THERM_DC 2

THERM_DA1

C2606

THERM_DC 1

Software Control

Hardware Control

℃

10.5K 14.0K

18.7K

87

97

107
99
101
103
105

SCD1U6D3V1KX-GP

109

111

113

115

D S

12

DY

C2607

117
119
121
123
125

G

Q2604
LSK3541G1ET2L-GP

THERM_SYS_SHD N#

IMVP_PWRGD _THERMAL

89
91
93
95

12

DY

R2610

10KR2J-L-GP

THERM_SYS_SHD N# NTC7718_2_CR IT#

R2608 10KR2J-3-GP

1 2

4

D2605
RB530SM-30T2R -GP-U

DY

C2615
SC1U6D3V1MX- GP

1 2

C2616
SCD1U6D3V1 KX-GP

1 2

D2606
RB530SM-30T2R -GP-U

DY

3D3V_S0

KA

KA

3D3V_S0

12

3D3V_S0

12

R2629
0R0402-PAD-1- GP

3D3V_S0_NTC7 718
THERM_DC 2

R2631
0R0402-PAD-1- GP

NTC7717_SDA_ THERM

3D3V_S0

12

R2634
0R0402-PAD-1- GP

3D3V_S0_NTC7 718_2
THERM_DC 1

12

C2614

SCD1U6D3V1KX-GP

3D3V_S0_NTC7 717

12

C2617

SCD1U6D3V1KX-GP

Close to DIMM

U2603

1

VDD

2

D+

3

D­T_CRIT#4GND

74.07718.0B9

Close to Charger

U2604

5

SDA

4

VDD

74.07717.0BF

Close to SSD Bottom side

U2601

1

VDD

2

D+

3

D­T_CRIT#4GND

74.07718.0B9

ALERT#

NCT7718W -GP

ALERT#

NCT7717U-1- GP

ALERT#

NCT7718W -GP

8

SCL

7

SDA

6
5

1

SCL

2

GND

3

8

SCL

7

SDA

6
5

3

NTC7718_SCL_T HERM
NTC7718_SDA_ THERMTHERM_DA2
NTC7718_ALER T#

NTC7717_SDA_ THERM CPU_SMB_SDA_THERM
NTC7717_SCL_T HERM

NTC7717_ALER T# THERM_SYS_SHD N#

NTC7718_2_ALER T#

1 2

R2628 0R2-PT5-LILY-GP-U

1 2

R2626 0R2-PT5-LILY-GP-U

1 2

R2624 0R2-PT5-LILY-GP-U

1 2

R2625 0R2-PT5-LILY-GP-U

D2601
RB530SM-30T2R -GP-U

K A

DY

3D3V_S0

1

23

RN2601
SRN2K2J-5-G P

4

1 2

R2636 0R2-PT5-LILY-GP-U

1 2

R2633 0R2-PT5-LILY-GP-U

CPU_SMB_SCL_ THERM

BAT_SMB_SCL_P1NTC 7718_2_SCL_THER M
BAT_SMB_SDA_P1NTC7718_2_SDA _THERMTHERM_D A1

2

CPU_SMB_SCL_ THERM 24,7 0
CPU_SMB_SDA _THERM 24 ,70

THERM_TAC H2 4

FAN_PWM24

FAN_ID20

BAT_SMB_SCL_P166

BAT_SDA_EC24,43,44

3D3V_S0

4

RN2604
SRN10KJ-5-G P

1

2 3

D2602 RB551VM-30TE-1 7-GP

1 2

R2614 0R2-PT5-LILY-GP-U

3D3V_S0

6

2N7002KDW -1-GP

75.27002.F7C

KA

Q2607

Note:ZZ.27002.F7C01

1

BB1_EVT_MAIN_W001
BB1_EVT_MAIN_W032
BB1_EVT_MAIN_W050

BB1_FVT_MAIN_W007
BB1_FVT_MAIN_W008
BB1_FVT_MAIN_W017
BB1_FVT_MAIN_W041

BB1_SIT_MAIN_W010
BB1_SIT_MAIN_W022

BB1_SVT_MAIN_W006
BB1_SVT_MAIN_W008

5V_S0

12

DY

C2612

SC4D7U6D3V3KX-GP

12

DY

EC2601

SC1KP50V2KX-1GP

AFTP2601
AFTP2602
AFTP2603
AFTP2604
AFTP2605

3D3V_S0

2345
1

BAT_SCL_EC 24,43,44

BAT_SMB_SDA_P1 66

12

12

R2606
10KR2J-L-GP

F2601

POLYSW-1D1A6V-6-GP

FAN_PWM _C

12

FC2602

SC100P50V2JN-3GP

1
1
1
1
1

5V_S0_FAN

FAN_TACH

FAN_PWM _C
FAN_TACH
5V_S0_FAN
FAN_ID

FAN CONN

FAN1

7
1
2

3
4
5
6

8

ACES-CON 6-20-GP-U

20.F1639.006

PURE_HW_SHUTDOWN# logic table

signal name
RT_COMP_OUT
PURE_HW_SHUTDOWN#

TABLE:

ID

Target Function

RT2601

PU5101 1D2V_S3

RT2602

PU4801
PQ5201
PU4701
PQ4505
PQ4506
PU4404
PU4406

1V_VCCGT
1D05V_SUS
1V_CPU_CORE
5V_S5
3D3V_S5
Charger-Buck
Charger-Boost

5

RT2603
RT2604
RT2605
RT2606

A A

RT2607
RT2608

12

RT2602

PTC-540-2-GP

RT_6

12

RT2601

PTC-540-2-GP

12

RT2604

PTC-540-2-GP

RT_5

RT_4

12

RT2603

PTC-540-2-GP

12

RT2606

PTC-540-2-GP

RT_2

RT_3

12

RT2605

PTC-540-2-GP

12

RT2607

PTC-540-2-GP

RT_1

RT_0

12

RT2608

PTC-540-2-GP

4

5V_S5

12

R2617

6K81R2F-1-GP

12

C2611

SCD1U6D3V1KX-GP

5V *100K/(100K+40K) = 3.57V

5V_S5

R2616
40K2R2F-GP

1 2

R2618
100KR2F-L1-GP

1 2

3

RT_COMP+
RT_COMP-

5V_S5

52

1

+

3

-

SCD1U6D3V1KX-GP

4

U2602
LMV331IDCKRG4-G P

74.00331.A2F

3D3V_AUX_S5 3D3V_S5

12

C2610

RT_COMP_OU T RT_COMP_OU T_R PURE_H W_SHU TDOWN #

12

R2613
100KR2J-1-GP

R2615
0R2-PT5-LILY-GP-U

1 2

Sys. Temp < Ref. Temp

High
High

2

Sys. Temp > Ref. Temp

Low
Low

G

Q2606
LSK3541G1ET2L-GP

DS

LBB-1

LBB-1

LBB-1

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
Taipei Hsie n 221, Taiwan, R.O. C.

Taipei Hsie n 221, Taiwan, R.O. C.

Title

Title

Title

INT IO (THERMAL/FAN)

INT IO (THERMAL/FAN)

INT IO (THERMAL/FAN)

Size Document Num ber Rev

Size Document Num ber Rev

Size Document Num ber Rev
A2

A2

A2

Thursday, May 30, 2019

Thursday, May 30, 2019

Thursday, May 30, 2019

Date: Sheet of

Date: Sheet of

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O. C.

Bumblebee-1

Bumblebee-1

Bumblebee-1

1

26 99

26 99

26 99

-1

-1

-1

5

3D3V_SUS

12

R2720

D D

5V_S0

R2704
0R0603-PAD-1- GP-U

1 2

12

C2708

SC10U6D3V3MX-GP

Nearby CODEC

C C

SENSE_A_SYS_HP30

SENSE A: Pin 9 200K : HP Detect
SENSE B: Pin 8 200K : Dock Mic Detect
100K : Dock HP Detect

B B

R2710 200KR2F-L-GP

5V_S0 5V_S0_A UDIO

12

12

DY

C2728

SC10U6D3V3MX-GP

SCD1U6D3V1KX-GP

0R0603-PAD-1-GP-U

12

12

C2701

SC10U6D3V3MX-GP

SCD1U6D3V1KX-GP

AGND

Nearby CODEC

12

12

12

C2709

SCD1U6D3V1KX-GP

1 2

1 2

R2714 0R0603-PAD-1- GP-U

DY

C2729

C2732
SCD01U50V2KX- 1GP

1 2

DY

C2711

C2710

SC10U6D3V3MX-GP

SCD1U6D3V1KX-GP

3D3V_S0

12

12

SCD1U6D3V1KX-GP

C2702

HDA_SYNC_C ODEC19

HDA_BITCLK_C ODEC19
HDA_SDOU T_CODEC1 9

HDA_SDIN0_CP U19

R2709
100KR2F-L3-GP

DMIC_SDA_COD EC66

DMIC_SCL_COD EC66

C2730

SC4D7U6D3V3KX-GP

AGND

SPK_MUTE#24

12

C2731

Near U2701

12

DY

R2745
0R3J-0-U-G P

12

12

C2704

C2703

SC10U6D3V3MX-GP

SCD1U6D3V1KX-GP

1 2

ER2707 0R2-PT5-LILY-GP-U

12

EMC

SC33P50V2JN-3GP

12

SC33P50V2JN-3GP

DY

EC2714

DY

C2724

12

R2702
0R3J-0-U-G P

4

12

C2705

SC10U6D3V3MX-GP

SCD1U6D3V1KX-GP

3D3V_S0

12

DY

C2715

3D3V_S0

SC33P50V2JN-3GP

12

DY

C2725

SC33P50V2JN-3GP

3D3V_S03D3V_S01D8V_SUS 5V_S0_AUDIO

5V_S0

12

12

R2703

R2717

0R0402-PAD-1-GP

0R0603-PAD-1-GP-U

12

C2706

DY

1 2

1 2

12
12

12

R2708 33R2J-2-GP
R2746 10KR2J-3-GP

R2718 100KR2J-1-GP

R2711 33R2J-2-GP

R2712 0R0603-PAD-1- GP-U

PCBeep

KBC_BEEP24

HDA_SPKR15,19

3D3V_S0_DVDD _AUD
3D3V_S0_DVDD -IO_AUD

1D8V_SUS_AVD D2_AUD

5V_S0_PVDD2_AU D
5V_S0_AUDIO_R

HDA_BCLK_A
HDA_SDIN0_CO DEC

HDA_EAPD

SENSE_A
3D3V_S0_MIC2

DMIC_SCL_COD EC_R

SPK_MUTE#_AU D

C2727 SCD01U50V2 KX-1GP

U2701

3

DVDD

Analog Plane

18

DVDD-IO

40

AVDD1

20

CPVDD/AVDD2

41

PVDD1

46

PVDD2

Analog Plane Speaker 4 ohm ==> 40 mils

33

5VSTB

6

I2C-DATA

Analog Plane

7

I2C-CLK

15

AUDIOLINK_SYNC

14

AUDIOLINK_BCLK

17

AUDIOLINK_SDATA-OUT

16

AUDIOLINK_SDATA-IN

13

DC-DET/EAPD

8

NC#8

Analog Plane

9

NC#9

10

NC#10

11

NC#11

12

NC#12

48

HP/LINE2-JD(JD1)

47

MIC2/FROUT-JD(JD2)

4

GPIO0/DMIC-DATA12

5

GPIO1/DMIC-CLK

1

DMIC-CLK-IN/SPDIF-OUT/GPIO2/DM IC-DATA34

2

PDB

PLACE UNDER CODEC (ALC3287)

DY

1 2

D2703

2

BEEP_MIX_ATT_D

3

1

BAT54C-11-GP

12

R2716
10KR2J-3-GP

12

R2715
10KR2J-3-GP

3

34

PCBEEP

SPK-OUT-L+

SPK-OUT-L-

SPK-OUT-R+

SPK-OUT-R-

VREF

LDO1-CAP
LDO2-CAP
LDO3-CAP

MIC2-VREFO-L

MIC2-VREFO-R

MIC2-CAP

CPVEE

AVSS1
AVSS2

PVSS

ALC3287-CG-G P

30
31

36
35

42
43
45
44

27
26

38
39

21
19

28
29

32
25
23

CBP

24

CBN

37
22

49

AGNDAGND

MIC2-L(PORT-F-L)/RING2

MIC2-R(PORT-F-R)/SLEEVE

LINE2-L(PORT-E-L)

LINE2-R(PORT-E-R)

HPOUT-L(PORT-I-L)

HPOUT-R(PORT-I-R)

1 2

R2713 0R0402-PAD-1- GP

BEEP_MIX_ATT_R

BEEP_MIX_ATT_C

HP_L_JACK_AU D
HP_R_JACK_A UD

VREF_AUD

LDO1-CAP_AU D
LDO2-CAP_AU D
LDO3-CAP_AU D

MIC-CAP_AUD
CPVEE_AUD
CBN1_AUD

CBP1_AUD

R2744
0R2-PT5-LILY-GP-U

1 2

PCB trace width of Mic1-R/Mic1-L(SLEEVE/RING2) are
required at least 40 mil for HP crosstalk consideration
and its length should be as short as possible

1 2

C2733 SCD1U 6D3V1KX-GP

CODEC_SP_O UTL+ 29
CODEC_SP_O UTL- 29
CODEC_SP_O UTR+ 29
CODEC_SP_O UTR- 29

1 2

C2712 SC 2D2U10V3KX- 1GP

1 2

C2713 SC 2D2U10V3KX- 1GP

1 2

C2716 SC 2D2U10V3KX- 1GP

MIC1_VREFOL 28
MIC1_VREFOR 2 8

C2717

1 2

SC2D2U10V3KX- 1GP

12

C2718

SC2D2U10V3KX-1GP

AGND

BEEP_MIX_ATT

2

R2705 43R2J-L-GP
R2706 43R2J-L-GP

AGND

12

12

C2719

SC2D2U10V3KX-1GP

AGND AGND AGNDAGND AGND

12

DY

C2726

C2734

SC2D2U10V3KX-1GP

SC33P50V2JN-3GP

AGND

Nearby CODEC

Nearby C2712/C2713/EC2903

For Audio no sound CDE solution

BEEP_MIX_ATT

1 2
1 2

12

DY

C2735

SC33P50V2JN-3GP

1 2

ER2701 0R0402-PAD-1-GP

1 2

ER2702 0R0402-PAD-1-GP

12

SC33P50V2JN-3GP

Speaker 8 ohm ==> 20 mils

12

DY

DY

C2737

C2736

SC33P50V2JN-3GP

AGND

RING2 28

SLEEVE 28

HP_L_JACK 30

HP_R_JACK 30

1

BB1_EVT_MAIN_W010
BB1_EVT_MAIN_W032

BB1_FVT_MAIN_W017

BB1_SIT_MAIN_W032

BB1_SVT_MAIN_W008

DS

Q2701
LSK3541G1ET2L-GP

BEEP_ENABLE#24

A A

5

4

12

R2723
100KR2J-1-GP

G

LBB-1

LBB-1

LBB-1

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
Taipei Hsie n 221, Taiwan, R.O. C.

Taipei Hsie n 221, Taiwan, R.O. C.

Title

Title

Title

AUDIO (CODEC ALC3287)

AUDIO (CODEC ALC3287)

AUDIO (CODEC ALC3287)

Size Document Numb er Rev

Size Document Numb er Rev

Size Document Numb er Rev
Custom

Custom

Custom

Thursday, May 30, 2019

Thursday, May 30, 2019

Thursday, May 30, 2019

Date: Sheet of

Date: Sheet of

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O. C.

Bumblebee-1

Bumblebee-1

Bumblebee-1

1

27 99

27 99

27 99

-1

-1

-1

5

MIC1_VREFOR27

D D

MIC1_VREFOL27

C C

PCB trace width of Mic1-R/Mic1-L(SLEEVE/RING2) are
required at least 40 mil for HP crosstalk consideration
and its length should be as short as possible

MIC_SLEEVE30

SC1U6D3V1MX-GP

AGND

SC1U6D3V1MX-GP

AGND

12

12

4

DY

C2801

DY

C2802

12

R2802
2K2R2F-GP

LINE1_VREFO_1

12

R2803
2K2R2F-GP

LINE1_VREFO_2

12

DY

R2806
0R2J-2-GP

3

NEAR EXT MIC CONN

1 2

R2801 0R2-PT5-LILY-GP-U

1 2

R2804 0R2-PT5-LILY-GP-U

1 2

R2805 0R0805-PAD-1-GP-U

12

C2803

SC1KP50V2KX-1GP

2

BB1_EVT_MAIN_W032

BB1_SIT_MAIN_W032

BB1_SVT_MAIN_W008

SLEEVE 27

1

AGND

1 2

MIC_RING230

12

DY

B B

A A

PCB trace width of Mic1-R/Mic1-L(SLEEVE/RING2) are
required at least 40 mil for HP crosstalk consideration
and its length should be as short as possible

1 2

ER2809 0R0402-PAD-1-GP

AGND

1 2

C2805 SC2D2U10V3KX-1GP

AGND

5

4

R2808
0R2J-2-GP

AGND

R2807 0R0805-PAD-1-GP-U

12

C2804

SC1KP50V2KX-1GP

3

LBB-1

LBB-1

LBB-1

Title

Title

Title

AUDIO (MIC I/F)

AUDIO (MIC I/F)

AUDIO (MIC I/F)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A4

A4

A4

Thursday, May 30, 2019

Thursday, May 30, 2019

Thursday, May 30, 2019

Date: Sheet of

Date: Sheet of

Date: Sheet of

2

RING2 27

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Bumblebee-1

Bumblebee-1

Bumblebee-1

28 99

28 99

28 99

1

-1

-1

-1

5

4

3

2

1

Main Func = AUDIO

D D

BB1_SIT_MAIN_W025

BB1_SVT_MAIN_W008

SPEAKER CONN

SPK1

5

1 2

CODEC_SP_OUTL+27

C C

B B

CODEC_SP_OUTL-27
CODEC_SP_OUTR+27
CODEC_SP_OUTR-27

R2901 0R0603-PAD-1-GP-U

1 2

R2902 0R0603-PAD-1-GP-U

1 2

R2903 0R0603-PAD-1-GP-U

1 2

R2904 0R0603-PAD-1-GP-U

1 2

SC1KP50V2KX-1GP

PLACE NEAR SPEAKER CONNECTOR

To solve SPK EMI failed issue

EC2902

SC1KP50V2KX-1GP

1 2

EC2901

EC2904

1 2

SC1KP50V2KX-1GP

CODEC_SP_OUTL+_C
CODEC_SP_OUTL-_C

CODEC_SP_OUTR+_C
CODEC_SP_OUTR-_C

EC2903

1 2

SC1KP50V2KX-1GP

1
2

3
4

6

ACES-CON4-67-GP-U

020.F0220.0004

Near SPK1 (SPEAKER)

AFTP2901
AFTP2902
AFTP2903
AFTP2904

1
1
1
1

CODEC_SP_OUTL+_C
CODEC_SP_OUTL-_C
CODEC_SP_OUTR+_C
CODEC_SP_OUTR-_C

LBB-1

LBB-1

LBB-1

Wistron Corporation

Wistron Corporation

A A

Title

Title

Title

AUDIO (SPEAKER)

AUDIO (SPEAKER)

AUDIO (SPEAKER)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A4

A4

A4

Thursday, May 30, 2019

Thursday, May 30, 2019

Thursday, May 30, 2019

Date: Sheet of

Date: Sheet of

5

4

3

Date: Sheet of

2

Bumblebee-1

Bumblebee-1

Bumblebee-1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

-1

-1

29 99

29 99

29 99

1

-1

5

D D

4

1 2

HP_L_JACK27

HP_R_JACK27

R3007 0R2-PT5-LILY-GP-U

1 2

R3008 0R2-PT5-LILY-GP-U

DY

C3002

12

SC100P50V2JN-L-GP

3

DY

C3003

12

SC100P50V2JN-L-GP

2

BB1_EVT_MAIN_W006

BB1_FVT_MAIN_W034

BB1_SIT_MAIN_W021
BB1_SIT_MAIN_W032

BB1_SVT_MAIN_W008

1

Moat

3D3V_S0

12

R3001
10KR2J-3-GP

Combo Jack

C C

AUD1

Audio(IP/NK comb)

AUDIO-JK687-GP

ZZ.00SKT.022

AUD1 will use BOM control to 022.10002.01H1

Near AUD1 (AUDIO)

AFTP3001
AFTP3002
AFTP3003
AFTP3004
AFTP3005

B B

AFTP3006
AFTP3007

3
1

5
6
2
4
MS

1
1
1
1
1
1
1

MIC_RING2
HP_L_JACK_CONN

3D3V_S0_HPJD
HP_JACK_SYS
HP_R_JACK_CONN
MIC_SLEEVE

AGND

MIC_RING2
HP_L_JACK_CONN
3D3V_S0_HPJD
HP_JACK_SYS
HP_R_JACK_CONN
MIC_SLEEVE

AGND

NEAR AUDIO JACK CONN

AUDIO JACK SENSE

CLOSE TO CODEC

6-10 mil trace recommend

MIC_RING2
HP_L_JACK_CONN

HP_JACK_SYS
HP_R_JACK_CONN
MIC_SLEEVE

R3005 0R2-PT5-LILY-GP-U

2

1

EMC

ED3001
AZ5125-02S-R7G-GP

75.05125.07D

3

Close to AUD1

1 2

1 2

R3006 0R0402-PAD-1-GP

HGNDA/HGNDB trace width >70mil,
changed to sharp will be better.

MIC_RING2 28

HP_JACK_IN 24

MIC_SLEEVE 28

2

12

SC1KP50V2KX-1GP

EC3006

12

DY

EC3007

SC1KP50V2KX-1GP

1

EMC

ED3002
AZ5125-02S-R7G-GP

75.05125.07D

3

Close to AUD1 Close to AUD1

2

1

EMC

ED3003
AZ5125-02S-R7G-GP

75.05125.07D

3

AGND

DY

1 2

EC3005 SCD1U16V2KX-3GP

AGND

Moat

Moat

AUDIO JACK SENSE

SENSE_A_SYS_HP 27

R3002

12

R3010
100KR2J-1-GP

4

22KR2J-GP

1 2

HP_JACK_SYS

A A

5

HP_JACK_SYS_R

C3001
SC2D2U10V3KX-1GP

1 2

AGND AGND

DS

Q3001

G

LSK3541G1ET2L-GP

3

LBB-1

LBB-1

LBB-1

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

AUDIO (AUDIO JACK)

AUDIO (AUDIO JACK)

AUDIO (AUDIO JACK)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A3

A3

A3

Thursday, May 30, 2019

Thursday, May 30, 2019

Thursday, May 30, 2019

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Bumblebee-1

Bumblebee-1

Bumblebee-1

1

30 99

30 99

30 99

-1

-1

-1