Lenovo ThinkPad L490 Schematic

A

1 1

B

C

D

E

LCFC FL490/FL590 NM-B931

2 2

Solo/Lando 2.0

NM-XXXX Rev 1.0 Schematic

3 3

4 4

A

Intel Whiskey Processor with DDR4 + PCH

AMD R18M-M2-60

2018-09-26 Rev 0.3

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

C

2015/01/12

2015/01/12

2015/01/12

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2016/01/12

2016/01/12

2016/01/12

D

Title

Title

Title

COVER PAGE

COVER PAGE

COVER PAGE

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

FL490/FL590 NM-B931

FL490/FL590 NM-B931

FL490/FL590 NM-B931

Wednesday, March 13, 2019

Wednesday, March 13, 2019

Wednesday, March 13, 2019

Date: Sheet

Date: Sheet

Date: Sheet of

E

of

of

1 99

1 99

1 99

0.3

0.3

0.3

5

4

3

2

1

LCD
14" FHD IPS/HD
15" FHD IPS/HD

HDMI

D D

C C

B B

USB Type-C Re ar Port

USB Type-C Fr ont Port

USB 2.0 System Port(AOU)

USB 2.0 System Port(on SUB/B)

USB 2.0 TYPE-C(Rear Side)

USB 2.0 TYP E-C(Front Side)

Smart Card

BT

RGB Camera

Fingerprint Reader

WWAN

Touch Panel

USB 2.0 Port 1

USB 3.0 Port 1

Microphone
Headphone

Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9

Audio Sub Board

Stereo
Speaker

Embedded Display Port(1.4supported)

PS833 7

PS8747

PS8812

TPS65988

GBE

USB 3.0 TYP E-C(Front Side)
USB 3.0 TYPE-C(Rear Side)
USB 3.0 System Port(AOU)

USB 3.0 System Port(on SUB/B)

HDA CODEC
ALC3287

HDA

DDI 1.2a Port 1HDMI 1.4b

DDI 1.2a Port 2

TI

USB 2.0x10 ports

USB 3.0x4 ports

Port 0
Port 1
Port 2
Port 3

49

Internal
Mic

SPIFlash

1MB

I2C0 NFC

RTC Ba ttery

FAN

I2C-BAT/BC

LED LOGO/CHG

I2C0_NFC

PECI 3.0

G-Sensor
T-Sensor

PWRSW

CPU

Intel

Whiskey Lake

Embedded
Controll er

IT8227

PS2

DRV/SENSE

SM Bus

DDR4

2133-2400M HZ

PECI 3.0

SM Bus

PCI Express Max 6 ports

SPI

SPI Flash
32MB

TPM 2.0

LPC Bus
24MH z

8K EEPROM

DDR4 SO-DIMM
4GB,8GB,16GB,32GB (max)

SM Bus_B

Port 13
(Gen.3)

Keyboard

Track Point

WLAN

Type-A M.2 Card

Port 12

USB 2.0

(Gen.3)

Port 14
(Gen.3)

Media
Card
Controller
RTS5232 S

Micro SD
Card Slot

Intel
GbE PHY
JACKSONVILLE
ULT

VINT20 from USB Type-C Rear Port

RJ 45 Docking

RJ 45

Solo/Lando2 Block Diagram

Project Code: L490&L590

Wireless WAN
Antenna

(M.2 WWAN Card)

Type-B M.2 Card

USBSW1
Port 2

Micro SIM
Card Slot

Port 9

M.2 Sub Card

M.2 SSD

I2C-BAT

Battery

DC/DC
Converte r

I2C-CHARGE

Port 16
Gen 3

SATA
Port 11

2.5" SATA
HDD

Battery
Charger

GPU

(AMD R18M-

M2-60)

Port 5
Gen.3

GDDR5 2GB

ClickPadNFC

External C onnector/Socket

Internal Connector/Socket

Internal Switch

3

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZEDBY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZEDBY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZEDBY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2018/01/12

2018/01/12

2018/01/12

4

Camera(USB2.0 Port 7)
Internal Mic

PWRSW

LED

USB2.0 Port 10

RGB + IR Camera(Optional)

Touch FPR

USB 2.0
Port 8

Non Camera Sub card

Power SW Sub card

A A

Touch Panel(Optional)

5

ThinkPad Logo LED

Difference with Solo/Lando-1.0

Title

Title

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2018/01/12

2018/01/12

2018/01/12

Title

BLOCK DIAGRAM

BLOCK DIAGRAM

BLOCK DIAGRAM

Size

Size

Size

Document Number Rev

Document Number Rev

Document Number Rev

Custom

Custom

Custom

Wednesday, March 13, 2019

Wednesday, March 13, 2019

Wednesday, March 13, 2019

Date: Sheet

Date: Sheet

Date: Sheet of

1

of

of

2 99

2 99

2 99

0.3

0.3

0.3

A

B

C

D

E

HIGH

LOWLOWLOW

+3VS

X

V

SIGNAL

HIGHHIGHHIGH

HIGH

HIGH

Thermal
Sensor

XV

X XXX X XX X

V

X

V

+3VS

USB2.0 Port

1
2
3
4
5
6
7
8
9
10

ONONON

ON

ON

OFF

OFF

OFF

PCH

V

+3VALW_PC H

V

+3VALW_PC H

V

+3VALW_PC H

+3VALW_PC H

ON OFF

ON

ON

CP

Module

XXX

XX

V

+3VS

ON

OFF

OFFLOW LO W LOW LOW

LAN PHY

X

X

X

+3VALW

Devic ePort

USB Port1 ( AOU)
USB Port2 (SUB/B)
USB Port3 (TYPE-C)
USB Port4(TYPE- C_CS18 DOCK)
SMART Ca rd
BT
RGB USB CAMERA
Finger Printer
WWAN
Touch panel

SYSON

HIGH

HIGH

HIGH

LOW

LOW

G-Sensor

X

V

+3VS

X

X

V

+3VS

EC

V

+3VL_EC

V

VCC3_LDO_P D

V

+3VS

X

X

V

+3VS

O --> Means ON

+1.2V

+0.6VS

+VCC_ST

OO

X

X

X --> Means OFF

+5VS

+3VS

+VCC_CORE

+VCC_GT

+VCC_SA

+VCC_IO

+VCC_STG

+VGA_CORE

+1.5VS

+0.95VS_VG A

+1.5VS_VG A

+1.8VS_VG A

+3VS_VGA

X

X

X

X

Voltage Rails

1 1

2 2

3 3

4 4

Power Plane

State

S0

S3

S5 S4/AC Only

S5 S4

Battery only

S5 S4
AC & Battery
don't exist

+1.05VALW

+3VALW

B+

+1.8VALW

+5VALW

O

O

O

O

X X

O O O

O

X X

STATE

Full ON

S1 (Power on)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SMBUS Control Table

EC_SMB_DA 1

EC_SMB_CK 2

EC_SMB_DA 2

EC_SMB_CK 3

EC_SMB_DA 3

PCH_SMB_CL K
PCH_SMB_DA TA

PCH_SML0_C LK
PCH_SML0_DA TA

PCH_SML1_C LK
PCH_SML1_DA TA

HSIO Port

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

SLP_A# SLP_S3# SLP_S4# SLP_S5# EC_ON2 EC_ON SUSP#

HIGH HI GH HI GH HI GH

HIGH

LOW LO W

SOURCE

+3VL_EC

VCC3_LDO_P D

+3VALW_PC H

+3VALW_PC H

+3VALW_PC H

Main

BATT SODIMM

VGA

IT8227EC_SMB_CK 1

IT8227

IT8227

+3VS

PCH

X

+3VL_EC

V

+3VS_VGA +3VS

X X

PCH

X X X X X V

PCH

X V

X X X X

Devic ePort

TYPE-C(Front Side)
TYPE-C(Rear Side)
Syetem Port(AOU)
System Port on S UB/B
PCIE (GP U)
PCIE (GP U)
PCIE (GP U)
PCIE (GP U)
NVMe SSD
NVMe SSD

2.5" SATA HDD
PCIE (WLAN)
Card Reader
LAN
M.2 (PCI E)
M.2 (SAT A)

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

C

2015/01/12

2015/01/12

2015/01/12

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2016/01/12

2016/01/12

2016/01/12

D

Title

SYSTEM LIST

SYSTEM LIST

SYSTEM LIST

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

FL490/FL590 NM-B931

FL490/FL590 NM-B931

FL490/FL590 NM-B931

Wednesday, March 13, 2019

Wednesday, March 13, 2019

Wednesday, March 13, 2019

Date: Sheet

Date: Sheet

Date: Sheet of

E

of

of

3 99

3 99

3 99

0.3

0.3

0.3

5

4

3

2

1

BOM Structure Table

BOM Structure

D D

PCH_SMB_CLK
PCH_SM B_DATA

PCH

PCH_SML0_CLK
PCH_SM L0_DATA

PCH_SML1_CLK
PCH_SM L1_DATA

C C

B B

EC
IT8227

EC_SMB_CK3
EC_SMB_DA3

EC_SMB_CK2
EC_SMB_DA2

EC_SMB_CK1
EC_SMB_DA1

+3VALW

R0951
10k

+3VALW

R0907, R0908
499

+3VALW

R0951
10k

VCC3_LDO_PD

R4505, R4506

3.3k

+3VL_EC

R4019, R4020

2.2k

Level Shift

Level Shift

+3VS

R0920, R0921

4.7k

LAN

+3VS

R4022, R4023

2.2k

Level Shift GPU

PD Controller

Charger

Battery

+3VS_VGA

R32102, R32103
47k

DIMM1

DIMM2

Click Pad

G-Sensor

Thermal Sensor

PCB@ For PCB load BOM

3G@

DIS@

UMA@

3G function with WWAN

Discreate SKU

UMA SKU

SATA_ RE@ With SATA re-driver

NSATA _RE@ Bypass SATA r e-driver

NVPRO @

For Non- VPRO function

For VPRO functionVPRO @

MIRRO R@ For mirror function

TPM@

TPM function

NTPM @ Non TPM function

X76@

GPU VRAM Setting

DCI@ DCI function

ME@

ME Connector

For EMC functionEMC@

EMC_N S@

For EMC function (no mount)

RF@ For RF fun ction

RF_NS @ For RF function (no mount)

Audio @

SW@

CRR@

CRG@

For Non Audio debug function

For Audio debug function

For Card reader REALTEK strap

For Card reader BayHub strap

NOTE

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2015/01/12

2015/01/12

2015/01/12

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2016/01/12

2016/01/12

2016/01/12

2

Title

BOM LIST

BOM LIST

BOM LIST

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

FL490/FL590 NM-B931

FL490/FL590 NM-B931

FL490/FL590 NM-B931

Wednesday, March 13, 2019

Wednesday, March 13, 2019

Wednesday, March 13, 2019

Date: Sheet

Date: Sheet

Date: Sheet of

1

of

of

4 99

4 99

4 99

0.3

0.3

0.3

+3VS

+VCC_IO

Change to 2K for 15m test

+3VS

R0502 2K_0402_5%

D D

R0503 2K_0402_5%

R0504 2.2K_0201_1%@

R0505 2.2K_0402_5%

Rear Side TYPE-C Port/ HDMI

C C

B B

A A

5

+3VS 9, 10,11,12,14,15,23,25,30,32,37,39,40,42,49,50,51,55,56,57,58,59,60,61,62,63,65,66,72,82,86,87

+VCC_IO 11,18, 21,71

1 2

1 2

1 2

1 2

Front Side TYPE-C Port

EDP_RCOMP

1. Trace width=20 mils, Spacing=25mil, M ax length=600mils

2. RC1 close to MCP

Pull-up to VCCIO through 24.9-Ω ± 1 % resistor.
For CNL, it is 100 Ω ± 1%.
Please refer to PDG Table 3-2.

5

PCH_MUX_CLK

PCH_MUX_DAT

DDIP2_CTRLCLK

DDIP2_CTRLDATA

R0501

24.9_0402_1%

1 2

DDIP1_0N
DDIP1_0P
DDIP1_1N
DDIP1_1P
DDIP1_2N
DDIP1_2P
DDIP1_3N
DDIP1_3P

DDIP2_0N
DDIP2_0P
DDIP2_1N
DDIP2_1P
DDIP2_2N
DDIP2_2P
DDIP2_3N
DDIP2_3P

DDIP1_0N42
DDIP1_0P42
DDIP1_1N42
DDIP1_1P42
DDIP1_2N42
DDIP1_2P42
DDIP1_3N42
DDIP1_3P42

DDIP2_0N46
DDIP2_0P46
DDIP2_1N46
DDIP2_1P46
DDIP2_2N46
DDIP2_2P46
DDIP2_3N46
DDIP2_3P46

+VCC_IO

PCH_MUX_CLK42

PCH_MUX_DAT42

Trace Width=20mil, Spacing=25mil, Max l ength=600mil

4

+3VALW_PCH

20181220
follow Lx80 change MUX_HPD to mount

PCH_MUX_HPD

TYPEC_HPD-2

CPU_EDP_HPD

ENBKL

EDP_COMP

PCH_MUX_CLK
PCH_MUX_DAT

DDIP2_CTRLCLK
DDIP2_CTRLDATA

GPP_H17

4

1 2

R0506 100K_0402_5%

1 2

R0507 100K_0201_1%

1 2

R0508 100K_0402_5%

1 2

R0509 100K_0201_1%

?

UC1A

AL5

DDI1_TXN_0

AL6

DDI1_TXP_0

AJ5

DDI1_TXN_1

AJ6

DDI1_TXP_1

AF6

DDI1_TXN_2

AF5

DDI1_TXP_2

AE5

DDI1_TXN_3

AE6

DDI1_TXP_3

AC4

DDI2_TXN_0

AC3

DDI2_TXP_0

AC1

DDI2_TXN_1

AC2

DDI2_TXP_1

AE4

DDI2_TXN_2

AE3

DDI2_TXP_2

AE1

DDI2_TXN_3

AE2

DDI2_TXP_3

AM6

DISP_RCOMP

CC8

GPP_E18/DPPB_CTRLCLK/CNV_BT_HOST_WAKE#

CC9

GPP_E19/DPPB_CTRLDATA

CH4

GPP_E20/DPPC_CTRLCLK

CH3

GPP_E21/DPPC_CTRLDATA

CP4

GPP_E22/DPPD_CTRLCLK

CN4

GPP_E23/DPPD_CTRLDATA

CR26

GPP_H16/DDPF_CTRLCLK

CP26

GPP_H17/DDPF_CTRLDATA

WHISKEYLAKE-U_BGA1528

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CE NTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CE NTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CE NTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUTPRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUTPRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUTPRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

+3VALW_PCH 8,9,10,11,12,13,15,19

GPP_E13/DDPB_HPD0/DISP_MISC0
GPP_E14/DDPC_HPD1/DISP_MISC1
GPP_E15/DPPD_HPD2/DISP_MISC2
GPP_E16/DPPE_HPD3/DISP_MISC3

GPP_E17/EDP_HPD/DISP_MISC4

1 of 20

Issued Date

Issued Date

Issued Date

EDP_TXN_0
EDP_TXP_0
EDP_TXN_1
EDP_TXP_1
EDP_TXN_2
EDP_TXP_2
EDP_TXN_3
EDP_TXP_3

EDP_AUX_N
EDP_AUX_P

DISP_UTILS

DDI1_AUX_N
DDI1_AUX_P
DDI2_AUX_N
DDI2_AUX_P
DDI3_AUX_N
DDI3_AUX_P

EDP_BKLTEN

EDP_VDDEN

EDP_BKLTCTL

2015/01/12

2015/01/12

2015/01/12

3

AG4
AG3
AG2
AG1
AJ4
AJ3
AJ2
AJ1

AH4
AH3

AM7

PCH_MUX_AUX#

AC7

PCH_MUX_AUX

AC6

DDIP2_AUXN

AD4

DDIP2_AUXP

AD3
AG7
AG6

PCH_MUX_HPD

CN6

TYPEC_HPD-2

CM6

PCH_WWAN_PST#

CP7
CP6

CPU_EDP_HPD

CM7

CK11

ENBKL
PANEL_POWER_ON_CPU

CG11

PANEL_BKLT_CTRL_CPU

CH11

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

3

EDP_TXN0
EDP_TXP0
EDP_TXN1
EDP_TXP1

EDP_AUXN
EDP_AUXP

Deciphered Date

Deciphered Date

Deciphered Date

DP port

DDPB_CTRL DATA

DDPC_CTRL DATA

EDP_TXN0 60
EDP_TXP0 60
EDP_TXN1 60
EDP_TXP1 60

EDP_AUXN 60
EDP_AUXP 60

PCH_MUX_AUX# 42

PCH_MUX_AUX 42

DDIP2_AUXN 46

DDIP2_AUXP 46

PCH_MUX_HPD 42
TYPEC_HPD-2 45,46
PCH_WWAN_PST# 62

CPU_EDP_HPD 60

2

Enable Disa ble

Pull up to 3.3 V with 2.2-k ohm ± 5% resistor

Pull up to 3.3 V with 2.2-k ohm ± 5% resistor

20180824
Add GPIO control WWAN sequence

ENBKL 40
PANEL_POWER_ON_CPU 60
PANEL_BKLT_CTRL_CPU 60

2016/01/12

2016/01/12

2016/01/12

2

GPP_H17, Reserved,
Rising edge of PCH_PWROK
This signal has a weak
internal pull-down.

GPP_H17

Notes:

1. The internal pull-down is disabled after
PCH_PWROK is high.

2. This signal is in the primary well.

Titl e

Titl e

Titl e

WHL(A)_DDI/eDP

WHL(A)_DDI/eDP

WHL(A)_DDI/eDP

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

B

B

B

Date: Sheet of

Date: Sheet of

Date: Sheet of

FL490/FL590 NM-B931

FL490/FL590 NM-B931

FL490/FL590 NM-B931

Wednesday, March 13, 2019

Wednesday, March 13, 2019

Wednesday, March 13, 2019

1

+3VALW_PCH

1

no connect

no connect

12

R0510
1K_0201_1%

@

12

R0511
20K_0201_5%

@

5 99

5 99

5 99

0.3

0.3

0.3

5

www.teknisi-indonesia.com

+2.5V

+2.5V 23,24,25,26,95

+3VALW

+3VALW 9,10,12,13,15 ,18,19,3 9,40,41 ,43,45,46 ,49,52,5 8,60,62,6 3,65,66,6 7,71,72 ,83,84,8 5,96

+1.2V

+1.2V 7,18,23,24,25,2 6,86

TABLE

D D

Block 0

C C

Block 2

Block 4

B B

Block 6

A A

AL71
AL68
AN68
AN69
AL70
AL69
AN70
AN71
AR70
AR68
AU71
AU68
AR71
AR69
AU70
AU69

BB65

AW65
AW63
AY63
BA65
AY65
BA63
BB63
BA61
AW61
BB59
AW59
BB61
AY61
BA59
AY59

AY39

AW39
AY37
AW37
BB39
BA39
BA37
BB37
AY35
AW35
AY33
AW33
BB35
BA35
BA33
BB33

AY31

AW31
AY29
AW29
BB31
BA31
BA29
BB29
AY27
AW27
AY25
AW25
BB27
BA27
BA25
BB25

Interleave

Pin

DDR0_DQ[0]
DDR0_DQ[1]
DDR0_DQ[2]
DDR0_DQ[3]
DDR0_DQ[4]
DDR0_DQ[5]
DDR0_DQ[6]
DDR0_DQ[7]
DDR0_DQ[8]
DDR0_DQ[9]
DDR0_DQ[10]
DDR0_DQ[11]
DDR0_DQ[12]
DDR0_DQ[13]
DDR0_DQ[14]
DDR0_DQ[15]

DDR0_DQ[16]
DDR0_DQ[17]
DDR0_DQ[18]
DDR0_DQ[19]
DDR0_DQ[20]
DDR0_DQ[21]
DDR0_DQ[22]
DDR0_DQ[23]
DDR0_DQ[24]
DDR0_DQ[25]
DDR0_DQ[26]
DDR0_DQ[27]
DDR0_DQ[28]
DDR0_DQ[29]
DDR0_DQ[30]
DDR0_DQ[31]

DDR0_DQ[32]
DDR0_DQ[33]
DDR0_DQ[34]
DDR0_DQ[35]
DDR0_DQ[36]
DDR0_DQ[37]
DDR0_DQ[38]
DDR0_DQ[39]
DDR0_DQ[40]
DDR0_DQ[41]
DDR0_DQ[42]
DDR0_DQ[43]
DDR0_DQ[44]
DDR0_DQ[45]
DDR0_DQ[46]
DDR0_DQ[47]

DDR0_DQ[48]
DDR0_DQ[49]
DDR0_DQ[50]
DDR0_DQ[51]
DDR0_DQ[52]
DDR0_DQ[53]
DDR0_DQ[54]
DDR0_DQ[55]
DDR0_DQ[56]
DDR0_DQ[57]
DDR0_DQ[58]
DDR0_DQ[59]
DDR0_DQ[60]
DDR0_DQ[61]
DDR0_DQ[62]
DDR0_DQ[63]

Non-Interleav e

DDR0_DQ[0]
DDR0_DQ[1]
DDR0_DQ[2]
DDR0_DQ[3]
DDR0_DQ[4]
DDR0_DQ[5]
DDR0_DQ[6]
DDR0_DQ[7]
DDR0_DQ[8]
DDR0_DQ[9]
DDR0_DQ[10]
DDR0_DQ[11]
DDR0_DQ[12]
DDR0_DQ[13]
DDR0_DQ[14]
DDR0_DQ[15]

DDR0_DQ[32]
DDR0_DQ[33]
DDR0_DQ[34]
DDR0_DQ[35]
DDR0_DQ[36]
DDR0_DQ[37]
DDR0_DQ[38]
DDR0_DQ[39]
DDR0_DQ[40]
DDR0_DQ[41]
DDR0_DQ[42]
DDR0_DQ[43]
DDR0_DQ[44]
DDR0_DQ[45]
DDR0_DQ[46]
DDR0_DQ[47]

DDR1_DQ[0]
DDR1_DQ[1]
DDR1_DQ[2]
DDR1_DQ[3]
DDR1_DQ[4]
DDR1_DQ[5]
DDR1_DQ[6]
DDR1_DQ[7]
DDR1_DQ[8]
DDR1_DQ[9]
DDR1_DQ[10]
DDR1_DQ[11]
DDR1_DQ[12]
DDR1_DQ[13]
DDR1_DQ[14]
DDR1_DQ[15]

DDR1_DQ[32]
DDR1_DQ[33]
DDR1_DQ[34]
DDR1_DQ[35]
DDR1_DQ[36]
DDR1_DQ[37]
DDR1_DQ[38]
DDR1_DQ[39]
DDR1_DQ[40]
DDR1_DQ[41]
DDR1_DQ[42]
DDR1_DQ[43]
DDR1_DQ[44]
DDR1_DQ[45]
DDR1_DQ[46]
DDR1_DQ[47]

4

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ1 0
M_A_DQ1 1
M_A_DQ1 2
M_A_DQ1 3
M_A_DQ1 4
M_A_DQ1 5
M_A_DQ3 2
M_A_DQ3 3
M_A_DQ3 4
M_A_DQ3 5
M_A_DQ3 6
M_A_DQ3 7
M_A_DQ3 8
M_A_DQ3 9
M_A_DQ4 0
M_A_DQ4 1
M_A_DQ4 2
M_A_DQ4 3
M_A_DQ4 4
M_A_DQ4 5
M_A_DQ4 6
M_A_DQ4 7
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ1 0
M_B_DQ1 1
M_B_DQ1 2
M_B_DQ1 3
M_B_DQ1 4
M_B_DQ1 5
M_B_DQ3 2
M_B_DQ3 3
M_B_DQ3 4
M_B_DQ3 5
M_B_DQ3 6
M_B_DQ3 7
M_B_DQ3 8
M_B_DQ3 9
M_B_DQ4 0
M_B_DQ4 1
M_B_DQ4 2
M_B_DQ4 3
M_B_DQ4 4
M_B_DQ4 5
M_B_DQ4 6
M_B_DQ4 7

TABLE

Block 0

Block 2

Block 4

Block 6

?

UC1B

A26

DDR0_DQ_0/DDR0_DQ_0

D26

DDR0_DQ_1/DDR0_DQ_1

D28

DDR0_DQ_2/DDR0_DQ_2

C28

DDR0_DQ_3/DDR0_DQ_3

B26

DDR0_DQ_4/DDR0_DQ_4

C26

DDR0_DQ_5/DDR0_DQ_5

B28

DDR0_DQ_6/DDR0_DQ_6

A28

DDR0_DQ_7/DDR0_DQ_7

B30

DDR0_DQ_8/DDR0_DQ_8

D30

DDR0_DQ_9/DDR0_DQ_9

B33

DDR0_DQ_10/DDR0_DQ_10

D32

DDR0_DQ_11/DDR0_DQ_11

A30

DDR0_DQ_12/DDR0_DQ_12

C30

DDR0_DQ_13/DDR0_DQ_13

B32

DDR0_DQ_14/DDR0_DQ_14

C32

DDR0_DQ_15/DDR0_DQ_15

H37

DDR0_DQ_16/DDR0_DQ_32

H34

DDR0_DQ_17/DDR0_DQ_33

K34

DDR0_DQ_18/DDR0_DQ_34

K35

DDR0_DQ_19/DDR0_DQ_35

H36

DDR0_DQ_20/DDR0_DQ_36

H35

DDR0_DQ_21/DDR0_DQ_37

K36

DDR0_DQ_22/DDR0_DQ_38

K37

DDR0_DQ_23/DDR0_DQ_39

N36

DDR0_DQ_24/DDR0_DQ_40

N34

DDR0_DQ_25/DDR0_DQ_41

R37

DDR0_DQ_26/DDR0_DQ_42

R34

DDR0_DQ_27/DDR0_DQ_43

N37

DDR0_DQ_28/DDR0_DQ_44

N35

DDR0_DQ_29/DDR0_DQ_45

R36

DDR0_DQ_30/DDR0_DQ_46

R35

DDR0_DQ_31/DDR0_DQ_47

AN35

DDR0_DQ_32/DDR1_DQ_0

AN34

DDR0_DQ_33/DDR1_DQ_1

AR35

DDR0_DQ_34/DDR1_DQ_2

AR34

DDR0_DQ_35/DDR1_DQ_3

AN37

DDR0_DQ_36/DDR1_DQ_4

AN36

DDR0_DQ_37/DDR1_DQ_5

AR36

DDR0_DQ_38/DDR1_DQ_6

AR37

DDR0_DQ_39/DDR1_DQ_7

AU35

DDR0_DQ_40/DDR1_DQ_8

AU34

DDR0_DQ_41/DDR1_DQ_9

AW35

DDR0_DQ_42/DDR1_DQ_10

AW34

DDR0_DQ_43/DDR1_DQ_11

AU37

DDR0_DQ_44/DDR1_DQ_12

AU36

DDR0_DQ_45/DDR1_DQ_13

AW36

DDR0_DQ_46/DDR1_DQ_14

AW37

DDR0_DQ_47/DDR1_DQ_15

BA35

DDR0_DQ_48/DDR1_DQ_32

BA34

DDR0_DQ_49/DDR1_DQ_33

BC35

DDR0_DQ_50/DDR1_DQ_34

BC34

DDR0_DQ_51/DDR1_DQ_35

BA37

DDR0_DQ_52/DDR1_DQ_36

BA36

DDR0_DQ_53/DDR1_DQ_37

BC36

DDR0_DQ_54/DDR1_DQ_38

BC37

DDR0_DQ_55/DDR1_DQ_39

BE35

DDR0_DQ_56/DDR1_DQ_40

BE34

DDR0_DQ_57/DDR1_DQ_41

BG35

DDR0_DQ_58/DDR1_DQ_42

BG34

DDR0_DQ_59/DDR1_DQ_43

BE37

DDR0_DQ_60/DDR1_DQ_44

BE36

DDR0_DQ_61/DDR1_DQ_45

BG36

DDR0_DQ_62/DDR1_DQ_46

BG37

DDR0_DQ_63/DDR1_DQ_47

WHISKE YLAKE-U_B GA152 8

Pin Interleav e

AM70

DDR0_DQSN[0]

AM69

DDR0_DQSP[0]

AT69

DDR0_DQSN[1]

AT70

DDR0_DQSP[1]

BA64

DDR0_DQSN[2]

AY64

DDR0_DQSP[2]

AY60

DDR0_DQSN[3]

BA60

DDR0_DQSP[3]

BA38

DDR0_DQSN[4]

AY38

DDR0_DQSP[4]

AY34

DDR0_DQSN[5]

BA34

DDR0_DQSP[5]

BA30

DDR0_DQSN[6]

AY30

DDR0_DQSP[6]

AY26

DDR0_DQSN[7]

BA26

DDR0_DQSP[7]

DDR0_CKN_0/DDR0_CKN_0
DDR0_CKP_0/DDR0_CKP_0
DDR0_CKN_1/DDR0_CKN_1
DDR0_CKP_1/DDR0_CKP_1

DDR0_CKE_0/DDR0_CKE_0
DDR0_CKE_1/DDR0_CKE_1

DDR0_CKE_2/NC
DDR0_CKE_3/NC

DDR0_CS#_0/DDR0_CS#_0
DDR0_CS#_1/DDR0_CS#_1
DDR0_ODT_0/DDR0_ODT_0

NC/DDR0_ODT_1

DDR0_CAB_9/DDR0_MA_0
DDR0_CAB_8/DDR0_MA_1
DDR0_CAB_5/DDR0_MA_2

NC/DDR0_MA_3

NC/DDR0_MA_4
DDR0_CAA_0/DDR0_MA_5
DDR0_CAA_2/DDR0_MA_6
DDR0_CAA_4/DDR0_MA_7
DDR0_CAA_3/DDR0_MA_8
DDR0_CAA_1/DDR0_MA_9

DDR0_CAB_7/DDR0_MA_10
DDR0_CAA_7/DDR0_MA_11
DDR0_CAA_6/DDR0_MA_12
DDR0_CAB_0/DDR0_MA_13

DDR0_CAB_2/DDR0_MA_14
DDR0_CAB_1/DDR0_MA_15
DDR0_CAB_3/DDR0_MA_16

DDR0_CAB_4/DDR0_BA_0
DDR0_CAB_6/DDR0_BA_1
DDR0_CAA_5/DDR0_BG_0

DDR0_CAA_8/DDR0_ACT#
DDR0_CAA_9/DDR0_BG_1

DDR0_DQSN_0/DDR0_DQSN_0
DDR0_DQSP_0/DDR0_DQSP_0
DDR0_DQSN_1/DDR0_DQSN_1
DDR0_DQSP_1/DDR0_DQSP_1
DDR0_DQSN_2/DDR0_DQSN_4
DDR0_DQSP_2/DDR0_DQSP_4
DDR0_DQSN_3/DDR0_DQSN_5
DDR0_DQSP_3/DDR0_DQSP_5
DDR0_DQSN_4/DDR1_DQSN_0
DDR0_DQSP_4/DDR1_DQSP_0
DDR0_DQSN_5/DDR1_DQSN_1
DDR0_DQSP_5/DDR1_DQSP_1
DDR0_DQSN_6/DDR1_DQSN_4
DDR0_DQSP_6/DDR1_DQSP_4
DDR0_DQSN_7/DDR1_DQSN_5
DDR0_DQSP_7/DDR1_DQSP_5

NC/DDR0_ALERT#

NC/DDR0_PAR

DDR_VREF_CA
DDR0_VREF_DQ_0
DDR0_VREF_DQ_1

DDR1_VREF_DQ

DDR_VTT_CNTL

2 of 20

3

V32
V31
T32
T31

U36
U37
U34
U35

AE32
AF32
AE31
AF31

AC37
AC36
AC34
AC35
AA35
AB35
AA37
AA36
AB34
W36
Y31
W34
AA34
AC32

AC31
AB32
Y32

W32
AB31
V34

V35
W35

C27
D27
D31
C31
J35
J34
P34
P35
AP35
AP34
AV34
AV35
BB35
BB34
BF34
BF35

W37
W31
F36
D35
D37
E36
C35

Non-Interleav e

DDR0_DQSN[0]
DDR0_DQSP[0]
DDR0_DQSN[1]
DDR0_DQSP[1]

DDR0_DQSN[4]
DDR0_DQSP[4]
DDR0_DQSN[5]
DDR0_DQSP[5]

DDR1_DQSN[0]
DDR1_DQSP[0]
DDR1_DQSN[1]
DDR1_DQSP[1]

DDR1_DQSN[4]
DDR1_DQSP[4]
DDR1_DQSN[5]
DDR1_DQSP[5]

LOGIC

-M_A_DDR CLK0_1 066M
M_A_DDR CLK0_1 066M

-M_A_DDR CLK1_1 066M
M_A_DDR CLK1_1 066M

M_A_CKE 0
M_A_CKE 1

-M_A_CS0

-M_A_CS1
M_A_ODT 0
M_A_ODT 1

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13

M_A_A14
M_A_A15
M_A_A16

M_A_BS0
M_A_BS1
M_A_BG0

-M_A_ACT
M_A_BG1

-M_A_DQS 0
M_A_DQS 0

-M_A_DQS 1
M_A_DQS 1

-M_A_DQS 4
M_A_DQS 4

-M_A_DQS 5
M_A_DQS 5

-M_B_DQS 0
M_B_DQS 0

-M_B_DQS 1
M_B_DQS 1

-M_B_DQS 4
M_B_DQS 4

-M_B_DQS 5
M_B_DQS 5

-M_A_ALE RT
M_A_PAR ITY
M_A_VRE F_CA_C PU

M_B_VRE F_CA_C PU
DDR_PG _CTRL

TABLE

BA51
BB54
BA52
AY52
AW52
AY55
AW54
BA54
BA55
AY54

AU46
AU48
AT46
AU50
AU52
AY51
AT48
AT50
BB50
AY50
BA50
BB52

Pin

-M_A_DDR CLK0_1 066M 23
M_A_DDR CLK0_1 066M 23

-M_A_DDR CLK1_1 066M 23
M_A_DDR CLK1_1 066M 23

M_A_CKE 0 23
M_A_CKE 1 23

-M_A_CS0 2 3

-M_A_CS1 2 3
M_A_ODT 0 23
M_A_ODT 1 23

M_A_BS0 23
M_A_BS1 23
M_A_BG0 23

-M_A_ACT 23
M_A_BG1 23

-M_A_ALE RT 23
M_A_PAR ITY 2 3
M_A_VRE F_CA_C PU 23

M_B_VRE F_CA_C PU 25

DDR0_MA[5]
DDR0_MA[9]
DDR0_MA[6]
DDR0_MA[8]
DDR0_MA[7]
DDR0_BA[2]
DDR0_MA[12]
DDR0_MA[11]
DDR0_MA[15]
DDR0_MA[14]

DDR0_MA[13]
DDR0_CAS#
DDR0_WE#
DDR0_RAS#
DDR0_BA[0]
DDR0_MA[2]
DDR0_BA[1]
DDR0_MA[10]
DDR0_MA[1]
DDR0_MA[0]
DDR0_MA[3]
DDR0_MA[4]

LPDDR3DDR3L

DDR0_CAA[0]
DDR0_CAA[1]
DDR0_CAA[2]
DDR0_CAA[3]
DDR0_CAA[4]
DDR0_CAA[5]
DDR0_CAA[6]
DDR0_CAA[7]
DDR0_CAA[8]
DDR0_CAA[9]

DDR0_CAB[0]
DDR0_CAB[1]
DDR0_CAB[2]
DDR0_CAB[3]
DDR0_CAB[4]
DDR0_CAB[5]
DDR0_CAB[6]
DDR0_CAB[7]
DDR0_CAB[8]
DDR0_CAB[9]
Not Used
Not Used

2

1

C0601

0.1U_040 2_10V7 -K

@

2

DDR4

DDR0_MA[5]
DDR0_MA[9]
DDR0_MA[6]
DDR0_MA[8]
DDR0_MA[7]
DDR0_BG[0 ]
DDR0_MA[12]
DDR0_MA[11]
DDR0_ACT#
DDR0_BG[1 ]

DDR0_MA[13]
DDR0_MA[15]
DDR0_MA[14]
DDR0_MA[16]
DDR0_BA[0]
DDR0_MA[2]
DDR0_BA[1]
DDR0_MA[10]
DDR0_MA[1]
DDR0_MA[0]
DDR0_MA[3]
DDR0_MA[4]

1

M_A_DQ[6 3:0] 7,23

M_B_DQ[6 3:0] 7,25

M_A_A[16 :0] 2 3

-M_A_DQS [7:0] 7,23

M_A_DQS [7:0] 7,23

-M_B_DQS [7:0] 7,25

M_B_DQS [7:0] 7,25

+2.5V

+3VALW

12

12

R0602

SM_PG_C TRL

1

Q0601

DTC015 TMT2L_V MT3

3

12

R0604
10K_04 02_5%

@

R0601
100K_0 402_5%

100K_0 402_5%

@

SM_PG_C TRL 86

+1.2V

2

LOGIC

LOGIC

5

4

3

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/09/01

2015/09/01

2015/09/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/12/31

2016/12/31

2016/12/31

Title

Title

Title

WHL(B)_DDR4 CH.A

WHL(B)_DDR4 CH.A

WHL(B)_DDR4 CH.A

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

FL490/FL590 NM-B931

FL490/FL590 NM-B931

FL490/FL590 NM-B931

Wednesday, March 13, 2019

Wednesday, March 13, 2019

Wednesday, March 13, 2019

Date : Sheet of

Date : Sheet of

Date : Sheet of

6 99

6 99

6 99

1

0.3

0.3

0.3

5

www.teknisi-indonesia.com

+1.2V

+1.2V 6,18,2 3,24,25,2 6,86

TABLE

D D

Block 1

C C

Block 3

Block 5

B B

Block 7

A A

AF65
AF64
AK65
AK64
AF66
AF67
AK67
AK66
AF70
AF68
AH71
AH68
AF71
AF69
AH70
AH69

AT66

AU66
AP65
AN65
AN66
AP66
AT65
AU65
AT61
AU61
AP60
AN60
AN61
AP61
AT60
AU60

AU40
AT40
AT37
AU37
AR40
AP40
AP37
AR37
AT33
AU33
AU30
AT30
AR33
AP33
AR30
AP30

AU27
AT27
AT25
AU25
AP27
AN27
AN25
AP25
AT22
AU22
AU21
AT21
AN22
AP22
AP21
AN21

Interleave

Pin

DDR1_DQ[0]
DDR1_DQ[1]
DDR1_DQ[2]
DDR1_DQ[3]
DDR1_DQ[4]
DDR1_DQ[5]
DDR1_DQ[6]
DDR1_DQ[7]
DDR1_DQ[8]
DDR1_DQ[9]
DDR1_DQ[10]
DDR1_DQ[11]
DDR1_DQ[12]
DDR1_DQ[13]
DDR1_DQ[14]
DDR1_DQ[15]

DDR1_DQ[16]
DDR1_DQ[17]
DDR1_DQ[18]
DDR1_DQ[19]
DDR1_DQ[20]
DDR1_DQ[21]
DDR1_DQ[22]
DDR1_DQ[23]
DDR1_DQ[24]
DDR1_DQ[25]
DDR1_DQ[26]
DDR1_DQ[27]
DDR1_DQ[28]
DDR1_DQ[29]
DDR1_DQ[30]
DDR1_DQ[31]

DDR1_DQ[32]
DDR1_DQ[33]
DDR1_DQ[34]
DDR1_DQ[35]
DDR1_DQ[36]
DDR1_DQ[37]
DDR1_DQ[38]
DDR1_DQ[39]
DDR1_DQ[40]
DDR1_DQ[41]
DDR1_DQ[42]
DDR1_DQ[43]
DDR1_DQ[44]
DDR1_DQ[45]
DDR1_DQ[46]
DDR1_DQ[47]

DDR1_DQ[48]
DDR1_DQ[49]
DDR1_DQ[50]
DDR1_DQ[51]
DDR1_DQ[52]
DDR1_DQ[53]
DDR1_DQ[54]
DDR1_DQ[55]
DDR1_DQ[56]
DDR1_DQ[57]
DDR1_DQ[58]
DDR1_DQ[59]
DDR1_DQ[60]
DDR1_DQ[61]
DDR1_DQ[62]
DDR1_DQ[63]

Non-Interleav e

DDR0_DQ[16]
DDR0_DQ[17]
DDR0_DQ[18]
DDR0_DQ[19]
DDR0_DQ[20]
DDR0_DQ[21]
DDR0_DQ[22]
DDR0_DQ[23]
DDR0_DQ[24]
DDR0_DQ[25]
DDR0_DQ[26]
DDR0_DQ[27]
DDR0_DQ[28]
DDR0_DQ[29]
DDR0_DQ[30]
DDR0_DQ[31]

DDR0_DQ[48]
DDR0_DQ[49]
DDR0_DQ[50]
DDR0_DQ[51]
DDR0_DQ[52]
DDR0_DQ[53]
DDR0_DQ[54]
DDR0_DQ[55]
DDR0_DQ[56]
DDR0_DQ[57]
DDR0_DQ[58]
DDR0_DQ[59]
DDR0_DQ[60]
DDR0_DQ[61]
DDR0_DQ[62]
DDR0_DQ[63]

DDR1_DQ[16]
DDR1_DQ[17]
DDR1_DQ[18]
DDR1_DQ[19]
DDR1_DQ[20]
DDR1_DQ[21]
DDR1_DQ[22]
DDR1_DQ[23]
DDR1_DQ[24]
DDR1_DQ[25]
DDR1_DQ[26]
DDR1_DQ[27]
DDR1_DQ[28]
DDR1_DQ[29]
DDR1_DQ[30]
DDR1_DQ[31]

DDR1_DQ[48]
DDR1_DQ[49]
DDR1_DQ[50]
DDR1_DQ[51]
DDR1_DQ[52]
DDR1_DQ[53]
DDR1_DQ[54]
DDR1_DQ[55]
DDR1_DQ[56]
DDR1_DQ[57]
DDR1_DQ[58]
DDR1_DQ[59]
DDR1_DQ[60]
DDR1_DQ[61]
DDR1_DQ[62]
DDR1_DQ[63]

4

M_A_DQ1 6
M_A_DQ1 7
M_A_DQ1 8
M_A_DQ1 9
M_A_DQ2 0
M_A_DQ2 1
M_A_DQ2 2
M_A_DQ2 3
M_A_DQ2 4
M_A_DQ2 5
M_A_DQ2 6
M_A_DQ2 7
M_A_DQ2 8
M_A_DQ2 9
M_A_DQ3 0
M_A_DQ3 1
M_A_DQ4 8
M_A_DQ4 9
M_A_DQ5 0
M_A_DQ5 1
M_A_DQ5 2
M_A_DQ5 3
M_A_DQ5 4
M_A_DQ5 5
M_A_DQ5 6
M_A_DQ5 7
M_A_DQ5 8
M_A_DQ5 9
M_A_DQ6 0
M_A_DQ6 1
M_A_DQ6 2
M_A_DQ6 3
M_B_DQ1 6
M_B_DQ1 7
M_B_DQ1 8
M_B_DQ1 9
M_B_DQ2 0
M_B_DQ2 1
M_B_DQ2 2
M_B_DQ2 3
M_B_DQ2 4
M_B_DQ2 5
M_B_DQ2 6
M_B_DQ2 7
M_B_DQ2 8
M_B_DQ2 9
M_B_DQ3 0
M_B_DQ3 1
M_B_DQ4 8
M_B_DQ4 9
M_B_DQ5 0
M_B_DQ5 1
M_B_DQ5 2
M_B_DQ5 3
M_B_DQ5 4
M_B_DQ5 5
M_B_DQ5 6
M_B_DQ5 7
M_B_DQ5 8
M_B_DQ5 9
M_B_DQ6 0
M_B_DQ6 1
M_B_DQ6 2
M_B_DQ6 3

[WHL PDG]for WHL DDR4 COMPENSATION
DDR_RCOMP[0] Pull down 121 ohm resistor
DDR_RCOMP[1] Pull down 80.6 ohm resistor
DDR_RCOMP[2] Pull down 100 ohm resistor

TABLE

Interleave

AH66

DDR1_DQSN[0]

AH65

DDR1_DQSP[0]

AG69

Block 1

Block 3

Block 5

Block 7

AG70

AR66
AR65
AR61
AR60

AT38

AR38
AT32
AR32

AR25
AR27
AR22
AR21

DDR1_DQSN[1]
DDR1_DQSP[1]

DDR1_DQSN[2]
DDR1_DQSP[2]
DDR1_DQSN[3]
DDR1_DQSP[3]

DDR1_DQSN[4]
DDR1_DQSP[4]
DDR1_DQSN[5]
DDR1_DQSP[5]

DDR1_DQSN[6]
DDR1_DQSP[6]
DDR1_DQSN[7]
DDR1_DQSP[7]

?

UC1C

J22

DDR1_DQ_0/DDR0_DQ_16

H25

DDR1_DQ_1/DDR0_DQ_17

G22

DDR1_DQ_2/DDR0_DQ_18

H22

DDR1_DQ_3/DDR0_DQ_19

F25

DDR1_DQ_4/DDR0_DQ_20

J25

DDR1_DQ_5/DDR0_DQ_21

G25

DDR1_DQ_6/DDR0_DQ_22

F22

DDR1_DQ_7/DDR0_DQ_23

D22

DDR1_DQ_8/DDR0_DQ_24

C22

DDR1_DQ_9/DDR0_DQ_25

C24

DDR1_DQ_10/DDR0_DQ_26

D24

DDR1_DQ_11/DDR0_DQ_27

A22

DDR1_DQ_12/DDR0_DQ_28

B22

DDR1_DQ_13/DDR0_DQ_29

A24

DDR1_DQ_14/DDR0_DQ_30

B24

DDR1_DQ_15/DDR0_DQ_31

G31

DDR1_DQ_16/DDR0_DQ_48

G32

DDR1_DQ_17/DDR0_DQ_49

H29

DDR1_DQ_18/DDR0_DQ_50

H28

DDR1_DQ_19/DDR0_DQ_51

G28

DDR1_DQ_20/DDR0_DQ_52

G29

DDR1_DQ_21/DDR0_DQ_53

H31

DDR1_DQ_22/DDR0_DQ_54

H32

DDR1_DQ_23/DDR0_DQ_55

L31

DDR1_DQ_24/DDR0_DQ_56

L32

DDR1_DQ_25/DDR0_DQ_57

N29

DDR1_DQ_26/DDR0_DQ_58

N28

DDR1_DQ_27/DDR0_DQ_59

L28

DDR1_DQ_28/DDR0_DQ_60

L29

DDR1_DQ_29/DDR0_DQ_61

N31

DDR1_DQ_30/DDR0_DQ_62

N32

DDR1_DQ_31/DDR0_DQ_63

AJ29

DDR1_DQ_32/DDR1_DQ_16

AJ30

DDR1_DQ_33/DDR1_DQ_17

AM32

DDR1_DQ_34/DDR1_DQ_18

AM31

DDR1_DQ_35/DDR1_DQ_19

AM30

DDR1_DQ_36/DDR1_DQ_20

AM29

DDR1_DQ_37/DDR1_DQ_21

AJ31

DDR1_DQ_38/DDR1_DQ_22

AJ32

DDR1_DQ_39/DDR1_DQ_23

AR31

DDR1_DQ_40/DDR1_DQ_24

AR32

DDR1_DQ_41/DDR1_DQ_25

AV30

DDR1_DQ_42/DDR1_DQ_26

AV29

DDR1_DQ_43/DDR1_DQ_27

AR30

DDR1_DQ_44/DDR1_DQ_28

AR29

DDR1_DQ_45/DDR1_DQ_29

AV32

DDR1_DQ_46/DDR1_DQ_30

AV31

DDR1_DQ_47/DDR1_DQ_31

BA32

DDR1_DQ_48/DDR1_DQ_48

BA31

DDR1_DQ_49/DDR1_DQ_49

BD31

DDR1_DQ_50/DDR1_DQ_50

BD32

DDR1_DQ_51/DDR1_DQ_51

BA30

DDR1_DQ_52/DDR1_DQ_52

BA29

DDR1_DQ_53/DDR1_DQ_53

BD29

DDR1_DQ_54/DDR1_DQ_54

BD30

DDR1_DQ_55/DDR1_DQ_55

BG31

DDR1_DQ_56/DDR1_DQ_56

BG32

DDR1_DQ_57/DDR1_DQ_57

BK32

DDR1_DQ_58/DDR1_DQ_58

BK31

DDR1_DQ_59/DDR1_DQ_59

BG29

DDR1_DQ_60/DDR1_DQ_60

BG30

DDR1_DQ_61/DDR1_DQ_61

BK30

DDR1_DQ_62/DDR1_DQ_62

BK29

DDR1_DQ_63/DDR1_DQ_63

WHISKE YLAKE-U_B GA152 8

DDR1_CKN_0/DDR1_CKN_0
DDR1_CKP_0/DDR1_CKP_0
DDR1_CKN_1/DDR1_CKN_1
DDR1_CKP_1/DDR1_CKP_1

DDR1_CKE_0/DDR1_CKE_0
DDR1_CKE_1/DDR1_CKE_1

DDR1_CS#_0/DDR1_CS#_0

DDR1_CS#_1/DDR1_CS#_1
DDR1_ODT_0/DDR1_ODT_0

DDR1_CAB_7/DDR1_MA_10
DDR1_CAA_7/DDR1_MA_11
DDR1_CAA_6/DDR1_MA_12
DDR1_CAB_0/DDR1_MA_13

DDR1_CAB_2/DDR1_MA_14

DDR1_CAB_1/DDR1_MA_15
DDR1_CAB_3/DDR1_MA_16

DDR1_DQSN_0/DDR0_DQSN_2
DDR1_DQSP_0/DDR0_DQSP_2
DDR1_DQSN_1/DDR0_DQSN_3
DDR1_DQSP_1/DDR0_DQSP_3
DDR1_DQSN_2/DDR0_DQSN_6
DDR1_DQSP_2/DDR0_DQSP_6
DDR1_DQSN_3/DDR0_DQSN_7
DDR1_DQSP_3/DDR0_DQSP_7
DDR1_DQSN_4/DDR1_DQSN_2
DDR1_DQSP_4/DDR1_DQSP_2
DDR1_DQSN_5/DDR1_DQSN_3
DDR1_DQSP_5/DDR1_DQSP_3
DDR1_DQSN_6/DDR1_DQSN_6
DDR1_DQSP_6/DDR1_DQSP_6
DDR1_DQSN_7/DDR1_DQSN_7
DDR1_DQSP_7/DDR1_DQSP_7

3 of 20

Non-Interleav ePin

DDR0_DQSN[2]
DDR0_DQSP[2]
DDR0_DQSN[3]
DDR0_DQSP[3]

DDR0_DQSN[6]
DDR0_DQSP[6]
DDR0_DQSN[7]
DDR0_DQSP[7]

DDR1_DQSN[2]
DDR1_DQSP[2]
DDR1_DQSN[3]
DDR1_DQSP[3]

DDR1_DQSN[6]
DDR1_DQSP[6]
DDR1_DQSN[7]
DDR1_DQSP[7]

LOGIC

DDR1_CKE_2/NC
DDR1_CKE_3/NC

NC/DDR1_ODT_1
DDR1_CAB_9/DDR1_MA_0
DDR1_CAB_8/DDR1_MA_1
DDR1_CAB_5/DDR1_MA_2

NC/DDR1_MA_3

NC/DDR1_MA_4
DDR1_CAA_0/DDR1_MA_5
DDR1_CAA_2/DDR1_MA_6
DDR1_CAA_4/DDR1_MA_7
DDR1_CAA_3/DDR1_MA_8
DDR1_CAA_1/DDR1_MA_9

DDR1_CAB_4/DDR1_BA_0
DDR1_CAB_6/DDR1_BA_1
DDR1_CAA_5/DDR1_BG_0

DDR1_CAA_9/DDR1_BG_1
DDR1_CAA_8/DDR1_ACT#

NC/DDR1_ALERT#

NC/DDR1_PAR

DRAM_RESET#

DDR_COMP_0
DDR_COMP_1
DDR_COMP_2

3

-M_B_DDR CLK0_1 066M

AF28

M_B_DDR CLK0_1 066M

AF29

-M_B_DDR CLK1_1 066M

AE28

M_B_DDR CLK1_1 066M

AE29

M_B_CKE 0

T28

M_B_CKE 1

T29
V28
V29

-M_B_CS0

AL37

-M_B_CS1

AL35

M_B_ODT 0

AL36

M_B_ODT 1

AL34

M_B_A0

AG36

M_B_A1

AG35

M_B_A2

AF34

M_B_A3

AG37

M_B_A4

AE35

M_B_A5

AF35

M_B_A6

AE37

M_B_A7

AC29

M_B_A8

AE36

M_B_A9

AB29

M_B_A10

AG34

M_B_A11

AC28

M_B_A12

AB28

M_B_A13

AK35

M_B_A14

AJ35

M_B_A15

AK34

M_B_A16

AJ34

M_B_BS0

AJ37

M_B_BS1

AJ36

M_B_BG0

W29

M_B_BG1

Y28

-M_B_ACT

W28

-M_A_DQS 2

H24

M_A_DQS 2

G24

-M_A_DQS 3

C23

M_A_DQS 3

D23

-M_A_DQS 6

G30

M_A_DQS 6

H30

-M_A_DQS 7

L30

M_A_DQS 7

N30

-M_B_DQS 2

AL31

M_B_DQS 2

AL30

-M_B_DQS 3

AU31

M_B_DQS 3

AU30

-M_B_DQS 6

BC31

M_B_DQS 6

BC30

-M_B_DQS 7

BH31

M_B_DQS 7

BH30

-M_B_ALE RT

Y29

M_B_PAR ITY

AE34
BU31

-DRAMRST

DDR_RC OMP0
DDR_RC OMP1
DDR_RC OMP2

R0704 121_02 01_1%
R0701 80.6_02 01_1%
R0702 100_02 01_1%

BN28
BN27
BN29

[WHL PDG]for CNL DDR4 COMPENSATION
DDR_RCOMP[0] Pull down 100 ohm resistor
DDR_RCOMP[1] Pull down 100 ohm resistor
DDR_RCOMP[2] Pull down 100 ohm resistor

TABLE

Pin

AY48

DDR1_MA[5]

AP50

DDR1_MA[9]

BA48

DDR1_MA[6]

BB48

DDR1_MA[8]

AP48

DDR1_MA[7]

AP52

DDR1_BA[2]

AN50

DDR1_MA[12]

AN48

DDR1_MA[11]

AN53

DDR1_MA[15]

AN52

DDR1_MA[14]

BA43

DDR1_MA[13]

AY43

DDR1_CAS#

AY44

DDR1_WE#

AW44

DDR1_RAS#

BB44

DDR1_BA[0]

AY47

DDR1_MA[2]

BA44

DDR1_BA[1]

AW46

DDR1_MA[10]

AY46

DDR1_MA[1]

BA46

DDR1_MA[0]

BB46

DDR1_MA[3]

BA47

DDR1_MA[4]

1 2
1 2
1 2

DDR1_CAA[0]
DDR1_CAA[1]
DDR1_CAA[2]
DDR1_CAA[3]
DDR1_CAA[4]
DDR1_CAA[5]
DDR1_CAA[6]
DDR1_CAA[7]
DDR1_CAA[8]
DDR1_CAA[9]

DDR1_CAB[0]
DDR1_CAB[1]
DDR1_CAB[2]
DDR1_CAB[3]
DDR1_CAB[4]
DDR1_CAB[5]
DDR1_CAB[6]
DDR1_CAB[7]
DDR1_CAB[8]
DDR1_CAB[9]
Not Used
Not Used

2

-M_B_DDR CLK0_1 066M 25
M_B_DDR CLK0_1 066M 25

-M_B_DDR CLK1_1 066M 25
M_B_DDR CLK1_1 066M 25

M_B_CKE 0 25
M_B_CKE 1 25

-M_B_CS0 2 5

-M_B_CS1 2 5
M_B_ODT 0 25
M_B_ODT 1 25

M_B_BS0 25
M_B_BS1 25
M_B_BG0 25

M_B_BG1 25

-M_B_ACT 25

+1.2V

R0703
470_02 01_5%

1 2

-M_B_ALE RT 25
M_B_PAR ITY 2 5

-DRAMRST 23,25

LPDDR3DDR3L

DDR4

DDR1_MA[5]
DDR1_MA[9]
DDR1_MA[6]
DDR1_MA[8]
DDR1_MA[7]
DDR1_BG[0 ]
DDR1_MA[12]
DDR1_MA[11]
DDR1_ACT#
DDR1_BG[1 ]

DDR1_MA[13]
DDR1_MA[15]
DDR1_MA[14]
DDR1_MA[16]
DDR1_BA[0]
DDR1_MA[2]
DDR1_BA[1]
DDR1_MA[10]
DDR1_MA[1]
DDR1_MA[0]
DDR1_MA[3]
DDR1_MA[4]

M_A_DQ[6 3:0] 6,23

M_B_DQ[6 3:0] 6,25

M_B_A[16 :0] 25

-M_A_DQS [7:0] 6,23

M_A_DQS [7:0] 6,23

-M_B_DQS [7:0] 6,25

M_B_DQS [7:0] 6,25

1

LOGIC

LOGIC

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/09/01

2015/09/01

2015/09/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/12/31

2016/12/31

2016/12/31

Title

WHL(C)_DDR4 CH.B

WHL(C)_DDR4 CH.B

WHL(C)_DDR4 CH.B

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

FL490/FL590 NM-B931

FL490/FL590 NM-B931

FL490/FL590 NM-B931

Wednesday, March 13, 2019

Wednesday, March 13, 2019

Wednesday, March 13, 2019

Date : Sheet of

Date : Sheet of

Date : Sheet of

7 99

7 99

7 99

1

0.3

0.3

0.3

5

www.teknisi-indonesia.com

+VCC_ST

+VCC_STG

+3VALW_PCH

D D

VR_HOT#40,83,87

EC_WAKE#40

RJ45_LINKUP#52,53

MIC_DTCT#60

C C

B B

+VCC_ST 15,16,18,71 ,87

+VCC_STG 16 ,18,71

+3VALW_PCH 5,9,10,11,1 2,13,15,19

VR_HOT#

R0805
0_0402_SP

1 2

+VCC_STG

12

+VCC_ST

12

+3VALW_PCH

12

R0801
1K_0402_5%

R0803
1K_0201_1%

R0806
10K_0402_5%

R0802
499_0201_1%

1 2

TBC

4

H_PECI40

R0807 49.9_0402_1%

1 2

R0808 49.9_0402_1%

1 2

R0809 49.9_0402_1%

1 2

R0810 49.9_0402_1%

1 2

Follow the CRB

[WHL PDG FOR DCL DEBUG]

+VCC_ST

12

R0804

49.9_0402_1%

T4
T6
T8
T10

CATERR#

H_PECI

VR_HOT#_R

THERMTRIP#

XDP_BPM#0

1

XDP_BPM#1

1

XDP_BPM#2

1

XDP_BPM#3

1

EC_WAKE#_SUS

PROC_POPIRCOMP
PCH_OPIRCOMP
OPCE_RCOMP
OPC_RCOMP

3

?

UC1D

AA4

CATERR#

AR1

PECI

Y4

PROCHOT#

BJ1

THRMTRIP#

U1

BPM#_0

U2

BPM#_1

U3

BPM#_2

U4

BPM#_3

CE9

GPP_E3/CPU_GP0

CN3

GPP_E7/CPU_GP1

CB34

GPP_B3/CPU_GP2

CC35

GPP_B4/CPU_GP3

BP27

PROC_POPIRCOMP

BW25

PCH_OPIRCOMP

L5

RSVD35

N5

RSVD36

WHISKEYLAKE-U_BGA1528

4 of 20

PROC_TCK

PROC_TDI
PROC_TDO
PROC_TMS

PROC_TRST#

PCH_TCK

PCH_TDI
PCH_TDO
PCH_TMS

PCH_TRST#
PCH_JTAGX

PROC_PREQ#
PROC_PRDY#

T6
U6
Y5
T5
AB6

W6
U5
W5
P5
Y6
P6

W2
W1

XDP_TCLK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#

PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
PCH_JTAG_TRST#
PCH_JTAGX

2

R0817 51_0201_5%

1 2

R0818 51_0201_5%@

1 2

R0816 100_0201_5%

XDP_TCLK

XDP_TDI

XDP_TDO

XDP_TMS

XDP_TRST#

+VCC_STG

1 2

R0811 0_0201_SP

1 2

R0812 0_0201_SP

1 2

R0813 0_0201_SP

1 2

R0814 0_0201_SP

1 2

R0815 0_0201_SP

1 2

1

PCH_JTAGX

PCH_JTAG_TDI

PCH_JTAG_TDO

PCH_JTAG_TMS

PCH_JTAG_TRST#

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2015/01/12

2015/01/12

2015/01/12

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2016/01/12

2016/01/12

2016/01/12

2

Title

WHL(D)_MISC/ JTAG

WHL(D)_MISC/ JTAG

WHL(D)_MISC/ JTAG

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

FL490/FL590 NM-B931

FL490/FL590 NM-B931

FL490/FL590 NM-B931

Wednesday, March 13, 2019

Wednesday, March 13, 2019

Wednesday, March 13, 2019

Date: Sheet

Date: Sheet

Date: Sheet

1

of

of

of

8 99

8 99

8 99

0.3

0.3

0.3

+3VALW_PCH

www.teknisi-indonesia.com

+3V_SPI

+3VS

+3VALW

Mirror Code, Close to SPI ROM (U0901).

FSCE#40
SPI_FMOSI#40
SPI_FMISO40
SPI_FSCK40

D D

+3VS

JTAG ODT

SPI0_MOSI

+3V_SPI +3V_SP I

12

R0914
100K_0201_5%

SPI_SI SPI_SO

12

R0915
20K_0201_5%

@

C C

+1.8VALW+3VS

For ESPI and LPC interface

Reserved for future using

B B

A A

5

+3VALW_PCH 5,8,10,11,12,13,15,19

+3V_SPI 19

+3VS 5,10,11,12,14,15,23,25,30,32,37,39,40,42,49,50,51,55,56,57,58,59,60,61,62,63,65,66,72,82,86,87

+3VALW 6,10,12,13,15,18,19,39,40,41,43,45,46,49,52,58,60,62,63,65,66,67,71,72,83,84,85,96

R0947
1/20W_1K_5%_0201

@

SPI0_CLK

12

R0933
100K_0201_5%

@

SERIRQ

+3VS

12

R0929

@

10K_0201_5%

12

R0930

@

10K_0201_5%

12

R0902
100K_0201_5%

12

SPI_CS0#_16MB
SPI_SI_16MB
SPI_SO_16MB
SPI_CLK_16MBSPI_FSCK

R0946
1/20W_1K_5%_0201

@

1

C0904
22P_0402_50V8-J

2

EMC_NS@

FSCE#
SPI_FMOSI#

SPI_FMISO

R0950

1 8
2 7

KBRST#
EC_SCI#

3 6
4 5

10K_0804_8P4R_5%

12

R0916
1/20W_1K_5%_0201

@

12

R0917
20K_0201_5%

@

1 2

R0955 10K_0402_5%@

1 2

R0956 10K_0402_5%

@

GPP_D21
GPP_D22

@

1 2

R0924 0_0201_SP

1 2

R0925 0_0201_SP

1 2

R0926 0_0201_SP

1 2

R0927 0_0201_SP

Reverse i nternal 1K PU high

+3V_SPI +3V_SPI

12

R0928
100K_0201_5%

12

12

R0922

10K_0201_5%

12

R0923

10K_0201_5%

5

SPI_CLK

To TPM IC

SPI_CLK58
SPI_SO58
SPI_SI58

SPI_CS2#_TPM58

R0935,0936,0937,0938,094 2 shold be Near U0901 SPI ROM(0.5~1 inch)

SPI_IO3_16MB SPI_IO3
SPI_CLK_16MB
SPI_SI_16MB
SPI_IO2_16MB
SPI_SO_16MB SPI_SO

SPI_CS0#_16MB_R

4

SPI0 2 Load Topology Reserved

SPI_CLK

1 2

R0940 0_0201_SP

SPI_SO

1 2

R0941 0_0201_SP

SPI_SI

1 2

R0942 0_0201_SP

1 2

R0943 0_0201_SP

1 2

R0944 0_0201_SP

EC_SCI#40

C-LINK

CL_CLK_WLAN63

CL_DATA_WLAN63

CL_RST_WLAN#63

KBRST#40
SERIRQ40,58

1 2

R0935 1/20W_49.9_1%_0201

1 2

R0936 1/20W_49.9_1%_0201

1 2

R0937 1/20W_49.9_1%_0201

1 2

R0938 1/20W_49.9_1%_0201

1 2

R0939 1/20W_49.9_1%_0201

1 2

R0948 0_0201_SP

4

?

SPI0_CLK

CH37

SPI0_MISO

CF37

SPI0_MOSI

CF36

SPI0_IO2SPI_IO2

CF34

SPI0_IO3SPI_IO3

CG34

SPI_CS0#_16MB_R

CG36
CG35

SPI_CS2#_TPM

CH34

CF20

CG22

CF22

GPP_D21

CG23

GPP_D22

CH23

EC_SCI#

CG20

CL_CLK_WLAN

CH7

CL_DATA_WLAN

CH8

CL_RST_WLAN#

CH9

BV29

KBRST#

BV28

SERIRQ

0.085 A, 10m ils

@

12

D0901

RB520CM-30T2R_VMN2M2

1 2

R0905 0_0402_SP

SPI_CLK
SPI_SI
SPI_IO2

SPI_SO_16MB

SPI_IO2_16MB

32MB (256Mb) 200MIL SOIC8

MACRONIX MX25L25673GM2I-08G
MACRONIX MX25L25673GM2I-10G

32MB (256Mb) 8x6mm WSON8 (Opt ional)
WINBOND W25Q256JVEIQ

SPI_CS0#_16MB
SPI_SO_16MB
SPI_IO2_16MB

UC1E

SPI0_CLK
SPI0_MISO
SPI0_MOSI
SPI0_IO2
SPI0_IO3
SPI0_CS0#
SPI0_CS1#
SPI0_CS2#

GPP_D1/SPI1_CLK/BK1/SBK1
GPP_D2/SPI1_MISO_IO1/BK2/SBK2
GPP_D3/SPI1_MOSI_IO0/BK3/SBK3
GPP_D21/SPI1_IO2
GPP_D22/SPI1_IO3
GPP_D0/SPI1_CS0#/BK0/SBK0

CL_CLK
CL_DATA
CL_RST#

GPP_A0/RCIN#/TIME_SYNC1
GPP_A6/SERIRQ

WHISKEYLAKE-U_BGA1528

+3V_SPI+3VALW

32MB(25 6Mb)

U0901

1

/CS

2

DO(IO1)

/HOLD(IO3)

3

/WP(IO2)

GND4DI(IO0)

W25Q256JVEIQ_WSON8_8X6

@

U0902

1

CS#

VCC

2

SO/SIO1

SIO3

3

SIO2

SCLK

GND4SI/SIO0

MX25L25673GM2I-08G_SO8

3

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_B23/SML1ALERT#/PCHHOT#

GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

GPP_A8/CLKRUN#

5 of 20

20181 115
Need to verify the function.
R0905 should be mounted after SVT.
And vice versa umount D0901.

[WHL]SPI0_CS0#: SPI FLASH
SPI0_CS2#: S PI TPM

+3V_SPI

+3V_SPISPI_CS0#_16MB

8

VCC

SPI_IO3_16MB

7

SPI_CLK_16MB

6

CLK

SPI_SI_16MB

5

+3V_SPI

8

SPI_IO3_16MB

7

SPI_CLK_16MB

6

SPI_SI_16MB

5

3

2

C0902

0.1U_0201_6.3V6-K

1

CK14
CH15
CJ15

CH14
CF15
CG15

CN15
CM15
CC34

CA29
BY29
BY27
BV27
CA28
CA27

BV32
BV30
BY30

PCH_SMB_CLK
PCH_SMB_DATA
GPP_C2

PCH_SML0_CLK
PCH_SML0_DAT
GPP_C5

PCH_SML1_CLK
PCH_SML1_DATA
GPP_B23

LPC_AD0_R
LPC_AD1_R
LPC_AD2_R
LPC_AD3_R
LPC_FRAME#_R
ESPI_RST#_R

PCH_PCI_CLK_R

CLKRUN#

2

+3VALW_PCH

PCH_SMB_CLK
PCH_SMB_DATA
PCH_SML1_CLK
PCH_SML1_DATA

PCH_SML0_DAT
PCH_SML0_CLK

ESPI_RST#

R0901 0_0201_SP
R0903 0_0201_SP
R0904 0_0201_SP
R0906 0_0201_SP
R0931 0_0201_SP
R0932 0_0201_SP

R0910 22_0402_5%EMC@

R0911 8.2K_0402_5%

R0951

1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

LAN PHY

+3VS

+3VALW_PCH

+3VS

+3VALW_PCH

This signal has an internal p ull-down.
0 = Disable Inte lR DCI-OOB (Def ault)
1 = Enable IntelR DCI- OOB

1

C0903
22P_0402_50V8-J

EMC_NS@

2

+3VS

2

G

6 1

D

Q0901A
L2N7002KDW1T1G_SOT363-6

SB000013A00

1 2

R0953 0_0402_5%@

5

G

3 4

S

D

Q0901B
L2N7002KDW1T1G_SOT363-6

SB000013A00

1 2

R0954 0_0402_5%@

+3VS

2

G

6 1

D

Q0902A
L2N7002KDW1T1G_SOT363-6

SB000013A00

1 2

R0958 0_0402_5%@

5

G

3 4

S

D

Q0902B
L2N7002KDW1T1G_SOT363-6

SB000013A00

1 2

R0957 0_0402_5%@

2015/01/12

2015/01/12

2015/01/12

2

LPC_AD0 40
LPC_AD1 40
LPC_AD2 40
LPC_AD3 40
LPC_FRAME# 40
ESPI_RST# 40

CLK_PCI_EC 40

S

S

2N7002 KDWH
Vth= min 1V, max 2.5V
ESD 2KV

LC Future Center Sec ret Data

LC Future Center Sec ret Data

LC Future Center Sec ret Data

1 2

R0907 499_0201_1%

1 2

R0908 499_0201_1%

1 2

R0952 10K_0402_5%@

PCH_SML0_CLK 52

PCH_SML0_DAT 52

1 2

R0909 150K_0402_5%

FOR DCI USE

1 2
1 2
1 2
1 2
1 2
1 2

1 2

1 2

SMBus

PCH_SMB_CLK

PCH_SMB_DATA

PCH_SML1_CLK

PCH_SML1_DATA

Security Classificat ion

Security Classificat ion

Security Classificat ion

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY O R DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY O R DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY O R DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

20121 218

GPP_C5, Internal PD 20K

*L: LPC
H: eSPI

GPP_C5

+3VS

12

R0920

4.7K_0402_5%

DIMM1, DIMM 2 ,CP

Deciphered Date

Deciphered Date

Deciphered Date

Functional Strap Def initions

L:Disable Intel ME Crypto TLS cipher suite
(no confidentiality).
*H:Enable Intel ME Crypto Transport Layer
Security (TLS) cipher
suite (with confidentiality).Support Intel
AMT with TLS and Intel

12

12

R0918
1K_0402_5%

@

R0919
20K_0402_5%

@

SBA (Small Business Advantage) with TLS.

+3VALW_PCH

EC and TPM Module debug port

12

R0921

4.7K_0402_5%

PM_SMB_CLK

PM_SMB_DAT

EC_SMB_CK3

EC_SMB_DA3

GPU, Thermal Sendor,
Embedded Controller, G sensor

2016/01/12

2016/01/12

2016/01/12

1

GPP_C2, Internal PD 20K

+3VALW_PCH

12

R0912
1K_0402_5%

GPP_C2

12

R0913
20K_0201_5%

@

PM_SMB_CLK 23,25,65

PM_SMB_DAT 23,25,65

EC_SMB_CK3 32,40,57,59

EC_SMB_DA3 32,40,57,59

Title

Title

Title

WHL(E)_SPI/LPC/CLINK/ SMBUS

WHL(E)_SPI/LPC/CLINK/ SMBUS

WHL(E)_SPI/LPC/CLINK/ SMBUS

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

FL490/F L590 NM-B931

FL490/F L590 NM-B931

FL490/F L590 NM-B931

Wednesday, March 13, 2019

Wednesday, March 13, 2019

Wednesday, March 13, 2019

Date: Sheet

Date: Sheet

Date: Sheet

1

9 99

9 99

9 99

of

of

of

0.3

0.3

0.3

+3VALW_PCH

www.teknisi-indonesia.com

+3VS

+3VALW

+1.8VALW

D D

+1.8VALW

need to c heck

GPP_F6 A weak exte rnal pull-up is require d.
0 = Integrated CNVi enable.
1 = Integrated CNVi disable.

C C

To VGA_CORE IC, RPC3.7

IR_CAM_DTCT60

UART_EN4 0,41

B B

A A

5

+3VALW_PCH 5,8, 9,11,12,13 ,15,19

+3VS 5,9,11,1 2,14,15,23 ,25,30,32,3 7,39,40,42 ,49,50,51 ,55,56,57,5 8,59,60,61 ,62,63,65, 66,72,82,8 6,87

+3VALW 6,9, 12,13,15,1 8,19,39,40 ,41,43,45, 46,49,52,5 8,60,62,63 ,65,66,67,7 1,72,83,8 4,85,96

+1.8VALW 9,19,38,40 ,49,62,65,9 4

+3VALW_PCH

R1001
10K_0402_ 5%

1 2

+3VS

R1002
10K_0402_ 5%

1 2

@

+3VS

R1038
20K_0402_ 1%

1 2

@

RF_OFF#63

NFC_DLREQ66

20180920
Add GPIO control WWAN FW update

R1037 10K_0201_ 5%

HP_JACK_IN50

WWAN_PEW AKE#62

1 2

UART2_RX41,63

UART2_TX41,63

DGPU_PWROK37

DGPU_HOLD_RST#30

I2C0_DATA66

I2C0_CLK66

I2C_DATA_PD45
I2C_CLK_PD45

1 2

R1024

0_0201_SP

20181221
Add EC GPIO control IR CAM FW update

Graphics ID

-DISCRETE_

Status

PRESENCE
(GPP_D1 6)

UMA

0 (R101 6)

1 (R101 5)DIS

5

RF_OFF# BT_ON

WWAN_PEW AKE#

BT_ON63

VGA_ON37,38,39

R1023 0_0201 _5%@

Board ID

PHASE

EVT

FVT

SIT

SIT-R

SVT

+3VS

RF_OFF#

NFC_DLREQ
HP_JACK_IN
GPP_B18

WWAN_PEW AKE#

BT_ON
GPP_B22

GPP_F6

UART2_RX
UART2_TX

VGA_ON

DGPU_PWROK
DGPU_HOLD_RST#

I2C0_DATA
I2C0_CLK

I2C_DATA_PD
I2C_CLK_PD

1 2

PLANARID1

PLANARID2

(GPP_D1 4)

(GPP_D1 5)

0 (R101 8) 0 (R1020)

0 (R101 8)

0 (R102 0)

1 (R101 9)

0 (R101 8)

0 (R101 8)

1 (R101 7) 0 (R1020)

4

R1004

4.7K_0402 _5%

1 2

?

UC1F

CC27

GPP_B15/GSPI0_CS0#

CC32

GPP_A7/PIRQA#/GSPI0_CS1#

CE28

GPP_B16/GSPI0_CLK

CE27

GPP_B17/GSPI0_MISO

CE29

GPP_B18/GSPI0_MOSI

CA31

GPP_B19/GSPI1_CS0#

CA32

GPP_A11/PME#/GSPI1_CS1#/SD_VDD2_PWR_EN#

CC29

GPP_B20/GSPI1_CLK

CC30

GPP_B21/GSPI1_MISO

CA30

GPP_B22/GSPI1_MOSI

CK20

GPP_F5/CNV_BRI_RSP

CG19

GPP_F6/CNV_RGI_DT

CJ20

GPP_F4/CNV_BRI_DT

CH19

GPP_F7/CNV_RGI_RSP

CR12

GPP_C20/UART2_RXD

CP12

GPP_C21/UART2_TXD

CN12

GPP_C22/UART2_RTS#

CM12

GPP_C23/UART2_CTS#

CM11

GPP_C16/I2C0_SDA

CN11

GPP_C17/I2C0_SCL

CK12

GPP_C18/I2C1_SDA

CJ12

GPP_C19/I2C1_SCL

CF27

GPP_H4/I2C2_SDA

CF29

GPP_H5/I2C2_SCL

CH27

GPP_H6/I2C3_SDA

CH28

GPP_H7/I2C3_SCL

CJ30

GPP_H8/I2C4_SDA

CJ31

GPP_H9/I2C4_SCL

WHISKEYLAKE-U_BGA15 28

PLANARID0
(GPP_D1 3)

0 (R103 1)

1 (R103 0)

-DISCRETE_PRESENCE

0 (R103 1)

1 (R103 0)1 (R1019)

0 (R103 1)

4

GPP_A12/ISH_GP6/BM_BUSY#/SX_EXIT_HOLDOFF#

6 of 20

12

R1015

10K_0201_ 5%

PLANARID0
PLANARID1
PLANARID2

12

R1016

10K_0201_ 5%

GPP_D9/ISH_SPI_CS#/GSPI2_CS0#

GPP_D10/ISH_SPI_CLK/GSPI2_CLK
GPP_D11/ISH_SPI_MISO/GSPI2_MISO
GPP_D12/ISH_SPI_MOSI/GSPI2_MOSI

GPP_D5/ISH_I2C0_SDA
GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA
GPP_D8/ISH_I2C1_SCL

GPP_H10/I2C5_SDA/ISH_I2C2_SDA

GPP_H11/I2C5_SCL/ISH_I2C2_SCL

GPP_D13/ISH_UART0_RXD

GPP_D14/ISH_UART0_TXD

GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
GPP_C15/UART1_CTS#/ISH_UART1_CTS#

GPP_A18/ISH_GP0
GPP_A19/ISH_GP1
GPP_A20/ISH_GP2
GPP_A21/ISH_GP3
GPP_A22/ISH_GP4
GPP_A23/ISH_GP5

+3VS

12

12

R1017

10K_0201_ 5%

12

@

10K_0201_ 5%

R1019

@

10K_0201_ 5%

12

R1018

R1020

10K_0201_ 5%

DIS@

UMA@

3

TP_RESET_PCH

CN22

-LID_CLOSE_PC H -LID_CLOSE

CR22
CM22
CP22

GPP_D5

CK22

-PD_I2C_INT

CH20

GPP_D7

CH22
CJ22

-NFC_DTCT

CJ27

WWANRF_DISABL E#

CJ29

CM24

PLANARID0

CN23

PLANARID1

CM23

PLANARID2

-DISCRETE_PRESENCE

CR24

CG12

F1_LED#

CH12

F4_LED#

CF12

GPP_C15

CG14

BW35
BW34
CA37
CA36
CA35
CA34
BW37

12

R1030

@

10K_0201_ 5%

12

R1031
10K_0201_ 5%

Security Classification LC Future Center Secret Data

Security Classification LC Future Center Secret Data

Security Classification LC Future Center Secret Data

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUT URE CENT ER NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUT URE CENT ER NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUT URE CENT ER NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED T O ANY T HIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED T O ANY T HIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED T O ANY T HIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

+3VALW_PCH

1 2

R1034 0_ 0201_SP

1 2

R1032 0_ 0201_SP

-PD_I2C_INT 45

1 2

R1033 0_ 0201_SP

-NFC_DTCT 66
WWANRF_DISABL E# 62

F1_LED# 65
F4_LED# 65

GPP_B18, Internal PD 20K

*L: Disable “ No Reboot” mode
H: Enable “ No Reboot” mode

2015/01/12

2015/01/12

2015/01/12

2

1 2

R1007 10K_0 201_5%@

1 2

R1035 100K_ 0201_5%

TP_RESET

20180622
Swap DCI_DATA and DCI_CLK for DCI function

PAD_DISABLEPAD_DISABLE_PCH

+3VALW

12

R1039
10K_0402_ 5%

+3VALW_PCH

GPP_B18

Deciphered Date

Deciphered Date

Deciphered Date

2

DGPU_HOLD_RST#

TP_RESET 65

-LID_CLOSE 65
DCI_CLK 46
DCI_DATA 46

PAD_DISABLE 65

12

R1036

@

10K_0402_ 5%

WWAN_CFG1 62
WWAN_CFG2 62
WWAN_CFG3 62
WWAN_CFG0 62

GPP_B22, Internal PD 20K

*L: SPI
H: LPC

GPP_D12, External pull-up is required.
Recommend 100K if pulled up to 3.3V or 75K
if pulled up to 1.8V.

This strap should sampl e HIGH.
There should NOT be any on-board device driving it
to opposite direction during strap sampling.

GPP_D7, Reserved, Rising edge of DSW_PWROK

12

R1008
1K_0402_5 %

@

12

R1009
20K_0402_ 5%

@

External pull-up is required. Recommend 100K.
This strap should sampl e HIGH.
There should NOT be any on-board device driving it
to opposite direction during strap sa mpling

2016/01/12

2016/01/12

2016/01/12

+3VS

R1003
10K_0201_ 5%

1 2

@

R1026
10K_0201_ 5%

1 2

@

R1041
10K_0402_ 5%

1 2

@

12

R1010
1K_0402_5 %

@

GPP_B22

12

R1011
20K_0402_ 5%

@

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Shee t

Date: Shee t

Date: Shee t

GPP_D5

DCI_CLK

GPP_D7

WHL(F)_GPIO

WHL(F)_GPIO

WHL(F)_GPIO

FL490/FL590 NM-B931

FL490/FL590 NM-B931

FL490/FL590 NM-B931

Wednesday, March 13, 2019

Wednesday, March 13, 2019

Wednesday, March 13, 2019

1

VGA_ON

GPP_C15

WWANRF_DISABL E#

1

+3VS+3VS

12

12

R1013

10K_0201_ 5%

@

+3VS

12

R1005
100K_0201 _1%

12

R1006

10K_0201_ 5%

@

+3VALW_PCH

12

R1014
100K_0201 _1%

10 99

10 99

10 99

R1012
10K_0201_ 5%

@

of

of

of

0.3

0.3

0.3

5

www.teknisi-indonesia.com

+3VALW_PCH

+3VS

+VCC_HDA

+VCC_IO

+3VALW

D D

PCH_HDA_SDOUT49
PCH_HDA_SYNC49

ME_FLASH40

PCH_HDA_BCLK49

C C

B B

A A

WINDU and E470 can't stu ff TBD

+3VALW_PCH 5,8,9,10,12 ,13,15,19

+3VS 5,9,10,12,14 ,15,23,25,30,32,37,39,40,42,49,50,51 ,55,56,57,58,59,60,61,62,63,65,66,72 ,82,86,87

+VCC_HDA 19

+VCC_IO 5 ,18,21,71

+3VALW 6,9,10,12,13,15,18,19 ,39,40,41,43,45,46,49,52,58,60,62,63 ,65,66,67,71,72,83,84,85,96

PCH_HDA_SDOUT
PCH_HDA_SYNC HDA_SYNC

PCH_HDA_BCLK HDA_BCLK

PCH_HDA_SDIN049

MUX_SW_PCH42

S_L_CTL60

Full_Card_Power_Off#62

PCH_BEEP50

BIOS_HEALING40

201809 18
Add Bios Healing function

1

C1101
22P_0402_50V8-J

EMC@

2

201809 12
Add C1101 for HDA CLK EA test result

+3VALW_PCH

12

HDA_SYNC
HDA_BCLK
HDA_SDOUT
PCH_HDA_SDIN0

1

PLANARID4

HDA_RST#

MUX_SW_PCH

S_L_CTL

Full_Card_Power_Off#

CR_ID

PLANARID4

PCH_BEEP

BIOS_HEALING

+3VS

12

12

R1021

10K_0201_5%

R1022

10K_0201_5%

TP4618@

4

RP1101

1 8
2 7
3 6
4 5

33_0804_8P4R_5%

SD30000370T

R1101 0_04 02_SP

1 2

R1110 33_0402_5%EMC@

1 2

R1108
1K_0402_5%

@

R1123 0_02 01_SP

1 2

NTPM@

TPM@

HDA_SDOUT

Panel ID

(Pin#7 Control)

S_L_CTL

Status

(GPP_D 19)

0 (GND Low)

15"

14" 1 (NC High)

?

UC1G

BN34

HDA_SYNC/I2S0_SFRM

BN37

HDA_BCLK/I2S0_SCLK

BN36

HDA_SDO/I2S0_TXD

BN35

HDA_SDI0/I2S0_RXD

BL36

HDA_SDI1/I2S1_RXD/SNDW1_DATA

BL35

HDA_RST#/I2S1_SCLK/SNDW1_CLK

CK23

GPP_D23/I2S_MCLK

BL37

I2S1_SFRM/SNDW2_CLK

BL34

I2S1_TXD/SNDW2_DATA

CJ32

GPP_H1/I2S2_SFRM/CNV_BT_I2S_BCLK/CNV_RF_RESET#

CH32

GPP_H0/I2S2_SCLK/CNV_BT_I2S_SCLK

CH29

GPP_H2/I2S2_TXD/CNV_BT_I2S_SDI/MODEM_CLKREQ

CH30

GPP_H3/I2S2_RXD/CNV_BT_I2S_SDO

CP24

GPP_D19/DMIC_CLK0/SNDW4_CLK

CN24

GPP_D20/DMIC_DATA0/SNDW4_DATA

CK25

GPP_D17/DMIC_CLK1/SNDW3_CLK

CJ25

GPP_D18/DMIC_DATA1/SNDW3_DATA

CF35

GPP_B14/SPKR

WHISKEYLAKE-U_BGA1528

TPM ID

Status

TPM

NTPM

PLANARID4
(GPP_D1 8)

0 (R1022 )

1 (R1021 )

GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7

7 of 20

3

To enable Flash Descriptor Security Ove rride,
this signal should be pulled up to VCCHDA
through a 1 KΩ to 2.2 KΩ ± 5% resistor.

12

R1102
1K_0402_5%

@

12

R1103
20K_0402_5%

@

CH36

GPP_G0/SD_CMD

GPP_G4/SD_DATA3

GPP_G5/SD_CD#
GPP_G6/SD_CLK
GPP_G7/SD_WP

SD_1P8_RCOMP
SD_3P3_RCOMP

CL35
CL36
CM35
CN35
CH35
CK36

Table 3-1.RCOMP Recommendation for WHL and CFL

CK34

BW36
BY31

CK33
CM34

R1109 200_0402_1%

1 2

CR_ID

GPP_G1/SD3_DATA0
GPP_G2/SD3_DATA1
GPP_G3/SD3_DATA2

GPP_A16/SD_1P8_SEL

PCH_HDA_SDIN0HDA_SDOUT

+3VS

12

R1121

10K_0201_5%

12

R1122

10K_0201_5%

CRR@

CRG@

2

+VCC_IO+VCC_HDA

12

R1104
1K_0402_5%

@

12

R1105
20K_0402_5%

@

1

GPP_B14, Internal PD 20K
No Reboot on TCO
Timer ex piration
pull-up to VCC3_ 3 through a 1~8.2KΩ
resistor to disable this capabi lity

PCH_BEEP

+3VS

12

R1106

8.2K_0402_5%

@

12

R1107
20K_0402_5%

@

Card Reader ID

CR_ID

Status

(GPP_D17)

CRG

0 (R1022 )

CRR

1 (R1021 )

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2015/01/12

2015/01/12

2015/01/12

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2016/01/12

2016/01/12

2016/01/12

2

Title

WHL(G)_HDA/ GPIO

WHL(G)_HDA/ GPIO

WHL(G)_HDA/ GPIO

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

FL490/FL590 NM-B931

FL490/FL590 NM-B931

FL490/FL590 NM-B931

Wednesday, March 13, 2019

Wednesday, March 13, 2019

Wednesday, March 13, 2019

Date: Sheet

Date: Sheet

Date: Sheet

1

of

of

of

11 99

11 99

11 99

0.3

0.3

0.3

(Lef t back AOU)

+3VALW _PCH

www.teknisi-indonesia.com

+3VS

+3VALW

D D

C C

2.5" S ATA HDD

2242 PCIE SSD
2242 SATA SSD

B B

Optane Memory
PCIE WWAN CARD

5

+3VALW _PCH 5,8,9,10,1 1,13,15 ,19

+3VS 5,9,10,11 ,14,15,23 ,25,30,3 2,37,39,4 0,42,49 ,50,51,55 ,56,57,5 8,59,60,6 1,62,63 ,65,66,72 ,82,86,8 7

+3VALW 6,9 ,10,13,15 ,18,19,3 9,40,41,4 3,45,46 ,49,52,58 ,60,62,6 3,65,66,6 7,71,72 ,83,84,85 ,96

PCIE0_ L0_RXN30
PCIE0_ L0_RXP3 0
PCIE0_ L0_TXN30
PCIE0_ L0_TXP30

PCIE0_ L1_RXN30
PCIE0_ L1_RXP3 0
PCIE0_ L1_TXN30

GPU

NVMe SSD

WLAN

Card Reader

LAN

PCIE0_ L1_TXP30

PCIE0_ L2_RXN30
PCIE0_ L2_RXP3 0
PCIE0_ L2_TXN30
PCIE0_ L2_TXP30

PCIE0_ L3_RXN30
PCIE0_ L3_RXP3 0
PCIE0_ L3_TXN30
PCIE0_ L3_TXP30

PCIE9_ L0_RXN55
PCIE9_ L0_RXP5 5
PCIE9_ L0_TXN55
PCIE9_ L0_TXP55

PCIE9_ L1_RXN55
PCIE9_ L1_RXP5 5
PCIE9_ L1_TXN55
PCIE9_ L1_TXP55

PCIE11 _L0_SA TA1_R XN61
PCIE11 _L0_SA TA1_R XP61
PCIE11 _L0_SA TA1_T XN61
PCIE11 _L0_SA TA1_T XP61

PCIE12 _RXN63
PCIE12 _RXP63
PCIE12 _TXN63
PCIE12 _TXP63

PCIE13 _RXN51
PCIE13 _RXP51
PCIE13 _TXN51
PCIE13 _TXP51

PCIE14 _RXN52
PCIE14 _RXP52
PCIE14 _TXN52
PCIE14 _TXP52

PCIE15 _L1_RX N62
PCIE15 _L1_RX P62
PCIE15 _L1_TX N62
PCIE15 _L1_TX P62

PCIE15 _L0_SA TA2_R XN62
PCIE15 _L0_SA TA2_R XP62
PCIE15 _L0_SA TA2_T XN62
PCIE15 _L0_SA TA2_T XP62

1 2

C9918 0 .22U_020 1_6.3V 6M DIS@

1 2

C9917 0 .22U_020 1_6.3V 6M DIS@

1 2

C9920 0 .22U_020 1_6.3V 6M DIS@

1 2

C9919 0 .22U_020 1_6.3V 6M DIS@

Cap near UCPU1 side

1 2

C1005 0 .22U_020 1_6.3V 6M DIS@

1 2

C1006 0 .22U_020 1_6.3V 6M DIS@

1 2

C1007 0 .22U_020 1_6.3V 6M DIS@

1 2

C1008 0 .22U_020 1_6.3V 6M DIS@

R1208 100_0 201_1 %

1 2

SATA0_ DEVSLP

SSD_DE VSLP1

4

PCIE0_ L0_TXN_ C
PCIE0_ L0_TXP _C

PCIE0_ L1_TXN_ C
PCIE0_ L1_TXP _C

PCIE0_ L2_TXN_ C
PCIE0_ L2_TXP _C

PCIE0_ L3_TXN_ C
PCIE0_ L3_TXP _C

PCIE_R COMP
PCIE_R COMP_R

R1201
10K_02 01_5%

R1202
10K_02 01_5%

12

12

?

BW9
BW8
BW4
BW3

BU6
BU5
BU4
BU3

BT7
BT6
BU2
BU1

BU9
BU8
BT4
BT3

BP5
BP6
BR2
BR1

BN6
BN5
BR4
BR3

BN10

BN8
BN4
BN3

BL6
BL5
BN2
BN1

BK6

BK5
BM4
BM3

BJ6

BJ5

BL2

BL1

BG5
BG6

BL4

BL3

BE5

BE6

BJ4

BJ3

CE6

CE5

CR28
CP28
CN28

CM28

+3VS

UC1H

PCIE5_RXN/USB31_5_RXN
PCIE5_RXP/USB31_5_RXP
PCIE5_TXN/USB31_5_TXN
PCIE5_TXP/USB31_5_TXP

PCIE6_RXN/USB31_6_RXN
PCIE6_RXP/USB31_6_RXP
PCIE6_TXN/USB31_6_TXN
PCIE6_TXP/USB31_6_TXP

PCIE7_RXN
PCIE7_RXP
PCIE7_TXN
PCIE7_TXP

PCIE8_RXN
PCIE8_RXP
PCIE8_TXN
PCIE8_TXP

PCIE9_RXN
PCIE9_RXP
PCIE9_TXN
PCIE9_TXP

PCIE10_RXN
PCIE10_RXP
PCIE10_TXN
PCIE10_TXP

PCIE11_RXN/SATA0_RXN
PCIE11_RXP/SATA0_RXP
PCIE11_TXN/SATA0_TXN
PCIE11_TXP/SATA0_TXP

PCIE12_RXN/SATA1A_RXN
PCIE12_RXP/SATA1A_RXP
PCIE12_TXN/SATA1A_TXN
PCIE12_TXP/SATA1A_TXP

PCIE13_RXN
PCIE13_RXP
PCIE13_TXN
PCIE13_TXP

PCIE14_RXN
PCIE14_RXP
PCIE14_TXN
PCIE14_TXP

PCIE15_RXN/SATA1B_RXN
PCIE15_RXP/SATA1B_RXP
PCIE15_TXN/SATA1B_TXN
PCIE15_TXP/SATA1B_TXP

PCIE16_RXN/SATA2_RXN
PCIE16_RXP/SATA2_RXP
PCIE16_TXN/SATA2_TXN
PCIE16_TXP/SATA2_TXP

PCIE_RCOMP_N
PCIE_RCOMP_P

GPP_H12/M2_SKT2/CFG_0
GPP_H13/M2_SKT2/CFG_1
GPP_H14/M2_SKT2/CFG_2
GPP_H15/M2_SKT2/CFG_3

WHISKE YLAKE-U_B GA152 8

USB_OC0 #
USB_OC1 #
USB_OC3 #
USB_OC2 #

12

R1211
1/20W_ 15K_5% _0201

@

PCIE1_RXN/USB31_1_RXN
PCIE1_RXP/USB31_1_RXP

PCIE1_TXN/USB31_1_TXN
PCIE1_TXP/USB31_1_TXP

PCIE2_RXN/USB31_2_RXN/SSIC_1_RXN
PCIE2_RXP/USB31_2_RXP/SSIC_1_RXP
PCIE2_TXN/USB31_2_TXN/SSIC_1_TXN
PCIE2_TXP/USB31_2_TXP/SSIC_1_TXP

PCIE3_RXN/USB31_3_RXN
PCIE3_RXP/USB31_3_RXP

PCIE3_TXN/USB31_3_TXN
PCIE3_TXP/USB31_3_TXP

PCIE4_RXN/USB31_4_RXN
PCIE4_RXP/USB31_4_RXP

PCIE4_TXN/USB31_4_TXN
PCIE4_TXP/USB31_4_TXP

USB2_VBUSSENSE

GPP_E9/USB2_OC0#/GP_BSSB_CLK
GPP_E10/USB2_OC1#/GP_BSSB_DI

GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#

GPP_E4/DEVSLP0
GPP_E5/DEVSLP1
GPP_E6/DEVSLP2

GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2

GPP_E8/SATALED#/SPI1_CS1#

8 of 20

3

USB2_1N
USB2_1P

USB2_2N
USB2_2P

USB2_3N
USB2_3P

USB2_4N
USB2_4P

USB2_5N
USB2_5P

USB2_6N
USB2_6P

USB2_7N
USB2_7P

USB2_8N
USB2_8P

USB2_9N
USB2_9P

USB2_10N
USB2_10P

USB2_COMP

USB2_ID

RSVD37

12

R1210
1/20W_ 15K_5% _0201

@

CB5
CB6
CA4
CA3

BY8
BY9
CA2
CA1

BY7
BY6
BY4
BY3

BW6
BW5
BW2
BW1

CE3
CE4

CE1
CE2

CG3
CG4

CD3
CD4

CG5
CG6

CC1
CC2

CG8
CG9

CB8
CB9

CH5
CH6

CC3
CC4

CC5
CE8
CC6

CK6
CK5
CK8
CK9

CP8
CR8
CM8

CN8
CM10
CP10

CN7

AR3

USBCOMP

USB_OC0 #
USB_OC1 #
USB_OC2 #
NFC_INT

SATA0_ DEVSLP
NFC_ON
SSD_DE VSLP1

GPP_E1

12

R1213
1/20W_ 15K_5% _0201

@

+3VALW _PCH

R1217

1 8
2 7
3 6
4 5

12

10K_08 04_8P4 R_5%
R1214
1/20W_ 15K_5% _0201

@

1 2

R1218 113_0402_1%
R1215 1K_0402_5%@

1 2
1 2

R1216 1K_0402_5%@

USB_OC0 # 64

USB_OC2 # 50
NFC_INT 66

SATA0_ DEVSLP 61
NFC_ON 66
SSD_DE VSLP1 62

1

@

20180613

TP947

Swap GPP_E4 and GPP_E5 for HSIO modify

2

(TYPE-C)
(AUDIO SUB CARD)

USB3P1_ RXN 4 6
USB3P1_ RXP 46
USB3P1_ TXN 46
USB3P1_ TXP 46

USB3P2_ RXN 4 3
USB3P2_ RXP 43
USB3P2_ TXN 43
USB3P2_ TXP 43

USB3P3_ RXN 6 4
USB3P3_ RXP 64
USB3P3_ TXN 64
USB3P3_ TXP 64

USB3P4_ RXN 5 0
USB3P4_ RXP 50
USB3P4_ TXN 50
USB3P4_ TXP 50

USBP1- 64
USBP1+ 64

USBP2- 50
USBP2+ 50

USBP3- 47
USBP3+ 47

USBP4- 44
USBP4+ 44

USBP5- 65
USBP5+ 65

USBP6- 63
USBP6+ 63

USBP7- 60
USBP7+ 60

USBP8- 66
USBP8+ 66

USBP9- 62
USBP9+ 62

USBP10- 6 0
USBP10+ 6 0

+3VALW

TYPE-C(Front Side)

TYPE-C(Rear Side)

Syetem Port(AOU)

System Port on SUB/B

USB Port1 ( AOU)

USB Port2 (SUB/B)

USB Port3 (TYPE-C)

USB Port4(TYPE-C_CS18 DOCK)

SMART C ard

BT

RGB USB CAMERA

FPR

WWAN

Touch panel

R1206
10K_02 01_5%

1 2

GPP_E1/S ATA XPCI E1

GPP_E1

-WWAN_ PE_DTC T 62

+3VALW

1 2

1 2

1

R1204
10K_02 01_5%

@

R1205
10K_02 01_5%

@

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/01/12

2015/01/12

2015/01/12

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/01/12

2016/01/12

2016/01/12

Title

WHL(H)_PCIE/ SATA/ USB30

WHL(H)_PCIE/ SATA/ USB30

WHL(H)_PCIE/ SATA/ USB30

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

FL490/FL590 NM-B931

FL490/FL590 NM-B931

FL490/FL590 NM-B931

Wednesday, March 13, 2019

Wednesday, March 13, 2019

Wednesday, March 13, 2019

Date : Sheet

Date : Sheet

Date : Sheet

1

of

of

of

12 99

12 99

12 99

0.3

0.3

0.3

5

www.teknisi-indonesia.com

+3VS

+3VALW_PCH

D D

C C

+3VS 5,9,10,11, 12,14,15,23,25,30,32,37,39,40,42,49,50,51,55,56,57,58,59,60,61,62,63,65,66,72,82,86,87

+3VALW_PCH 5,8,9,10,11,12, 15,19

NFC_ACTIVE65,66

PCH_WWAN_RST#62

4

need to check

R1302

R1111 0_0201_5%@

PCH_WWAN_RST#

SC_DET#65

SC_DET#

1 2

1 2

150_0201_1%

?

UC1I

CR30

CNV_WR_D0N

CP30

CNV_WR_D0P

CM30

CNV_WR_D1N

CN30

CNV_WR_D1P

CN32

CNV_WT_D0N

CM32

CNV_WT_D0P

CP33

CNV_WT_D1N

CN33

CNV_WT_D1P

CN31

CNV_WR_CLKN

CP31

CNV_WR_CLKP

CP34

CNV_WT_CLKN

CN34

CNV_WT_CLKP

CP32

CNV_WT_RCOMP_0

CR32

CNV_WT_RCOMP_1

CP20

GPP_F0/CNV_PA_BLANKING

CK19

GPP_F1

CG17

GPP_F2

CR14

GPP_C8/UART0_RXD

CP14

GPP_C9/UART0_TXD

CN14

GPP_C10/UART0_RTS#

CM14

GPP_C11/UART0_CTS#

CJ17

GPP_F8/CNV_MFUART2_RXD

CH17

GPP_F9/CNV_MFUART2_TXD

CF17

GPP_F23/A4WP_PRESENT

WHISKEYLAKE-U_BGA1528

3

GPP_H18/CPU_C10_GATE#

GPP_H19/TIMESYNC_0

GPP_H21 / XTAL_FREQ_SELECT

GPP_D4/IMGCLKOUT0/BK4/SBK4

9 of 20

GPP_H22
GPP_H23
GPP_F10

GPD7

GPP_F3

GPP_H20/IMGCLKOUT_1

GPP_F12/EMMC_DATA0
GPP_F13/EMMC_DATA1
GPP_F14/EMMC_DATA2
GPP_F15/EMMC_DATA3
GPP_F16/EMMC_DATA4
GPP_F17/EMMC_DATA5
GPP_F18/EMMC_DATA6
GPP_F19/EMMC_DATA7

GPP_F20/EMMC_RCLK

GPP_F21/EMMC_CLK

GPP_F11/EMMC_CMD

GPP_F22/EMMC_RESET#

EMMC_RCOMP

2

CN27

CM27

GPP_H21

CF25
CN26

GPP_H23

CM26
CK17

BV35

GPD7

CN20

CG25
CH25

CR20
CM20
CN19
CM19
CN18
CR18
CP18
CM18

CM16
CP16
CR16

1 2

CN16

R43270 0_0201_SP

1 2

CK15

R1301

200_0402_1%

1

CPU_C10_GATE# 18,71

+3VALW

12

R1316
100K_0402_5%

GPD7

20190108
follow intel request pull high Res

-TAMPER_SW_DTCT 15

+3VALW_PCH

R1312

4.7K_0201_5%

1 2

GPP_H21

12

R1313
10K_0201_5%

@

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

2015/01/12

2015/01/12

2015/01/12

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

3

Deciphered Date

Deciphered Date

Deciphered Date

2016/01/12

2016/01/12

2016/01/12

2

Titl e

Titl e

Titl e

WHL(I)_CS12/ EMMC

WHL(I)_CS12/ EMMC

WHL(I)_CS12/ EMMC

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

B

B

B

Date: Sheet of

Date: Sheet of

Date: Sheet of

FL490/FL590 NM-B931

FL490/FL590 NM-B931

FL490/FL590 NM-B931

Wednesday, March 13, 2019

Wednesday, March 13, 2019

Wednesday, March 13, 2019

1

13 99

13 99

13 99

0.3

0.3

0.3

GPP_H23

+3VALW_PCH

R1314

4.7K_0201_5%

@

1 2

12

R1315
10K_0201_5%

@

GPP_H23, Internal Weak

B B

A A

pull-down

This strap must be configured to 0
(SAFS is disabled)
if the eSPI or LPC strap is configured to 0
(eSPI is disabled)

5

GPP_H21, Internal Weak
pull-down
LOW: 38.4/19.2MHZ (DEFAULT)
HIGH: 24MHZ

4

5

MCP for temp inf l uence

www.teknisi-indonesia.com

+RTCBATT

+RTCVCC

+3VS

RTC External Circuit

D D

+RTCBATT, +RTCVCC

Trace width = 20mils

near CC59 for layout

C C

PCIE SSD

WWAN

WLAN

LAN

GPU

CR

B B

+RTCBATT 66,80

+RTCVCC 15,19

+3VS 5,9,10,11,12 ,15,23,25,30,32,37,39,40,42,49,50,51 ,55,56,57,58,59,60,61,62,63,65,66,72 ,82,86,87

+RTCVCC+RTCBATT

R1401 0_04 02_SP

1 2

-PCIE9_CLK_100M56
PCIE9_CLK_100M56

-CLKREQ_PCIE956

-PCIE15_CLK_100M62
PCIE15_CLK_100M62

-CLKREQ_PCIE1562

-PCIE12_CLK_100M63
PCIE12_CLK_100M63

-CLKREQ_PCIE1263

-PCIE14_CLK_100M52
PCIE14_CLK_100M52

-CLKREQ_PCIE1452

-PCIE0_CLK_100M30
PCIE0_CLK_100M30

-CLKREQ_PCIE032

-PCIE13_CLK_100M51
PCIE13_CLK_100M51

-CLKREQ_PCIE1351

1

C1402

0.1U_0402_10V6-K

2

+RTCVCC

4

R1402
20K_0402_5%

1 2

R1403
20K_0402_5%

1 2

AW2

CF32

CE32

CF30

CE31

CE30

CF31

?

UC1J

CLKOUT_PCIE_N_0

AY3

CLKOUT_PCIE_P_0
GPP_B5/SRCCLKREQ0#

BC1

CLKOUT_PCIE_N_1

BC2

CLKOUT_PCIE_P_1
GPP_B6/SRCCLKREQ1#

BD3

CLKOUT_PCIE_N_2

BC3

CLKOUT_PCIE_P_2
GPP_B7/SRCCLKREQ2#

BH3

CLKOUT_PCIE_N_3

BH4

CLKOUT_PCIE_P_3
GPP_B8/SRCCLKREQ3#

BA1

CLKOUT_PCIE_N_4

BA2

CLKOUT_PCIE_P_4
GPP_B9/SRCCLKREQ4#

BE1

CLKOUT_PCIE_N_5

BE2

CLKOUT_PCIE_P_5
GPP_B10/SRCCLKREQ5#

WHISKEYLAKE-U_BGA1528

PCH_RTCRST#

C1404 1U_0402_ 10V6-K

PCH_SRTCRST#

C1405 1U_0402_ 10V6-K

10 of 20

PCH_XTAL24_IN

PCH_XTAL24_OUT

JCMOS1

@

1 2

1 2

JME1

@

1 2

1 2

CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

GPD8/SUSCLK

XTAL_IN

XTAL_OUT

CLK_BIASREF

CLKIN_XTAL

SRTCRST#

RTCRST#

RTCX1
RTCX2

3

RTC Crystal

1. Space > 15mils

2. No trace under crystal

3. Place on oppsosit side of

201812 19
change RTC crystal cap for RTC test result

CLKOUT_ITPXDP_N

AU1

CLKOUT_ITPXDP_P

AU2

SUSCLK_32K

BT32

PCH_XTAL24_IN

CK3

PCH_XTAL24_OUT

CK2

XCLK_BIASREF

CJ1

CLKIN_XTAL

CM3

PCH_RTCX1

BN31

PCH_RTCX2

BN32

PCH_SRTCRST#

BR37

PCH_RTCRST#

BR34

Need close CPU

EMC

L1401 SBY100 505T-300Y-N

1 2

SM01000JN0J

FOOTPRINT:R_0402

EMC

L1402 SBY100 505T-300Y-N

1 2

SM01000JN0J

FOOTPRINT:R_0402

R1404
10M_0402_5%

1 2

YC3

32.768KHZ_9PF_9H0328001 2

1 2

1

C1406

8.2P_0201_50V8-C

2

1

T56

1

T57

R1409 60.4_0402_1%

1 2

R1432 0_0201_SP

1 2

SUSCLK_32K 63

need to check

PCH_RTCX1

PCH_RTCX2

1

C1407

8.2P_0201_50V8-C

2

PCH_XTAL24_IN_R

PCH_XTAL24_OUT_R

to WLAN

2

R1433
0_0201_SP

1 2

XTAL24_OUT_R

1

C1401
12P_0201_25V8-J

2

+3VS

12

R1406
10K_0402_5%

UMA@

-CLKREQ_PCIE0

12

R1407
10K_0402_5%

DIS@

+3VS

+3VS

12

R1431
10K_0402_5%

R1408
1/20W_200K_1%_0201

1 2

YC1
24MHZ_10PF_8Y2400001 1

1

1

GND1

2

SJ10000P100

RP1401

1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

-CLKREQ_PCIE15

3

GND2

4

3

-CLKREQ_PCIE12

-CLKREQ_PCIE14

-CLKREQ_PCIE9

-CLKREQ_PCIE13

1

2

1

C1403
12P_0201_25V8-J

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2015/01/12

2015/01/12

2015/01/12

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2016/01/12

2016/01/12

2016/01/12

2

Title

WHL(J)_RTC/ CLK

WHL(J)_RTC/ CLK

WHL(J)_RTC/ CLK

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

FL490/FL590 NM-B931

FL490/FL590 NM-B931

FL490/FL590 NM-B931

Wednesday, March 13, 2019

Wednesday, March 13, 2019

Wednesday, March 13, 2019

1

of

of

of

14 99

14 99

14 99

0.3

0.3

0.3

5

This must always be pulled high on product i on boards.

www.teknisi-indonesia.com

+3VALW

+3VALW_PCH

+3VS

+RTCVCC

+VCC_ST

+3VALW +3VS

D D

+3VALW

C C

PCH_PWROK40

VGATE4 0,87

PCH_LAN_WAKE#52

FOR VPRO LAN WAKE#

B B

A A

-TAMPER_SW_DTCT13

+3VALW 6,9,10,12,13,18,19,39 ,40,41,43,45,46,49,52,58,60,62,63,65 ,66,67,71,72,83,84,85,96

+3VALW_PCH 5,8,9,10,11 ,12,13,19

+3VS 5,9,10,11,12 ,14,23,25,30,32,37,39,40,42,49,50,51 ,55,56,57,58,59,60,61,62,63,65,66,72 ,82,86,87

+RTCVCC 14,19

+VCC_ST 8,16,18,71,87

RP1501

AC_PRESENT

1 8
2 7

BATLOW#

3 6
4 5

10K_0804_8P4R_5%

SD300002P0T

R1501 10K_0402_5%@

1 2

R1502 10K_0402_5%@

1 2

R1503 1K_0402_5%

1 2

PCH_PLT_RST#

For vPRO LAN WAKE#

EC_WAKE#_DSW

PM_SLP_S5#

PCIE_WAKE#

R1515 0_0402_SP

1 2

R1516 0_0402_5%@

1 2

R1532 0_0402_SP

1 2

12

R1524
100K_0402_5%

5

R1523 0_0402_SP

1 2

U1501

@

NC1VCC

2

IN_A

3

GND

TC7SG17FE_SON5

S3

1

2

SPVR310100_4P

+3VALW_PCH

+3VALW

12

R43271

4.7K_0402_5%

OUT_Y

4

3

4

R1505 10K_0201_5%@

1 2

R1506 10K_0201_5%

1 2

R1507 10K_0402_5%

1 2

R1508 10K_0201_5%@

1 2

R1525 10K_0402_5%

1 2

R1526 10K_0201_5%@

1 2

R1527 10K_0402_5%@

1 2

VCCST_PWRGD

R1519 60.4_0402_1%

1 2

EC_RSMRST#

R1520 0_0402_SP

1 2

R1521 0_0402_SP

1 2

+3VALW

5

4

12

C7214

0.1U_0402_16V7-K

EMC_NS@

R1531 0_02 01_SP

1 2

4

PCH_SYSPWROK40,66

PLT_RST#

EC_RSMRST#40

PCIE_WAKE#62,63

LANPHYPC52

SYS_RESET#

EC_RSMRST#

H_CPUPWRGDH_CPUPWRGD

PCH_PWROK

PCH_SYSPWROK

AC_PRESENT

1

PCH_PLT_RST#
SYS_RESET#
EC_RSMRST#

H_CPUPWRGD

PCH_SYSPWROK

PWROK
DSW_PWROK

SUSWARN#
SUSACK#

PCIE_WAKE#
EC_WAKE#_DSW

LANPHYPC

PLT_RST# 30,40,51,52,56,58,6 2,63

T1509

PCH_INTRUDER#

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

Reserved for HW co ntrol

VCCST_PG_EC40

?

UC1K

BJ35

GPP_B13/PLTRST#

CN10

SYS_RESET#

BR36

RSMRST#

AR2

PROCPWRGD

BJ2

VCCST_PWRGOOD

CR10

SYS_PWROK

BP31

PCH_PWROK

BP30

DSW_PWROK

BV34

GPP_A13/SUSWARN#/SUSPWRDACK

BY32

GPP_A15/SUSACK#

BU30

WAKE#

BU32

GPD2/LAN_WAKE#

BU34

GPD11/LANPHYPC

Issued Date

Issued Date

Issued Date

3

VR_ON40,87

11 of 20

GPP_B11/EXT_PWR_GATE#

GPP_B2/VRALERT#

WHISKEYLAKE-U_BGA1528

2015/01/12

2015/01/12

2015/01/12

R1509 0_0402_5%@

1 2

R1510 0_0402_5%@

1 2

GPP_B12/SLP_S0#

GPD1/ACPRESENT

BJ37
BU36

GPD4/SLP_S3#

BU27

GPD5/SLP_S4#

BT29

GPD10/SLP_S5#

BU29

SLP_SUS#

BT31

SLP_LAN#

BT30

GPD9/SLP_WLAN#

BU37

GPD6/SLP_A#

BU28

GPD3/PWRBTN#

BU35
BV36

GPD0/BATLOW#

BR35

INTRUDER#

CC37
CC36

BT27

INPUT3VSEL

1. must be always pulled-up to VCCRTC.

2. 1 = Enable DSW 3 .3V-to-1.05V Integrated DeepSx Well (DS W) On-Die Voltage Regulator.

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

R1529 0_04 02_SP

1 2

12

@

R1511
100K_0402_5%

2

G

PM_SLP_S3#

1

PM_SLP_S4#

1

PM_SLP_S5#

1

PM_SLP_S0#

1

PM_SLP_S3#
PM_SLP_S4#
PM_SLP_S5#

PCH_SLP_SUS#

1

PCH_SLP_LAN#
PCH_SLP_WLAN#
PM_SLP_A#

1

PBTN_OUT#
AC_PRESENT

BATLOW#

PCH_INTRUDER#

EXT_PWR_GATE#

1

VRALERT#

INPUT3VSEL

2016/01/12

2016/01/12

2016/01/12

2

+3VALW

12

@

R1512
100K_0402_5%

13

D

Q1501
LSK3541G1ET2L_VMT3

@

S

T1501
T1502
T1503

T1504

PM_SLP_S3# 40
PM_SLP_S4# 40
PM_SLP_S5# 40

T1505

PCH_SLP_LAN# 40
PCH_SLP_WLAN# 40

T1508

PBTN_OUT# 40

AC_PRESENT 40

R1522 1M_0 402_5%

1 2

T1507

1

+VCC_ST

12

R1513
1K_0402_5%

VCCST_PWRGD

13

D

Q1502

2

G

LSK3541G1ET2L_VMT3

@

S

+3VALW

12

R1517
100K_0402_5%

+RTCVCC

Follow the CRB

INPUT3VSEL

Title

Title

Title

WHL(K)_SYS PM

WHL(K)_SYS PM

WHL(K)_SYS PM

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

FL490/FL590 NM-B931

FL490/FL590 NM-B931

FL490/FL590 NM-B931

Wednesday, March 13, 2019

Wednesday, March 13, 2019

Wednesday, March 13, 2019

Date: Sheet

Date: Sheet

Date: Sheet

+3VALW

R1504

@

4.7K_0402_5%

1 2

R1514

4.7K_0402_5%

1 2

of

of

of

15 99

15 99

15 99

1

0.3

0.3

0.3

5

www.teknisi-indonesia.com

+VCC_CORE

+VCC_ST

+VCC_STG

D D

C C

B B

+VCC_CORE 17,27 ,88,91

+VCC_ST 8,15,18,71,87

+VCC_STG 8,18 ,71

1
1
1
1

?

UC1L

AN9

VCCCORE5

AN10

VCCCORE1

AN24

VCCCORE2

AN26

VCCCORE3

AN27

VCCCORE4

AP2

VCCCORE6

AP9

VCCCORE9

AP24

VCCCORE7

AP26

VCCCORE8

AR5

VCCCORE13

AR6

VCCCORE14

AR7

VCCCORE15

AR8

VCCCORE16

AR10

VCCCORE10

AR25

VCCCORE11

AR27

VCCCORE12

AT9

VCCCORE19

AT24

VCCCORE17

AT26

VCCCORE18

AU5

VCCCORE24

AU6

VCCCORE25

AU7

VCCCORE26

AU8

VCCCORE27

AU9

VCCCORE28

AU24

VCCCORE20

AU25

VCCCORE21

AU26

VCCCORE22

AU27

VCCCORE23

AV2

VCCCORE30

AV5

VCCCORE32

AV7

VCCCORE33

AV10

VCCCORE29

AV27

VCCCORE31

AW5

VCCCORE39

AW6

VCCCORE40

AW7

VCCCORE41

AW8

VCCCORE42

AW9

VCCCORE43

AW10

VCCCORE34

BB9

RSVD3

BC24

RSVD4

AY9

RSVD1

BB24

RSVD2

WHISKEYLAKE-U_BGA1528

12 of 20

VCCCORE35
VCCCORE36
VCCCORE37
VCCCORE38
VCCCORE44
VCCCORE45
VCCCORE48
VCCCORE49
VCCCORE50
VCCCORE46
VCCCORE47
VCCCORE51
VCCCORE52
VCCCORE56
VCCCORE57
VCCCORE58
VCCCORE59
VCCCORE53
VCCCORE54
VCCCORE55
VCCCORE63
VCCCORE64
VCCCORE60
VCCCORE61
VCCCORE62
VCCCORE69
VCCCORE65
VCCCORE66
VCCCORE67
VCCCORE68
VCCCORE70
VCCCORE73
VCCCORE71
VCCCORE72
VCCCORE74

VCC_SENSE

VSS_SENSE

VIDALERT#

VIDSCK

VIDSOUT

RSVD5

VCCSTG1

AW24
AW25
AW26
AW27
AY24
AY26
BA5
BA7
BA8
BA25
BA27
BB2
BB26
BC5
BC6
BC7
BC9
BC10
BC26
BC27
BD5
BD8
BD10
BD25
BD27
BE9
BE24
BE25
BE26
BE27
BF2
BF9
BF24
BF26
BG27

AN6
AN5

AA3

AA1

AA2

Y3

BG3

+VCC_CORE +VCC_CORE

@

TP5

@

TP6

@

TP4305

@

TP4306

4

+VCC_CORE

12

R1603
100_0201_1%

R1601 0_04 02_SP

1 2

R1602 0_04 02_SP

1

1 2

TP4307

@

+VCC_STG

12

R1604
100_0201_1%

VR_SVID_ALRT#_R

VR_SVID_CLK

VR_SVID_DAT

[WHL PDG]Package Sensing Recommendations

1.Trace Length Match: <25mil

2.Space: >25mil

3.Trace impedance:50ohm

4.Sense traces should be referenced to a solid ground plane

5.Avoid crossing over plane splits

[WHL PDG]SVID

VIDALERT#, VIDSCLK, and VIDSCLK comprise a three signal serial synchronous
interface (SVID) used to transfer power management information between the Whiskey
Lake processor and the voltage regulator controllers. Alert signal must be routed
between Clk and Data signals to minimize Cross-Talk.

3

VCC_SENSE 87

VSS_SENSE 87

VR_SVID_CLK

VR_SVID_DAT

VR_SVID_ALRT#_R

2

R1608
220_0201_5%

Rs1

1 2

+VCC_ST

+VCC_ST

+VCC_ST

12

R1605
100_0201_1%

@

Rpu1

12

R1606
100_0201_1%

Rpu2

12

R1607
56_0201_5%

Rpu1

[SKL PDG]VIDSCK

[SKL PDG]VIDSOUT

[SKL PDG]VIDALERT#

VR_SVID_ALRT#

1

VR_SVID_CLK 87

VR_SVID_DAT 87

VR_SVID_ALRT# 87

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2015/01/12

2015/01/12

2015/01/12

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2016/01/12

2016/01/12

2016/01/12

2

Title

WHL(L)_PW-VCCCORE

WHL(L)_PW-VCCCORE

WHL(L)_PW-VCCCORE

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

FL490/FL590 NM-B931

FL490/FL590 NM-B931

FL490/FL590 NM-B931

Wednesday, March 13, 2019

Wednesday, March 13, 2019

Wednesday, March 13, 2019

Date: Sheet

Date: Sheet

Date: Sheet

1

of

of

of

16 99

16 99

16 99

0.3

0.3

0.3

5

www.teknisi-indonesia.com

+VCC_GT

+VCC_CORE

D D

+VCC_GT 2 7,89,91

+VCC_CORE 16 ,27,88,91

4

3

2

1

VCCGT58
VCCGT59
VCCGT60
VCCGT61
VCCGT64
VCCGT69
VCCGT70
VCCGT71
VCCGT72
VCCGT65
VCCGT66
VCCGT67
VCCGT68
VCCGT73
VCCGT74
VCCGT75
VCCGT76
VCCGT77
VCCGT78
VCCGT79
VCCGT87
VCCGT88
VCCGT89
VCCGT90
VCCGT80
VCCGT81
VCCGT82
VCCGT83
VCCGT84
VCCGT85
VCCGT86
VCCGT95
VCCGT96
VCCGT91
VCCGT92
VCCGT93
VCCGT94
VCCGT98

VCCGT97
VCCGT100
VCCGT101

VCCGT99
VCCGT102
VCCGT104
VCCGT105
VCCGT106
VCCGT103
VCCGT107
VCCGT108
VCCGT109
VCCGT111
VCCGT112
VCCGT110
VCCGT114
VCCGT113

VCCGT116
VCCGT117
VCCGT118

+VCC_GT

D15
D17
D18
D20
E4
F5
F6
F7
F8
F11
F14
F17
F20
G11
G12
G14
G15
G17
G18
G20
H5
H6
H7
H8
H11
H12
H14
H15
H17
H18
H20
J7
J8
J11
J14
J17
J20
K2
K11
L7
L8
L10
M9
N7
N8
N9
N10
P2
P8
R9
T8

+VCC_CORE

T9
T10
U8
U10
V2
V9
W8
W9
Y8

E3
D2

R1703 0_ 0402_SP
R1704 0_ 0402_SP

+VCC_GT

12

R1701

100_0402_ 1%

1 2
1 2

R1702

100_0402_ 1%

Security Classification LC Future Center Secret Data

Security Classification LC Future Center Secret Data

Security Classification LC Future Center Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUT URE CENT ER NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUT URE CENT ER NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUT URE CENT ER NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED T O ANY T HIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED T O ANY T HIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED T O ANY T HIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

12

Issued Date

Issued Date

Issued Date

VCCGT_SENSE 87
VSSGT_SENSE 87

2015/01/12

2015/01/12

2015/01/12

Deciphered Date

Deciphered Date

Deciphered Date

Title

Title

2016/01/12

2016/01/12

2016/01/12

2

Title

WHL(M)_PW-VCCGT

WHL(M)_PW-VCCGT

WHL(M)_PW-VCCGT

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

FL490/FL590 NM-B931

FL490/FL590 NM-B931

FL490/FL590 NM-B931

Wednesday, March 13, 2019

Wednesday, March 13, 2019

Wednesday, March 13, 2019

Date: Shee t

Date: Shee t

Date: Shee t

1

of

of

of

17 99

17 99

17 99

0.3

0.3

0.3

+VCC_GT

UC1M

A5

VCCGT8

A6

VCCGT9

A8

VCCGT10

A11

VCCGT1

A12

VCCGT2

A14

VCCGT3

4

A15

VCCGT4

A17

VCCGT5

A18

VCCGT6

A20

VCCGT7

AA9

VCCCORE75

AB2

VCCCORE76

AB8

VCCCORE77

AB9

VCCCORE78

AB10

VCCCORE79

AC8

VCCCORE80

AD9

VCCCORE81

AE8

VCCCORE82

AE9

VCCCORE83

AE10

VCCCORE84

AF2

VCCCORE85

AF8

VCCCORE86

AF10

VCCCORE87

AG8

VCCCORE88

AG9

VCCCORE89

AH9

VCCCORE90

AJ8

VCCCORE91

AJ10

VCCCORE92

AK2

VCCCORE93

AK9

VCCCORE94

AL8

VCCCORE95

AL9

VCCCORE96

AL10

VCCCORE97

AM8

VCCCORE98

B3

VCCGT39

B4

VCCGT40

B6

VCCGT41

B8

VCCGT42

B11

VCCGT35

B14

VCCGT36

B17

VCCGT37

B20

VCCGT38

C2

VCCGT49

C3

VCCGT51

C6

VCCGT52

C7

VCCGT53

C8

VCCGT54

C11

VCCGT43

C12

VCCGT44

C14

VCCGT45

C15

VCCGT46

C17

VCCGT47

C18

VCCGT48

C20

VCCGT50

D4

VCCGT62

D7

VCCGT63

D11

VCCGT55

D12

VCCGT56

D14

VCCGT57

Y10

VCCCORE99

WHISKEYLAKE-U_BGA15 28

13 of 20

VCCCORE100

VCCCORE101

VCCGT_SENSE
VSSGT_SENSE

C C

+VCC_CORE

+VCC_GT

575414_WHL_Bal lout List

B B

+VCC_CORE

A A

5

+1.2V 6,7,23,24,25,26,86

www.teknisi-indonesia.com

+VCC_IO 5,11,21,71

+VCC_SA 90,91

1

C1814
10U_0402_6.3V6-M

2

+VCC_STG +VCC_ST+VCC_SFROC+VCC_SFR

[WHL PDG]VCCST

[WHL PDG]1uF x1

Primary side cap

1

C1834

0.1U_0402_10V7-K

2

1

1

C1835

C27178
1U_0402_10V6-K

0.1U_0402_10V7-K

2

2

C2718 need to close CPU

5

1

C1815
10U_0402_6.3V6-M

2

TP4322

+VCC_STG

+VCC_STG 8,16,71

+VCC_ST

+VCC_ST 8,15,16,71,87

TOP

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11

RSVD1

VCCST1
VCCST2

VCCSTG1
VCCSTG2

VCCPLL_OC1
VCCPLL_OC2

VCCPLL1
VCCPLL2

[SKL PDG]VDDQC

[SKL PDG]10uF x1

+1.2V

1

C1836
10U_0402_6.3V6-M

2

14 of 20

1

C1817
10U_0402_6.3V6-M

2

VCCIO_SENSE
VSSIO_SENSE

VSSSA_SENSE
VCCSA_SENSE

1

1

C1818

C1819

10U_0402_6.3V6-M

10U_0402_6.3V6-M

2

2

@

+VCC_IO

AK24

VCCIO1

AK26

VCCIO2

AL24

VCCIO3

AL25

+VCC_SA

VCCIO4

AL26

VCCIO5

AL27

VCCIO6

AM25

VCCIO7

AM27

VCCIO8

BH24

VCCIO9

BH25

VCCIO10

BH26

VCCIO11

BH27

VCCIO12

BJ24

VCCIO13

BJ26

VCCIO14

BP16

VCCIO15

BP18

VCCIO16

BG8

VCCSA2

BG10

VCCSA1

BH9

VCCSA3

BJ8

VCCSA5

BJ9

VCCSA6

BJ10

VCCSA4

BK8

VCCSA9

BK25

VCCSA7

BK27

VCCSA8

BL8

VCCSA13

BL9

VCCSA14

BL10

VCCSA10

BL24

VCCSA11

BL26

VCCSA12

BM24

VCCSA15

BN25

VCCSA16

VCCIO_SENSE

BP28

VSSIO_SENSE

BP29

VSSSA_SENSE_L

BE7

VCCSA_SENSE_L

BG7

VCCIO_SENSE
VSSIO_SENSE

1 2

R1806 0_0201_SP

1 2

R1807 0_0201_SP

1

C1816
10U_0402_6.3V6-M

2

?

+1.2V

UC1N

AD36

AH32
AH36

AM36

AN32

AW32

AY36
BE32
BH36

R32
Y36

1

BC28

BP11

BP2

BG1
BG2

BL27

BM26

BR11

BT11

WHISKEYLAKE-U_BGA1528

+1.2V

+VCC_IO

+VCC_SA

D D

[WHL U4+2 Processor]VCCSA
[WHL U4+2 Processor]10uF x7

+VCC_SA

1

C1813
10U_0402_6.3V6-M

2

C C

[WHL PDG]VCCSTG

[WHL PDG]1uF x1

Primary side cap

+VCC_STG +VCC_ST

1

C1833

0.1U_0402_10V7-K

2

[WHL PDG]VCCPLL

[WHL PDG]1uF x1

Primary side cap

B B

+VCC_SFR

+VCC_ST

R1808
0_0402_SP

1 2

The following capacitors can be placed on as either Primary or back side cap.

4

[WHL U4+2 Processor]VCCSA
[WHL U4+2 Processor]10uF x6,47uF x2

BOTTOM

+VCC_SA +1.2V

1

C1803
10U_0402_6.3V6-M

2

1

1

C1837

C1838

10U_0402_6.3V6-M

10U_0402_6.3V6-M

2

2

@

+VCC_IO

12

R1801
100_0201_1%

12

R1802
100_0201_1%

VSSSA_SENSE 87

VCCSA_SENSE 87

VCCSA_SENSE
VSSSA_SENSE

CPU_C10_GATE#13,71

1

C1802
10U_0402_6.3V6-M

2

@

+VCC_SA

1

C1820
1U_0201_6.3V6-M

2

@

+VCC_SA

12

R1803
100_0201_1%

12

R1804
100_0201_1%

[WHL PDG]VCCPLL

[WHL PDG]1uF x1

Primary side cap

SYSON40,71,86,95

1

C1805
10U_0402_6.3V6-M

2

@

1

C1821
1U_0201_6.3V6-M

2

@

D1801

D1802

1

1

C1806

C1804

10U_0402_6.3V6-M

10U_0402_6.3V6-M

2

2

@

1

1

C1822

C1823

1U_0201_6.3V6-M

1U_0201_6.3V6-M

2

2

@

@

Power Rail

VCC

Processor IA Cores Power Rail

VccGT SVIDProcessor Graphics Power Rails

VccGTX Processor Graphics Extended Power Rail

Available only for GT3/GT4 processor SKUs

VccST Sustain Power Rail Fixed

VccPLL Processor PLLs power rail Fixed

VDDQ Integrated Memory Controller Power Rail Fixed

Processor OPC power rail (available only

VccOPC Fixed

in SKU’ s with OPC)

VccOPC_1P 8 Processor OPC power rail (available only

in SKU’ s with OPC)

VccEOPIO Processor OPC power rail (available only

in SKU’ s with OPC)

[WHL U4+2 Processor]VCCIO
[WHL U4+2 Processor]1uF x4

BOTTOM

+VCC_IO

1

C1809
1U_0201_6.3V6-M

2

+3VALW

12

R1821
10K_0402_5%

@

RB521CM-30T2R_VMN2M-2@

21

@

21

RB521CM-30T2R_VMN2M-2

1

C1810
1U_0201_6.3V6-M

2

1

C1807
10U_0402_6.3V6-M

2

1

C1824
1U_0201_6.3V6-M

2

@

Descriptio n

1

C1848
10U_6.3V_M_X5R_0402

2

1

C1811
1U_0201_6.3V6-M

2

1

C1839
22U_0603_6.3V6-M

2

@

1

C1825
1U_0201_6.3V6-M

2

@

R1809
0_0603_SP

1 2

U1801
TPS22971YZPT_DSBGA8

A2

VIN1

B2

VIN2

C2

CT

D2

ON

@

1

C1812
1U_0201_6.3V6-M

2

VOUT1

VOUT2

GND

3

1

C1840
22U_0603_6.3V6-M

2

@

1

2

@

PG

C1826
1U_0201_6.3V6-M

A1

B1

C1

D1

Control

SVID

SVID

SVIDSystem Agent Power RailVccSA

FixedIO Power RailV ccIO

Fixed

Fixed

+VCC_SFROC+1.2V

1

C1801
1U_0201_6.3V6-M

2

[WHL U4+2 Processor]VDDQ
[WHL U4+2 Processor]10uF x6, 22uF x1

BOTTOM

1

1

1

C27171
1U_0201_6.3V6-M

2

1

C27175
10U_0402_6.3V6-M

2

C1832
10U_0402_6.3V6-M

2

1

C1844
1U_0201_6.3V6-M

2

1

C27169
1U_0201_6.3V6-M

2

1

C27174
10U_0402_6.3V6-M

2

1

C1808
10U_0402_6.3V6-M

2

1

C1842
1U_0201_6.3V6-M

2

C1830
10U_0402_6.3V6-M

2

[WHL U4+2 Processor]VDDQ
[WHL U4+2 Processor]10uF x3, 1uF x4

TOP

+1.2V

1

C1841
1U_0201_6.3V6-M

2

[WHL U4+2 Processor]10uF x6 , 1uF x4

TOP

+VCC_IO

1

C27168
1U_0201_6.3V6-M

2

+VCC_IO

1

C27173
10U_0402_6.3V6-M

2

1

C27170
1U_0201_6.3V6-M

2

1

C27172
10U_0402_6.3V6-M

2

2

1

C1827
10U_0402_6.3V6-M

2

1

C1843
1U_0201_6.3V6-M

2

1

C27176
10U_0402_6.3V6-M

2

1

C1829
10U_0402_6.3V6-M

2

1

C1845
10U_0402_6.3V6-M

2

1

C27177
10U_0402_6.3V6-M

2

1

C1831
10U_0402_6.3V6-M

2

1

C1847
10U_0402_6.3V6-M

2

1

C1828
22U_0603_6.3V6-M

2

1

C1846
10U_0402_6.3V6-M

2

1

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2

2015/01/12

2015/01/12

2015/01/12

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2016/01/12

2016/01/12

2016/01/12

Title

WHL(N)_PW-VCCIO & VCCSA

WHL(N)_PW-VCCIO & VCCSA

WHL(N)_PW-VCCIO & VCCSA

Size

Size

Size

Document Number Rev

Document Number Rev

Document Number Rev

D

D

D

FL490/ FL590 NM-B931

FL490/ FL590 NM-B931

FL490/ FL590 NM-B931

Wednesday, March 13, 2019

Wednesday, March 13, 2019

Wednesday, March 13, 2019

Date: Sheet

Date: Sheet

Date: Sheet

1

18 99

18 99

18 99

of

of

of

0.3

0.3

0.3

5

www.teknisi-indonesia.com

+3VL

+3VL 40,52,63,65,66,80,82,83,84

+3VALW

+3VALW 6,9,10,12,13,15,18,39,40,41,43,45,46,49,52,58,60,62,63,65,66,67,71,72,83,84,85,96

+1.8VALW

+1.8VALW 9,10,38,40,49,62,65,94

+1.05VALW

+1.05VALW 21,39,71,96

+3VALW_PCH

+3VALW_PCH 5,8,9,10,11,12,13,15

D D

+3V_SPI

+VCC_HDA

+RTCVCC

+3V_SPI 9

+VCC_HDA 11

+RTCVCC 14,15

4

3

2

1

+1.05VALW

?

UC1P

BP20

VCCPRIM_1P051

BW16

VCCPRIM_1P059

BW18

VCCPRIM_1P0510

BW19

VCCPRIM_1P0511

BY16

+VCCPRIM_1P8

+VCCPRIM_3P3

+1.05VALW

C C

+1.05VALW

+VCCDSW_GPIO

+VCC_HDA

+3V_SPI

+1.05VALW

+VCCMPHYGTAON_1P05

B B

+1.8VALW_PCH

+VCC_HDA

R1912

1 2

@

0_0402_5%

+3VALW_PCH

R1913

0_0402_SP

1 2

1

C1918

Close to BT20

A A

2

0.1U_0402_10V6-K

5

+1.05VALW

L1901 MMZ0603AFY560VT_2P

[WHL PDG]VCCP RIM_3P3

[WHL PDG]Close C P29
[WHL PDG] 1uF x1 an d 0.1uF x 1

+3VALW_PCH

R1905
0_0402_SP

1 2

[WHL PDG]VC CA_XTAL_1P05

[WHL PDG]Close C P5
[WHL PD G]1uF x1

1 2

@

R1908

12

0_0603_SP

+VCCPRIM_3P3

2

C1910

C1909

1

1U_0402_6.3V6-K

1

C1902

2

47U_0603_6.3V6-M

@

1

2

0.1U_0402_10V6-K

+1.05VALW

+VCCA_XTAL_1P05

+3VALW_PCH

+VCCMPHYGTAON_1P05

+VCCAMPHYPLL_1P05

2

1

C1903

1U_0402_6.3V6-K

[WHL PDG]VCCD SW_GPIO

[WHL PDG]Close B R24
[WHL PD G]1uF x1

+3VL

+VCCDSW_1P05

+1.05VALW

20180918
Change to +1.05VALW for modify power plane

+VCCDSW_GPIO

R1906
0_0402_SP

1 2

R1914

@

1 2

0_0402_5%

2

C1911

1

1U_0402_6.3V6-K

[WHL PDG]VCCP RIM_1P05

[WHL PDG]Close B P20
[WHL PD G]1uF x1

+1.05VALW

2

C1901

1

1U_0402_6.3V6-K

[WHL PDG]VCCRTC

[WHL PDG]Close B R23
[WHL PDG] 1uF x1 an d 0.1uF x 1

4

VCCPRIM_1P0512

CA14

VCCPRIM_1P0514

CC15

VCCPRIM_1P81

CD15

VCCPRIM_1P84

CD16

VCCPRIM_1P85

CP17

VCCPRIM_1P88

CB22

VCCPRIM_3P34

CB23

VCCPRIM_3P35

CC22

VCCPRIM_3P36

CC23

VCCPRIM_3P37

CD22

VCCPRIM_3P38

CD23

VCCPRIM_3P39

CP29

VCCPRIM_3P310

BU15

VCCPRIM_CORE1

BU22

VCCPRIM_CORE2

BV15

VCCPRIM_CORE3

BV16

VCCPRIM_CORE4

BV18

VCCPRIM_CORE5

BV19

VCCPRIM_CORE6

BV20

VCCPRIM_CORE7

BV22

VCCPRIM_CORE8

BW20

VCCPRIM_CORE9

BW22

VCCPRIM_CORE10

CA12

VCCPRIM_CORE11

CA16

VCCPRIM_CORE12

CA18

VCCPRIM_CORE13

CA19

VCCPRIM_CORE14

CA20

VCCPRIM_CORE15

CB12

VCCPRIM_CORE16

CB14

VCCPRIM_CORE17

CB15

VCCPRIM_CORE18

BT24

VCCDSW_1P05

BU14

VCCAPLL_1P054

BV12

VCCPRIM_MPHY_1P051

BW12

VCCPRIM_MPHY_1P053

BW14

VCCPRIM_MPHY_1P054

BY12

VCCPRIM_MPHY_1P055

BY14

VCCPRIM_MPHY_1P056

BV2

VCCAMPHYPLL_1P05

BR15

VCCAPLL_1P052

CC12

VCCDUSB_1P05

BR24

VCCDSW_3P31

BT20

VCCHDA

BV23

VCCSPI

BT18

VCCPRIM_1P054

BT19

VCCPRIM_1P055

BU18

VCCPRIM_1P057

BU19

VCCPRIM_1P058

BT22

VCCPRIM_1P056

BP22

VCCPRIM_1P052

BV14

VCCPRIM_MPHY_1P052

WHISKEYLAKE-U_BGA1528

+RTCVCC

2

1

16 of 20

+1.05VALW

1

C1913

C1912

2

1U_0402_6.3V6-K

0.1U_0402_10V6-K

+VCCPRIM_3P3

+RTCVCC

+1.05VALW

+VCCRTCEXT

+1.05VALW

CB16

VCCPRIM_3P33

BR23

VCCRTC

BY20

VCCPRIM_1P0513

BP24

DCPRTC

BR20

VCCPRIM_1P053

BT12

VCCAPLL_1P053

BP14

VCCA_BCLK_1P05

BR14

VCCAPLL_1P051

BU12

VCCA_SRC_1P05

CP5

VCCA_XTAL_1P05

BY24

VCCDPHY_1P242

CA24

VCCDPHY_1P244

BY23

VCCDPHY_1P241

CA23

VCCDPHY_1P243

CP25

VCCDPHY_EC_1P24

BT23

VCCDSW_3P32

BR12

VCCA_19P2_1P05

CC18

VCCPRIM_1P82

CC19

VCCPRIM_1P83

CD18

VCCPRIM_1P86

CD19

VCCPRIM_1P87

CP23

VCCPRIM_1P89

BW23

VCCPRIM_3P32

BP23

VCCPRIM_3P31

CB36

GPP_B0/CORE_VID0

CB35

GPP_B1/CORE_VID1

[WHL P DG]VCCMPHYGTAON_1P05

[WHL PDG]Close B V12 [WHL PDG]Close B V2

[WHL PDG]22uF x1

+VCCMPHYGTAON_1P05

R1902
0_0402_SP

1 2

1

C1917
22U_0603_6.3V6-M

2

[WHL PDG]VCCD SW_1P05

[WHL PDG]Close B T24 [WHL PDG] Close BP24
[WHL PD G]1uF x1

+VCCDSW_1P05 +VCCRTCEXT +VCCDPHY_EC_1P24

2

C1916

1

1U_0402_6.3V6-K

+1.05VALW

+VCCA_XTAL_1P05

+VCCDPHY_1P24

+VCCDPHY_EC_1P24

+VCCDSW_GPIO

+1.05VALW

+VCCPRIM_1P8

+VCCPRIM_3P3

[WHL PDG ]VCCAMPHYPLL_1P05

[WHL PD G]1uF x1

+1.05VALW

1 2

L1902 MMZ0603AFY560VT_2P

@

R1910

12

0_0603_SP

[WHL PDG]VCCRTCE XT [W HL PDG] VCCDPHY_1P24

[WHL PD G]1uF x1

3

2

C1915

1

1U_0402_6.3V6-K

+VCCAMPHYPLL_1P05

2

1

C1904

C1905

1

2

47U_0603_6.3V6-M

1U_0402_6.3V6-K

@

20180918
Change to +1.05VALW for modify power plane

[WHL PDG]VCCP RIM_CORE

[WHL PDG]Close B V18
[WHL PD G]1uF x1

+1.05VALW

[WHL PDG]Close C P25
[WHL PDG]4.7uF x1

2

C1906

1

2

C1914

4.7U_0402_6.3V6-M

1

[WHL PDG]VCCP RIM_1P8

[WHL PD G]Close CP17 and CP2 3
[WHL PD G]1uF x2

+1.8VALW_PCH

+VCCPRIM_1P8

R1904
0_0402_SP

1 2

2

2

C1907

C1908

1

1

1U_0402_6.3V6-K

1U_0402_6.3V6-K

+3VALW

R1907

0_0603_SP

+1.8VALW

R1909

0_0603_SP

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2

1U_0402_6.3V6-K

+3VALW_PCH

12

+1.8VALW_PCH

12

Title

Title

2015/01/12

2015/01/12

2015/01/12

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2016/01/12

2016/01/12

2016/01/12

Title

WHL(O)_PW-OTHERS

WHL(O)_PW-OTHERS

WHL(O)_PW-OTHERS

Size

Size

Size

Document Number Rev

Document Number Rev

Document Number Rev

Custom

Custom

Custom

FL490/ FL590 NM-B931

FL490/ FL590 NM-B931

FL490/ FL590 NM-B931

Wednesday, March 13, 2019

Wednesday, March 13, 2019

Wednesday, March 13, 2019

Date: Sheet

Date: Sheet

Date: Sheet

1

19 99

19 99

19 99

of

of

of

0.3

0.3

0.3

5

www.teknisi-indonesia.com

D D

C C

B B

A A

5

?

UC1R

CR34

VSS_1

BT5

VSS_2

BY5

VSS_3

CP35

VSS_4

CM37

VSS_5

CK37

VSS_6

AW1

VSS_7

CM1

VSS_8

BD6

VSS_9

AY4

VSS_10

B34

VSS_11

E35

VSS_12

A4

VSS_13

AE24

VSS_14

AE26

VSS_15

AF25

VSS_16

AG24

VSS_17

AG26

VSS_18

AH24

VSS_19

AH25

VSS_20

B2

VSS_21

B36

VSS_22

C36

VSS_23

C37

VSS_24

CN1

VSS_25

CN2

VSS_26

CN37

VSS_27

CP2

VSS_28

D1

VSS_29

A32

VSS_30

F33

VSS_31

A3

VSS_32

BJ7

VSS_33

CJ36

VSS_34

A36

VSS_35

BK10

VSS_36

CJ4

VSS_37

AB27

VSS_38

BK2

VSS_39

CK1

VSS_40

AB3

VSS_41

BK28

VSS_42

AB30

VSS_43

BK3

VSS_44

CK4

VSS_45

AB33

VSS_46

BK33

VSS_47

CK7

VSS_48

AB36

VSS_49

BK4

VSS_50

CL2

VSS_51

AB4

VSS_52

BK7

VSS_53

CM13

VSS_54

AB7

VSS_55

BL25

VSS_56

CM17

VSS_57

AC10

VSS_58

BL28

VSS_59

CM21

VSS_60

AC27

VSS_61

BL29

VSS_62

CM25

VSS_63

AC30

VSS_64

BL30

VSS_65

CM29

VSS_66

BL31

VSS_67

CM31

VSS_68

AD33

VSS_69

BL32

VSS_70

CM33

VSS_71

AD35

VSS_72

17 of 20

WHISKEYLAKE-U_BGA1528

VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98

VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144

BL7
AE25
BM33
CM5
AE27
BM35
CM9
AE30
BM36
CN13
AE7
BM9
CN17
AF27
BN30
CN21
AF3
BN7
CN25
AF30
CN29
AF33
BP15
AF36
AF4
CN5
AF7
BP25
CN9
AG10
BP3
CP1
BP32
CP11
AH27
BP33
CP13
AH28
BP4
CP15
AH29
BP7
CP19
AH30
CP21
AH31
BR19
CP27
AH33
BR25
AH35
CP37
AJ25
BT15
AJ28
BT16
CP9
AJ7
CR2
AK3
CR36
AK33
D21
AK36
BT25
D25
AK4
BT28
AL28
BT33
D5
AL29

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

4

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

?

UC1S

BT35

VSS_145

D6

VSS_146

AL32

VSS_147

BT36

VSS_148

D8

VSS_149

AL7

VSS_150

D9

VSS_151

AM10

VSS_152

BU11

VSS_153

E23

VSS_154

AM28

VSS_155

E27

VSS_156

AM33

VSS_157

BU23

VSS_158

E29

VSS_159

AM35

VSS_160

BU24

VSS_161

E31

VSS_162

BU25

VSS_163

E33

VSS_164

AN25

VSS_165

BU7

VSS_166

E9

VSS_167

AN28

VSS_168

BV11

VSS_169

F12

VSS_170

AN29

VSS_171

F15

VSS_172

AN30

VSS_173

F18

VSS_174

AN31

VSS_175

BV3

VSS_176

F2

VSS_177

AN7

VSS_178

BV31

VSS_179

F21

VSS_180

AN8

VSS_181

BV33

VSS_182

F24

VSS_183

BV4

VSS_184

F3

VSS_185

AP3

VSS_186

BW11

VSS_187

F4

VSS_188

AP33

VSS_189

BW15

VSS_190

G21

VSS_191

AP36

VSS_192

G27

VSS_193

AP4

VSS_194

G33

VSS_195

AR28

VSS_196

G35

VSS_197

G36

VSS_198

AT33

VSS_199

BW24

VSS_200

G9

VSS_201

AT35

VSS_202

H21

VSS_203

AT36

VSS_204

BW7

VSS_205

H27

VSS_206

AT4

VSS_207

BY11

VSS_208

AU10

VSS_209

BY15

VSS_210

H9

VSS_211

AU28

VSS_212

BY22

VSS_213

J12

VSS_214

AU29

VSS_215

J15

VSS_216

18 of 20

WHISKEYLAKE-U_BGA1528

2015/01/12

2015/01/12

2015/01/12

3

BY25

VSS_217

J18

VSS_218

AU32

VSS_219

BY28

VSS_220

J21

VSS_221

AV25

VSS_222

BY33

VSS_223

J24

VSS_224

AV28

VSS_225

BY35

VSS_226

J33

VSS_227

AV3

VSS_228

BY36

VSS_229

J36

VSS_230

AV33

VSS_231

J6

VSS_232

AV36

VSS_233

C1

VSS_234

K21

VSS_235

AV4

VSS_236

C21

VSS_237

K22

VSS_238

AV6

VSS_239

C25

VSS_240

K24

VSS_241

AV8

VSS_242

C29

VSS_243

K25

VSS_244

AW28

VSS_245

C33

VSS_246

K27

VSS_247

AW29

VSS_248

C4

VSS_249

K28

VSS_250

AW3

VSS_251

C9

VSS_252

K29

VSS_253

AW30

VSS_254

CA11

VSS_255

K3

VSS_256

AW31

VSS_257

CA15

VSS_258

K30

VSS_259

AY33

VSS_260

CA22

VSS_261

K31

VSS_262

AY35

VSS_263

K32

VSS_264

B12

VSS_265

K4

VSS_266

B15

VSS_267

CA25

VSS_268

K9

VSS_269

B18

VSS_270

CB11

VSS_271

L27

VSS_272

B21

VSS_273

L33

VSS_274

B23

VSS_275

L35

VSS_276

B25

VSS_277

CB18

VSS_278

L36

VSS_279

B27

VSS_280

CB19

VSS_281

L6

VSS_282

B29

VSS_283

CB2

VSS_284

N25

VSS_285

B31

VSS_286

CB20

VSS_287

N27

VSS_288

CB25

VSS_289

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

3

Deciphered Date

Deciphered Date

Deciphered Date

2016/01/12

2016/01/12

2016/01/12

?

2

UC1T

N6

VSS_290

B37

VSS_291

CB3

VSS_292

P10

VSS_293

B5

VSS_294

CB33

VSS_295

P3

VSS_296

B7

VSS_297

CB4

VSS_298

P33

VSS_299

B9

VSS_300

CB7

VSS_301

P36

VSS_302

BA10

VSS_303

CC11

VSS_304

P4

VSS_305

BA28

VSS_306

P7

VSS_307

BA3

VSS_308

CC20

VSS_309

R27

VSS_310

BB3

VSS_311

CC25

VSS_312

R28

VSS_313

BB33

VSS_314

CC28

VSS_315

R29

VSS_316

BB36

VSS_317

CC31

VSS_318

R30

VSS_319

BB4

VSS_320

CC7

VSS_321

R31

VSS_322

BC25

VSS_323

CD11

VSS_324

T27

VSS_325

CD12

VSS_326

T30

VSS_327

BC29

VSS_328

CD14

VSS_329

T33

VSS_330

T35

VSS_331

BC32

VSS_332

CD24

VSS_333

T36

VSS_334

CD25

VSS_335

T7

VSS_336

BC8

VSS_337

CE33

VSS_338

U26

VSS_339

BD28

VSS_340

CE35

VSS_341

U7

VSS_342

BD33

VSS_343

CE36

VSS_344

V26

VSS_345

BD35

VSS_346

CE7

VSS_347

V27

VSS_348

BD36

VSS_349

CF11

VSS_350

V3

VSS_351

BE10

VSS_352

CF14

VSS_353

V30

VSS_354

BE28

VSS_355

CF19

VSS_356

V33

VSS_357

BE29

VSS_358

CF2

VSS_359

V36

VSS_360

BE3

VSS_361

19 of 20

WHISKEYLAKE-U_BGA1528

2

1

CF23

VSS_362

V4

VSS_363

BE30

VSS_364

CF28

VSS_365

W10

VSS_366

BE31

VSS_367

CF3

VSS_368

W27

VSS_369

CF4

VSS_370

W30

VSS_371

BF3

VSS_372

CG33

VSS_373

W7

VSS_374

BF33

VSS_375

CG7

VSS_376

BF36

VSS_377

Y26

VSS_378

BF4

VSS_379

CH31

VSS_380

Y27

VSS_381

BG25

VSS_382

Y30

VSS_383

BG28

VSS_384

CJ11

VSS_385

Y33

VSS_386

CJ14

VSS_387

Y35

VSS_388

BH28

VSS_389

CJ19

VSS_390

Y7

VSS_391

BH29

VSS_392

CJ23

VSS_393

BH32

VSS_394

CJ28

VSS_395

BH33

VSS_396

CJ33

VSS_397

BH35

VSS_398

CJ35

VSS_399

BP19

VSS_400

BR16

VSS_401

BY18

VSS_402

BY19

VSS_403

CC16

VSS_404

BU16

VSS_405

CC14

VSS_406

BR22

VSS_407

BU20

VSS_408

CD20

VSS_409

BT14

VSS_410

BP12

VSS_411

CB24

VSS_412

CC24

VSS_413

J5

VSS_414

U24

VSS_415

BD7

VSS_416

AR4

VSS_417

AU4

VSS_418

AW4

VSS_419

BA6

VSS_420

BC4

VSS_421

BE4

VSS_422

BE8

VSS_423

BA4

VSS_424

BD4

VSS_425

BG4

VSS_426

CJ2

VSS_427

CJ3

VSS_428

AM5

VSS_429

CM4

VSS_430

AC5

VSS_431

AG5

VSS_432

CR6

VSS_433

Titl e

Titl e

Titl e

WHL(P/Q/R)_VSS

WHL(P/Q/R)_VSS

WHL(P/Q/R)_VSS

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

B

B

B

Date: Sheet of

Date: Sheet of

Date: Sheet of

FL490/FL590 NM-B931

FL490/FL590 NM-B931

FL490/FL590 NM-B931

Wednesday, March 13, 2019

Wednesday, March 13, 2019

Wednesday, March 13, 2019

1

20 99

20 99

20 99

0.3

0.3

0.3

5

www.teknisi-indonesia.com

+1.05VALW

+VCC_IO

D D

C C

B B

A A

+1.05VALW 1 9,39,71,96

+VCC_IO 5 ,11,18,71

+VCC_IO +VCC_IO

CFG0
[SKL EDS]

12

R2101

L:Stall.

1K_0402_5%

*H:(Default) Normal

@

Operation; No stall.

CFG0 CFG4

12

R2102
1K_0402_1%

@

[SKL CRB]

[SKL PDG]Route
HOOK[6] to
Skylak e
ITP_PM ODE.
Termina tion:
Resistor value
from 1K ohm to 3K
ohm pull up to
PCH_V1.0A Rail.

R2105 49.9_0402_1%

12

12

12

TP24@
TP26@

TP74@
TP30@

TP86@
TP85@

TP88@
TP87@

TP90@
TP89@

TP32@
TP91@

TP92@

TP93@
TP94@

TP95@
TP96@

CFG4

*L: Embedded DisplayPort Enabled
H: Embedded DisplayPort Disabled

R2103
1K_0402_5%

@

R2104
1K_0402_1%

CFG0

CFG3
CFG4

CFG_RCOMP

ITP_PMODE

1
1

1
1

1
1

1
1

1
1

1
1

1

1
1

1
1

?

UC1Q

T4

CFG_0

R4

CFG_1

T3

CFG_2

R3

CFG_3

J4

CFG_4

M4

CFG_5

J3

CFG_6

M3

CFG_7

R2

CFG_8

N2

CFG_9

R1

CFG_10

N1

CFG_11

J2

CFG_12

L2

CFG_13

J1

CFG_14

L1

CFG_15

L3

CFG_16

N3

CFG_18

L4

CFG_17

N4

CFG_19

AB5

CFG_RCOMP

W4

ITP_PMODE

CG2

RSVD25

CG1

RSVD24

H4

RSVD34

H3

RSVD33

BV24

RSVD22

BV25

RSVD23

G3

RSVD69

G4

RSVD70

BK36

RSVD17

BK35

RSVD16

W3

RSVD35

AM4

RSVD7

AM3

RSVD71

A35

RSVD1

D34

RSVD30

G2

RSVD32

G1

RSVD31

WHISKEYLAKE-U_BGA1528

4

CFG3

PHYSICAL_DEBUG_ENABLED (DFX PRIVACY)
0 : ENABLED
SET DFX ENABLED BIT IN DEBUG INTERFACE MSR
1 : DISABLED

CFG3

12

R2108
1K_0402_1%

@

F37

RSVD_TP5

F34

RSVD_TP4

CP36

IST_TRIG

CN36

RSVD_TP3

BJ36

RSVD72

BJ34

RSVD73

BK34

TP1

BR18

TP3

BT9

RSVD74

BT8

RSVD75

BP8

RSVD76

BP9

RSVD77

CR4

RSVD29

CP3

RSVD26

CR3

RSVD27

AU3

RSVD78

AT3

RSVD79

AN1

RSVD8

AN2

RSVD9

AN4

RSVD11

AN3

RSVD10

AL2

RSVD80

AL1

RSVD81

AL4

RSVD82

AL3

RSVD83

BP34

TP2

BP36

VSS_392

BP35

TP5

C34

RSVD68

A34

RSVD_TP1

B35

RSVD67

CR35

RSVD84

AH26

RSVD66

AJ27

RSVD85

E1

SKTOCC#

20 of 20

3

+1.05VALW

R2106

1.5K_0402_5%

1 2

12

R2110
1K_0402_1%

@

TP37 @

1

TP39 @

1

TP936 @

1

TP97 @

1

TP43 @

1

TP45 @

1

TP49 @

1

TP51 @

1

TP59 @

1

TP60 @

1

TP22 @

1

TP23 @

1

TP25 @

1

TP27 @

1

TP64 @

1

TP66 @

1

TP29 @

1

TP31 @

1

TP33 @

1

TP34 @

1

TP35 @

1

TP67 @

1

TP68 @

1

TP54 @

1

TP927 @

1

TP928 @

1

1

1

1
1

1

1
1

TP929 @

TP930 @

TP931 @
TP932 @

TP933 @

TP934 @
TP935 @

R2107 0_04 02_SP

R2109 0_04 02_SP

DFXTESTMOD E

ITP_PMODE

HIGH - DFXTESTMODE DISABLED(DEFAULT)
LOW - DFXTESTMODE ENABLED
WEAK INTERNAL PU

1 2

1 2

2

1

TABLE

CFG0 : Stall Reset S equence
after P CU PLL Lock until de-asserted

1 : No Stall
0 : Stall

CFG4 : eDP Enable

1 : Disabled
0 : Enabled

CFG9 : SVID Bus Communication
1 : Enabled
0 : Disabled

[SKL EDS]Zero Voltage Mode:VCCOPC is fixed OPC VR output voltage of 1V, the
processor can drive VR to LPM (Low Power Mode) which sets VR output to 0V using
ZVM# signal as shown below:

ZVM# state

[SKL EDS]Minimum Speed Mode: VCCEOPIO can be connected to OPC VR in this
case VCCEOPIO is fixed to 1V. The processor can drive VR to LPM (Low Power
Mode) which sets VR output to 0V using ZVM# signal .
In order to achieve better power/performance it is recommended to use a
separate VR for VCCEOPIO in this case VCCEOPIO is configurable to 0.8V/1V.
The processor drives the VR to set VCCEOPIO value(0.8V/1V) using MSM#
signal, based on the required bandwidth for the EOPIO interface as shown
below:

ZVM# state

VCCOPC

0V

0V

1V

1V

MSM# state

0V

1V

1V

VCCEOPIO

X

0V

1V 1V

0V

0.8V

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2015/01/12

2015/01/12

2015/01/12

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2016/01/12

2016/01/12

2016/01/12

2

Title

WHL(S)_CFG/ RSVD

WHL(S)_CFG/ RSVD

WHL(S)_CFG/ RSVD

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

FL490/FL590 NM-B931

FL490/FL590 NM-B931

FL490/FL590 NM-B931

Wednesday, March 13, 2019

Wednesday, March 13, 2019

Wednesday, March 13, 2019

Date: Sheet

Date: Sheet

Date: Sheet

1

of

of

of

21 99

21 99

21 99

0.3

0.3

0.3

5

www.teknisi-indonesia.com

D D

TP98@

C C

TP99@
TP100@
TP101@
TP103@
TP104@
TP105@
TP4311@
TP4312@
TP4313@
TP4314@
TP4308@
TP4309@
TP4310@

TP4316@
TP4317@

TP4318@
TP4319@

4

?

1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1

1
1

UC1O

K12

RSVD46

K14

RSVD47

K15

RSVD48

K17

RSVD49

K18

RSVD50

K20

RSVD51

L25

RSVD52

M24

RSVD53

M26

RSVD54

P24

RSVD55

P26

RSVD56

R24

RSVD57

R25

RSVD58

R26

RSVD59

W25

RSVD60

V24

RSVD61

Y25

RSVD62

Y24

RSVD63

3

RSVD38
RSVD39
RSVD40
RSVD41
RSVD42
RSVD43
RSVD44
RSVD45

RSVD64
RSVD65

AA24
AA26
AB25
AC24
AC25
AC26
AD24
AD26

V25
T25

2

1

TP106 @

1

TP108 @

1

TP109 @

1

TP110 @

1

TP111 @

1

TP112 @

1

TP113 @

1

TP4315 @

1

TP4321 @

1

TP4320 @

1

B B

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

5

4

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

15 of 20

WHISKEYLAKE-U_BGA1528

2015/01/12

2015/01/12

2015/01/12

3

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2016/01/12

2016/01/12

2016/01/12

Titl e

Titl e

Titl e

WHL(T)_RSVD

WHL(T)_RSVD

WHL(T)_RSVD

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

B

B

B

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

FL490/FL590 NM-B931

FL490/FL590 NM-B931

FL490/FL590 NM-B931

Wednesday, March 13, 2019

Wednesday, March 13, 2019

Wednesday, March 13, 2019

1

22 99

22 99

22 99

0.3

0.3

0.3

+3VS

www.teknisi-indonesia.com

+2.5V

+1.2V

+0.6VS

D D

C C

B B

A A

5

+3VS 5,9,10,11,12,14,15,25,30,32,37,39,40,42,49,50,51,55,56,57,58,59,60,61,62,63,65,66,72,82,86,87

+2.5V 6,24,25,26,95

+1.2V 6,7,18,24,25,26,86

+0.6VS 24,25,26,86

+1.2V +1.2V

JDIMM1A

M_A_DQ1

M_A_DQ0

-M_A_DQS0
M_A_DQS0

M_A_DQ6

M_A_DQ2

M_A_DQ24

M_A_DQ25

M_A_DQ26

M_A_DQ31

M_A_DQ9

M_A_DQ13

-M_A_DQS1
M_A_DQS1

M_A_DQ10

M_A_DQ11

M_A_DQ21

M_A_DQ20

M_A_DQ18

M_A_DQ22

M_A_CKE0

M_A_CKE06

M_A_BG1

M_A_BG16

M_A_BG0

M_A_BG06

M_A_A12
M_A_A9

M_A_A8
M_A_A6

M_A_VREF_CA_CPU6

1

VSS_1

3

DQ5

5

VSS_3

7

DQ1

9

VSS_5

11

DQS0_C

13

DQS0_t

15

VSS_8

17

DQ7

19

VSS_10

21

DQ3

23

VSS_12

25

DQ13

27

VSS_14

29

DQ9

31

VSS_16

33

DM1_n/DBl_n

35

VSS_17

37

DQ15

39

VSS_19

41

DQ10

43

VSS_21

45

DQ21

47

VSS_23

49

DQ17

51

VSS_25

53

DQS2_c

55

DQS2_t

57

VSS_28

59

DQ23

61

VSS_30

63

DQ19

65

VSS_32

67

DQ29

69

VSS_34

71

DQ25

73

VSS_36

75

DM3_n/DBl3_n

77

VSS_37

79

DQ30

81

VSS_39

83

DQ26

85

VSS_41

87

CB5/NC

89

VSS_43

91

CB1/NC

93

VSS_45

95

DQS8_c

97

DQS8_t

99

VSS_48

101

CB2/NC

103

VSS_50

105

CB3/NC

107

VSS_52

109

CKE0

111

VDD_1

113

BG1

115

BG0

117

VDD_3

119

A12

121

A9

123

VDD_5

125

A8

127

A6

129

VDD_7

ARGOS_D4AR0-26005-1P40

ME@

1

C2305

0.022U_0402_25V7-K

2

12

R2311

24.9_0402_1%

DM8_n/DBl_n/NC

R2310
2_0402_1%

1 2

DM0_n/DBl0_n

DM2_n/DBl2_n

VSS_2

VSS_4

VSS_6

VSS_7

VSS_9

VSS_11

VSS_13

VSS_15
DQS1_c
DQS1_t
VSS_18

VSS_20

VSS_22

VSS_24

VSS_26

VSS_27

VSS_29

VSS_31

VSS_33

VSS_35
DQS3_c
DQS3_t
VSS_38

VSS_40

VSS_42
CB4/NC
VSS_44
CB0/NC
VSS_46

VSS_47
CB6/NC
VSS_49
CB7/NC
VSS_51

RESET_n

VDD_2

ACT_n

ALERT_n

VDD_4

VDD_6

VDD_8

2
4

DQ4

6
8

DQ0

10
12
14
16

DQ6

18
20

DQ2

22
24

DQ12

26
28

DQ8

30
32
34
36
38

DQ14

40
42

DQ11

44
46

DQ20

48
50

DQ16

52
54
56
58

DQ22

60
62

DQ18

64
66

DQ28

68
70

DQ24

72
74
76
78
80

DQ31

82
84

DQ27

86
88
90
92
94
96
98
100
102
104
106
108
110

CKE1

112
114
116
118
120

A11

122

A7

124
126

A5

128

A4

130

+1.2V

12

R2309
1K_0402_1%

12

R2312
1K_0402_1%

4

M_A_DQ4

M_A_DQ5

M_A_DQ3

M_A_DQ7

M_A_DQ29

M_A_DQ28

-M_A_DQS3
M_A_DQS3

M_A_DQ27

M_A_DQ30

M_A_DQ8

M_A_DQ12

M_A_DQ15

M_A_DQ14

M_A_DQ17

M_A_DQ16

-M_A_DQS2
M_A_DQS2

M_A_DQ19

M_A_DQ23

-DRAMRST
M_A_CKE1

-M_A_ACT

-M_A_ALERT

12

C2307

0.1U_0402_16V7-K

EMC_NS@

M_VREF_CA_DIMMA SA0_CHA_P SA1_CHA_P SA2_CHA_P

12

C2306

0.1U_0402_16V7-K

@

M_A_A11
M_A_A7

M_A_A5
M_A_A4

M_A_DQ[63:0]6,7

-M_A_DQS[7:0]6,7

M_A_DQS[7:0]6,7

M_A_A[16:0]6

-DRAMRST 7,25
M_A_CKE1 6

-M_A_ACT 6

-M_A_ALERT 6

[WHL PDG]VDDSPD

[WHL PDG] EE 0.1uF x2,

2.2uF x2.

Place
decoupling cap
close to DIMM

+3VS +3VS+3VS

12

R2303
10K_0402_5%

@

12

R2304
0_0402_SP

3

M_A_A3
M_A_A1

M_A_DDRCLK0_1066M6

-M_A_DDRCLK0_1066M6

+3VS

12

R2302
0_0402_SP

12

R2305
10K_0402_5%

@

12

R2306
0_0402_SP

M_A_DDRCLK0_1066M

-M_A_DDRCLK0_1066M

M_A_PARITY M_A_A0

M_A_PARITY6

M_A_BS1

M_A_BS16

-M_A_CS0

-M_A_CS06

M_A_A14

M_A_ODT0

M_A_ODT06

-M_A_CS1

-M_A_CS16

M_A_ODT1

M_A_ODT16

PM_SMB_CLK9,25,65 PM_SMB_DAT 9,25,65

1

C2303

0.1U_0402_10V7-K

2

12

R2307
10K_0402_5%

@

12

R2308
0_0402_SP

M_A_DQ48

M_A_DQ49

-M_A_DQS6
M_A_DQS6

M_A_DQ54

M_A_DQ55

M_A_DQ32

M_A_DQ36

M_A_DQ35

M_A_DQ38

M_A_DQ40

M_A_DQ43

-M_A_DQS5
M_A_DQS5

M_A_DQ47

M_A_DQ42

M_A_DQ56

M_A_DQ57

M_A_DQ63

M_A_DQ62

PM_SMB_CLK
VDDSPD_1

1

C2304

2.2U_0402_10V6-K

2

2

M_A_A2

M_A_DDRCLK1_1066M

-M_A_DDRCLK1_1066M

M_A_A10

M_A_BS0
M_A_A16

M_A_A15
M_A_A13

M_A_DQ51

M_A_DQ52

M_A_DQ50

M_A_DQ53

M_A_DQ33

M_A_DQ37

-M_A_DQS4
M_A_DQS4

M_A_DQ39

M_A_DQ34

M_A_DQ44

M_A_DQ45

M_A_DQ41

M_A_DQ46

M_A_DQ61

M_A_DQ60

-M_A_DQS7
M_A_DQS7

M_A_DQ58

M_A_DQ59

RF

+1.2V

1 2

+1.2V

+1.2V

+1.2V+2.5V

+1.2V

131
133
135
137
139
141
143

145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
205
207
209
211
213
215
217
219
221
223
225
227
229
231
233
235
237
239
241
243
245
247
249
251
253
255
257
259

261

JDIMM1B

A3
A1
VDD_9
CK0_t
CK0_c
VDD_11
Parity

BA1
VDD_13
CS0_n
A14/WE_n
VDD_15
ODT0
CS1_n
VDD_17
ODT1
VDD_19
C1/CS3_n/NC
VSS_53
DQ37
VSS_55
DQ33
VSS_57
DQS4_c
DQS4_t
VSS_60
DQ38
VSS_62
DQ34
VSS_64
DQ44
VSS_66
DQ40
VSS_68
DM5_n/DBl5_n
VSS_69
DQ46
VSS_71
DQ42
VSS_73
DQ52
VSS_75
DQ49
VSS_77
DQS6_c
DQS6_t
VSS_80
DQS5
VSS_82
DQ51
VSS_84
DQ61
VSS_86
DQ56
VSS_88
DM7_n/DBl7_n
VSS_89
DQ62
VSS_91
DQ58
VSS_93
SCL
VDDSPD
VPP_1
VPP_2

GND_1

ME@

ARGOS_D4AR0-26005-1P40

EVENT_n/NF

VDD_10
CK1_t/NF
CK1_c/NF

VDD_12

A10/AP

VDD_14

A16/RAS_n

VDD_16

A15/CAS_n

VDD_18

C0/CS2_n/NC

VREFCA

VSS_54

VSS_56

VSS_58

DM4_n/DBl4_n

VSS_59

VSS_61

VSS_63

VSS_65

VSS_67

DQS5_c

DQS5_t

VSS_70

VSS_72

VSS_74

VSS_76

VSS_78

DM6_n/DBl6_n

VSS_79

VSS_81

VSS_83

VSS_85

VSS_87

DQS7_c

DQS7_t

VSS_90

VSS_92

VSS_94

GND_2

DQ36

DQ32

DQ39

DQ35

DQ45

DQ41

DQ47

DQ43

DQ53

DQ48

DQ54

DQ50

DQ60

DQ57

DQ63

DQ59

SDA

A2

A0

BA0

A13

SA2

SA0
VTT
SA1

+1.2V + 0.6VS

132
134
136
138
140
142
144

146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
210
212
214
216
218
220
222
224
226
228
230
232
234
236
238
240
242
244
246
248
250
252
254
256
258
260

262

EVENT_n_1

M_VREF_CA_DIMMA
SA2_CHA_P

PM_SMB_DAT
SA0_CHA_P

SA1_CHA_P

R2301
240_0402_1%

1

C2301

2.2U_0402_10V6-K

2

@

1

M_A_DDRCLK1_1066M 6

-M_A_DDRCLK1_1066M 6

M_A_BS0 6

2

C2302

0.1U_0402_10V7-K

1

@

SPD Address = 0H

5

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRA NSFERED FROM THE CUSTODY OF THE COMPETENT DIVI SION OF R& D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRA NSFERED FROM THE CUSTODY OF THE COMPETENT DIVI SION OF R& D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRA NSFERED FROM THE CUSTODY OF THE COMPETENT DIVI SION OF R& D
DEPARTMENT EXCEPT AS AUTHORIZED B Y LC FUTURE CENTER NEI THER THIS S HEET NOR THE INFORMATION IT CO NTAINS

DEPARTMENT EXCEPT AS AUTHORIZED B Y LC FUTURE CENTER NEI THER THIS S HEET NOR THE INFORMATION IT CO NTAINS

DEPARTMENT EXCEPT AS AUTHORIZED B Y LC FUTURE CENTER NEI THER THIS S HEET NOR THE INFORMATION IT CO NTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRI TTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRI TTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRI TTEN CONSENT OF LC FUTURE CENTER.

3

2015/09/01

2015/09/01

2015/09/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/12/31

2016/12/31

2016/12/31

Title

Title

Title

DDR4 CH-A PRIMARY

DDR4 CH-A PRIMARY

DDR4 CH-A PRIMARY

Size

Size

Size

Document N umber Re v

Document N umber Re v

Document N umber Re v

FL490/FL590 NM-B931

FL490/FL590 NM-B931

FL490/FL590 NM-B931

Wednesday, March 13, 2019

Wednesday, March 13, 2019

Wednesday, March 13, 2019

Date: Sheet of

Date: Sheet of

Date: Sheet of

23 99

23 99

23 99

1

0.3Custom

0.3Custom

0.3Custom

5

www.teknisi-indonesia.com

4

3

2

1

+2.5V

+1.2V

+0.6VS

D D

C C

B B

[WHL PDG]VDDQ

[WHL PDG] EE 10uF x16, 1uF x16. 330uF x1

Place 10uF/1uF decoupling cap, 4
near each side of the DIMM
connector close to VDD pins.
330uF placeholder

+1.2V

1

C2401
10U_0603_6.3V6-M

2

+1.2V

1

C2409

0.1U_0402_10V7-K

2

[WHL PDG]VPP

[WHL PD G] EE 10u F x2, 1u F x2.
Place decoupling cap on DRAM side.

+2.5V

1

C2420

0.1U_0402_10V7-K

2

RF_NS@

[WHL PDG]VTT

[WHL PD G] EE 10u F x2, 1u F x4.

+0.6VS

1

C2426

0.1U_0402_10V7-K

2

RF_NS@

+2.5V 6,23,25,26,95

+1.2V 6,7,18,23,25,26,86

+0.6VS 23,25,26,86

1

C2402
10U_0603_6.3V6-M

2

@

1

C2410
100P_0402_50V8J

2

1

C2421
100P_0402_50V8J

2

RF_NS@

1

C2427
100P_0402_50V8J

2

RF_NS@

12

C2403
10U_0603_6.3V6-M

C2411
1U_0402_6.3V6-K

12

C2422
10U_0603_6.3V6-M

12

C2428
10U_0603_6.3V6-M

1

C2404
10U_0603_6.3V6-M

2

@

2

C2412
1U_0402_6.3V6-K

1

@

12

C2429
10U_0603_6.3V6-M

Total quantity is referring to 2 channels.

1

2

2

C2413
1U_0402_6.3V6-K

1

@

12

C2423
10U_0603_6.3V6-M

@

C2405
10U_0603_6.3V6-M

C2430
1U_0402_6.3V6-K

12

C2414
1U_0402_6.3V6-K

C2424
1U_0402_6.3V6-K

C2406
10U_0603_6.3V6-M

C2431
1U_0402_6.3V6-K

1

C2407
10U_0603_6.3V6-M

2

@

C2415
1U_0402_6.3V6-K

C2425
1U_0402_6.3V6-K

C2432
1U_0402_6.3V6-K

12

C2408
10U_0603_6.3V6-M

@

C2416
1U_0402_6.3V6-K

C2433
1U_0402_6.3V6-K

C2417
1U_0402_6.3V6-K

2

C2418
1U_0402_6.3V6-K

1

@

1

+

C2419
330U_D1_2VM_R6M

2

Place decoupling on the VTT plane close to SODI MM

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2015/01/12

2015/01/12

2015/01/12

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2016/01/12

2016/01/12

2016/01/12

2

Title

DDR4 CH-A PRIMARY_POWER

DDR4 CH-A PRIMARY_POWER

DDR4 CH-A PRIMARY_POWER

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

FL490/FL590 NM-B931

FL490/FL590 NM-B931

FL490/FL590 NM-B931

Wednesday, March 13, 2019

Wednesday, March 13, 2019

Wednesday, March 13, 2019

Date: Sheet

Date: Sheet

Date: Sheet

1

of

of

of

24 99

24 99

24 99

0.3

0.3

0.3

5

www.teknisi-indonesia.com

+3VS

+2.5V

+1.2V

+0.6VS

D D

M_B_DQ1

M_B_DQ0

-M_B_DQS0
M_B_DQS0

M_B_DQ6

M_B_DQ7

M_B_DQ13

M_B_DQ12

M_B_DQ15

M_B_DQ14

M_B_DQ20

M_B_DQ17

-M_B_DQS2

C C

B B

A A

M_B_DQS2

M_B_DQ18

M_B_DQ23

M_B_DQ44

M_B_DQ45

M_B_DQ42

M_B_DQ46

M_B_CKE0

M_B_CKE07

M_B_BG1

M_B_BG17

M_B_BG0

M_B_BG07

M_B_A12
M_B_A9

M_B_A8
M_B_A6

M_B_VREF_CA_CPU6

+3VS 5,9,10,11,12,14,15,23,30,32,37,39,40,42,49,50,51,55,56,57,58,59,60,61,62,63,65,66,72,82,86,87 M_B_DQ[63:0]6,7

+2.5V 6,23,24,26,95

+1.2V 6,7,18,23,24,26,86

+0.6VS 23,24,26,86

+1.2V +1.2V

JDIMM2A

1

VSS_1

3

DQ5

5

VSS_3

7

DQ1

9

VSS_5

11

DQS0_C

13

DQS0_t

15

VSS_8

17

DQ7

19

VSS_10

21

DQ3

23

VSS_12

25

DQ13

27

VSS_14

29

DQ9

31

VSS_16

33

DM1_n/DBl_n

35

VSS_17

37

DQ15

39

VSS_19

41

DQ10

43

VSS_21

45

DQ21

47

VSS_23

49

DQ17

51

VSS_25

53

DQS2_c

55

DQS2_t

57

VSS_28

59

DQ23

61

VSS_30

63

DQ19

65

VSS_32

67

DQ29

69

VSS_34

71

DQ25

73

VSS_36

75

DM3_n/DBl3_n

77

VSS_37

79

DQ30

81

VSS_39

83

DQ26

85

VSS_41

87

CB5/NC

89

VSS_43

91

CB1/NC

93

VSS_45

95

DQS8_c

97

DQS8_t

99

VSS_48

101

CB2/NC

103

VSS_50

105

CB3/NC

107

VSS_52

109

CKE0

111

VDD_1

113

BG1

115

BG0

117

VDD_3

119

A12

121

A9

123

VDD_5

125

A8

127

A6

129

VDD_7

ARGOS_D4AR0-26005-1P40

ME@

R2504
2_0402_1%

1 2

1

CD65

0.022U_0402_25V7-K

2

12

R2506

24.9_0402_1%

5

VSS_2

VSS_4

VSS_6

DM0_n/DBl0_n

VSS_7

VSS_9

VSS_11

VSS_13

VSS_15
DQS1_c
DQS1_t
VSS_18

VSS_20

VSS_22

VSS_24

VSS_26

DM2_n/DBl2_n

VSS_27

VSS_29

VSS_31

VSS_33

VSS_35
DQS3_c
DQS3_t
VSS_38

VSS_40

VSS_42
CB4/NC
VSS_44
CB0/NC
VSS_46

DM8_n/DBl_n/NC

VSS_47
CB6/NC
VSS_49
CB7/NC
VSS_51

RESET_n

VDD_2

ALERT_n

VDD_4

VDD_6

VDD_8

ACT_n

2
4

DQ4

6
8

DQ0

10
12
14
16

DQ6

18
20

DQ2

22
24

DQ12

26
28

DQ8

30
32
34
36
38

DQ14

40
42

DQ11

44
46

DQ20

48
50

DQ16

52
54
56
58

DQ22

60
62

DQ18

64
66

DQ28

68
70

DQ24

72
74
76
78
80

DQ31

82
84

DQ27

86
88
90
92
94
96
98
100
102
104
106
108
110

CKE1

112
114
116
118
120

A11

122

A7

124
126

A5

128

A4

130

+1.2V

12

R2503
1K_0402_1%

12

R2507
1K_0402_1%

4

Layout Node:

Place Close DIMMs

M_B_DQ4

M_B_DQ5

M_B_DQ3

M_B_DQ2

M_B_DQ9

M_B_DQ8

-M_B_DQS1
M_B_DQS1

M_B_DQ10

M_B_DQ11

M_B_DQ21

M_B_DQ16

M_B_DQ19

M_B_DQ22

M_B_DQ40

M_B_DQ41

-M_B_DQS5
M_B_DQS5

M_B_DQ47

M_B_DQ43

-DRAMRST
M_B_CKE1

-M_B_ACT

-M_B_ALERT

12

C2501

0.1U_0402_16V7-K

EMC_NS@

M_VREF_CA_DIMMB

12

CD66

0.1U_0402_16V7-K

@

4

-DRAMRST 7,23
M_B_CKE1 7

-M_B_ACT 7

-M_B_ALERT 7

M_B_A11
M_B_A7

M_B_A5
M_B_A4

3

-M_B_DQS[7:0]6,7

M_B_DQS[7:0]6,7

M_B_A[16:0]7

M_B_DDRCLK0_1066M7

-M_B_DDRCLK0_1066M7

M_B_PARITY7

M_B_BS17

-M_B_CS07

M_B_ODT07

-M_B_CS17

M_B_ODT17

+3VS

12

R2502
0_0402_SP

PM_SMB_CLK9,23,65 PM_SMB_DAT 9,23,65

[WHL PDG]VDDSPD

[WHL PDG] EE 0.1uF
x1, 2.2uF x1.

Place decoupling
cap close to DIMM

+3VS +3VS +3VS

12

R2510
10K_0402_5%

@

SA0_CHB_P SA1_CHB_P SA2_CHB_P

12

R2511
0_0402_SP

12

R2512
10K_0402_5%

12

R2513
0_0402_5%

@

1

2

SPD Address = 2H

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRA NSFERED FROM THE CUSTODY OF THE COMPETENT DIVI SION OF R& D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRA NSFERED FROM THE CUSTODY OF THE COMPETENT DIVI SION OF R& D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRA NSFERED FROM THE CUSTODY OF THE COMPETENT DIVI SION OF R& D
DEPARTMENT EXCEPT AS AUTHORIZED B Y LC FUTURE CENTER NEI THER THIS S HEET NOR THE INFORMATION IT CO NTAINS

DEPARTMENT EXCEPT AS AUTHORIZED B Y LC FUTURE CENTER NEI THER THIS S HEET NOR THE INFORMATION IT CO NTAINS

DEPARTMENT EXCEPT AS AUTHORIZED B Y LC FUTURE CENTER NEI THER THIS S HEET NOR THE INFORMATION IT CO NTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRI TTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRI TTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRI TTEN CONSENT OF LC FUTURE CENTER.

3

CD63

0.1U_0402_10V7-K

12

R2514
10K_0402_5%

@

12

R2515
0_0402_SP

M_B_A3
M_B_A1

M_B_DDRCLK0_1066M

-M_B_DDRCLK0_1066M

M_B_PARITY

M_B_BS1

-M_B_CS0
M_B_A14

M_B_ODT0

-M_B_CS1

M_B_ODT1

M_B_DQ52

M_B_DQ49

-M_B_DQS6
M_B_DQS6

M_B_DQ50

M_B_DQ51

M_B_DQ33

M_B_DQ36

M_B_DQ34

M_B_DQ35

M_B_DQ61

M_B_DQ60

-M_B_DQS7
M_B_DQS7

M_B_DQ58

M_B_DQ59

M_B_DQ24

M_B_DQ25

M_B_DQ27

M_B_DQ26

PM_SMB_CLK
VDDSPD_2

1

CD64

2.2U_0402_10V6-K

2

2015/09/01

2015/09/01

2015/09/01

+1.2V+2.5V

+1.2V

131
133
135
137
139
141
143

145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
205
207
209
211
213
215
217
219
221
223
225
227
229
231
233
235
237
239
241
243
245
247
249
251
253
255
257
259

261

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

JDIMM2B

A3
A1
VDD_9
CK0_t
CK0_c
VDD_11
Parity

BA1
VDD_13
CS0_n
A14/WE_n
VDD_15
ODT0
CS1_n
VDD_17
ODT1
VDD_19
C1/CS3_n/NC
VSS_53
DQ37
VSS_55
DQ33
VSS_57
DQS4_c

DM4_n/DBl4_n
DQS4_t
VSS_60
DQ38
VSS_62
DQ34
VSS_64
DQ44
VSS_66
DQ40
VSS_68
DM5_n/DBl5_n
VSS_69
DQ46
VSS_71
DQ42
VSS_73
DQ52
VSS_75
DQ49
VSS_77
DQS6_c

DM6_n/DBl6_n
DQS6_t
VSS_80
DQS5
VSS_82
DQ51
VSS_84
DQ61
VSS_86
DQ56
VSS_88
DM7_n/DBl7_n
VSS_89
DQ62
VSS_91
DQ58
VSS_93
SCL
VDDSPD
VPP_1
VPP_2

GND_1

ARGOS_D4AR0-26005-1P40

ME@

2

EVENT_n/NF

VDD_10
CK1_t/NF
CK1_c/NF

VDD_12

A10/AP

VDD_14

A16/RAS_n

VDD_16

A15/CAS_n

VDD_18

C0/CS2_n/NC

VREFCA

VSS_54

VSS_56

VSS_58

VSS_59

VSS_61

VSS_63

VSS_65

VSS_67

DQS5_c

DQS5_t

VSS_70

VSS_72

VSS_74

VSS_76

VSS_78

VSS_79

VSS_81

VSS_83

VSS_85

VSS_87

DQS7_c

DQS7_t

VSS_90

VSS_92

VSS_94

GND_2

A2

A0

BA0

A13

SA2

DQ36

DQ32

DQ39

DQ35

DQ45

DQ41

DQ47

DQ43

DQ53

DQ48

DQ54

DQ50

DQ60

DQ57

DQ63

DQ59

SDA

SA0
VTT
SA1

2016/12/31

2016/12/31

2016/12/31

+1.2V + 0.6VS

132
134
136
138
140
142
144

146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
210
212
214
216
218
220
222
224
226
228
230
232
234
236
238
240
242
244
246
248
250
252
254
256
258
260

262

1

+1.2V

12

R2501

M_B_A2
EVENT_n_2

M_B_DDRCLK1_1066M

-M_B_DDRCLK1_1066M

M_B_A0

M_B_A10

M_B_BS0
M_B_A16

M_B_A15
M_B_A13

M_VREF_CA_DIMMB
SA2_CHB_P

M_B_DQ48

M_B_DQ53

M_B_DQ54

M_B_DQ55

M_B_DQ32

M_B_DQ37

-M_B_DQS4
M_B_DQS4

M_B_DQ39

M_B_DQ38

M_B_DQ56

M_B_DQ57

M_B_DQ63

M_B_DQ62

M_B_DQ29

M_B_DQ28

-M_B_DQS3
M_B_DQS3

M_B_DQ30

M_B_DQ31

PM_SMB_DAT
SA0_CHB_P

SA1_CHB_P

Title

Title

Title

Size

Size

Size

Date: Sheet of

Date: Sheet of

Date: Sheet of

240_0402_1%

M_B_DDRCLK1_1066M 7

-M_B_DDRCLK1_1066M 7

M_B_BS0 7

+1.2V

1

1

CD61

CD62

2.2U_0402_10V6-K

2

+1.2V

DDR4 CH-B PRIMARY

DDR4 CH-B PRIMARY

DDR4 CH-B PRIMARY

Document N umber Re v

Document N umber Re v

Document N umber Re v

FL490/FL590 NM-B931

FL490/FL590 NM-B931

FL490/FL590 NM-B931

Wednesday, March 13, 2019

Wednesday, March 13, 2019

Wednesday, March 13, 2019

0.1U_0402_10V7-K

2

@

@

25 99

25 99

25 99

1

0.3Custom

0.3Custom

0.3Custom

5

www.teknisi-indonesia.com

4

3

2

1

+2.5V

D D

C C

B B

+1.2V

+0.6VS

[WHL PDG]VDDQ

[WHL PDG] EE 10uF x16, 1uF x16. 330uF x1

Place 10uF/1uF decoupling cap, 4
near each side of the DIMM
connector close to VDD pins.
330uF placeholder

+1.2V

1

C2601
10U_0603_6.3V6-M

2

+1.2V

1

C2609

0.1U_0402_10V7-K

2

[WHL PDG]VPP

[WHL PD G] EE 10u F x2, 1u F x2.
Place decoupling cap on DRAM side.

+2.5V

1

C2619

0.1U_0402_10V7-K

2

RF_NS@

[WHL PDG]VTT

[WHL PD G] EE 10u F x2, 1u F x4.

+0.6VS

1

C2625

0.1U_0402_10V7-K

2

RF_NS@

+2.5V 6,23,24,25,95

+1.2V 6,7,18,23,24,25,86

+0.6VS 23,24,25,86

12

C2602
10U_0603_6.3V6-M

1

C2610
100P_0402_50V8J

2

1

C2620
100P_0402_50V8J

2

RF_NS@

1

C2626
100P_0402_50V8J

2

RF_NS@

12

C2603
10U_0603_6.3V6-M

2

C2611
1U_0402_6.3V6-K

1

@

12

C2621
10U_0603_6.3V6-M

@

12

C2627
10U_0603_6.3V6-M

12

C2604
10U_0603_6.3V6-M

2

C2612
1U_0402_6.3V6-K

1

@

12

C2622
10U_0603_6.3V6-M

12

C2628
10U_0603_6.3V6-M

@

Total quantity is referring to 2 channels.

1

C2605
10U_0603_6.3V6-M

2

C2613
1U_0402_6.3V6-K

C2623
1U_0402_6.3V6-K

C2629
1U_0402_6.3V6-K

12

C2606
10U_0603_6.3V6-M

C2614
1U_0402_6.3V6-K

C2630
1U_0402_6.3V6-K

C2615
1U_0402_6.3V6-K

C2624
1U_0402_6.3V6-K

12

C2631
1U_0402_6.3V6-K

C2607
10U_0603_6.3V6-M

2

1

12

C2608
10U_0603_6.3V6-M

C2616
1U_0402_6.3V6-K

@

C2632
1U_0402_6.3V6-K

C2617
1U_0402_6.3V6-K

C2618
1U_0402_6.3V6-K

Place decoupling on the VTT plane close to SODI MM

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2015/01/12

2015/01/12

2015/01/12

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2016/01/12

2016/01/12

2016/01/12

2

Title

DDR4 CH-B PRIMARY_POWER

DDR4 CH-B PRIMARY_POWER

DDR4 CH-B PRIMARY_POWER

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

FL490/FL590 NM-B931

FL490/FL590 NM-B931

FL490/FL590 NM-B931

Wednesday, March 13, 2019

Wednesday, March 13, 2019

Wednesday, March 13, 2019

Date: Sheet

Date: Sheet

Date: Sheet

1

of

of

of

26 99

26 99

26 99

0.3

0.3

0.3

+VCC_CORE +VCC_GT

www.teknisi-indonesia.com

5

+VCC_GT 17,89,91+VCC_CORE 16,17,88,91

[WHL U4+2 Processor]VCC

+VCC_CORE

1

1

C2719

D D

C C

B B

A A

C2701

22U_0603_6.3V6-M

22U_0603_6.3V6-M

2

2

Cost@

+VCC_CORE

1

1

C2720

C2721

10U_0402_6.3V6-M

10U_0402_6.3V6-M

2

2

Cost@

+VCC_CORE

1

1

C27136

C27139

10U_0402_6.3V6-M

10U_0402_6.3V6-M

2

2

Cost@

Cost@

+VCC_CORE

1

1

C2710

C2709

1U_0201_6.3V6-M

1U_0201_6.3V6-M

2

2

Cost@

Cost@

+VCC_CORE

1

1

C2728

C2727

1U_0201_6.3V6-M

1U_0201_6.3V6-M

2

2

Cost@

Cost@

+VCC_CORE

1

1

C2737

C2738

1U_0201_6.3V6-M

1U_0201_6.3V6-M

2

2

Cost@

+VCC_CORE

1

1

C2747

C27129

1U_0201_6.3V6-M

1U_0201_6.3V6-M

2

2

[WHL U4+2 Processor]22uF x8
BOTTOM

+VCC_CORE

1

1

C2775

C2781

10U_0402_6.3V6-M

10U_0402_6.3V6-M

2

2

Cost@

Cost@

[WHL U4+2 Processor]47uF x18
The following capacitors can be placed on as either Primary or back side cap.

+VCC_CORE

1

1

C27126

C27124

22U_0603_6.3V6-M

22U_0603_6.3V6-M

2

2

Cost@

+VCC_CORE

1

1

C2783

C2784

22U_0603_6.3V6-M

22U_0603_6.3V6-M

2

2

Cost@

Cost@

1

C2702
22U_0603_6.3V6-M

2

1

C2722
10U_0402_6.3V6-M

2

Cost@

1

C27137
10U_0402_6.3V6-M

2

1

C2711
1U_0201_6.3V6-M

2

Cost@

1

C2729
1U_0201_6.3V6-M

2

Cost@

1

C2739
1U_0201_6.3V6-M

2

1

C27131
1U_0201_6.3V6-M

2

Cost@

1

C2776
10U_0402_6.3V6-M

2

Cost@

1

C27120
22U_0603_6.3V6-M

2

1

C2785
22U_0603_6.3V6-M

2

Cost@

5

1

C2703
22U_0603_6.3V6-M

2

1

C2723
10U_0402_6.3V6-M

2

Cost@

1

C27138
10U_0402_6.3V6-M

2

Cost@

1

C2712
1U_0201_6.3V6-M

2

Cost@

1

C2730
1U_0201_6.3V6-M

2

1

C2740
1U_0201_6.3V6-M

2

1

C27130
1U_0201_6.3V6-M

2

1

C2777
10U_0402_6.3V6-M

2

1

C27127
22U_0603_6.3V6-M

2

1

C2786
22U_0603_6.3V6-M

2

Cost@

1

C2704
22U_0603_6.3V6-M

2

Cost@

1

C2724
10U_0402_6.3V6-M

2

Cost@

1

C2713
1U_0201_6.3V6-M

2

Cost@

1

C2731
1U_0201_6.3V6-M

2

Cost@

1

C2741
1U_0201_6.3V6-M

2

1

C27132
1U_0201_6.3V6-M

2

Cost@

1

C2778
10U_0402_6.3V6-M

2

Cost@

1

C27125
22U_0603_6.3V6-M

2

1

C2787
22U_0603_6.3V6-M

2

1

C2705
22U_0603_6.3V6-M

2

1

C2725
10U_0402_6.3V6-M

2

1

C2714
1U_0201_6.3V6-M

2

Cost@

1

C2732
1U_0201_6.3V6-M

2

1

C2742
1U_0201_6.3V6-M

2

Cost@

1

C2779
10U_0402_6.3V6-M

2

Cost@

1

C27119
22U_0603_6.3V6-M

2

1

C2788
22U_0603_6.3V6-M

2

Cost@

1

C2706
22U_0603_6.3V6-M

2

1

C2726
10U_0402_6.3V6-M

2

Cost@

1

C2715
1U_0201_6.3V6-M

2

1

C2733
1U_0201_6.3V6-M

2

Cost@

1

C2743
1U_0201_6.3V6-M

2

1

C2780
10U_0402_6.3V6-M

2

1

C27123
22U_0603_6.3V6-M

2

Cost@

1

C2789
22U_0603_6.3V6-M

2

Cost@

1

C2707
22U_0603_6.3V6-M

2

1

C27133
10U_0402_6.3V6-M

2

1

C2716
1U_0201_6.3V6-M

2

1

C2734
1U_0201_6.3V6-M

2

1

C2744
1U_0201_6.3V6-M

2

1

C2782
10U_0402_6.3V6-M

2

1

C27121
22U_0603_6.3V6-M

2

1

C2790
22U_0603_6.3V6-M

2

1

C2708
22U_0603_6.3V6-M

2

1

C27134
10U_0402_6.3V6-M

2

Cost@

1

C2717
1U_0201_6.3V6-M

2

1

C2735
1U_0201_6.3V6-M

2

Cost@

1

C2745
1U_0201_6.3V6-M

2

Cost@

1

C27122
22U_0603_6.3V6-M

2

4

1

C27135
10U_0402_6.3V6-M

2

Cost@

1

C2718
1U_0201_6.3V6-M

2

1

C2736
1U_0201_6.3V6-M

2

1

C2746
1U_0201_6.3V6-M

2

Cost@

1

C27128
22U_0603_6.3V6-M

2

4

[WHL U4+2 Processor]VCCGT

[WHL U4+2 Processor]10uF x15,1uF x11[WHL U4+2 Processor]10uF x14,1uF x35,22uF x9
TOPTOP

+VCC_GT

1

C2763
1U_0201_6.3V6-M

2

@

1

C27156
10U_0402_6.3V6-M

2

1

C27163
10U_0402_6.3V6-M

2

@

1

C27100
22U_0603_6.3V6-M

2

1

C27148
22U_0603_6.3V6-M

2

1

C27151
22U_0603_6.3V6-M

2

1

C27112
1U_0201_6.3V6-M

2

@

1

C2753
10U_0402_6.3V6-M

2

@

1

C2764
1U_0201_6.3V6-M

2

1

C27157
10U_0402_6.3V6-M

2

1

C27164
10U_0402_6.3V6-M

2

1

C2799
22U_0603_6.3V6-M

2

1

C27147
22U_0603_6.3V6-M

2

1

C27150
22U_0603_6.3V6-M

2

1

C27115
1U_0201_6.3V6-M

2

@

1

C2754
10U_0402_6.3V6-M

2

@

1

C2762
1U_0201_6.3V6-M

2

+VCC_GT

1

C2771

2.2U_6.3V_M_X5R_0201

2

+VCC_GT

1

C27162
10U_0402_6.3V6-M

2

+VCC_GT

1

C27167
10U_0402_6.3V6-M

2

[WHL U4+2 Processor]22uF x15,47uF x4

BOTTOM

+VCC_GT

1

C27101
22U_0603_6.3V6-M

2

+VCC_GT

1

C27149
22U_0603_6.3V6-M

2

@

+VCC_GT

1

C27152
22U_0603_6.3V6-M

2

[WHL U4+2 Processor]+VCC_CORE

[WHL U4+2 Processor]1uF x7,22uF x7

TOP

+VCC_CORE

1

C27113
1U_0201_6.3V6-M

2

@

+VCC_CORE

1

C2752
10U_0402_6.3V6-M

2

@

1

C2765

2.2U_6.3V_M_X5R_0201

2

1

C27158
10U_0402_6.3V6-M

2

1

C27165
10U_0402_6.3V6-M

2

1

C2795
22U_0603_6.3V6-M

2

1

C27143
22U_0603_6.3V6-M

2

1

C27114
1U_0201_6.3V6-M

2

Cost@

1

C2755
10U_0402_6.3V6-M

2

Cost@

3

1

C2766

2.2U_6.3V_M_X5R_0201

2

1

C27159
10U_0402_6.3V6-M

2

1

C27166
10U_0402_6.3V6-M

2

1

C2798
22U_0603_6.3V6-M

2

1

C27146
22U_0603_6.3V6-M

2

1

C27116
1U_0201_6.3V6-M

2

@

1

C2756
10U_0402_6.3V6-M

2

Cost@

3

1

C2767
1U_0201_6.3V6-M

2

1

C27160
10U_0402_6.3V6-M

2

1

C2796
22U_0603_6.3V6-M

2

1

C27144
22U_0603_6.3V6-M

2

1

C27117
1U_0201_6.3V6-M

2

Cost@

1

C2792
10U_0402_6.3V6-M

2

@

1

C2793
1U_0201_6.3V6-M

2

@

1

C27161
10U_0402_6.3V6-M

2

@

1

C2797
22U_0603_6.3V6-M

2

1

C27145
22U_0603_6.3V6-M

2

1

C27107
1U_0201_6.3V6-M

2

Cost@

1

C2757
10U_0402_6.3V6-M

2

Cost@

1

C2768
1U_0201_6.3V6-M

2

@

1

C27154
10U_0402_6.3V6-M

2

1

C27102
22U_0603_6.3V6-M

2

@

1

C27140
22U_0603_6.3V6-M

2

1

C2769
1U_0201_6.3V6-M

2

@

1

C27153
10U_0402_6.3V6-M

2

@

1

C27103
22U_0603_6.3V6-M

2

1

C27141
22U_0603_6.3V6-M

2

@

1

C2770

2.2U_6.3V_M_X5R_0201

2

1

C27155
10U_0402_6.3V6-M

2

@

1

C27104
22U_0603_6.3V6-M

2

1

C27142
22U_0603_6.3V6-M

2

@

2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2

2015/01/12

2015/01/12

2015/01/12

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2016/01/12

2016/01/12

2016/01/12

1

Title

Title

Title

VCC_CORE & VCC_GT CAP

VCC_CORE & VCC_GT CAP

VCC_CORE & VCC_GT CAP

Size

Size

Size

Document Number Rev

Document Number Rev

Document Number Rev

D

D

D

FL490/ FL590 NM-B931

FL490/ FL590 NM-B931

FL490/ FL590 NM-B931

Wednesday, March 13, 2019

Wednesday, March 13, 2019

Wednesday, March 13, 2019

Date: Sheet

Date: Sheet

Date: Sheet

1

27 99

27 99

27 99

of

of

of

0.3

0.3

0.3

5

www.teknisi-indonesia.com

D D

C C

B B

4

3

2

1

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2015/01/12

2015/01/12

2015/01/12

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2016/01/12

2016/01/12

2016/01/12

2

Title

BLANK

BLANK

BLANK

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

FL490/FL590 NM-B931

FL490/FL590 NM-B931

FL490/FL590 NM-B931

Wednesday, March 13, 2019

Wednesday, March 13, 2019

Wednesday, March 13, 2019

Date: Sheet

Date: Sheet

Date: Sheet

1

of

of

of

28 99

28 99

28 99

0.3

0.3

0.3

5

www.teknisi-indonesia.com

4

3

2

1

+1.8VS_VGA

TEST_PG

TEST6

K4G80325FB-HC28

H5GC8H24AJR-R0C

2G

MT51J256M32HF-70:B

PS_0[1]
PS_0[2]
PS_0[3]

TEST_PG 32

TEST6 30

12

DIS@

1K_0402_1%

D D

R2909

12

R2910
0_0402_SP

Samsung

Hynix2G2G

C C

Micron

PS_0[4]

PS_0[5]

PS_1[1]

PS_1[2]

B B

PS_1[3]

PS_1[4]

PS_1[5]

PS_2[1]

PS_2[2]

PS_2[3]

PS_2[4]

PS_2[5]

PS_3[1]
PS_3[2]
PS_3[3]

PS_3[4]

PS_3[5]

A A

12

R2901

DIS@

8.45K_0402_1%

GENERICG_HPD6

1

@

R2902

DIS@

+1.8VS_VGA

DIS@

DIS@

1 2

12

1 2

2K_0402_1%

R2903

8.45K_0402_1%

R2904
2K_0402_1%

C2901

0.1U_0402_10V7-K

2

1

@

C2902

0.1U_0402_10V7-K

2

R2907Memory (GDDR5)

PU 3.4K PD 10K

PU 4.75K NC

PU 3.24K PD 5.62K

ROM_CONFIG[0]
ROM_CONFIG[1]
ROM_CONFIG[2]

N/A

N/A

STRAP_BIF_GEN3_EN_A

STRAP_BIF_CLK_PM_ EN

N/A

STRAP_TX_CFG_DRV_FULL_SWING

STRAP_TX_DEEMPH_ EN

N/A

N/A

STRAP_BIOS_ROM_EN

N/A

N/A

BOARD_CONFIG [0]
BOARD_CONFIG [1]
BOARD_CONFIG [2]

N/A

N/A

GENERICB 32

R2908

+1.8VS_VGA

12

R2905

@

DIS@

+1.8VS_VGA

X76@

X76@

10K_0402_1%

12

R2906

4.75K_0402_1%

12

R2907

3.24K_0402_1%

12

R2908

5.62K_0402_1%

GENERICG_HPD6 32

110

111

101

STRAP_BIOS_ROM_EN = 1

ROM_CONFIG[2:0] = [001] 256MB

1 (Default)

1 (Default)

1 = PCIe GEN3 is supported

0 = The CLKREQB power management
capability is disabled

0 (Default)

1 = The transmitter full-swing
is enabled

1 = Tx deemphasis enabled

0 (Default)

0 (Default)

0 = Disable the external BIOS ROM device

1 (Default)

1 (Default)

PS_3[3..1]
101 = Micron 2G
110 = Samsung 2G
111 = Hynix 2G

1 (Default)

1 (Default)

@

@

MLPS

PS_0[5:1]

PS_1[5:1]

PS_2[5:1]

PS_3[5:1]

GENERICC

1

C2903

0.1U_0402_10V7-K

2

GENERICDGENERICB

1

C2904

0.1U_0402_10V7-K

2

5 4 3 1

1

1 1 0 0 1

GENERICC 32

GENERICD 32

Bit

2

1 0 0 1

X X

UV3001K

0.1U_0402_10V6-K

TX2M_ DPB 0N

TX1M_ DPB 1N

TX0M_ DPB 2N

TXCBP_ DPB 3P

TXCBM _DP B3N

TX5M_ DPA 0N

TX4M_ DPA 1N

TX3M_ DPA 2N

TXCAP_ DPA 3P

TXCAM _DP A3N

TX2P_ DPB 0P

TX1P_ DPB 1P

TX0P_ DPB 2P

DDCAUX3P

DDCAUX3N

TX5P_ DPA 0P

TX4P_ DPA 1P

TX3P_ DPA 2P

DDCAUX4P

DDCAUX4N

3

2

AY32

BA32

AY31

BA31

AY30

BA30

AY28

BA28

AM21

AP21

AY36

BA36

AY35

BA35

AY34

BA34

AY33

BA33

AR23

AP23

C2906

DIS@

12

symbol11

REV 0.91

216-0915006-A0_FCBGA769

DIS@

DGB_DATA[5]

XTALIN

1

C3204
22P_0402_50V8-J

2

DIS@

1

2

0.1U_0402_10V6-K

R2912

51.1_0402_1%

DIS@

DBGDAT A_1 0

DBGDAT A_1 1

DBGDAT A_1 2

DBGDAT A_1 3

DBGDAT A_1 4

DBGDAT A_1 5

L40

DBGDAT A_0

L41

DBGDAT A_1

M40

DBGDAT A_2

M41

DBGDAT A_3

N40

DBGDAT A_4

N41

DBGDAT A_5

P40

DBGDAT A_6

P41

DBGDAT A_7

R40

DBGDAT A_8

R41

DBGDAT A_9

T40
T41
U40
U41
V40
V41

GPU_ROMSCK

1

R3220

16.2K_0402_1%

@

TV55 PAD@

1

TV56 PAD@

1

TV57 PAD@

1

TV58 PAD@

1

TV59 PAD@

1

TV60 PAD@

1

TV61 PAD@

1

TV62 PAD@

1

TV63 PAD@

1

TV64 PAD@

1

TV65 PAD@

1

TV66 PAD@

1

TV67 PAD@

1

TV68 PAD@

1

TV69 PAD@

1

TV70 PAD@

UV3001G

symbol7

BA12

AUX_ZVS S

REV 0.91

216-0915006-A0_FCBGA769

DIS@

R3271
1M_0402_5%

DIS@

1 2

Y3202

DIS@

4

NC2

OSC2

1

XTALOUT

OSC1

NC1

27MHZ_16PF_7V27000011

1

C3203
22P_0402_50V8-J

2

DIS@

1

C2905

2

DIS@

1

TV42 PAD@

1

TV43 PAD@

12

R2911

51.1_0402_1%

DIS@

BA39

AY39

AV15
AU15

AY38

XTALIN

XTALOUT

PLLCHARZ_L
PLLCHARZ_H

PLL_ANALOG_OUT

GPU_ROMSI
GPU_ROMSO
GPIO22_ROMCSB
DGB_DATA[0]
DGB_DATA[1]
DGB_DATA[2]
DGB_DATA[3]
DGB_DATA[4]
DGB_DATA[5]
DGB_DATA[6]
DGB_DATA[7]
DGB_DATA[8]
DGB_DATA[9]
DGB_DATA[10]
DGB_DATA[11]

1 2

GPU_ROMSCK32
GPU_ROMSI32
GPU_ROMSO32
GPIO22_ROMCSB32
DGB_DATA[0]33
DGB_DATA[1]33
DGB_DATA[2]32
DGB_DATA[3]32
DGB_DATA[4]32

DGB_DATA[6]32
DGB_DATA[7]33
DGB_DATA[8]33
DGB_DATA[9]32
DGB_DATA[10]33
DGB_DATA[11]33

0001111

X

UV3001F

symbol6

XTALIN

XTALO UT

PLLCHAR Z_L

PLLCHAR Z_H

ANALOG IO

REV 0.91

216-0915006-A0_FCBGA769

DIS@

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC F UTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC F UTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC F UTURE CENTER.

2015/01/12

2015/01/12

2015/01/12

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/01/12

2016/01/12

2016/01/12

Title

M2-60(F/G/K)_Compatibility

M2-60(F/G/K)_Compatibility

M2-60(F/G/K)_Compatibility

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

FL490/FL590 NM-B931

FL490/FL590 NM-B931

FL490/FL590 NM-B931

Wednesday, March 13, 2019

Wednesday, March 13, 2019

Wednesday, March 13, 2019

Date: Sheet

Date: Sheet

Date: Sheet

1

of

of

of

29 99

29 99

29 99

0.3

0.3

0.3

+3VS_VGA

www.teknisi-indonesia.com

+1.8VS_VGA

5

+3VS

+3VS 5,9,10,11,12 ,14,15,23,25,32,37,39,40,42,49,50,51 ,55,56,57,58,59,60,61,62,63,65,66,72 ,82,86,87

+3VS_VGA 32,37,38,39,92

+1.8VS_VGA 29,32,34,38,92

4

3

AMD(R17M-P1-70)
AMD(R17M-P1-50)

2

TABLE of GPU (UV3001)

LCFC P/N

SA00008ED00

SA00008DT00

Description Vendor
S IC 216-0905004 C0 FCBGA 769P GPU
S IC 216-0905018 C3 FCBGA 769P GPU

1

D D

UV3001B

PCIE0_L0_TXP12
PCIE0_L0_TXN12

PCIE0_L1_TXP12
PCIE0_L1_TXN12

PCIE0_L2_TXP12
PCIE0_L2_TXN12

PCIE0_L3_TXP12
PCIE0_L3_TXN12

C C

+1.8VS_VGA

PCIE0_CLK_100M14

-PCIE0_CLK_100M14

PCIE0_L0_TXP
PCIE0_L0_TXN

PCIE0_L1_TXP
PCIE0_L1_TXN

PCIE0_L2_TXP
PCIE0_L2_TXN

PCIE0_L3_TXP
PCIE0_L3_TXN

PCIE0_CLK_100M

-PCIE0_CLK_100M

AT41

PCIE_RX0P

AT40

PCIE_RX0N

AR41

PCIE_RX1P

AR40

PCIE_RX1N

AP41

PCIE_RX2P

AP40

PCIE_RX2N

AM41

PCIE_RX3P

AM40

PCIE_RX3N

AL41

PCIE_RX4P

AL40

PCIE_RX4N

AK41

PCIE_RX5P

AK40

PCIE_RX5N

AJ41

PCIE_RX6P

AJ40

PCIE_RX6N

AH41

PCIE_RX7P

AH40

PCIE_RX7N

AV33

PCIE_REFCLKP

AU33

PCIE_REFCLKN

REV 0.91

216-0915006-A0 _FCBGA769

DIS@

symbol2

PCIE0_L0_RXP_C

AV35

PCIE_TX0P

PCIE0_L0_RXN_C

AU35

PCIE_TX0N

PCIE0_L1_RXP_C

AU38

PCIE_TX1P

PCIE0_L1_RXN_C

AU39

PCIE_TX1N

PCIE0_L2_RXP_C

AR37

PCIE_TX2P

PCIE0_L2_RXN_C

AR38

PCIE_TX2N

PCIE0_L3_RXP_C

AN37

PCIE_TX3P

PCIE0_L3_RXN_C

AN38

PCIE_TX3N

AL37

PCIE_TX4P

AL38

PCIE_TX4N

AJ37

PCIE_TX5P

AJ38

PCIE_TX5N

AG37

PCIE_TX6P

AG38

PCIE_TX6N

AE37

PCIE_TX7P

AE38

PCIE_TX7N

AV41

PERSTB

AC41

PX_EN

AU41

PCIE_ZVSS

C3008 0.22U_0201_6.3V6MDIS@
C3001 0.22U_0201_6.3V6MDIS@

C3002 0.22U_0201_6.3V6MDIS@
C3003 0.22U_0201_6.3V6MDIS@

C3004 0.22U_0201_6.3V6MDIS@
C3005 0.22U_0201_6.3V6MDIS@

C3006 0.22U_0201_6.3V6MDIS@
C3007 0.22U_0201_6.3V6MDIS@

PLT_RST_VGA#

PX_EX

DIS@

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

R3006 1K_0402_5%DIS@

support GEN3

PCIE0_L0_RXP
PCIE0_L0_RXN

PCIE0_L1_RXP
PCIE0_L1_RXN

PCIE0_L2_RXP
PCIE0_L2_RXN

PCIE0_L3_RXP
PCIE0_L3_RXN

+3VS_VGA

12

12

R3005
10K_0402_5%

@

12

R3007
100K_0402_5%

DIS@

PCIE0_L0_RXP 12
PCIE0_L0_RXN 12

PCIE0_L1_RXP 12
PCIE0_L1_RXN 12

PCIE0_L2_RXP 12
PCIE0_L2_RXN 12

PCIE0_L3_RXP 12
PCIE0_L3_RXN 12

JTAG

R3015

R3016

10K_0402_5%

10K_0402_5%

DIS@

DIS@

1 2

1 2

TV52

B B

A A

1

TV53

1

TEST629

R3014 33_0402_5%DIS@

1 2

R3013 33_0402_5%DIS@

1 2

TEST6

UV3001A

AA38

BP_0

AA37

BP_1

B2

TEST6

216-0915006-A0 _FCBGA769

DIS@

symbol1

REV 0.91

JTAG_TRSTB

JTAG_TDO
JTAG_TDI
JTAG_TMS
JTAG_TCK

TESTEN
JTAG_TRSTB

1
1
1
1

AF41

JTAG_TDO

AD40

JTAG_TDI

AD41

JTAG_TMS

AE41

JTAG_TCK

AE40

TESTEN

AF40

+3VS_VGA

12

+3VS_VGA

R3009
1K_0402_5%

@

12

R3008
1K_0402_5%

DIS@

12

R3010
10K_0402_5%

DIS@

12

R3011
1K_0402_5%

@

R3002
0_0402_5%

1 2

@

+3VS

U3003

1

R3004 0_04 02_SP

PLT_RST#15,40,51,52,56,58,62,63

DGPU_HOLD_RST#10

1 2

DGPU_HOLD_RST#

B

VCC

2

A

GND3Y

74LVC1G08GW_SOT353-1 -5

DIS@

SA00005U300

5

4

PD 10K at GPU Pin

PLT_RST_VGA# 32,92

TV48
TV49
TV50
TV51

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2015/01/12

2015/01/12

2015/01/12

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2016/01/12

2016/01/12

2016/01/12

2

Title

R17M-P1-50(A)_PCIE

R17M-P1-50(A)_PCIE

R17M-P1-50(A)_PCIE

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

FL490/FL590 NM-B931

FL490/FL590 NM-B931

FL490/FL590 NM-B931

Wednesday, March 13, 2019

Wednesday, March 13, 2019

Wednesday, March 13, 2019

1

of

of

of

30 99

30 99

30 99

0.3

0.3

0.3