Lenovo ThinkPad L470 Schematic

5

D D

4

3

2

1

1 2 1 2

SKL_ULT

DDI

DISPLAY SIDEBANDS

1 OF 20REV = 1

EDP

GPP_E13/DDPB_HPD0 GPP_E14/DDPC_HPD1 GPP_E15/DDPD_HPD2 GPP_E16/DDPE_HPD3

GPP_E17/EDP_HPD

DDIP1_CTRLCLK DDIP1_CTRLDATA

DDIP2_CTRLCLK DDIP2_CTRLDATA

EDP_TXN[0] EDP_TXP[0] EDP_TXN[1] EDP_TXP[1] EDP_TXN[2] EDP_TXP[2] EDP_TXN[3] EDP_TXP[3]

EDP_AUXN EDP_AUXP

EDP_DISP_UTIL

DDI1_AUXN DDI1_AUXP DDI2_AUXN DDI2_AUXP DDI3_AUXN DDI3_AUXP

EDP_BKLTEN

EDP_BKLTCTL

EDP_VDDEN

C47 C46 D46 C45 A45 B45 A47 B47

E45 F45

B52 G50

F50 E48 F48 G46 F46

L9 L7 L6 N9 L10

R12 R11 U13

MINI-DP

CPU_EDP_TX0CPU_EDP_TX0+ CPU_EDP_TX1CPU_EDP_TX1+ CPU_EDP_TX2CPU_EDP_TX2+ CPU_EDP_TX3CPU_EDP_TX3+

CPU_EDP_AUX# CPU_EDP_AUX

DDIP1_AUXN DDIP1_AUXP DDIP2_AUXN DDIP2_AUXP

DDIP1_HPD DDIP2_HPD

CPU_EDP_HPD ENBKL

PCH_EDP_PWM PCH_ENVDD

DDIP1_HPD DDIP2_HPD CPU_EDP_HPD ENBKL

CPU_EDP_TX0- [52] CPU_EDP_TX0+ [52] CPU_EDP_TX1- [52] CPU_EDP_TX1+ [52] CPU_EDP_TX2- [52] CPU_EDP_TX2+ [52] CPU_EDP_TX3- [52] CPU_EDP_TX3+ [52]

CPU_EDP_AUX# [52] CPU_EDP_AUX [52]

DDIP1_AUXN [43]

DDIP1_AUXP [43]

DDIP2_AUXN [46]

DDIP2_AUXP [46]

DDIP1_HPD [43,45] DDIP2_HPD [46]

CPU_EDP_HPD [52]

ENBKL [77] PCH_EDP_PWM [52]

PCH_ENVDD [52]

1 2

RC103 100K_0402_5%

1 2

RC57 100K_0402_5%

1 2

RC58 100K_0402_5%

1 2

RC59 100K_0402_5%

CPU_DDI1_N0[43] CPU_DDI1_P0[43]

DDIP1_CTRLCLK[43,45]

DDIP1_CTRLDATA[43,45]

DDIP2_CTRLCLK[44]

DDIP2_CTRLDATA[44]

CPU_DDI1_N1[43] CPU_DDI1_P1[43] CPU_DDI1_N2[43] CPU_DDI1_P2[43] CPU_DDI1_N3[43] CPU_DDI1_P3[43]

CPU_DDI2_N0[46] CPU_DDI2_P0[46] CPU_DDI2_N1[46] CPU_DDI2_P1[46] CPU_DDI2_N2[46] CPU_DDI2_P2[46] CPU_DDI2_N3[46] CPU_DDI2_P3[46]

1 2

24.9_0402_1%

RC1

MINI DP

C C

B B

DOCKING & D-SUB

MINI-DP

DOCKING

+VCC_IO

EDP_RCOMP

1. Trace width=20 mils, Spacing=25mil, Max length=100mils

2. RC1 close to MCP Trace Width=20mil, Spacing=25mil, Max length=100mil

CPU_DDI1_N0 CPU_DDI1_P0 CPU_DDI1_N1 CPU_DDI1_P1 CPU_DDI1_N2 CPU_DDI1_P2 CPU_DDI1_N3 CPU_DDI1_P3

CPU_DDI2_N0 CPU_DDI2_P0 CPU_DDI2_N1 CPU_DDI2_P1 CPU_DDI2_N2 CPU_DDI2_P2 CPU_DDI2_N3 CPU_DDI2_P3

DDIP1_CTRLCLK DDIP1_CTRLDATA

DDIP2_CTRLCLK DDIP2_CTRLDATA

EDP_COMP

UC1A

E55

DDI1_TXN[0]

F55

DDI1_TXP[0]

E58

DDI1_TXN[1]

F58

DDI1_TXP[1]

F53

DDI1_TXN[2]

G53

DDI1_TXP[2]

F56

DDI1_TXN[3]

G56

DDI1_TXP[3]

C50

DDI2_TXN[0]

D50

DDI2_TXP[0]

C52

DDI2_TXN[1]

D52

DDI2_TXP[1]

A50

DDI2_TXN[2]

B50

DDI2_TXP[2]

D51

DDI2_TXN[3]

C51

DDI2_TXP[3]

L13

GPP_E18/DDPB_CTRLCLK

L12

GPP_E19/DDPB_CTRLDATA

N7

GPP_E20/DDPC_CTRLCLK

N8

GPP_E21/DDPC_CTRLDATA

N11

GPP_E22/DDPD_CTRLCLK

N12

GPP_E23/DDPD_CTRLDATA

E52

EDP_RCOMP

SKYLAKE-U_BGA1356

+3VS

RC12 2.2K_0402_5%@ RC13 2.2K_0402_5%

RC49 2.2K_0402_5%@ RC52 2.2K_0402_5%

DDIP2_HPD : PS8338B has Int.PD 150K

DP port

DDPB_CTRLDATA

DDPC_CTRLDATA

Enable Disable

pull-high

no connect

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2015/01/12

LC Future Center Secret Data

Deciphered Date

2

2016/01/12

Title

KBL_DDI/eDP

Size

Document Number Rev

Custom

Friday, November 04, 2016

Date: Sheet of

Friday, November 04, 2016

DL470_NM-B021

1

5 99

0.2

5

4

3

2

1

DDR_A_MA0

D D

DDR_A_D[63..0][23]

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21

C C

B B

DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

UC1B

AL71

DDR0_DQ[0]

AL68

DDR0_DQ[1]

AN68

DDR0_DQ[2]

AN69

DDR0_DQ[3]

AL70

DDR0_DQ[4]

AL69

DDR0_DQ[5]

AN70

DDR0_DQ[6]

AN71

DDR0_DQ[7]

AR70

DDR0_DQ[8]

AR68

DDR0_DQ[9]

AU71

DDR0_DQ[10]

AU68

DDR0_DQ[11]

AR71

DDR0_DQ[12]

AR69

DDR0_DQ[13]

AU70

DDR0_DQ[14]

AU69

DDR0_DQ[15]

BB65

DDR0_DQ[16]/DDR0_DQ[32]

AW65

DDR0_DQ[17]/DDR0_DQ[33]

AW63

DDR0_DQ[18]/DDR0_DQ[34]

AY63

DDR0_DQ[19]/DDR0_DQ[35]

BA65

DDR0_DQ[20]/DDR0_DQ[36]

AY65

DDR0_DQ[21]/DDR0_DQ[37]

BA63

DDR0_DQ[22]/DDR0_DQ[38]

BB63

DDR0_DQ[23]/DDR0_DQ[39]

BA61

DDR0_DQ[24]/DDR0_DQ[40]

AW61

DDR0_DQ[25]/DDR0_DQ[41]

BB59

DDR0_DQ[26]/DDR0_DQ[42]

AW59

DDR0_DQ[27]/DDR0_DQ[43]

BB61

DDR0_DQ[28]/DDR0_DQ[44]

AY61

DDR0_DQ[29]/DDR0_DQ[45]

BA59

DDR0_DQ[30]/DDR0_DQ[46]

AY59

DDR0_DQ[31]/DDR0_DQ[47]

AY39

DDR0_DQ[32]/DDR1_DQ[0]

AW39

DDR0_DQ[33]/DDR1_DQ[1]

AY37

DDR0_DQ[34]/DDR1_DQ[2]

AW37

DDR0_DQ[35]/DDR1_DQ[3]

BB39

DDR0_DQ[36]/DDR1_DQ[4]

BA39

DDR0_DQ[37]/DDR1_DQ[5]

BA37

DDR0_DQ[38]/DDR1_DQ[6]

BB37

DDR0_DQ[39]/DDR1_DQ[7]

AY35

DDR0_DQ[40]/DDR1_DQ[8]

AW35

DDR0_DQ[41]/DDR1_DQ[9]

AY33

DDR0_DQ[42]/DDR1_DQ[10]

AW33

DDR0_DQ[43]/DDR1_DQ[11]

BB35

DDR0_DQ[44]/DDR1_DQ[12]

BA35

DDR0_DQ[45]/DDR1_DQ[13]

BA33

DDR0_DQ[46]/DDR1_DQ[14]

BB33

DDR0_DQ[47]/DDR1_DQ[15]

AY31

DDR0_DQ[48]/DDR1_DQ[32]

AW31

DDR0_DQ[49]/DDR1_DQ[33]

AY29

DDR0_DQ[50]/DDR1_DQ[34]

AW29

DDR0_DQ[51]/DDR1_DQ[35]

BB31

DDR0_DQ[52]/DDR1_DQ[36]

BA31

DDR0_DQ[53]/DDR1_DQ[37]

BA29

DDR0_DQ[54]/DDR1_DQ[38]

BB29

DDR0_DQ[55]/DDR1_DQ[39]

AY27

DDR0_DQ[56]/DDR1_DQ[40]

AW27

DDR0_DQ[57]/DDR1_DQ[41]

AY25

DDR0_DQ[58]/DDR1_DQ[42]

AW25

DDR0_DQ[59]/DDR1_DQ[43]

BB27

DDR0_DQ[60]/DDR1_DQ[44]

BA27

DDR0_DQ[61]/DDR1_DQ[45]

BA25

DDR0_DQ[62]/DDR1_DQ[46]

BB25

DDR0_DQ[63]/DDR1_DQ[47]

SKYLAKE-U_BGA1356

REV = 1 @

SKL_ULT

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]

DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]

DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]

DDR0_DQSN[2]/DDR0_DQSN[4] DDR0_DQSP[2]/DDR0_DQSP[4] DDR0_DQSN[3]/DDR0_DQSN[5] DDR0_DQSP[3]/DDR0_DQSP[5] DDR0_DQSN[4]/DDR1_DQSN[0] DDR0_DQSP[4]/DDR1_DQSP[0] DDR0_DQSN[5]/DDR1_DQSN[1] DDR0_DQSP[5]/DDR1_DQSP[1] DDR0_DQSN[6]/DDR1_DQSN[4] DDR0_DQSP[6]/DDR1_DQSP[4] DDR0_DQSN[7]/DDR1_DQSN[5] DDR0_DQSP[7]/DDR1_DQSP[5]

DDR CH - A

DDR0_CKN[0] DDR0_CKP[0] DDR0_CKN[1] DDR0_CKP[1]

DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3]

DDR0_CS#[0] DDR0_CS#[1] DDR0_ODT[0] DDR0_ODT[1]

DDR0_MA[3] DDR0_MA[4]

DDR0_DQSN[0] DDR0_DQSP[0] DDR0_DQSN[1] DDR0_DQSP[1]

DDR0_ALERT#

DDR0_PAR

DDR_VREF_CA DDR0_VREF_DQ DDR1_VREF_DQ

DDR_VTT_CNTL

??2 OF 20

DDR_A_DDRCLK0_1866M#

AU53

DDR_A_DDRCLK0_1866M

AT53

DDR_A_DDRCLK1_1866M#

AU55

DDR_A_DDRCLK1_1866M

AT55

DDR_A_CKE0

BA56

DDR_A_CKE1

BB56 AW56 AY56

DDR_A_CS0#

AU45

DDR_A_CS1#

AU43

DDR_A_ODT0

AT45

DDR_A_ODT1

AT43

DDR_A_MA5

BA51

DDR_A_MA9

BB54

DDR_A_MA6

BA52

DDR_A_MA8

AY52

DDR_A_MA7

AW52

DDR_A_BG0

AY55

DDR_A_MA12

AW54

DDR_A_MA11

BA54

DDR_A_ACT_N

BA55

DDR_A_BG1

AY54

DDR_A_MA13

AU46

DDR_A_MA15

AU48

DDR_A_MA14

AT46

DDR_A_MA16

AU50

DDR_A_BA0

AU52

DDR_A_MA2

AY51

DDR_A_BA1

AT48

DDR_A_MA10

AT50

DDR_A_MA1

BB50

DDR_A_MA0

AY50

DDR_A_MA3

BA50

DDR_A_MA4

BB52

DDR_A_DQS#0

AM70

DDR_A_DQS0

AM69

DDR_A_DQS#1

AT69

DDR_A_DQS1

AT70

DDR_A_DQS#2

BA64

DDR_A_DQS2

AY64

DDR_A_DQS#3

AY60

DDR_A_DQS3

BA60

DDR_A_DQS#4

BA38

DDR_A_DQS4

AY38

DDR_A_DQS#5

AY34

DDR_A_DQS5

BA34

DDR_A_DQS#6

BA30

DDR_A_DQS6

AY30

DDR_A_DQS#7

AY26

DDR_A_DQS7

BA26

DDR_A_ALERT_N

AW50

DDR_A_PARITY

AT52

DDR4_VREF_CA_CPU_A

AY67

DDR4_VREF_DQ_CPU_A

AY68

DDR4_VREF_DQ_CPU_B

BA67

DDR_PG_CTRL

AW67

DDR_A_DDRCLK0_1866M# [23] DDR_A_DDRCLK0_1866M [23] DDR_A_DDRCLK1_1866M# [23] DDR_A_DDRCLK1_1866M [23]

DDR_A_CKE0 [23] DDR_A_CKE1 [23]

DDR_A_CS0# [23] DDR_A_CS1# [23] DDR_A_ODT0 [23] DDR_A_ODT1 [23]

DDR_A_BG0 [23]

DDR_A_ACT_N [23] DDR_A_BG1 [23]

DDR_A_BA0 [23] DDR_A_BA1 [23]

DDR_A_ALERT_N [23] DDR_A_PARITY [23]

DDR4_VREF_CA_CPU_A [23]

1

TC1

DDR4_VREF_DQ_CPU_B [24]

CC538

0.1U_0402_10V7-K @

DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 DDR_A_MA16

DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7

+3V_DDR

12

+1.2V

DDR_PG_CTRLDDR_PG_CTRL

1

12

@

2

RD31 10K_0402_5%

1

3

RD32 100K_0402_5%

@

SM_PG_CTRL

QD1 DTC115TMT2L_VMT3

+3VALW

12

R0601 100K_0402_5%

DDR_A_MA[0..16] [23]

DDR_A_DQS#[0..7] [23]

DDR_A_DQS[0..7] [23]

+2.5V

12

R0602 100K_0402_5%

@

SM_PG_CTRL [87]

+1.2V

+3VALW

UC2

NC11Vcc

2

A

3

GND

74AUP1G07GF_SOT891-6_1X1

@

2

RC515

@

0_0402_5%

12

2016/12/31

DDR_PG_CTRL

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2015/09/01

LC Future Center Secret Data

Deciphered Date

6 5

NC2

4

Y

Title

KBL(3/16):DDR4 CH.A

Size

Custom

Date: Sheet of

@

1 2

1

CC100

0.1U_0402_10V7-K@

2

Document Number Rev

DL470_NM-B021

Friday, November 04, 2016

RC500 100K_0402_5%

1

+3VS

@

1 2

RC516 100K_0402_5%

SM_PG_CTRL

6 99

0.2

5

D D

4

3

2

1

DDR_B_D[0..63][24]

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18

C C

B B

DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

UC1C

AF65

DDR1_DQ[0]/DDR0_DQ[16]

AF64

DDR1_DQ[1]/DDR0_DQ[17]

AK65

DDR1_DQ[2]/DDR0_DQ[18]

AK64

DDR1_DQ[3]/DDR0_DQ[19]

AF66

DDR1_DQ[4]/DDR0_DQ[20]

AF67

DDR1_DQ[5]/DDR0_DQ[21]

AK67

DDR1_DQ[6]/DDR0_DQ[22]

AK66

DDR1_DQ[7]/DDR0_DQ[23]

AF70

DDR1_DQ[8]/DDR0_DQ[24]

AF68

DDR1_DQ[9]/DDR0_DQ[25]

AH71

DDR1_DQ[10]/DDR0_DQ[26]

AH68

DDR1_DQ[11]/DDR0_DQ[27]

AF71

DDR1_DQ[12]/DDR0_DQ[28]

AF69

DDR1_DQ[13]/DDR0_DQ[29]

AH70

DDR1_DQ[14]/DDR0_DQ[30]

AH69

DDR1_DQ[15]/DDR0_DQ[31]

AT66

DDR1_DQ[16]/DDR0_DQ[48]

AU66

DDR1_DQ[17]/DDR0_DQ[49]

AP65

DDR1_DQ[18]/DDR0_DQ[50]

AN65

DDR1_DQ[19]/DDR0_DQ[51]

AN66

DDR1_DQ[20]/DDR0_DQ[52]

AP66

DDR1_DQ[21]/DDR0_DQ[53]

AT65

DDR1_DQ[22]/DDR0_DQ[54]

AU65

DDR1_DQ[23]/DDR0_DQ[55]

AT61

DDR1_DQ[24]/DDR0_DQ[56]

AU61

DDR1_DQ[25]/DDR0_DQ[57]

AP60

DDR1_DQ[26]/DDR0_DQ[58]

AN60

DDR1_DQ[27]/DDR0_DQ[59]

AN61

DDR1_DQ[28]/DDR0_DQ[60]

AP61

DDR1_DQ[29]/DDR0_DQ[61]

AT60

DDR1_DQ[30]/DDR0_DQ[62]

AU60

DDR1_DQ[31]/DDR0_DQ[63]

AU40

DDR1_DQ[32]/DDR1_DQ[16]

AT40

DDR1_DQ[33]/DDR1_DQ[17]

AT37

DDR1_DQ[34]/DDR1_DQ[18]

AU37

DDR1_DQ[35]/DDR1_DQ[19]

AR40

DDR1_DQ[36]/DDR1_DQ[20]

AP40

DDR1_DQ[37]/DDR1_DQ[21]

AP37

DDR1_DQ[38]/DDR1_DQ[22]

AR37

DDR1_DQ[39]/DDR1_DQ[23]

AT33

DDR1_DQ[40]/DDR1_DQ[24]

AU33

DDR1_DQ[41]/DDR1_DQ[25]

AU30

DDR1_DQ[42]/DDR1_DQ[26]

AT30

DDR1_DQ[43]/DDR1_DQ[27]

AR33

DDR1_DQ[44]/DDR1_DQ[28]

AP33

DDR1_DQ[45]/DDR1_DQ[29]

AR30

DDR1_DQ[46]/DDR1_DQ[30]

AP30

DDR1_DQ[47]/DDR1_DQ[31]

AU27

DDR1_DQ[48]

AT27

DDR1_DQ[49]

AT25

DDR1_DQ[50]

AU25

DDR1_DQ[51]

AP27

DDR1_DQ[52]

AN27

DDR1_DQ[53]

AN25

DDR1_DQ[54]

AP25

DDR1_DQ[55]

AT22

DDR1_DQ[56]

AU22

DDR1_DQ[57]

AU21

DDR1_DQ[58]

AT21

DDR1_DQ[59]

AN22

DDR1_DQ[60]

AP22

DDR1_DQ[61]

AP21

DDR1_DQ[62]

AN21

DDR1_DQ[63]

SKYLAKE-U_BGA1356

REV = 1 @

SKL_ULT

DDR1_CKN[0] DDR1_CKN[1] DDR1_CKP[0] DDR1_CKP[1]

DDR1_CKE[0] DDR1_CKE[1] DDR1_CKE[2] DDR1_CKE[3]

DDR1_CS#[0] DDR1_CS#[1] DDR1_ODT[0]

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]

DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]

DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]

DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]

DDR1_DQSN[0]/DDR0_DQSN[2] DDR1_DQSP[0]/DDR0_DQSP[2] DDR1_DQSN[1]/DDR0_DQSN[3] DDR1_DQSP[1]/DDR0_DQSP[3] DDR1_DQSN[2]/DDR0_DQSN[6] DDR1_DQSP[2]/DDR0_DQSP[6] DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQSP[3]/DDR0_DQSP[7] DDR1_DQSN[4]/DDR1_DQSN[2] DDR1_DQSP[4]/DDR1_DQSP[2] DDR1_DQSN[5]/DDR1_DQSN[3] DDR1_DQSP[5]/DDR1_DQSP[3]

DDR CH - B

DDR1_ODT[1]

DDR1_MA[3] DDR1_MA[4]

DDR1_DQSN[6] DDR1_DQSP[6] DDR1_DQSN[7] DDR1_DQSP[7]

DDR1_ALERT#

DRAM_RESET# DDR_RCOMP[0] DDR_RCOMP[1] DDR_RCOMP[2]

DDR1_PAR

??3 OF 20

DDR_B_DDRCLK0_1866M#

AN45

DDR_B_DDRCLK1_1866M#

AN46

DDR_B_DDRCLK0_1866M

AP45

DDR_B_DDRCLK1_1866M

AP46

DDR_B_CKE0

AN56

DDR_B_CKE1

AP55 AN55 AP53

DDR_B_CS0#

BB42

DDR_B_CS1#

AY42

DDR_B_ODT0

BA42

DDR_B_ODT1

AW42

DDR_B_MA5

AY48

DDR_B_MA9

AP50

DDR_B_MA6

BA48

DDR_B_MA8

BB48

DDR_B_MA7

AP48

DDR_B_BG0

AP52

DDR_B_MA12

AN50

DDR_B_MA11

AN48

DDR_B_ACT_N

AN53

DDR_B_BG1

AN52

DDR_B_MA13

BA43

DDR_B_MA15

AY43

DDR_B_MA14

AY44

DDR_B_MA16

AW44

DDR_B_BA0

BB44

DDR_B_MA2

AY47

DDR_B_BA1

BA44

DDR_B_MA10

AW46

DDR_B_MA1

AY46

DDR_B_MA0

BA46

DDR_B_MA3

BB46

DDR_B_MA4

BA47

DDR_B_DQS#0

AH66

DDR_B_DQS0

AH65

DDR_B_DQS#1

AG69

DDR_B_DQS1

AG70

DDR_B_DQS#2

AR66

DDR_B_DQS2

AR65

DDR_B_DQS#3

AR61

DDR_B_DQS3

AR60

DDR_B_DQS#4

AT38

DDR_B_DQS4

AR38

DDR_B_DQS#5

AT32

DDR_B_DQS5

AR32

DDR_B_DQS#6

AR25

DDR_B_DQS6

AR27

DDR_B_DQS#7

AR22

DDR_B_DQS7

AR21

DDR_B_ALERT_N

AN43

DDR_B_PARITY

AP43

DDR4_DRAMRST_N DDR4_DRAMRST_N

AT13

SM_RCOMP0

AR18

SM_RCOMP1

AT18

SM_RCOMP2

AU18

[KBL PDG]for DDR4 COMPENSATION DDR_RCOMP[0] Pull down 121 ohm resistor DDR_RCOMP[1] Pull down 80.6 ohm resistor DDR_RCOMP[2] Pull down 100 ohm resistor

DDR_B_DDRCLK0_1866M# [24] DDR_B_DDRCLK1_1866M# [24] DDR_B_DDRCLK0_1866M [24] DDR_B_DDRCLK1_1866M [24]

DDR_B_CKE0 [24] DDR_B_CKE1 [24]

DDR_B_CS0# [24] DDR_B_CS1# [24] DDR_B_ODT0 [24] DDR_B_ODT1 [24]

DDR_B_BG0 [24]

DDR_B_ACT_N [24] DDR_B_BG1 [24]

DDR_B_BA0 [24] DDR_B_BA1 [24]

DDR_B_ALERT_N [24] DDR_B_PARITY [24]

1 2

RC8 121_0402_1%

1 2

RC9 80.6_0402_1%

1 2

RC10 100_0402_1%

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15 DDR_B_MA16

DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7

+1.2V

RC501 470_0402_5%

1 2

RC502 0_0402_SM

1 2

DDR_B_MA[0..16] [24]

DDR_B_DQS#[0..7] [24]

DDR_B_DQS[0..7] [24]

DDR4_DRAMRST# [23,24]

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2015/09/01

LC Future Center Secret Data

Deciphered Date

2

2016/12/31

Title

KBL(4/16):DDR4 CH.B

Size

Document Number Rev

Custom

Date: Sheet of

DL470_NM-B021

Friday, November 04, 2016

7 99

1

7 99

0.2

5

D D

+VCC_STG

12

RC2 1K_0402_5%

12

RC61 1K_0402_1%

12

RC51 10K_0402_5%

RC3

1 2

499_0402_1%

VR_HOT#[77,85,93]

C C

H_THERMTRIP#[30]

EC_WAKE#[30,77]

VR_HOT#

RC62

1 2

@

0_0402_5%

RC54 0_0402_SM

1 2

+VCC_ST

+3V_PCH

4

H_PECI[77]

1 2

RC151 49.9_0402_1%

1 2

RC114 49.9_0402_1%

1 2

RC200 49.9_0402_1%

1 2

RC113 49.9_0402_1%

T1

T4 T6 T8 T10

1

CATERR# H_PECI VR_HOT#_R THRMTRIP#

XDP_BPM#0

1

XDP_BPM#1

1

XDP_BPM#2

1

XDP_BPM#3

1

EC_WAKE#_SUS

PROC_POPIRCOMP PCH_OPIRCOMP OPCE_RCOMP OPC_RCOMP

UC1D

D63

CATERR#

A54

PECI

C65

PROCHOT#

C63

THERMTRIP#

A65

SKTOCC#

C55

BPM#[0]

D55

BPM#[1]

B54

BPM#[2]

C56

BPM#[3]

A6

GPP_E3/CPU_GP0

A7

GPP_E7/CPU_GP1

BA5

GPP_B3/CPU_GP2

AY5

GPP_B4/CPU_GP3

AT16

PROC_POPIRCOMP

AU16

PCH_OPIRCOMP

H66

OPCE_RCOMP

H65

OPC_RCOMP

SKYLAKE-U_BGA1356

3

SKL_ULT

CPU MISC

4 OF 20REV = 1

JTAG

PROC_TCK

PROC_TDI PROC_TDO PROC_TMS

PROC_TRST#

PCH_JTAG_TCK

PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS

PCH_TRST#

JTAGX

B61 D60 A61 C60 B59

B56 D59 A56 C59 C61 A59

XDP_TCLK XDP_TDI XDP_TDO XDP_TMS XDP_TRST#

2

1 2

RC517 100_0402_5%

XDP@

RC518 51_0402_5%

XDP@

1 2

1

+VCC_ST

1

T63

1

T64

1

T65

1

T66

1

T67

B B

[KBL PDG FOR DCL DEBUG]

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2015/01/12

LC Future Center Secret Data

Deciphered Date

2

2016/01/12

Title

KBL_XDP/ JTAG

Size

Document Number Rev

Custom

Friday, November 04, 2016

Date: Sheet of

Friday, November 04, 2016

DL470_NM-B021

1

8 99

0.2

5

4

3

2

1

Near UC16M1

SPI_IO3_16MB SPI_IO3 SPI_CLK_16MB SPI_MOSI_IO0_16MB SPI_IO2_16MB

D D

C C

Functional Strap Definitions

RPC5

1 8

SPI_CLK

2 7

SPI_MOSI_IO0

3 6

SPI_IO2

4 5

33_0804_8P4R_5%

SD30000370T

+3V_PCH

RPC12

18 27 36 45

10K_0804_8P4R_5%

+3VS

RPC26

1 8 2 7 3 6 4 5

10K_0804_8P4R_5%

L:Disable Intel ME Crypto TLS cipher suite (no confidentiality). *H:Enable Intel ME Crypto Transport Layer Security (TLS) cipher suite (with confidentiality).Support Intel AMT with TLS and Intel SBA (Small Business Advantage) with TLS.

GPP_C2, Internal PD 20K

GPP_C2

GPP_C5, Internal PD 20K

B B

Reverse internal 1K PU high

+3V_SPI

RC33 1K_0402_1% RC34 1K_0402_1%

DOCK_ID0 DOCK_ID1 DOCK_ID2 DOCK_ID3

SERIRQ KBRST# EC_SCI#

1 2

RC306 1K_0402_5%

1 2

RC307 20K_0402_5%@

*L: LPC H: eSPI

GPP_C5

RC83 1K_0402_5%

1 2

RC350 20K_0402_5%

@ @

1 2 1 2

RC399

1K_0402_1%

@

C-LINK

To TPM IC

+3V_PCH

12

1K_0402_1% @

1 2

SPI_CLK[70] SPI_MOSI_IO0[70] SPI_MISO_IO1[70]

SPI_CS2#_TPM[70]

+3VALW_PCH

RC392

1 2

CL_DATA_WLAN[66] CL_RST_WLAN#[66]

CL_CLK_WLAN[66]

DOCK_ID1[44] DOCK_ID2[44] DOCK_ID3[44]

1

T17

DOCK_ID0[44]

EC_SCI#[77]

KBRST#[77] SERIRQ[70,77]

SPI_CLK SPI_MOSI_IO0 SPI_MISO_IO1 SPI_CS2#_TPM

JTAG ODT

SPI0_MOSI

SPI_MOSI_IO0

SPI_MISO_IO1

SPI_CLK SPI_MISO_IO1 SPI_MOSI_IO0 SPI_IO2 SPI_IO3 SPI_CS0#_16MB

SPI_CS2#_TPM

DOCK_ID1 DOCK_ID2 DOCK_ID3 DOCK_CAP_ID# DOCK_ID0 EC_SCI#

CL_CLK_WLAN CL_DATA_WLAN CL_RST_WLAN#

KBRST# SERIRQ

RC298 1K_0402_5% RC303 20K_0402_5%

RC308 1K_0402_5% RC309 20K_0402_5%@

UC1E

AV2

AW3

AV3

AW2

AU4 AU3 AU2 AU1

M2 M3

J4 V1 V2 M1

G3 G2 G1

AW13

AY11

SKYLAKE-U_BGA1356

1 2

@

1 2

@

RGB(128,255,128)

1 2

@

1 2

SPI - FLASH

SPI0_CLK SPI0_MISO SPI0_MOSI SPI0_IO2 SPI0_IO3 SPI0_CS0# SPI0_CS1# SPI0_CS2#

SPI - TOUCH

GPP_D1/SPI1_CLK GPP_D2/SPI1_MISO GPP_D3/SPI1_MOSI GPP_D21/SPI1_IO2 GPP_D22/SPI1_IO3 GPP_D0/SPI1_CS#

C LINK

CL_CLK CL_DATA CL_RST#

GPP_A0/RCIN# GPP_A6/SERIRQ

+3V_SPI

20121218

+3V_SPI

SKL_ULT

5 OF 20REV = 1

SMBUS, SMLINK

GPP_B23/SML1ALERT#/PCHHOT#

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

GPP_C6/SML1CLK

GPP_C7/SML1DATA

R7 R8 R10

R9 W2 W1

W3 V3 AM7

PCH_SMB_CLK PCH_SMB_DATA GPP_C2

PCH_SML0_CLK PCH_SML0_DAT GPP_C5

PCH_SML1CLK PCH_SML1DATA GPP_B23

PCH_SML0_CLK [60] PCH_SML0_DAT [60]

RC375 150K_0402_5%

LAN PHY

1 2

+3V_PCH

FOR DCI USE

LPC_AD0

LPC

GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

GPP_A8/CLKRUN#

AY13 BA13 BB13 AY12 BA12 BA11

AW9 AY9 AW11

LPC_AD1 LPC_AD2 LPC_AD3 LPC_FRAME# SUS_STAT#

PCH_PCI_CLK_R CLKRUN#

SMBus

PCH_SMB_CLK

PCH_SMB_DATA

EC and TPM Module debug port

1 2

RC26 22_0402_5%

1 2

RC48 8.2K_0402_5%

+3VS

2

G

6 1

S

D

QC1A

5

2N7002KDWH_SOT363-6

G

SB000013A00

3 4

S

D

QC1B 2N7002KDWH_SOT363-6

SB000013A00

PCH_SML0_DAT PCH_SML0_CLK

PCH_SMB_CLK PCH_SMB_DATA PCH_SML1CLK PCH_SML1DATA

DIMM1, DIMM2 CP, Security ROM

1 2

RC35 4.7K_0402_5%

1 2

RC36 4.7K_0402_5%

PM_SMB_CLK

PM_SMB_DAT

LPC_AD0 [77] LPC_AD1 [77] LPC_AD2 [77] LPC_AD3 [77] LPC_FRAME# [77]

1

T61

CLK_PCI_EC [77]

1

CV178

RF@

+3VS

RC30 499_0402_1% RC29 499_0402_1%

22P_0402_50V8-J

2

1 2 1 2

RPC6

1 8 2 7 3 6 4 5

10K_0804_8P4R_5%

PM_SMB_CLK [23,24,63]

PM_SMB_DAT [23,24,63]

+3VS

+3V_PCH

M3 Support, Intel LAN PHY, (Wireless LAN)

+3VM = +3V_SPI

1. VPRO : Q6, +3VLAW To +3VM

2. NVPRO : a. R17 and RC38, +3VALW to +3VM

+3V_SPI

1 2

+3VS

+3VM

A A

RC37 0_0402_5%@

1 2

RC38 0_0402_SM

+3V_SPI

0.085 A, 10mils

D100 RB520CM-30T2R_VMN2M2

1 2

VCC3_SUS_SPI

2

CC101

1

0.1U_0201_6.3V6-K

UC16M1

8

SPI_IO3_16MB SPI_CLK_16MB

2

SPI_MOSI_IO0_16MB

CC102

1

0.1U_0201_6.3V6-K

2

CC103 33P_0201_25V8-J

EMC@

1

VCC

7

/HOLD/RESET(IO3)

6

CLK

5

DI(IO0)

W25Q128FVSIQ_SO8

2

CC104 33P_0201_25V8-J

EMC@

1

DO(IO1)

/WP(IO2)

GND

1

/CS

2 3 4

R530 33_0402_5% RC504 33_0402_5%

2

CC105 33P_0201_25V8-J

EMC@

1

1 2 1 2

SPI_CS0#_16MB SPI_MISO_IO1SPI_MISO_IO1_16MB

SPI_IO2_16MB

PCH_SML1CLK EC_SMB_CK3

PCH_SML1DATA EC_SMB_DA3

+3VS

2

6 1

D

QC2A

5

2N7002KDWH_SOT363-6

G

SB000013A00

3 4

S

D

QC2B 2N7002KDWH_SOT363-6

SB000013A00

GPU, Thermal Sendor, Embedded Controller, G sensor

G

S

2N7002KDWH Vth= min 1V, max 2.5V ESD 2KV

EC_SMB_CK3 [30,69,70,77]

EC_SMB_DA3 [30,69,70,77]

Mirror Code, Close to SPI ROM (UC8M1).

Title

Security Classification

FSCE#[77] SPI_FMOSI#[77] SPI_FMISO[77] SPI_FSCK[77]

FSCE# SPI_FMOSI# SPI_FMISO

5

1 2

RE1 0_0402_SM

1 2

RE2 0_0402_SM

1 2

RE3 0_0402_SM

1 2

RE4 0_0402_SM

SPI_CS0#_16MB SPI_MOSI_IO0_16MB SPI_MISO_IO1_16MB SPI_CLK_16MBSPI_FSCK

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2015/01/12

LC Future Center Secret Data

Deciphered Date

2

2016/01/12

Title

KBL_LPC/SPI/SMBUS

Size

Document Number Rev

Custom

Friday, November 04, 2016

Date: Sheet of

Friday, November 04, 2016

DL470_NM-B021

1

9 99

0.2

5

4

3

2

1

GPP_B18, Internal PD 20K

*L: Disable “ No Reboot” mode H: Enable “ No Reboot” mode

GPP_B18 GPP_B22

D D

FN, F1, F4 PD 100K, BIOS need output "High" while act i ve

C C

RC98 1K_0402_5% RC97 20K_0402_5%

12

@

12

@

To VGA_CORE IC, RPC3.7

+3VS +3VS

RF_OFF#[66]

HP_JACK_IN[57]

TRACKP_ON#[63]

BT_ON[66]

@

TP1

@

TP2

F4_LED[65]

TPNL_EN[52]

VGA_ON[30,38,39,91]

GPP_B22, Internal PD 20K

*L: SPI H: LPC

RF_OFF# HP_JACK_IN

GPP_B18

TRACKP_ON#

BT_ON GPP_B22

PLANARID0 PLANARID1 PLANARID2 PLANARID3

UART2_RX

1

UART2_TX

1

F4_LED

TPNL_EN

VGA_ON

DGPU_HOLD_RST#

12

@

RC99 20K_0402_5%

1 2

@

RC100 20K_0402_5%

UC1F

LPSS ISH

AN8

GPP_B15/GSPI0_CS#

AP7

GPP_B16/GSPI0_CLK

AP8

GPP_B17/GSPI0_MISO

AR7

GPP_B18/GSPI0_MOSI

AM5

GPP_B19/GSPI1_CS#

AN7

GPP_B20/GSPI1_CLK

AP5

GPP_B21/GSPI1_MISO

AN5

GPP_B22/GSPI1_MOSI

AB1

GPP_C8/UART0_RXD

AB2

GPP_C9/UART0_TXD

W4

GPP_C10/UART0_RTS#

AB3

GPP_C11/UART0_CTS#

AD1

GPP_C20/UART2_RXD

AD2

GPP_C21/UART2_TXD

AD3

GPP_C22/UART2_RTS#

AD4

GPP_C23/UART2_CTS#

U7

GPP_C16/I2C0_SDA

U6

GPP_C17/I2C0_SCL

U8

GPP_C18/I2C1_SDA

U9

GPP_C19/I2C1_SCL

AH9

GPP_F4/I2C2_SDA

AH10

GPP_F5/I2C2_SCL

AH11

GPP_F6/I2C3_SDA

AH12

GPP_F7/I2C3_SCL

AF11

GPP_F8/I2C4_SDA

AF12

GPP_F9/I2C4_SCL

SKYLAKE-U_BGA1356

SKL_ULT

6 OF 20REV = 1

+3VS

1 2

RC505 10K_0402_5%DIS@

1 2

RC506 10K_0402_5%UMA@

GPP_D9 GPP_D10 GPP_D11 GPP_D12

GPP_D5/ISH_I2C0_SDA

GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA

GPP_D8/ISH_I2C1_SCL

GPP_F10/I2C5_SDA/ISH_I2C2_SDA GPP_F11/I2C5_SCL/ISH_I2C2_SCL

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL

GPP_D15/ISH_UART0_RTS#

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_C15/UART1_CTS#/ISH_UART1_CTS#

GPP_A18/ISH_GP0 GPP_A19/ISH_GP1 GPP_A20/ISH_GP2 GPP_A21/ISH_GP3 GPP_A22/ISH_GP4 GPP_A23/ISH_GP5

GPP_A12/BM_BUSY#/ISH_GP6

P2 P3 P4 P1

M4 N3

N1 N2

AD11 AD12

U1 U2 U3 U4

AC1 AC2 AC3 AB4

AY8 BA8 BB7 BA7 AY7 AW7 AP13

DISCRETE_PRESENCE

PCH_WWAN_RST#

CP_RESET# CP_BYPASS TP4RST

DISCRETE_PRESENCE

WWANRF_DISABLE#

GPP_D13

FN_LED F1_LED

WWAN_CFG1 WWAN_CFG2 WWAN_CFG3

PCH_WWAN_RST# [66]

CP_RESET# [63] CP_BYPASS [63] TP4RST [63]

WWANRF_DISABLE# [66]

GPP_D13 [58]

FN_LED [65]

F1_LED [65]

+3VALW

R517

R516

1 2

10K_0402_5%

WWAN_CFG1 [66,67] WWAN_CFG2 [66] WWAN_CFG3 [66,67]

Project/SKU ID

PLANARID3 (GPP_C11)

1

B B

1 2

PCH_PLT_RST#[15]

PLT_RST#[15,42,60,66,70,71,77]

+3V_PCH

+3VS

A A

+3V_PCH

1 2

R288 4.7K_0402_5%@

1 2

RC120 10K_0402_5%

1 2

RC121 4.7K_0402_5%

1 2

RC123 10K_0402_5%

1 2

RC124 10K_0402_5%@

1 2

RC125 10K_0402_5%

5

1 2

RC119 10K_0402_5%

RF_OFF#

VGA_ON BT_ON CP_BYPASS

WWANRF_DISABLE#

DGPU_HOLD_RST#

RC385 0_0402_5%@

RC386 0_0402_5%DIS@

4

1 2

DGPU_HOLD_RST#

1 2

RC60 0_0402_5%@

+3VS

5

2

P

B

4

Y

1

A

G

UC5

DIS@

TC7SZ08FU SC70-5

3

SA000067X00

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

PD 10K at GPU Pin

PLT_RST_VGA# [30,35,91]

2015/01/12

LC Future Center Secret Data

Deciphered Date

2

PLANARID0 PLANARID1 PLANARID2 PLANARID3

2016/01/12

1(RC65)

0

12

RC65 10K_0402_5%

12

RC69

@

10K_0402_5%

X

PLANARID2 (GPP_C10)

NVPRO SKU (RC70)

12

RC66

VPRO@

10K_0402_5%

12

RC70

NVPRO@

10K_0402_5%

Title

Size

Document Number Rev

Custom

Date: Sheet of

PLANARID1 (GPP_C9)

DIS (RC67)VPRO SKU (RC66)

UMA (RC71)

DIS@

UMA@

SKL_GPIO

Friday, November 04, 2016

PLANARID0 (GPP_C8)

15" (RC68)

14" (RC72)

12

RC67 10K_0402_5%

12

RC71 10K_0402_5%

DL470_NM-B021

1

+3VS

12

RC68

@

10K_0402_5%

12

RC72 10K_0402_5%

10 99

0.2

5

D D

4

3

2

1

PCH_HDA_BCLK[56] PCH_HDA_RST#[56] PCH_HDA_SDOUT[56] PCH_HDA_SYNC[56]

C C

GPP_B14, Internal PD 20K No Reboot on TCO Timer expiration pull-up to VCC3_3 through a 1~8.2KΩ resistor to disable this capability

B B

Processor Strapping 543016_543016_SKL_PDG_UY_1_0_pub P780

PCH_HDA_BCLK PCH_HDA_RST# HDA_RST# PCH_HDA_SDOUT PCH_HDA_SYNC HDA_SYNC

1

CV179

RF@

22P_0402_50V8-J

2

ME_FLASH[77]

PCH_BEEP

PCH_HDA_SDIN0

HDA_SDOUT

RPC2

1 8 2 7 3 6 4 5

33_0804_8P4R_5%

SD30000370T

1 2

RC21 0_0402_SM

1 2

@

RC376 8.2K_0402_5%

1 2

@

RC300 20K_0402_5%

1 2

@

RC297 1K_0402_5%

1 2

RC301 20K_0402_5%@

1 2

@

RC299 1K_0402_5%

1 2

RC302 20K_0402_5%@

HDA_BCLK HDA_SDOUT

+3VS

+VCC_IO

+VCC_HDA

UC1G

HDA_SYNC HDA_BCLK HDA_SDOUT

PCH_HDA_SDIN0[56]

PCH_BEEP[58]

PCH_HDA_SDIN0 HDA_RST#

PCH_BEEP

BA22 AY22 BB22 BA21 AY21

AW22

AY20

AW20

AK10

AW5

J5

AK7 AK6 AK9

H5 D7

D8 C8

AUDIO

HDA_SYNC/I2S0_SFRM HDA_BLK/I2S0_SCLK HDA_SDO/I2S0_TXD HDA_SDI0/I2S0_RXD HDA_SDI1/I2S1_RXD HDA_RST#/I2S1_SCLK GPP_D23/I2S_MCLK I2S1_SFRM I2S1_TXD

GPP_F1/I2S2_SFRM GPP_F0/I2S2_SCLK GPP_F2/I2S2_TXD GPP_F3/I2S2_RXD

GPP_D19/DMIC_CLK0 GPP_D20/DMIC_DATA0

GPP_D17/DMIC_CLK1 GPP_D18/DMIC_DATA1

GPP_B14/SPKR

SKYLAKE-U_BGA1356

SKL_ULT

7 OF 20REV = 1

SDIO/SDXC

GPP_G0/SD_CMD GPP_G1/SD_DATA0 GPP_G2/SD_DATA1 GPP_G3/SD_DATA2 GPP_G4/SD_DATA3

GPP_G5/SD_CD# GPP_G6/SD_CLK

GPP_A17/SD_PWR_EN#/ISH_GP7

GPP_G7/SD_WP

GPP_A16/SD_1P8_SEL

SD_RCOMP

GPP_F23

AB11 AB13 AB12 W12 W11 W10 W8 W7

BA9 BB9

AB7

AF13

1 2

R111 200_0402_1%

SC_DET#

SC_DET# [73]

+3V_PCH

A A

HDA_SYNC

5

1 2

RC356

1K_0402_5%

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2015/01/12

LC Future Center Secret Data

Deciphered Date

2

2016/01/12

Title

KBL_HDA/GPIO

Size

Document Number Rev

Custom

Friday, November 04, 2016

Date: Sheet of

Friday, November 04, 2016

DL470_NM-B021

1

11 99

0.2

5

4

3

2

1

8 OF 20REV = 1

SKL_ULT

SSIC / USB3

USB3_2_RXN/SSIC_1_RXN USB3_2_RXP/SSIC_1_RXP

USB3_2_TXN/SSIC_1_TXN USB3_2_TXP/SSIC_1_TXP

USB3_3_RXN/SSIC_2_RXN USB3_3_RXP/SSIC_2_RXP

USB3_3_TXN/SSIC_2_TXN USB3_3_TXP/SSIC_2_TXP

USB2

USB2_VBUSSENSE

GPP_E9/USB2_OC0# GPP_E10/USB2_OC1# GPP_E11/USB2_OC2# GPP_E12/USB2_OC3#

GPP_E4/DEVSLP0 GPP_E5/DEVSLP1 GPP_E6/DEVSLP2

GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2

GPP_E8/SATALED#

USB3_1_RXN USB3_1_RXP USB3_1_TXN USB3_1_TXP

USB3_4_RXN USB3_4_RXP USB3_4_TXN USB3_4_TXP

USB2N_1 USB2P_1

USB2N_2 USB2P_2

USB2N_3 USB2P_3

USB2N_4 USB2P_4

USB2N_5 USB2P_5

USB2N_6 USB2P_6

USB2N_7 USB2P_7

USB2N_8 USB2P_8

USB2N_9 USB2P_9

USB2N_10 USB2P_10

USB2_COMP

USB2_ID

SATA1_DEVSLP

SSD_DEVSLP1

USB3P1_RXN

H8

USB3P1_RXP

G8

USB3P1_TXN

C13

USB3P1_TXP

D13

USB3P2_RXN

J6

USB3P2_RXP

H6

USB3P2_TXN

B13

USB3P2_TXP

A13

USB3P3_RXN_DOCK

J10

USB3P3_RXP_DOCK

H10

USB3P3_TXN_DOCK

B15

USB3P3_TXP_DOCK

A15

USB3P4_RXN

E10

USB3P4_RXP

F10

USB3P4_TXN

C15

USB3P4_TXP

D15

USB20_N0

AB9

USB20_P0

AB10

USB20_N1

AD6

USB20_P1

AD7

USB20_N2

AH3

USB20_P2

AJ3

USB20_N3

AD9

USB20_P3

AD10

USB20_N4

AJ1

USB20_P4

AJ2

USB20_N5

AF6

USB20_P5

AF7

USB20_N6

AH1

USB20_P6

AH2

USB20_N7

AF8

USB20_P7

AF9

USB20_N8

AG1

USB20_P8

AG2

USB20_N9

AH7

USB20_P9

AH8 AB6

USBCOMP

AG3 AG4

USB_OC0#

A9

USB_OC1#

C9

USB_OC2#

D9

USB_OC3#

B9 J1

SATA1_DEVSLP

J2

SSD_DEVSLP1

J3 H2

H3 G4

H1

RC377 10K_0402_5%@

RC378 10K_0402_5%@

USB3P1_RXN [54] USB3P1_RXP [54] USB3P1_TXN [54] USB3P1_TXP [54]

USB3P2_RXN [54] USB3P2_RXP [54] USB3P2_TXN [54] USB3P2_TXP [54]

USB3P3_RXN_DOCK [44]

USB3P3_RXP_DOCK [44] USB3P3_TXN_DOCK [44] USB3P3_TXP_DOCK [44]

USB3P4_RXN [53]

USB3P4_RXP [53] USB3P4_TXN [53] USB3P4_TXP [53]

USB20_N0 [54] USB20_P0 [54]

USB20_N1 [54] USB20_P1 [54]

USB20_N2 [44] USB20_P2 [44]

USB20_N3 [53] USB20_P3 [53]

USB20_N4 [73] USB20_P4 [73]

USB20_N5 [66] USB20_P5 [66]

USB20_N6 [52] USB20_P6 [52]

USB20_N7 [73] USB20_P7 [73]

USB20_N8 [66] USB20_P8 [66]

USB20_N9 [52] USB20_P9 [52]

1 2

R121 113_0402_1%

1 2

RC403 1K_0402_5%@

1 2

RC404 1K_0402_5%@

USB_OC0# [54] USB_OC1# [53]

SATA1_DEVSLP [42]

SSD_DEVSLP1 [66]

+3VS

12

On Board (Right-Front)

On Board (Right-Back)

DOCKING

S/B (AOU Port)

On Board (Right-Front) On Board (Right-Back) DOCKING S/B (AOU Port) SMART CARD

BT

CAMERA

Finger Printer

WWAN Touch Panel

On Board (Right-Front) S/B (AOU Port)

12

R286

15K_0402_5%@

USB_OC0#

USB_OC1# USB_OC2# USB_OC3#

R287 15K_0402_5%@

+3VALW

R512

R2750

1 2

10K_0402_5%

RPC23

1 8 2 7 3 6 4 5

10K_0804_8P4R_5%

10K_0402_5%

-PE_DTCT [42]

-WWAN_PE_DTCT [67]

+3V_PCH

D D

PCIE_CRX_GTX_N0[35]

PCIE_CRX_GTX_P0[35] PCIE_CTX_C_GRX_N0[35] PCIE_CTX_C_GRX_P0[35]

PCIE_CRX_GTX_N1[35]

PCIE_CRX_GTX_P1[35] PCIE_CTX_C_GRX_N1[35] PCIE_CTX_C_GRX_P1[35]

PCIE_CRX_GTX_N2[35]

PCIE12_SATA2_CRX_DTX_N[66] PCIE12_SATA2_CRX_DTX_P[66] PCIE12_SATA2_CTX_DRX_N[66] PCIE12_SATA2_CTX_DRX_P[66]

PCIE8_SATA1_CRX_DTX_N[42] PCIE8_SATA1_CRX_DTX_P[42] PCIE8_SATA1_CTX_DRX_N[42] PCIE8_SATA1_CTX_DRX_P[42]

PCIE_CTX_C_GRX_N2[35] PCIE_CTX_C_GRX_P2[35]

PCIE_CTX_C_GRX_N3[35] PCIE_CTX_C_GRX_P3[35]

PCIE5_CTX_C_DRX_N[60] PCIE5_CTX_C_DRX_P[60]

PCIE6_CTX_C_DRX_N[71]

PCIE6_CTX_C_DRX_P[71]

PCIE9_CTX_C_DRX_N[66] PCIE9_CTX_C_DRX_P[66]

PCIE11_CRX_DTX_N[66] PCIE11_CRX_DTX_P[66] PCIE11_CTX_DRX_N[66] PCIE11_CTX_DRX_P[66]

PCIE_CRX_GTX_P2[35]

PCIE_CRX_GTX_N3[35]

PCIE_CRX_GTX_P3[35]

PCIE5_CRX_DTX_N[60]

PCIE5_CRX_DTX_P[60]

PCIE6_CRX_DTX_N[71]

PCIE6_CRX_DTX_P[71]

PCIE7_CRX_DTX_N[42] PCIE7_CRX_DTX_P[42]

PCIE7_CTX_DRX_N[42]

PCIE7_CTX_DRX_P[42]

PCIE9_CRX_DTX_N[66]

PCIE9_CRX_DTX_P[66]

DGPU_PWROK

GPU

LAN

C C

Card Reader

HDD

WLAN

+3VS

B B

1 2

RC85 10K_0402_5%

UMA@

DGPU_PWROK[38,91]

M.2 SSD

1 2

CC8 0.22U_0402_10V6-KDIS@

1 2

CC9 0.22U_0402_10V6-KDIS@

1 2

CC26 0.22U_0402_10V6-KDIS@

1 2

CC27 0.22U_0402_10V6-KDIS@

1 2

CC28 0.22U_0402_10V6-KDIS@

1 2

CC29 0.22U_0402_10V6-KDIS@

1 2

CC18 0.22U_0402_10V6-KDIS@

1 2

CC21 0.22U_0402_10V6-KDIS@

1 2

CC552 0.1U_0402_10V7-K

1 2

CC551 0.1U_0402_10V7-K

1 2

CC547 0.1U_0402_10V7-K

CC548

1 2

0.1U_0402_10V7-K

1 2

CC553 0.1U_0402_10V7-K

1 2

CC554 0.1U_0402_10V7-K

1 2

R122 100_0402_1%

TP3@ TP4@

PCIE_CRX_GTX_N0 PCIE_CRX_GTX_P0 PCIE1_CTX_DRX_N0 PCIE1_CTX_DRX_P0

PCIE_CRX_GTX_N1 PCIE_CRX_GTX_P1 PCIE2_CTX_DRX_N1 PCIE2_CTX_DRX_P1

PCIE_CRX_GTX_N2 PCIE_CRX_GTX_P2 PCIE3_CTX_DRX_N2 PCIE3_CTX_DRX_P2

PCIE_CRX_GTX_N3 PCIE_CRX_GTX_P3 PCIE4_CTX_DRX_N3 PCIE4_CTX_DRX_P3

PCIE5_CRX_DTX_N PCIE5_CRX_DTX_P PCIE5_CTX_DRX_N

PCIE5_CTX_DRX_P

PCIE6_CRX_DTX_N PCIE6_CRX_DTX_P PCIE6_CTX_DRX_N PCIE6_CTX_DRX_P

PCIE7_CRX_DTX_N PCIE7_CRX_DTX_P PCIE7_CTX_DRX_N PCIE7_CTX_DRX_P

PCIE8_SATA1_CRX_DTX_N

PCIE8_SATA1_CRX_DTX_P PCIE8_SATA1_CTX_DRX_N PCIE8_SATA1_CTX_DRX_P

PCIE9_CRX_DTX_N PCIE9_CRX_DTX_P PCIE9_CTX_DRX_N PCIE9_CTX_DRX_P

PCIE_RCOMP

XDP_PRDY_N

1

XDP_PREQ_N

1

PCIE11_CRX_DTX_N PCIE11_CRX_DTX_P PCIE11_CTX_DRX_N

PCIE11_CTX_DRX_P PCIE12_SATA2_CRX_DTX_N PCIE12_SATA2_CRX_DTX_P

PCIE12_SATA2_CTX_DRX_N PCIE12_SATA2_CTX_DRX_P

UC1H

PCIE/USB3/SATA

H13

PCIE1_RXN/USB3_5_RXN

G13

PCIE1_RXP/USB3_5_RXP

B17

PCIE1_TXN/USB3_5_TXN

A17

PCIE1_TXP/USB3_5_TXP

G11

PCIE2_RXN/USB3_6_RXN

F11

PCIE2_RXP/USB3_6_RXP

D16

PCIE2_TXN/USB3_6_TXN

C16

PCIE2_TXP/USB3_6_TXP

H16

PCIE3_RXN

G16

PCIE3_RXP

D17

PCIE3_TXN

C17

PCIE3_TXP

G15

PCIE4_RXN

F15

PCIE4_RXP

B19

PCIE4_TXN

A19

PCIE4_TXP

F16

PCIE5_RXN

E16

PCIE5_RXP

C19

PCIE5_TXN

D19

PCIE5_TXP

G18

PCIE6_RXN

F18

PCIE6_RXP

D20

PCIE6_TXN

C20

PCIE6_TXP

F20

PCIE7_RXN/SATA0_RXN

E20

PCIE7_RXP/SATA0_RXP

B21

PCIE7_TXN/SATA0_TXN

A21

PCIE7_TXP/SATA0_TXP

G21

PCIE8_RXN/SATA1A_RXN

F21

PCIE8_RXP/SATA1A_RXP

D21

PCIE8_TXN/SATA1A_TXN

C21

PCIE8_TXP/SATA1A_TXP

E22

PCIE9_RXN

E23

PCIE9_RXP

B23

PCIE9_TXN

A23

PCIE9_TXP

F25

PCIE10_RXN

E25

PCIE10_RXP

D23

PCIE10_TXN

C23

PCIE10_TXP

F5

PCIE_RCOMPN

E5

PCIE_RCOMPP

D56

PROC_PRDY#

D61

PROC_PREQ#

BB11

GPP_A7/PIRQA#

E28

PCIE11_RXN/SATA1B_RXN

E27

PCIE11_RXP/SATA1B_RXP

D24

PCIE11_TXN/SATA1B_TXN

C24

PCIE11_TXP/SATA1B_TXP

E30

PCIE12_RXN/SATA2_RXN

F30

PCIE12_RXP/SATA2_RXP

A25

PCIE12_TXN/SATA2_TXN

B25

PCIE12_TXP/SATA2_TXP

SKYLAKE-U_BGA1356

USB_OC0# USB_OC1#

2016/01/12

USB_OC2# USB_OC3#

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2015/01/12

LC Future Center Secret Data

Deciphered Date

2

Port 1, 2 Port 4 Unused. Unused. Unused.

Date: Sheet of

USB3.0 Port NO.

Pin.

USB2.0 Port NO.

Port 0, 1 Port 3

Default Port Mapping

Port 0, 1 Port 2, 3 Port 4, 5

Unused.

Title

KBL_PCIE/ SATA/ USB

Size

Document Number Rev

Custom

Friday, November 04, 2016

Port 6, 7

DL470_NM-B021

1

12 99

0.2

5

D D

4

3

2

1

UC1I

CSI-2

A36

CSI2_DN0

B36

CSI2_DP0

C38

CSI2_DN1

D38

CSI2_DP1

C36

CSI2_DN2

D36

CSI2_DP2

A38

CSI2_DN3

B38

CSI2_DP3

C31

CSI2_DN4

D31

CSI2_DP4

C33

CSI2_DN5

C C

D33 A31 B31 A33 B33

A29 B29 C28 D28 A27 B27 C27 D27

CSI2_DP5 CSI2_DN6 CSI2_DP6 CSI2_DN7 CSI2_DP7

CSI2_DN8 CSI2_DP8 CSI2_DN9 CSI2_DP9 CSI2_DN10 CSI2_DP10 CSI2_DN11 CSI2_DP11

SKYLAKE-U_BGA1356

B B

SKL_ULT

CSI2_CLKN0

CSI2_CLKP0

CSI2_CLKN1

CSI2_CLKP1

CSI2_CLKN2

CSI2_CLKP2

CSI2_CLKN3

CSI2_CLKP3

CSI2_COMP

GPP_D4/FLASHTRIG

EMMC

GPP_F13/EMMC_DATA0 GPP_F14/EMMC_DATA1 GPP_F15/EMMC_DATA2 GPP_F16/EMMC_DATA3 GPP_F17/EMMC_DATA4 GPP_F18/EMMC_DATA5 GPP_F19/EMMC_DATA6 GPP_F20/EMMC_DATA7

GPP_F21/EMMC_RCLK

GPP_F22/EMMC_CLK

GPP_F12/EMMC_CMD

EMMC_RCOMP

9 OF 20REV = 1

C37 D37 C32 D32 C29 D29 B26 A26

E13 B7

AP2 AP1 AP3 AN3 AN1 AN2 AM4 AM1

AM2 AM3 AP4

AT1

R33

1 2

200_0402_1%

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

2015/01/12

LC Future Center Secret Data

Deciphered Date

3

2016/01/12

Title

KBL_CS12/ EMMC

Size

Document Number Rev

A4

Friday, November 04, 2016

Date: Sheet of

2

Friday, November 04, 2016

DL470_NM-B021

13 99

1

0.2

5

D D

RTC External Circuit

+RTCBATT

+RTCBATT, +RTCVCC Trace width = 20mils

1 2

RC14 0_0402_SM

+RTCVCC

1

2

CC4

0.1U_0402_10V6-K

near CC59 for layout

+RTCVCC

4

RC15

1 2

20K_0402_5%

RC17

1 2

20K_0402_5%

PCH_RTCRST#

PCH_SRTCRST#

1 2 1 2

CC3 1U_0402_10V6-K

1 2 1 2

CC7 1U_0402_10V6-K

JCMOS1 @

JME1 @

3

2

1

RTC CrystalJCMOS, JME Set t i ng, Need Under DDR Door

PCH_XTAL24_IN

PCH_XTAL24_OUT

10P_0402_50V8-J

CC10

1

2

RC24

1 2

1M_0402_5%

YC2

1

GND1

GND2

2

24MHZ_10PF_8Y24000011

3

1

4

CC11 10P_0402_50V8-J

2

1 2

10M_0402_5%

YC1

1 2

32.768KHZ_9PF_9H03280012

1

CC5

5.6P_0402_50V8-D

2

RC16

PCH_RTCX1

PCH_RTCX2

1. Space > 15mils

2. No trace under crystal

3. Place on oppsosit side of MCP for temp influence

1

CC6

5.6P_0402_50V8-D

2

UC1J

C C

HDD

M.2 SSD

WLAN

LAN

VGA

CR

B B

+3VS

CLK_PCIE_HDD#[42] CLK_PCIE_HDD[42]

CLKREQ_PCIE0_HDD#[42]

CLK_PCIE_SSD#[66] CLK_PCIE_SSD[66] CLKREQ_PCIE1_SSD#[66]

CLK_PCIE_WLAN#[66] CLK_PCIE_WLAN[66] CLKREQ_PCIE2_WLAN#[66]

CLK_PCIE_LAN#[60] CLK_PCIE_LAN[60] CLKREQ_PCIE3_LAN#[60]

CLK_PCIE_VGA#[35] CLK_PCIE_VGA[35] CLKREQ_PCIE4_VGA#[30]

CLK_PCIE_CR#[71] CLK_PCIE_CR[71] CLKREQ_PCIE5_CR#[71]

UMA@

1 2

RC45 10K_0402_5%

DIS@

1 2

RC39 10K_0402_5%

CLK_PCIE_HDD# CLK_PCIE_HDD CLKREQ_PCIE0_HDD#

CLK_PCIE_SSD# CLK_PCIE_SSD CLKREQ_PCIE1_SSD#

CLK_PCIE_WLAN# CLK_PCIE_WLAN CLKREQ_PCIE2_WLAN#

CLK_PCIE_LAN# CLK_PCIE_LAN CLKREQ_PCIE3_LAN#

CLK_PCIE_VGA# CLK_PCIE_VGA CLKREQ_PCIE4_VGA#

CLK_PCIE_CR# CLK_PCIE_CR CLKREQ_PCIE5_CR#

CLKREQ_PCIE4_VGA#

D42

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0

AR10

GPP_B5/SRCCLKREQ0#

B42

CLKOUT_PCIE_N1

A42

CLKOUT_PCIE_P1

AT7

GPP_B6/SRCCLKREQ1#

D41

CLKOUT_PCIE_N2

C41

CLKOUT_PCIE_P2

AT8

GPP_B7/SRCCLKREQ2#

D40

CLKOUT_PCIE_N3

C40

CLKOUT_PCIE_P3

AT10

GPP_B8/SRCCLKREQ3#

B40

CLKOUT_PCIE_N4

A40

CLKOUT_PCIE_P4

AU8

GPP_B9/SRCCLKREQ4#

E40

CLKOUT_PCIE_N5

E38

CLKOUT_PCIE_P5

AU7

GPP_B10/SRCCLKREQ5#

SKYLAKE-U_BGA1356

+3VS

SKL_ULT

CLOCK SIGNALS

RPC24

1 8 2 7 3 6 4 5

10K_0804_8P4R_5%

10 OF 20REV = 1

CLKREQ_PCIE2_WLAN# CLKREQ_PCIE3_LAN# CLKREQ_PCIE1_SSD# CLKREQ_PCIE5_CR#

CLKOUT_ITPXDP_N

CLKOUT_ITPXDP_P

GPD8/SUSCLK

XTAL24_IN

XTAL24_OUT

XCLK_BIASREF

RTCX1 RTCX2

SRTCRST#

RTCRST#

CLKOUT_ITPXDP_N

F43

CLKOUT_ITPXDP_P

E43

SUSCLK_32K

BA17

PCH_XTAL24_IN

E37

PCH_XTAL24_OUT

E35

XCLK_BIASREF

E42

PCH_RTCX1

AM18

PCH_RTCX2

AM20

PCH_SRTCRST#

AN18

PCH_RTCRST#

AM16

+3VS

1 2

RC513 10K_0402_5%

1 1

1 2

T56 T57

R92

2.71K_0402_0.5%

SD00001LB1T

CLKREQ_PCIE0_HDD#

+1VALW

SUSCLK_32K [66]

to WLAN

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2015/01/12

LC Future Center Secret Data

Deciphered Date

2

2016/01/12

Title

KBL_RTC/ CLK

Size

Document Number Rev

Custom

Friday, November 04, 2016

Date: Sheet of

Friday, November 04, 2016

DL470_NM-B021

1

14 99

0.2

5

D D

4

3

2

1

+3VALW

12

R1501

4.7K_0402_5%

VCCST_PWRGD

1 2

PCH_PWROK[77]

C C

B B

VGATE[77,93]

GPU_WAKE#[30] PCH_LAN_WAKE#[60]

For vPRO LAN WAKE#

+3VALW

RC40 0_0402_SM

1 2

RC383 0_0402_5%@

1 2

RC64 0_0402_5%@

1 2

RC76 0_0402_SM

RPC9

1 8 2 7 3 6 4 5

10K_0804_8P4R_5%

SD300002P0T

RC74 10K_0402_5%

RC379 10K_0402_5%@ RC380 10K_0402_5%@ RC387 10K_0402_5%@

1 2

1 2 1 2 1 2

AC_PRESENT BATLOW# PCIE_WAKE#

For vPRO LAN WAKE#

EC_WAKE#_DSW

PM_SLP_S5# PCH_SLP_WLAN# PCH_SLP_LAN#

EC_RSMRST#

+3VS

RC47 10K_0402_5%@

+3VALW_PRIM

RC398 10K_0402_5%

RC53 10K_0402_5%

RC5 10K_0402_5%

PCH_PLT_RST#[10]

EC_RSMRST#[77]

1 2

R281 60.4_0402_1%

PCH_SYSPWROK[77]

1 2

RC382 0_0402_SM

1 2

RC55 0_0402_SM

PCIE_WAKE#[66]

LANPHYPC[60]

1 2

@

PCH_PLT_RST# SYS_RESET# EC_RSMRST#

H_CPUPWRGD

PCH_SYSPWROK PWROK DSW_PWROK

SUSWARN# SUSACK#

PCIE_WAKE# EC_WAKE#_DSW LANPHYPC

SYS_RESET#

EC_RSMRST#

H_CPUPWRGDH_CPUPWRGD

UC1K

AN10

GPP_B13/PLTRST#

B5

SYS_RESET#

AY17

RSMRST#

A68

PROCPWRGD

B65

VCCST_PWRGD

B6

SYS_PWROK

BA20

PCH_PWROK

BB20

DSW_PWROK

AR13

GPP_A13/SUSWARN#/SUSPWRDNACK

AP11

GPP_A15/SUSACK#

BB15

WAKE#

AM15

GPD2/LAN_WAKE#

AW17

GPD11/LANPHYPC

AT15

GPD7/RSVD

SKYLAKE-U_BGA1356

SKL_ULT

SYSTEM POWER MANAGEMENT

11 OF 20REV = 1

PCH_PLT_RST#

100K_0402_5%

12

RC50

GPP_B12/SLP_S0#

GPD4/SLP_S3# GPD5/SLP_S4#

GPD10/SLP_S5#

SLP_SUS# SLP_LAN#

GPD9/SLP_WLAN#

GPD6/SLP_A#

GPD3/PWRBTN#

GPD1/ACPRESENT

GPD0/BATLOW#

GPP_A11/PME#

GPP_B11/EXT_PWR_GATE#

INTRUDER#

GPP_B2/VRALERT#

1 2

RC42 0_0402_SM

UC4

1

NC

2

IN_A

3

GND

TC7SG17FE_SON5

PM_SLP_S0#

AT11

PM_SLP_S3#

AP15

PM_SLP_S4#

BA16

PM_SLP_S5#

AY16

PCH_SLP_SUS#

AN15

PCH_SLP_LAN#

AW15

PCH_SLP_WLAN#

BB17

PM_SLP_A#

AN16

PBTN_OUT#

BA15

AC_PRESENT

AY15 AU13

BATLOW#

AU11

PCH_INTRUDER#

AP16

EXT_PWR_GATE#

AM10 AM11

VRALERT#

1. must be always pulled-up to VCCRTC.

2. 1 = Enable DSW 3.3V-to-1.05V Integrated DeepSx Well (DSW) On-Die Voltage Regulator. This must always be pulled high on product i on boar ds.

@

VCC

OUT_Y

1

T50

PM_SLP_S3# [77] PM_SLP_S4# [77] PM_SLP_S5# [77]

PCH_SLP_SUS# [77] PCH_SLP_LAN# [77]

PCH_SLP_WLAN# [77] PM_SLP_A# [77]

PBTN_OUT# [77]

AC_PRESENT [77]

1 2

RC18 1M_0402_5%

EXT_PWR_GATE# [19]

1

T55

+3VALW

5

4

PLT_RST#

PM_SLP_S3# PM_SLP_S4# PM_SLP_S5#

+RTCVCC

PLT_RST# [10,42,60,66,70,71,77]

1 1 1

T51 T52 T53

Reserved for HW control

+VCC_ST

+3VALW

12

RC394

@

100K_0402_5%

1 2

VCCST_PG_EC

A A

SUSP#

RC395 0_0402_SM

1 2

RC396 0_0402_5%@

5

12

RC391 100K_0402_5%

61

D

2

G

Q13A 2N7002KDWH_SOT363-6

SB000013A00

S

12

RC390 1K_0402_5%

VCCST_PWRGD

34

D

5

G

4

Q13B 2N7002KDWH_SOT363-6

SB000013A00

S

RTC clock debounce

@

S3

SPVR310100_4P

2

1

3

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

PCH_INTRUDER#

2015/01/12

LC Future Center Secret Data

Deciphered Date

2

2016/01/12

Title

KBL_SYS / PM

Size

Document Number Rev

Custom

Friday, November 04, 2016

Date: Sheet of

Friday, November 04, 2016

DL470_NM-B021

1

15 99

0.2

5

D D

4

3

2

1

+VCC_ST +VCC_ST

Rpu1

12

RC373

@

100_0402_1%

VR_SVID_CLK VR_SVID_DAT

C C

B B

+VCC_CORE +VCC_CORE

A30 A34 A39

A44 AK33 AK35 AK37 AK38 AK40 AL33 AL37 AL40

AM32 AM33 AM35 AM37 AM38

G30

K32 AK32 AB62

P62

V62

H63

@ @

1

TP5 TP6

G61

1

AC63 AE63

AE62 AG62

AL63 AJ62

SKYLAKE-U_BGA1356

SKL_ULT

UC1L

CPU POWER 1 OF 4

VCC_A30 VCC_A34 VCC_A39 VCC_A44 VCC_AK33 VCC_AK35 VCC_AK37 VCC_AK38 VCC_AK40 VCC_AL33 VCC_AL37 VCC_AL40 VCC_AM32 VCC_AM33 VCC_AM35 VCC_AM37 VCC_AM38 VCC_G30

RSVD_K32 RSVD_AK32 VCCOPC_AB62

VCCOPC_P62 VCCOPC_V62

VCC_OPC_1P8_H63 VCC_OPC_1P8_G61 VCCOPC_SENSE

VSSOPC_SENSE VCCEOPIO_AE62

VCCEOPIO_AG62 VCCEOPIO_SENSE

VSSEOPIO_SENSE

VCC_G32 VCC_G33 VCC_G35 VCC_G37 VCC_G38 VCC_G40 VCC_G42

VCC_J30 VCC_J33 VCC_J37

VCC_J40 VCC_K33 VCC_K35 VCC_K37 VCC_K38 VCC_K40 VCC_K42 VCC_K43

VCC_SENSE VSS_SENSE

VIDALERT#

VIDSCK

VIDSOUT

VCCSTG_G20

12 OF 20REV = 1

G32 G33 G35 G37 G38 G40 G42 J30 J33 J37 J40 K33 K35 K37 K38 K40 K42 K43

E32 E33

B63 A63 D64

G20

VR_SVID_ALRT#_R VR_SVID_CLK VR_SVID_DAT

1 2

RC126 0_0402_SM

1 2

RC142 0_0402_SM

+VCC_STG

[SKL PDDG]Package Sensing Recommendations

1.Trace Length Match: <25mil

2.Space: >25mil

3.Trace impedance:50ohm

4.Sense traces should be referenced to a solid ground plane

5.Avoid crossing over plane splits

[SKL PDG]VIDSCK

Rpu2

12

RC372 100_0402_1%

VR_SVID_CLK [93] VR_SVID_DAT [93]

+VCC_ST

Rpu1

12

RC20

VR_SVID_ALRT#_R VR_SVID_ALRT#

+VCC_CORE

Rs1

1 2

RC19 220_0402_1%

12

RC128 100_0402_1%

12

RC143 100_0402_1%

56_0402_1%

VCC_SENSE [93]

VSS_SENSE [93]

[SKL PDG]VIDSOUT

[SKL PDG]VIDALERT#

VR_SVID_ALRT# [93]

[SKL PDG]SVID

1.Alert signal must be routed between Clk and Data signals to minimize Cross-Talk.

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2015/01/12

LC Future Center Secret Data

Deciphered Date

2

2016/01/12

Title

KBL_POWER_VCCCORE

Size

Document Number Rev

Custom

Friday, November 04, 2016

Date: Sheet of

Friday, November 04, 2016

DL470_NM-B021

1

16 99

0.2

5

D D

4

3

2

1

N70 N71 R63 R64 R65 R66 R67 R68 R69 R70 R71 T62 U65 U68 U71 W63 W64 W65 W66 W67 W68 W69 W70 W71 Y62

AK42 AK43 AK45 AK46 AK48 AK50 AK52 AK53 AK55 AK56 AK58 AK60 AK70 AL43 AL46 AL50 AL53 AL56 AL60 AM48 AM50 AM52 AM53 AM56 AM58 AU58 AU63 BB57 BB66

AK62 AL61

+VCC_GT

A48 A53 A58 A62

A66 AA63 AA64 AA66 AA67 AA69 AA70 AA71 AC64 AC65 AC66 AC67

C C

+VCC_GT

B B

VCCGT_SENSE[93]

VSSGT_SENSE[93]

12

RC130 100_0402_1%

1 2

RC129 0_0402_SM

1 2

RC183 0_0402_SM

12

RC184 100_0402_1%

AC68 AC69 AC70 AC71

J43 J45 J46 J48 J50 J52 J53 J55 J56 J58

J60 K48 K50 K52 K53 K55 K56 K58 K60

L62

L63

L64

L65

L66

L67

L68

L69

L70

L71 M62 N63 N64 N66 N67 N69

J70

J69

SKL_ULT

UC1M

CPU POWER 2 OF 4

VCCGT_A48 VCCGT_A53 VCCGT_A58 VCCGT_A62 VCCGT_A66 VCCGT_AA63 VCCGT_AA64 VCCGT_AA66 VCCGT_AA67 VCCGT_AA69 VCCGT_AA70 VCCGT_AA71 VCCGT_AC64 VCCGT_AC65 VCCGT_AC66 VCCGT_AC67 VCCGT_AC68 VCCGT_AC69 VCCGT_AC70 VCCGT_AC71 VCCGT_J43 VCCGT_J45 VCCGT_J46 VCCGT_J48 VCCGT_J50 VCCGT_J52 VCCGT_J53 VCCGT_J55 VCCGT_J56 VCCGT_J58 VCCGT_J60 VCCGT_K48 VCCGT_K50 VCCGT_K52 VCCGT_K53 VCCGT_K55 VCCGT_K56 VCCGT_K58 VCCGT_K60 VCCGT_L62 VCCGT_L63 VCCGT_L64 VCCGT_L65 VCCGT_L66 VCCGT_L67 VCCGT_L68 VCCGT_L69 VCCGT_L70 VCCGT_L71 VCCGT_M62 VCCGT_N63 VCCGT_N64 VCCGT_N66 VCCGT_N67 VCCGT_N69

VCCGT_SENSE VSSGT_SENSE

SKYLAKE-U_BGA1356

VCCGT_N70 VCCGT_N71 VCCGT_R63 VCCGT_R64 VCCGT_R65 VCCGT_R66 VCCGT_R67 VCCGT_R68 VCCGT_R69 VCCGT_R70 VCCGT_R71

VCCGT_T62 VCCGT_U65 VCCGT_U68 VCCGT_U71

VCCGT_W63 VCCGT_W64 VCCGT_W65 VCCGT_W66 VCCGT_W67 VCCGT_W68 VCCGT_W69 VCCGT_W70 VCCGT_W71

VCCGT_Y62

VCCGTX_AK42 VCCGTX_AK43 VCCGTX_AK45 VCCGTX_AK46 VCCGTX_AK48 VCCGTX_AK50 VCCGTX_AK52 VCCGTX_AK53 VCCGTX_AK55 VCCGTX_AK56 VCCGTX_AK58 VCCGTX_AK60 VCCGTX_AK70 VCCGTX_AL43 VCCGTX_AL46 VCCGTX_AL50 VCCGTX_AL53 VCCGTX_AL56

VCCGTX_AL60 VCCGTX_AM48 VCCGTX_AM50 VCCGTX_AM52 VCCGTX_AM53 VCCGTX_AM56 VCCGTX_AM58

VCCGTX_AU58

VCCGTX_AU63

VCCGTX_BB57

VCCGTX_BB66

VCCGTX_SENSE VSSGTX_SENSE

13 OF 20REV = 1

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2015/01/12

LC Future Center Secret Data

Deciphered Date

2

2016/01/12

Title

KBL_POWER_VCCGT

Size

Document Number Rev

Custom

Friday, November 04, 2016

Date: Sheet of

Friday, November 04, 2016

DL470_NM-B021

1

17 99

0.2

5

4

3

2

1

D D

[SKL PDG]VDDQ

[SKL PDG]10uF x6, 1uF x4

+1.2V

SKL_ULT

1U_0402_10V6K

1

2

UC1N

AU23

VDDQ_AU23

AU28

VDDQ_AU28

AU35

VDDQ_AU35

AU42

VDDQ_AU42

BB23

VDDQ_BB23

BB32

VDDQ_BB32

BB41

VDDQ_BB41

BB47

VDDQ_BB47

BB51

VDDQ_BB51

AM40

VDDQC

A18

VCCST

A22

VCCSTG_A22

AL23

VCCPLL_OC

K20

VCCPLL_K20

K21

VCCPLL_K21

SKYLAKE-U_BGA1356

CPU POWER 3 OF 4

VCCIO_AK28 VCCIO_AK30 VCCIO_AL30

VCCIO_AL42 VCCIO_AM28 VCCIO_AM30 VCCIO_AM42

VCCSA_AK23 VCCSA_AK25

VCCSA_G23 VCCSA_G25 VCCSA_G27 VCCSA_G28

VCCSA_J22 VCCSA_J23

VCCSA_J27 VCCSA_K23 VCCSA_K25 VCCSA_K27 VCCSA_K28 VCCSA_K30

VCCIO_SENSE

VSSIO_SENSE

VSSSA_SENSE

VCCSA_SENSE

14 OF 20REV = 1

10U_0402_6.3V6-M

C210

C209

C C

B B

+VCC_SFR

[SKL PDG]VCCSTG

[SKL PDG]1uF x1

CC94

CD@

[SKL PDG]VDDQC

[SKL PDG]1uF x1

+VCC_SFROC

+VCC_STG +VCC_ST +VCC_SFR

1U_0402_10V6K

CC84

1

2

[SKL PDG]VCCST

[SKL PDG]1uF x1

+1.2V

10U_0402_6.3V6-M

1

2

+1.2V

1U_0201_6.3V6-M

C344

1

2

Primary side cap

[SKL PDG]VCCPLL

[SKL PDG]1uF x1

1

2

+VCC_STG

C340

1

2

RC293 0_0603_SM

1 2

1

2

+VCC_ST

CC83

1U_0201_6.3V6-M

C341

1

2

1U_0402_10V6K

1

2

+VCC_SFROC

C348

1U_0201_6.3V6-M

C342

1

2

+1.2V

+VCC_ST

Primary side capPrimary side cap

[SKL PDG]VCCPLL

[SKL PDG]1uF x1

1U_0201_6.3V6-M

1

2

1U_0201_6.3V6-M

C343

1 2

1U_0201_6.3V6-M

1

2

RC197 0_0603_SM

CC86

AK28 AK30 AL30 AL42 AM28 AM30 AM42

AK23 AK25 G23 G25 G27 G28 J22 J23 J27 K23 K25 K27 K28 K30

AM23 AM22

H21 H20

+VCC_IO

VCCIO_SENSE VSSIO_SENSE

+VCC_SA

[SKL PDG]VCCIO

[SKL PDG]10uF x2, 1uF x4

10U_0402_6.3V6-M

C211

C212

1

2

+VCC_SA

RC192 100_0402_1% RC189 100_0402_1%

RC127 0_0402_SM RC185 0_0402_SM

12

RC370 100_0402_1%

VCCSA_SENSE

VSSSA_SENSE

12

RC369 100_0402_1%

1U_0201_6.3V6-M

C337

C336

1

2

CD@

[SKL PDG]VCCSA

[SKL PDG]10uF x7, 1uF x7

10U_0402_6.3V6-M

C214

C213

1

2

CD@

10U_0402_6.3V6-M

C224

C223

1

2

1 2 1 2

1U_0201_6.3V6-M

C338

1

2

CD@

10U_0402_6.3V6-M

C215

1

2

CD@

10U_0402_6.3V6-M

C225

1

2

C339

1

2

10U_0402_6.3V6-M

C216

1

2

10U_0402_6.3V6-M

C329

1

2

VSSSA_SENSE VCCSA_SENSE

1U_0201_6.3V6-M

1

2

10U_0402_6.3V6-M

1

2

1U_0201_6.3V6-M

C330

1

2

+VCC_IO

Power Rail

1U_0201_6.3V6-M

C331

C332

1

2

VCC

1U_0201_6.3V6-M

C333

C334

1

2

CD@

VSSSA_SENSE [93]

VCCSA_SENSE [93]

1U_0201_6.3V6-M

C335

1

2

CD@

Description

Processor IA Cores Power Rail

Control

SVID VccGT SVIDProcessor Graphics Power Rails VccGTX Processor Graphics Extended Power Rail

Available only for GT3/GT4 processor SKUs

SVID

SVIDSystem Agent Power RailVccSA

FixedIO Power RailVccIO VccST Sustain Power Rail Fixed VccPLL Processor PLLs power rail Fixed VDDQ Integrated Memory Controller Power Rail Fixed VccOPC Fixed

VccOPC_1P8 Processor OPC power rail (available only

A A

VccEOPIO Processor OPC power rail (available only

Processor OPC power rail (available only in SKU’ s with OPC)

in SKU’ s with OPC)

Fixed

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2015/01/12

LC Future Center Secret Data

Deciphered Date

2

2016/01/12

Title

KBL_POWER_VCCIO/SA

Size

Document Number Rev

Custom

Friday, November 04, 2016

Date: Sheet of

Friday, November 04, 2016

DL470_NM-B021

1

18 99

0.2

5

4

3

2

1

0.1U_0402_10V6-K

1

CC99

2

Near AG15 Near T16Near Y16

+1.8VALW_PCH

+3VALW_PRIM

+1.8VALW_PCH +3VALW_RTCPRIM +RTCVCC

1 2

LC3 0_0603_SM

1 2

LC4 0_0603_SM

1 2

LC5 0_0603_SM

1

T58

1

T59

1U_0402_10V6K

1

CC530

2

VCC1R0_SUS

Thermal Sensor Primary Well 1.8 V

[SKL PDG]VccATS

[SKL PDG]1uF x1 [SKL PDG]Close AA1, Placement type:Edge<10mm(394mil)

D D

SRAM Primary Well 1.0 V. Dedicated SRAM rail and can have on board power down gate control.

+VCC_MPHYGT

1 2

RC139 0_0805_5%

[SKL PDG]VccSRAM

[SKL PDG]1uF x1 [SKL PDG]Close AF20, Placement type:Edge<10mm(394mil)

C C

B B

EXT_PWR_GATE#[15]

+VCC_MPHYGT

+VCC_SRAM +VCC_PLLEBB

1U_0402_10V6K

1

@

CC47

2

+3VALW

RC346 20K_0402_5%

1 2

RC321 0_0402_SM

[SKL PDG]VccAPLLEBB

[SKL PDG]1uF x1 [SKL PDG]Close N18, Placement type:Edge<3mm(118mil)

Reserve for Sense Resistor

1 2

RC173 0_0603_SM

1 2

RC341 0_0805_SM

1 2

RC176 0_0805_SM

@

RC343

0_0805_5%

+3VALW

+1VALW

+VCC_MPHYGT+1VALW

+VCC_AMPHYPLL

1U_0402_10V6K

+1.8VALW_PCH+1.8VALW

+3VALW_PCH+3VALW

+1VALW_PCH+1VALW

VccMPHYGT(Mod PHY Externally Gated Primary 1.0 V: Externally gated primary supply for PCIe/DMI/USB3/SATA/MIPI MPHY logic.)

1U_0402_10V6K

1

@

CC46

2

U5

VDD1S1 ON7S2

2

D1

3

D2

SLG59M1470VTR_FC-TDFN9_1P5X2

+VCC_MPHYGT

1

[SKL PDG]VccMPHYGT

CC52

[SKL PDG]1uF x1 [SKL PDG]Close N15,

2

Placement type:Edge<3mm(118mil)

[SKL PDG]47uF x1 [SKL PDG]Close N15, Placement type:Edge<10mm(394mil)

Mod PHY Always On Primary 1.0 V: Always on primary supply for PCIe/DMI/USB3/SATA/MIPI MPHY logic

[SKL PDG]VccMPHYAON

[SKL PDG]1uF x1 [SKL PDG]Close K17, Placement type:Edge<3mm(118mil)

Primary Well 1.0 V: For I/O blocks, ungated ISH SRAM power, USB AFE Digital Logic, JTAG, Thermal Sensor and MIPI DPHY.

+1VALW_PCH

RC318 0_0402_5%@

[SKL PDG]VCCPRIM

[SKL PDG]1uF x1 [SKL PDG]Close AB19, Placement type:Edge<10mm(394mil)

4

@

5

6

GND

1 2

RC137 0.01_1206_1%

1 2

+VCC_MPHYGT

+1VALW_1P0

close to N15

1U_0402_10V6K

47U_0805_6.3V6-M

@

1

12

CC50

C194

2

+1VALW_PCH

1U_0402_10V6K

1

CC49

2

VCC1R0_SUS

1U_0402_10V6K

1

CC95

2

Core Logic Primary Well: This rail scales from 0.85 V to 1.0 V.

+1VALW_PCH

RC304 0_0805_5%@

[SKL PDG]VccPRIM_Core

[SKL PDG]1uF x1 [SKL PDG]Close AF18, Placement type:Edge<10mm(394mil)

LC1 0_0603_SM

+VCC_MPHYGT

LC2 0_0603_SM

+1VALW_PCH

0.1U_0402_10V6-K

1

RF@

CC535

2

LAYOUT near to CPU side

1 2

0603 Footprint

1 2

0603 Footprint

1 2

VCC1R0_SUS

1U_0402_10V6K

+1VALW_PCH

+1VALW_1P0

0.1U_0402_10V6-K

1

CC96

2

VCC1R0_SUS

+1VALW_PCH

+1VALW_1P0

+VCC_AMPHYPLL

+1VALW_PLL

+VCC_DSW3P3

+VCC_HDA

1

+3V_SPI

RF@

CC534

+VCC_SRAM

2

+3VALW_PRIM VCC1R0_SUS +VCC_PLLEBB

Primary Well 3.3 V

+3VALW_PCH

[SKL PDG]VCCPRIM

[SKL PDG]1uF x1 [SKL PDG]Close V19, Placement type:Edge<3mm(118mil)

+DCPDSW

1 2

RC326 0_0402_SM

UC1O

AB19

VCCPRIM_1P0_AB19

AB20

VCCPRIM_1P0_AB20

P18

VCCPRIM_1P0_P18

AF18

VCCPRIM_CORE_AF18

AF19

VCCPRIM_CORE_AF19

V20

VCCPRIM_CORE_V20

V21

VCCPRIM_CORE_V21

AL1

DCPDSW_1P0

K17

VCCMPHYAON_1P0_K17

L1

VCCMPHYAON_1P0_L1

N15

VCCMPHYGT_1P0_N15

N16

VCCMPHYGT_1P0_N16

N17

VCCMPHYGT_1P0_N17

P15

VCCMPHYGT_1P0_P15

P16

VCCMPHYGT_1P0_P16

K15

VCCAMPHYPLL_1P0_K15

L15

VCCAMPHYPLL_1P0_L15

V15

VCCAPLL_1P0

AB17

VCCPRIM_1P0_AB17

Y18

VCCPRIM_1P0_Y18

AD17

VCCDSW_3P3_AD17

AD18

VCCDSW_3P3_AD18

AJ17

VCCDSW_3P3_AJ17

AJ19

VCCHDA

AJ16

VCCSPI

AF20

VCCSRAM_1P0_AF20

AF21

VCCSRAM_1P0_AF21

T19

VCCSRAM_1P0_T19

T20

VCCSRAM_1P0_T20

AJ21

VCCPRIM_3P3_AJ21

AK20

VCCPRIM_1P0_AK20

N18

VCCAPLLEBB

SKYLAKE-U_BGA1356

+3VALW_PRIM

SKL_ULT

CPU POWER 4 OF 4

1U_0402_10V6K

1

CC97

2

+3VALW_PCH

AK15

VCCPGPPA

AG15

VCCPGPPB

Y16

VCCPGPPC

Y15

VCCPGPPD

T16

VCCPGPPE

AF16

VCCPGPPF

AD15

VCCPGPPG

V19

VCCPRIM_3P3_V19

T1

VCCPRIM_1P0_T1

AA1

VCCATS_1P8

AK17

VCCRTCPRIM_3P3

AK19

VCCRTC_AK19

BB14

VCCRTC_BB14

BB10

DCPRTC

A14

VCCCLK1

K19

VCCCLK2

L21

VCCCLK3

N20

VCCCLK4

L19

VCCCLK5

A10

VCCCLK6

AN11

GPP_B0/CORE_VID0

AN13

GPP_B1/CORE_VID1

15 OF 20REV = 1

HD Audio Power 3.3 V, 1.8 V, 1.5 V. For Intel High Definition Audio.

+1.8VALW_PCH

1 2

RC331 0_0402_5%@

1 2

RC330 0_0402_SM

[SKL PDG]VccHDA

[SKL PDG]1uF x1 [SKL PDG]Close AJ19, Placement type:Edge<10mm(394mil)

+DCPRTC

+1VALW_CLK2

+1VALW_CLK4 +1VALW_CLK5

[SKL PDG]The CORE_VID[0:1] signal is used by external VRs to indicate the final settling voltage for VCCPRIM_CORE rail.

+VCC_HDA

CC531

0603 Footprint

1U_0402_10V6K

1

CC532

2

+1VALW_PCH

+3VALW_PCH

Deep Sx Well 1.0 V: This rail is generated by on die DSW low dropout (LDO) linear voltage regulator to supply DSW

+1.8VALW_PCH

GPIOs, DSW core logic and DSW USB2 logic. Board needs to connect 1 uF capacitor to this rail and power should NOT be driven from the board. When primary well power is up, this rail is bypassed from VCCPRIM_1p0.

1U_0402_10V6K

1

CC61

2

[SKL PDG]DcpDSW

[SKL PDG]1uF x1 [SKL PDG]Close AL1, Placement type:Edge<3mm(118mil)

RTC Logic Primary Well 3.3 V. This power supplies the RTC internal VRM. It will be off during Deep Sx mode.

+3VALW_PCH

[SKL PDG]VccRTCPRIM

[SKL PDG]1uF x1,0.1uF x2 [SKL PDG]Close AK17, Placement type:Edge<3mm(118mil)

Deep Sx Well for GPD GPIOs and USB2

+3VALW_PCH

1 2

RC333 0_0402_SM

RC131 0_0402_5%@

+3VL

RC132 0_0402_SM

[SKL PDG]VccDSW

1U_0402_10V6K

+3VALW_RTCPRIM

1U_0402_10V6K

1 2

RTC de-coupling capacitor only. This rail should NOT be driven.

+DCPDSW

1

[SKL PDG]DcpRTC

CC60

[SKL PDG]0.1uF x1 [SKL PDG]Close BB10,

2

Placement type:Edge<3mm(118mil)

RTC Logic Primary Well 3.3 V. This power supplies the RTC internal VRM. It will be off during Deep Sx mode.

0.1U_0402_10V6-K

1

C200

C201

CC58

2

+VCC_DSW3P3

[SKL PDG]VccRTC

[SKL PDG]1uF x1 [SKL PDG]Close AK19, Placement type:Edge<3mm(118mil)

+DCPRTC

1

C197

0.1U_0402_10V6-K

2

+RTCVCC

1U_0402_10V6K

1

CC59

2

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2

2015/01/12

LC Future Center Secret Data

Deciphered Date

2016/01/12

Title

KBL_POWER_OTHERS

Size

Document Number Rev

D

Date: Sheet of

1

Friday, November 04, 2016

DL470_NM-B021

19 99

0.2

5

D D

SKL_ULT

UC1P

GND 1 OF 3

A5

VSS_A5

A67

VSS_A67

A70

VSS_A70

AA2

VSS_AA2

AA4

VSS_AA4

AA65

VSS_AA65

AA68

VSS_AA68

AB15

VSS_AB15

AB16

VSS_AB16

AB18

VSS_AB18

AB21

VSS_AB21

AB8

VSS_AB8

AD13

VSS_AD13

AD16

VSS_AD16

AD19

VSS_AD19

AD20

VSS_AD20

AD21

VSS_AD21

AD62

VSS_AD62

AD8

VSS_AD8

AE64

VSS_AE64

AE65

VSS_AE65

AE66

VSS_AE66

AE67

VSS_AE67

AE68

VSS_AE68

AE69

C C

B B

AF10 AF15 AF17

AF63 AG16 AG17 AG18 AG19 AG20 AG21 AG71 AH13

AH63 AH64 AH67

AJ15 AJ18 AJ20

AK11 AK16 AK18 AK21 AK22 AK27 AK63 AK68 AK69

AL28 AL32 AL35 AL38

AL45 AL48 AL52 AL55 AL58 AL64

AF1

AF2 AF4

AH6

AK8 AL2

AL4

AJ4

VSS_AE69 VSS_AF1 VSS_AF10 VSS_AF15 VSS_AF17 VSS_AF2 VSS_AF4 VSS_AF63 VSS_AG16 VSS_AG17 VSS_AG18 VSS_AG19 VSS_AG20 VSS_AG21 VSS_AG71 VSS_AH13 VSS_AH6 VSS_AH63 VSS_AH64 VSS_AH67 VSS_AJ15 VSS_AJ18 VSS_AJ20 VSS_AJ4 VSS_AK11 VSS_AK16 VSS_AK18 VSS_AK21 VSS_AK22 VSS_AK27 VSS_AK63 VSS_AK68 VSS_AK69 VSS_AK8 VSS_AL2 VSS_AL28 VSS_AL32 VSS_AL35 VSS_AL38 VSS_AL4 VSS_AL45 VSS_AL48 VSS_AL52 VSS_AL55 VSS_AL58 VSS_AL64

SKYLAKE-U_BGA1356

VSS_AL65

VSS_AL66 VSS_AM13 VSS_AM21 VSS_AM25 VSS_AM27 VSS_AM43 VSS_AM45 VSS_AM46 VSS_AM55 VSS_AM60 VSS_AM61 VSS_AM68 VSS_AM71

VSS_AM8 VSS_AN20 VSS_AN23 VSS_AN28 VSS_AN30 VSS_AN32 VSS_AN33 VSS_AN35 VSS_AN37 VSS_AN38 VSS_AN40 VSS_AN42 VSS_AN58 VSS_AN63

VSS_AP10 VSS_AP18 VSS_AP20 VSS_AP23 VSS_AP28 VSS_AP32 VSS_AP35 VSS_AP38 VSS_AP42 VSS_AP58 VSS_AP63 VSS_AP68

VSS_AP70 VSS_AR11 VSS_AR15 VSS_AR16 VSS_AR20 VSS_AR23 VSS_AR28 VSS_AR35 VSS_AR42 VSS_AR43 VSS_AR45 VSS_AR46 VSS_AR48

VSS_AR5 VSS_AR50 VSS_AR52 VSS_AR53 VSS_AR55 VSS_AR58 VSS_AR63

VSS_AR8

VSS_AT2 VSS_AT20 VSS_AT23 VSS_AT28 VSS_AT35

VSS_AT4 VSS_AT42 VSS_AT56 VSS_AT58

16 OF 20REV = 1

AL65 AL66 AM13 AM21 AM25 AM27 AM43 AM45 AM46 AM55 AM60 AM61 AM68 AM71 AM8 AN20 AN23 AN28 AN30 AN32 AN33 AN35 AN37 AN38 AN40 AN42 AN58 AN63 AP10 AP18 AP20 AP23 AP28 AP32 AP35 AP38 AP42 AP58 AP63 AP68 AP70 AR11 AR15 AR16 AR20 AR23 AR28 AR35 AR42 AR43 AR45 AR46 AR48 AR5 AR50 AR52 AR53 AR55 AR58 AR63 AR8 AT2 AT20 AT23 AT28 AT35 AT4 AT42 AT56 AT58

4

SKL_ULT

UC1Q

GND 2 OF 3

AT63

VSS_AT63

AT68

VSS_AT68

AT71

VSS_AT71

AU10

VSS_AU10

AU15

VSS_AU15

AU20

VSS_AU20

AU32

VSS_AU32

AU38

VSS_AU38

AV1

VSS_AV1

AV68

VSS_AV68

AV69

VSS_AV69

AV70

VSS_AV70

AV71

VSS_AV71

AW10

VSS_AW10

AW12

VSS_AW12

AW14

VSS_AW14

AW16

VSS_AW16

AW18

VSS_AW18

AW21

VSS_AW21

AW23

VSS_AW23

AW26

VSS_AW26

AW28

VSS_AW28

AW30

VSS_AW30

AW32

VSS_AW32

AW34

VSS_AW34

AW36

VSS_AW36

AW38

VSS_AW38

AW41

VSS_AW41

AW43

VSS_AW43

AW45

VSS_AW45

AW47

VSS_AW47

AW49

VSS_AW49

AW51

VSS_AW51

AW53

VSS_AW53

AW55

VSS_AW55

AW57

VSS_AW57

AW6

VSS_AW6

AW60

VSS_AW60

AW62

VSS_AW62

AW64

VSS_AW64

AW66

VSS_AW66

AW8

VSS_AW8

AY66

VSS_AY66

B10

VSS_B10

B14

VSS_B14

B18

VSS_B18

B22

VSS_B22

B30

VSS_B30

B34

VSS_B34

B39

VSS_B39

B44

VSS_B44

B48

VSS_B48

B53

VSS_B53

B58

VSS_B58

B62

VSS_B62

B66

VSS_B66

B71

VSS_B71

BA1

VSS_BA1

BA10

VSS_BA10

BA14

VSS_BA14

BA18

VSS_BA18

BA2

VSS_BA2

BA23

VSS_BA23

BA28

VSS_BA28

BA32

VSS_BA32

BA36

VSS_BA36

F68

VSS_F68

BA45

VSS_BA45

SKYLAKE-U_BGA1356

17 OF 20REV = 1

VSS_BA49 VSS_BA53 VSS_BA57

VSS_BA6 VSS_BA62 VSS_BA66 VSS_BA71 VSS_BB18 VSS_BB26 VSS_BB30 VSS_BB34 VSS_BB38 VSS_BB43 VSS_BB55

VSS_BB6 VSS_BB60 VSS_BB64 VSS_BB67 VSS_BB70

VSS_C1

VSS_C25

VSS_C5 VSS_D10 VSS_D11 VSS_D14 VSS_D18 VSS_D22 VSS_D25 VSS_D26 VSS_D30 VSS_D34 VSS_D39 VSS_D44 VSS_D45 VSS_D47 VSS_D48 VSS_D53 VSS_D58

VSS_D6 VSS_D62 VSS_D66 VSS_D69 VSS_E11 VSS_E15 VSS_E18 VSS_E21 VSS_E46 VSS_E50 VSS_E53 VSS_E56

VSS_E6 VSS_E65 VSS_E71

VSS_F1 VSS_F13

VSS_F2 VSS_F22 VSS_F23 VSS_F27 VSS_F28 VSS_F32 VSS_F33 VSS_F35 VSS_F37 VSS_F38

VSS_F4 VSS_F40 VSS_F42

VSS_BA41

3

BA49 BA53 BA57 BA6 BA62 BA66 BA71 BB18 BB26 BB30 BB34 BB38 BB43 BB55 BB6 BB60 BB64 BB67 BB70 C1 C25 C5 D10 D11 D14 D18 D22 D25 D26 D30 D34 D39 D44 D45 D47 D48 D53 D58 D6 D62 D66 D69 E11 E15 E18 E21 E46 E50 E53 E56 E6 E65 E71 F1 F13 F2 F22 F23 F27 F28 F32 F33 F35 F37 F38 F4 F40 F42 BA41

F8 G10 G22 G43 G45 G48

G5 G52 G55 G58

G6 G60 G63 G66

H15 H18 H71

J11 J13 J25 J28 J32 J35 J38 J42

J8 K16 K18 K22 K61 K63 K64 K65 K66 K67 K68 K70 K71 L11 L16 L17

2

SKL_ULT

UC1R

GND 3 OF 3

VSS_F8 VSS_G10 VSS_G22 VSS_G43 VSS_G45 VSS_G48 VSS_G5 VSS_G52 VSS_G55 VSS_G58 VSS_G6 VSS_G60 VSS_G63 VSS_G66 VSS_H15 VSS_H18 VSS_H71 VSS_J11 VSS_J13 VSS_J25 VSS_J28 VSS_J32 VSS_J35 VSS_J38 VSS_J42 VSS_J8 VSS_K16 VSS_K18 VSS_K22 VSS_K61 VSS_K63 VSS_K64 VSS_K65 VSS_K66 VSS_K67 VSS_K68 VSS_K70 VSS_K71 VSS_L11 VSS_L16 VSS_L17

SKYLAKE-U_BGA1356

18 OF 20REV = 1

VSS_L18

VSS_L2

VSS_L20

VSS_L4

VSS_L8 VSS_N10 VSS_N13 VSS_N19 VSS_N21

VSS_N6 VSS_N65 VSS_N68 VSS_P17 VSS_P19 VSS_P20 VSS_P21 VSS_R13

VSS_R6 VSS_T15 VSS_T17 VSS_T18

VSS_T2 VSS_T21

VSS_T4 VSS_U10 VSS_U63 VSS_U64 VSS_U66 VSS_U67 VSS_U69 VSS_U70 VSS_V16 VSS_V17 VSS_V18

VSS_W13

VSS_W6

VSS_W9 VSS_Y17 VSS_Y19 VSS_Y20 VSS_Y21

L18 L2 L20 L4 L8 N10 N13 N19 N21 N6 N65 N68 P17 P19 P20 P21 R13 R6 T15 T17 T18 T2 T21 T4 U10 U63 U64 U66 U67 U69 U70 V16 V17 V18 W13 W6 W9 Y17 Y19 Y20 Y21

1

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2015/01/12

LC Future Center Secret Data

Deciphered Date

2

2016/01/12

Title

KBL_VSS

Size

Document Number Rev

Custom

Friday, November 04, 2016

Date: Sheet of

Friday, November 04, 2016

DL470_NM-B021

1

20 99

0.2

5

4

3

2

1

[SKL EDS]

CFG0

D D

L:Stall. *H:(Default) Normal Operation; No stall.

UC1S

AL25 AL27

BA70 BA68

E68 B67 D65 D67 E70 C68 D68 C67 F71 G69 F70 G68 H70 G71 H69 G70

E63 F63

E66 F66

E60

E8

AY2 AY1

D1 D3

K46 K45

C71 B70

F60 A52

J71 J68

F65 G65

F61 E61

CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15]

CFG[16] CFG[17]

CFG[18] CFG[19]

CFG_RCOMP ITP_PMODE RSVD_AY2

RSVD_AY1 RSVD_D1

RSVD_D3 RSVD_K46

RSVD_K45 RSVD_AL25

RSVD_AL27 RSVD_C71

RSVD_B70 RSVD_F60 RSVD_A52 RSVD_TP_BA70

RSVD_TP_BA68 RSVD_J71

RSVD_J68 VSS_F65

VSS_G65 RSVD_F61

RSVD_E61

CFG0

CFG4

C C

[SKL CRB]

RC152 49.9_0402_1%

+1VALW_PCH

B B

RC371 1.5K_0402_5%

[SKL PDG]Route HOOK[6] to Skylake ITP_PMODE. Termination: Resistor value from 1K ohm to 3K ohm pull up to PCH_V1.0A Rail.

12 12

@ @

@ @ @

@ @

@

TP24 TP26

TP74 TP30

TP86 TP85

TP88@ TP87@

TP90 TP89

TP32 TP91

TP92 TP93

TP94 TP95

TP96@ TP97@

CFG_RCOMP ITP_PMODE

1 1

1 1 1

1 1

1

1 1

SKYLAKE-U_BGA1356

SKL_ULT

RESERVED SIGNALS-1

RSVD_TP_BB68 RSVD_TP_BB69

RSVD_TP_AK13 RSVD_TP_AK12

RSVD_TP_AW71 RSVD_TP_AW70

PROC_SELECT#

19 OF 20REV = 1

RSVD_BB2 RSVD_BA3

RSVD_D5 RSVD_D4

RSVD_B2

RSVD_C2

RSVD_B3 RSVD_A3

RSVD_AW1

RSVD_E1 RSVD_E2

RSVD_BA4 RSVD_BB4

RSVD_A4

RSVD_C4

RSVD_A69 RSVD_B69

RSVD_AY3 RSVD_D71

RSVD_C70 RSVD_C54

RSVD_D54

VSS_AY71

ZVM#

MSM#

1 2

1 1

1 1 1 1

1 1

1 1 1

1

1 1

TP37 TP39

TP43 @ TP45 @

TP49 TP51

TP59 @ TP60 @

TP22 TP23 TP25 TP27

TP64 TP66

TP29 TP31

TP33 TP34

TP35 TP67

TP68 TP54 TP927

TP928

TP929 @ TP930 @

TP931 @ TP932 @

TP933 @ TP934 @

TP935 @ TP936 @

TP937 @ TP938 @

@ @

@ @ @ @

@ @

@ @ @

@

BB68 BB69

AK13 AK12

BB2 BA3

AU5

TP5

AT5

TP6

D5 D4 B2 C2

B3 A3

AW1 E1

E2 BA4

BB4 A4

C4 BB5

TP4

A69 B69

AY3

RC296 0_0402_5%

D71 C70

C54 D54

AY4

TP1

BB3

TP2

AY71

RC295 0_0402_5%

AR56 AW71

AW70 AP56

C64

RC105 1K_0402_5%@ RC201 1K_0402_1%@

RC374

100K_0402_1%

12 12

TABLE

CFG0 : Stall Reset Sequence

after PCU PLL Lock until de-asserted

1 : No Stall

0 : Stall

CFG4 : eDP Enable

1 : Disabled 0 : Enabled

CFG9 : SVID Bus Communication 1 : Enabled 0 : Disabled

[SKL EDS]Zero Voltage Mode:VCCOPC is fixed OPC VR output voltage of 1V, the processor can drive VR to LPM (Low Power Mode) which sets VR output to 0V using ZVM# signal as shown below:

ZVM# state

0V

1V

+VCC_ST

[SKL EDS]Minimum Speed Mode: VCCEOPIO can be connected to OPC VR in this case VCCEOPIO is fixed to 1V. The processor can drive VR to LPM (Low Power Mode) which sets VR output to 0V using ZVM# signal . In order to achieve better power/performance it is recommended to use a separate VR for VCCEOPIO in this case VCCEOPIO is configurable to 0.8V/1V. The processor drives the VR to set VCCEOPIO value(0.8V/1V) using MSM# signal, based on the required bandwidth for the EOPIO interface as shown

12

below:

ZVM# state

CFG4

CFG4CFG0

*L: Embedded DisplayPort Enabled H: Embedded DisplayPort Disabled

VCCOPC

0V

1V

MSM# state

0V

1V

X

0V

1V 1V

VCCEOPIO

RC104 1K_0402_5%@ RC144 1K_0402_1%

12 12

0V

0.8V

+VCC_IO+VCC_IO

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2015/01/12

LC Future Center Secret Data

Deciphered Date

2

2016/01/12

Title

KBL_CFG/ RSVD

Size

Document Number Rev

Custom

Friday, November 04, 2016

Date: Sheet of

Friday, November 04, 2016

DL470_NM-B021

1

21 99

0.2

5

D D

C C

4

UC1T

TP98@ TP99@ TP100@ TP101@ TP102@ TP103@ TP104@ TP105@

1 1 1 1 1 1 1 1

AW69 AW68

AU56

AW48

U12 U11 H11

C7

RSVD_AW69 RSVD_AW68 RSVD_AU56 RSVD_AW48 RSVD_C7 RSVD_U12 RSVD_U11 RSVD_H11

SKYLAKE-U_BGA1356

SKL_ULT

20 OF 20REV = 1

SPARE

3

RSVD_F6

RSVD_E3 RSVD_C11 RSVD_B11 RSVD_A11 RSVD_D12 RSVD_C12 RSVD_F52

F6 E3 C11 B11 A11 D12 C12 F52

1 1 1 1 1 1 1 1

TP106 @

TP107 @ TP108 @ TP109 @ TP110 @ TP111 @ TP112 @ TP113 @

2

1

B B

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

2015/01/12

3

LC Future Center Secret Data

Deciphered Date

2016/01/12

2

Title

KBL_RSVD

Size

Document Number Rev

B

Friday, November 04, 2016

Date: Sheet of

Friday, November 04, 2016

DL470_NM-B021

1

22 99

0.2

5

Place 10uF/1uF decoupling cap, 4 near each side of the DIMM connector close to VDD pins. 330uF placeholder

[KBL PDG]VDDQ

[KBL PDG] EE 10uF x16, 1uF x16. 330uF x1

+1.2V +2.5V

1

2

CD@

CD1 10U_0603_6.3V6-M

12

CD2 10U_0603_6.3V6-M

12

CD3 10U_0603_6.3V6-M

4

12

CD4 10U_0603_6.3V6-M

1

CD5 10U_0603_6.3V6-M

2

CD@

12

CD6 10U_0603_6.3V6-M

12

CD7 10U_0603_6.3V6-M

12

CD8 10U_0603_6.3V6-M

3

2

1

Place decoupling cap on DRAM side.

[KBL PDG]VPP

[KBL PDG] EE 10uF x2, 1uF x2.

1

CRF7

0.1U_0402_10V7-K

RF_NS@

2

1

CRF8 100P_0402_50V8J

RF_NS@

2

12

CD9

CD@

10U_0603_6.3V6-M

12

CD10 10U_0603_6.3V6-M

CD11 1U_0402_6.3V6-K

CD12 1U_0402_6.3V6-K

CD@

1

CRF4 100P_0402_50V8J

RF_NS@

2

+1.2V

CD14

CD13

1U_0402_6.3V6-K

+1.2V +1.2V

JDIMM1A

1

DDR_A_D5 DDR_A_D1 DDR_A_DQS#0

DDR_A_DQS0 DDR_A_D2 DDR_A_D7 DDR_A_D9 DDR_A_D12

DDR_A_D10 DDR_A_D15 DDR_A_D16 DDR_A_D20 DDR_A_DQS#2

DDR_A_DQS2 DDR_A_D23 DDR_A_D18 DDR_A_D25 DDR_A_D24

DDR_A_D30 DDR_A_D26

DDR_A_DQS#8 DDR_A_DQS8

DDR_A_CKE0 DDR_A_BG1

DDR_A_BG0 DDR_A_MA12

DDR_A_MA9 DDR_A_MA8

DDR_A_MA6

VSS_1

3

DQ5

5

VSS_3

7

DQ1

9

VSS_5

11

DQS0_C

13

DQS0_t

15

VSS_8

17

DQ7

19

VSS_10

21

DQ3

23

VSS_12

25

DQ13

27

VSS_14

29

DQ9

31

VSS_16

33

DM1_n/DBl1_n

35

VSS_17

37

DQ15

39

VSS_19

41

DQ10

43

VSS_21

45

DQ21

47

VSS_23

49

DQ17

51

VSS_25

53

DQS2_c

55

DQS2_t

57

VSS_28

59

DQ23

61

VSS_30

63

DQ19

65

VSS_32

67

DQ29

69

VSS_34

71

DQ25

73

VSS_36

75

DM3_n/DBl3_n

77

VSS_37

79

DQ30

81

VSS_39

83

DQ26

85

VSS_41

87

CB5/NC

89

VSS_43

91

CB1/NC

93

VSS_45

95

DQS8_c

97

DQS8_t

99

VSS_48

101

CB2/NC

103

VSS_50

105

CB3/NC

107

VSS_52

109

CKE0

111

VDD_1

113

BG1

115

BG0

117

VDD_3

119

A12

121

A9

123

VDD_5

125

A8

127

A6

129

VDD_7

FOX_AS0A826-H4RB-7H

CD15 1U_0402_6.3V6-K

VSS_2 VSS_4 VSS_6

DM0_n/DBl0_n

VSS_7

VSS_9 VSS_11 VSS_13 VSS_15

DQS1_c DQS1_t VSS_18

VSS_20 VSS_22 VSS_24 VSS_26

DM2_n/DBl2_n

VSS_27 VSS_29 VSS_31 VSS_33 VSS_35

DQS3_c DQS3_t VSS_38

VSS_40 VSS_42

CB4/NC VSS_44 CB0/NC VSS_46

DM8_n/DBl8_n/NC

VSS_47 CB6/NC VSS_49 CB7/NC VSS_51

RESET_n

VDD_2

ACT_n

ALERT_n

VDD_4

VDD_6

VDD_8

Place decoupling on the VTT plane close to SODIMM

1

CD16

CD17

1U_0402_6.3V6-K

CD@

ME@

2

DDR_A_D0

4

DQ4

6

DDR_A_D4

8

DQ0

10 12 14

DDR_A_D6

16

DQ6

18

DDR_A_D3

20

DQ2

22

DDR_A_D8

24

DQ12

26

DDR_A_D13

28

DQ8

30

DDR_A_DQS#1

32

DDR_A_DQS1

34 36

DDR_A_D11

38

DQ14

40

DDR_A_D14

42

DQ11

44

DDR_A_D17

46

DQ20

48

DDR_A_D21

50

DQ16

52 54 56

DDR_A_D22

58

DQ22

60

DDR_A_D19

62

DQ18

64

DDR_A_D29

66

DQ28

68

DDR_A_D28

70

DQ24

72

DDR_A_DQS#3

74

DDR_A_DQS3

76 78

DDR_A_D31

80

DQ31

82

DDR_A_D27

84

DQ27

86 88 90 92 94 96 98 100 102 104 106 108 110

CKE1

112

DDR_A_ACT_N

114

DDR_A_ALERT_N

116 118

DDR_A_MA11

120

A11

A7 A5

A4

DDR_A_MA7

122 124

DDR_A_MA5

126

DDR_A_MA4

128 130

CD19

CD18

1U_0402_6.3V6-K

+3VS +3VS +3VS

12

RD2 10K_0402_5%

@

SA0_CHA_P SA1_CHA_P SA2_CHA_P

12

RD5 0_0402_SM

SPD Address = 0H

DDR4_DRAMRST# [7,24] DDR_A_CKE1 [6]

DDR_A_ACT_N [6] DDR_A_ALERT_N [6]

+

CD20 1U_0402_6.3V6-K

2

CD@

DDR_A_D[0..63] [6] DDR_A_MA[0..16] [6] DDR_A_DQS#[0..7] [6] DDR_A_DQS[0..7] [6]

DDR_A_DDRCLK0_1866M[6] DDR_A_DDRCLK0_1866M#[6]

12

RD3 10K_0402_5%

@

12

RD6 0_0402_SM

[KBL PDG]VDDSPD

[KBL PDG] EE 0.1uF x1, 2.2uF x1.

CD21 330U_D2_2VM_R9M

12

RD4 10K_0402_5%

@

12

RD7 0_0402_SM

+3VS

RD8 0_0402_SM

1 2

+0.6VS

DDR_A_PARITY[6]

DDR_A_BA1[6] DDR_A_CS0#[6]

DDR_A_ODT0[6] DDR_A_CS1#[6]

DDR_A_ODT1[6]

PM_SMB_CLK[9,24,63]

1

CRF5

0.1U_0402_10V7-K

RF_NS@

2

1

CD30

0.1U_0402_10V7-K

2

[KBL PDG]VTT

[KBL PDG] EE 10uF x2, 1uF x4.

1

CRF6 100P_0402_50V8J

RF_NS@

2

+1.2V

DDR_A_MA3 DDR_A_MA1

DDR_A_DDRCLK0_1866M DDR_A_DDRCLK0_1866M#

DDR_A_PARITY

DDR_A_BA1 DDR_A_CS0#

DDR_A_MA14 DDR_A_ODT0

DDR_A_CS1# DDR_A_ODT1

DDR_A_D37 DDR_A_D32 DDR_A_DQS#4

DDR_A_DQS4 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D44

DDR_A_D43 DDR_A_D46 DDR_A_D49 DDR_A_D52 DDR_A_DQS#6

DDR_A_DQS6 DDR_A_D50 DDR_A_D55 DDR_A_D56 DDR_A_D60

DDR_A_D59 DDR_A_D58 PM_SMB_CLK

VDDSPD_1

1

CD31

2.2U_0402_6.3V6-M

2

12

CD22 10U_0603_6.3V6-M

+1.2V+2.5V

JDIMM1B

131

A3

133

A1

135

VDD_9

137

CK0_t

139

CK0_c

141

VDD_11

143

Parity

145

BA1

147

VDD_13

149

CS0_n

151

A14/WE_n

153

VDD_15

155

ODT0

157

CS1_n

159

VDD_17

161

ODT1

163

VDD_19

165

C1/CS3_n/NC

167

VSS_53

169

DQ37

171

VSS_55

173

DQ33

175

VSS_57

177

DQS4_c

179

DQS4_t

181

VSS_60

183

DQ38

185

VSS_62

187

DQ34

189

VSS_64

191

DQ44

193

VSS_66

195

DQ40

197

VSS_68

199

DM5_n/DBl5_n

201

VSS_69

203

DQ46

205

VSS_71

207

DQ42

209

VSS_73

211

DQ52

213

VSS_75

215

DQ49

217

VSS_77

219

DQS6_c

221

DQS6_t

223

VSS_80

225

DQS5

227

VSS_82

229

DQ51

231

VSS_84

233

DQ61

235

VSS_86

237

DQ56

239

VSS_88

241

DM7_n/DBl7_n

243

VSS_89

245

DQ62

247

VSS_91

249

DQ58

251

VSS_93

253

SCL

255

VDDSPD

257

VPP_1

259

VPP_2

261

GND_1

FOX_AS0A826-H4RB-7H

12

CD23 10U_0603_6.3V6-M

C0/CS2_n/NC

DM4_n/DBl4_n

DM6_n/DBl6_n

ME@

EVENT_n/NF

VDD_10

CK1_t/NF

CK1_c/NF

VDD_12

A10/AP

VDD_14

A16/RAS_n

VDD_16

A15/CAS_n

VDD_18

VREFCA

VSS_54 VSS_56 VSS_58 VSS_59 VSS_61 VSS_63 VSS_65 VSS_67

DQS5_c DQS5_t VSS_70

VSS_72 VSS_74 VSS_76 VSS_78 VSS_79 VSS_81 VSS_83 VSS_85 VSS_87

DQS7_c DQS7_t VSS_90

VSS_92 VSS_94

GND_2

BA0

A13

SA2 DQ36 DQ32

DQ39 DQ35 DQ45 DQ41

DQ47 DQ43 DQ53 DQ48

DQ54 DQ50 DQ60 DQ57

DQ63 DQ59

SDA

SA0

VTT

SA1

A2

A0

CD24 1U_0402_6.3V6-K

+1.2V +0.6VS

132 134 136 138 140 142 144

146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232 234 236 238 240 242 244 246 248 250 252 254 256 258 260

262

CD25 1U_0402_6.3V6-K

DDR_A_MA2 EVENT_n_1

DDR_A_DDRCLK1_1866M DDR_A_DDRCLK1_1866M#

DDR_A_MA0

DDR_A_MA10 DDR_A_BA0

DDR_A_MA16 DDR_A_MA15

DDR_A_MA13

M_VREF_CA_DIMMA SA2_CHA_P

DDR_A_D33 DDR_A_D36

DDR_A_D35 DDR_A_D34 DDR_A_D41 DDR_A_D45 DDR_A_DQS#5

DDR_A_DQS5 DDR_A_D42 DDR_A_D47 DDR_A_D48 DDR_A_D53

DDR_A_D54 DDR_A_D51 DDR_A_D57 DDR_A_D61 DDR_A_DQS#7

DDR_A_DQS7 DDR_A_D63 DDR_A_D62 PM_SMB_DAT

SA0_CHA_P SA1_CHA_P

RF

CD26 1U_0402_6.3V6-K

CD@

+1.2V

RD1 240_0402_1%

1 2

DDR_A_DDRCLK1_1866M [6] DDR_A_DDRCLK1_1866M# [6]

DDR_A_BA0 [6]

+1.2V

2.2U_0402_6.3V6-M

1

CD28

2

@

+1.2V

PM_SMB_DAT [9,24,63]

0.1U_0402_10V7-K

2

CD29

1

@

CD27 1U_0402_6.3V6-K

D D

1

CRF3

0.1U_0402_10V7-K

RF_NS@

2

C C

B B

DDR_A_CKE0[6] DDR_A_BG1[6]

DDR_A_BG0[6]

Place decoupling cap close to DIMM

+1.2V

12

RD9 1K_0402_1%

A A

DDR4_VREF_CA_CPU_A[6]

5

1 2

1

CD32

0.022U_0402_25V7-K

2

12

RD14

24.9_0402_1%

RD10 2_0402_1%

12

RD13 1K_0402_1%

M_VREF_CA_DIMMA

12

CD33

0.1U_0402_16V7-K

@

4

RD11

240_0402_1%

+1.2V

12

RD12 240_0402_1%

DDR_A_DQS#8

DDR_A_DQS8

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2015/09/01

LC Future Center Secret Data

Deciphered Date

2

2016/12/31

Title

DDR4 CH-A PRIMARY

Size

Document Number Rev

Friday, November 04, 2016

Date: Sheet of

DL470_NM-B021

23 99

1

0.2Custom

5

4

3

2

1

Place 10uF/1uF decoupling cap, 4 near each side of the DIMM connector close to VDD pins. 330uF placeholder

[KBL PDG]VDDQ

+1.2V

[KBL PDG] EE 10uF x16, 1uF x16. 330uF x1

1

2

CD@

+1.2V

D D

1

CRF9

0.1U_0402_10V7-K

RF_NS@

2

C C

B B

1

CRF10 100P_0402_50V8J

RF_NS@

2

DDR_B_D13 DDR_B_D12 DDR_B_DQS#1

DDR_B_DQS1 DDR_B_D10 DDR_B_D14 DDR_B_D4 DDR_B_D0

DDR_B_D6 DDR_B_D2 DDR_B_D21 DDR_B_D16 DDR_B_DQS#2

DDR_B_DQS2 DDR_B_D18 DDR_B_D22 DDR_B_D29 DDR_B_D25

DDR_B_D30 DDR_B_D26

DDR_B_DQS#8 DDR_B_DQS8

DDR_B_CKE0[7] DDR_B_BG1[7]

DDR_B_BG0[7]

DDR_B_CKE0 DDR_B_BG1

DDR_B_BG0 DDR_B_MA12

DDR_B_MA9 DDR_B_MA8

DDR_B_MA6

1

CD34 10U_0603_6.3V6-M

2

CD@

CD46

CD45

1U_0402_6.3V6-K

+1.2V +1.2V

CD35 10U_0603_6.3V6-M

JDIMM2A

1

VSS_1

3

DQ5

5

VSS_3

7

DQ1

9

VSS_5

11

DQS0_C

13

DQS0_t

15

VSS_8

17

DQ7

19

VSS_10

21

DQ3

23

VSS_12

25

DQ13

27

VSS_14

29

DQ9

31

VSS_16

33

DM1_n/DBl1_n

35

VSS_17

37

DQ15

39

VSS_19

41

DQ10

43

VSS_21

45

DQ21

47

VSS_23

49

DQ17

51

VSS_25

53

DQS2_c

55

DQS2_t

57

VSS_28

59

DQ23

61

VSS_30

63

DQ19

65

VSS_32

67

DQ29

69

VSS_34

71

DQ25

73

VSS_36

75

DM3_n/DBl3_n

77

VSS_37

79

DQ30

81

VSS_39

83

DQ26

85

VSS_41

87

CB5/NC

89

VSS_43

91

CB1/NC

93

VSS_45

95

DQS8_c

97

DQS8_t

99

VSS_48

101

CB2/NC

103

VSS_50

105

CB3/NC

107

VSS_52

109

CKE0

111

VDD_1

113

BG1

115

BG0

117

VDD_3

119

A12

121

A9

123

VDD_5

125

A8

127

A6

129

VDD_7

FOX_AS0A826-H4SB-7H

SP071407011

12

CD36 10U_0603_6.3V6-M

CD47 1U_0402_6.3V6-K

VSS_2 VSS_4 VSS_6

DM0_n/DBIO_n

VSS_7

VSS_9 VSS_11 VSS_13 VSS_15

DQS1_c DQS1_t VSS_18

VSS_20 VSS_22 VSS_24 VSS_26

DM2_n/DBl2_n

VSS_27 VSS_29 VSS_31 VSS_33 VSS_35

DQS3_c DQS3_t VSS_38

VSS_40 VSS_42

CB4/NC VSS_44 CB0/NC VSS_46 DBI8_n VSS_47 CB6/NC VSS_49 CB7/NC VSS_51

RESET_n

VDD_2

ACT_n

ALERT_n

VDD_4

VDD_6

VDD_8

CD37 10U_0603_6.3V6-M

DDR_B_D8 DDR_B_D9

DDR_B_D15 DDR_B_D11 DDR_B_D1 DDR_B_D5 DDR_B_DQS#0

DDR_B_DQS0 DDR_B_D3 DDR_B_D7 DDR_B_D20 DDR_B_D17

DDR_B_D23 DDR_B_D19 DDR_B_D28 DDR_B_D24 DDR_B_DQS#3

DDR_B_DQS3 DDR_B_D31 DDR_B_D27

DDR_B_MA11 DDR_B_MA7

DDR_B_MA5 DDR_B_MA4

12

CD38 10U_0603_6.3V6-M

CD49 1U_0402_6.3V6-K

CD@

12

CD48 1U_0402_6.3V6-K

Layout Node:

Place Close DIMMs

ME@

2 4

DQ4

6 8

DQ0

10 12 14 16

DQ6

18 20

DQ2

22 24

DQ12

26 28

DQ8

30 32 34 36 38

DQ14

40 42

DQ11

44 46

DQ20

48 50

DQ16

52 54 56 58

DQ22

60 62

DQ18

64 66

DQ28

68 70

DQ24

72 74 76 78 80

DQ31

82 84

DQ27

86 88 90 92 94 96 98 100 102 104 106 108 110

CKE1

112 114 116 118 120

A11

122

A7

124 126

A5

128

A4

130

12

CD39 10U_0603_6.3V6-M

CD50 1U_0402_6.3V6-K

DDR4_DRAMRST# [7,23] DDR_B_CKE1 [7]

DDR_B_ACT_N [7] DDR_B_ALERT_N [7]

CD40 10U_0603_6.3V6-M

CD52 1U_0402_6.3V6-K

CD@

12

CD41 10U_0603_6.3V6-M

+3VS +3VS

12

RD17 10K_0402_5%

12

RD20 0_0402_5%

@

12

CD51 1U_0402_6.3V6-K

+3VS

12

RD16 10K_0402_5%

@

SA0_CHB_P SA1_CHB_P SA2_CHB_P

12

RD19 0_0402_SM

SPD Address = 2H

[KBL PDG]VDDSPD

[KBL PDG] EE 0.1uF x1, 2.2uF x1.

DDR_B_D[0..63] [7] DDR_B_MA[0..16] [7] DDR_B_DQS#[0..7] [7] DDR_B_DQS[0..7] [7]

DDR_B_DDRCLK0_1866M[7] DDR_B_DDRCLK0_1866M#[7]

DDR_B_PARITY[7]

DDR_B_BA1[7] DDR_B_CS0#[7]

DDR_B_ODT0[7] DDR_B_CS1#[7]

DDR_B_ODT1[7]

12

RD18 10K_0402_5%

@

12

RD21 0_0402_SM

+3VS

RD22 0_0402_SM

1 2

+2.5V

12

PM_SMB_CLK[9,23,63]

CD54 10U_0603_6.3V6-M

CD@

1

CD63

0.1U_0402_10V7-K

2

Place decoupling cap on DRAM side.

[KBL PDG]VPP

[KBL PDG] EE 10uF x2, 1uF x2.

+0.6VS

12

CD@

CD42 10U_0603_6.3V6-M

12

CD43

CD@

10U_0603_6.3V6-M

CD44 1U_0402_6.3V6-K

Place decoupling on the VTT plane close to SODIMM

[KBL PDG]VTT

[KBL PDG] EE 10uF x2, 1uF x4.

12

CD55 10U_0603_6.3V6-M

DDR_B_MA3 DDR_B_MA1

DDR_B_DDRCLK0_1866M DDR_B_DDRCLK0_1866M#

DDR_B_PARITY

DDR_B_BA1 DDR_B_CS0#

DDR_B_MA14 DDR_B_ODT0

DDR_B_CS1# DDR_B_ODT1

DDR_B_D37 DDR_B_D33 DDR_B_DQS#4

DDR_B_DQS4 DDR_B_D34 DDR_B_D38 DDR_B_D41 DDR_B_D40

DDR_B_D43 DDR_B_D47 DDR_B_D53 DDR_B_D48 DDR_B_DQS#6

DDR_B_DQS6 DDR_B_D50 DDR_B_D55 DDR_B_D60 DDR_B_D61

DDR_B_D59 DDR_B_D58 PM_SMB_CLK

VDDSPD_2

+1.2V

1

CD64

2.2U_0402_6.3V6-M

2

CD56 1U_0402_6.3V6-K

CD@

+1.2V+2.5V

CD57 1U_0402_6.3V6-K

JDIMM2B

131

A3

133

A1

135

VDD_9

137

CK0_t

139

CK0_c

141

VDD_11

143

Parity

145

BA1

147

VDD_13

149

CS0_n

151

WE_n/A14

153

VDD_15

155

ODT0

157

CS1_n

159

VDD_17

161

ODT1

163

VDD_19

165

C1/CS3_n/NC

167

VSS_53

169

DQ37

171

VSS_55

173

DQ33

175

VSS_57

177

DQS4_c

179

DQS4_t

181

VSS_60

183

DQ38

185

VSS_62

187

DQ34

189

VSS_64

191

DQ44

193

VSS_66

195

DQ40

197

VSS_68

199

DM5_n/DBl5_n

201

VSS_69

203

DQ46

205

VSS_71

207

DQ42

209

VSS_73

211

DQ52

213

VSS_75

215

DQ49

217

VSS_77

219

DQS6_c

221

DQS6_t

223

VSS_80

225

DQ55

227

VSS_82

229

DQ51

231

VSS_84

233

DQ61

235

VSS_86

237

DQ56

239

VSS_88

241

DM7_n/DBl7_n

243

VSS_89

245

DQ62

247

VSS_91

249

DQ58

251

VSS_93

253

SCL

255

VDDSPD

257

VPP_1

259

VPP_2

261

GND_1

FOX_AS0A826-H4SB-7H

SP071407011

RAS_n/A16 CAS_n/A15

C0/CS2_n/NC

DM4_n/DBl4_n

DM6_n/DBl6_n

CD@

EVENT_n

VDD_10

CK1_t CK1_c

VDD_12

A10/AP VDD_14

VDD_16

VDD_18

VREFCA

VSS_54 VSS_56 VSS_58 VSS_59 VSS_61 VSS_63 VSS_65 VSS_67

DQS5_c DQS5_t VSS_70

VSS_72 VSS_74 VSS_76 VSS_78 VSS_79 VSS_81 VSS_83 VSS_85 VSS_87

DQS7_c DQS7_t VSS_90

VSS_92 VSS_94

GND_2

DQ36 DQ32

DQ39 DQ35 DQ45 DQ41

DQ47 DQ43 DQ53 DQ48

DQ54 DQ50 DQ60 DQ57

DQ63 DQ59

1

CRF11

0.1U_0402_10V7-K

2

RF_NS@

CD58 1U_0402_6.3V6-K

+1.2V +0.6VS

ME@

132

A2

134 136 138 140 142 144

A0

146 148 150

BA0

152 154 156 158

A13

160 162 164 166

RFU

168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232 234 236 238 240 242 244 246 248 250 252 254

SDA

256

SA0

258

Vtt

260

SA1

262

1

CRF12 100P_0402_50V8J

2

RF_NS@

CD59 1U_0402_6.3V6-K

DDR_B_MA2 EVENT_n_2

DDR_B_DDRCLK1_1866M DDR_B_DDRCLK1_1866M#

DDR_B_MA0

DDR_B_MA10 DDR_B_BA0

DDR_B_MA16 DDR_B_MA15

DDR_B_MA13

M_VREF_CA_DIMMB SA2_CHB_P

DDR_B_D36 DDR_B_D32

DDR_B_D35 DDR_B_D39 DDR_B_D45 DDR_B_D44 DDR_B_DQS#5

DDR_B_DQS5 DDR_B_D42 DDR_B_D46 DDR_B_D52 DDR_B_D49

DDR_B_D51 DDR_B_D54 DDR_B_D56 DDR_B_D57 DDR_B_DQS#7

DDR_B_DQS7 DDR_B_D62 DDR_B_D63 PM_SMB_DAT

SA0_CHB_P SA1_CHB_P

CD60 1U_0402_6.3V6-K

CD@

+1.2V

12

+1.2V

PM_SMB_DAT [9,23,63]

1

CRF13

0.1U_0402_10V7-K

2

RF_NS@

RD15 240_0402_1%

DDR_B_DDRCLK1_1866M [7] DDR_B_DDRCLK1_1866M# [7]

DDR_B_BA0 [7]

2.2U_0402_6.3V6-M

1

CD61

2

@

1

2

0.1U_0402_10V7-K

CD62

@

1

CRF14 100P_0402_50V8J

2

RF_NS@

Place decoupling cap close to DIMM

+1.2V

12

RD23 1K_0402_1%

RD24 2_0402_1%

DDR4_VREF_DQ_CPU_B[6]

A A

1 2

1

CD65

0.022U_0402_25V7-K

2

12

RD29

24.9_0402_1%

12

RD30 1K_0402_1%

M_VREF_CA_DIMMB

12

CD66

0.1U_0402_16V7-K

@

RD25

240_0402_1%

+1.2V

12

RD26 240_0402_1%

DDR_B_DQS#8

DDR_B_DQS8

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2015/09/01

LC Future Center Secret Data

Deciphered Date

2

2016/12/31

Title

DDR4 CH-B PRIMARY

Size

Document Number Rev

Date: Sheet of

Friday, November 04, 2016

DL470_NM-B021

24 99

1

0.2Custom

5

4

3

2

1

+VCC_CORE +VCC_GT

D D

C C

[SKL PDG]VCC

[SKL PDG]22uF x9,10uF x7,1uF x35

22U_0603_6.3V6-M

C228

C227

C226

1

2

10U_0402_6.3V6-M

C236

C247

C364

C374

10U_0402_6.3V6-M

C237

C238

1

2

1U_0201_6.3V6-M

C249

C248

1

2

1U_0201_6.3V6-M

C363

C361

1

2

1U_0201_6.3V6-M

C371

C373

1

2

[SKL PDG]VCCGT

[SKL PDG]10uF x10,1uF x12

22U_0603_6.3V6-M

C229

C266

1

2

10U_0402_6.3V6-M

C239

1

2

1U_0201_6.3V6-M

C250

1

2

1U_0201_6.3V6-M

C369

1

2

1U_0201_6.3V6-M

C379

1

2

C267

1

2

10U_0402_6.3V6-M

C241

C240

1

2

1U_0201_6.3V6-M

C251

C252

1

2

1U_0201_6.3V6-M

C370

C362

1

2

1U_0201_6.3V6-M

C380

C372

1

2

22U_0603_6.3V6-M

C233

C232

1

2

1U_0201_6.3V6-M

10U_0402_6.3V6-M

C243

C244

1

2

1U_0201_6.3V6-M

C253

C254

1

2

1U_0201_6.3V6-M

C368

C367

1

2

1U_0201_6.3V6-M

C378

C377

1

2

22U_0603_6.3V6-M

C268

1

2

1U_0201_6.3V6-M

C245

1

2

1U_0201_6.3V6-M

C255

1

2

1U_0201_6.3V6-M

C366

1

2

1U_0201_6.3V6-M

C376

1

2

10U_0402_6.3V6-M

C235

1

2

1U_0201_6.3V6-M

C246

1

2

1U_0201_6.3V6-M

C256

1

2

1U_0201_6.3V6-M

C365

1

2

1U_0201_6.3V6-M

C257

1

2

C273

C283

C293

10U_0402_6.3V6-M

C275

C274

1

2

CD@

1U_0201_6.3V6-M

C284

C285

1

2

CD@

1U_0201_6.3V6-M

C294

1

2

10U_0402_6.3V6-M

C276

1

2

CD@

1U_0201_6.3V6-M

C286

1

2

CD@

10U_0402_6.3V6-M

C277

C278

1

2

CD@

1U_0201_6.3V6-M

C287

C288

1

2

10U_0402_6.3V6-M

C279

1

2

1U_0201_6.3V6-M

C289

1

2

10U_0402_6.3V6-M

C281

C280

1

2

1U_0201_6.3V6-M

C291

C290

1

2

10U_0402_6.3V6-M

C282

C355

1

2

1U_0201_6.3V6-M

C292

C357

1

2

10U_0402_6.3V6-M

C356

1

2

1U_0201_6.3V6-M

C359

C358

1

2

1U_0201_6.3V6-M

C360

1

2

B B

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2015/01/12

LC Future Center Secret Data

Deciphered Date

2

2016/01/12

Title

CPU_CAPS

Size

Document Number Rev

Custom

Friday, November 04, 2016

Date: Sheet of

Friday, November 04, 2016

DL470_NM-B021

1

25 99

0.2

5

D D

C C

4

3

2

1

B B

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2015/01/12

LC Future Center Secret Data

Deciphered Date

2

2016/01/12

Title

XXXX

Size

Document Number Rev

Custom

Friday, November 04, 2016

Date: Sheet of

Friday, November 04, 2016

DL470_NM-B021

1

26 99

0.2

5

D D

C C

4

3

2

1

B B

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2015/01/12

LC Future Center Secret Data

Deciphered Date

2

2016/01/12

Title

XXXX

Size

Document Number Rev

Custom

Friday, November 04, 2016

Date: Sheet of

Friday, November 04, 2016

DL470_NM-B021

1

27 99

0.2

5

D D

C C

4

3

2

1

B B

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2015/01/12

LC Future Center Secret Data

Deciphered Date

2

2016/01/12

Title

XXXX

Size

Document Number Rev

Custom

Friday, November 04, 2016

Date: Sheet of

Friday, November 04, 2016

DL470_NM-B021

1

28 99

0.2

5

D D

C C

4

3

2

1

B B

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2015/01/12

LC Future Center Secret Data

Deciphered Date

2

2016/01/12

Title

XXXX

Size

Document Number Rev

Custom

Friday, November 04, 2016

Date: Sheet of

Friday, November 04, 2016

DL470_NM-B021

1

29 99

0.2

5

4

3

2

1

UV3A

DIS@

1

N9

TPV3 TPV4 TPV5 TPV40

TPV6

TPV7 TPV8 TPV9 TPV10 TPV11

TPV13

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

12

RV71

@

4.7K_0402_5%

SMBDAT SMBCLK

GPIO6 GPIO8_ROMSO

GPIO9_ROMSI GPIO10_ROMSCK GPIO17_THERMAL

GPIO15

GPIO20 GPIO22_ROMCSB

JTAG_TRSTB JTAG_TDI JTAG_TCK JTAG_TMS JTAG_TDO

XTALIN XTALOUT

FDO

TPV17 TPV18 TPV19 TPV20 TPV21 TPV22 TPV23 TPV24 TPV25 TPV26 TPV27 TPV28 TPV29 TPV30 TPV31 TPV32 TPV33 TPV34

NC_DBG_DATA16

L9

NC_DBG_DATA15

AE9

NC_DBG_DATA14

Y11

NC_DBG_DATA13

AE8

NC_DBG_DATA12

AD9

DBG_DATA11

AC10

DBG_DATA10

AD7

DBG_DATA9

AC8

DBG_DATA8

AC7

DBG_DATA7

AB9

DBG_DATA6

AB8

DBG_DATA5

AB7

DBG_DATA4

AB4

DBG_DATA3

AB2

DBG_DATA2

Y8

DBG_DATA1

Y7

DBG_DATA0

AL9

NC_DBG_CNTL0

U1

BP_0

U3

BP_1

AM26

DIECRACKMON

W6

NC_2

V6

NC_3

AC6

NC_4

AC5

NC_5

AA5

NC_6

AA6

NC_7

Y6

NC_8

I2C

R1

SCL

R3

SDA

GENERAL PURPOSE I/O

U6

GPIO_0

U8

SMBDATA

U7

SMBCLK

T9

GPIO_5_AC_BATT

T8

GPIO_6_TACH

T7

NC_GPIO_7

P10

GPIO_8_ROMSO

P4

GPIO_9_ROMSI

P2

GPIO_10_ROMSCK

N6

NC_GPIO_11

N5

NC_GPIO_12

N3

NC_GPIO_13

N1

GPIO_15_PWRCNTL_0

M4

GPIO_16

R6

GPIO_17_THERMAL_INT

M2

GPIO_19_CTF

P8

GPIO_20_PWRCNTL_1

P7

GPIO_21

N8

GPIO_22_ROMCSB

AK10

GPIO_29

AM10

GPIO_30

N7

CLKREQB

L6

JTAG_TRSTB

L5

JTAG_TDI

L3

JTAG_TCK

L1

JTAG_TMS

K4

JTAG_TDO

K7

TESTEN

AF24

NC_9

W8

NC_GENERICB

W7

NC_GENERICD

AD10

NC_GENERICE_HPD4

AJ9

NC_10

AB16

PX_EN

AJ27

WAKEB

AC16

NC_DBG_VREFG

PLL/CLOCK

AA1

PLL_ANALOG_IN

AA3

PLL_ANALOG_OUT

AM28

XTALIN

AK28

XTALOUT

AC22

XO_IN

AB22

XO_IN2

THERMAL

T4

DPLUS

T2

DMINUS

R5

GPIO28_FDO

AD17

TSVDD

AC17

TSVSS

AE19

TS_A

216-0858020-A0_FCBGA631

SA00007QD10

RV84

DBG

EXO@

1 2

10K_0402_5%

NC_DAC1

MLPS&SV I2

NC_DDC/AUX

Test_Point_20MIL Test_Point_20MIL Test_Point_20MIL Test_Point_20MIL Test_Point_20MIL Test_Point_20MIL Test_Point_20MIL

12

RV55

4.7K_0402_5%

MESO@

+3VS_VGA

12

RV70

@

4.7K_0402_5%

DIS@

1 2

DIS@

1 2

Test_Point_20MIL Test_Point_20MIL Test_Point_20MIL Test_Point_20MIL

1 2 1 2

1 2

Test_Point_20MIL

1 2 1 2

Test_Point_20MIL Test_Point_20MIL Test_Point_20MIL Test_Point_20MIL Test_Point_20MIL

+3VS_VGA

RV76 5.11K_0402_1%@ RV77 1K_0402_1%DIS@

RV78 0_0402_5%@

TPV12

RV79 0_0402_5%@

RV80 4.7K_0402_5% RV106 4.7K_0402_5%DIS@

Test_Point_20MIL

RV81 16.2K_0402_1%DIS@

RV82 10K_0402_5%DIS@ RV83 10K_0402_5%DIS@

1

CV145 1U_0402_10V6-K

2

Test_Point_20MIL Test_Point_20MIL Test_Point_20MIL Test_Point_20MIL Test_Point_20MIL Test_Point_20MIL Test_Point_20MIL Test_Point_20MIL Test_Point_20MIL Test_Point_20MIL Test_Point_20MIL

1 1 1 1

1

1 1 1 1 1

1 2 1 2

@

1 2 1 2

1

1 2

1 2 1 2

D D

+3VS_VGA

SMBCLK

SMBDAT

C C

VGA_AC_DC#[77]

GPU_VR_HOT#[77,91]

+3VS_VGA

B B

12

RV63

@

10K_0402_5%

A A

VGA_ON[10,38,39,91]

CLKREQ_PCIE4_VGA#[14]

1

QV2A NTJD5121NT1G_SC88-6

5

DIS@

G2

4

D23S2

QV2B

SB000013A00

NTJD5121NT1G_SC88-6

DIS@

+3VS_VGA

RV111 10K_0402_5%DIS@

VGA_AC_DC# GPIO5_AC_BATTGPIO5_AC_BATT

DV2 RB751V-40_SOD323-2

SCS00006S00

RV113 0_0402_5%@

RV114

1 2

@

0_0402_5%

12

RV64

RV65

@

10K_0402_5%

RV49

12

@

10K_0402_5%

1

CV141

@

0.1U_0402_10V7-K

2

5

can remove

1 2

RV41 0_0402_5%@

2

G1 D16S1

SB000013A00

PU AT EC SIDE, +3VS AND 4.7K

1 2

DIS@

1 2

+3VS_VGA

12

RV61

@

10K_0402_5%

RV62

OCP_L

1 2

@

1K_0402_1%

12

RV66

@

10K_0402_5%

JTAG_TRSTB JTAG_TDI JTAG_TCK JTAG_TMS JTAG_TDO

+3VS_VGA

12

@

1

CV140

@

0.1U_0402_10V7-K

2

1 3

D

QV72N7002KW _SOT323-3

SB000019400

1 2

@

RV51 0_0402_5%

EC_SMB_CK3 [9,69,70,77]

EC_SMB_DA3 [9,69,70,77]

GPIO6

1

CV142

@

0.1U_0402_10V7-K

2

12

RV58

@

10K_0402_5%

RV50 10K_0402_5%

+3VS_VGA

G

@

S

PLT_RST_VGA#

12

RV52

@

10K_0402_5%

CLK_REQ_GPU#

RV53

@

10K_0402_5%

1 2

Test_Point_20MIL Test_Point_20MIL

BIOS directly open PCIE bus

+3VS_VGA

RV115 4.7K_0402_5%@

RV140 0_0402_5%@

EC_WAKE#[8,77] GPU_WAKE#[15]

1 2

RV68 1M_0402_5%

4 1

XTALOUT

1

CV143

DIS@

22P_0402_50V8-J

2

+1.8VS_VGA

12

RV54

4.7K_0402_5%

MESO@

1

TPV1

1

TPV2

+3VS_VGA

RV72 45.3K_0402_1% RV73 45.3K_0402_1%

SVI2_SVD

RV117 0_0402_5%DIS@ RV74 10K_0402_5%DIS@

GPIO19_CTF SVI2_SVC

RV116 0_0402_5%DIS@

CLK_REQ_GPU# SVI2_SVC

RV112 0_0402_5%@ RV75 10K_0402_5%DIS@

1

Test_Point_20MIL

1 2

DIS@

YV1

DIS@

3

NC2

OSC2

2

OSC1

NC1

27MHZ_16PF_7V27000011

DIS@

4

2

G

@

1 3

D

S

QV42N7002KW _SOT323-3

SB000019400

XTALIN

1

CV144 22P_0402_50V8-J

2

+3VS_VGA

+1.8VS_VGA

DIS@

NC_DPA

NC_DPB

NC_DPC

NC_AVSSN_1 NC_AVSSN_2

NC_AVSSN_3

NC_HSYNC

NC_RSET NC_AVDD

NC_AVSSQ NC_VDD1DI

NC_VSS1DI

NC_CEC_1

GPIO_SVD GPIO_SVT GPIO_SVC

NC_GENLK_CLK

NC_GENLK_VSYNC

NC_SWAPLOCKA

NC_SWAPLOCKB

NC_DDC1CLK

NC_DDC1DATA

NC_AUX1P NC_AUX1N

NC_AUX2P NC_AUX2N

NC_DDCVGACLK

NC_DDCVGADATA

FDO

3

NC_13 NC_14

NC_15 NC_16

NC_17 NC_18

NC_19 NC_20

NC_21 NC_22

NC_23 NC_24

NC_25 NC_26

NC_27 NC_28

NC_29 NC_30

NC_31 NC_32

NC_33

NC_34 NC_35

NC_36 NC_37

AF2 AF4

AG3 AG5

AH3 AH1

AK3 AK1

AK5 AM3

AK6 AM5

AJ7 AH6

AK8 AL7

V4 U5

V2 Y4

W5

Y2 J8

AL25

NC_G

AK26 AJ25

AH24

NC_B

AG25 AH26

AD22 AG24

AE22 AE23

AD23

AM12

AK12

1 2

RV107 0_0402_5%MESO@

1 2

AL11

RV108 0_0402_5%MESO@

AJ11

1 2

RV109 0_0402_5%MESO@

AL13 AJ13

AG13

PS_0

AC19

PS_0

AH12

PS_1

AD19

PS_1

PS_2

AE17

PS_2

PS_3

AE20

PS_3

+1.8VS_VGA

AE6 AE5

AD2 AD4

AD13 AD11

AE16 AD16

AC1 AC3

12

DIS@

1 2

+1.8VS_VGA

12

DIS@

1 2

RV98

8.45K_0402_1%

RV99 2K_0402_1%

RV102

8.45K_0402_1%

RV103 2K_0402_1%

@

SVI2_SVD SVI2_SVT SVI2_SVC

PS_0PS_0

1

CV153

0.1U_0402_10V7-K

2

PS_1

1

CV155

0.1U_0402_10V7-K

2

PLT_RST_VGA#[10,35,91]

GPIO19_CTF

PLT_RST_VGA#

GPIO15

RV89 33_0402_5%@

GPIO20

RV90 33_0402_5%@

SVI2_SVD [91] SVI2_SVC [91]

+1.8VS_VGA

DIS@

+1.8VS_VGA

X76@

SVI2_SVD SVI2_SVT SVI2_SVC

12

RV100

@

10K_0402_1%

12

@

RV101

4.75K_0402_1%

12

RV104

3.24K_0402_1%

12

RV105

@

5.62K_0402_1%X76@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

1 2

RV86 47K_0402_5%@

1 2

DV1 RB751V-40_SOD323-2

SCS00006S00

RV91 10K_0402_5%

1 2 1 2

RV93 10K_0402_5%

RV118

@

10K_0402_5%

1 2

PS_2

1

CV154

0.1U_0402_10V7-K

2

PS_3

1

CV156

0.1U_0402_10V7-K

2

2015/01/12

2

@

+3VS_VGA

12

@

RV92 10K_0402_5%

12

RV94

@

10K_0402_5%

RV119

@

10K_0402_5%

1 2

Samsung

Hynix

Micron

LC Future Center Secret Data

@

1G

2G

1G

2G

1G

2G

Deciphered Date

RV87

1 2

@

2.2K_0402_5%

12

RV88

@

100K_0402_5%

+3VS_VGA

CV149

0.1U_0402_10V7-K

1

@

2

1

CV151

CV152

@

0.1U_0402_10V7-K

RV120 10K_0402_5%

EXO@

10U_0603_6.3V6-M

2

1 2

SA22225SH30*4

SA000063F30*4

SA00005VS10*4

SA00007DU00*4

SA00005M100*4

SA000060I00*4(SA00007QJ00)

RV147 0_0402_5%@ RV148 0_0402_5%@

UV2

1 2 3 5

74AVCH2T45GD_XSON8_3X2

RV95

1 2

@

10K_0402_5%

SVI2_SVD SVI2_SVT

2016/01/12

C

2

QV3

@

B

MMST3904-7-F_SOT323-3

CV148

0.1U_0402_10V7-K

E

SB000010U00

3 1

1

@

2

1 2

VCC(A) 1A 2A DIR

1 2

@

+1.8VS_VGA+3VS_VGA

VCC(B)

1B 2B

GND

+3VS_VGA

RV121 10K_0402_5%

@

1 2

RV122 10K_0402_5%

DIS@

1 2

+1.8VS_VGA

8 7

RV96 33_0402_5%@

6

RV97 33_0402_5%@

4

1 2

RV104Memory (GDDR3)

PU 8.45K

PU 3.4K PD 10K

PU 4.53K PD 2K

PU 4.75K NC

NC PD 4.75K

PU 3.24K PD 5.62K

Title

R16M-M1-30_CLK/GPIO

Size

Document Number Rev

Custom

Date: Sheet of

H_THERMTRIP# [8]

1

CV150

@

0.1U_0402_10V7-K

2

1 2 1 2

RV123

RV125

10K_0402_5%

@

MESO@

1 2

RV126

RV124

10K_0402_5%

@

1 2

Pre-PWROK Metal VID

SVC SVD Boot Voltage

0 0 001

1

1 1

1.1V

1.0V

0.9V(Default)

0.8V

RV105

PD 2K

DL470_NM-B021

Friday, November 04, 2016

1

SVI2_SVD SVI2_SVC

001

110

010

111

000

101

30 99

0.2

Lenovo ThinkPad L470 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual