Lenovo THINKPAD L460 Schematic
A
www.laptoprepairsecrets.com
B
C
D
E
1 1
LCFC Confidential
BL460
(L460)
2 2
NM-A651 Rev1.0 Schematic
Intel SKL Processor with DDRIIIL + PCH
3 3
AMD Exo Pro Radeon R5 64bit
2015-10-22 Rev1.0
4 4
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
2015/01/12
2015/01/12
2015/01/12
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
2016/01/12
2016/01/12
2016/01/12
Title
COVER PAGE
COVER PAGE
COVER PAGE
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
Friday, October 23, 2015
Friday, October 23, 2015
Date: Sheet
Date: Sheet of
Date: Sheet of
Friday, October 23, 2015
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
E
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B
C
D
E
DDR3L/-RS SODIMM T3/8L
eDP Conn.
Page 52
1 1
mDP Conn.
Page 46
VGA Conn
DP Traslater to CRT
Re-driver
Pericom PI3EQXDP1201
Sub boardSub board
Page 44
DP Switch
Parade
eDP
DDI1
DDI2
PS8338B
Page 47
Docking CS13
2 2
RJ45 Conn.
Page 62
Pericom(Reserve)
PI3L720ZHEX
Page 45
Page 61
Intel
WGI219V Non Vpro
WGI219LM Vpro
Page 60
USB 3.0 Port 3
PCIe Gen1 Port 10
INTEL
SKL 2+2
PCH-LP
42 mm x 24 mm
BGA package
(BGA1356)
Realtek
RTS5232S
SD/MMC/XD Conn
3 3
TPM
Page 71
Infenon NPCT650
Page 70
SPI ROM
(8MB for NVpro)
Power Circuit DC/DC
(16MB for Vpro)
Page 8
Combon Jack Board
&
JUSB3
USB 2.0 Port4/USB 3.0 Port4
4 4
HP_R/L_JACK
Ext Mic
PCIe Gen1 Port 3
SPI BUS
Mirror function
EC
ITE IT8586E/FX
Click Pad
Page 63
LPC BUS
Page 77
Int.KBD
Page 65
Back-to-Back (B2B) Interleave (IL)
1.35V DDRIIIL 1333/1600 MT/s
PCIE Port 5
AMD Exo Pro Radeon R5 64bit
631-FCBGA 23x23mm
VRAM 128M*16 *8, VRAM 256M*16 *8
USB 2.0 Port1,2
USB 3.0 Port1,2
PCIe Gen1 Port 9
SATA Gen3 Port 2
USB 2.0 port 5&7
SATA Gen3 Port 1
USB 2.0 Port 6&9
HDA
USB 2.0 Port 10
SMBus
JUSB1
USB 3.0 Port 1 USB 3.0 Port 2
USB 2.0 Port 0
NGFF Card WLAN
PCIe Port 3
USB 2.0 port 7
SATA HDD
Page 51
Finger Printer
USB 2.0 port 6 USB 2.0 port 5
Codec
ALC3245-GRT
Page 56
Touch Panel
Page 52
Thermal Sensor
Fintek F75303M
G Sensor
ST LIS3DHTR
JUSB2
USB 2.0 Port 1
NGFF Card
mSATA/WWAN(option)
Page 69
Page 70
DDR3L-SO-DIMM X2
BANK 0, 1, 2, 3
Up to 32G
Page 31~39
Page 54
SATA Port 2
USB 2.0 port 9
Smart Card
SPK OUT R/L
Page 66
Page 73
SPK Conn.
Page 22,23
Page 58
Camera Board
Title
Title
Security Classification
Security Classification
USB 2.0 Port 8
A
B
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
2015/01/12
2015/01/12
2015/01/12
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
2016/01/12
2016/01/12
2016/01/12
Title
BLOCK DIAGRAM
BLOCK DIAGRAM
BLOCK DIAGRAM
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
Friday, October 23, 2015
Friday, October 23, 2015
Date: Sheet
Date: Sheet of
Date: Sheet of
Friday, October 23, 2015
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
E
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C
D
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O --> Means ON
Voltage Rails
1 1
Power Plane
+1VALW
+3VALW
B+
+1.8VALW
+5VALW
State
2 2
S0
S3
S5 S4/AC Only
S5 S4
Battery only
O
O O O
O
O
O
O
X X
+1.35V
+0.675VS
+VCC_ST
X --> Means OFF
OO
X
+5VS
+3VS
+VCC_CORE
+VCC_GT
+VCC_SA
+VCC_IO
+VCC_STG
+VGA_CORE
+1.5VS
+0.95VS_VGA
+1.5VS_VGA
+1.8VS_VGA
+3VS_VGA
X
X
X
STATE
Full ON
S1 (Power on)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
SLP_A# SLP_S3# SLP_S4# SLP_S5# VM_PWRON EC_ON SUSP#
HIGH HIGH HIGH HIGH
HIGH
LOW LOW
SMBUS Control Table
SOURCE
IT8586EEC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK3
EC_SMB_DA3
PCH_SMB_CLK
PCH_SMB_DATA
PCH_SML0_CLK
PCH_SML0_DAT
+3VL
IT8586E
+3VS
PCH
+3V_PCH
PCH
+3V_PCH
+3VS_VGA
SIGNAL
Main
VGA
X
V
X X
HIGH
LOWLOWLOW
BATT SODIMM
V
+3VALW
+3VS
ON
Thermal
Sensor
ON
ON
ON
HIGHHIGHHIGH
HIGH
HIGH
WLAN
WiMAX
X X
X
V
X
+3VS
V
+3VS
V
V
+3VS
PCH
XX
V
+3V_PCH
X
ONONON
ON
ONONOFF
OFF
ON
OFFLOW LOW LOW LOW
ON
CP
Module
X
XX
V
+5VS
Security
ROM
X
X
V
+3VS
X X X X X X X X V
LAN PHY
X
X
X
+3VALW
S5 S4
AC & Battery
don't exist
3 3
4 4
X X
X
X
HSIO Port
DevicePort
1 USB port (On Board)
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
USB3.0 port (On Board)
USB3.0 port (On Board)
USB3.0 port (Docking)
USB3.0 port (Sub Board)
N/A
N/A
PCIE (Card Reader)
N/A
PCIE (GPU)
PCIE (GPU)
PCIE (GPU)
PCIE (GPU)
PCIE (WLAN)
PCIE (LAN)
SATA (HDD)
SATA (NGFF)
USB2.0 Port
1
2
3
4
5
6
7
8
9
10
USB port (On bBoard)
USB port (Docking)
USB port (Sub Board)
WWAN
Finger Printer
BT
Camera
Smart Card
Touch Panel
DevicePort
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
2015/01/12
2015/01/12
2015/01/12
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
2016/01/12
2016/01/12
2016/01/12
Title
Title
Title
NOTE LIST
NOTE LIST
NOTE LIST
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
Friday, October 23, 2015
Friday, October 23, 2015
Date: Sheet
Date: Sheet of
Date: Sheet of
Friday, October 23, 2015
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
E
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VGA GPIO (EXO-PRO-S3)
GPIO I/O ACTIVE Function Description
D D
GPIO0
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO15
C C
GPIO16
GPIO17
GPIO19
GPIO20 IN
GPIO21
GPIO22 OUT
GPIO29
GPIO30
OUT
N/A
IN
IN
OUT
N/A
OUT
N/A
OUT
N/A
OUT
N/A
OUT
N/A
OUT
N/A
OUT
N/A
IN
OUT
N/A
N/A
OUT
OUT N/A
OUT N/A
N/A
OUT
N/A
OUT
N/A
GPIO5_AC_BATT
GPIO6
GPIO8_ROMSO
GPIO9_ROMSI
GPIO10_ROMSCK
SVI2_SVD
GPIO19_CTF
SVI2_SVC
GPIO22_ROMCSB
BOM Structure Table
BOM Structure
PCB@ For PCB load BOM
3G@
DIS@
UMA@
3G function with WWAN
Discreate SKU
UMA SKU
DPRE@ With DP re-driver
NODPRE@ Bypass DP re-driver
NVPRO@
For Non-VPRO function
For VPRO functionVPRO@
MIRROR@ For mirror function
TPM@
X76@
TPM function
GPU VRAM Setting
XDP@ XDP function
EXO@ EXO function
ME@
ME Connector
For EMC functionEMC@
EMC_NS@
For EMC function (no mount)
RF@ For RF function
RF_NS@ For RF function (no mount)
NOTE
B B
+3VS_VGA
+0.95VS_VGA
+1.8VS_VGA
+VGA_CORE
+1.5VS_VGA
A A
GPU POWER UP sequence GPU POWER DOWN sequence
> 10us
< 20ms
5
4
< 20ms
Device ID
EXO-pro 6660
Samsung
1000MHz
Hynix
1000MHz
Micro
1000MHz
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
3
2015/01/12
2015/01/12
2015/01/12
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
GPU
VRAM (GDDR3)
K4W4G1646E-BC1A (2G)
H5TC4G63CFR-N0C (2G)
MT41J256M16HA-093G:E (2G)
2016/01/12
2016/01/12
2016/01/12
2
EXO-Pro-S3
PS_3 (RV104)
PH 3.4K
PH 4.75K
PH 3.24K
Title
Title
Title
VGA NOTE
VGA NOTE
VGA NOTE
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
Friday, October 23, 2015
Friday, October 23, 2015
Date: Sheet of
Date: Sheet of
Date: Sheet of
Friday, October 23, 2015
PS_3 (RV105)
PD 10K
NC
PD 5.62K
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
1
4 99
4 99
4 99
0.1
0.1
0.1
5
www.laptoprepairsecrets.com
D D
4
3
2
1
1 2
1 2
1 2
1 2
SKL_U LT
DDI
DISPLAY SIDEBANDS
1 OF 20REV = 1
EDP
GPP_E13/DDPB_HPD0
GPP_E14/DDPC_HPD1
GPP_E15/DDPD_HPD2
GPP_E16/DDPE_HPD3
GPP_E17/EDP_HPD
DDIP1_CTRLCLK
DDIP1_CTRLDATA
DDIP2_CTRLCLK
DDIP2_CTRLDATA
EDP_TXN[0]
EDP_TXP[0]
EDP_TXN[1]
EDP_TXP[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]
EDP_AUXN
EDP_AUXP
EDP_DISP_UTIL
DDI1_AUXN
DDI1_AUXP
DDI2_AUXN
DDI2_AUXP
DDI3_AUXN
DDI3_AUXP
EDP_BKLTEN
EDP_BKLTCTL
EDP_VDDEN
C47
C46
D46
C45
A45
B45
A47
B47
E45
F45
B52
G50
F50
E48
F48
G46
F46
L9
L7
L6
N9
L10
R12
R11
U13
MINI-DP
CPU_EDP_TX0CPU_EDP_TX0+
CPU_EDP_TX1CPU_EDP_TX1+
CPU_EDP_TX2CPU_EDP_TX2+
CPU_EDP_TX3CPU_EDP_TX3+
CPU_EDP_AUX#
CPU_EDP_AUX
DDIP1_AUXN
DDIP1_AUXP
DDIP2_AUXN
DDIP2_AUXP
DDIP1_HPD
DDIP2_HPD
CPU_EDP_HPD
ENBKL
PCH_EDP_PWM
PCH_ENVDD
DDIP1_HPD
DDIP2_HPD
CPU_EDP_HPD
ENBKL
CPU_EDP_TX0- [52]
CPU_EDP_TX0+ [52]
CPU_EDP_TX1- [52]
CPU_EDP_TX1+ [52]
CPU_EDP_TX2- [52]
CPU_EDP_TX2+ [52]
CPU_EDP_TX3- [52]
CPU_EDP_TX3+ [52]
CPU_EDP_AUX# [52]
CPU_EDP_AUX [52]
DDIP1_AUXN [44]
DDIP1_AUXP [44]
DDIP2_AUXN [47]
DDIP2_AUXP [47]
DDIP1_HPD [44,46]
DDIP2_HPD [47]
CPU_EDP_HPD [52]
ENBKL [77]
PCH_EDP_PWM [52]
PCH_ENVDD [52]
1 2
RC103 100K_0402_5%
1 2
RC57 100K_0402_5%
1 2
RC58 100K_0402_5%
1 2
RC59 100K_0402_5%
CPU_DDI1_N0[44]
CPU_DDI1_P0[44]
DDIP1_CTRLCLK[44,46]
DDIP2_CTRLCLK[45]
DDIP1_CTRLDATA[44,46]
DDIP2_CTRLDATA[45]
CPU_DDI1_N1[44]
CPU_DDI1_P1[44]
CPU_DDI1_N2[44]
CPU_DDI1_P2[44]
CPU_DDI1_N3[44]
CPU_DDI1_P3[44]
CPU_DDI2_N0[47]
CPU_DDI2_P0[47]
CPU_DDI2_N1[47]
CPU_DDI2_P1[47]
CPU_DDI2_N2[47]
CPU_DDI2_P2[47]
CPU_DDI2_N3[47]
CPU_DDI2_P3[47]
1 2
24.9_0402_1%
RC1
MINI DP
C C
B B
DOCKING & D-SUB
MINI-DP
DOCKING
+VCC_IO
EDP_RCOMP
1. Trace width=20 mils, Spacing=25mil, Max length=100mils
2. RC1 close to MCP
Trace Width=20mil, Spacing=25mil, Max length=100mil
CPU_DDI1_N0
CPU_DDI1_P0
CPU_DDI1_N1
CPU_DDI1_P1
CPU_DDI1_N2
CPU_DDI1_P2
CPU_DDI1_N3
CPU_DDI1_P3
CPU_DDI2_N0
CPU_DDI2_P0
CPU_DDI2_N1
CPU_DDI2_P1
CPU_DDI2_N2
CPU_DDI2_P2
CPU_DDI2_N3
CPU_DDI2_P3
DDIP1_CTRLCLK
DDIP1_CTRLDATA
DDIP2_CTRLCLK
DDIP2_CTRLDATA
EDP_COMP
UC1A
E55
DDI1_TXN[0]
F55
DDI1_TXP[0]
E58
DDI1_TXN[1]
F58
DDI1_TXP[1]
F53
DDI1_TXN[2]
G53
DDI1_TXP[2]
F56
DDI1_TXN[3]
G56
DDI1_TXP[3]
C50
DDI2_TXN[0]
D50
DDI2_TXP[0]
C52
DDI2_TXN[1]
D52
DDI2_TXP[1]
A50
DDI2_TXN[2]
B50
DDI2_TXP[2]
D51
DDI2_TXN[3]
C51
DDI2_TXP[3]
L13
GPP_E18/DDPB_CTRLCLK
L12
GPP_E19/DDPB_CTRLDATA
N7
GPP_E20/DDPC_CTRLCLK
N8
GPP_E21/DDPC_CTRLDATA
N11
GPP_E22/DDPD_CTRLCLK
N12
GPP_E23/DDPD_CTRLDATA
E52
EDP_RCOMP
SKYLAKE-U_BGA1356
+3VS
RC12 2.2K_0402_5%@
RC13 2.2K_0402_5%
RC49 2.2K_0402_5%@
RC52 2.2K_0402_5%
DDIP2_HPD : PS8338B has Int.PD 150K
DP port
DDPB_CTRLDATA
DDPC_CTRLDATA
Enable Disable
pull-high
pull-high
no connect
no connect
A A
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
3
2015/01/12
2015/01/12
2015/01/12
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2016/01/12
2016/01/12
2016/01/12
Title
SKL_DDI/eDP
SKL_DDI/eDP
SKL_DDI/eDP
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
Friday, October 23, 2015
Friday, October 23, 2015
Date: Sheet of
Date: Sheet of
Date: Sheet of
Friday, October 23, 2015
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
1
5 99
5 99
5 99
0.1
0.1
0.1
5
www.laptoprepairsecrets.com
DDR_A_D[0..63][22]
DDR_A_DQS#[0..7][22]
DDR_A_DQS[0..7][22]
DDR_A_MA[0..15][22]
DDR_B_D[0..63][23]
D D
DDR_B_DQS#[0..7][23]
DDR_B_DQS[0..7][23]
DDR_B_MA[0..15][23]
4
3
2
1
UC1B
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
C C
B B
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
AL71
DDR0_DQ[0]
AL68
DDR0_DQ[1]
AN68
DDR0_DQ[2]
AN69
DDR0_DQ[3]
AL70
DDR0_DQ[4]
AL69
DDR0_DQ[5]
AN70
DDR0_DQ[6]
AN71
DDR0_DQ[7]
AR70
DDR0_DQ[8]
AR68
DDR0_DQ[9]
AU71
DDR0_DQ[10]
AU68
DDR0_DQ[11]
AR71
DDR0_DQ[12]
AR69
DDR0_DQ[13]
AU70
DDR0_DQ[14]
AU69
DDR0_DQ[15]
BB65
DDR0_DQ[16]/DDR0_DQ[32]
AW65
DDR0_DQ[17]/DDR0_DQ[33]
AW63
DDR0_DQ[18]/DDR0_DQ[34]
AY63
DDR0_DQ[19]/DDR0_DQ[35]
BA65
DDR0_DQ[20]/DDR0_DQ[36]
AY65
DDR0_DQ[21]/DDR0_DQ[37]
BA63
DDR0_DQ[22]/DDR0_DQ[38]
BB63
DDR0_DQ[23]/DDR0_DQ[39]
BA61
DDR0_DQ[24]/DDR0_DQ[40]
AW61
DDR0_DQ[25]/DDR0_DQ[41]
BB59
DDR0_DQ[26]/DDR0_DQ[42]
AW59
DDR0_DQ[27]/DDR0_DQ[43]
BB61
DDR0_DQ[28]/DDR0_DQ[44]
AY61
DDR0_DQ[29]/DDR0_DQ[45]
BA59
DDR0_DQ[30]/DDR0_DQ[46]
AY59
DDR0_DQ[31]/DDR0_DQ[47]
AY39
DDR0_DQ[32]/DDR1_DQ[0]
AW39
DDR0_DQ[33]/DDR1_DQ[1]
AY37
DDR0_DQ[34]/DDR1_DQ[2]
AW37
DDR0_DQ[35]/DDR1_DQ[3]
BB39
DDR0_DQ[36]/DDR1_DQ[4]
BA39
DDR0_DQ[37]/DDR1_DQ[5]
BA37
DDR0_DQ[38]/DDR1_DQ[6]
BB37
DDR0_DQ[39]/DDR1_DQ[7]
AY35
DDR0_DQ[40]/DDR1_DQ[8]
AW35
DDR0_DQ[41]/DDR1_DQ[9]
AY33
DDR0_DQ[42]/DDR1_DQ[10]
AW33
DDR0_DQ[43]/DDR1_DQ[11]
BB35
DDR0_DQ[44]/DDR1_DQ[12]
BA35
DDR0_DQ[45]/DDR1_DQ[13]
BA33
DDR0_DQ[46]/DDR1_DQ[14]
BB33
DDR0_DQ[47]/DDR1_DQ[15]
AY31
DDR0_DQ[48]/DDR1_DQ[32]
AW31
DDR0_DQ[49]/DDR1_DQ[33]
AY29
DDR0_DQ[50]/DDR1_DQ[34]
AW29
DDR0_DQ[51]/DDR1_DQ[35]
BB31
DDR0_DQ[52]/DDR1_DQ[36]
BA31
DDR0_DQ[53]/DDR1_DQ[37]
BA29
DDR0_DQ[54]/DDR1_DQ[38]
BB29
DDR0_DQ[55]/DDR1_DQ[39]
AY27
DDR0_DQ[56]/DDR1_DQ[40]
AW27
DDR0_DQ[57]/DDR1_DQ[41]
AY25
DDR0_DQ[58]/DDR1_DQ[42]
AW25
DDR0_DQ[59]/DDR1_DQ[43]
BB27
DDR0_DQ[60]/DDR1_DQ[44]
BA27
DDR0_DQ[61]/DDR1_DQ[45]
BA25
DDR0_DQ[62]/DDR1_DQ[46]
BB25
DDR0_DQ[63]/DDR1_DQ[47]
SKYLAKE-U_BGA1356
SKL_U LT
DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]
DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]
DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#
DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]
DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]
DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]
DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]
DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]
DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]
DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]
DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]
DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]
DDR0_DQSN[2]/DDR0_DQSN[4]
DDR0_DQSP[2]/DDR0_DQSP[4]
DDR0_DQSN[3]/DDR0_DQSN[5]
DDR0_DQSP[3]/DDR0_DQSP[5]
DDR0_DQSN[4]/DDR1_DQSN[0]
DDR0_DQSP[4]/DDR1_DQSP[0]
DDR0_DQSN[5]/DDR1_DQSN[1]
DDR0_DQSP[5]/DDR1_DQSP[1]
DDR0_DQSN[6]/DDR1_DQSN[4]
DDR0_DQSP[6]/DDR1_DQSP[4]
DDR0_DQSN[7]/DDR1_DQSN[5]
DDR0_DQSP[7]/DDR1_DQSP[5]
DDR CH - A
2 OF 20REV = 1
DDR0_CKN[0]
DDR0_CKP[0]
DDR0_CKN[1]
DDR0_CKP[1]
DDR0_CKE[0]
DDR0_CKE[1]
DDR0_CKE[2]
DDR0_CKE[3]
DDR0_CS#[0]
DDR0_CS#[1]
DDR0_ODT[0]
DDR0_ODT[1]
DDR0_MA[3]
DDR0_MA[4]
DDR0_DQSN[0]
DDR0_DQSP[0]
DDR0_DQSN[1]
DDR0_DQSP[1]
DDR0_ALERT#
DDR0_PAR
DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ
DDR_VTT_CNTL
AU53
AT53
AU55
AT55
BA56
BB56
AW56
AY56
AU45
AU43
AT45
AT43
BA51
BB54
BA52
AY52
AW52
AY55
AW54
BA54
BA55
AY54
AU46
AU48
AT46
AU50
AU52
AY51
AT48
AT50
BB50
AY50
BA50
BB52
AM70
AM69
AT69
AT70
BA64
AY64
AY60
BA60
BA38
AY38
AY34
BA34
BA30
AY30
AY26
BA26
AW50
AT52
AY67
AY68
BA67
AW67
SA_CLK_DDR#0
SA_CLK_DDR0
SA_CLK_DDR#1
SA_CLK_DDR1
DDRA_CKE0_DIMMA
DDRA_CKE1_DIMMA
DDRA_CS0_DIMMA#
DDRA_CS1_DIMMA#
DDRA_ODT0_DIMMA#
DDRA_ODT1_DIMMA#
DDR_A_MA5
DDR_A_MA9
DDR_A_MA6
DDR_A_MA8
DDR_A_MA7
DDR_A_BS2
DDR_A_MA12
DDR_A_MA11
DDR_A_MA15
DDR_A_MA14
DDR_A_MA13
DDR_A_CAS#
DDR_A_WE#
DDR_A_RAS#
DDR_A_BS0
DDR_A_MA2
DDR_A_BS1
DDR_A_MA10
DDR_A_MA1
DDR_A_MA0
DDR_A_MA3
DDR_A_MA4
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_DQS#7
DDR_A_DQS7
SM_DIMM_VREFCA
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
DDR_PG_CTRL
SA_CLK_DDR#0 [22]
SA_CLK_DDR0 [22]
SA_CLK_DDR#1 [22]
SA_CLK_DDR1 [22]
DDRA_CKE0_DIMMA [22]
DDRA_CKE1_DIMMA [22]
DDRA_CS0_DIMMA# [22]
DDRA_CS1_DIMMA# [22]
DDRA_ODT0_DIMMA# [22]
DDRA_ODT1_DIMMA# [22]
DDR_A_BS2 [22]
DDR_A_CAS# [22]
DDR_A_WE# [22]
DDR_A_RAS# [22]
DDR_A_BS0 [22]
DDR_A_BS1 [22]
SM_DIMM_VREFCA [22]
SA_DIMM_VREFDQ [22]
SB_DIMM_VREFDQ [23]
DDR_PG_CTRL [22]
DDR_B_D13
DDR_B_D9
DDR_B_D11
DDR_B_D14
DDR_B_D12
DDR_B_D8
DDR_B_D15
DDR_B_D10
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D5
DDR_B_D4
DDR_B_D7
DDR_B_D6
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D29
DDR_B_D28
DDR_B_D30
DDR_B_D31
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D21
DDR_B_D20
DDR_B_D22
DDR_B_D23
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
UC1C
AF65
DDR1_DQ[0]/DDR0_DQ[16]
AF64
DDR1_DQ[1]/DDR0_DQ[17]
AK65
DDR1_DQ[2]/DDR0_DQ[18]
AK64
DDR1_DQ[3]/DDR0_DQ[19]
AF66
DDR1_DQ[4]/DDR0_DQ[20]
AF67
DDR1_DQ[5]/DDR0_DQ[21]
AK67
DDR1_DQ[6]/DDR0_DQ[22]
AK66
DDR1_DQ[7]/DDR0_DQ[23]
AF70
DDR1_DQ[8]/DDR0_DQ[24]
AF68
DDR1_DQ[9]/DDR0_DQ[25]
AH71
DDR1_DQ[10]/DDR0_DQ[26]
AH68
DDR1_DQ[11]/DDR0_DQ[27]
AF71
DDR1_DQ[12]/DDR0_DQ[28]
AF69
DDR1_DQ[13]/DDR0_DQ[29]
AH70
DDR1_DQ[14]/DDR0_DQ[30]
AH69
DDR1_DQ[15]/DDR0_DQ[31]
AT66
DDR1_DQ[16]/DDR0_DQ[48]
AU66
DDR1_DQ[17]/DDR0_DQ[49]
AP65
DDR1_DQ[18]/DDR0_DQ[50]
AN65
DDR1_DQ[19]/DDR0_DQ[51]
AN66
DDR1_DQ[20]/DDR0_DQ[52]
AP66
DDR1_DQ[21]/DDR0_DQ[53]
AT65
DDR1_DQ[22]/DDR0_DQ[54]
AU65
DDR1_DQ[23]/DDR0_DQ[55]
AT61
DDR1_DQ[24]/DDR0_DQ[56]
AU61
DDR1_DQ[25]/DDR0_DQ[57]
AP60
DDR1_DQ[26]/DDR0_DQ[58]
AN60
DDR1_DQ[27]/DDR0_DQ[59]
AN61
DDR1_DQ[28]/DDR0_DQ[60]
AP61
DDR1_DQ[29]/DDR0_DQ[61]
AT60
DDR1_DQ[30]/DDR0_DQ[62]
AU60
DDR1_DQ[31]/DDR0_DQ[63]
AU40
DDR1_DQ[32]/DDR1_DQ[16]
AT40
DDR1_DQ[33]/DDR1_DQ[17]
AT37
DDR1_DQ[34]/DDR1_DQ[18]
AU37
DDR1_DQ[35]/DDR1_DQ[19]
AR40
DDR1_DQ[36]/DDR1_DQ[20]
AP40
DDR1_DQ[37]/DDR1_DQ[21]
AP37
DDR1_DQ[38]/DDR1_DQ[22]
AR37
DDR1_DQ[39]/DDR1_DQ[23]
AT33
DDR1_DQ[40]/DDR1_DQ[24]
AU33
DDR1_DQ[41]/DDR1_DQ[25]
AU30
DDR1_DQ[42]/DDR1_DQ[26]
AT30
DDR1_DQ[43]/DDR1_DQ[27]
AR33
DDR1_DQ[44]/DDR1_DQ[28]
AP33
DDR1_DQ[45]/DDR1_DQ[29]
AR30
DDR1_DQ[46]/DDR1_DQ[30]
AP30
DDR1_DQ[47]/DDR1_DQ[31]
AU27
DDR1_DQ[48]
AT27
DDR1_DQ[49]
AT25
DDR1_DQ[50]
AU25
DDR1_DQ[51]
AP27
DDR1_DQ[52]
AN27
DDR1_DQ[53]
AN25
DDR1_DQ[54]
AP25
DDR1_DQ[55]
AT22
DDR1_DQ[56]
AU22
DDR1_DQ[57]
AU21
DDR1_DQ[58]
AT21
DDR1_DQ[59]
AN22
DDR1_DQ[60]
AP22
DDR1_DQ[61]
AP21
DDR1_DQ[62]
AN21
DDR1_DQ[63]
SKYLAKE-U_BGA1356
SKL_U LT
DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]
DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]
DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#
DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]
DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]
DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]
DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]
DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]
DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]
DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]
DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]
DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
DDR1_DQSN[0]/DDR0_DQSN[2]
DDR1_DQSP[0]/DDR0_DQSP[2]
DDR1_DQSN[1]/DDR0_DQSN[3]
DDR1_DQSP[1]/DDR0_DQSP[3]
DDR1_DQSN[2]/DDR0_DQSN[6]
DDR1_DQSP[2]/DDR0_DQSP[6]
DDR1_DQSN[3]/DDR0_DQSN[7]
DDR1_DQSP[3]/DDR0_DQSP[7]
DDR1_DQSN[4]/DDR1_DQSN[2]
DDR1_DQSP[4]/DDR1_DQSP[2]
DDR1_DQSN[5]/DDR1_DQSN[3]
DDR1_DQSP[5]/DDR1_DQSP[3]
DDR CH - B
3 OF 20REV = 1
DDR1_CKN[0]
DDR1_CKN[1]
DDR1_CKP[0]
DDR1_CKP[1]
DDR1_CKE[0]
DDR1_CKE[1]
DDR1_CKE[2]
DDR1_CKE[3]
DDR1_CS#[0]
DDR1_CS#[1]
DDR1_ODT[0]
DDR1_ODT[1]
DDR1_MA[3]
DDR1_MA[4]
DDR1_DQSN[6]
DDR1_DQSP[6]
DDR1_DQSN[7]
DDR1_DQSP[7]
DDR1_ALERT#
DDR1_PAR
DRAM_RESET#
DDR_RCOMP[0]
DDR_RCOMP[1]
DDR_RCOMP[2]
AN45
AN46
AP45
AP46
AN56
AP55
AN55
AP53
BB42
AY42
BA42
AW42
AY48
AP50
BA48
BB48
AP48
AP52
AN50
AN48
AN53
AN52
BA43
AY43
AY44
AW44
BB44
AY47
BA44
AW46
AY46
BA46
BB46
BA47
AH66
AH65
AG69
AG70
AR66
AR65
AR61
AR60
AT38
AR38
AT32
AR32
AR25
AR27
AR22
AR21
AN43
AP43
AT13
AR18
AT18
AU18
SB_CLK_DDR#0
SB_CLK_DDR#1
SB_CLK_DDR0
SB_CLK_DDR1
DDRB_CKE0_DIMMB
DDRB_CKE1_DIMMB
DDRB_CS0_DIMMB#
DDRB_CS1_DIMMB#
DDRB_ODT0_DIMMB#
DDRB_ODT1_DIMMB#
DDR_B_MA5
DDR_B_MA9
DDR_B_MA6
DDR_B_MA8
DDR_B_MA7
DDR_B_BS2
DDR_B_MA12
DDR_B_MA11
DDR_B_MA15
DDR_B_MA14
DDR_B_MA13
DDR_B_CAS#
DDR_B_WE#
DDR_B_RAS#
DDR_B_BS0
DDR_B_MA2
DDR_B_BS1
DDR_B_MA10
DDR_B_MA1
DDR_B_MA0
DDR_B_MA3
DDR_B_MA4
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_DQS#7
DDR_B_DQS7
DDR3_DRAMRST#
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
RC8 121_0402_1%
RC9 80.6_0402_1%
RC10 100_0402_1%
SB_CLK_DDR#0 [23]
SB_CLK_DDR#1 [23]
SB_CLK_DDR0 [23]
SB_CLK_DDR1 [23]
DDRB_CKE0_DIMMB [23]
DDRB_CKE1_DIMMB [23]
DDRB_CS0_DIMMB# [23]
DDRB_CS1_DIMMB# [23]
DDRB_ODT0_DIMMB# [23]
DDRB_ODT1_DIMMB# [23]
DDR_B_BS2 [23]
DDR_B_CAS# [23]
DDR_B_WE# [23]
DDR_B_RAS# [23]
DDR_B_BS0 [23]
DDR_B_BS1 [23]
DG - Not used at DDR3L. Tied to GND.
DDR3_DRAMRST# [22,23]
1 2
1 2
1 2
A A
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
3
2015/01/12
2015/01/12
2015/01/12
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2016/01/12
2016/01/12
2016/01/12
Title
SKL_DDR3L
SKL_DDR3L
SKL_DDR3L
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
Friday, October 23, 2015
Friday, October 23, 2015
Date: Sheet of
Date: Sheet of
Date: Sheet of
Friday, October 23, 2015
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
1
6 99
6 99
6 99
0.1
0.1
0.1
5
www.laptoprepairsecrets.com
D D
+VCC_STG
12
RC2
1K_0402_5%
12
RC61
1K_0402_1%
12
RC51
10K_0402_5%
RC3
1 2
499_0402_1%
VR_HOT#[77,85,93]
C C
H_THERMTRIP#[30]
EC_WAKE#[30,77]
VR_HOT#
RC62
1 2
@
0_0402_5%
RC54
1 2
0_0402_5%
+VCC_ST
+3V_PCH
4
H_PECI[77]
1 2
RC151 49.9_0402_1%
1 2
RC114 49.9_0402_1%
1 2
RC200 49.9_0402_1%
1 2
RC113 49.9_0402_1%
T60
T15
T16
T23
T22
1
CATERR#
H_PECI
VR_HOT#_R
THRMTRIP#
XDP_BPM#0
1
XDP_BPM#1
1
XDP_BPM#2
1
XDP_BPM#3
1
EC_WAKE#_SUS
PROC_POPIRCOMP
PCH_OPIRCOMP
OPCE_RCOMP
OPC_RCOMP
UC1D
D63
CATERR#
A54
PECI
C65
PROCHOT#
C63
THERMTRIP#
A65
SKTOCC#
C55
BPM#[0]
D55
BPM#[1]
B54
BPM#[2]
C56
BPM#[3]
A6
GPP_E3/CPU_GP0
A7
GPP_E7/CPU_GP1
BA5
GPP_B3/CPU_GP2
AY5
GPP_B4/CPU_GP3
AT16
PROC_POPIRCOMP
AU16
PCH_OPIRCOMP
H66
OPCE_RCOMP
H65
OPC_RCOMP
SKYLAKE-U_BGA1356
3
SKL_U LT
CPU MISC
4 OF 20REV = 1
JTAG
PROC_TCK
PROC_TDI
PROC_TDO
PROC_TMS
PROC_TRST#
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
PCH_TRST#
JTAGX
B61
D60
A61
C60
B59
B56
D59
A56
C59
C61
A59
XDP_TCLK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
PCH_JTAG_TRST#
PCH_JTAGX
2
[SKL PDG]Refer Figure 45-1
1
T13
1
T26
1
T29
1
T32
1
T17
1
T33
1
T30
1
T25
1
T28
1
T31
1
T27
XDP_TDO
XDP_TDI
XDP_TMS
XDP_TCLK
XDP_TRST#
1 2
RC4 51_0402_1%XDP@
1 2
RC116 51_0402_1%@
1 2
RC115 51_0402_1%@
1 2
RC7 51_0402_1%
1 2
RC6 51_0402_1%@
1
+VCC_ST
B B
A A
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
3
2015/01/12
2015/01/12
2015/01/12
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2016/01/12
2016/01/12
2016/01/12
Title
SKL_XDP/ JTAG
SKL_XDP/ JTAG
SKL_XDP/ JTAG
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
Friday, October 23, 2015
Friday, October 23, 2015
Date: Sheet of
Date: Sheet of
Date: Sheet of
Friday, October 23, 2015
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
1
7 99
7 99
7 99
0.1
0.1
0.1
5
www.laptoprepairsecrets.com
4
3
2
1
Near UC8M1 and UC8M2
1
SPI_SI
SPI_SO
SPI_CLK
SPI_SO
SPI_SI
SPI_IO2
SPI_IO3
SPI_CS0#_8MB
SPI_CS1#_4MB
SPI_CS2#_TPM
DOCK_ID1
DOCK_ID2
DOCK_ID3
DOCK_CAP_ID#
DOCK_ID0
EC_SCI#
CL_CLK_WLAN
CL_DATA_WLAN
CL_RST_WLAN#
KBRST#
SERIRQ
RC298 1K_0402_5%
RC303 20K_0402_5%
RC308 1K_0402_5%
RC309 20K_0402_5%@
SPI_IO3_8MB SPI_IO3
SPI_CLK_8MB
SPI_SI_8MB
SPI_IO2_8MB
D D
C C
SPI_IO3_4MB SPI_IO3
SPI_CLK_4MB
SPI_SI_4MB
SPI_IO2_4MB
Functional Strap Definitions
L:Disable Intel ME Crypto TLS cipher suite (no confidentiality).
*H:Enable Intel ME Crypto Transport Layer Security (TLS) cipher
suite (with confidentiality).Support Intel AMT with TLS and Intel
SBA (Small Business Advantage) with TLS.
GPP_C2, Internal PD 20K
RPC5
1 8
2 7
3 6
4 5
33_0804_8P4R_5%
SD30000370T
RPC7
VPRO@
1 8
2 7
3 6
4 5
33_0804_8P4R_5%
SD30000370T
+3V_PCH
RPC12
10K_0804_8P4R_5%
+3VS
RPC26
1 8
2 7
3 6
4 5
10K_0804_8P4R_5%
GPP_C2
SPI_CLK
SPI_SI
SPI_IO2
SPI_CLK
SPI_SI
SPI_IO2
18
27
36
45
DOCK_ID0
DOCK_ID1
DOCK_ID2
DOCK_ID3
SERIRQ
KBRST#
EC_SCI#
RC306 1K_0402_5%
RC307 20K_0402_5%@
GPP_C5, Internal PD 20K
GPP_C5
B B
SPI_SO_4MB
SPI_SO_8MB
+3V_SPI
RC33 1K_0402_1%
RC34 1K_0402_1%
1 2
1 2
*L: LPC
H: eSPI
@
RC83 1K_0402_5%
1 2
@
RC350 20K_0402_5%
1 2
1 2
1K_0402_1%
To TPM IC
12
1 2
RC32 33_0402_5%VPRO@
1 2
RC31 33_0402_5%
@
1 2
C-LINK
+3V_PCH
RC392
1K_0402_1% @
SPI_CLK[70]
SPI_SI[70]
SPI_SO[70]
SPI_CS2#_TPM[70]
+3VALW_PCH
1 2
CL_DATA_WLAN[66]
CL_RST_WLAN#[66]
CL_CLK_WLAN[66]
DOCK_ID1[45]
DOCK_ID2[45]
DOCK_ID3[45]
DOCK_ID0[45]
KBRST#[77]
SERIRQ[70,77]
SPI_CLK
SPI_SI
SPI_SO
SPI_CS2#_TPM
RC399
T34
EC_SCI#[77]
JTAG ODT
SPI0_MOSI
UC1E
AV2
AW3
AV3
AW2
AU4
AU3
AU2
AU1
M2
M3
J4
V1
V2
M1
G3
G2
G1
AW13
AY11
SKYLAKE-U_BGA1356
1 2
@
1 2
@
RGB(128,255,128)
1 2
@
1 2
SPI - FLASH
SPI0_CLK
SPI0_MISO
SPI0_MOSI
SPI0_IO2
SPI0_IO3
SPI0_CS0#
SPI0_CS1#
SPI0_CS2#
SPI - TOUCH
GPP_D1/SPI1_CLK
GPP_D2/SPI1_MISO
GPP_D3/SPI1_MOSI
GPP_D21/SPI1_IO2
GPP_D22/SPI1_IO3
GPP_D0/SPI1_CS#
C LINK
CL_CLK
CL_DATA
CL_RST#
GPP_A0/RCIN#
GPP_A6/SERIRQ
+3V_SPI
+3V_SPI
20121218
M3 Support, Intel LAN PHY, (Wireless LAN)
+3VM = +3V_SPI
1. VPRO : Q6, +3VLAW To +3VM
2. NVPRO :
a. R17 and RC38, +3VALW to +3VM
1 2
RC37 0_0402_5%@
+3VS
1 2
RC38 0_0402_5%
+3VM
A A
+3V_SPI
+3V_SPI
0.085 A, 10mils
SPI_CLK_8MB
RC381
33_0402_5%
EMC_NS@
CC533
10P_0402_50V8-J
EMC_NS@
12
1
2
SPI_CS0#_8MB
SPI_SO_8MB
SPI_IO2_8MB
SPI_CS1#_4MB
SPI_SO_4MB
SPI_IO2_4MB
Mirror Code, Close to SPI ROM (UC8M1).
FSCE#[77]
SPI_FMOSI#[77]
SPI_FMISO[77]
SPI_FSCK[77]
FSCE#
SPI_FMOSI#
SPI_FMISO
5
1 2
RE1 0_0402_5%
1 2
RE2 0_0402_5%
1 2
RE3 0_0402_5%
1 2
RE4 0_0402_5%
SPI_CS0#_8MB
SPI_SI_8MB
SPI_SO_8MB
SPI_CLK_8MBSPI_FSCK
4
UC8M1
1
CS#
2
DO
3
4
1
2
3
4
HOLD#
WP#
GND
W25Q64FVSSIG_SO8
SA000039A00
UC8M2
VPRO@
CS#
DO
HOLD#
WP#
GND
W25Q64FVSSIG_SO8
SA000039A00
+3V_SPI
8
VCC
SPI_IO3_8MB
7
SPI_CLK_8MB
6
CLK
SPI_SI_8MB
5
DI
+3V_SPI
8
VCC
SPI_IO3_4MB
7
SPI_CLK_4MB
6
CLK
SPI_SI_4MB
5
DI
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
3
SKL_U LT
SMBUS, SMLINK
GPP_B23/SML1ALERT#/PCHHOT#
GPP_C0/SMBCLK
GPP_C1/SMBDATA
GPP_C2/SMBALERT#
GPP_C3/SML0CLK
GPP_C4/SML0DATA
GPP_C5/SML0ALERT#
GPP_C6/SML1CLK
GPP_C7/SML1DATA
R7
R8
R10
R9
W2
W1
W3
V3
AM7
PCH_SMB_CLK
PCH_SMB_DATA
GPP_C2
PCH_SML0_CLK
PCH_SML0_DAT
GPP_C5
PCH_SML1CLK
PCH_SML1DATA
GPP_B23
PCH_SML0_CLK [60]
PCH_SML0_DAT [60]
RC375 150K_0402_5%
LAN PHY
1 2
+3V_PCH
FOR DCI USE
LPC_AD0
LPC
5 OF 20REV = 1
GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3
GPP_A5/LFRAME#/ESPI_CS#
GPP_A14/SUS_STAT#/ESPI_RESET#
GPP_A9/CLKOUT_LPC0/ESPI_CLK
GPP_A10/CLKOUT_LPC1
GPP_A8/CLKRUN#
AY13
BA13
BB13
AY12
BA12
BA11
AW9
AY9
AW11
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
SUS_STAT#
PCH_PCI_CLK_R
CLKRUN#
Security ROM
USROM1
1
2
PLT_RST#[9,14,60,66,70,71,77]
3
4
@
VCC
SCL
SDA
WP
8
7
PM_SMB_CLK
6
PM_SMB_DAT
5
NC_1
NC_2
PROT#
GND
PCA24S08AD_SO8
SA00004MK00/SA00004ML00
SMBus
PCH_SMB_CLK
PCH_SMB_DATA
+3V_SPI
1
CC13
0.1U_0402_10V7-K
2
+3V_SPI
1
CC14
0.1U_0402_10V7-K
2
2015/01/12
2015/01/12
2015/01/12
VPRO@
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
PCH_SML1CLK EC_SMB_CK3
PCH_SML1DATA EC_SMB_DA3
2
EC and TPM Module debug port
RC26 22_0402_5%
RC48 8.2K_0402_5%
+3VS
1
CC12
@
0.1U_0402_10V6-K
2
+3VS
6 1
D
QC1A
5
2N7002KDWH_SOT363-6
G
SB000013A00
3 4
S
D
QC1B
2N7002KDWH_SOT363-6
SB000013A00
+3VS
6 1
D
QC2A
5
2N7002KDWH_SOT363-6
G
SB000013A00
3 4
S
D
QC2B
2N7002KDWH_SOT363-6
SB000013A00
2016/01/12
2016/01/12
2016/01/12
LPC_AD0 [77]
LPC_AD1 [77]
LPC_AD2 [77]
LPC_AD3 [77]
LPC_FRAME# [77]
1
T61
1 2
1 2
PCH_SML0_DAT
PCH_SML0_CLK
DIMM1, DIMM2
CP, Security ROM
RC35 4.7K_0402_5%
2
G
S
2
G
S
RC36 4.7K_0402_5%
PM_SMB_CLK
PM_SMB_DAT
GPU, Thermal Sendor,
Embedded Controller, G sensor
2N7002 KDWH
Vth= min 1V, max 2.5V
ESD 2KV
Title
Title
Title
SKL_LPC/SPI/SMBUS
SKL_LPC/SPI/SMBUS
SKL_LPC/SPI/SMBUS
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
Friday, October 23, 2015
Friday, October 23, 2015
Date: Sheet of
Date: Sheet of
Date: Sheet of
Friday, October 23, 2015
+3VS
RC30 499_0402_1%
RC29 499_0402_1%
PCH_SMB_CLK
PCH_SMB_DATA
PCH_SML1CLK
PCH_SML1DATA
1 2
1 2
1
CV178
RF@
22P_0402_50V8-J
2
1 2
1 2
RPC6
1 8
2 7
3 6
4 5
10K_0804_8P4R_5%
PM_SMB_CLK [22,23,63]
PM_SMB_DAT [22,23,63]
EC_SMB_CK3 [30,69,70,77]
EC_SMB_DA3 [30,69,70,77]
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
1
CLK_PCI_EC [77]
+3V_PCH
+3V_PCH
+3VS
8 99
8 99
8 99
0.1
0.1
0.1
5
www.laptoprepairsecrets.com
4
3
2
1
GPP_B18, Internal PD 20K
*L: Disable “ No Reboot” mode
H: Enable “ No Reboot” mode
GPP_B18 GPP_B22
D D
FN, F1, F4 PD 100K, BIOS need output
"High" while act i ve
C C
RC98 1K_0402_5%
RC97 20K_0402_5%
12
@
12
@
To VGA_CORE IC, RPC3.7
+3VS +3VS
RF_OFF#[66]
HP_JACK_IN[57]
TRACKP_ON#[63]
BT_ON[66]
@
TP939
@
TP940
F4_LED[65]
TPNL_EN[52]
VGA_ON[30,38,39,91]
GPP_B22, Internal PD 20K
*L: SPI
H: LPC
RF_OFF#
HP_JACK_IN
GPP_B18
TRACKP_ON#
BT_ON
GPP_B22
PLANARID0
PLANARID1
PLANARID2
PLANARID3
UART2_RX
1
UART2_TX
1
F4_LED
TPNL_EN
VGA_ON
DGPU_HOLD_RST#
12
@
RC99 20K_0402_5%
1 2
@
RC100 20K_0402_5%
UC1F
LPSS ISH
AN8
GPP_B15/GSPI0_CS#
AP7
GPP_B16/GSPI0_CLK
AP8
GPP_B17/GSPI0_MISO
AR7
GPP_B18/GSPI0_MOSI
AM5
GPP_B19/GSPI1_CS#
AN7
GPP_B20/GSPI1_CLK
AP5
GPP_B21/GSPI1_MISO
AN5
GPP_B22/GSPI1_MOSI
AB1
GPP_C8/UART0_RXD
AB2
GPP_C9/UART0_TXD
W4
GPP_C10/UART0_RTS#
AB3
GPP_C11/UART0_CTS#
AD1
GPP_C20/UART2_RXD
AD2
GPP_C21/UART2_TXD
AD3
GPP_C22/UART2_RTS#
AD4
GPP_C23/UART2_CTS#
U7
GPP_C16/I2C0_SDA
U6
GPP_C17/I2C0_SCL
U8
GPP_C18/I2C1_SDA
U9
GPP_C19/I2C1_SCL
AH9
GPP_F4/I2C2_SDA
AH10
GPP_F5/I2C2_SCL
AH11
GPP_F6/I2C3_SDA
AH12
GPP_F7/I2C3_SCL
AF11
GPP_F8/I2C4_SDA
AF12
GPP_F9/I2C4_SCL
SKYLAKE-U_BGA1356
SKL_U LT
6 OF 20REV = 1
GPP_D9
GPP_D10
GPP_D11
GPP_D12
GPP_D5/ISH_I2C0_SDA
GPP_D6/ISH_I2C0_SCL
GPP_D7/ISH_I2C1_SDA
GPP_D8/ISH_I2C1_SCL
GPP_F10/I2C5_SDA/ISH_I2C2_SDA
GPP_F11/I2C5_SCL/ISH_I2C2_SCL
GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA
GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL
GPP_D16/ISH_UART0_CTS#/SML0BALERT#
GPP_D15/ISH_UART0_RTS#
GPP_C12/UART1_RXD/ISH_UART1_RXD
GPP_C13/UART1_TXD/ISH_UART1_TXD
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
GPP_C15/UART1_CTS#/ISH_UART1_CTS#
GPP_A18/ISH_GP0
GPP_A19/ISH_GP1
GPP_A20/ISH_GP2
GPP_A21/ISH_GP3
GPP_A22/ISH_GP4
GPP_A23/ISH_GP5
GPP_A12/BM_BUSY#/ISH_GP6
P2
P3
P4
P1
M4
N3
N1
N2
AD11
AD12
U1
U2
U3
U4
AC1
AC2
AC3
AB4
AY8
BA8
BB7
BA7
AY7
AW7
AP13
PCH_WWAN_RST#
CP_RESET#
CP_BYPASS
TP4RST
WWAN_DET#
WWANRF_DISABLE#
GPP_D13
FN_LED
F1_LED
PCH_WWAN_RST# [66]
CP_RESET# [63]
CP_BYPASS [63]
TP4RST [63]
WWAN_DET# [66]
WWANRF_DISABLE# [66]
GPP_D13 [58]
FN_LED [65]
F1_LED [65]
Project/SKU ID
PLANARID3
(GPP_C11)
1
B B
1 2
PCH_PLT_RST#[14]
PLT_RST#[8,14,60,66,70,71,77]
+3V_PCH
+3VS
+3VS
A A
+3V_PCH
1 2
R288 4.7K_0402_5%@
1 2
RC120 10K_0402_5%
1 2
RC121 4.7K_0402_5%
1 2
RC122 10K_0402_5%
1 2
RC123 10K_0402_5%@
1 2
RC124 10K_0402_5%@
1 2
RC125 10K_0402_5%
5
1 2
RC119 10K_0402_5%
RF_OFF#
VGA_ON
BT_ON
CP_BYPASS
WWAN_DET#
WWANRF_DISABLE#
DGPU_HOLD_RST#
RC385 0_0402_5%@
RC386 0_0402_5%DIS@
4
1 2
DGPU_HOLD_RST#
1 2
RC60 0_0402_5%@
+3VS
5
2
P
B
4
Y
1
A
G
UC5
DIS@
TC7SZ08FU SC70-5
3
SA000067X00
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
3
PD 10K at GPU Pin
PLT_RST_VGA# [30,35,91]
2015/01/12
2015/01/12
2015/01/12
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
PLANARID0
PLANARID1
PLANARID2
PLANARID3
2016/01/12
2016/01/12
2016/01/12
1(RC65)
0
12
RC65
10K_0402_5%
12
RC69
@
10K_0402_5%
X
PLANARID2
(GPP_C10)
NVPRO SKU (RC70)
12
RC66
VPRO@
10K_0402_5%
12
RC70
NVPRO@
10K_0402_5%
Title
Title
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
PLANARID1
( GPP_C9)
DIS (RC67)VPRO SKU (RC66)
UMA (RC71)
DIS@
UMA@
SKL_GPIO
SKL_GPIO
SKL_GPIO
Friday, October 23, 2015
Friday, October 23, 2015
Friday, October 23, 2015
PLANARID0
( GPP_C8)
15" (RC68)
14" (RC72)
+3VS
12
RC67
10K_0402_5%
12
RC71
10K_0402_5%
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
1
12
RC68
@
10K_0402_5%
12
RC72
10K_0402_5%
9 99
9 99
9 99
0.1
0.1
0.1
5
www.laptoprepairsecrets.com
D D
4
3
2
1
Need to check again?
PCH_HDA_BCLK[56]
PCH_HDA_RST#[56]
PCH_HDA_SDOUT[56]
PCH_HDA_SYNC[56]
C C
GPP_B14, Internal PD 20K
No Reboot on TCO
Timer expiration
pull-up to VCC3_3 through a 1~8.2KΩ
resistor to disable this capability
PCH_HDA_BCLK
PCH_HDA_RST# HDA_RST#
PCH_HDA_SDOUT
PCH_HDA_SYNC HDA_SYNC
1
CV179
RF@
22P_0402_50V8-J
2
ME_FLASH[77]
PCH_BEEP
RPC2
1 8
2 7
3 6
4 5
33_0804_8P4R_5%
SD30000370T
1 2
RC21 0_0402_5%
1 2
@
RC376 8.2K_0402_5%
1 2
@
RC300 20K_0402_5%
HDA_BCLK
HDA_SDOUT
+3VS
UC1G
HDA_SYNC
HDA_BCLK
HDA_SDOUT
PCH_HDA_SDIN0[56]
PCH_BEEP[58]
PCH_HDA_SDIN0
HDA_RST#
PCH_BEEP
BA22
AY22
BB22
BA21
AY21
AW22
AY20
AW20
AK10
AW5
J5
AK7
AK6
AK9
H5
D7
D8
C8
AUDIO
HDA_SYNC/I2S0_SFRM
HDA_BLK/I2S0_SCLK
HDA_SDO/I2S0_TXD
HDA_SDI0/I2S0_RXD
HDA_SDI1/I2S1_RXD
HDA_RST#/I2S1_SCLK
GPP_D23/I2S_MCLK
I2S1_SFRM
I2S1_TXD
GPP_F1/I2S2_SFRM
GPP_F0/I2S2_SCLK
GPP_F2/I2S2_TXD
GPP_F3/I2S2_RXD
GPP_D19/DMIC_CLK0
GPP_D20/DMIC_DATA0
GPP_D17/DMIC_CLK1
GPP_D18/DMIC_DATA1
GPP_B14/SPKR
SKYLAKE-U_BGA1356
SKL_U LT
7 OF 20REV = 1
SDIO/SDXC
GPP_G0/SD_CMD
GPP_G1/SD_DATA0
GPP_G2/SD_DATA1
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3
GPP_G5/SD_CD#
GPP_G6/SD_CLK
GPP_A17/SD_PWR_EN#/ISH_GP7
GPP_G7/SD_WP
GPP_A16/SD_1P8_SEL
SD_RCOMP
GPP_F23
AB11
AB13
AB12
W12
W11
W10
W8
W7
BA9
BB9
AB7
AF13
1 2
R111 200_0402_1%
SC_DET#
SC_DET# [73]
B B
A A
Processor Strapping
543016_543016_SKL_PDG_UY_1_0_pub
P780
PCH_HDA_SDIN0
HDA_SDOUT
HDA_SYNC
5
1 2
@
RC297 1K_0402_5%
1 2
RC301 20K_0402_5%@
1 2
@
RC299 1K_0402_5%
1 2
RC302 20K_0402_5%@
1 2
RC356 1K_0402_5%
+VCC_IO
+VCC_HDA
+3V_PCH
4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
3
2015/01/12
2015/01/12
2015/01/12
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2016/01/12
2016/01/12
2016/01/12
Title
Title
Title
SKL_HDA/GPIO
SKL_HDA/GPIO
SKL_HDA/GPIO
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
Friday, October 23, 2015
Friday, October 23, 2015
Date: Sheet of
Date: Sheet of
Date: Sheet of
Friday, October 23, 2015
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
1
10 99
10 99
10 99
0.1
0.1
0.1
5
www.laptoprepairsecrets.com
4
3
2
1
D D
1
1
PCIE1_CRX_DTX_N
PCIE1_CRX_DTX_P
PCIE1_CTX_DRX_N
PCIE1_CTX_DRX_P
PCIE3_CRX_DTX_N
PCIE3_CRX_DTX_P
PCIE3_CTX_DRX_N
PCIE3_CTX_DRX_P
PCIE4_CRX_DTX_N
PCIE4_CRX_DTX_P
PCIE4_CTX_DRX_N
PCIE4_CTX_DRX_P
SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
SATA_PTX_DRX_N0
SATA_PTX_DRX_P0
SATA_PRX_DTX_N1
SATA_PRX_DTX_P1
SATA_PTX_DRX_N1
SATA_PTX_DRX_P1
PCIE_CRX_GTX_N0
PCIE_CRX_GTX_P0
PCIE9_PTX_DRX_N0
PCIE9_PTX_DRX_P0
PCIE_CRX_GTX_N1
PCIE_CRX_GTX_P1
PCIE10_PTX_DRX_N1
PCIE10_PTX_DRX_P1
PCIE_RCOMP
XDP_PRDY_N
XDP_PREQ_N
PCIE_CRX_GTX_N2
PCIE_CRX_GTX_P2
PCIE11_PTX_DRX_N2
PCIE11_PTX_DRX_P2
PCIE_CRX_GTX_N3
PCIE_CRX_GTX_P3
PCIE12_PTX_DRX_N3
PCIE12_PTX_DRX_P3
PCIE1_CRX_DTX_N[71]
Card Reader
WLAN
LAN
C C
PCIE1_CRX_DTX_P[71]
PCIE1_CTX_C_DRX_N[71]
PCIE1_CTX_C_DRX_P[71]
PCIE3_CRX_DTX_N[66]
PCIE3_CRX_DTX_P[66]
PCIE3_CTX_C_DRX_N[66]
PCIE3_CTX_C_DRX_P[66]
PCIE4_CRX_DTX_N[60]
PCIE4_CRX_DTX_P[60]
PCIE4_CTX_C_DRX_N[60]
PCIE4_CTX_C_DRX_P[60]
HDD
SSD(NGFF)
PCIE_CRX_GTX_N0[35]
PCIE_CRX_GTX_P0[35]
PCIE_CTX_C_GRX_N0[35]
PCIE_CTX_C_GRX_P0[35]
PCIE_CRX_GTX_N1[35]
PCIE_CRX_GTX_P1[35]
PCIE_CTX_C_GRX_N1[35]
+3VS
B B
1 2
RC41 10K_0402_5%
UMA@
DGPU_PWROK[38,91]
GPU
PCIE_CTX_C_GRX_P1[35]
DGPU_PWROK
PCIE_CRX_GTX_N2[35]
PCIE_CRX_GTX_P2[35]
PCIE_CTX_C_GRX_N2[35]
PCIE_CTX_C_GRX_P2[35]
PCIE_CRX_GTX_N3[35]
PCIE_CRX_GTX_P3[35]
PCIE_CTX_C_GRX_N3[35]
PCIE_CTX_C_GRX_P3[35]
CC18 0.1U_0402_10V7-KDIS@
CC21 0.1U_0402_10V7-KDIS@
CC19 0.1U_0402_10V7-KDIS@
CC20 0.1U_0402_10V7-KDIS@
CC22 0.1U_0402_10V7-KDIS@
CC23 0.1U_0402_10V7-KDIS@
CC24 0.1U_0402_10V7-KDIS@
CC25 0.1U_0402_10V7-KDIS@
1 2
CC8 0.1U_0402_10V7-K
1 2
CC9 0.1U_0402_10V7-K
CC26 0.1U_0402_10V7-K
CC27 0.1U_0402_10V7-K
CC28 0.1U_0402_10V7-K
CC29 0.1U_0402_10V7-K
1 2
1 2
1 2
1 2
SATA_PRX_DTX_N0[51]
SATA_PRX_DTX_P0[51]
SATA_PTX_DRX_N0[51]
SATA_PTX_DRX_P0[51]
SATA_PRX_DTX_N1[66]
SATA_PRX_DTX_P1[66]
SATA_PTX_DRX_N1[66]
SATA_PTX_DRX_P1[66]
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
R122 100_0402_1%
TP115@
TP116@
UC1H
PCIE/US B3/SATA
H13
PCIE1_RXN/USB3_5_RXN
G13
PCIE1_RXP/USB3_5_RXP
B17
PCIE1_TXN/USB3_5_TXN
A17
PCIE1_TXP/USB3_5_TXP
G11
PCIE2_RXN/USB3_6_RXN
F11
PCIE2_RXP/USB3_6_RXP
D16
PCIE2_TXN/USB3_6_TXN
C16
PCIE2_TXP/USB3_6_TXP
H16
PCIE3_RXN
G16
PCIE3_RXP
D17
PCIE3_TXN
C17
PCIE3_TXP
G15
PCIE4_RXN
F15
PCIE4_RXP
B19
PCIE4_TXN
A19
PCIE4_TXP
F16
PCIE5_RXN
E16
PCIE5_RXP
C19
PCIE5_TXN
D19
PCIE5_TXP
G18
PCIE6_RXN
F18
PCIE6_RXP
D20
PCIE6_TXN
C20
PCIE6_TXP
F20
PCIE7_RXN/SATA0_RXN
E20
PCIE7_RXP/SATA0_RXP
B21
PCIE7_TXN/SATA0_TXN
A21
PCIE7_TXP/SATA0_TXP
G21
PCIE8_RXN/SATA1A_RXN
F21
PCIE8_RXP/SATA1A_RXP
D21
PCIE8_TXN/SATA1A_TXN
C21
PCIE8_TXP/SATA1A_TXP
E22
PCIE9_RXN
E23
PCIE9_RXP
B23
PCIE9_TXN
A23
PCIE9_TXP
F25
PCIE10_RXN
E25
PCIE10_RXP
D23
PCIE10_TXN
C23
PCIE10_TXP
F5
PCIE_RCOMPN
E5
PCIE_RCOMPP
D56
PROC_PRDY#
D61
PROC_PREQ#
BB11
GPP_A7/PIRQA#
E28
PCIE11_RXN/SATA1B_RXN
E27
PCIE11_RXP/SATA1B_RXP
D24
PCIE11_TXN/SATA1B_TXN
C24
PCIE11_TXP/SATA1B_TXP
E30
PCIE12_RXN/SATA2_RXN
F30
PCIE12_RXP/SATA2_RXP
A25
PCIE12_TXN/SATA2_TXN
B25
PCIE12_TXP/SATA2_TXP
SKYLAKE-U_BGA1356
SKL_U LT
SSIC / USB3
USB2
GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2
8 OF 20REV = 1
USB3_1_RXN
USB3_1_RXP
USB3_1_TXN
USB3_1_TXP
USB3_2_RXN/SSIC_1_RXN
USB3_2_RXP/SSIC_1_RXP
USB3_2_TXN/SSIC_1_TXN
USB3_2_TXP/SSIC_1_TXP
USB3_3_RXN/SSIC_2_RXN
USB3_3_RXP/SSIC_2_RXP
USB3_3_TXN/SSIC_2_TXN
USB3_3_TXP/SSIC_2_TXP
USB3_4_RXN
USB3_4_RXP
USB3_4_TXN
USB3_4_TXP
USB2N_1
USB2P_1
USB2N_2
USB2P_2
USB2N_3
USB2P_3
USB2N_4
USB2P_4
USB2N_5
USB2P_5
USB2N_6
USB2P_6
USB2N_7
USB2P_7
USB2N_8
USB2P_8
USB2N_9
USB2P_9
USB2N_10
USB2P_10
USB2_COMP
USB2_ID
USB2_VBUSSENSE
GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#
GPP_E4/DEVSLP0
GPP_E5/DEVSLP1
GPP_E6/DEVSLP2
GPP_E8/SATALED#
HDD_DEVSLP0
SSD_DEVSLP1
USB3P1_RXN
H8
USB3P1_RXP
G8
USB3P1_TXN
C13
USB3P1_TXP
D13
USB3P2_RXN
J6
USB3P2_RXP
H6
USB3P2_TXN
B13
USB3P2_TXP
A13
USB3P3_RXN_DOCK
J10
USB3P3_RXP_DOCK
H10
USB3P3_TXN_DOCK
B15
USB3P3_TXP_DOCK
A15
USB3P4_RXN
E10
USB3P4_RXP
F10
USB3P4_TXN
C15
USB3P4_TXP
D15
USB20_N0
AB9
USB20_P0
AB10
USB20_N1
AD6
USB20_P1
AD7
USB20_N2
AH3
USB20_P2
AJ3
USB20_N3
AD9
USB20_P3
AD10
USB20_N4
AJ1
USB20_P4
AJ2
USB20_N5
AF6
USB20_P5
AF7
USB20_N6
AH1
USB20_P6
AH2
USB20_N7
AF8
USB20_P7
AF9
USB20_N8
AG1
USB20_P8
AG2
USB20_N9
AH7
USB20_P9
AH8
AB6
USBCOMP
AG3
AG4
USB_OC0#
A9
USB_OC1#
C9
USB_OC2#
D9
USB_OC3#
B9
HDD_DEVSLP0
J1
SSD_DEVSLP1
J2
J3
H2
H3
G4
H1
RC377 10K_0402_5%@
RC378 10K_0402_5%@
USB3P1_RXN [54]
USB3P1_RXP [54]
USB3P1_TXN [54]
USB3P1_TXP [54]
USB3P2_RXN [54]
USB3P2_RXP [54]
USB3P2_TXN [54]
USB3P2_TXP [54]
USB3P3_RXN_DOCK [45]
USB3P3_RXP_DOCK [45]
USB3P3_TXN_DOCK [45]
USB3P3_TXP_DOCK [45]
USB3P4_RXN [53]
USB3P4_RXP [53]
USB3P4_TXN [53]
USB3P4_TXP [53]
USB20_N0 [54]
USB20_P0 [54]
USB20_N1 [54]
USB20_P1 [54]
USB20_N2 [45]
USB20_P2 [45]
USB20_N3 [53]
USB20_P3 [53]
USB20_N4 [73]
USB20_P4 [73]
USB20_N5 [73]
USB20_P5 [73]
USB20_N6 [66]
USB20_P6 [66]
USB20_N7 [52]
USB20_P7 [52]
USB20_N8 [66]
USB20_P8 [66]
USB20_N9 [52]
USB20_P9 [52]
1 2
R121 113_0402_1%
1 2
RC403 1K_0402_5%@
1 2
RC404 1K_0402_5%@
USB_OC0# [54]
USB_OC1# [53]
HDD_DEVSLP0 [51]
SSD_DEVSLP1 [66]
+3VS
12
12
On Board (Right-Front)
On Board (Right-Back)
DOCKING
S/B (AOU Port)
On Board (Right-Front)
On Board (Right-Back)
DOCKING
S/B (AOU Port)
SMART CARD
Finger Printer
BT
CAMERA
WWAN
Touch Panel
On Board (Right-Front)
S/B (AOU Port)
12
12
R286
15K_0402_5%@
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
R287
15K_0402_5%@
RPC23
1 8
2 7
3 6
4 5
10K_0804_8P4R_5%
+3V_PCH
USB_OC0#
USB_OC1#
2016/01/12
2016/01/12
2016/01/12
USB_OC2#
USB_OC3#
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
3
2015/01/12
2015/01/12
2015/01/12
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Port 1, 2
Port 4
Unused. Unused.
Unused.
Date: Sheet of
Date: Sheet of
Date: Sheet of
USB3.0 Port NO.
Pin.
USB2.0 Port NO.
Port 0, 1
Port 3
Default Port Mapping
Port 0, 1
Port 2, 3
Port 4, 5
Unused.
Title
Title
Title
SKL_PCIE/ SATA/ USB
SKL_PCIE/ SATA/ USB
SKL_PCIE/ SATA/ USB
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
Friday, October 23, 2015
Friday, October 23, 2015
Friday, October 23, 2015
Port 6, 7
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
1
11 99
11 99
11 99
0.1
0.1
0.1
5
www.laptoprepairsecrets.com
D D
4
3
2
1
UC1I
CSI-2
A36
CSI2_DN0
B36
CSI2_DP0
C38
CSI2_DN1
D38
CSI2_DP1
C36
CSI2_DN2
D36
CSI2_DP2
A38
CSI2_DN3
B38
CSI2_DP3
C31
CSI2_DN4
D31
CSI2_DP4
C33
CSI2_DN5
C C
D33
A31
B31
A33
B33
A29
B29
C28
D28
A27
B27
C27
D27
CSI2_DP5
CSI2_DN6
CSI2_DP6
CSI2_DN7
CSI2_DP7
CSI2_DN8
CSI2_DP8
CSI2_DN9
CSI2_DP9
CSI2_DN10
CSI2_DP10
CSI2_DN11
CSI2_DP11
SKYLAKE-U_BGA1356
B B
SKL_ULT
CSI2_CLKN0
CSI2_CLKP0
CSI2_CLKN1
CSI2_CLKP1
CSI2_CLKN2
CSI2_CLKP2
CSI2_CLKN3
CSI2_CLKP3
CSI2_COMP
GPP_D4/FLASHTRIG
EMMC
GPP_F13/EMMC_DATA0
GPP_F14/EMMC_DATA1
GPP_F15/EMMC_DATA2
GPP_F16/EMMC_DATA3
GPP_F17/EMMC_DATA4
GPP_F18/EMMC_DATA5
GPP_F19/EMMC_DATA6
GPP_F20/EMMC_DATA7
GPP_F21/EMMC_RCLK
GPP_F22/EMMC_CLK
GPP_F12/EMMC_CMD
EMMC_RCOMP
9 OF 20REV = 1
C37
D37
C32
D32
C29
D29
B26
A26
E13
B7
AP2
AP1
AP3
AN3
AN1
AN2
AM4
AM1
AM2
AM3
AP4
AT1
R33
1 2
200_0402_1%
A A
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
4
2015/01/12
2015/01/12
2015/01/12
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2016/01/12
2016/01/12
2016/01/12
3
Title
SKL_CS12/ EMMC
SKL_CS12/ EMMC
SKL_CS12/ EMMC
Size
Size
Size
Document Number Rev
Document Number Rev
Document Number Rev
A4
A4
A4
Friday, October 23, 2015
Friday, October 23, 2015
Date: Sheet
Date: Sheet of
Date: Sheet of
2
Friday, October 23, 2015
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
12 99
12 99
12 99
1
0.1
0.1
0.1
of
5
MCP for temp inf l uence
www.laptoprepairsecrets.com
D D
RTC External Circuit
+RTCBATT
RC14 0_0402_5%
+RTCBATT, +RTCVCC
Trace width = 20mils
1 2
+RTCVCC
1
2
CC4
0.1U_0402_10V6-K
JCMOS, JME Set t i ng, Need Under DDR Door
near CC59 for layout
+RTCVCC
4
RC15
1 2
20K_0402_5%
RC17
1 2
20K_0402_5%
PCH_RTCRST#
PCH_SRTCRST#
1 2
1 2
CC3 1U_0402_10V6-K
1 2
1 2
CC7 1U_0402_10V6-K
JCMOS1 @
JME1@
3
RTC Crystal
1
2
RC16
1 2
10M_0402_5%
YC1
1 2
32.768KHZ_9PF_9H03280012
CC5
8P_0402_50V8-C
PCH_RTCX1
PCH_RTCX2
1. Space > 15mils
2. No trace under crystal
3. Place on oppsosit side of
1
CC6
8P_0402_50V8-C
2
2
PCH_XTAL24_IN
PCH_XTAL24_OUT
1
CC10
10P_0402_50V8-J
2
1
RC24
1 2
1M_0402_5%
YC2
1
1
GND1
GND2
2
24MHZ_10PF_8Y24000011
3
3
1
4
CC11
10P_0402_50V8-J
2
+3VS
1 2
C C
B B
RC22 10K_0402_5%DIS@
1 2
RC23 10K_0402_5%UMA@
WLAN
LAN
VGA
CR
+3VS
CLK_PCIE_WLAN#[66]
CLK_PCIE_WLAN[66]
CLKREQ_PCIE2_WLAN#[66]
CLK_PCIE_LAN#[60]
CLK_PCIE_LAN[60]
CLKREQ_PCIE3_LAN#[60]
CLK_PCIE_VGA#[35]
CLK_PCIE_VGA[35]
CLKREQ_PCIE4_VGA#[30]
CLK_PCIE_CR#[71]
CLK_PCIE_CR[71]
CLKREQ_PCIE5_CR#[71]
UMA@
1 2
RC45 10K_0402_5%
DIS@
1 2
RC39 10K_0402_5%
DISCRETE_PRESENCE
CLK_PCIE_WLAN#
CLK_PCIE_WLAN
CLKREQ_PCIE2_WLAN#
CLK_PCIE_LAN#
CLK_PCIE_LAN
CLKREQ_PCIE3_LAN#
CLK_PCIE_VGA#
CLK_PCIE_VGA
CLKREQ_PCIE4_VGA#
CLK_PCIE_CR#
CLK_PCIE_CR
CLKREQ_PCIE5_CR#
CLKREQ_PCIE4_VGA#
UC1J
D42
CLKOUT_PCIE_N0
C42
CLKOUT_PCIE_P0
AR10
GPP_B5/SRCCLKREQ0#
B42
CLKOUT_PCIE_N1
A42
CLKOUT_PCIE_P1
AT7
GPP_B6/SRCCLKREQ1#
D41
CLKOUT_PCIE_N2
C41
CLKOUT_PCIE_P2
AT8
GPP_B7/SRCCLKREQ2#
D40
CLKOUT_PCIE_N3
C40
CLKOUT_PCIE_P3
AT10
GPP_B8/SRCCLKREQ3#
B40
CLKOUT_PCIE_N4
A40
CLKOUT_PCIE_P4
AU8
GPP_B9/SRCCLKREQ4#
E40
CLKOUT_PCIE_N5
E38
CLKOUT_PCIE_P5
AU7
GPP_B10/SRCCLKREQ5#
SKYLAKE-U_BGA1356
+3VS
SKL_U LT
CLOCK SIGNALS
RPC24
1 8
2 7
3 6
4 5
10K_0804_8P4R_5%
10 OF 20REV = 1
CLKREQ_PCIE2_WLAN#
CLKREQ_PCIE3_LAN#
CLKREQ_PCIE5_CR#
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
GPD8/SUSCLK
XTAL24_IN
XTAL24_OUT
XCLK_BIASREF
RTCX1
RTCX2
SRTCRST#
RTCRST#
F43
E43
BA17
E37
E35
E42
AM18
AM20
AN18
AM16
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
SUSCLK_32K
PCH_XTAL24_IN
PCH_XTAL24_OUT
XCLK_BIASREF
PCH_RTCX1
PCH_RTCX2
PCH_SRTCRST#
PCH_RTCRST#
1
T56
1
T57
1 2
R92 2.7K_0402_1%
SUSCLK_32K [66]
+1VALW
to WLAN
A A
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
3
2015/01/12
2015/01/12
2015/01/12
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2016/01/12
2016/01/12
2016/01/12
Title
SKL_RTC/ CLK
SKL_RTC/ CLK
SKL_RTC/ CLK
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
Friday, October 23, 2015
Friday, October 23, 2015
Date: Sheet of
Date: Sheet of
Date: Sheet of
Friday, October 23, 2015
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
1
13 99
13 99
13 99
0.1
0.1
0.1
5
www.laptoprepairsecrets.com
D D
4
3
2
1
UC1K
PCH_PLT_RST#[9]
VCCST_PWRGD
1 2
PCH_PWROK[77]
C C
B B
VGATE[77,93]
GPU_WAKE#[30]
PCH_LAN_WAKE#[60]
For vPRO LAN WAKE#
+3VALW
+3VALW
RC40 0_0402_5%
1 2
RC383 0_0402_5%@
1 2
RC64 0_0402_5%@
1 2
RC76 0_0402_5%
RPC9
1 8
2 7
3 6
4 5
10K_0804_8P4R_5%
SD300002P0T
RC74 10K_0402_5%
RC379 10K_0402_5%@
RC380 10K_0402_5%@
RC387 10K_0402_5%@
1 2
1 2
1 2
1 2
AC_PRESENT
BATLOW#
PCIE_WAKE#
For vPRO LAN WAKE#
EC_WAKE#_DSW
PM_SLP_S5#
PCH_SLP_WLAN#
PCH_SLP_LAN#
EC_RSMRST#
+3VS
RC47 10K_0402_5%@
+3VALW_PRIM
RC398 10K_0402_5%
RC53 10K_0402_5%
RC5 10K_0402_5%
EC_RSMRST#[77]
1 2
R281 60.4_0402_1%
PCH_SYSPWROK[77]
1 2
RC382 0_0402_5%
1 2
RC55 0_0402_5%
PCIE_WAKE#[66]
LANPHYPC[60]
1 2
1 2
1 2
1 2
@
PCH_PLT_RST#
SYS_RESET#
EC_RSMRST#
H_CPUPWRGD
PCH_SYSPWROK
PWROK
DSW_PWROK
SUSWARN#
SUSACK#
PCIE_WAKE#
EC_WAKE#_DSW
LANPHYPC
SYS_RESET#
EC_RSMRST#
H_CPUPWRGDH_CPUPWRGD
AN10
GPP_B13/PLTRST#
B5
SYS_RESET#
AY17
RSMRST#
A68
PROCPWRGD
B65
VCCST_PWRGD
B6
SYS_PWROK
BA20
PCH_PWROK
BB20
DSW_PWROK
AR13
GPP_A13/SUSWARN#/SUSPWRDNACK
AP11
GPP_A15/SUSACK#
BB15
WAKE#
AM15
GPD2/LAN_WAKE#
AW17
GPD11/LANPHYPC
AT15
GPD7/RSVD
SKYLAKE-U_BGA1356
SKL_U LT
SYSTEM POWER MANAGEMENT
11 OF 20REV = 1
PCH_PLT_RST#
100K_0402_5%
12
RC50
GPP_B12/SLP_S0#
GPD4/SLP_S3#
GPD5/SLP_S4#
GPD10/SLP_S5#
SLP_SUS#
SLP_LAN#
GPD9/SLP_WLAN#
GPD6/SLP_A#
GPD3/PWRBTN#
GPD1/ACPRESENT
GPD0/BATLOW#
GPP_A11/PME#
GPP_B11/EXT_PWR_GATE#
INTRUDER#
GPP_B2/VRALERT#
1 2
RC42 0_0402_5%
UC4
1
NC
2
IN_A
3
GND
TC7SG17FE_SON5
PM_SLP_S0#
AT11
PM_SLP_S3#
AP15
PM_SLP_S4#
BA16
PM_SLP_S5#
AY16
PCH_SLP_SUS#
AN15
PCH_SLP_LAN#
AW15
PCH_SLP_WLAN#
BB17
PM_SLP_A#
AN16
PBTN_OUT#
BA15
AC_PRESENT
AY15
AU13
BATLOW#
AU11
PCH_INTRUDER#
AP16
EXT_PWR_GATE#
AM10
AM11
VRALERT#
1. must be always pulled-up to VCCRTC.
2. 1 = Enable DSW 3.3V-to-1.05V Integrated DeepSx Well ( DSW) On-Die Voltage Regulator.
This must always be pulled high on product i on boards.
@
VCC
OUT_Y
1
T50
PM_SLP_S3# [77]
PM_SLP_S4# [77]
PM_SLP_S5# [77]
PCH_SLP_SUS# [77]
PCH_SLP_LAN# [77]
PCH_SLP_WLAN# [77]
PM_SLP_A# [77]
PBTN_OUT# [77]
AC_PRESENT [77]
1 2
RC18 1M_0402_5%
EXT_PWR_GATE# [18]
1
T55
+3VALW
5
4
PLT_RST#
PM_SLP_S3#
PM_SLP_S4#
PM_SLP_S5#
+RTCVCC
PLT_RST# [8,9,60,66,70,71,77]
1
1
1
T51
T52
T53
Reserved for HW control
+VCC_ST
+3VALW
12
RC394
@
100K_0402_5%
1 2
VCCST_PG_EC[77]
A A
SUSP#
RC395 0_0402_5%
1 2
RC396 0_0402_5%@
5
12
RC391
100K_0402_5%
61
D
2
G
Q13A
2N7002KDWH_SOT363-6
SB000013A00
S
12
RC390
1K_0402_5%
VCCST_PWRGD
34
D
5
G
4
Q13B
2N7002KDWH_SOT363-6
SB000013A00
S
RTC clock debounce
PCH_INTRUDER#
@
S3
SPVR310100_4P
2
1
2015/01/12
2015/01/12
2015/01/12
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2016/01/12
2016/01/12
2016/01/12
3
4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
3
Title
Title
Title
SKL_SYS / PM
SKL_SYS / PM
SKL_SYS / PM
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
Friday, October 23, 2015
Friday, October 23, 2015
Date: Sheet of
Date: Sheet of
Date: Sheet of
Friday, October 23, 2015
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
1
14 99
14 99
14 99
0.1
0.1
0.1
5
www.laptoprepairsecrets.com
D D
4
3
2
1
+VCC_ST +VCC_ST
Rpu1
12
RC373
@
100_0402_1%
VR_SVID_CLK VR_SVID_DAT
C C
B B
+VCC_CORE +VCC_CORE
A30
A34
A39
A44
AK33
AK35
AK37
AK38
AK40
AL33
AL37
AL40
AM32
AM33
AM35
AM37
AM38
G30
K32
AK32
AB62
P62
V62
1
@
TP942
@
TP941
H63
1
G61
AC63
AE63
AE62
AG62
AL63
AJ62
SKYLAKE-U_BGA1356
SKL_U LT
UC1L
CPU POWER 1 OF 4
VCC_A30
VCC_A34
VCC_A39
VCC_A44
VCC_AK33
VCC_AK35
VCC_AK37
VCC_AK38
VCC_AK40
VCC_AL33
VCC_AL37
VCC_AL40
VCC_AM32
VCC_AM33
VCC_AM35
VCC_AM37
VCC_AM38
VCC_G30
RSVD_K32
RSVD_AK32
VCCOPC_AB62
VCCOPC_P62
VCCOPC_V62
VCC_OPC_1P8_H63
VCC_OPC_1P8_G61
VCCOPC_SENSE
VSSOPC_SENSE
VCCEOPIO_AE62
VCCEOPIO_AG62
VCCEOPIO_SENSE
VSSEOPIO_SENSE
VCC_G32
VCC_G33
VCC_G35
VCC_G37
VCC_G38
VCC_G40
VCC_G42
VCC_J30
VCC_J33
VCC_J37
VCC_J40
VCC_K33
VCC_K35
VCC_K37
VCC_K38
VCC_K40
VCC_K42
VCC_K43
VCC_SENSE
VSS_SENSE
VIDALERT#
VIDSCK
VIDSOUT
VCCSTG_G20
12 OF 20REV = 1
G32
G33
G35
G37
G38
G40
G42
J30
J33
J37
J40
K33
K35
K37
K38
K40
K42
K43
E32
E33
B63
A63
D64
G20
VR_SVID_ALRT#_R
VR_SVID_CLK
VR_SVID_DAT
1 2
RC126 0_0402_5%
1 2
RC142 0_0402_5%
+VCC_STG
[SKL PDDG]Package Sensing Recommendations
1.Trace Length Match: <25mil
2.Space: >25mil
3.Trace impedance:50ohm
4.Sense traces should be referenced to a solid ground plane
5.Avoid crossing over plane splits
[SKL PDG]VIDSCK
Rpu2
12
RC372
100_0402_1%
VR_SVID_CLK [93] VR_SVID_DAT [93]
+VCC_ST
Rpu1
12
RC20
VR_SVID_ALRT#_R VR_SVID_ALRT#
+VCC_CORE
Rs1
1 2
RC19 220_0402_1%
12
RC128
100_0402_1%
12
RC143
100_0402_1%
56_0402_1%
VCC_SENSE [93]
VSS_SENSE [93]
[SKL PDG]VIDSOUT
[SKL PDG]VIDALERT#
VR_SVID_ALRT# [93]
[SKL PDG]SVID
1.Alert signal must be routed between Clk and Data signals to
minimize Cross-Talk.
A A
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
3
2015/01/12
2015/01/12
2015/01/12
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2016/01/12
2016/01/12
2016/01/12
Title
SKL_POWER_VCCCORE
SKL_POWER_VCCCORE
SKL_POWER_VCCCORE
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
Friday, October 23, 2015
Friday, October 23, 2015
Date: Sheet of
Date: Sheet of
Date: Sheet of
Friday, October 23, 2015
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
1
15 99
15 99
15 99
0.1
0.1
0.1
5
www.laptoprepairsecrets.com
D D
4
3
2
1
N70
N71
R63
R64
R65
R66
R67
R68
R69
R70
R71
T62
U65
U68
U71
W63
W64
W65
W66
W67
W68
W69
W70
W71
Y62
AK42
AK43
AK45
AK46
AK48
AK50
AK52
AK53
AK55
AK56
AK58
AK60
AK70
AL43
AL46
AL50
AL53
AL56
AL60
AM48
AM50
AM52
AM53
AM56
AM58
AU58
AU63
BB57
BB66
AK62
AL61
+VCC_GT
+VCC_GT
A48
A53
A58
A62
A66
AA63
AA64
AA66
AA67
AA69
AA70
AA71
AC64
AC65
AC66
AC67
C C
+VCC_GT
B B
VCCGT_SENSE[93]
VSSGT_SENSE[93]
12
RC130
100_0402_1%
1 2
RC129 0_0402_5%
1 2
RC183 0_0402_5%
12
RC184
100_0402_1%
AC68
AC69
AC70
AC71
M62
N63
N64
N66
N67
N69
J43
J45
J46
J48
J50
J52
J53
J55
J56
J58
J60
K48
K50
K52
K53
K55
K56
K58
K60
L62
L63
L64
L65
L66
L67
L68
L69
L70
L71
J70
J69
SKL_U LT
UC1M
CPU POWER 2 OF 4
VCCGT_A48
VCCGT_A53
VCCGT_A58
VCCGT_A62
VCCGT_A66
VCCGT_AA63
VCCGT_AA64
VCCGT_AA66
VCCGT_AA67
VCCGT_AA69
VCCGT_AA70
VCCGT_AA71
VCCGT_AC64
VCCGT_AC65
VCCGT_AC66
VCCGT_AC67
VCCGT_AC68
VCCGT_AC69
VCCGT_AC70
VCCGT_AC71
VCCGT_J43
VCCGT_J45
VCCGT_J46
VCCGT_J48
VCCGT_J50
VCCGT_J52
VCCGT_J53
VCCGT_J55
VCCGT_J56
VCCGT_J58
VCCGT_J60
VCCGT_K48
VCCGT_K50
VCCGT_K52
VCCGT_K53
VCCGT_K55
VCCGT_K56
VCCGT_K58
VCCGT_K60
VCCGT_L62
VCCGT_L63
VCCGT_L64
VCCGT_L65
VCCGT_L66
VCCGT_L67
VCCGT_L68
VCCGT_L69
VCCGT_L70
VCCGT_L71
VCCGT_M62
VCCGT_N63
VCCGT_N64
VCCGT_N66
VCCGT_N67
VCCGT_N69
VCCGT_SENSE
VSSGT_SENSE
SKYLAKE-U_BGA1356
VCCGT_N70
VCCGT_N71
VCCGT_R63
VCCGT_R64
VCCGT_R65
VCCGT_R66
VCCGT_R67
VCCGT_R68
VCCGT_R69
VCCGT_R70
VCCGT_R71
VCCGT_T62
VCCGT_U65
VCCGT_U68
VCCGT_U71
VCCGT_W63
VCCGT_W64
VCCGT_W65
VCCGT_W66
VCCGT_W67
VCCGT_W68
VCCGT_W69
VCCGT_W70
VCCGT_W71
VCCGT_Y62
VCCGTX_AK42
VCCGTX_AK43
VCCGTX_AK45
VCCGTX_AK46
VCCGTX_AK48
VCCGTX_AK50
VCCGTX_AK52
VCCGTX_AK53
VCCGTX_AK55
VCCGTX_AK56
VCCGTX_AK58
VCCGTX_AK60
VCCGTX_AK70
VCCGTX_AL43
VCCGTX_AL46
VCCGTX_AL50
VCCGTX_AL53
VCCGTX_AL56
VCCGTX_AL60
VCCGTX_AM48
VCCGTX_AM50
VCCGTX_AM52
VCCGTX_AM53
VCCGTX_AM56
VCCGTX_AM58
VCCGTX_AU58
VCCGTX_AU63
VCCGTX_BB57
VCCGTX_BB66
VCCGTX_SENSE
VSSGTX_SENSE
13 OF 20REV = 1
A A
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
3
2015/01/12
2015/01/12
2015/01/12
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2016/01/12
2016/01/12
2016/01/12
Title
SKL_POWER_VCCGT
SKL_POWER_VCCGT
SKL_POWER_VCCGT
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
Friday, October 23, 2015
Friday, October 23, 2015
Date: Sheet of
Date: Sheet of
Date: Sheet of
Friday, October 23, 2015
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
1
16 99
16 99
16 99
0.1
0.1
0.1
5
www.laptoprepairsecrets.com
4
3
2
1
D D
[SKL PDG]VDDQ
[SKL PDG]10uF x6, 1uF x4
+1.35V
SKL_U LT
10U_0402_6.3V6-M
10U_0402_6.3V6-M
C209
C210
1
2
C C
B B
+VCC_SFR
[SKL PDG]VCCSTG
[SKL PDG]1uF x1
CC94
[SKL PDG]VDDQC
[SKL PDG]1uF x1
+VCC_SFROC
+VCC_STG +VCC_ST +VCC_SFR
1U_0402_10V6K
CC84
1
2
+1.35V
10U_0402_6.3V6-M
1U_0201_6.3V6-M
C344
1
1
2
2
+VCC_STG
[SKL PDG]VCCST
[SKL PDG]1uF x1
RC293
1 2
0_0603_5%
Primary side cap
[SKL PDG]VCCPLL
[SKL PDG]1uF x1
1U_0201_6.3V6-M
C340
C341
1
1
2
2
+VCC_ST
1U_0402_10V6K
CC83
1
2
+VCC_SFROC+1.35V
1U_0201_6.3V6-M
C348
1
2
1U_0201_6.3V6-M
C342
1
2
+1.35V
+VCC_ST
Primary side capPrimary side cap
[SKL PDG]VCCPLL
[SKL PDG]1uF x1
1U_0201_6.3V6-M
C343
1
2
RC197
1 2
0_0603_5%
1U_0201_6.3V6-M
1
2
1U_0402_10V6K
CC86
1
2
UC1N
AU23
VDDQ_AU23
AU28
VDDQ_AU28
AU35
VDDQ_AU35
AU42
VDDQ_AU42
BB23
VDDQ_BB23
BB32
VDDQ_BB32
BB41
VDDQ_BB41
BB47
VDDQ_BB47
BB51
VDDQ_BB51
AM40
VDDQC
A18
VCCST
A22
VCCSTG_A22
AL23
VCCPLL_OC
K20
VCCPLL_K20
K21
VCCPLL_K21
SKYLAKE-U_BGA1356
CPU POWER 3 OF 4
VCCIO_AK28
VCCIO_AK30
VCCIO_AL30
VCCIO_AL42
VCCIO_AM28
VCCIO_AM30
VCCIO_AM42
VCCSA_AK23
VCCSA_AK25
VCCSA_G23
VCCSA_G25
VCCSA_G27
VCCSA_G28
VCCSA_J22
VCCSA_J23
VCCSA_J27
VCCSA_K23
VCCSA_K25
VCCSA_K27
VCCSA_K28
VCCSA_K30
VCCIO_SENSE
VSSIO_SENSE
VSSSA_SENSE
VCCSA_SENSE
14 OF 20REV = 1
AK28
AK30
AL30
AL42
AM28
AM30
AM42
AK23
AK25
G23
G25
G27
G28
J22
J23
J27
K23
K25
K27
K28
K30
AM23
AM22
H21
H20
+VCC_IO
VCCIO_SENSE
VSSIO_SENSE
+VCC_SA
[SKL PDG]VCCIO
[SKL PDG]10uF x2, 1uF x4
10U_0402_6.3V6-M
10U_0402_6.3V6-M
C212
C211
1
2
+VCC_SA
RC192 100_0402_1%
RC189 100_0402_1%
RC127 0_0402_5%
RC185 0_0402_5%
12
RC370
100_0402_1%
VCCSA_SENSE
VSSSA_SENSE
12
RC369
100_0402_1%
1U_0201_6.3V6-M
C337
C336
1
1
2
2
[SKL PDG]VCCSA
[SKL PDG]10uF x7, 1uF x7
10U_0402_6.3V6-M
C214
C213
1
2
10U_0402_6.3V6-M
C223
C224
1
2
1 2
1 2
1 2
1 2
1U_0201_6.3V6-M
C338
1
2
10U_0402_6.3V6-M
C215
1
2
10U_0402_6.3V6-M
C225
1
2
1U_0201_6.3V6-M
C339
1
2
10U_0402_6.3V6-M
C216
1
2
10U_0402_6.3V6-M
C329
1
2
VSSSA_SENSE
VCCSA_SENSE
1U_0201_6.3V6-M
1
2
10U_0402_6.3V6-M
1
2
1U_0201_6.3V6-M
C330
1
2
+VCC_IO
Power Rail
1U_0201_6.3V6-M
C331
1
2
VCC
1U_0201_6.3V6-M
1U_0201_6.3V6-M
C332
1
2
1U_0201_6.3V6-M
C333
C334
1
1
2
2
VSSSA_SENSE [93]
VCCSA_SENSE [93]
Processor IA Cores Power Rail
1U_0201_6.3V6-M
1U_0201_6.3V6-M
C335
1
1
2
2
Description
Control
SVID
VccGT SVIDProcessor Graphics Power Rails
VccGTX Processor Graphics Extended Power Rail
Available only for GT3/GT4 processor SKUs
SVID
SVIDSystem Agent Power RailVccSA
FixedIO Power RailVccIO
VccST Sustain Power Rail Fixed
VccPLL Processor PLLs power rail Fixed
VDDQ Integrated Memory Controller Power Rail Fixed
VccOPC Fixed
VccOPC_1P8 Processor OPC power rail (available only
A A
VccEOPIO Processor OPC power rail (available only
Processor OPC power rail (available only
in SKU’ s with OPC)
in SKU’ s with OPC)
in SKU’ s with OPC)
Fixed
Fixed
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
3
2015/01/12
2015/01/12
2015/01/12
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2016/01/12
2016/01/12
2016/01/12
Title
Title
Title
SKL_POWER_VCCIO/SA
SKL_POWER_VCCIO/SA
SKL_POWER_VCCIO/SA
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
Friday, October 23, 2015
Friday, October 23, 2015
Date: Sheet of
Date: Sheet of
Date: Sheet of
Friday, October 23, 2015
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
1
17 99
17 99
17 99
0.1
0.1
0.1
5
www.laptoprepairsecrets.com
4
3
2
1
1
CC99
2
+3VALW _PRIM
+1.8VALW _PCH
+3VALW _RTCPR IM
+RTCVCC
1
T58
1
T59
Near AG15 Near T16Near Y16
1U_0402_10V6K
1U_0402_10V6K
1
CC530
2
+1.8VALW _PCH
VCC1R0 _SUS
0603 Footprint
1 2
LC30_0 603_5%
0603 Footprint
1 2
LC40_0 603_5%
0603 Footprint
1 2
LC50_0 603_5%
Thermal Sensor Primary Well 1.8 V
[SKL PDG]VccATS
[SKL PDG]1uF x1
[SKL PDG]Close AA1,
Placement type:Edge<10mm(394mil)
1
2
D D
SRAM Primary Well 1.0 V. Dedicated SRAM rail and can
have on board power down gate control.
+VCC_MPHYG T
1 2
RC139 0_ 0805_5%
[SKL PDG]VccSRAM
[SKL PDG]1uF x1
[SKL PDG]Close AF20,
Placement type:Edge<10mm(394mil)
C C
B B
EXT_PW R_GATE #[14]
+VCC_MPHYG T
+VCC_SR AM +VCC_PL LEBB
1U_0402_10V6K
1
@
CC47
2
+3VALW
RC346
20K_04 02_5%
1 2
1 2
0_0805 _5%
1 2
RC321 0_0402_5 %
[SKL PDG]VccAPLLEBB
[SKL PDG]1uF x1
[SKL PDG]Close N18,
Placement type:Edge<3mm(118mil)
Reserve for Sense Resistor
1 2
RC173 0_0603_ 5%
1 2
RC341 0_ 0805_5%
1 2
RC176 0_ 0805_5%
@
+1VALW
+VCC_MPHYG T+1VALW
RC343
+VCC_AMP HYPLL
1U_0402_10V6K
+1.8VALW _PCH+1.8VA LW
+3VALW _PCH+3VALW
+1VALW _PCH+1VALW
+3VALW
VccMPHYGT(Mod PHY Externally Gated Primary 1.0 V: Externally gated
primary supply for PCIe/DMI/USB3/SATA/MIPI MPHY logic.)
1U_0402_10V6K
1
@
CC46
2
U5
2
3
SLG59M1 470VTR_ FC-TDFN9_ 1P5X2
+VCC_MPHYG T
1
[SKL PDG]VccMPHYGT
CC52
[SKL PDG]1uF x1
[SKL PDG]Close N15,
Placement type:Edge<3mm(118mil)
2
[SKL PDG]47uF x1
[SKL PDG]Close N15,
Placement type:Edge<10mm(394mil)
Mod PHY Always On Primary 1.0 V: Always on primary
supply for PCIe/DMI/USB3/SATA/MIPI MPHY logic
[SKL PDG]VccMPHYAON
[SKL PDG]1uF x1
[SKL PDG]Close K17,
Placement type:Edge<3mm(118mil)
Primary Well 1.0 V: For I/O blocks, ungated ISH SRAM
power, USB AFE Digital Logic, JTAG, Thermal Sensor and
MIPI DPHY.
+1VALW _PCH
RC318 0_0402_5 %@
[SKL PDG]VCCPRIM
[SKL PDG]1uF x1
[SKL PDG]Close AB19,
Placement type:Edge<10mm(394mil)
4
@
VDD1S1
5
ON7S2
D1
6
GND
D2
1 2
RC137 0.0 1_1206_ 1%
1 2
+VCC_MPHYG T
+1VALW _1P0
close to N15
47U_0805_6.3V6-M
1U_0402_10V6K
@
1
12
C194
CC50
2
+1VALW _PCH
1U_0402_10V6K
1
CC49
2
VCC1R0 _SUS
1U_0402_10V6K
1
CC95
2
Core Logic Primary Well: This rail scales from 0.85 V
to 1.0 V.
+1VALW _PCH
RC304 0_ 0805_5%@
[SKL PDG]VccPRIM_Core
[SKL PDG]1uF x1
[SKL PDG]Close AF18,
Placement type:Edge<10mm(394mil)
+1VALW _PCH
+1VALW _1P0
+VCC_MPHYG T
+1VALW _PCH
VCC1R0 _SUS
0.1U_0402_10V6-K
0.1U_0402_10V6-K
1
RF@
CC535
2
LAYOUT near t o CPU side
VCC1R0 _SUS
1 2
1U_0402_10V6K
1
CC96
2
VCC1R0 _SUS
VCC1R0 _SUS
+1VALW _PCH
+1VALW _1P0
0603 Footprint
1 2
0603 Footprint
1 2
+VCC_DS W3P3
+VCC_HDA
1
+3V_SPI
RF@
CC534
+VCC_SR AM
2
+3VALW _PRIM
VCC1R0 _SUS
+VCC_PL LEBB
Primary Well 3.3 V
+3VALW _PCH
[SKL PDG]VCCPRIM
[SKL PDG]1uF x1
[SKL PDG]Close V19,
Placement type:Edge<3mm(118mil)
+DCPDSW
+VCC_AMP HYPLL
LC10_0603 _5%
+1VALW _PLL
LC20_0603 _5%
1 2
RC326 0_ 0402_5%
UC1O
AB19
VCCPRIM_1P0_AB19
AB20
VCCPRIM_1P0_AB20
P18
VCCPRIM_1P0_P18
AF18
VCCPRIM_CORE_AF18
AF19
VCCPRIM_CORE_AF19
V20
VCCPRIM_CORE_V20
V21
VCCPRIM_CORE_V21
AL1
DCPDSW_1P0
K17
VCCMPHYAON_1P0_K17
L1
VCCMPHYAON_1P0_L1
N15
VCCMPHYGT_1P0_N15
N16
VCCMPHYGT_1P0_N16
N17
VCCMPHYGT_1P0_N17
P15
VCCMPHYGT_1P0_P15
P16
VCCMPHYGT_1P0_P16
K15
VCCAMPHYPLL_1P0_K15
L15
VCCAMPHYPLL_1P0_L15
V15
VCCAPLL_1P0
AB17
VCCPRIM_1P0_AB17
Y18
VCCPRIM_1P0_Y18
AD17
VCCDSW_3P3_AD17
AD18
VCCDSW_3P3_AD18
AJ17
VCCDSW_3P3_AJ17
AJ19
VCCHDA
AJ16
VCCSPI
AF20
VCCSRAM_1P0_AF20
AF21
VCCSRAM_1P0_AF21
T19
VCCSRAM_1P0_T19
T20
VCCSRAM_1P0_T20
AJ21
VCCPRIM_3P3_AJ21
AK20
VCCPRIM_1P0_AK20
N18
VCCAPLLEBB
SKYLAKE -U_BGA135 6
+3VALW _PRIM
1U_0402_10V6K
1
2
CC97
SKL_ULT
CPU POWER 4 OF 4
AK15
VCCPGPPA
AG15
VCCPGPPB
Y16
VCCPGPPC
Y15
VCCPGPPD
T16
VCCPGPPE
AF16
VCCPGPPF
AD15
VCCPGPPG
V19
VCCPRIM_3P3_V19
T1
VCCPRIM_1P0_T1
AA1
VCCATS_1P8
AK17
VCCRTCPRIM_3P3
AK19
VCCRTC_AK19
BB14
VCCRTC_BB14
BB10
DCPRTC
A14
VCCCLK1
K19
VCCCLK2
L21
VCCCLK3
N20
VCCCLK4
L19
VCCCLK5
A10
VCCCLK6
AN11
GPP_B0/CORE_VID0
AN13
GPP_B1/CORE_VID1
15 OF 20REV = 1
HD Audio Power 3.3 V, 1.8 V, 1.5 V. For Intel High
Definition Audio.
+3VALW _PCH
+1.8VALW _PCH
1 2
RC331 0 _0402_ 5%@
1 2
RC330 0 _0402_ 5%
[SKL PDG]VccHDA
[SKL PDG]1uF x1
[SKL PDG]Close AJ19,
Placement type:Edge<10mm(394mil)
+DCPRTC
+1VALW _CLK2
+1VALW _CLK4
+1VALW _CLK5
[SKL PDG]The CORE_VID[0:1] signal is used by
external VRs to indicate the final settling
voltage for VCCPRIM_CORE rail.
+VCC_HDA
0.1U_0402_10V6-K
+3VALW _PCH
1U_0402_10V6K
1
CC531
CC532
2
+1VALW _PCH
Deep Sx Well 1.0 V: This rail is generated by on die DSW
low dropout (LDO) linear voltage regulator to supply DSW
+1.8VALW _PCH
GPIOs, DSW core logic and DSW USB2 logic. Board needs to
connect 1 uF capacitor to this rail and power should NOT
be driven from the board. When primary well power is up,
this rail is bypassed from VCCPRIM_1p0.
1U_0402_10V6K
1
CC61
2
[SKL PDG]DcpDSW
[SKL PDG]1uF x1
[SKL PDG]Close AL1,
Placement type:Edge<3mm(118mil)
RTC Logic Primary Well 3.3 V. This power supplies the RTC
internal VRM. It will be off during Deep Sx mode.
+3VALW _PCH
RC333 0 _0402_ 5%
[SKL PDG]VccRTCPRIM
[SKL PDG]1uF x1,0.1uF x2
[SKL PDG]Close AK17,
Placement type:Edge<3mm(118mil)
Deep Sx Well for GPD GPIOs and USB2
+3VL
+3VALW _PCH
[SKL PDG]VccDSW
+3VALW _RTCPR IM
1 2
1 2
RC131 0_ 0402_5%@
1 2
RC132 0_ 0402_5%
1U_0402_10V6K
1U_0402_10V6K
RTC de-coupling capacitor only. This rail should NOT
be driven.
+DCPDSW
1
[SKL PDG]DcpRTC
CC60
[SKL PDG]0.1uF x1
[SKL PDG]Close BB10,
Placement type:Edge<3mm(118mil)
2
RTC Logic Primary Well 3.3 V. This power supplies
the RTC internal VRM. It will be off during Deep
Sx mode.
0.1U_0402_10V6-K
0.1U_0402_10V6-K
1
1
1
C201
C200
CC58
2
2
2
+VCC_DS W3P3
[SKL PDG]VccRTC
[SKL PDG]1uF x1
[SKL PDG]Close AK19,
Placement type:Edge<3mm(118mil)
+DCPRTC
1
C197
0.1U_040 2_10V6-K
2
+RTCVCC
1U_0402_10V6K
1
CC59
2
A A
Title
Title
Security C lassification
Security C lassification
Security C lassification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
2
2015/01/12
2015/01/12
2015/01/12
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2016/01/12
2016/01/12
2016/01/12
Title
SKL_POWER_OTHERS
SKL_POWER_OTHERS
SKL_POWER_OTHERS
Size
Size
Size
Document Number Rev
Document Number Rev
Document Number Rev
D
D
D
Date: Sheet
Date: Sheet
Date: Sheet
1
Friday, October 23, 2015
Friday, October 23, 2015
Friday, October 23, 2015
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
18 99
18 99
18 99
of
of
of
0.1
0.1
0.1
5
www.laptoprepairsecrets.com
D D
SKL_U LT
UC1P
GND 1 OF 3
A5
VSS_A5
A67
VSS_A67
A70
VSS_A70
AA2
VSS_AA2
AA4
VSS_AA4
AA65
VSS_AA65
AA68
VSS_AA68
AB15
VSS_AB15
AB16
VSS_AB16
AB18
VSS_AB18
AB21
VSS_AB21
AB8
VSS_AB8
AD13
VSS_AD13
AD16
VSS_AD16
AD19
VSS_AD19
AD20
VSS_AD20
AD21
VSS_AD21
AD62
VSS_AD62
AD8
VSS_AD8
AE64
VSS_AE64
AE65
VSS_AE65
AE66
VSS_AE66
AE67
VSS_AE67
AE68
VSS_AE68
AE69
C C
B B
VSS_AE69
AF1
VSS_AF1
AF10
VSS_AF10
AF15
VSS_AF15
AF17
VSS_AF17
AF2
VSS_AF2
AF4
VSS_AF4
AF63
VSS_AF63
AG16
VSS_AG16
AG17
VSS_AG17
AG18
VSS_AG18
AG19
VSS_AG19
AG20
VSS_AG20
AG21
VSS_AG21
AG71
VSS_AG71
AH13
VSS_AH13
AH6
VSS_AH6
AH63
VSS_AH63
AH64
VSS_AH64
AH67
VSS_AH67
AJ15
VSS_AJ15
AJ18
VSS_AJ18
AJ20
VSS_AJ20
AJ4
VSS_AJ4
AK11
VSS_AK11
AK16
VSS_AK16
AK18
VSS_AK18
AK21
VSS_AK21
AK22
VSS_AK22
AK27
VSS_AK27
AK63
VSS_AK63
AK68
VSS_AK68
AK69
VSS_AK69
AK8
VSS_AK8
AL2
VSS_AL2
AL28
VSS_AL28
AL32
VSS_AL32
AL35
VSS_AL35
AL38
VSS_AL38
AL4
VSS_AL4
AL45
VSS_AL45
AL48
VSS_AL48
AL52
VSS_AL52
AL55
VSS_AL55
AL58
VSS_AL58
AL64
VSS_AL64
SKYLAKE-U_BGA1356
16 OF 20REV = 1
VSS_AL65
VSS_AL66
VSS_AM13
VSS_AM21
VSS_AM25
VSS_AM27
VSS_AM43
VSS_AM45
VSS_AM46
VSS_AM55
VSS_AM60
VSS_AM61
VSS_AM68
VSS_AM71
VSS_AM8
VSS_AN20
VSS_AN23
VSS_AN28
VSS_AN30
VSS_AN32
VSS_AN33
VSS_AN35
VSS_AN37
VSS_AN38
VSS_AN40
VSS_AN42
VSS_AN58
VSS_AN63
VSS_AP10
VSS_AP18
VSS_AP20
VSS_AP23
VSS_AP28
VSS_AP32
VSS_AP35
VSS_AP38
VSS_AP42
VSS_AP58
VSS_AP63
VSS_AP68
VSS_AP70
VSS_AR11
VSS_AR15
VSS_AR16
VSS_AR20
VSS_AR23
VSS_AR28
VSS_AR35
VSS_AR42
VSS_AR43
VSS_AR45
VSS_AR46
VSS_AR48
VSS_AR5
VSS_AR50
VSS_AR52
VSS_AR53
VSS_AR55
VSS_AR58
VSS_AR63
VSS_AR8
VSS_AT2
VSS_AT20
VSS_AT23
VSS_AT28
VSS_AT35
VSS_AT4
VSS_AT42
VSS_AT56
VSS_AT58
AL65
AL66
AM13
AM21
AM25
AM27
AM43
AM45
AM46
AM55
AM60
AM61
AM68
AM71
AM8
AN20
AN23
AN28
AN30
AN32
AN33
AN35
AN37
AN38
AN40
AN42
AN58
AN63
AP10
AP18
AP20
AP23
AP28
AP32
AP35
AP38
AP42
AP58
AP63
AP68
AP70
AR11
AR15
AR16
AR20
AR23
AR28
AR35
AR42
AR43
AR45
AR46
AR48
AR5
AR50
AR52
AR53
AR55
AR58
AR63
AR8
AT2
AT20
AT23
AT28
AT35
AT4
AT42
AT56
AT58
4
SKL_U LT
UC1Q
GND 2 OF 3
AT63
VSS_AT63
AT68
VSS_AT68
AT71
VSS_AT71
AU10
VSS_AU10
AU15
VSS_AU15
AU20
VSS_AU20
AU32
VSS_AU32
AU38
VSS_AU38
AV1
VSS_AV1
AV68
VSS_AV68
AV69
VSS_AV69
AV70
VSS_AV70
AV71
VSS_AV71
AW10
VSS_AW10
AW12
VSS_AW12
AW14
VSS_AW14
AW16
VSS_AW16
AW18
VSS_AW18
AW21
VSS_AW21
AW23
VSS_AW23
AW26
VSS_AW26
AW28
VSS_AW28
AW30
VSS_AW30
AW32
VSS_AW32
AW34
VSS_AW34
AW36
VSS_AW36
AW38
VSS_AW38
AW41
VSS_AW41
AW43
VSS_AW43
AW45
VSS_AW45
AW47
VSS_AW47
AW49
VSS_AW49
AW51
VSS_AW51
AW53
VSS_AW53
AW55
VSS_AW55
AW57
VSS_AW57
AW6
VSS_AW6
AW60
VSS_AW60
AW62
VSS_AW62
AW64
VSS_AW64
AW66
VSS_AW66
AW8
VSS_AW8
AY66
VSS_AY66
B10
VSS_B10
B14
VSS_B14
B18
VSS_B18
B22
VSS_B22
B30
VSS_B30
B34
VSS_B34
B39
VSS_B39
B44
VSS_B44
B48
VSS_B48
B53
VSS_B53
B58
VSS_B58
B62
VSS_B62
B66
VSS_B66
B71
VSS_B71
BA1
VSS_BA1
BA10
VSS_BA10
BA14
VSS_BA14
BA18
VSS_BA18
BA2
VSS_BA2
BA23
VSS_BA23
BA28
VSS_BA28
BA32
VSS_BA32
BA36
VSS_BA36
F68
VSS_F68
BA45
VSS_BA45
SKYLAKE-U_BGA1356
17 OF 20REV = 1
VSS_BA49
VSS_BA53
VSS_BA57
VSS_BA6
VSS_BA62
VSS_BA66
VSS_BA71
VSS_BB18
VSS_BB26
VSS_BB30
VSS_BB34
VSS_BB38
VSS_BB43
VSS_BB55
VSS_BB6
VSS_BB60
VSS_BB64
VSS_BB67
VSS_BB70
VSS_C1
VSS_C25
VSS_C5
VSS_D10
VSS_D11
VSS_D14
VSS_D18
VSS_D22
VSS_D25
VSS_D26
VSS_D30
VSS_D34
VSS_D39
VSS_D44
VSS_D45
VSS_D47
VSS_D48
VSS_D53
VSS_D58
VSS_D6
VSS_D62
VSS_D66
VSS_D69
VSS_E11
VSS_E15
VSS_E18
VSS_E21
VSS_E46
VSS_E50
VSS_E53
VSS_E56
VSS_E6
VSS_E65
VSS_E71
VSS_F1
VSS_F13
VSS_F2
VSS_F22
VSS_F23
VSS_F27
VSS_F28
VSS_F32
VSS_F33
VSS_F35
VSS_F37
VSS_F38
VSS_F4
VSS_F40
VSS_F42
VSS_BA41
3
BA49
BA53
BA57
BA6
BA62
BA66
BA71
BB18
BB26
BB30
BB34
BB38
BB43
BB55
BB6
BB60
BB64
BB67
BB70
C1
C25
C5
D10
D11
D14
D18
D22
D25
D26
D30
D34
D39
D44
D45
D47
D48
D53
D58
D6
D62
D66
D69
E11
E15
E18
E21
E46
E50
E53
E56
E6
E65
E71
F1
F13
F2
F22
F23
F27
F28
F32
F33
F35
F37
F38
F4
F40
F42
BA41
F8
G10
G22
G43
G45
G48
G5
G52
G55
G58
G6
G60
G63
G66
H15
H18
H71
J11
J13
J25
J28
J32
J35
J38
J42
J8
K16
K18
K22
K61
K63
K64
K65
K66
K67
K68
K70
K71
L11
L16
L17
2
SKL_U LT
UC1R
GND 3 OF 3
VSS_F8
VSS_G10
VSS_G22
VSS_G43
VSS_G45
VSS_G48
VSS_G5
VSS_G52
VSS_G55
VSS_G58
VSS_G6
VSS_G60
VSS_G63
VSS_G66
VSS_H15
VSS_H18
VSS_H71
VSS_J11
VSS_J13
VSS_J25
VSS_J28
VSS_J32
VSS_J35
VSS_J38
VSS_J42
VSS_J8
VSS_K16
VSS_K18
VSS_K22
VSS_K61
VSS_K63
VSS_K64
VSS_K65
VSS_K66
VSS_K67
VSS_K68
VSS_K70
VSS_K71
VSS_L11
VSS_L16
VSS_L17
SKYLAKE-U_BGA1356
18 OF 20REV = 1
VSS_L18
VSS_L2
VSS_L20
VSS_L4
VSS_L8
VSS_N10
VSS_N13
VSS_N19
VSS_N21
VSS_N6
VSS_N65
VSS_N68
VSS_P17
VSS_P19
VSS_P20
VSS_P21
VSS_R13
VSS_R6
VSS_T15
VSS_T17
VSS_T18
VSS_T2
VSS_T21
VSS_T4
VSS_U10
VSS_U63
VSS_U64
VSS_U66
VSS_U67
VSS_U69
VSS_U70
VSS_V16
VSS_V17
VSS_V18
VSS_W13
VSS_W6
VSS_W9
VSS_Y17
VSS_Y19
VSS_Y20
VSS_Y21
L18
L2
L20
L4
L8
N10
N13
N19
N21
N6
N65
N68
P17
P19
P20
P21
R13
R6
T15
T17
T18
T2
T21
T4
U10
U63
U64
U66
U67
U69
U70
V16
V17
V18
W13
W6
W9
Y17
Y19
Y20
Y21
1
A A
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
3
2015/01/12
2015/01/12
2015/01/12
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2016/01/12
2016/01/12
2016/01/12
Title
SKL_VSS
SKL_VSS
SKL_VSS
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
Friday, October 23, 2015
Friday, October 23, 2015
Date: Sheet of
Date: Sheet of
Date: Sheet of
Friday, October 23, 2015
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
1
19 99
19 99
19 99
0.1
0.1
0.1
5
www.laptoprepairsecrets.com
4
3
2
1
[SKL EDS]
CFG0
D D
L:Stall.
*H:(Default) Normal Operation; No stall.
UC1S
AL25
AL27
BA70
BA68
E68
B67
D65
D67
E70
C68
D68
C67
F71
G69
F70
G68
H70
G71
H69
G70
E63
F63
E66
F66
E60
E8
AY2
AY1
D1
D3
K46
K45
C71
B70
F60
A52
J71
J68
F65
G65
F61
E61
CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
CFG[18]
CFG[19]
CFG_RCOMP
ITP_PMODE
RSVD_AY2
RSVD_AY1
RSVD_D1
RSVD_D3
RSVD_K46
RSVD_K45
RSVD_AL25
RSVD_AL27
RSVD_C71
RSVD_B70
RSVD_F60
RSVD_A52
RSVD_TP_BA70
RSVD_TP_BA68
RSVD_J71
RSVD_J68
VSS_F65
VSS_G65
RSVD_F61
RSVD_E61
CFG0
CFG4
C C
[SKL CRB]
RC152 49.9_0402_1%
+1VALW_PCH
B B
RC371 1.5K_0402_5%
[SKL PDG]Route
HOOK[6] to
Skylake
ITP_PMODE.
Termination:
Resistor value
from 1K ohm to 3K
ohm pull up to
PCH_V1.0A Rail.
12
12
@
@
@
@
@
@
@
@
@
@
@
@
@
@
TP24
TP26
TP74
TP30
TP86
TP85
TP88@
TP87@
TP90
TP89
TP32
TP91
TP92
TP93
TP94
TP95
TP96@
TP97@
CFG_RCOMP
ITP_PMODE
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
SKYLAKE-U_BGA1356
SKL_U LT
RESERVED SIGNALS-1
RSVD_TP_BB68
RSVD_TP_BB69
RSVD_TP_AK13
RSVD_TP_AK12
RSVD_TP_AW71
RSVD_TP_AW70
PROC_SELECT#
19 OF 20REV = 1
RSVD_BB2
RSVD_BA3
RSVD_D5
RSVD_D4
RSVD_B2
RSVD_C2
RSVD_B3
RSVD_A3
RSVD_AW1
RSVD_E1
RSVD_E2
RSVD_BA4
RSVD_BB4
RSVD_A4
RSVD_C4
RSVD_A69
RSVD_B69
RSVD_AY3
RSVD_D71
RSVD_C70
RSVD_C54
RSVD_D54
VSS_AY71
ZVM#
MSM#
BB68
BB69
AK13
AK12
BB2
BA3
AU5
TP5
AT5
TP6
D5
D4
B2
C2
B3
A3
AW1
E1
E2
BA4
BB4
A4
C4
BB5
TP4
A69
B69
AY3
RC296 0_0402_5%
D71
C70
C54
D54
AY4
TP1
BB3
TP2
AY71
RC295 0_0402_5%
AR56
AW71
AW70
AP56
C64
1 2
1 2
1
TP37
@
1
TP39
@
1
TP43 @
1
TP45 @
1
TP49
@
1
TP51
@
1
TP59 @
1
TP60 @
1
TP22
@
1
TP23
@
1
TP25
@
1
TP27
@
1
TP64
@
1
TP66
@
1
TP29
@
1
TP31
@
1
TP33
@
1
TP34
@
1
TP35
@
1
TP67
@
1
TP68
@
1
TP54
@
1
TP927
@
1
TP928
@
1
TP929 @
1
TP930 @
1
TP931 @
1
TP932 @
1
TP933 @
1
TP934 @
1
TP935 @
1
TP936 @
1
TP937 @
1
TP938 @
RC105 1K_0402_5%@
RC201 1K_0402_1%@
RC374
100K_0402_1%
12
12
TABLE
CFG0 : Stall Reset Sequence
after PCU PLL Lock until de-asserted
1 : No Stall
0 : Stall
CFG4 : eDP Enable
1 : Disabled
0 : Enabled
CFG9 : SVID Bus Communication
1 : Enabled
0 : Disabled
[SKL EDS]Zero Voltage Mode:VCCOPC is fixed OPC VR output voltage of 1V, the
processor can drive VR to LPM (Low Power Mode) which sets VR output to 0V using
ZVM# signal as shown below:
ZVM# state
0V
1V
+VCC_ST
[SKL EDS]Minimum Speed Mode: VCCEOPIO can be connected to OPC VR in this
case VCCEOPIO is fixed to 1V. The processor can drive VR to LPM (Low Power
Mode) which sets VR output to 0V using ZVM# signal .
In order to achieve better power/performance it is recommended to use a
separate VR for VCCEOPIO in this case VCCEOPIO is configurable to 0.8V/1V.
The processor drives the VR to set VCCEOPIO value(0.8V/1V) using MSM#
signal, based on the required bandwidth for the EOPIO interface as shown
12
below:
ZVM# state
CFG4
CFG4CFG0
*L: Embedded DisplayPort Enabled
H: Embedded DisplayPort Disabled
VCCOPC
0V
1V
MSM# state
0V
1V
1V
X
0V
1V 1V
VCCEOPIO
RC104 1K_0402_5%@
RC144 1K_0402_1%
12
12
0V
0.8V
+VCC_IO+VCC_IO
A A
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
3
2015/01/12
2015/01/12
2015/01/12
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2016/01/12
2016/01/12
2016/01/12
Title
SKL_CFG/ RSVD
SKL_CFG/ RSVD
SKL_CFG/ RSVD
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
Friday, October 23, 2015
Friday, October 23, 2015
Date: Sheet of
Date: Sheet of
Date: Sheet of
Friday, October 23, 2015
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
1
20 99
20 99
20 99
0.1
0.1
0.1
5
www.laptoprepairsecrets.com
D D
C C
4
UC1T
TP98@
TP99@
TP100@
TP101@
TP102@
TP103@
TP104@
TP105@
1
1
1
1
1
1
1
1
AW69
AW68
AU56
AW48
U12
U11
H11
C7
RSVD_AW69
RSVD_AW68
RSVD_AU56
RSVD_AW48
RSVD_C7
RSVD_U12
RSVD_U11
RSVD_H11
SKYLAKE-U_BGA1356
SKL_ULT
20 OF 20REV = 1
SPARE
3
RSVD_F6
RSVD_E3
RSVD_C11
RSVD_B11
RSVD_A11
RSVD_D12
RSVD_C12
RSVD_F52
F6
E3
C11
B11
A11
D12
C12
F52
1
1
1
1
1
1
1
1
TP106 @
TP107 @
TP108 @
TP109 @
TP110 @
TP111 @
TP112 @
TP113 @
2
1
B B
A A
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
2015/01/12
2015/01/12
2015/01/12
3
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2016/01/12
2016/01/12
2016/01/12
2
Title
SKL_RSVD
SKL_RSVD
SKL_RSVD
Size
Size
Size
Document Number Re v
Document Number Re v
Document Number Re v
B
B
B
Friday, October 23, 2015
Friday, October 23, 2015
Date: Sheet
Date: Sheet
Date: Sheet
Friday, October 23, 2015
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
1
21 99
21 99
21 99
0.1
0.1
0.1
of
of
of
5
www.laptoprepairsecrets.com
SA_DIMM_VREFDQ[6]
1 2
D D
C C
B B
A A
1
CD2
DIMM1@
0.022U_0402_25V7-K
2
12
RD4
DIMM1@
24.9_0402_1%
+1.35V
12
RD1
DIMM1@
DIMM1@
1.8K_0402_1%
12
1.8K_0402_1%
RD3
0.1U_0402_10V7-K
DIMM1@
1
CD3
2
DIMM1@
RD2
2_0402_1%
Close to JDIMM1
DDRA_CKE0_DIMMA[6]
DDR_A_BS2[6]
SA_CLK_DDR0[6]
SA_CLK_DDR#0[6]
DDR_A_BS0[6]
DDR_A_WE#[6]
DDR_A_CAS#[6]
DDRA_CS1_DIMMA#[6]
+3VS
+0.675VS +0.675VS
5
0.1U_0402_10V6-K
2.2U_0402_6.3V6-K
@
DIMM1@
1
CD29
2
2.2U_0402_6.3V6-K
1
CD1
EMC@
2
DDRA_CKE0_DIMMA
DDR_A_BS2
DDRA_CS1_DIMMA#
CD51
1
2
+V_DDR_REFA
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
SA_CLK_DDR0
SA_CLK_DDR#0
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
DDR_A_MA13
DDR_A_D32
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
RC316
0_0402_5%
1 2
1 2
RC315
0_0402_5%
4
+1.35V +1.35V
JDIMM1
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
9
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1
DQS129RESET#
31
VSS11
33
DQ10
35
DQ11
37
VSS13
39
DQ16
41
DQ17
43
VSS15
45
DQS#2
47
DQS2
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25
VSS2261DQS#3
63
DM3
65
VSS23
67
DQ26
69
DQ27
71
VSS25
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
99
VDD9
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
LCN_DAN06-K4406-0102
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS3
VSS24
DQ30
DQ31
VSS26
CKE1
VDD2
VDD4
VDD6
VDD8
VDD10
CK1#
VDD12
RAS#
VDD14
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
VTT2
ME@
A15
A14
A11
CK1
BA1
S0#
SCL
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
A7
88
90
A6
92
A4
94
96
A2
98
A0
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
G2
Channel A
4
DDR_A_D4
DDR_A_D5
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D6
DDR_A_D7
DDR_A_D12
DDR_A_D13
DDR3_DRAMRST#
DDR_A_D14
DDR_A_D15
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31
DDRA_CKE1_DIMMA
DDR_A_MA15
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
SA_CLK_DDR1
SA_CLK_DDR#1
DDR_A_BS1
DDR_A_RAS#
DDRA_CS0_DIMMA#
DDRA_ODT0_DIMMA#
DDRA_ODT1_DIMMA#
+VREF_CA
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
3
DDR_A_DQS#[0..7] [6]
DDR_A_DQS[0..7] [6]
DDR_A_D[0..31] [6]
DDR_A_MA[0..15] [6]
+1.35V
12
RD26
470_0402_5%
CD59
180P_0402_50V8-J
2.2U_0402_6.3V6-K
1
CD17
CD18
2
EMC@
DDR3_DRAMRST# [6,23]
1
2
DDRA_CKE1_DIMMA [6]
SA_CLK_DDR1 [6]
SA_CLK_DDR#1 [6]
DDR_A_BS1 [6]
DDR_A_RAS# [6]
DDRA_CS0_DIMMA# [6]
DDRA_ODT0_DIMMA# [6]
DDRA_ODT1_DIMMA# [6]
0.1U_0402_10V7-K
DIMM1@
1
2
close to JDDR3L.126
PM_SMB_DAT [8,23,63]
PM_SMB_CLK [8,23,63]
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
3
DDR_A_D[32..63] [6]
+1.35V
12
RD9
1.8K_0402_1%
12
RD11
1.8K_0402_1%
+VREF_CA [23]
DDR_PG_CTRL
2015/01/12
2015/01/12
2015/01/12
All VREF traces should
have 10 mil trace width
RD10
1 2
2_0402_1%
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
1
2
12
Deciphered Date
Deciphered Date
Deciphered Date
2
CD12
0.022U_0402_25V7-K
RD12
24.9_0402_1%
12
R3020_0402_5% @
2
DIMM1@
10U_0603_6.3V6-M
1U_0402_6.3VA-K
SM_DIMM_VREFCA [6]
DDR_PG_CTRL[6]
UD1
2
3
74AUP1G07GF_SOT891-6_1X1
2016/01/12
2016/01/12
2016/01/12
Layout Note:
Place near JDIMM1
DIMM1@
CD14
10U_0603_6.3V6-M
DIMM1@
CD9
1U_0402_6.3VA-K
DIMM1@
CD23
1U_0402_6.3VA-K
CC538
NC2
Y
DIMM1@
10U_0603_6.3V6-M
1
2
1U_0402_6.3VA-K
1
2
1U_0402_6.3VA-K
1
2
6
5
4
CD13
1
2
CD8
@
1
2
0.1U_0402_10V7-K @
@
NC11Vcc
A
GND
1
+1.35V
CD22
330U_D2_2V_Y
1
1
+
2
2
CD15
DIMM1@
DIMM1@
CD19
CD16
10U_0603_6.3V6-M
10U_0603_6.3V6-M
1
2
1
1
2
2
DIMM1@
CD20
10U_0603_6.3V6-M
DIMM1@
CD21
10U_0603_6.3V6-M
1
2
For RF solution.
DIMM1@
CD10
CD11
1U_0402_6.3VA-K
@
1
2
Layout Note:
Place near JDIMM1.203,204
DIMM1@
CD24
1
2
1
2
+1.35V
@
Title
Title
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
0.1U_0402_10V7-K
1
2
CD25
1U_0402_6.3VA-K
1U_0402_6.3VA-K
@
1
2
+1.35V
DDR_PG_CTRL
12
RD24
@
10K_0402_5%
1
CD62
0.1U_0402_10V7-K
2
R301 0_0402_5%@
DDR3L SO-DIMM1 LOW
DDR3L SO-DIMM1 LOW
DDR3L SO-DIMM1 LOW
Friday, October 23, 2015
Friday, October 23, 2015
Friday, October 23, 2015
CRF1
1
RF@
2
CD26
@
1
2
2
1 2
CRF2
100P_0402_50V8J
1
RF@
2
+0.675VS
+3V_DDR
12
RD25
100K_0402_5%
SM_PG_CTRL
1
QD1
DTC115TMT2L_VMT3
3
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
1
SM_PG_CTRL [87]
SM_PG_CTRL
22 99
22 99
22 99
0.1
0.1
0.1
5
www.laptoprepairsecrets.com
+1.35V
12
RD15
DIMM2@
RD17
SB_DIMM_VREFDQ[6]
D D
DIMM2@
DIMM2@
1 2
1
2_0402_1%
CD310.022U_0402_25V7-K
DIMM2@
2
12
RD1824.9_0402_1%
1.8K_0402_1%
12
RD16
DIMM2@
1.8K_0402_1%
0.1U_0402_10V7-K
1
2
+V_DDR_REFB
2.2U_0402_6.3V6-K
CD32
1
CD33
DIMM2@
2
EMC@
Close to JDIMM2
12
RD19
DIMM2@
10K_0402_5%
0.1U_0402_10V6-K
CD57
DDRB_CKE0_DIMMB
DDR_B_BS2
DDRB_CS1_DIMMB#
CD58
1
DIMM2@
2
1 2
DDRB_CKE0_DIMMB[6]
+3VS
+0.675VS
DDR_B_BS2[6]
SB_CLK_DDR0[6]
SB_CLK_DDR#0[6]
DDR_B_BS0[6]
DDR_B_WE#[6]
DDR_B_CAS#[6]
DDRB_CS1_DIMMB#[6]
+3VS
2.2U_0402_6.3V6-K
@
1
2
C C
B B
A A
5
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
DDR_B_D24
DDR_B_D25
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D26
DDR_B_D27
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
SB_CLK_DDR0
SB_CLK_DDR#0
DDR_B_MA10
DDR_B_BS0DDR_B_BS0
DDR_B_WE#DDR_B_WE#
DDR_B_CAS#DDR_B_CAS#
DDR_B_MA13
DDR_B_D32
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
RC317
0_0402_5%
4
+1.35V
JDIMM2
1
VREF_DQ
3
VSS_1
5
DQ0
7
DQ1
9
VSS_3
11
DM0
13
VSS_5
15
DQ2
17
DQ3
19
VSS_7
21
DQ8
23
DQ9
25
VSS_9
27
DQS1#
29
DQS1
31
VSS_11
33
DQ10
35
DQ11
37
VSS_13
39
DQ16
41
DQ17
43
VSS_15
45
DQS2#
47
DQS2
49
VSS_17
51
DQ18
53
DQ19
55
VSS_19
57
DQ24
59
DQ25
61
VSS_21
63
DM3
65
VSS_23
67
DQ26
69
DQ27
71
VSS_25
73
CKE0
75
VDD_1
77
NC_1
79
BA2
81
VDD_3
83
A12/BC#
85
A9
87
VDD_5
89
A8
91
A5
93
VDD_7
95
A3
97
A1
99
VDD_9
101
CK0
103
CK0#
105
VDD_11
107
A10/AP
109
BA0
111
VDD_13
113
WE#
115
CAS#
117
VDD_15
119
A13
121
S1#
123
VDD_17
125
TEST
127
VSS_27
129
DQ32
131
DQ33
133
VSS_29
135
DQS4#
137
DQS4
139
VSS_31
141
DQ34
143
DQ35
145
VSS_33
147
DQ40
149
DQ41
151
VSS_36
153
DM5
155
VSS_37
157
DQ42
159
DQ43
161
VSS_39
163
DQ48
165
DQ49
167
VSS_41
169
DQS6#
171
DQS6
173
VSS_43
175
DQ50
177
DQ51
179
VSS_45
181
DQ56
183
DQ57
185
VSS_47
187
DM7
189
VSS_49
191
DQ58
193
DQ59
195
VSS_51
197
SA0
199
VDDSPD
201
SA1
203
VTT_1
205
GND1
207
BOSS1
LCN_DAN06-K4406-0103
VSS_2
VSS_4
DQS0#
DQS0
VSS_6
VSS_8
DQ12
DQ13
VSS_10
RESET#
VSS_12
DQ14
DQ15
VSS_14
DQ20
DQ21
VSS_16
VSS_18
DQ22
DQ23
VSS_20
DQ28
DQ29
VSS_22
DQS3#
DQS3
VSS_24
DQ30
DQ31
VSS_26
CKE1
VDD_2
VDD_4
VDD_6
VDD_8
VDD_10
CK1#
VDD_12
RAS#
VDD_14
ODT0
VDD_16
ODT1
NC_2
VDD_18
VREF_CA
VSS_28
DQ36
DQ37
VSS_30
VSS_32
DQ38
DQ39
VSS_34
DQ44
DQ45
VSS_35
DQS5#
DQS5
VSS_38
DQ46
DQ47
VSS_40
DQ52
DQ53
VSS_42
VSS_44
DQ54
DQ55
VSS_46
DQ60
DQ61
VSS_48
DQS7#
DQS7
VSS_50
DQ62
DQ63
VSS_52
EVENT#
VTT_2
GND2
BOSS2
DQ4
DQ5
DQ6
DQ7
DM1
DM2
CK1
BA1
DM4
DM6
SDA
SCL
ME@
A15
A14
A11
A7
A6
A4
A2
A0
S0#
Channel B
<Address: SA1:SA0=10>
DIMM_2 STD H:4mm
4
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
+1.35V
DDR_B_D4
DDR_B_D5
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D6
DDR_B_D7
DDR_B_D12
DDR_B_D13
DDR3_DRAMRST#
DDR_B_D14
DDR_B_D15
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D20
DDR_B_D21
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D22
DDR_B_D23
DDRB_CKE1_DIMMB
DDR_B_MA15
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
SB_CLK_DDR1
SB_CLK_DDR#1
DDR_B_BS1
DDR_B_RAS#
DDRB_CS0_DIMMB#
DDRB_ODT0_DIMMB#
DDRB_ODT1_DIMMB#
+VREF_CA
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
+0.675VS
3
DDR_B_DQS#[0..3] [6]
DDR_B_DQS[0..3] [6]
DDR_B_D[0..31] [6]
DDR_B_MA[0..15] [6]
DDR_B_D[32..63] [6]
DDR_B_DQS#[4..7] [6]
DDR_B_DQS[4..7] [6]
1
2
PM_SMB_DAT [8,22,63]
PM_SMB_CLK [8,22,63]
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
DDR3_DRAMRST# [6,22]
EMC_NS@
CD60
0.1U_0402_10V7-K
DDRB_CKE1_DIMMB [6]
SB_CLK_DDR1 [6]
SB_CLK_DDR#1 [6]
DDR_B_BS1 [6]
DDR_B_RAS# [6]
DDRB_CS0_DIMMB# [6]
DDRB_ODT0_DIMMB# [6]
DDRB_ODT1_DIMMB# [6]
1
CD49
DIMM2@
0.1U_0402_10V7-K
2
3
+VREF_CA [22]
All VREF traces should
have 10 mil trace width
2015/01/12
2015/01/12
2015/01/12
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2
DIMM2@
CD42
10U_0603_6.3V6-M
1
2
CD38
1U_0402_6.3VA-K
@
1
2
2016/01/12
2016/01/12
2016/01/12
10U_0603_6.3V6-M
1U_0402_6.3VA-K
Layout Note:
Place near JDIMM2
DIMM2@
DIMM2@
CD43
CD44
10U_0603_6.3V6-M
1
1
2
2
DIMM2@
CD40
CD39
1U_0402_6.3VA-K
@
1
1
2
2
Layout Note:
Place near JDIMM2.203,204
DIMM2@
DIMM2@
CD52
CD54
1U_0402_6.3VA-K
1U_0402_6.3VA-K
1
1
2
2
Title
Title
Title
DDR3L SO-DIMM2 HIGH
DDR3L SO-DIMM2 HIGH
DDR3L SO-DIMM2 HIGH
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
DIMM2@
DIMM2@
CD45
CD46
10U_0603_6.3V6-M
10U_0603_6.3V6-M
1
2
For RF solution.
DIMM2@
CD41
CRF3
0.1U_0402_10V7-K
1U_0402_6.3VA-K
1
2
DIMM2@
CD53
1U_0402_6.3VA-K
1
2
Friday, October 23, 2015
Friday, October 23, 2015
Friday, October 23, 2015
1
2
1
RF@
2
DIMM2@
CD61
1
2
1U_0402_6.3VA-K
DIMM2@
CD47
10U_0603_6.3V6-M
100P_0402_50V8J
1
2
CRF4
DIMM2@
CD55
1
RF@
2
1
2
1
DIMM2@
CD48
10U_0603_6.3V6-M
1
2
+0.675VS
DIMM2@
CD56
10U_0603_6.3V6-M
10U_0603_6.3V6-M
1
2
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
1
23 99
23 99
23 99
+1.35V
0.1
0.1
0.1
5
www.laptoprepairsecrets.com
D D
C C
4
3
2
1
B B
A A
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
3
2015/01/12
2015/01/12
2015/01/12
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2016/01/12
2016/01/12
2016/01/12
Title
XXXX
XXXX
XXXX
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
Friday, October 23, 2015
Friday, October 23, 2015
Date: Sheet of
Date: Sheet of
Date: Sheet of
Friday, October 23, 2015
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
1
24 99
24 99
24 99
0.1
0.1
0.1
5
www.laptoprepairsecrets.com
4
3
2
1
+VCC_CORE +VCC_GT
D D
C C
[SKL PDG]VCC
[SKL PDG]22uF x9,10uF x7,1uF x35
22U_0603_6.3V6-M
22U_0603_6.3V6-M
C228
C227
C226
1
1
2
2
10U_0402_6.3V6-M
C236
C247
C364
C374
10U_0402_6.3V6-M
C238
C237
1
1
2
2
1U_0201_6.3V6-M
1U_0201_6.3V6-M
C248
C249
1
1
2
2
1U_0201_6.3V6-M
1U_0201_6.3V6-M
C361
C363
1
1
2
2
1U_0201_6.3V6-M
1U_0201_6.3V6-M
C371
C373
1
1
2
2
[SKL PDG]VCCGT
[SKL PDG]10uF x10,1uF x12
22U_0603_6.3V6-M
22U_0603_6.3V6-M
C266
C229
1
1
2
2
10U_0402_6.3V6-M
10U_0402_6.3V6-M
C239
C240
1
1
2
2
1U_0201_6.3V6-M
1U_0201_6.3V6-M
C250
C251
1
1
2
2
1U_0201_6.3V6-M
1U_0201_6.3V6-M
C362
C369
1
1
2
2
1U_0201_6.3V6-M
1U_0201_6.3V6-M
C379
C372
1
1
2
2
22U_0603_6.3V6-M
22U_0603_6.3V6-M
C267
C232
1
1
2
2
10U_0402_6.3V6-M
10U_0402_6.3V6-M
C243
C241
1
1
2
2
1U_0201_6.3V6-M
1U_0201_6.3V6-M
C252
C253
1
1
2
2
1U_0201_6.3V6-M
1U_0201_6.3V6-M
C368
C370
1
1
2
2
1U_0201_6.3V6-M
1U_0201_6.3V6-M
C378
C380
1
1
2
2
22U_0603_6.3V6-M
22U_0603_6.3V6-M
C233
1
2
1U_0201_6.3V6-M
C244
1
2
1U_0201_6.3V6-M
C254
1
2
1U_0201_6.3V6-M
C367
1
2
1U_0201_6.3V6-M
C377
1
2
22U_0603_6.3V6-M
C268
1
2
1U_0201_6.3V6-M
C245
1
2
1U_0201_6.3V6-M
C255
1
2
1U_0201_6.3V6-M
C366
1
2
1U_0201_6.3V6-M
C376
1
2
10U_0402_6.3V6-M
C235
1
1
2
2
1U_0201_6.3V6-M
1U_0201_6.3V6-M
C246
1
1
2
2
1U_0201_6.3V6-M
1U_0201_6.3V6-M
C256
1
1
2
2
1U_0201_6.3V6-M
1U_0201_6.3V6-M
C365
1
1
2
2
1U_0201_6.3V6-M
1U_0201_6.3V6-M
C257
1
1
2
2
C273
C283
C293
10U_0402_6.3V6-M
10U_0402_6.3V6-M
10U_0402_6.3V6-M
C274
C275
1
1
2
2
1U_0201_6.3V6-M
1U_0201_6.3V6-M
C285
C284
1
1
2
2
1U_0201_6.3V6-M
1U_0201_6.3V6-M
C294
1
1
2
2
10U_0402_6.3V6-M
10U_0402_6.3V6-M
10U_0402_6.3V6-M
C276
C277
1
1
2
2
1U_0201_6.3V6-M
1U_0201_6.3V6-M
C286
C287
1
1
2
2
C279
C278
1
1
2
2
1U_0201_6.3V6-M
1U_0201_6.3V6-M
C288
C289
1
1
2
2
10U_0402_6.3V6-M
10U_0402_6.3V6-M
C281
C280
1
1
2
2
1U_0201_6.3V6-M
1U_0201_6.3V6-M
C291
C290
1
1
2
2
10U_0402_6.3V6-M
10U_0402_6.3V6-M
C282
C355
1
1
2
2
1U_0201_6.3V6-M
1U_0201_6.3V6-M
C357
C292
1
1
2
2
10U_0402_6.3V6-M
10U_0402_6.3V6-M
C356
1
1
2
2
1U_0201_6.3V6-M
1U_0201_6.3V6-M
C358
C359
1
1
2
2
1U_0201_6.3V6-M
1U_0201_6.3V6-M
C360
1
1
2
2
B B
A A
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
3
2015/01/12
2015/01/12
2015/01/12
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2016/01/12
2016/01/12
2016/01/12
Title
CPU_CAPS
CPU_CAPS
CPU_CAPS
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
Friday, October 23, 2015
Friday, October 23, 2015
Date: Sheet of
Date: Sheet of
Date: Sheet of
Friday, October 23, 2015
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
1
25 99
25 99
25 99
0.1
0.1
0.1
5
www.laptoprepairsecrets.com
D D
C C
4
3
2
1
B B
A A
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
3
2015/01/12
2015/01/12
2015/01/12
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2016/01/12
2016/01/12
2016/01/12
Title
XXXX
XXXX
XXXX
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
Friday, October 23, 2015
Friday, October 23, 2015
Date: Sheet of
Date: Sheet of
Date: Sheet of
Friday, October 23, 2015
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
1
26 99
26 99
26 99
0.1
0.1
0.1
5
www.laptoprepairsecrets.com
D D
C C
4
3
2
1
B B
A A
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
3
2015/01/12
2015/01/12
2015/01/12
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2016/01/12
2016/01/12
2016/01/12
Title
XXXX
XXXX
XXXX
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
Friday, October 23, 2015
Friday, October 23, 2015
Date: Sheet of
Date: Sheet of
Date: Sheet of
Friday, October 23, 2015
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
1
27 99
27 99
27 99
0.1
0.1
0.1
5
www.laptoprepairsecrets.com
D D
C C
4
3
2
1
B B
A A
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
3
2015/01/12
2015/01/12
2015/01/12
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2016/01/12
2016/01/12
2016/01/12
Title
XXXX
XXXX
XXXX
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
Friday, October 23, 2015
Friday, October 23, 2015
Date: Sheet of
Date: Sheet of
Date: Sheet of
Friday, October 23, 2015
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
1
28 99
28 99
28 99
0.1
0.1
0.1
5
www.laptoprepairsecrets.com
D D
C C
4
3
2
1
B B
A A
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
3
2015/01/12
2015/01/12
2015/01/12
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2016/01/12
2016/01/12
2016/01/12
Title
XXXX
XXXX
XXXX
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
Friday, October 23, 2015
Friday, October 23, 2015
Date: Sheet of
Date: Sheet of
Date: Sheet of
Friday, October 23, 2015
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
1
29 99
29 99
29 99
0.1
0.1
0.1
5
www.laptoprepairsecrets.com
4
3
2
1
H_THERMTRIP# [7]
1
CV150
@
0.1U_0402_10V7-K
2
1 2
1 2
RV125
RV123
10K_0402_5%
10K_0402_5%
MESO@
@
1 2
RV124
RV126
10K_0402_5%
10K_0402_5%
@
@
1 2
Pre-PWROK Metal VID
SVC SVD Boot Voltage
0 0
001
1
1 1
1.1V
1.0V
0.9V(Default)
0.8V
RV105
PD 2K
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
BL460_NM-A651BL460_NM-A651
Friday, October 23, 2015
Friday, October 23, 2015
Friday, October 23, 2015
1
SVI2_SVD
SVI2_SVC
001
110
010
111
000
101
of
30 99
of
30 99
of
30 99
0.1
0.1
0.1
NC_DPA
NC_DPB
NC_DPC
NC_AVSSN_1
NC_AVSSN_2
NC_AVSSN_3
NC_DAC1
NC_GENLK_CLK
NC_GENLK_VSYNC
MLPS&SVI 2
NC_SWAPLOCKA
NC_SWAPLOCKB
NC_DDC/AUX
NC_DDC1CLK
NC_DDC1DATA
NC_DDCVGACLK
NC_DDCVGADATA
FDO
3
DIS@
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22
NC_23
NC_24
NC_25
NC_26
NC_27
NC_28
NC_29
NC_30
NC_31
NC_32
NC_33
NC_34
NC_35
NC_HSYNC
NC_RSET
NC_AVDD
NC_AVSSQ
NC_VDD1DI
NC_VSS1DI
NC_CEC_1
GPIO_SVD
GPIO_SVT
GPIO_SVC
NC_AUX1P
NC_AUX1N
NC_AUX2P
NC_AUX2N
NC_36
NC_37
1
CV151
0.1U_0402_10V7-K
2
RV120
10K_0402_5%
EXO@
1 2
12
RV88
@
100K_0402_5%
+3VS_VGA
CV149
@
Samsun g
Hynix
Micro n
RV87
1 2
2.2K_0402_5%
0.1U_0402_10V7-K
1
2
1
CV152
@
10U_0603_6.3V6-M
2
@
2016/01/12
2016/01/12
2016/01/12
RV95
1 2
@
10K_0402_5%
SVI2_SVD
SVI2_SVT
AF2
AF4
AG3
AG5
AH3
AH1
AK3
AK1
AK5
AM3
AK6
AM5
AJ7
AH6
AK8
AL7
V4
U5
V2
Y4
W5
Y2
J8
AL25
NC_G
AK26
AJ25
AH24
NC_B
AG25
AH26
AD22
AG24
AE22
AE23
AD23
AM12
1 2
AK12
RV107 0_0402_5%MESO@
AL11
1 2
RV108 0_0402_5%MESO@
AJ11
1 2
RV109 0_0402_5%MESO@
AL13
AJ13
AG13
PS_0
AC19
PS_0
AH12
PS_1
AD19
PS_1
PS_2
AE17
PS_2
PS_3
AE20
PS_3
AE6
AE5
AD2
AD4
AD13
AD11
AE16
AD16
AC1
AC3
+1.8VS_VGA
DIS@
DIS@
+1.8VS_VGA
DIS@
@
SVI2_SVD
SVI2_SVT
SVI2_SVC
12
1 2
12
12
RV98
8.45K_0402_1%
RV99
2K_0402_1%
RV102
10K_0402_1%
RV103
4.75K_0402_1%
PLT_RST_VGA#[9,35,91]
1
CV153
@
0.1U_0402_10V7-K
2
1
CV155
@
0.1U_0402_10V7-K
2
GPIO19_CTF
PLT_RST_VGA#
1 2
GPIO15
RV89 33_0402_5%@
1 2
GPIO20
RV90 33_0402_5%@
SVI2_SVD [91]
SVI2_SVC [91]
PS_0PS_0
PS_1
SVI2_SVD
SVI2_SVT
SVI2_SVC
+1.8VS_VGA
DIS@
+1.8VS_VGA
X76@
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIA L
THIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIA L
THIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIA L
AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DI VISION OF R& D
AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DI VISION OF R& D
AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DI VISION OF R& D
DEPARTMENT EXCEPT AS AUTHORIZED BY L C FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY L C FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY L C FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF LC FUTURE CENTER.
RV86 47K_0402_5%@
DV1 RB751V-40_SOD323-2
RV91
10K_0402_5%
RV93
10K_0402_5%
RV118
@
10K_0402_5%
1 2
12
RV100
@
10K_0402_1%
12
RV101
@
4.75K_0402_1%
12
RV104
3.24K_0402_1%
12
@
RV105
5.62K_0402_1%X76@
2015/01/12
2015/01/12
2015/01/12
2
1 2
@
1 2
SCS00006S00
+3VS_VGA
12
12
@
12
12
@
RV119
@
10K_0402_5%
1 2
PS_2
1
CV154
0.1U_0402_10V7-K
2
PS_3
1
CV156
0.1U_0402_10V7-K
2
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
RV92
10K_0402_5%
RV94
10K_0402_5%
@
@
@
Deciphered Date
Deciphered Date
Deciphered Date
2
B
CV148
0.1U_0402_10V7-K
1
@
2
1 2
RV147 0_0402_5%@
1 2
RV148 0_0402_5%@
UV9
@
1
VCC(A)
VCC(B)
2
1A
3
2A
5
DIR
74AVCH2T45GD_XSON8_3X2
+3VS_VGA
+1.8VS_VGA+3VS_VGA
1 2
1 2
1G
2G
1G
2G
1G
2G
C
QV3
@
MMST3904-7-F_SOT323-3
E
SB000010U00
3 1
+1.8VS_VGA
8
7
RV96 33_0402_5%@
1B
6
RV97 33_0402_5%@
2B
4
GND
RV121
10K_0402_5%
@
1 2
RV122
10K_0402_5%
DIS@
1 2
RV104Memory ( GDDR3)
PU 8.45K
PU 3.4K PD 10K
PU 4.53K PD 2K
PU 4.75K NC
NC PD 4.7 5K
PU 3.24K PD 5.62K
Title
Title
Title
EXO_S3_CLK/GPIO
EXO_S3_CLK/GPIO
EXO_S3_CLK/GPIO
Size
Size
Size
Document Number R ev
Document Number R ev
Document Number R ev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
UV3A
N9
1
TPV3
TPV4
TPV5
TPV6
TPV7
TPV8
TPV9
TPV10
TPV11
TPV13
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
12
RV71
DIS@
4.7K_0402_5%
SMBDAT
SMBCLK
GPIO6
GPIO8_ROMSO
GPIO9_ROMSI
GPIO10_ROMSCK
GPIO15
GPIO20
GPIO22_ROMCSB
JTAG_TRSTB
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO
XTALIN
XTALOUT
FDO
TPV17
TPV18
TPV19
TPV20
TPV21
TPV22
TPV23
TPV24
TPV25
TPV26
TPV27
TPV28
TPV29
TPV30
TPV31
TPV32
TPV33
TPV34
NC_DBG_DATA16
L9
NC_DBG_DATA15
AE9
NC_DBG_DATA14
Y11
NC_DBG_DATA13
AE8
NC_DBG_DATA12
AD9
DBG_DATA11
AC10
DBG_DATA10
AD7
DBG_DATA9
AC8
DBG_DATA8
AC7
DBG_DATA7
AB9
DBG_DATA6
AB8
DBG_DATA5
AB7
DBG_DATA4
AB4
DBG_DATA3
AB2
DBG_DATA2
Y8
DBG_DATA1
Y7
DBG_DATA0
AL9
NC_DBG_CNTL0
U1
BP_0
U3
BP_1
AM26
DIECRACKMON
W6
NC_2
V6
NC_3
AC6
NC_4
AC5
NC_5
AA5
NC_6
AA6
NC_7
Y6
NC_8
I2C
R1
SCL
R3
SDA
GENERAL PURPOSE I/O
U6
GPIO_0
U8
SMBDATA
U7
SMBCLK
T9
GPIO_5_AC_BATT
T8
GPIO_6_TACH
T7
NC_GPIO_7
P10
GPIO_8_ROMSO
P4
GPIO_9_ROMSI
P2
GPIO_10_ROMSCK
N6
NC_GPIO_11
N5
NC_GPIO_12
N3
NC_GPIO_13
N1
GPIO_15_PWRCNTL_0
M4
GPIO_16
R6
GPIO_17_THERMAL_INT
M2
GPIO_19_CTF
P8
GPIO_20_PWRCNTL_1
P7
GPIO_21
N8
GPIO_22_ROMCSB
AK10
GPIO_29
AM10
GPIO_30
N7
CLKREQB
L6
JTAG_TRSTB
L5
JTAG_TDI
L3
JTAG_TCK
L1
JTAG_TMS
K4
JTAG_TDO
K7
TESTEN
AF24
NC_9
W8
NC_GENERICB
W7
NC_GENERICD
AD10
NC_GENERICE_HPD4
AJ9
NC_10
AB16
PX_EN
AJ27
WAKEB
AC16
NC_DBG_VREFG
PLL/CLOCK
AA1
PLL_ANALOG_IN
AA3
PLL_ANALOG_OUT
AM28
XTALIN
AK28
XTALOUT
AC22
XO_IN
AB22
XO_IN2
T4
DPLUS
T2
DMINUS
R5
GPIO28_FDO
AD17
TSVDD
AC17
TSVSS
AE19
TS_A
216-0858020-A0_FCBGA631
THERMAL
RV84
DBG
EXO@
1 2
10K_0402_5%
Test_Point_20MIL
Test_Point_20MIL
Test_Point_20MIL
Test_Point_20MIL
Test_Point_20MIL
Test_Point_20MIL
Test_Point_20MIL
12
RV55
4.7K_0402_5%
MESO@
+3VS_VGA
12
DIS@
1 2
1 2
Test_Point_20MIL
Test_Point_20MIL
Test_Point_20MIL
1 2
1 2
1 2
Test_Point_20MIL
1 2
1 2
Test_Point_20MIL
Test_Point_20MIL
Test_Point_20MIL
Test_Point_20MIL
Test_Point_20MIL
+3VS_VGA
RV76 5.11K_0402_1%@
RV77 1K_0402_1%DIS@
TPV12
RV78 0_0402_5%@
RV79 0_0402_5%@
RV80 4.7K_0402_5%
RV106 4.7K_0402_5%MES O@
Test_Point_20MIL
RV81 16.2K_0402_1%MESO@
RV82 10K_0402_5%DIS@
RV83 10K_0402_5%DIS@
1
CV145
1U_0402_10V6-K
2
Test_Point_20MIL
Test_Point_20MIL
Test_Point_20MIL
Test_Point_20MIL
Test_Point_20MIL
Test_Point_20MIL
Test_Point_20MIL
Test_Point_20MIL
Test_Point_20MIL
Test_Point_20MIL
Test_Point_20MIL
RV70
4.7K_0402_5%
1
1
1
1
1
1
1
1
1
1 2
1 2
1 2
1 2
@
1 2
1 2
1
1 2
1 2
1 2
D D
+3VS_VGA
SMBCLK
SMBDAT
C C
VGA_AC_DC#[77]
GPU_VR_HOT#[77,91]
B B
+3VS_VGA
12
12
RV63
@
@
10K_0402_5%
A A
VGA_ON[9,38,39,91]
CLKREQ_PCIE4_VGA#[13]
1
QV2A
NTJD5121NT1G_SC88-6
5
DIS@
G2
4
D23S2
QV2B
SB000013A00
NTJD5121NT1G_SC88-6
DIS@
+3VS_VGA
RV111 10K_0402_5%DIS@
VGA_AC_DC# GPIO5_AC_BATTGPIO5_AC_BATT
DV2 RB751V-40_SOD323-2
SCS00006S00
RV113 0_0402_5%@
RV114
1 2
@
0_0402_5%
12
RV64
RV65
@
10K_0402_5%
10K_0402_5%
RV49
@
10K_0402_5%
1
CV141
@
0.1U_0402_10V7-K
2
12
5
can remove
1 2
RV41 0_0402_5%@
2
G1
D16S1
SB000013A00
PU AT EC SIDE, +3VS AND 4.7K
1 2
DIS@
1 2
1 2
+3VS_VGA
12
RV61
@
10K_0402_5%
RV62
OCP_L
1 2
@
1K_0402_1%
12
RV66
@
10K_0402_5%
JTAG_TRSTB
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO
+3VS_VGA
12
@
1
CV140
@
0.1U_0402_10V7-K
2
2
1 3
D
QV7 2N7002KW_SOT323-3
SB000019400
1 2
@
RV51 0_0402_5%
EC_SMB_CK3 [8,69,70,77]
EC_SMB_DA3 [8,69,70,77]
GPIO6
1
CV142
@
0.1U_0402_10V7-K
2
12
RV67
@
10K_0402_5%
RV50
10K_0402_5%
+3VS_VGA
G
@
S
PLT_RST_VGA#
12
RV52
@
10K_0402_5%
CLK_REQ_GPU#
RV53
@
10K_0402_5%
1 2
Test_Point_20MIL
Test_Point_20MIL
BIOS directly open PCIE bus
+3VS_VGA
RV115 4.7K_0402_5%@
RV140 0_0402_5%@
EC_WAKE#[7,77]
GPU_WAKE#[14]
RV68 1M_0402_5%
4
1
XTALOUT
1
CV143
DIS@
22P_0402_50V8-J
2
+1.8VS_VGA
12
RV54
4.7K_0402_5%
MESO@
1
TPV1
1
TPV2
+3VS_VGA
RV72 20K_0402_5%DIS@
RV73 20K_0402_5%DIS@
SVI2_SVD
RV117 0_0402_5%DIS@
RV74 10K_0402_5%DI S@
GPIO19_CTF
SVI2_SVC
RV116 0_0402_5%DIS@
CLK_REQ_GPU# SVI2_SVC
RV112 0_0402_5%@
RV75 10K_0402_5%DI S@
1
Test_Point_20MIL
1 2
1 2
DIS@
1 2
YV1
DIS@
3
NC2
OSC2
2
OSC1
NC1
27MHZ_16PF_7V27000011
DIS@
4
2
G
@
1 3
D
S
QV4 2N7002KW_SOT323-3
SB000019400
XTALIN
1
CV144
22P_0402_50V8-J
2
+3VS_VGA
+1.8VS_VGA
DIS@
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