Lenovo ThinkPad E440 Schematic

A

1 1

B

C

D

E

2 2

NM-A151 Rev1.0 Schematic

Intel Haswell Processor with DDRIII + Lynx point PCH

nVIDIA N14P-GV2/ N14M-GL

2013-07-11 Rev 1.0

3 3

www.rosefix.com

4 4

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

C

2012/12/05

LC Future Center Secret Data

Deciphered Date

D

2014/12/05

Title

Cover Page

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

E440 NM-A151

E440 NM-A151E440 NM-A151

E

1 57

of

1.0

A

B

C

D

E

N14P-GV2 2G N14M-GL 1G

VRAM 128M*16 *4 VRAM 256M*16 *4

1 1

Page 23,24,25,26,27,28,29,30,31,32,33

Small Board

2 2

Realtek RTL8111G

LAN Board

Realtek RTS5227 USB Charge Port

Card Reader Board

ODD Board For 15"

Card Reader Board

3 3

Power Circuit DC/DC

Page 52,53,54,55,56,57, 58,59,60,61,62

DC/DC Interface CKT.

Finger Print Conn

POWER/B Conn.

ODD/B Conn.

4 4

Touch Pad Conn

Page 51

Page 56

Page 40

page 41

Page 56

Page 55

A

SIM Conn

Track Point ConnClick Pad Conn

Page 54

Page 53

PCI-Express 16X Gen3

PEG 0~7

HDMI Conn.

HDMI1.4b

Page 36

eDP Conn.

Page 35

CRT Conn.

Page 35

JRJ45 Conn.

PCIe port 4

Page 42

JUCR Conn.

PCIe port 3

SATA ODD For 15"

SATA Port 2

SATA ODD For 14"

SATA Port 2

SATA HDD

SATA Port 1

Page 43

Page 44

Page 45

Page 44

SPI ROM (4MB+8MB)

Page 17

B

HDMI

1.65GT/s

eDP

3.3V 5.4GT/s

CRT

PCIe Gen1

1.5V 2.5GT/s

PCIe Gen1

1.5V 2.5GT/S

SATA Gen1 Port2 5V 3GHz(150MB/s)

SATA Gen3 Port 0 5V 6GHz(600MB/s)

SPI BUS

3.3V 33MHz

Debug Port

Page 39

G-Sensor LIS34ALTR

Intel CPU Haswell

rPGA-989

37.5mm*37.5mm

Page 5,6,7,8,9,10,11

DMI *4 5GT/s

Intel PCH Lynx point

695 ball FCBGA 20mm*20mm

Page 14,15,16,17,18,19,20,21,22

LPC BUS

3.3V 33MHz

EC ITE IT8586E-CX

Int.KBD

Issued Date

Int. K/B

Page 46

C

ADC

Page 47

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

FDI *2 5GT/s

USB 3.0 5V 500MB/S

USB 2.0 5V 60MB/S

PCIe Gen1 5V 2.5GT/S

SATA Gen3

5V 6GHz(600MB/s)

HD Audio

3.3V 24MHz

SMBus

PS2

Page 47

SMBus

Thermal Sensor EMC 1403

2012/12/05

SMBus Port3

Page 40

LC Future Center Secret Data

Memory BUS (DDRIII) Dual Channel

1.35V DDRIIIL 1066/1333/1600 MT/s

DP

Docking Conn

USB 3.0 Port 1

Page 51

USB Left

USB 3.0 Port 2 USB 3.0 Port 5

Page 50

Touch panel

USB 2.0 Port 4

PCIeMini Card WLAN

PCIe Port 5

USB 2.0 Port 10

Page 39

Sub Board

Codec COX 20751

Page 45

Security EEPROM

SMBus Port3

Page 41

Click Pad

SMBus Port3

Page 47 Page 48

2014/12/05

Deciphered Date

2014/12/05

D

DDR3-SO-DIMM X2

BANK 0, 1, 2, 3

UP TO 16G

USB Right

USB 2.0 Port 5

Page 50

mSATA SSD

SATA Port 0

Page 37

PCIeMini Card WWAN

USB 2.0 Port 11

Page 38

SPK Conn.

Int. Comb Conn. (Ext MIC & HP)

Track Point

Title

Block Diagram

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

Int. Camera

USB 2.0 Port 13

Page 46

Page 34

SMBus

E440 NM-A151

E440 NM-A151E440 NM-A151

Page 34Page 51

E

2 57

of

1.0

A

B

C

D

E

Voltage Rails

Power Plane

1 1

State

S0

S3

2 2

S5 S4/AC Only

S5 S4 Battery only

S5 S4 AC & Battery don't exist

SMBUS Control Table

3 3

EC_SMB_DA1

EC_SMB_CK2

EC_SMB_DA2

PM_SMBCLK PM_SMBDATA

( O --> Means ON , X --> Means OFF )

+3VALW

B+

+1.5V

+5VALW

O

O O O

O

X X

SOURCE

IT8580EEC_SMB_CK1

+3VALW

IT8580E

+3VS

PCH

+3V_PCH

Main VGA

+3VS +3VS

2nd VGA

X

V

BATT SODIMM

X X XV

+3VALW

V

X

IT8580E

X X X X X

+5VS

+3VS

+1.5VS

+VCCSA

+V1.5S_VCCP

+CPU_CORE

+VGA_CORE

+GFX_CORE

+1.8VS

+1.05VS

+0.75VS

+3.3VS_VGA

+1.5VS_VGA

+1.05VS_VGA

OO

X

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

USB Port Table

EHCI1

X

EHCI2

X

V V

+3VS

WLAN WiMAX

X

V

X

Thermal Sensor

V

+3VS

PCH

V

+3V_PCH

+3V_PCH+3VS

CP Module

XX

X

V

+3VS

SIGNAL

SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

HIGH HIGH HIGH HIGH

USB 3.0USB 2.0 Port

XHCI

1

2

3

4

0

1

5 6

7 8

9 10 11 12 13

PCIE PORT LIST

Port Device

1 2 3 4 5 6 7 8

LOW

LOW LOW LOW LOW

HIGH

LOWLOWLOW

HIGHHIGHHIGH

HIGH

4 External USB Port

Camera

USB Port (Right Side)

USB Port (Left Side)

USB Port (Right Side)

Mini Card(WLAN)

Blue Tooth

LAN WLAN

Card Reader

ON

OFF

ON ON

ON

OFF

ON

BOM Structure Table

HDMI@ CHG@

NOCHG@ CMOS@ 8171@

8171S@

SURGE@

X76@ GC6@ NOGC6@

AOAC@ KBL@ ME@

SLI@

DS3@

S3@

GT@

@

EDP@

daul@

LOW

OFF

BTO ItemBOM Structure

HDMI part

USB charger part

No USB charger part

NV no CG6 support part

CMOS Camera part

QCA8171 LAN part

QCA8171 LAN surge part

QCA8171&8172 LAN surge part

X76 Level part for VRAM

NV CG6 support part

AOAC support part

K/B Light part

ME part

For SLI function part

Deep S3 support part

For S3 function part

NV chip part

Unpop

Support EDP panel function

Support daul channel panel function

A

Address

0001 011X b

EC SM Bus2 address

B

Address

1001_101xb

0x9E 0x9C

Device

Thermal Sensor EMC1403-2

Master VGA

Slave VGA

PCH SM Bus address

Device Address

DDR DIMM0

DDR DIMM2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

C

1001 000Xb

1001 010Xb

2012/12/05

LC Future Center Secret Data

Deciphered Date

D

2014/12/05

4 4

EC SM Bus1 address

Device

Smart Battery

ZZZ1

DA80000TV00

Title

Notes List

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

E440 NM-A151

E440 NM-A151E440 NM-A151

E

3 57

of

1.0

5

4

3

2

1

Hot plug detect for IFP link E

VGA and GDDR5 Voltage Rails (N13Px GPIO)

GPIO I/O ACTIVE Function Description

GPIO0

D D

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

GPIO8

GPIO9

GPIO10

C C

GPIO11

GPIO12

GPIO13

GPIO14

GPIO15

GPIO16

GPIO17

GPIO18

GPIO19

B B

+1.05VS_VGA

OUT GPU VID4-

OUT

I/O

OUT

IN

OUT

IN

OUT

IN

+3VS_VGA

+VGA_CORE

+1.5VS_VGA

GPU VID3OUT

-

VGA_BL_PWM

-

VGA_ENVDD

- VGA_ENBKL

-

GPU VID1

-

GPU VID2

DPRSLPVR_VGA

-

Thermal Catastrophic Over Temperature

-

GPIO9

-

Memory VREF Control

GPU VID0-OUT

AC Power Detect Input

GPU VID5-

FB_CLAMP_TOGGLE_REQ#

-

N/A (100K pull low)

FRMLCK#

-

N/A

-

dGPU_HDMI_HPD

HPD_IRQ

-

tNVVDD >0

tFBVDDQ >0

tPEX_VDD >0

1. all power rail ramp up time should be larger than 40us

(10K pull High)

Performance Mode P0 TDP at Tj = 102 C* (GDDR5)

GPU Mem NVCLK (4) (1,5) (6)

Products

N13X 128bit 1GB GDDR5

Physical Strapping pin ROM_SCLK

(W) (W) (MHz)

ROM_SI

ROM_SO FB[0]

STRAP0

STRAP1

STRAP2

STRAP3

STRAP4

/MCLK NVVDD

(V) (A) (W) (A) (W)

TBD TBDTBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

Power Rail

+3VS_VGA

Logical Strapping Bit3

PCI_DEVID[4]

FB[1]

PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]

SOR3_EXPOSED

RESERVED PCIE_SPEED_

Device ID

N13P-GT (28nm)

0x0FDB

SMB_ALT_ADDR

(ROM_SO Bit 1)

FBVDD

Logical Strapping Bit2 SUB_VENDOR

USER[2] USER[1] USER[0]USER[3]

3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1]3GIO_PAD_CFG_ADR[3]

SOR2_EXPOSED SOR1_EXPOSED

CHANGE_GEN3

setting

0

1

ROM_SO ROM_SCLK

GPU

N13P-GT1 28nm

GPU

FB Memory (GDDR5)

Samsung 2500MHz

Hynix 2500MHz

Samsung 2500MHz

2500MHz

PU 25K

PU 45KPU 10K PD 10K

PU 25K PD 35KPU 45KPU 20K PD 10K PD 5K PD 10K

K4G10325FG-HC04

32Mx32

H5GQ1H24BFR-T2C

32Mx32 PD 35K

K4G20325FD-FC04

64Mx32

H5GQ2H24MFR-T2CHynix

64Mx32

PD 35K

N13P-GT

ROM_SI

PD 45K

PD 30K

PD 25K

FBVDDQ PCI Express I/O and (GPU+Mem) (1.35V)(1.35V)

(A) (W) (W)(mA) (W) (W) (W)(mA) (mA) (mA)

I2C Slave addrees ID

0x9E

0x9C

STRAP2STRAP1STRAP0

STRAP3

PU 5K PD 10K

(1.05V)

Logical Strapping Bit1

SLOT_CLK_CFG

RAM_CFG[1]RAM_CFG[3] RAM_CFG[2]

PLLVDD

I/O and PLLVDD

Logical Strapping Bit0

PEX_PLL_EN_TERM

RAM_CFG[0]

VGA_DEVICESMB_ALT_ADDR

3GIO_PAD_CFG_ADR[0]

PCIE_MAX_SPEED DP_PLL_VDD33V

SOR0_EXPOSED

STRAP4

Master

Slave

Other

(3.3V)(1.05V)(1.8V)

Other Power rail

A A

+3VS_VGA

Tpower-off <10ms

1.all GPU power rails should be turned off within 10ms

2. Optimus system VDD33 avoids drop down earlier than NVDD and FBVDDQ

5

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/12/05

LC Future Center Secret Data

Deciphered Date

2

2014/12/05

Title

VGA Notes List

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

E440 NM-A151

E440 NM-A151E440 NM-A151

1

4 57

of

1.0

5

4

3

2

1

D D

Haswell rPGA EDS

JCPU1A

ME@

DMI_CRX_PTX_N[3:0]<15>

DMI_CRX_PTX_P[3:0]<15>

DMI_CTX_PRX_N[3:0]<15>

DMI_CTX_PRX_P[3:0]<15>

C C

FDI_CSYNC<15> FDI_INT<15>

B B

DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3

DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3

DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3

DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3

FDI_CSYNC FDI_INT

D21

DMI_RXN_0

C21

DMI_RXN_1

B21

DMI_RXN_2

A21

DMI_RXN_3

D20

DMI_RXP_0

C20

DMI_RXP_1

B20

DMI_RXP_2

A20

DMI_RXP_3

D18

DMI_TXN_0

C17

DMI_TXN_1

B17

DMI_TXN_2

A17

DMI_TXN_3

D17

DMI_TXP_0

C18

DMI_TXP_1

B18

DMI_TXP_2

A18

DMI_TXP_3

H29

FDI_CSYNC

J29

DISP_INT

INTEL_HASWELL_HASWELL

DMI FDI

PEG

1 OF 9

PEG_RCOMP

PEG_RXN_10 PEG_RXN_11 PEG_RXN_12 PEG_RXN_13 PEG_RXN_14 PEG_RXN_15

PEG_RXP_10 PEG_RXP_11 PEG_RXP_12 PEG_RXP_13 PEG_RXP_14 PEG_RXP_15

PEG_TXN_10 PEG_TXN_11 PEG_TXN_12 PEG_TXN_13 PEG_TXN_14 PEG_TXN_15

PEG_TXP_10 PEG_TXP_11 PEG_TXP_12 PEG_TXP_13 PEG_TXP_14 PEG_TXP_15

PEG_RXN_0 PEG_RXN_1 PEG_RXN_2 PEG_RXN_3 PEG_RXN_4 PEG_RXN_5 PEG_RXN_6 PEG_RXN_7 PEG_RXN_8 PEG_RXN_9

PEG_RXP_0 PEG_RXP_1 PEG_RXP_2 PEG_RXP_3 PEG_RXP_4 PEG_RXP_5 PEG_RXP_6 PEG_RXP_7 PEG_RXP_8 PEG_RXP_9

PEG_TXN_0 PEG_TXN_1 PEG_TXN_2 PEG_TXN_3 PEG_TXN_4 PEG_TXN_5 PEG_TXN_6 PEG_TXN_7 PEG_TXN_8 PEG_TXN_9

PEG_TXP_0 PEG_TXP_1 PEG_TXP_2 PEG_TXP_3 PEG_TXP_4 PEG_TXP_5 PEG_TXP_6 PEG_TXP_7 PEG_TXP_8 PEG_TXP_9

E23 M29 K28 M31 L30 M33 L32 M35 L34 E29 D28 E31 D30 E35 D34 E33 E32 L29 L28 L31 K30 L33 K32 L35 K34 F29 E28 F31 E30 F35 E34 F33 D32 H35 H34 J33 H32 J31 G30 C33 B32 B31 A30 B29 A28 B27 A26 B25 A24 J35 G34 H33 G32 H31 H30 B33 A32 C31 B30 C29 B28 C27 B26 C25 B24

PEG_COMP PCIE_CRX_GTX_N0 PCIE_CRX_GTX_N1 PCIE_CRX_GTX_N2 PCIE_CRX_GTX_N3 PCIE_CRX_GTX_N4 PCIE_CRX_GTX_N5 PCIE_CRX_GTX_N6 PCIE_CRX_GTX_N7

PCIE_CRX_GTX_P0 PCIE_CRX_GTX_P1 PCIE_CRX_GTX_P2 PCIE_CRX_GTX_P3 PCIE_CRX_GTX_P4 PCIE_CRX_GTX_P5 PCIE_CRX_GTX_P6 PCIE_CRX_GTX_P7

PCIE_CTX_GRX_N0 PCIE_CTX_GRX_N1 PCIE_CTX_GRX_N2 PCIE_CTX_GRX_N3 PCIE_CTX_GRX_N4 PCIE_CTX_GRX_N5 PCIE_CTX_GRX_N6 PCIE_CTX_GRX_N7

PCIE_CTX_GRX_P0 PCIE_CTX_GRX_P1 PCIE_CTX_GRX_P2 PCIE_CTX_GRX_P3 PCIE_CTX_GRX_P4 PCIE_CTX_GRX_P5 PCIE_CTX_GRX_P6 PCIE_CTX_GRX_P7

PEG_COMP

CAD Note: Trace width=12 mils ,Spacing=15mils Max length= 400 mils.

CC1 0.22U_0 402_10V6-KDIS@CC1 0.22U_0402_10V6-KDIS@ CC2 0.22U_0 402_10V6-KDIS@CC2 0.22U_0402_10V6-KDIS@ CC3 0.22U_0 402_10V6-KDIS@CC3 0.22U_0402_10V6-KDIS@ CC4 0.22U_0 402_10V6-KDIS@CC4 0.22U_0402_10V6-KDIS@ CC5 0.22U_0402_10V6-KDIS@CC5 0.22U_0402_10V6-KDIS@ CC6 0.22U_0 402_10V6-KDIS@CC6 0.22U_0402_10V6-KDIS@ CC7 0.22U_0 402_10V6-KDIS@CC7 0.22U_0402_10V6-KDIS@ CC8 0.22U_0 402_10V6-KDIS@CC8 0.22U_0402_10V6-KDIS@

CC9 0.22U_0 402_10V6-KDIS@CC9 0.22U_0402_10V6-KDIS@ CC10 0.22U_0402_10V6-KDIS@CC10 0.22U_0402_10V6-KDIS@ CC11 0.22U_0402_10V6-KDIS@CC11 0.22U_0402_10V6-KDIS@ CC12 0.22U_0402_10V6-KDIS@CC12 0.22U_0402_10V6-KDIS@ CC13 0.22U_0402_10V6-KDIS@CC13 0.22U_0402_10V6-KDIS@ CC14 0.22U_0402_10V6-KDIS@CC14 0.22U_0402_10V6-KDIS@ CC15 0.22U_0402_10V6-KDIS@CC15 0.22U_0402_10V6-KDIS@ CC16 0.22U_0402_10V6-KDIS@CC16 0.22U_0402_10V6-KDIS@

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

1 2

RC1 24.9_0402_1%RC1 24.9_0402_1%

PCIE_CRX_GTX_N[7:0] <23>

PCIE_CRX_GTX_P[7:0] <23>

PCIE_CTX_C_GRX_N0 PCIE_CTX_C_GRX_N1 PCIE_CTX_C_GRX_N2 PCIE_CTX_C_GRX_N3 PCIE_CTX_C_GRX_N4 PCIE_CTX_C_GRX_N5 PCIE_CTX_C_GRX_N6 PCIE_CTX_C_GRX_N7

PCIE_CTX_C_GRX_P0 PCIE_CTX_C_GRX_P1 PCIE_CTX_C_GRX_P2 PCIE_CTX_C_GRX_P3 PCIE_CTX_C_GRX_P4 PCIE_CTX_C_GRX_P5 PCIE_CTX_C_GRX_P6 PCIE_CTX_C_GRX_P7

+VCCIOA_OUT

PCIE_CTX_C_GRX_N[7:0] <23>

PCIE_CTX_C_GRX_P[7:0] <23>

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/12/05

LC Future Center Secret Data

Deciphered Date

2

2014/12/05

Title

CPU_DMI/PEG/FDI

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

E440 NM-A151

E440 NM-A151E440 NM-A151

1

5 57

of

1.0

5

D D

4

3

2

1

Reserve for VCCST

+1.05VS_PCH_VPROC

+VCCIO_OUT

C C

1 2

RC3 62_0402_5%RC3 62_0402_5%

1 2

RC7 10K_0402_5%RC7 10K_0402_5%

Buffered Reset to CPU, 1.5V

135MHz

100 MHz PCIe 3.0

H_PROCHOT#

H_CPUPWRGD_R

CLK_CPU_DPLL#<16> CLK_CPU_DPLL<16> CLK_CPU_SSC_DPLL#<16> CLK_CPU_SSC_DPLL<16> CLK_CPU_DMI#<16> CLK_CPU_DMI<16>

H_PECI<48>

H_PROCHOT#<48> H_THERMTRIP#<19>

H_PM_SYNC<15> H_CPUPWRGD<19>

PLTRST_PROC#<19>

1 2

RC8 56_0402_5%RC8 56_0402_5%

1 2

RC10 0_0402_5%RC10 0_0402_5%

1 2

RC11 0_0402_5%RC11 0_0402_5%

1 2

RC12 0_0402_5%RC12 0_0402_5%

1 2

RC13 0_0402_5%RC13 0_0402_5%

1 2

RC14 0_0402_5%RC14 0_0402_5%

1 2

RC15 0_0402_5%RC15 0_0402_5%

1

CC41

@ CC41

@

0.1U_0402_25V6-K

2

H_PECI

H_PROCHOT#_R H_THERMTRIP#

H_PM_SYNC H_CPUPWRGD_R SM_DRAMPWROK CPU_PLTRSTIN#

CPU_DPLL# CPU_DPLL CPU_SSC_DPLL# CPU_SSC_DPLL CLK_CPU_DMI# CLK_CPU_DMI

Haswell rPGA EDS

JCPU1B

ME@

JCPU1B

ME@

MISC

AP32

1

T1T1

SKTOCC

AN32

CATERR

AR27

PECI

AK31

FC_AK31

AM30

PROCHOT

AM35

THERMTRIP

AT28

PM_SYNC

AL34

PWRGOOD

AC10

SM_DRAMPWROK

AT26

PLTRSTIN

G28

DPLL_REF_CLKN

H28

DPLL_REF_CLKP

F27

SSC_DPLL_REF_CLKN

E27

SSC_DPLL_REF_CLKP

D26

BCLKN

E26

BCLKP

INTEL_HASWELL_HASWELL

MISC

2 OF 9

DDR3

CLOCK

SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2

SM_DRAMRST

JTAG

BPM_N_0 BPM_N_1 BPM_N_2 BPM_N_3 BPM_N_4 BPM_N_5 BPM_N_6 BPM_N_7

PRDY PREQ

TCK TMS

TRST

TDO DBR

TDI

THERMAL

PWR

DDR3 COMPENSATION SIGNALS CAD Note: Trace width=12~15 mil, Spcing=20 mils Max trace length= 500 mil

AP3

SM_RCOMP0

AR3

SM_RCOMP1

AP2

SM_RCOMP2

AN3

H_DRAMRST# DDR3_DRAMRST#

AR29

XDP_PRDY#

AT29

XDP_PREQ#

AM34

XDP_TCLK

AN33

XDP_TMS

AM33

XDP_TRST#

AM31

XDP_TDI

AL33

XDP_TDO

AP33

XDP_DBRESET#

AR30 AN31 AN29 AP31 AP30 AN28 AP29 AP28

TP closer to CPU XDP Connector reserve test point

1 2

RC2 100_ 0402_1%RC2 100_0402_1%

1 2

RC4 75_0 402_1%RC4 75_0 402_1%

1 2

RC5 100_ 0402_1%RC5 100_0402_1%

1 2

RC6 0_04 02_5%RC6 0_0402_5%

1

T3 @T3 @

1

T4 @T4 @

1

T5 @T5 @

1

T6 @T6 @

1

CC43

CC43 330P_0402_50V7-K

330P_0402_50V7-K

2

XDP_TDO

XDP_TCLK

XDP_TRST#

DDR3_DRAMRST# <11,12>

ESD

1 2

RC16 51_0402_1%RC16 51_0402_1%

1 2

RC17 51_0402_1%RC17 51_0402_1%

1 2

RC18 51_0402_1%RC18 51_0402_1%

+1.05VS

XDP_DBRESET#

PU/PD for JTAG signals Place R closer to CPU

B B

1 2

RC9 1K_0402_1%RC9 1K_0402_1%

+3VS

SM_DRAMPWROK Topology for platforms supporting Deep S3

+1.35V

12

RC21

1.8K_0402_1%

1 2

RC22 0_0402_5%RC22 0_0402_5%

SM_DRAMPWROK rise and fall time must be < 50ns

12

measured between VDDQ *0.15 and VDDQ *0.47.

RC23

3.3K_0402_1%

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Issued Date

Close to JCPU. AC10

SM_DRAMPWROK

1

CC44

CC44 330P_0402_50V7-K

330P_0402_50V7-K

2

LC Future Center Secret Data

2012/12/05

3

Deciphered Date

2

SM_DRAMPWROK

2014/12/05

ESD

Title

CPU_JTAG/XDP/CLK

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

E440 NM-A151

E440 NM-A151E440 NM-A151

1

6 57

of

1.0

RC20

RC20 100K_0402_5%

100K_0402_5%

RC24 0_0402_5%@RC24 0_0402_5%@

+3V_PCH+3V_PCH

5

1

B

2

A

3

1 2

P

G

1

@

CC17

0.1U_0402_25V6-K

2

4

O

UC1

UC1 74AHC1G09GW_TSSOP5

74AHC1G09GW_TSSOP5

4

DRAMPWROK_AND

+3V_PCH

12

RC19

RC19 200_0402_1%

200_0402_1%

DRAMPWROK<15>

A A

5

12

5

4

3

2

1

D D

DDRA_DQ[0..63]<11>

C C

B B

+V_SM_VREF +VREF_DQA_M3 +VREF_DQB_M3

DDRA_DQ0 DDRA_DQ1 DDRA_DQ2 DDRA_DQ3 DDRA_DQ4 DDRA_DQ5 DDRA_DQ6 DDRA_DQ7 DDRA_DQ8 DDRA_DQ9 DDRA_DQ10 DDRA_DQ11 DDRA_DQ12 DDRA_DQ13 DDRA_DQ14 DDRA_DQ15 DDRA_DQ16 DDRA_DQ17 DDRA_DQ18 DDRA_DQ19 DDRA_DQ20 DDRA_DQ21 DDRA_DQ22 DDRA_DQ23 DDRA_DQ24 DDRA_DQ25 DDRA_DQ26 DDRA_DQ27 DDRA_DQ28 DDRA_DQ29 DDRA_DQ30 DDRA_DQ31 DDRA_DQ32 DDRA_DQ33 DDRA_DQ34 DDRA_DQ35 DDRA_DQ36 DDRA_DQ37 DDRA_DQ38 DDRA_DQ39 DDRA_DQ40 DDRA_DQ41 DDRA_DQ42 DDRA_DQ43 DDRA_DQ44 DDRA_DQ45 DDRA_DQ46 DDRA_DQ47 DDRA_DQ48 DDRA_DQ49 DDRA_DQ50 DDRA_DQ51 DDRA_DQ52 DDRA_DQ53 DDRA_DQ54 DDRA_DQ55 DDRA_DQ56 DDRA_DQ57 DDRA_DQ58 DDRA_DQ59 DDRA_DQ60 DDRA_DQ61 DDRA_DQ62 DDRA_DQ63

JCPU1C

AR15

SA_DQ_0

AT14

SA_DQ_1

AM14

SA_DQ_2

AN14

SA_DQ_3

AT15

SA_DQ_4

AR14

SA_DQ_5

AN15

SA_DQ_6

AM15

SA_DQ_7

AM9

SA_DQ_8

AN9

SA_DQ_9

AM8

SA_DQ_10

AN8

SA_DQ_11

AR9

SA_DQ_12

AT9

SA_DQ_13

AR8

SA_DQ_14

AT8

SA_DQ_15

AJ9

SA_DQ_16

AK9

SA_DQ_17

AJ6

SA_DQ_18

AK6

SA_DQ_19

AJ10

SA_DQ_20

AK10

SA_DQ_21

AJ7

SA_DQ_22

AK7

SA_DQ_23

AF4

SA_DQ_24

AF5

SA_DQ_25

AF1

SA_DQ_26

AF2

SA_DQ_27

AG4

SA_DQ_28

AG5

SA_DQ_29

AG1

SA_DQ_30

AG2

SA_DQ_31

J1

SA_DQ_32

J2

SA_DQ_33

J5

SA_DQ_34

H5

SA_DQ_35

H2

SA_DQ_36

H1

SA_DQ_37

J4

SA_DQ_38

H4

SA_DQ_39

F2

SA_DQ_40

F1

SA_DQ_41

D2

SA_DQ_42

D3

SA_DQ_43

D1

SA_DQ_44

F3

SA_DQ_45

C3

SA_DQ_46

B3

SA_DQ_47

B5

SA_DQ_48

E6

SA_DQ_49

A5

SA_DQ_50

D6

SA_DQ_51

D5

SA_DQ_52

E5

SA_DQ_53

B6

SA_DQ_54

A6

SA_DQ_55

E12

SA_DQ_56

D12

SA_DQ_57

B11

SA_DQ_58

A11

SA_DQ_59

E11

SA_DQ_60

D11

SA_DQ_61

B12

SA_DQ_62

A12

SA_DQ_63

AM3

SM_VREF

F16

SA_DIMM_VREFDQ

F13

SB_DIMM_VREFDQ

INTEL_HASWELL_HASWELL

ME@

Haswell rPGA EDS

SA_CK_N_0 SA_CK_P_0

SA_CKE_0 SA_CK_N_1 SA_CK_P_1

SA_CKE_1 SA_CK_N_2 SA_CK_P_2

SA_CKE_2 SA_CK_N_3 SA_CK_P_3

SA_CKE_3

SA_CS_N_0 SA_CS_N_1 SA_CS_N_2 SA_CS_N_3

SA_ODT_0

SA_ODT_1

SA_ODT_2

SA_ODT_3

SA_BS_0 SA_BS_1 SA_BS_2

SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8

SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14 SA_MA_15

SA_DQS_N_0 SA_DQS_N_1 SA_DQS_N_2 SA_DQS_N_3 SA_DQS_N_4 SA_DQS_N_5 SA_DQS_N_6 SA_DQS_N_7 SA_DQS_P_0 SA_DQS_P_1 SA_DQS_P_2 SA_DQS_P_3 SA_DQS_P_4 SA_DQS_P_5 SA_DQS_P_6 SA_DQS_P_7

3 OF 9

RSVD_1

VSS_1

SA_RAS

SA_WE

SA_CAS

AC7 U4 V4 AD9 U3 V3 AC9 U2 V2 AD8 U1 V1 AC8

M7 L9 M9 M10 M8 L7 L8 L10 V5 U5 AD1

V10 U6 U7 U8

V8 AC6 V9 U9 AC5 AC4 AD6 AC3 AD5 AC2 V6 AC1 AD4 V7 AD3 AD2

AP15 AP8 AJ8 AF3 J3 E2 C5 C11 AP14 AP9 AK8 AG3 H3 E3 C6 C12

DDRA_CLK0# DDRA_CLK0 DDRA_CKE0 DDRA_CLK1# DDRA_CLK1 DDRA_CKE1

DDRA_CS0# DDRA_CS1#

DDRA_ODT0 DDRA_ODT1

DDRA_BS0# DDRA_BS1# DDRA_BS2#

DDRA_RAS# DDRA_WE# DDRA_CAS#

DDRA_MA0 DDRA_MA1 DDRA_MA2 DDRA_MA3 DDRA_MA4 DDRA_MA5 DDRA_MA6 DDRA_MA7 DDRA_MA8 DDRA_MA9 DDRA_MA10 DDRA_MA11 DDRA_MA12 DDRA_MA13 DDRA_MA14 DDRA_MA15

DDRA_DQS#0 DDRA_DQS#1 DDRA_DQS#2 DDRA_DQS#3 DDRA_DQS#4 DDRA_DQS#5 DDRA_DQS#6 DDRA_DQS#7 DDRA_DQS0 DDRA_DQS1 DDRA_DQS2 DDRA_DQS3 DDRA_DQS4 DDRA_DQS5 DDRA_DQS6 DDRA_DQS7

DDRA_CLK0# <11> DDRA_CLK0 <11> DDRA_CKE0 <11> DDRA_CLK1# <11> DDRA_CLK1 <11> DDRA_CKE1 <11>

DDRA_CS0# <11> DDRA_CS1# <11>

DDRA_ODT0 <11> DDRA_ODT1 <11>

DDRA_BS0# <11> DDRA_BS1# <11> DDRA_BS2# <11>

DDRA_RAS# <11> DDRA_WE# <11> DDRA_CAS# <11>

DDRA_DQS#[0..7] <11>

DDRA_DQS[0..7] <11>

Haswell rPGA EDS

JCPU1D

ME@

JCPU1D

DDRB_DQ[0..63]<12>

DDRB_DQ0 DDRB_DQ1 DDRB_DQ2 DDRB_DQ3 DDRB_DQ4 DDRB_DQ5 DDRB_DQ6 DDRB_DQ7 DDRB_DQ8 DDRB_DQ9 DDRB_DQ10 DDRB_DQ11 DDRB_DQ12 DDRB_DQ13 DDRB_DQ14 DDRB_DQ15 DDRB_DQ16 DDRB_DQ17 DDRB_DQ18 DDRB_DQ19 DDRB_DQ20 DDRB_DQ21 DDRB_DQ22 DDRB_DQ23 DDRB_DQ24 DDRB_DQ25 DDRB_DQ26 DDRB_DQ27 DDRB_DQ28 DDRB_DQ29 DDRB_DQ30 DDRB_DQ31 DDRB_DQ32 DDRB_DQ33 DDRB_DQ34 DDRB_DQ35 DDRB_DQ36 DDRB_DQ37 DDRB_DQ38 DDRB_DQ39 DDRB_DQ40 DDRB_DQ41 DDRB_DQ42 DDRB_DQ43 DDRB_DQ44 DDRB_DQ45 DDRB_DQ46 DDRB_DQ47 DDRB_DQ48 DDRB_DQ49 DDRB_DQ50 DDRB_DQ51 DDRB_DQ52 DDRB_DQ53 DDRB_DQ54 DDRB_DQ55 DDRB_DQ56 DDRB_DQ57 DDRB_DQ58 DDRB_DQ59 DDRB_DQ60 DDRB_DQ61 DDRB_DQ62 DDRB_DQ63

AR18 AT18 AM17 AM18 AR17 AT17 AN17 AN18 AT12 AR12 AN12 AM11 AT11 AR11 AM12 AN11

AR5 AR6 AM5 AM6 AT5 AT6 AN5 AN6

AK4

AM1 AN1 AK2 AK1

G10

D15

D14

AJ4

AJ1 AJ2

L2

M2

L4

M4

L1

M1

L5 M5 G7

J8 G8 G9

J7

J9

J10

A8

B8

A9

B9 D8

E8 D9

E9

E15

A15 B15 E14

A14 B14

ME@

SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63

INTEL_HASWELL_HASWELL

Haswell rPGA EDS

SB_CKE_0

SB_CKE_1

SB_CKE_2

SB_CKE_3

SB_CS_N_0 SB_CS_N_1 SB_CS_N_2 SB_CS_N_3

SB_ODT_0 SB_ODT_1 SB_ODT_2 SB_ODT_3

SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14 SB_MA_15

SB_DQS_N_0 SB_DQS_N_1 SB_DQS_N_2 SB_DQS_N_3 SB_DQS_N_4 SB_DQS_N_5 SB_DQS_N_6 SB_DQS_N_7 SB_DQS_P_0 SB_DQS_P_1 SB_DQS_P_2 SB_DQS_P_3 SB_DQS_P_4 SB_DQS_P_5 SB_DQS_P_6 SB_DQS_P_7

4 OF 9

RSVD_2

SB_CKN0

SB_CK0

SB_CKN1

SB_CK1

SB_CKN2

SB_CK2

SB_CKN3

SB_CK3

SB_BS_0 SB_BS_1 SB_BS_2

VSS_2

SB_RAS

SB_WE

SB_CAS

SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9

AG8 Y4 AA4 AF10 Y3 AA3 AG10 Y2 AA2 AG9 Y1 AA1 AF9

P4 R2 P3 P1

R4 R3 R1 P2 R7 P8 AA9

R10 R6 P6 P7

R8 Y5 Y10 AA5 Y7 AA6 Y6 AA7 Y8 AA10 R9 Y9 AF7 P9 AA8 AG7

AP18 AP11 AP5 AJ3 L3 H9 C8 C14 AP17 AP12 AP6 AK3 M3 H8 C9 C15

DDRB_CLK0# DDRB_CLK0 DDRB_CKE0 DDRB_CLK1# DDRB_CLK1 DDRB_CKE1

DDRB_CS0# DDRB_CS1#

DDRB_ODT0 DDRB_ODT1

DDRB_BS0# DDRB_BS1# DDRB_BS2#

DDRB_RAS# DDRB_WE# DDRB_CAS#

DDRB_MA0 DDRB_MA1 DDRB_MA2 DDRB_MA3 DDRB_MA4 DDRB_MA5 DDRB_MA6 DDRB_MA7 DDRB_MA8 DDRB_MA9 DDRB_MA10 DDRB_MA11 DDRB_MA12 DDRB_MA13 DDRB_MA14 DDRB_MA15

DDRB_DQS#0 DDRB_DQS#1 DDRB_DQS#2 DDRB_DQS#3 DDRB_DQS#4 DDRB_DQS#5 DDRB_DQS#6 DDRB_DQS#7

DDRB_DQS0 DDRB_DQS1 DDRB_DQS2 DDRB_DQS3 DDRB_DQS4 DDRB_DQS5 DDRB_DQS6 DDRB_DQS7

DDRB_CLK0# <12> DDRB_CLK0 <12> DDRB_CKE0 <12> DDRB_CLK1# <12> DDRB_CLK1 <12> DDRB_CKE1 <12>

DDRB_CS0# <12> DDRB_CS1# <12>

DDRB_ODT0 <12> DDRB_ODT1 <12>

DDRB_BS0# <12> DDRB_BS1# <12> DDRB_BS2# <12>

DDRB_RAS# <12>DDRA_MA[0..15] <11> DDRB_WE# <12> DDRB_CAS# <12>

DDRB_MA[0..15] <12>

DDRB_DQS#[0..7] <12>

DDRB_DQS[0..7] <12>

A A

+VREF_DQA_M3 +VREF_DQB_M3

1

CC45

0.1U_0402_25V6-K

2

1

CC46

0.1U_0402_25V6-K

2

ESD

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/12/05

LC Future Center Secret Data

Deciphered Date

2

2014/12/05

Title

CPU_DDR3 INTERFACE

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

E440 NM-A151

E440 NM-A151E440 NM-A151

1

7 57

of

1.0

5

4

3

2

1

Haswell rPGA EDS

JCPU1H

ME@

JCPU1H

To HDMI

CPU_HDMI_TX2-<34> CPU_HDMI_TX2+<34>

D D

CPU_HDMI_TX1-<34> CPU_HDMI_TX1+<34> CPU_HDMI_TX0-<34> CPU_HDMI_TX0+<34> CPU_HDMI_CLK-<34> CPU_HDMI_CLK+<34>

CPU_DOCK_TX0-<42> CPU_DOCK_TX0+<42> CPU_DOCK_TX1-<42> CPU_DOCK_TX1+<42>

CPU_HDMI_TX2CPU_HDMI_TX2+ CPU_HDMI_TX1CPU_HDMI_TX1+ CPU_HDMI_TX0CPU_HDMI_TX0+ CPU_HDMI_CLKCPU_HDMI_CLK+

CPU_DOCK_TX0CPU_DOCK_TX0+ CPU_DOCK_TX1CPU_DOCK_TX1+

Docking DP

C C

ME@

T28

DDIB_TXBN_0

U28

DDIB_TXBP_0

T30

DDIB_TXBN_1

U30

DDIB_TXBP_1

U29

DDIB_TXBN_2

V29

DDIB_TXBP_2

U31

DDIB_TXBN_3

V31

DDIB_TXBP_3

T34

DDIC_TXCN_0

U34

DDIC_TXCP_0

U35

DDIC_TXCN_1

V35

DDIC_TXCP_1

U32

DDIC_TXCN_2

T32

DDIC_TXCP_2

U33

DDIC_TXCN_3

V33

DDIC_TXCP_3

P29

DDID_TXDN_0

R29

DDID_TXDP_0

N28

DDID_TXDN_1

P28

DDID_TXDP_1

P31

DDID_TXDN_2

R31

DDID_TXDP_2

N30

DDID_TXDN_3

P30

DDID_TXDP_3

INTEL_HASWELL_HASWELL

eDP

EDP_AUXN

EDP_RCOMP

EDP_DISP_UTIL

EDP_TXN_0 EDP_TXP_0 EDP_TXN_1 EDP_TXP_1

8 OF 9

EDP_AUXP

EDP_HPD

FDI_TXN_0 FDI_TXP_0 FDI_TXN_1 FDI_TXP_1

DDI

M27

CPU_EDP_AUX#

N27

CPU_EDP_AUX

P27

EDP_HPD_IN#

E24

EDP_COMP

R27

1

T10 @T10 @

P35

CPU_EDP_TX0-

R35

CPU_EDP_TX0+

N34

CPU_EDP_TX1- EDP_HPD_IN#

P34

CPU_EDP_TX1+

P33

FDI_CTX_PRX_N0

R33

FDI_CTX_PRX_P0

N32

FDI_CTX_PRX_N1

P32

FDI_CTX_PRX_P1

COMPENSATION PU FOR eDP CAD Note:Trace width=20 mils, Spacing=25mil, Max length=100 mils.

CPU_EDP_AUX# <36> CPU_EDP_AUX <36>

1 2

RC25 24.9_0402_1%RC25 24.9_0402_1%

CPU_EDP_TX0- <36> CPU_EDP_TX0+ <36> CPU_EDP_TX1- <36> CPU_EDP_TX1+ <36> FDI_CTX_PRX_N0 <15> FDI_CTX_PRX_P0 <15> FDI_CTX_PRX_N1 <15> FDI_CTX_PRX_P1 <15>

+VCCIOA_OUT

To eDP Panel

HPD INVERSION FOR EDP

CPU_EDP_HPD<36>

CPU_EDP_HPD

12

RC27

RC27 100K_0402_5%

100K_0402_5%

+VCCIO_OUT

12

RC26

RC26 10K_0402_5%

10K_0402_5%

13

D

2

G

S

It is an output from eDP sink device and it is a active high signal. However, the HPD processor input is a low voltage active low signal.

Pull up resistor on DP_HPD modified to 10kOhms from 1kOhms .

QC1

QC1 BSS138_NL_SOT23-3

BSS138_NL_SOT23-3

SB50138002J 2nd --> SB50138000T

CFG STRAPS For CPU

Haswell rPGA EDS

JCPU1I

ME@

JCPU1I

ME@

AT1

RSVD_TP_5

AT2

RSVD_TP_6

AD10

RSVD_17

A34

RSVD_TP_7

A35

RSVD_TP_8

W29

RSVD_TP_9

RC33

1 2

49.9_0402_1%

+VCC_CORE

B B

RC34

1 2

49.9_0402_1%

A A

T34@T34@

T41@T41@

CPU_TESTLO_G26

+VCC_CORE

CPU_TESTLO_W34

CFG2

1

CFG3 CFG4 CFG5 CFG6 CFG7

1

CFG9

W28

RSVD_TP_10

G26

TESTLO_G26

W33

RSVD_18

AL30

RSVD_19

AL29

RSVD_20

F25

VCC

C35

RSVD_TP_11

B35

RSVD_TP_12

AL25

RSVD_TP_13

W30

RSVD_TP_14

W31

RSVD_TP_15

W34

TESTLO

AT20

CFG_0

AR20

CFG_1

AP20

CFG_2

AP22

CFG_3

AT22

CFG_4

AN22

CFG_5

AT25

CFG_6

AN23

CFG_7

AR24

CFG_8

AT23

CFG_9

AN20

CFG_10

AP24

CFG_11

AP26

CFG_12

AN25

CFG_13

AN26

CFG_14

AP25

CFG_15

INTEL_HASWELL_HASWELL

9 OF 9

RSVD_TP_16 RSVD_TP_17 RSVD_TP_18 RSVD_TP_19

CFG_RCOMP

RSVD_TP_20

RSVD_TP_21 RSVD_TP_22

CFG_16 CFG_18 CFG_17 CFG_19

RSVD_21

FC_G6 RSVD_22 RSVD_23 RSVD_24 RSVD_25 RSVD_26

RSVD_27

RSVD_28 RSVD_29

RSVD_30

RSVD_31 RSVD_32

VSS_342 VSS_343

C23 B23 D24 D23

AT31 AR21 AR23 AP21 AP23

AR33 G6 AM27 AM26 F5 AM2 K6

E18

U10 P10

B1

NC

A2 AR1

E21 E20

AP27 AR26

AL31 AL32

12

RC44

@ RC44

@

2K_0402_1%

12

RC45

@ RC45

@

1K_0402_1%

CPU_CFG_RCOMP

PCH_PWROK

RC35

12

49.9_0402_1%

PCH_PWROK <15,48>

(CFG[17:0] internal pull high 5～～～～15K to VCCIO)

PEG Static Lane Reversal - CFG2 is for the 16x

1: (Default) Normal Operation;

*

CFG2

Display Port Presence Strap

CFG4

PCIE Port Bifurcation Straps

CFG[6:5]

PEG DEFER TRAINING

CFG7

Lane# definition matches socket pin map definition 0: Lane Reversed

1 : Disabled No Physical Display Port attached to Embedded Display Port 0 : Enabled;

*

An external Display Port device is connected to the Embedded Display Port

11 : Func 1 Disabled, Func 2 Disabled (x16,---,---) 10 : Func 1 Enabled, Func 2 Disabled (x8,x8,---)

*

01 : Func 1 Disabled, Func 2 Enabled 00 : Func 1 Enabled, Func 2 Enabled (x8,x4,x4)

1: (Default)

*

PEG Train Immediately Following XXRESETB Deassertion 0 : PEG Wait for BIOS for Training

CFG2

CFG4

CFG5

CFG6

CFG7

1 2

RC28 1K_0402_1%@RC28 1K_0402_1%@

1 2

RC29 1K_0402_1%RC29 1K_0402_1%

1 2

RC30 1K_0402_1%@RC30 1K_0402_1%@

1 2

RC31 1K_0402_1%@RC31 1K_0402_1%@

1 2

RC32 1K_0402_1%@RC32 1K_0402_1%@

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/12/05

LC Future Center Secret Data

Deciphered Date

2

2014/12/05

Title

CPU_eDP/DDI/RSVD/CFG

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

E440 NM-A151

E440 NM-A151E440 NM-A151

1

8 57

of

1.0

5

4

3

2

1

AA26 AA28 AA34 AA30 AA32 AB26 AB29 AB25 AB27 AB28 AB30 AB31 AB33 AB34 AB32 AC26 AB35 AC28 AD25 AC30 AD28 AC32 AD31 AC34 AD34 AD26 AD27 AD29 AD30 AD32 AD33 AD35 AE26 AE32 AE28 AE30 AG28 AG34 AE34 AF25 AF26 AF27 AF28 AF29 AF30 AF31 AF32 AF33 AF34 AF35 AG26 AH26 AH29 AG30 AG32 AH32 AH35 AH25 AH27 AH28 AH30 AH31 AH33 AH34 AJ25 AJ26 AJ27 AJ28 AJ29 AJ30 AJ31 AJ32 AJ33 AJ34 AJ35 G25 H25 J25 K25 L25 M25 N25 P25 R25 T25

U25 U26 V25 V26

W26 W27

+VCC_CORE

Haswell rPGA EDS

JCPU1E

ME@

JCPU1E

CPU VDDQ DECOUPLING

D D

C C

+1.35V

CC18

CC28

CC19

10U_0603_6.3V6-M

1

2

CC29

22U_0805_6.3V6-M

1

2

CC21

CC20

10U_0603_6.3V6-M

1

2

CC31

CC30

22U_0805_6.3V6-M

1

2

CC23

CC22

10U_0603_6.3V6-M

22U_0805_6.3V6-M

CC32

1

2

CC33

22U_0805_6.3V6-M

1

2

CC25

CC24

10U_0603_6.3V6-M

1

2

CC35

CC34

22U_0805_6.3V6-M

1

2

CC27

CC26

10U_0603_6.3V6-M

22U_0805_6.3V6-M

CC36

1

2

CC39

CC38

CC37

22U_0805_6.3V6-M

1

2

1

2

CC39

CC40

330U_D2_2VM_R6M

22U_0805_6.3V6-M

330U_D2_2VM_R6M

1

+

@

2

+VCC_CORE

+1.35V

VDDQ Decoupling :

1. MB Bottom Socket Edge --> 2* 330uf, 6mΩ

2. 6x MB Bottom Socket Cavity --> 11* 22 μF (0805), 3mΩ 5x MB Top Socket Cavity

3. 5x MB Bottom Socket Cavity --> 10 x 10 μF (0805), 3mΩ 5x MB Top Socket Cavity

Reserve for VCCST

+1.05VS_PCH_VPROC

1 2

RC43 0_0402_5%@RC43 0_0402_5%@

1

CC42

@ CC42

@

4.7U_0603_6.3V6K

2

VR_SVID_ALRT#<64> VR_SVID_CLK<64> VR_SVID_DAT<64>

Pull high resistor on VR side

+VCCIO_OUT

+VCCIOA_OUT

1 2

RC36 43_0402_1%RC36 43_0402_1%

1 2

RC37 0_0402_5%RC37 0_0402_5%

1 2

RC38 0_0402_5%RC38 0_0402_5%

1 2

RC42 130_0402_1%RC42 130_0402_1%

VCCSENSE

+VCCST_A23

H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT

T54@ T54@

VCC/VSS SENSE

+VCC_CORE

B B

VCCSENSE<64>

VSSSENSE<10,64 >

12

RC39

RC39 100_0402_1%

100_0402_1%

12

RC41

RC41 100_0402_1%

100_0402_1%

Reserve 0-Ohm on Power Side

VCCSENSE

VSSSENSE

RC40

1 2

0_0603_5%

RESISTOR STUFFING OPTIONS ARE PROVIDED FOR TESTING PURPOSES

Close to CPU

+VCCIO_OUT+1.05VS

@

+VCC_CORE

K27

L27 T27 V27

AB11

AB2 AB5 AB8

AE11

AE2 AE5 AE8

AH11

K11 N11

N8

T11

T2 T5 T8

W11

W2 W5 W8

N26 K26

AL27

AK27

AL35

E17

AN35

A23 F22

W32

AL16

J27

AL13

AM28 AM29

AL28

AP35

1

H27

AP34 AT35 AR35 AR32

AL26

AT34

AL22 AT33 AM21 AM25 AM22 AM20 AM24

AL19 AM23 AT32

Y25 Y26 Y27 Y28 Y29 Y30 Y31 Y32 Y33 Y34 Y35

ME@

RSVD_3 RSVD_4 RSVD_5 RSVD_6

4.2A

VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 VDDQ_10 VDDQ_11 VDDQ_12 VDDQ_13 VDDQ_14 VDDQ_15 VDDQ_16 VDDQ_17 VDDQ_18 VDDQ_19 VDDQ_20

RSVD_7 VCC_1 RSVD_8 RSVD_9

VCC_SENSE RSVD_10

300mA

VCCIO_OUT RSVD_11

300mA

VCOMP_OUT RSVD_12 RSVD_13 RSVD_14 RSVD_15

VIDALERT VIDSCLK VIDSOUT

VSS_3 PWR_DEBUG VSS_4 RSVD_TP_1 RSVD_TP_2 RSVD_TP_3 RSVD_TP_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15

VCC_2 VCC_3 VCC_4 VCC_5 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12

INTEL_HASWELL_HASWELL

5 OF 9

57W, 95A 47W, 85A 37W, 55A

VCC_13 VCC_14 VCC_15 VCC_16 VCC_17 VCC_18 VCC_19 VCC_20 VCC_21 VCC_22 VCC_23 VCC_24 VCC_25 VCC_26 VCC_27 VCC_28 VCC_29 VCC_30 VCC_31 VCC_32 VCC_33 VCC_34 VCC_35 VCC_36 VCC_37 VCC_38 VCC_39 VCC_40 VCC_41 VCC_42 VCC_43 VCC_44 VCC_45 VCC_46 VCC_47 VCC_48 VCC_49 VCC_50 VCC_51 VCC_52 VCC_53 VCC_54 VCC_55 VCC_56 VCC_57 VCC_58 VCC_59 VCC_60 VCC_61 VCC_62 VCC_63 VCC_64 VCC_65 VCC_66 VCC_67 VCC_68 VCC_69 VCC_70 VCC_71 VCC_72 VCC_73 VCC_74 VCC_75 VCC_76 VCC_77 VCC_78 VCC_79 VCC_80 VCC_81 VCC_82 VCC_83 VCC_84 VCC_85 VCC_86 VCC_87 VCC_88 VCC_89 VCC_90 VCC_91 VCC_92 VCC_93 VCC_94 VCC_95 VCC_96 VCC_97

VCC_98

VCC_99 VCC_100 VCC_101

VCC_102 VCC_103

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/12/05

LC Future Center Secret Data

Deciphered Date

2

2014/12/05

Title

CPU_POWER

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

E440 NM-A151

E440 NM-A151E440 NM-A151

1

9 57

of

1.0

5

4

3

2

1

D D

C C

B B

AA11 AA25 AA27 AA31 AA29

AB10 AA33 AA35

AC25 AC27

AC11 AD11 AC29 AC31 AC33 AC35

AD7

AE1 AE10 AE25 AE29

AE3 AE27 AE35

AE4

AE6

AE7

AE9 AF11

AF6

AF8 AG11 AG25 AE31 AG31 AE33

AG6

AH1 AH10

AH2 AG27 AG29

AH3 AG33 AG35

AH4

AH5

AH6

AH7

AH8

AH9 AJ11

AK11 AK25 AK26 AK28 AK29 AK30 AK32

A10 A13 A16 A19 A22 A25 A27 A29

A3 A31 A33

A4

A7

AB1

AB3

AB4 AB6 AB7 AB9

AJ5

E19

Haswell rPGA EDS

JCPU1F

VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105

INTEL_HASWELL_HASWELL

ME@

6 OF 9

VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184

AK34 AK5 AL1 AL10 AL11 AL12 AL14 AL15 AL17 AL18 AL2 AL20 AL21 AL23 E22 AL3 AL4 AL5 AL6 AL7 AL8 AL9 AM10 AM13 AM16 AM19 E25 AM32 AM4 AM7 AN10 AN13 AN16 AN19 AN2 AN21 AN24 AN27 AN30 AN34 AN4 AN7 AP1 AP10 AP13 AP16 AP19 AP4 AP7 W25 AR10 AR13 AR16 AR19 AR2 AR22 AR25 AR28 AR31 AR34 AR4 AR7 AT10 AT13 AT16 AT19 AT21 AT24 AT27 AT3 AT30 AT4 AT7 B10 B13 B16 B19 B2 B22

Haswell rPGA EDS

JCPU1G

B34

VSS_185

B4

VSS_186

B7

VSS_187

C1

VSS_188

C10

VSS_189

C13

VSS_190

C16

VSS_191

C19

VSS_192

C2

VSS_193

C22

VSS_194

C24

VSS_195

C26

VSS_196

C28

VSS_197

C30

VSS_198

C32

VSS_199

C34

VSS_200

C4

VSS_201

C7

VSS_202

D10

VSS_203

D13

VSS_204

D16

VSS_205

D19

VSS_206

D22

VSS_207

D25

VSS_208

D27

VSS_209

D29

VSS_210

D31

VSS_211

D33

VSS_212

D35

VSS_213

D4

VSS_214

D7

VSS_215

E1

VSS_216

E10

VSS_217

E13

VSS_218

E16

VSS_219

E4

VSS_220

E7

VSS_221

F10

VSS_222

F11

VSS_223

F12

VSS_224

F14

VSS_225

F15

VSS_226

F17

VSS_227

F18

VSS_228

F20

VSS_229

F21

VSS_230

F23

VSS_231

F24

VSS_232

F26

VSS_233

F28

VSS_234

F30

VSS_235

F32

VSS_236

F34

VSS_237

F4

VSS_238

F6

VSS_239

F7

VSS_240

F8

VSS_241

F9

VSS_242

G1

VSS_243

G11

VSS_244

G2

VSS_245

G27

VSS_246

G29

VSS_247

G3

VSS_248

G31

VSS_249

G33

VSS_250

G35

VSS_251

G4

VSS_252

G5

VSS_253

H10

VSS_254

H26

VSS_255

H6

VSS_256

H7

VSS_257

J11

VSS_258

J26

VSS_259

J28

VSS_260

J30

VSS_261

J32

VSS_262

J34

VSS_263

J6

VSS_264

K1

VSS_265

INTEL_HASWELL_HASWELL

ME@

VSS_SENSE

RSVD_17

VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325 VSS_326 VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341

7 OF 9

K10 K2 K29 K3 K31 K33 K35 K4 K5 K7 K8 K9 L11 L26 L6 M11 M26 M28 M30 M32 M34 M6 N1 N10 N2 N29 N3 N31 N33 N35 N4 N5 N6 N7 N9 P11 P26 P5 R11 R26 R28 R30 R32 R34 R5 T1 T10 T29 T3 T31 T33 T35 T4 T6 T7 T9 U11 U27 V11 V28 V30 V32 V34 W1 W10 W3 W35 W4 W6 W7 W9 Y11 H11 AL24 F19 T26 AK35 AK33

VSSSENSE

VSSSENSE <64 ,9>

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/12/05

LC Future Center Secret Data

Deciphered Date

2

2014/12/05

Title

CPU_GND

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

E440 NM-A151

E440 NM-A151E440 NM-A151

1

10 57

of

1.0

5

DDR3 SO-DIMM A

3A@1.5V

D D

C C

B B

A A

+VREF_DQA

CD1

Close to JDDR3H.1

DDRA_CKE0<7>

DDRA_BS2#<7>

DDRA_CLK0<7> DDRA_CLK0#<7>

DDRA_BS0#<7>

DDRA_WE#<7> DDRA_CAS#<7>

DDRA_CS1#<7>

SPD setting (SA0, SA1) PU/PD by Channel A/B

->Channel A 00

->Channel B 01

+3VS

CD22

2.2U_0603_6.3V6-K

1

2

CD2

0.1U_0402_10V7-K

1

2

5

1

2

2.2U_0402_6.3V6-M

1

CD23

0.1U_0402_10V6-K

2

DDRA_DQ0 DDRA_DQ1

DDRA_DQ2 DDRA_DQ3

DDRA_DQ8 DDRA_DQ9

DDRA_DQS#1 DDRA_DQS1

DDRA_DQ10 DDRA_DQ11

DDRA_DQ16 DDRA_DQ17

DDRA_DQS#2 DDRA_DQS2

DDRA_DQ18 DDRA_DQ19

DDRA_DQ24 DDRA_DQ25

DDRA_DQ26 DDRA_DQ27

DDRA_CKE0

DDRA_BS2#

DDRA_MA12 DDRA_MA9

DDRA_MA8 DDRA_MA5

DDRA_MA3 DDRA_MA1

DDRA_CLK0 DDRA_CLK0#

DDRA_MA10 DDRA_BS0#

DDRA_WE# DDRA_CAS# DDRA_ODT0

DDRA_MA13 DDRA_CS1#

DDRA_DQ32 DDRA_DQ33

DDRA_DQS#4 DDRA_DQS4

DDRA_DQ34 DDRA_DQ35

DDRA_DQ40 DDRA_DQ41

DDRA_DQ42 DDRA_DQ43

DDRA_DQ48 DDRA_DQ49

DDRA_DQS#6 DDRA_DQS6

DDRA_DQ50 DDRA_DQ51

DDRA_DQ56 DDRA_DQ57

DDRA_DQ58 DDRA_DQ59

RD1

1 2

10K_0402_5%

12

RD2

RD2 10K_0402_5%

10K_0402_5%

JDIMM1

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET# VSS1131VSS12

33

DQ10

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

TYCO_2-2013287-1

ME@JDIMM1

ME@

VSS3

DQS#0

DQS0

VSS6

VSS8 DQ12 DQ13

VSS10

DQ14 DQ15

DQ20 DQ21

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

VTT2

DQ4 DQ5

DQ6 DQ7

DM1

DM2

CK1

BA1

NC2

DM4

DM6

SDA SCL

4

+1.35V+1.35V

2 4

DDRA_DQ4

6

DDRA_DQ5

8 10

DDRA_DQS#0

12

DDRA_DQS0

14 16

DDRA_DQ6

18

DDRA_DQ7

20 22

DDRA_DQ12

24

DDRA_DQ13

26 28 30

DDR3_DRAMRST#

32 34

DDRA_DQ14

36

DDRA_DQ15

38 40

DDRA_DQ20

42

DDRA_DQ21

44 46 48 50

DDRA_DQ22

52

DDRA_DQ23

54 56

DDRA_DQ28

58

DDRA_DQ29

60 62

DDRA_DQS#3

64

DDRA_DQS3

66 68

DDRA_DQ30

70

DDRA_DQ31

72

74

DDRA_CKE1

76 78

A15 A14

A11

A7

A6 A4

A2 A0

S0#

G2

DDRA_MA15

80

DDRA_MA14

82 84

DDRA_MA11

86

DDRA_MA7

88 90

DDRA_MA6

92

DDRA_MA4

94 96

DDRA_MA2

98

DDRA_MA0

100 102

DDRA_CLK1

104

DDRA_CLK1#

106 108

DDRA_BS1#

110

DDRA_RAS#

112 114

DDRA_CS0#

116 118 120

DDRA_ODT1

122 124 126 128 130

DDRA_DQ36

132

DDRA_DQ37

134 136 138 140

DDRA_DQ38

142

DDRA_DQ39

144 146

DDRA_DQ44

148

DDRA_DQ45

150 152

DDRA_DQS#5

154

DDRA_DQS5

156 158

DDRA_DQ46

160

DDRA_DQ47

162 164

DDRA_DQ52

166

DDRA_DQ53

168 170 172 174

DDRA_DQ54

176

DDRA_DQ55

178 180

DDRA_DQ60

182

DDRA_DQ61

184 186

DDRA_DQS#7

188

DDRA_DQS7

190 192

DDRA_DQ62

194

DDRA_DQ63

196 198 200

PM_SMBDATA

202

PM_SMBCLK

204

206

4

0.65A@0.75V

0.65A@0.75V0.65A@0.75V

DDR3_DRAMRST# <12,6>

DDRA_CKE1 <7>

DDRA_CLK1 <7> DDRA_CLK1# <7>

DDRA_BS1# <7> DDRA_RAS# <7>

DDRA_CS0# <7> DDRA_ODT0 <7>

DDRA_ODT1 <7>

1

CD20

2

0.1U_0402_10V7-K

close to JDDR3L.126

PM_SMBDATA <12,17,39,43> PM_SMBCLK <12,17,39,43>

+0.675VS

CD21

1

2

3

2

DDR Decoupling

+1.35V

CD3

CD4

1U_0402_6.3V6-K

1

2

1U_0402_6.3V6-K

1

2

CD5

CD6

Layout Note :

1U_0402_6.3V6-K

1

2

1. Placed near JDDR3L

2

2. Place these 4 Caps near Command and Control signals of DIMMA

CD8

CD9

CD17

CD9

10U_0603_6.3V6-M

1

2

1

2

10U_0603_6.3V6-M

1

2

CD18

1U_0402_6.3V6-K

1

2

2014/12/05

2

CD7

10U_0603_6.3V6-M

1

2

+0.675VS

CD16

1U_0402_6.3V6-K

1

+V_SM_VREF_CNT

2.2U_0402_6.3V6-M

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/12/05

2

LC Future Center Secret Data

Deciphered Date

CD11

CD10

CD19

1

2

1

2

10U_0603_6.3V6-M

1

2

Layout Note : Placed near

1U_0402_6.3V6-K

JDDR3L1.Pin203, 204

1

DDRA_DQ[0..63] <7>

DDRA_DQS[0..7] <7>

DDRA_DQS#[0..7] <7>

DDRA_MA[0..15] <7>

1uF *4, 10uF *7, 330uF *1

CD15

CD13

CD14

CD12

10U_0603_6.3V6-M

1

2

Title

DDR3 SO-DIMMA/1

Size Document Number Rev

Custom

Date: Sheet

CD14

10U_0603_6.3V6-M

1

2

Thursday, July 11, 2013

10U_0603_6.3V6-M

1

2

CD15

330U_D2_2VM_R9M

1

+

2

E440 NM-A151

E440 NM-A151E440 NM-A151

1

11 57

of

1.0

5

DDR3 SO-DIMM B

+1.35V +1.35V

3A@1.5V

JDIMM2

ME@

+VREF_DQB

1

D D

CD25

1

CD24

2

0.1U_0402_10V7-K

2.2U_0402_6.3V6-M

Close to JDDR3L.1

C C

DDRB_CKE0<7>

DDRB_BS2#<7>

DDRB_CLK0<7> DDRB_CLK0#<7>

DDRB_BS0#<7>

DDRB_WE#<7> DDRB_CAS#<7>

DDRB_CS1#<7>

B B

SPD setting (SA0, SA1) PU/PD by Channel A/B

A A

->Channel A 00

->Channel B 01

+3VS

2.2U_0603_6.3V6-K

CD48

1

2

5

1

CD49

0.1U_0402_10V6-K

2

DDRB_DQ0 DDRB_DQ1

DDRB_DQ2 DDRB_DQ3

DDRB_DQ8 DDRB_DQ9

DDRB_DQS#1 DDRB_DQS1

DDRB_DQ10 DDRB_DQ11

DDRB_DQ16 DDRB_DQ17

DDRB_DQS#2 DDRB_DQS2

DDRB_DQ18 DDRB_DQ19

DDRB_DQ24 DDRB_DQ25

DDRB_DQ26 DDRB_DQ27

DDRB_CKE0

DDRB_BS2#

DDRB_MA12 DDRB_MA9

DDRB_MA8 DDRB_MA5

DDRB_MA3 DDRB_MA1

DDRB_CLK0 DDRB_CLK0#

DDRB_MA10 DDRB_BS0#

DDRB_WE# DDRB_CAS#

DDRB_MA13 DDRB_CS1#

DDRB_DQ32 DDRB_DQ33

DDRB_DQS#4 DDRB_DQS4

DDRB_DQ34 DDRB_DQ35

DDRB_DQ40 DDRB_DQ41

DDRB_DQ42 DDRB_DQ43

DDRB_DQ48 DDRB_DQ49

DDRB_DQS#6 DDRB_DQS6

DDRB_DQ50 DDRB_DQ51

DDRB_DQ56 DDRB_DQ57

DDRB_DQ58 DDRB_DQ59

1 2

RD14

10K_0402_5%

1 2

RD16

10K_0402_5%

11 13 15 17 19 21 23 25 27

33 35

39 41

45 47 49 51 53 55 57 59

63

67 69

73 75 77 79 81 83 85 87 89 91 93 95 97

99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203

205

ME@

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS129RESET# VSS1131VSS12 DQ10 DQ11 VSS1337VSS14 DQ16 DQ17 VSS1543VSS16 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS2261DQS#3 DM3 VSS2365VSS24 DQ26 DQ27 VSS2571VSS26

CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1

G1

LCN_DAN06-K4806-0103

DQS#0

VSS10

VSS17

VSS19

VSS21

VDD10

VDD12

VDD14

VDD16

VDD18

VREF_CA

VSS28

VSS30

VSS31

VSS33

VSS35 DQS#5

VSS38

VSS40

VSS42

VSS43

VSS45

VSS47 DQS#7

VSS50

VSS52

EVENT#

DQ4 DQ5

VSS3

DQS0

VSS6

DQ6 DQ7

VSS8 DQ12 DQ13

DM1

DQ14 DQ15

DQ20 DQ21

DM2

DQ22 DQ23

DQ28 DQ29

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

CK1#

RAS#

ODT0

ODT1

DQ36 DQ37

DM4

DQ38 DQ39

DQ44 DQ45

DQS5

DQ46 DQ47

DQ52 DQ53

DM6

DQ54 DQ55

DQ60 DQ61

DQS7

DQ62 DQ63

SDA

VTT2

CK1

BA1

NC2

SCL

4

2 4

DDRB_DQ4

6

DDRB_DQ5

8 10

DDRB_DQS#0

12

DDRB_DQS0

14 16

DDRB_DQ6

18

DDRB_DQ7

20 22

DDRB_DQ12

24

DDRB_DQ13

26 28 30

DDR3_DRAMRST#

32 34

DDRB_DQ14

36

DDRB_DQ15

38 40

DDRB_DQ20

42

DDRB_DQ21

44 46 48 50

DDRB_DQ22

52

DDRB_DQ23

54 56

DDRB_DQ28

58

DDRB_DQ29

60 62

DDRB_DQS#3

64

DDRB_DQS3

66 68

DDRB_DQ30

70

DDRB_DQ31

72

74

DDRB_CKE1

76 78

A15 A14

A11

A7

A6 A4

A2 A0

S0#

G2

DDRB_MA15

80

DDRB_MA14

82 84

DDRB_MA11

86

DDRB_MA7

88 90

DDRB_MA6

92

DDRB_MA4

94 96

DDRB_MA2

98

DDRB_MA0

100 102

DDRB_CLK1

104

DDRB_CLK1#

106 108

DDRB_BS1#

110

DDRB_RAS#

112 114

DDRB_CS0#

116

DDRB_ODT0

118 120

DDRB_ODT1

122 124 126 128 130

DDRB_DQ36

132

DDRB_DQ37

134 136 138 140

DDRB_DQ38

142

DDRB_DQ39

144 146

DDRB_DQ44

148

DDRB_DQ45

150 152

DDRB_DQS#5

154

DDRB_DQS5

156 158

DDRB_DQ46

160

DDRB_DQ47

162 164

DDRB_DQ52

166

DDRB_DQ53

168 170 172 174

DDRB_DQ54

176

DDRB_DQ55

178 180

DDRB_DQ60

182

DDRB_DQ61

184 186

DDRB_DQS#7

188

DDRB_DQS7

190 192

DDRB_DQ62

194

DDRB_DQ63

196 198 200

PM_SMBDATA

202

PM_SMBCLK

204

206

0.65A@0.75V

0.65A@0.75V0.65A@0.75V

4

DDR3_DRAMRST# <11,6>

DDRB_CKE1 <7>

DDRB_CLK1 <7> DDRB_CLK1# <7>

DDRB_BS1# <7> DDRB_RAS# <7>

DDRB_CS0# <7> DDRB_ODT0 <7>

DDRB_ODT1 <7>

1

CD44

CD43

2

0.1U_0402_10V7-K

2.2U_0402_6.3V6-M

Close to JDDR3H.126

PM_SMBDATA <11,17,39,43> PM_SMBCLK <11,17,39,43>

+0.675VS

+V_SM_VREF_CNT

3

2

DDR Decoupling

+1.35V

CD26

CD27

CD28

CD29

1U_0402_6.3V6-K

1

2

1U_0402_6.3V6-K

1

2

Layout Note :

1U_0402_6.3V6-K

1

1. Placed near JDDR3H

2

2. Place these 4 Caps near Command and Control signals of DIMMA

CD30

CD31

CD32

CD33

CD34

CD35

10U_0603_6.3V6-M

1

2

CD42

1U_0402_6.3V6-K

1

2

+0.675VS

CD39

1

2

CD41

CD40

1U_0402_6.3V6-K

1

2

1U_0402_6.3V6-K

1

2

All VREF traces should have 20 mil trace width

+1.35V

12

+VREF_DQA_M3

RD6

1 2

1

2_0402_1%

CD45

0.022U_0402_25V7-K

2

12

RD15

24.9_0402_1%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

12

2012/12/05

+VREF_DQA +1.35V

RD3

RD3 1K_0402_0.5%

1K_0402_0.5%

RD9

RD9 1K_0402_0.5%

1K_0402_0.5%

LC Future Center Secret Data

+VREF_DQB_M3

Deciphered Date

RD7

1 2

1

2_0402_1%

CD46

0.022U_0402_25V7-K

2

12

RD12

24.9_0402_1%

2

12

RD4

RD4 1K_0402_0.5%

1K_0402_0.5%

12

RD10

RD10 1K_0402_0.5%

1K_0402_0.5%

2014/12/05

CD35

10U_0603_6.3V6-M

1

2

Layout Note : Placed near JDDR3H.Pin203, 204

+VREF_DQB +1.35V

1

DDRB_DQ[0..63] <7>

DDRB_DQS[0..7] <7>

DDRB_DQS#[0..7] <7>

DDRB_MA[0..15] <7>

1uF *4, 10uF *7, 330uF *1

CD38

CD36

CD37

10U_0603_6.3V6-M

1

2

+V_SM_VREF

1

CD47

0.022U_0402_25V7-K

2

12

RD13

24.9_0402_1%

Thursday, July 11, 2013

CD37

10U_0603_6.3V6-M

1

2

RD8

1 2

2_0402_1%

10U_0603_6.3V6-M

1

2

Title

DDR3 SO-DIMMB/2

Size Document Number Rev

Custom

Date: Sheet

CD38

330U_D2_2VM_R9M

1

+

2

12

RD5

RD5 1K_0402_0.5%

1K_0402_0.5%

12

RD11

RD11 1K_0402_0.5%

1K_0402_0.5%

E440 NM-A151

E440 NM-A151E440 NM-A151

1

12 57

+V_SM_VREF_CNT

of

1.0

5

4

3

2

1

JCMOS, JME Setting, Need Under DDR Door

+RTCVCC

D D

1

CH9

CH9 18P_0402_50V8-J

18P_0402_50V8-J

2

C C

RH1

1 2

20K_0402_5%

1 2

20K_0402_5%

1 2

10M_0402_5%

1 2

32.768KHZ_12.5PF_9H03200019

SJ10000DM0J

Y_CM31532768DZFT_2P

PCH_RTCRST#

RH4

PCH_SRTCRST#

RH3

YH1

JCMOS1 @JCMOS1 @

1 2

CH1 1U_0603_10V6-KCH1 1U_0603_10V6-K

JME1 @JME1 @

1 2

CH2 1U_0603_10V6-KCH2 1U_0603_10V6-K

PCH_RTCX1

PCH_RTCX2

1

CH10

CH10 18P_0402_50V8-J

18P_0402_50V8-J

2

1. INTVRMEN, should always be pull high HIntegrated VRM enable (Default)

*

LIntegrated VRM disable

2. Internal Voltage Regulator Enable: This signal enables the internal 1.05 V regulators.

+RTCVCC

ME_FLASH<48>

EC_WAKE#<48>

During Reset", Immediately after Reset and S3/S4/S5

1. JTAG_TDI, JTAG_TMS --> Int. PU 20K

2. JTAG_TCK --> Int. PD 20K

3. JTAG_TDO --> High-Z

+3V_PCH

1 2

RH5 1M_0402_5%RH5 1M_0402_5%

1 2

RH2 330K_0402_5%RH2 330K_0402_5%

HDA_SDIN0<46>

1 2

RH6 0_0402_5%RH6 0_0402_5%

1 2

RH7 10K_0402_5%RH7 10K_0402_5%

LPT_PCH_M_EDS

UH1A

PCH_RTCX1

PCH_RTCX2

PCH_SRTCRST#

SM_INTRUDER#

PCH_INTVRMEN

PCH_RTCRST#

HDA_BCLK

HDA_SYNC

HDA_SPKR<47>

HDA_SPKR

HDA_RST#

HDA_SDIN0

HDA_SDOUTME_FLASH

EC_WAKE#

1

PCH_JTAG_TCK

T64@T64@

1

PCH_JTAG_TMS

T65@T65@

1

PCH_JTAG_TDI

T66@T66@

1

PCH_JTAG_TDO

T67@T67@

B5

RTCX1

B4

RTCX2

B9

SRTCRST#

A8

INTRUDER#

G10

INTVRMEN

D9

RTCRST#

B25

HDA_BCLK

A22

HDA_SYNC

AL10

SPKR

C24

HDA_RST#

L22

HDA_SDI0

K22

HDA_SDI1

G22

HDA_SDI2

F22

HDA_SDI3

A24

HDA_SDO

B17

DOCKEN#/GPIO33

C22

HDA_DOCK_RST#/GPIO13

AB3

JTAG_TCK

AD1

JTAG_TMS

AE2

JTAG_TDI

AD3

JTAG_TDO

F8

TP25

C26

TP22

AB6

TP20

LYNX-POINT-DH82LPMS_BGA695

SA00005U830

LPT_PCH_M_EDS

JTAGRTC AZALIA

REV = 5

1 OF 11

BC8

TP9

TP8

SATA_PRX_DTX_N0

BE8

SATA_PRX_DTX_P0

AW8

SATA_PTX_DRX_N0

AY8

SATA_PTX_DRX_P0

BC10

SATA_PRX_DTX_N1

BE10

SATA_PRX_DTX_P1

AV10

SATA_PTX_DRX_N1

AW10

SATA_PTX_DRX_P1

BB9

SATA_PRX_DTX_N2

BD9

SATA_PRX_DTX_P2

AY13

SATA_PTX_DRX_N2

AW13

SATA_PTX_DRX_P2

BC12 BE12

AR13 AT13

BD13 BB13

AV15 AW15

BC14 BE14

SATA Impedance Compensation :

AP15

--> Place the resistor within 500 mils of the PCH.

AR15

Avoid routing next to clock pins.

AY5

SATA_RCOMP

AP3

SATALED#

AT1

PCH_GPIO21

AU2

PCH_GPIO19

BD4

+1.5VS

BA2

BB2

SATA_RXN_0 SATA_RXP_0

SATA_TXN_0 SATA_TXP_0

SATA_RXN_1 SATA_RXP_1

SATA_TXN_1 SATA_TXP_1

SATA

SATA_RXN_2 SATA_RXP_2

SATA_TXN_2 SATA_TXP_2

SATA_RXN_3 SATA_RXP_3

SATA_TXN_3 SATA_TXP_3

SATA_RXN4/PERN1

SATA_RXP4/PERP1

SATA_TXN4/PETN1

SATA_TXP4/PETP1

SATA_RXN5/PERN2

SATA_RXP5/PERP2

SATA_TXN5/PETN2

SATA_TXP5/PETP2

SATA_RCOMP

SATALED#

SATA0GP/GPIO21

SATA1GP/GPIO19

SATA_IREF

SATA_PRX_DTX_N0 <38> SATA_PRX_DTX_P0 <38>

SATA_PTX_DRX_N0 <38> SATA_PTX_DRX_P0 <38>

SATA_PRX_DTX_N1 <40> SATA_PRX_DTX_P1 <40>

SATA_PTX_DRX_N1 <40> SATA_PTX_DRX_P1 <40>

SATA_PRX_DTX_N2 <38> SATA_PRX_DTX_P2 <38>

SATA_PTX_DRX_N2 <38> SATA_PTX_DRX_P2 <38>

1 2

RH8 7.5K_0402_1%RH8 7.5K_0 402_1%

1 2

RH9 10K_0402_5%RH9 10K_0402_5%

1 2

RH10 10K_0402_5%RH10 10K_0402_5%

1 2

RH12 10K_0402_5%RH12 10K_0402_5%

+1.5VS

1. RH12

HDD

SSD(NGFF)

ODD

+1.5VS

+3VS

B B

HDA AUDIO SIGNAL

HDA AUDIO For Codec

HDA_BCLK HDA_RST# HDA_SDOUT

Isolation

HDA_SYNC

A A

1 2

RH21 33_0402_5%RH21 33_0402_5%

1 2

RH24 33_0402_5%RH24 33_0402_5%

1 2

RH25 33_0402_5%RH25 33_0402_5%

+5VS

QH4

@

QH4

@

2

G

BSS138_NL_SOT23-3

1 3

HDA_SYNC_R

D

S

D

S

1 2

RH128 0_0402_5%RH128 0_0402_5%

5

HDA_BITCLK_AUDIO <46> HDA_RST_AUDIO# <46> HDA_SDOUT_AUDIO <46>

RH26

1 2

12

33_0402_5%

R422

@ R422

@

1M_0402_5%

HDA_SYNC_AUDIO <46>

4

HDA STRAP

2012/12/05

+3V_PCH+3VS

*

1 2

RH22 1K_0402_5%@RH22 1K_0402_5%@

HIGH= Enable ( No Reboot ) LOW= Disable (Default)

*

1. The internal pull-down is disabled after PLTRST# deasserts.

2. When Sampled : Rising edge of PWROK

+3V_PCH

1. This signal has a weak internal pull-down 15K

2. The internal pull-down on AZA_SYNC and AZA_SDO are enabled during reset.

1 2

RH27 1K_0402_5%@RH27 1K_0402_5%@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

HDA_SPKR HDA_SDOUT

HDA_SYNC

3

1 2

RH23 1K_0402_5%@RH23 1K_0402_5%@

Low = Disabled (Default) High = Enabled [Flash Descriptor Security Overide]

LC Future Center Secret Data

Deciphered Date

2

2014/12/05

RTCVCC Circuit

1 2

RH20 1K_0402_5%RH20 1K_0402_5%

+RTCBATT, +RTCVCC Trace width = 20mils

RTC External SRTCRST# Circuit

Title

PCH_RTC/HDA/SATA

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

+RTCVCC+RTCBATT

1

CH11

CH11 1U_0603_10V6-K

1U_0603_10V6-K

2

E440 NM-A151

E440 NM-A151E440 NM-A151

1

13 57

of

1.0

5

D D

+3VS

1 2

RH32 2.2K_0402_5%RH32 2.2K_0402_5%

1 2

RH33 2.2K_0402_5%RH33 2.2K_0402_5%

1 2

RH34 150_0402_1%RH34 150_0402_1%

1 2

RH35 150_0402_1%RH35 150_0402_1%

1 2

RH36 150_0402_1%RH36 150_0402_1%

+3VS

1 2

RH37 10K_0402_5%RH37 10K_0402_5%

1 2

RH38 10K_0402_5%RH38 10K_0402_5%

1 2

RH39 10K_0402_5%RH39 10K_0402_5%

1 2

C C

B B

RH40 10K_0402_5%RH40 10K_0402_5%

1 2

RH41 10K_0402_5%@RH41 10K_0402_5%@

1 2

RH42 10K_0402_5%RH42 10K_0402_5%

1 2

RH43 10K_0402_5%RH43 10K_0402_5%

1 2

RH44 10K_0402_5%RH44 10K_0402_5%

1 2

RH45 10K_0402_5%RH45 10K_0402_5%

1 2

RH46 100K_0402_5%RH46 100K_0402_5%

1 2

RH47 10K_0402_5%RH47 10K_0402_5%

1 2

RH48 10K_0402_5%RH48 10K_0402_5%

1 2

RH49 10K_0402_5%RH49 10K_0402_5%

1 2

RH50 10K_0402_5%@RH50 10K_0402_5%@

1 2

RH51 649_0402_1%RH51 649_0402_1%

1 2

RH52 100K_0402_5%RH52 100K_0402_5%

1 2

RH54 1K_0402_5%@RH54 1K_0402_5%@

1 2

RH55 10K_0402_5%@RH55 10K_0402_5%@

1 2

RH56 10K_0402_5%@RH56 10K_0402_5%@

PCH_CRT_DDC_CLK PCH_CRT_DDC_DAT

PCH_CRT_B PCH_CRT_G PCH_CRT_R

DGPU_RST#

NVDD_PWR_EN

DGPU_PWR_EN

PCH_GPIO51

PCH_GPIO55

PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#

PCH_GS_ON#

PCH_ODD_DA#

ODD_DETECT#_DP_R

SATA1_DEVSLP#

DGPU_GC6_EN

CRT_IREF

PCH_ENBKL

DGPU_PWR_EN

DGPU_GC6_EN

DGPU_RST#

4

PCH_CRT_B<35>

PCH_CRT_R<35>

PCH_CRT_DDC_CLK<35>

PCH_CRT_DDC_DAT<35>

PCH_CRT_HSYNC<35>

PCH_CRT_VSYNC<35>

PCH_EDP_PWM<36>

PCH_ENBKL<48>

PCH_ENVDD<36>

+VGA_CORE

+3VS_VGA

NVDD_PWR_EN<63>

DGPU_PWR_EN<23,54>

DGPU_GC6_EN<27>

PLT_RST#

DGPU_RST#

+3VS

2

B

1

A

3

PCH_CRT_B

PCH_CRT_G

PCH_CRT_R

PCH_CRT_DDC_CLK

PCH_CRT_DDC_DAT

PCH_CRT_HSYNC

PCH_CRT_VSYNC

CRT_IREF

PCH_EDP_PWM

PCH_ENBKL

PCH_ENVDD

PCI_PIRQA#

PCI_PIRQB#

PCI_PIRQC#

PCI_PIRQD#

DGPU_RST#

NVDD_PWR_EN

DGPU_PWR_EN

PCH_GPIO51

DGPU_GC6_EN

PCH_GPIO55

5

P

4

Y

G

UH2 NC7SZ08P5X_NL_SC70-5

NC7SZ08P5X_NL_SC70-5

3

DIS@UH2

DIS@

UH1E

T45

VGA_BLUE

U44

VGA_GREEN

V45

VGA_RED

M43

VGA_DDC_CLK

M45

VGA_DDC_DATA

N42

VGA_HSYNC

N44

VGA_VSYNC

U40

DAC_IREF

U39

VGA_IRTN

N36

EDP_BKLTCTL

K36

EDP_BKLTEN

G36

EDP_VDDEN

H20

PIRQA#

L20

PIRQB#

K17

PIRQC#

M20

PIRQD#

A12

GPIO50

B13

GPIO52

C12

GPIO54

C10

GPIO51

A10

GPIO53

AL6

GPIO55

LYNX-POINT-DH82LPMS_BGA695

SA00005U830

PLTRST_VGA# <23>

LPT_PCH_M_EV

LVDSCRT

PCI

5 OF 11

REV = 5

DISPLAY

2

DDPB_CTRLCLK

DDPB_CTRLDATA

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPB_AUXN

DDPC_AUXN

DDPD_AUXN

DDPB_AUXP

DDPC_AUXP

DDPD_AUXP

DDPB_HPD

DDPC_HPD

DDPD_HPD

PIRQE#/GPIO2

PIRQF#/GPIO3

PIRQG#/GPIO4

PIRQH#/GPIO5

PME#

PLTRST#

R40

R39

R35

R36

N40

N38

H45

K43

J42

H43

K45

J44

K40

K38

H39

G17

F17

L15

M15

AD10

Y11

PCH_HDMI_CLK PCH_HDMI_DATA

PCH_DOCK_CLK PCH_DOCK_DATA

PCH_HDMI_CLK

PCH_HDMI_DATA

PCH_DOCK_CLK

PCH_DOCK_DATA

PCH_DOCK_AUX#

PCH_DOCK_AUX

PCH_HDMI_HPD

PCH_DOCK_HPD

ODD_DETECT#_DP_R

PCH_ODD_DA#

SATA1_DEVSLP#

PCH_GS_ON#

PCI_PME#

PLT_RST#

12

RH53

RH53 100K_0402_5%

100K_0402_5%

1

1 2

RH28 2.2K_0402_5%RH28 2.2K_0402_5%

1 2

RH29 2.2K_0402_5%RH29 2.2K_0402_5%

1 2

RH136 2.2K_0402_5%RH136 2.2K_0402_5%

1 2

RH138 2.2K_0402_5%RH138 2.2K_0402_5%

PCH_HDMI_CLK <34>

PCH_HDMI_DATA <34>PCH_CRT_G<35>

PCH_DOCK_AUX# <42>

PCH_DOCK_AUX <42>

PCH_HDMI_HPD <34>

PCH_DOCK_HPD <42>

ODD_DETECT#_DP_R <38>

PCH_ODD_DA# <38>

SATA1_DEVSLP# <40>

PCH_GS_ON# <33>

PCI_PME# <42>

PLT_RST# <17,39,41,42,44,48>

To JIMIN1.Pin38

Integrated Pull-Up 20K

+3VS

A16 swap overide Strap/Top-Block Swap Override jumper

Low = A16 swap override/Top-Block

PCI_GNT3#

A A

1. The signal has a weak internal pull-up, which is disabled after PLTRST# deasserts.

2. When sampled : Rising edge of PWROK

Swap Override enabled

**High=Default

*

5

Boot BIOS Straps (BBS)

BBS_BIT1 (GPIO51)

1. GPIO51/19 has weak internal pull-up via 20kohm

2. The internal pull-up is disabled after PLTRST# deasserts.

3. GPIO51 (bit 11) at the rising edge of PWROK SATA1GP/GPIO19 (bit 10) at the rising edge of PWROK.

BBS_BIT0 (GPIO19)

Boot BIOS Location

00 LPC

0 1 Reserved (NAND)

1 0

11 SPI

PCI

*

4

For ESD

PCH_ODD_DA#

1

CH12

@ CH12

@

220P_0402_50V8-J

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/12/05

LC Future Center Secret Data

Deciphered Date

2

2014/12/05

Title

PCH_CRT/EDP/DDP

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

E440 NM-A151

E440 NM-A151E440 NM-A151

1

14 57

of

1.0

5

4

3

2

1

1 2

RH57 10K_0402_5%RH57 10K_0402_5%

D D

C C

B B

+3VALW

Stuff RH289 if EC does not want to involve in the handshake mechanism for the DeepSX state entry and exit

1 2

RH58 200K_0402_5%RH58 200K_0402_5%

1 2

RH59 10K_0402_5%RH59 10K_0402_5%

1 2

RH61 0_0402_5%@RH61 0_0402_5%@

DMI_CTX_PRX_N[3:0]<5>

DMI_CTX_PRX_P[3:0]<5>

DMI_CRX_PTX_N[3:0]<5>

DMI_CRX_PTX_P[3:0]<5>

EC to PCH

APWROK may come up earlier than PWROK but no later

PCH to EC

PCH_PWROK<48,8>

PCH_APWROK<48>

SUSWARN#<48>

+1.5VS

SUSACK#<48>

+3VS

+3VALW

+3V_PCH

SUSWARN#_R

AC_PRESENT

EC_RSMRST#

SUSWARN#_RSUSACK#_R

+1.5VS

1 2

RH67 7.5K_0402_1%RH67 7.5K_0402_1%

1 2

RH68 0_0402_5%RH68 0_0402_5%

1 2

RH70 10K_0402_5%RH70 10K_0402_5%

1 2

RH73 0_0402_5%RH73 0_0402_5%

1 2

RH74 0_0402_5%RH74 0_0402_5%

DRAMPWROK<6>

EC_RSMRST#<48>

1 2

RH75 0_0402_5%RH75 0_0402_5%

PBTN_OUT#<48>

AC_PRESENT<48>

1 2

RH76 10K_0402_5%RH76 10K_0402_5%

1 2

RH78 10K_0402_5%RH78 10K_0402_5%

DMI_CTX_PRX_N0 DMI_CTX_PRX_N1

DMI_CTX_PRX_N2 DMI_CTX_PRX_N3

DMI_CTX_PRX_P0 DMI_CTX_PRX_P1

DMI_CTX_PRX_P2 DMI_CTX_PRX_P3

DMI_CRX_PTX_N0 DMI_CRX_PTX_N1

DMI_CRX_PTX_N2 DMI_CRX_PTX_N3

DMI_CRX_PTX_P0 DMI_CRX_PTX_P1

DMI_CRX_PTX_P2 DMI_CRX_PTX_P3

DMI_RCOMP

SUSACK#_R

SYS_RESET#

SYS_PWROK

PWROK

APWROK

DRAMPWROK

EC_RSMRST#

SUSWARN#_R

PBTN_OUT#

AC_PRESENT

PCH_BATLOW#

RI#

VGATE<64>

UH1B

AW22

DMI_RXN_0

AR20

DMI_RXN_1

AP17

DMI_RXN_2

AV20

DMI_RXN_3

AY22

DMI_RXP_0

AP20

DMI_RXP_1

AR17

DMI_RXP_2

AW20

DMI_RXP_3

BD21

DMI_TXN_0

BE20

DMI_TXN_1

BD17

DMI_TXN_2

BE18

DMI_TXN_3

BB21

DMI_TXP_0

BC20

DMI_TXP_1

BB17

DMI_TXP_2

BC18

DMI_TXP_3

BE16

DMI_IREF

AW17

TP12

AV17

TP7

AY17

DMI_RCOMP

R6

SUSACK#

AM1

SYS_RESET#

AD7

SYS_PWROK

F10

PWROK

AB7

APWROK

H3

DRAMPWROK

J2

RSMRST#

J4

SUSWARN#/SUSPWRNACK/GPIO30

K1

PWRBTN#

E6

ACPRESENT/GPIO31

K7

BATLOW#/GPIO72

N4

RI#

AB10

TP21

D2

SLP_WLAN#/GPIO29

LYNX-POINT-DH82LPMS_BGA695

SA00005U830

VGATE

PCH_PWROK

12

LPT_PCH_M_EDS

APWROK only for A phase

A A

PWROK APWROK

1 2

RH13 0_0402_5%@RH13 0_0402_5%@

5

4

+3VS+3V_PCH

1

CH13

CH13 .1U_0402_16V4-Z

.1U_0402_16V4-Z

2

5

2

P

B

4

Y

1

A

G

UH3

3

MC74VHC1G08DFT2G SC70 5P

RH62

RH62 10K_0402_5%

10K_0402_5%

DMI

System Power

Management

MC74VHC1G08DFT2G SC70 5P

REV = 5

FDI

4 OF 11

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

FDI_RXN_0

FDI_RXN_1

FDI_RXP_0

FDI_RXP_1

TP16

TP5

TP15

TP10

FDI_CSYNC

FDI_INT

FDI_IREF

TP17

TP13

FDI_RCOMP

DSWVRMEN

DPWROK

WAKE#

CLKRUN#

SUS_STAT#/GPIO61

SUSCLK/GPIO62

SLP_S5#/GPIO63

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

SLP_LAN#

3

SYS_PWROK

12

R1

@ R1

@

100K_0402_5%

AJ35

FDI_CTX_PRX_N0

AL35

FDI_CTX_PRX_N1

AJ36

FDI_CTX_PRX_P0

AL36

FDI_CTX_PRX_P1

AV43

AY45

AV45

AW44

AL39

FDI_CSYNC

AL40

FDI_INT

AT45

FDI_IREF

AU42

AU44

AR44

FDI_RCOMP

C8

DSWVRMEN

L13

DPWROK EC_DPWROK

K3

WAKE#

AN7

PM_CLKRUN#

U7

Y6

Y7

C6

H1

F3

F1

AY3

G5

Can be left NC if no use integrated LAN. 10/06 Test point request

2012/12/05

1

SUS_STAT#

1

SUSCLK

PM_SLP_S5#

PM_SLP_S4#

PM_SLP_S3#

PM_SLP_A#

PM_SLP_SUS#_R

H_PM_SYNC

1

PCH_SLPLAN#

LC Future Center Secret Data

Deciphered Date

FDI_CTX_PRX_N0 <8>

FDI_CTX_PRX_N1 <8>

FDI_CTX_PRX_P0 <8>

FDI_CTX_PRX_P1 <8>

FDI_CSYNC <5>

FDI_INT <5>

1 2

RH65 0_0402_5%RH65 0_0402_5%

1 2

RH66 7.5K_0402_1%RH66 7.5K_040 2_1%

1 2

RH69 330K_0402_5%RH69 330K_0402_5%

1 2

RH71 0_0402_5%RH71 0_0402_5%

1 2

RH72 0_0402_5%@RH72 0_0402_5%@

PM_CLKRUN# <44>

T72 @T72 @

T73 @T73 @

PM_SLP_S5# <48>

PM_SLP_S4# <48>

PM_SLP_S3# <48>

PM_SLP_A# <48>

1 2

RH77 0_0402_5%RH77 0_0402_5%

H_PM_SYNC <6>

T74 @T74 @

2

+1.5VS

+RTCVCC

WLAN_WAKE#

PM_SLP_SUS#

Can be left NC when IAMT is not support on the platfrom

2014/12/05

DPWROK

1 2

RH60 100K_0402_5%RH60 100K_0402_5%

100 kOhms ±1% pull-down to GND

DSWVREN must be always pulled high to +RTCVCC DSWVREN - Internal Deep Sleep 1.05V regulator

：：：：

Enable

**H

*

：：：：

Disable

L

EC_DPWROK <48>

WLAN_WAKE# <39>

WAKE#

PM_CLKRUN#

For Deep S3

PM_SLP_SUS# <48,55>

RH63 10K_0402_5%RH63 10K_0402_5%

RH64 10K_0402_5%RH64 10K_0402_5%

For Deep S3

For WLAN WAKE# (Disable)

1 2

SUSCLK/GPIO62

This signal has a weak internal pull-up. 0 = Disable PLL On-Die voltage regulator. 1 = Enable PLL On-Die voltage regulator.

*

NOTES:

1. The internal pull-up is disabled after RSMRST# deasserts.

2. This signal is in the Suspend well.

Title

PCH_DMI/FDI/PM

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

E440 NM-A151

E440 NM-A151E440 NM-A151

1

15 57

+3VALW

of

+3VS

1.0

5

D D

1 2

RH80 10K_0402_5%RH80 10K_0402_5%

+3V_PCH

1. No use Native function

2. When configured as GPIO, default direction is Output (GPO).

CardReader, Core

LAN, Suspend

WLAN, Suspend

+3V_PCH

C C

+3V_PCH

When configured as GPIO, default direction is Input (GPI).RH87, 90 and 94

CLK_PCI_EC<48>

CLK_PCI_DB<39>

CLK_PCI_TPM<44>

CLK_PCIE_CR#<41>

CLK_PCIE_CR<41>

CLKREQ_CR#<41>

CLK_PCIE_LAN#<42> CLK_PCIE_LAN<42> CLKREQ_LAN#<42>

CLK_PCIE_WLAN#<39> CLK_PCIE_WLAN<39> CLKREQ_WLAN#<39>

1 2

RH87 10K_0402_5%RH87 10K_0402_5%

1 2

RH90 10K_0402_5%RH90 10K_0402_5%

1 2

RH94 10K_0402_5%RH94 10K_0402_5%

1 2

RH96 22_0402_5%RH96 22_0402_5%

1 2

RH97 22_0402_5%@RH97 22_0402_5%@

1 2

RH98 22_0402_5%TPM@RH98 22_0402_5%TPM@

1 2

RH99 22_0402_5%RH99 22_0402_5%

CLK_PCI_LOOPBACK

4

PCH_GPIO73

CLK_PCIE_CR#

CLK_PCIE_CR

CLKREQ_CR#

CLK_PCIE_LAN# CLK_PCIE_LAN CLKREQ_LAN#

CLK_PCIE_WLAN# CLK_PCIE_WLAN CLKREQ_WLAN#

PCH_GPIO44

PCH_GPIO45

PCH_GPIO46

Remove TP

CLK_PCI_EC_R

PCH_CLK_PCI_DB

CLK_PCI_TPM_R

PCI_LOOPBACKOUT

UH1C

Y43

CLKOUT_PCIE_N_0

Y45

CLKOUT_PCIE_P_0

AB1

PCIECLKRQ0#/GPIO73

AA44

CLKOUT_PCIE_N_1

AA42

CLKOUT_PCIE_P_1

AF1

PCIECLKRQ1#/GPIO18

AB43

CLKOUT_PCIE_N_2

AB45

CLKOUT_PCIE_P_2

AF3

PCIECLKRQ2#/GPIO20/SMI#

AD43

CLKOUT_PCIE_N_3

AD45

CLKOUT_PCIE_P_3

T3

PCIECLKRQ3#/GPIO25

AF43

CLKOUT_PCIE_N_4

AF45

CLKOUT_PCIE_P_4

V3

PCIECLKRQ4#/GPIO26

AE44

CLKOUT_PCIE_N5

AE42

CLKOUT_PCIE_P_5

AA2

PCIECLKRQ5#/GPIO44

AB40

CLKOUT_PCIE_N_6

AB39

CLKOUT_PCIE_P_6

AE4

PCIECLKRQ6#/GPIO45

AJ44

CLKOUT_PCIE_N_7

AJ42

CLKOUT_PCIE_P_7

Y3

PCIECLKRQ7#/GPIO46

AH43

CLKOUT_ITPXDP_N

AH45

CLKOUT_ITPXDP_P

D44

CLKOUT_33MHZ0

E44

CLKOUT_33MHZ1

B42

CLKOUT_33MHZ2

F41

CLKOUT_33MHZ3

A40

CLKOUT_33MHZ4

CLOCK SIGNAL

LYNX-POINT-DH82LPMS_BGA695

SA00005U830

LPT_PCH_M_EDS

REV = 5

PEG_A_CLKRQ#/GPIO47

PEG_B_CLKRQ#/GPIO56

CLKIN_33MHZLOOPBACK

2 OF 11

3

CLKOUT_PEG_A_N

CLKOUT_PEG_A_P

CLKOUT_PEG_B_N

CLKOUT_PEG_B_P

CLKOUT_DMI_N

CLKOUT_DMI_P

CLKOUT_DP_N CLKOUT_DP_P

CLKOUT_DPNS_N CLKOUT_DPNS_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_GND_N

CLKIN_GND_P

CLKIN_DOT96N CLKIN_DOT96P

CLKIN_SATA_N CLKIN_SATA_P

REFCLK14IN

XTAL25_IN

XTAL25_OUT

CLKOUTFLEX0/GPIO64

CLKOUTFLEX1/GPIO65

CLKOUTFLEX2/GPIO66

CLKOUTFLEX3/GPIO67

ICLK_IREF

TP19 TP18

DIFFCLK_BIASREF

AB35

AB36

AF6

Y39

Y38

U4

AF39

AF40

AJ40 AJ39

AF35 AF36

AY24 AW24

AR24 AT24

H33 G33

BE6 BC6

F45 D17

AM43 AL44

C40

F38

F36

F39

AM45

AD39 AD38

AN44

CLK_PCIE_VGA#

CLK_PCIE_VGA

CLK_REQ_GPU#_R

PCH_GPIO56

CLK_CPU_DMI#

CLK_CPU_DMI

CLK_CPU_SSC_DPLL# CLK_CPU_SSC_DPLL

CLK_CPU_DPLL# CLK_CPU_DPLL

CLK_BUF_CPU_DMI# CLK_BUF_CPU_DMI

CLKIN_BUF_DMI2# CLKIN_BUF_DMI2

CLK_BUF_DREF_96M# CLK_BUF_DREF_96M

CLK_BUF_PCIE_SATA# CLK_BUF_PCIE_SATA

CLK_BUF_ICH_14M CLK_PCI_LOOPBACK

PCH_XTAL25_IN PCH_XTAL25_OUT

PCH_GPIO64

PCH_GPIO65

LAN_25M

PCH_GPIO67

+1.5VS

PCH_CLK_BIASREF

2

CLK_PCIE_VGA# <23>

CLK_PCIE_VGA <23>

CLK_REQ_GPU#_R <23>

CLK_CPU_DMI# <6>

CLK_CPU_DMI <6>

CLK_CPU_SSC_DPLL# <6> CLK_CPU_SSC_DPLL <6>

CLK_CPU_DPLL# <6> CLK_CPU_DPLL <6>

1 2

RH83 10K_0402_5%RH83 10K_0402_5%

1 2

RH84 10K_0402_5%RH84 10K_0402_5%

1 2

RH85 10K_0402_5%RH85 10K_0402_5%

1 2

RH86 10K_0402_5%RH86 10K_0402_5%

1 2

RH88 10K_0402_5%RH88 10K_0402_5%

1 2

RH89 10K_0402_5%RH89 10K_0402_5%

1 2

RH91 10K_0402_5%RH91 10K_0402_5%

1 2

RH92 10K_0402_5%RH92 10K_0402_5%

1 2

RH93 10K_0402_5%RH93 10K_0402_5%

1 2

RH95 0_0402_5%@RH95 0_0402_5%@

PCH_GPIO67 <19>

+1.5VS

1 2

RH100 7.5K_0402_1%RH100 7.5K_0402_1%

Reseve for SKU ID

CLK_REQ_GPU#_R

PCH_GPIO56

PCH_LAN_25M <42>

+1.05VS_+1.5VS_RUN

1

1 2

RH79 10K_0402_5%RH79 10K_0402_5%

1 2

RH81 10K_0402_5%RH81 10K_0402_5%

+1.5VS

+3V_PCH

B B

+3V_PCH

1 2

RH101 10K_0402_5%RH101 10K_0402_5%

1 2

RH103 10K_0402_5%RH103 10K_0402_5%

+3VS

A A

Reserve for EMI please close to PCH

CLK_PCI_LOOPBACK

5

1 2

RH105 10K_0402_5%RH105 10K_0402_5%

RH102

1 2

@

33_0402_5%

CLKREQ_LAN#

CLKREQ_WLAN#

CLKREQ_CR#

CH14

1 2

@

22P_0402_50V8-J

4

PCH Crystal Project Phase ID

PCH_XTAL25_IN

PCH_XTAL25_OUT

CH15

12P_0402_50V8-J

1

2

1 2

RH104 1M_0402_5%RH104 1M_0402_5%

YH2

1

OSC1

GND12OSC2

25MHZ_10PF_7V25000014

GND2

4

3

1

CH16

CH16 12P_0402_50V8-J

12P_0402_50V8-J

2

SDV, FVT

SIT2 (R 0.5)

SIT (R 0.4)

SVT

*

Change to 7V25000014 (TXC),. Cap 15pF*2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/12/05

LC Future Center Secret Data

Deciphered Date

PCH_GPIO64Project Phase

0 0

0 1

1 0

1 1

2014/12/05

2

PCH_GPIO65

+3VS

1 2

RH31 10K_0402_5%RH31 10K_0402_5%

1 2

RH82 10K_0402_5%RH82 10K_0402_5%

1 2

RH152 10K_0402_5%@RH152 10K_0402_5%@

1 2

RH162 10K_0402_5%@RH162 10K_0402_5%@

Title

PCH_PCIE/CLK

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

E440 NM-A151

E440 NM-A151E440 NM-A151

1

PCH_GPIO64

PCH_GPIO65

PCH_GPIO64

PCH_GPIO65

16 57

of

1.0

5

EC, MINI CARD and TPM Module debug port

LPC_AD[3:0]<39,44,48>

D D

+3VS

C C

1 2

RH110 10K_0402_5%RH110 10K_0402_5%

1 2

RH119 10K_0402_5%RH119 10K_0402_5%

SERIRQ

PCH_GPIO23

SPI_CLK_8MB SPI_CLK_4MB

SPI_CS0#_8MB

SPI_CS1#_4MB

SPI_SI_8MB SPI_SI_4MB SPI_SI

SPI_SO_8MB SPI_SO_4MB

SPI_IO2_8MB SPI_IO2_4MB

SPI_IO3_8MB SPI_IO3 SPI_IO3_4MB

+3V_SPI

RH111 33_0402_5%RH111 33_0402_5% RH112 33_0402_5%RH112 33_0402_5%

RH113 0_0402_5%RH113 0_0402_5%

RH114 0_0402_5%RH114 0_0402_5%

RH115 33_0402_5%RH115 33_0402_5% RH116 33_0402_5%RH116 33_0402_5%

RH117 33_0402_5%RH117 33_0402_5% RH118 33_0402_5%RH118 33_0402_5%

RH129 33_0402_5%RH129 33_0402_5% RH130 33_0402_5%RH130 33_0402_5%

RH131 33_0402_5%RH131 33_0402_5% RH132 33_0402_5%RH132 33_0402_5%

Near U4M1 and U8M1

RH16 1K_0402_5%RH16 1K_0402_5% RH17 1K_0402_5%RH17 1K_0402_5%

1 2 1 2

1 2

1 2 1 2

LPC_FRAME#<39,44,48>

Near U4M1

8MB + 4MB SPI ROM, 5MB ME(SBA), Security EEPROM

Security EEPROM

SBA Fun. Power rail

B B

+3VS

PLT_RST#<14,39,41,42,44,48>

+3VS

+3VM

8MB(64Mb) 4MB(32Mb)

CH17

VCC

CLK

DI

CH17

1 2

10P_0402_50V8-J

8

7

6

5

RH133

1 2

@

10_0402_5%

U8M1

SPI_CS0#_8MB

SPI_SO_8MB

A A

SPI_IO2_8MB

1

CS#

2

DO

3

WP#

4

GND

W25Q64FVSSIG_SO8

SA000039A2J

5

HOLD#

RH124

1 2

@

0_0402_5%

1 2

RH125 0_0402_5%@RH125 0_0402_5%@

1 2

RH127 0_0402_5%RH127 0_0402_5%

For EMI For EMI

@

SPI_IO3_8MB SPI_IO2_4MB

SPI_CLK_8MB

SPI_SI_8MB

PLT_RST#

+3V_SPI +3V_SPI

2

CH19

0.1U_0402_10V7-K

1

4

UH1D

LPC_AD0

LPC_AD1

LPC_AD2

LPC_AD3

LPC_FRAME#

PCH_GPIO23

SERIRQ<44,48>

SERIRQ

SPI_CLK

SPI_CS0#

SPI_CS1#

SPI_SO

SPI_IO2

SPI_IO2 SPI_IO3

A20

LAD_0

C20

LAD_1

A18

LAD_2

C18

LAD_3

B21

LFRAME#

D21

LDRQ0#

G20

LDRQ1#/GPIO23

AL11

SERIRQ

AJ11

SPI_CLK

AJ7

SPI_CS0#

AL7

SPI_CS1#

AJ10

SPI_CS2#

AH1

SPI_MOSI

AH3

SPI_MISO

AJ4

SPI_IO2

AJ2

SPI_IO3

LYNX-POINT-DH82LPMS_BGA695

SA00005U830

SPILPC

LPT_PCH_M_EDS

REV = 5

SMBus

C-Link

Thermal

3 OF 11

3

SML1ALERT#/PCHHOT#/GPIO74

SMBALERT#/GPIO11

SMBCLK

SMBDATA

SML0ALERT#/GPIO60

SML0CLK

SML0DATA

SML1CLK/GPIO58

SML1DATA/GPIO75

CL_CLK

CL_DATA

CL_RST#

TD_IREF

SM Bus

2

N7

PCH_SMBALERT#

R10

PCH_SMBCLK

U11

PCH_SMBDATA

N8

PCH_GPIO60

U8

PCH_SML0CLK

R7

PCH_SML0DATA

H6

PCH_GPIO74

K6

PCH_SML1CLK

N11

PCH_SML1DATA

AF11

AF10

AF7

BA45

TP1

BC45

TP2

BE43

TP4

BE44

TP3

AY43

PCH_TD_IREF

Touch Panel

PCH_SMBALERT#

PCH_GPIO60

PCH_GPIO74

PCH_TD_IREF

RH106 10K_0402_5%RH106 10K_0402_5%

RH107 1K_0402_5%RH107 1K_0402_5%

RH108 10K_0402_5%RH108 10K_0402_5%

RH109 8.2K_0402_1%RH109 8.2K_0402_1%

PCH_SML1CLK PCH_SML1DATA PCH_SMBDATA PCH_SMBCLK

PCH_SML0CLK PCH_SML0DATA

1 2

RPH3

1 8 2 7 3 6 4 5

2.2K_0804_5%

SD30922010T

RPH4

1 8 2 7 3 6 4 5

2.2K_0804_5%

SD30922010T

1

+3V_PCH

DIMM1, DIMM2, WLAN(@), CP, Security EEPROM

+3VS

Touch Panel

SMB_CLK_TPANEL <44>

SMB_DATA_TPANEL <44>

17 57

of

1.0

USROM1

1

NC_1

2 3 4

VCC

NC_2

WP

SCL

PROT#

SDA

GND

PCA24S08AD_SO8

SA00004MK00/SA00004ML00

+3V_SPI

0.085 A

SPI_CLK_4MBSPI_CLK_8MB

SPI_CS1#_4MB SPI_SO_4MB

SA00005P500 SA00003K80J --> EOL

4

8 7 6

PM_SMBCLK

5

PM_SMBDATA

U4M1

1

CS#

2

DO

3

WP#

4

GND

W25Q32FVSSIQ_SO8

SA00005P500

RH134

1 2

@

10_0402_5%

VCC

HOLD#

CLK

8 7 6 5

DI

+3VS

1

C1

0.1U_0402_16V4Z

2

CH18

1 2

@

10P_0402_50V8-J

SPI_IO3_4MB SPI_CLK_4MB SPI_SI_4MB

+3VS

2

G

PCH_SMBCLK

PCH_SMBDATA

PCH_SML1DATA EC_SMB_DA3

2

CH20

0.1U_0402_10V7-K

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/12/05

PCH_SML0CLK

PCH_SML0DATA

LC Future Center Secret Data

Deciphered Date

2

2014/12/05

6 1

D

5

QH1A

G

2N7002KDWH_SOT363-6

SB00000YR00

3 4

S

D

QH1B

QH1B 2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

SB00000YR00

+3VS

2

G

6 1

D

5

QH2A

G

2N7002KDWH_SOT363-6

SB00000YR00

3 4

SB00000YR00

S

D

QH2B

QH2B 2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

SB00000YR00

+3VS +3VS

2

G

6 1

D

5

QH3A

G

2N7002KDWH_SOT363-6

SB00000YR00

S

D

QH3B

QH3B 2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

SB00000YR00

1 2

RH121 4.7K_0402_5%RH121 4.7K_0402_5%

1 2

RH123 4.7K_0402_5%RH123 4.7K_0402_5%

PM_SMBCLK

S

PM_SMBDATA

PM_SMBCLK <11,12,39,43>

PM_SMBDATA <11,12,39,43>

GPU, EC, Thermal Sensor

2N7002KDWH Vth= min 1V, max 2.5V ESD 2KV

EC_SMB_CK3PCH_SML1CLK

S

RH135 2.2K_0402_5%RH135 2.2K_0402_5%

RH137 2.2K_0402_5%RH137 2.2K_0402_5%

SMB_CLK_TPANEL

S

SMB_DATA_TPANEL

Title

PCH_LPC/SPI/SM BUS

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

EC_SMB_CK3 <23,32,48>

EC_SMB_DA3 <23,32,48>

1 2

E440 NM-A151

E440 NM-A151E440 NM-A151

1

5

D D

PCIE_PRX_DTX_N3<41>

CardReader

C C

LAN

WLAN

B B

PCIE_PRX_DTX_P3<41>

PCIE_PTX_C_DRX_N3<41> PCIE_PTX_C_DRX_P3<41>

PCIE_PRX_DTX_N4<42> PCIE_PRX_DTX_P4<42>

PCIE_PTX_C_DRX_N4<42> PCIE_PTX_C_DRX_P4<42>

PCIE_PRX_DTX_N5<39> PCIE_PRX_DTX_P5<39>

PCIE_PTX_C_DRX_N5<39> PCIE_PTX_C_DRX_P5<39>

1 2

CH21 0.1U_0402_10V7-KCH21 0.1U_0402_10V7-K

1 2

CH22 0.1U_0402_10V7-KCH22 0.1U_0402_10V7-K

1 2

CH23 0.1U_0402_10V7-KCH23 0.1U_0402_10V7-K

1 2

CH24 0.1U_0402_10V7-KCH24 0.1U_0402_10V7-K

1 2

CH25 0.1U_0402_10V7-KCH25 0.1U_0402_10V7-K

1 2

CH26 0.1U_0402_10V7-KCH26 0.1U_0402_10V7-K

+1.5VS

4

+1.5VS

R2

1 2

7.5K_0402_1%

PCIE_PRX_DTX_N3 PCIE_PRX_DTX_P3

PCIE_PTX_DRX_N3 PCIE_PTX_DRX_P3

PCIE_PRX_DTX_N4 PCIE_PRX_DTX_P4

PCIE_PTX_DRX_N4 PCIE_PTX_DRX_P4

PCIE_PRX_DTX_N5 PCIE_PRX_DTX_P5

PCIE_PTX_DRX_N5 PCIE_PTX_DRX_P5

PCIE_RCOMP

UH1I

AW31

PERN1/USB3RN3

AY31

PERP1/USB3RP3

BE32

PETN1/USB3TN3

BC32

PETP1/USB3TP3

AT31

PERN2/USB3RN4

AR31

PERP2/USB3RP4

BD33

PETN2/USB3TN4

BB33

PETP2/USB3TP4

AW33

PERN_3

AY33

PERP_3

BE34

PETN_3

BC34

PETP_3

AT33

PERN_4

AR33

PERP_4

BE36

PETN_4

BC36

PETP_4

AW36

PERN_5

AV36

PERP_5

BD37

PETN_5

BB37

PETP_5

AY38

PERN_6

AW38

PERP_6

BC38

PETN_6

BE38

PETP_6

AT40

PERN_7

AT39

PERP_7

BE40

PETN_7

BC40

PETP_7

AN38

PERN_8

AN39

PERP_8

BD42

PETN_8

BD41

PETP_8

BE30

PCIE_IREF

BC30

TP11

BB29

TP6

BD29

PCIE_RCOMP

LYNX-POINT-DH82LPMS_BGA695

SA00005U830

LPT_PCH_M_EDS

PCIe

9 OF 11

3

REV = 5

USB

USB2N0 USB2P0 USB2N1 USB2P1 USB2N2 USB2P2 USB2N3 USB2P3 USB2N4 USB2P4 USB2N5 USB2P5 USB2N6 USB2P6 USB2N7 USB2P7 USB2N8 USB2P8 USB2N9

USB2P9 USB2N10 USB2P10 USB2N11 USB2P11 USB2N12 USB2P12 USB2N13 USB2P13

USB3RN1

USB3RP1 USB3TN1 USB3TP1

USB3RN2

USB3RP2 USB3TN2 USB3TP2

USB3RN5

USB3RP5 USB3TN5 USB3TP5

USB3RN6

USB3RP6 USB3TN6 USB3TP6

USBRBIAS#

USBRBIAS

TP24 TP23

OC0#/GPIO59 OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43

OC5#/GPIO9 OC6#/GPIO10 OC7#/GPIO14

2

B37

USB20_N0

D37

USB20_P0

A38

USB20_N1

C38

USB20_P1

A36 C36 A34

USB20_N3

C34

USB20_P3

B33

USB20_N4

D33

USB20_P4

F31

USB20_N5

G31

USB20_P5

K31 L31

Some PCH config not support USB port 6 & 7.

G29 H29 A32 C32 A30

USB20_N9

C30

USB20_P9

B29

USB20_N10

D29

USB20_P10

A28

USB20_N11

C28

USB20_P11

G26

USB20_N12

F26

USB20_P12

F24

USB20_N13

G24

USB20_P13

AR26

USB30_RX_N1

AP26

USB30_RX_P1

BE24

USB30_TX_N1

BD23

USB30_TX_P1

AW26

USB30_RX_N2

AV26

USB30_RX_P2

BD25

USB30_TX_N2

BC24

USB30_TX_P2

AW29

USB30_RX_N5

AV29

USB30_RX_P5

BE26

USB30_TX_N5

BC26

USB30_TX_P5

AR29 AP29 BD27 BE28

K24

USBRBIAS

K26

Within 500 mils

M33 L33

P3

USB_OC0#

V1

USB_OC1#

U2

USB_OC2#

P1

USB_OC3#

M3

USB_OC4#

T1

USB_OC5#

N2

PCH_3G_DET#

M1

USB_OC7#

USB20_N0 <37> USB20_P0 <37> USB20_N1 <37> USB20_P1 <37>

USB20_N3 <42> USB20_P3 <42> USB20_N4 <44> USB20_P4 <44>

1

T77 @T77 @

1

T78 @T78 @

USB20_N9 <41> USB20_P9 <41>

USB20_N10 <39> USB20_P10 <39> USB20_N11 <40> USB20_P11 <40> USB20_N12 <44> USB20_P12 <44> USB20_N13 <36> USB20_P13 <36>

USB30_RX_N1 <4 2> USB30_RX_P1 <42>

USB30_TX_N1 <42>

USB30_TX_P1 <42> USB30_RX_N2 <3 7> USB30_RX_P2 <37>

USB30_TX_N2 <37>

USB30_TX_P2 <37> USB30_RX_N5 <3 7> USB30_RX_P5 <37>

USB30_TX_N5 <37>

USB30_TX_P5 <37>

1 2

RH139 22.6_0402_1%RH139 22.6_0402_1%

USB_OC0# <37>

USB_OC5# <41> PCH_3G_DET# <40>

LEFT USB20 (Front)

LEFT USB20 (Back)

Docking USB3.0

Touch Panel

RIGHT USB20 Sleep&charge (S/B), Debug port,

WLAN

WWAN

FingerPrint (S/B)

CAMERA

RIGHT Docking

LEFT USB30 (Front)

LEFT USB30 (Back)

USB Port0, 1 (LEFT USB)

USB Port5 (Sleep&Charge)

USB_OC1# USB_OC2# USB_OC5# USB_OC0#

USB_OC3# PCH_3G_DET# USB_OC7# USB_OC4#

1

RPH1

1 8 2 7 3 6 4 5

10K_0804_8P4R_5%

SD300002P0T

RPH2

1 8 2 7 3 6 4 5

10K_0804_8P4R_5%

SD300002P0T

+3V_PCH

USB2.0 : OC#0-3 --> Port 0-7 OC#4-7 --> Port 8-13

A A

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

OC[3:0]# should be connected with USB 2.0 ports 0 - 7 and any 4 of USB 3.0 ports 1 - 6.

LC Future Center Secret Data

Issued Date

2012/12/05

3

LC Future Center Secret Data

Deciphered Date

2

2014/12/05

Port1

Port2

Port5

X Sleep&Charge (Right)

USB2.0USB3.0

Port3

Port0

Port1

Port9

Title

PCH_PCIE/USB/OC#

Size Document Number Rev

Custom

Date: Sheet

OC#

X

OC0#

OC5#

Thursday, July 11, 2013

Note

Docking (Right)

LEFT USB (Front)

LEFT USB (Back)

E440 NM-A151

E440 NM-A151E440 NM-A151

1

18 57

1.0

of

5

+3VS

1 2

RH141 10K_0402_5%RH141 10K_0402_5%

1 2

D D

C C

+3VALW

RH143 10K_0402_5%RH143 10K_0402_5%

RH144 10K_0402_5%RH144 10K_0402_5%

RH145 10K_0402_5%RH145 10K_0402_5%

RH146 10K_0402_5%RH146 10K_0402_5%

RH147 10K_0402_5%RH147 10K_0402_5%

RH148 10K_0402_5%RH148 10K_0402_5%

RH149 10K_0402_5%RH149 10K_0402_5%

RH150 10K_0402_5%RH150 10K_0402_5%

RH151 200K_0402_5%RH151 200K_0402_5%

RH153 10K_0402_5%@RH153 10K_0402_5%@

RH154 10K_0402_5%RH154 10K_0402_5%

RH155 10K_0402_5%RH155 10K_0402_5%

RH157 10K_0402_5%RH157 10K_0402_5%

RH158 10K_0402_5%RH158 10K_0402_5%

RH15 10K_0402_5%RH15 10K_0402_5%

+3V_PCH

RH159 10K_0402_5%@RH159 10K_0402_5%@

RH160 10K_0402_5%RH160 10K_0402_5%

RH163 10K_0402_5%RH163 10K_0402_5%

RH177 10K_0402_5%RH177 10K_0402_5%

RH161 10K_0402_5%RH161 10K_0402_5%

RH14 10K_0402_5%RH14 10K_0402_5%

RH165 10K_0402_5%@RH165 10K_0402_5%@

1 2

FN_LED#_R

F1_LED#_R

F4_LED#_R

GC6_EVENT#_R

EC_SCI#

PCH_BT_DISABLE#

BT_DET#

3G_OFF#

GPS_OFF#

ODD_DETECT#

ODD_DETECT#_R

PCH_GPIO35

CMOS_ON#

GATEA20

KBRST#

PCH_GPIO37

WWAN_ON

DOCK_DETECT#

PCH_GPIO57

PCH_MSATA_DET

WWAN_ON

TRACKP_ON

PCH_GPIO37

4

1 2

GC6_EVENT#<23,48>

FN_LED#<45>

F1_LED#<45>

RH194 0_0402_5%@RH194 0_0402_5%@

1 2

RH140 0_0402_5%RH140 0_0402_5%

1 2

RH142 0_0402_5%RH142 0_0402_5%

EC_SCI#<48>

DOCK_DETECT#<42>

WWAN_ON<39>

DGPU_PWROK<27,54,62,63>

PCH_BT_DISABLE#<39>

ODD_EN<38>

For tempo detect

TRACKP_ON<43>

1 2

PCH_BT_ON#<39>

ODD_DETECT#_DP<38>

F4_LED#<45>

RH18 0_0402_5%@RH18 0_0402_5%@

1 2

RH19 0_0402_5%@RH19 0_0402_5%@

3G_OFF#<40>

GPS_OFF#<40>

CMOS_ON#<36>

1 2

RH164 0_0402_5%RH164 0_0402_5%

Reseve for SKU ID

BT_DET#<39>

ODD_DETECT#_R ODD_DETECT#

1 2

RH30 0_0402_5%RH30 0_0402_5%

GC6_EVENT#_R

FN_LED#_R

F1_LED#_R

EC_SCI#

DOCK_DETECT#

WWAN_ON

PCH_GPIO16

DGPU_PWROK

PCH_BT_DISABLE#

ODD_EN

PCH_MSATA_DET

TRACKP_ON

ODD_DETECT#_R

PCH_GPIO35

ODD_DETECT#

PCH_GPIO37

PCH_GPIO38

3G_OFF#

GPS_OFF#

PCH_GPIO49

PCH_GPIO57

CMOS_ON#

F4_LED#_R

PCH_GPIO70

BT_DET#

3

LPT_PCH_M_EDS

Output

LPT_PCH_M_EDS

Input

GPIO

NCTF

6 OF 11

REV = 5

UH1F

AT8

BMBUSY#/GPIO0

F13

TACH1/GPIO1

A14

TACH2/GPIO6

G15

TACH3/GPIO7

Y1

GPIO8

K13

LAN_PHY_PWR_CTRL/GPIO12

AB11

GPIO15

AN2

SATA4GP/GPIO16

C14

TACH0/GPIO17

BB4

SCLOCK/GPIO22

Y10

GPIO24

R11

GPIO27

AD11

GPIO28

AN6

GPIO34

AP1

GPIO35/NMI#

AT3

SATA2GP/GPIO36

AK1

SATA3GP/GPIO37

AT7

SLOAD/GPIO38

AM3

SDATAOUT0/GPIO39

AN4

SDATAOUT1/GPIO48

AK3

SATA5GP/GPIO49

U12

GPIO57

C16

TACH4/GPIO68

D13

TACH5/GPIO69

G13

TACH6/GPIO70

H15

TACH7/GPIO71

BE41

VSS_NCTF_1

BE5

VSS_NCTF_2

C45

VSS_NCTF_3

A5

VSS_NCTF_4

LYNX-POINT-DH82LPMS_BGA695

SA00005U830

2

CPU/Misc

RCIN#

PROCPWRGD

THRMTRIP#

PLTRST_PROC#

VSS_N10

VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8

VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21 VSS_NCTF_22 VSS_NCTF_23 VSS_NCTF_24

TP14

PECI

AN10

GATEA20

AY1

AT6

KBRST#

AV3

H_CPUPWRGD

AV1

PCH_THERMTRIP#

AU4

PLTRST_PROC#

N10

PCH_THERMTRIP#

A2 A41 A43 A44 B1 B2 B44 B45 BA1 BC1 BD1 BD2 BD44 BD45 BE2 BE3 D1 E1 E45 A4

GATEA20 <48>

KBRST# <48>

H_CPUPWRGD <6>

PLTRST_PROC# <6>

1 2

RH156 390_0402_5%RH156 390_0402_5%

1 2

RH11 0_0402_5%@RH11 0_0402_5%@

1

H_THERMTRIP# <6>

VGA_THERMTRIP# <23>

B B

PCH_MSATA_DET#<40>

2

G

PCH_MSATA_DET

13

D

QH5

QH5 2N7002KW_SOT323-3

2N7002KW_SOT323-3

S

CONFIG

USB X4,PCIEX8,SATAX6

*

GPIO16, 49

11

01USB X6,PCIEX8,SATAX4

+3VS

1 2

RH167 10K_0402_5%RH167 10K_0402_5%

1 2

RH169 10K_0402_5%RH169 10K_0402_5%

PCH_GPIO16 PCH_GPIO49

No use Flexible I/O pin, delete RH172, RH174

SKU ID

PCH_GPIO38

*

Optimus

Reserve

A A

DIS

UMA

*

14"

*

15"

*

PCH_GPIO67

0 0

0 1

1 0

1 1

5

PCH_GPIO70Function

+3VS

1 2

RH166 10K_0402_5%UMA@RH166 10K_0402_5%UMA@

1 2

RH168 10K_0402_5%UMA@RH168 10K_0402_5%UMA@

1 2

RH170 10K_0402_5%NM15@RH170 10K_0402_5%NM15@

1 2

RH171 10K_0402_5%DIS@RH171 10K_0402_5%DIS@

1 2

RH173 10K_0402_5%DIS@RH173 10K_0402_5%DIS@

1 2

0

RH175 10K_0402_5%NM14@RH175 10K_0402_5%NM14@

1

4

PCH_GPIO38

PCH_GPIO67

PCH_GPIO70

PCH_GPIO38

PCH_GPIO67

PCH_GPIO70

PCH_GPIO67 <16>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/12/05

LC Future Center Secret Data

Deciphered Date

2

2014/12/05

Title

PCH_GPIO/CPU-MISC

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

E440 NM-A151

E440 NM-A151E440 NM-A151

1

19 57

of

1.0

5

4

3

2

1

LH1

RH178

+1.5VS_VCCADAC

D D

LPT_PCH_M_EDS

0.67 A

LPT_PCH_M_EDS

CRT DAC

HVCMOS

Core

PCIe/DMI

SATA

VCCMPHY

REV = 5

FDI

USB3

7 OF 11

0.07 A

0.0133 A

0.183 A

0.133 A

0.261 A

3.269 A

VCCADAC1_5

VSSADAC

VCCADACBG3_3

VCCVRM[1]

VCCIO[1]

VCCIO[2]

VCC3_3_R30 VCC3_3_R32

DCPSUS1

VCCSUS3_3_AJ30 VCCSUS3_3_AJ32

DCPSUS3_AJ26 DCPSUS3_AJ28

VCCIO[3] VCCVRM[2] VCCVRM[3]

VCCVRM[4]

VCCIO[4]

VCCVRM[5]

VCCIO[5]

VCCIO[6]

VCCIO[7]

VCCIO[8]

VCCIO[9]

VCCIO[10] VCCIO[11]

P45

P43

M31

BB44

AN34

AN35

R30 R32

Y12

AJ30 AJ32

AJ26 AJ28 AK20 AK26 AK28

BE22

AK18

AN11

AK22

AM18 AM20 AM22 AP22 AR22 AT22

+3VS

+1.05VS_+1.5VS_RUN

+1.05VS

+3VS

+1.05VM_PCH_DCPSUS1

+3V_PCH

+1.05VM_PCH_DCPSUS3

+1.05VS

+1.05VS_+1.5VS_RUN

+1.05VS

+1.05VS_+1.5VS_RUN

+1.05VS

UH1G

+1.05VS

CH30

CH32

CH31

10U_0603_6.3V6-M

1

2

1U_0402_6.3V6-K

1

2

CH33

+1.05VS

1U_0402_6.3V6-K

1

2

Layout note: Fanout : 5mil

+1.05VM_PCH_VCCASW

C C

12

1

2

+PCH_VCCDSW

RH179

5.11_0402_1%

CH48

CH48 1U_0402_6.3V6-K

1U_0402_6.3V6-K

CH38

22U_0805_6.3V6-M

1

2

CH39

CH40

1U_0402_6.3V6-K

1

2

Breakout : 10mil

+PCH_VCCDSW +1.05VM_PCH_VCCASW

UH1G

AA24

VCC[1]

AA26

VCC[2]

AD20 AD22 AD24 AD26 AD28 AE18 AE20 AE22 AE24 AE26 AG18 AG20 AG22 AG24

AA18

1.312 A

VCC[3] VCC[4] VCC[5] VCC[6] VCC[7] VCC[8] VCC[9] VCC[10] VCC[11] VCC[12] VCC[13] VCC[14] VCC[15] VCC[16]

Y26

VCC[17]

U14

DCPSUSBYP VCCASW[1]

U18

VCCASW[2]

U20

VCCASW[3]

U22

VCCASW[4]

U24

VCCASW[5]

V18

VCCASW[6]

V20

VCCASW[7]

V22

VCCASW[8]

V24

VCCASW[9]

Y18

VCCASW[10]

Y20

VCCASW[11]

Y22

VCCASW[12]

LYNX-POINT-DH82LPMS_BGA695

SA00005U830

+3VS

CH27

CH43

.01U_0402_16V7-K

1

2

+3V_PCH

+1.05VS

1U_0402_6.3V6-K

1

2

CH28

CH44

CH29

0.1U_0402_10V7-K

1

2

CH45

1U_0402_6.3V6-K

1

2

1 2

0_0603_5%

10U_0603_6.3V6-M

1

2

+3VS

1

2

+1.05VS_+1.5VS_RUN

1

@ CH42

@

2

CH46

CH47

1U_0402_6.3V6-K

10U_0603_6.3V6-M

1

2

10U_0603_6.3V6-M

1

2

LH1

1 2

BLM18PG181SN1D_2P

CH36

0.1U_0402_10V7-K

CH42 10U_0603_6.3V6-M

10U_0603_6.3V6-M

+1.05VS

1

CH35

CH35 1U_0402_6.3V6-K

1U_0402_6.3V6-K

2

+1.05VS_+1.5VS_RUN

1

CH41

@ CH41

@

10U_0603_6.3V6-M

2

+1.05VS

+1.5VS

+1.05VS_+1.5VS_RUN

1

CH34

@ CH34

@

10U_0603_6.3V6-M

2

+1.05VS_+1.5VS_RUN

1

CH37

@ CH37

@

10U_0603_6.3V6-M

2

PCH Power Rail Table (EDS Rev1.0)

Voltage Rail

Voltage

S0 Iccmax Current (A)

1.05V 1.312 AVCC

B B

VCCIO

1.05V

3.629 A

VCCADAC1_5 1.5V 0.07 A

VCCADAC3_3 0.0133 A3.3V

VCCCLK

VCCCLK3_3

+1.05VS_PCH_VCC +1.05VS_PCH_VCCIO

RH180

1

CH51

@ CH51

@

10U_0603_6.3V6-M

2

1 2

0_0402_5%

RH183

1 2

0_0402_5%

+1.05VM_PCH_DCPSUS1

1

CH49

@ CH49

@

1U_0402_6.3V6-K

+1.05VM_PCH_VCCASW +1.05VS_+1.5VS_RUN

+1.05VS +1.05VM_PCH_VCCASW

A A

+1.05VM

1 2

RH181 0_0603_5%@RH181 0_0603_5%@

1 2

RH184 0_0603_5%RH184 0_0603_5%

5

0.67 A

+1.5VS +1.05VS_+1.5VS_RUN

+1.05VS

4

1 2

RH182 0_0603_5%RH182 0_0603_5%

1 2

RH185 0_0603_5%@RH185 0_0603_5%@

0.183 A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/12/05

2

+1.05VM_PCH_DCPSUS3

1

CH50

@ CH50

@

0.1U_0402_10V7-K

2

LC Future Center Secret Data

Deciphered Date

@

2

+1.05VM_PCH_VCCASW

2014/12/05

Title

Size Document Number Rev

Custom

Date: Sheet

VCCVRM 0.183 A

VCC3_3 3.3V 0.133 A

VCCASW 1.05V

VCCSUSHDA 3.3V 0.01 A

VCCSUS3_3 3.3V 0.261 A

VCCDSW3_3

V_PROC_IO 1.05V 0.004 A

PCH_POWER-1

Thursday, July 11, 2013

1.05V 0.306 A

3.3V

0.055 A

1.5V

0.67 A

3.3V 0.022 AVCCSPI

3.3V 0.015 A

E440 NM-A151

E440 NM-A151E440 NM-A151

1

20 57

1.0

of

5

4

3

2

1

CH52

1 2

+3VS

1

CH68

0.1U_0402_10V7-K

2

+3V_PCH

1

2

+1.05VS

1

CH67

CH67 1U_0402_6.3V6-K

1U_0402_6.3V6-K

2

1

CH53

0.1U_0402_10V7-K

2

1

CH58

0.1U_0402_10V7-K

2

CH64

+1.05VM_PCH_VCCASW

+1.05VS_+1.5VS_RUN

LPT_PCH_M_EDS

0.261 A

0.306 A

0.055 A

0.306 A

LPT_PCH_M_EDS

USB

ICC

REV = 5

8 OF 11

GPIO/LPC

Azalia

RTC

CPU

SPI

Fuse

Thermal

0.015 A

0.01 A

0.004 A

0.022 A

VCCSUS3_3_R20 VCCSUS3_3_R22

VCCDSW3_3

DCPSST

VCC3_3_AE14 VCC3_3_AF12

VCC3_3_AG14

VCCIO[16]

VCCSUSHDA

VCCSUS3_3_K8

VCCRTC

DCPRTC[1] DCPRTC[2]

V_PROC_IO[1] V_PROC_IO[2]

VCCSPI

VCC[19] VCC[20]

VCCASW[13]

VCCASW[14]

VCCVRM[7]

VCC3_3_AK30

VCC3_3_AK32

UH1H

D D

C C

+3V_PCH

1

2

CH54

0.1U_0402_10V7-K

+1.05VS

+3V_PCH

CH56

0.1U_0402_10V7-K

+3VS

1

CH57

0.1U_0402_10V7-K

2

1

+1.05VS

CH59

2

CH59

1U_0402_6.3V6-K

+1.05VS_+1.5VS_RUN

1

2

1

2

CH61

10U_0603_6.3V6-M

+PCH_VCC

+PCH_VCCCLK

+PCH_VCCCLK3_3

+PCH_VCCCLK

+1.05VS

+3VS

+1.05VS

+1.05VM_PCH_DCPSUS2

+PCH_VCC

+PCH_VCCCLK

+PCH_VCCCLK3_3

+PCH_VCCCLK

CPI, 14" only

+1.05VS_+1.5VS_RUN +1.05VS

1

CH86

CH86 10P_0402_50V8-J

10P_0402_50V8-J

2

1

CH87

CH87 10P_0402_50V8-J

10P_0402_50V8-J

2

UH1H

R24

VCCSUS3_3_R24

R26

VCCSUS3_3_R26

R28

VCCSUS3_3_R28

U26

VCCSUS3_3_U26

M24

VSS_USB

U35

VCCUSBPLL

L24

VCC3_3_L24

U30

VCCIO[12]

V28

VCCIO[13]

V30

VCCIO[14]

Y30

VCCIO[15]

Y35

DCPSUS2

AF34

VCCVRM[6]

AP45

VCC[18]

Y32

VCCCLK[1]

M29

VCCCLK3_3[1]

L29

VCCCLK3_3[2]

L26

VCCCLK3_3[3]

M26

VCCCLK3_3[4]

U32

VCCCLK3_3[5]

V32

VCCCLK3_3[6]

AD34

VCCCLK[2]

AA30

VCCCLK[3]

AA32

VCCCLK[4]

AD35

VCCCLK[5]

AG30

VCCCLK[6]

AG32

VCCCLK[7]

AD36

VCCCLK[8]

AE30

VCCCLK[9]

AE32

VCCCLK[10]

LYNX-POINT-DH82LPMS_BGA695

SA00005U830

+3V_PCH

R20 R22

A16

AA14

AE14 AF12 AG14

U36

A26

K8

A6

P14 P16

AJ12 AJ14

AD12

P18 P20

L17

R18

AW40

AK30

AK32

0.1U_0402_10V7-K

+3VALW_VCCDSW3_3

CH55 0.1U_0402_10V7-KCH55 0.1U_0402_10V7-K

+3VS

+1.05VS

+3V_PCH

+RTCVCC

CH63 0.1U_0402_10V7-KCH63 0.1U_0402_10V7-K

+1.05VS_PCH_VPROC

+3VM_VCCSPI

+PCH_VCCCFUSE

+1.05VM_PCH_VCCASW

+1.05VS_+1.5VS_RUN

1 2

RH186 0_0402_5%RH186 0_0402_5%

1 2

RH187 0_0402_5%@RH187 0_0402_5%@

+3VS

CH66

CH65

1U_0402_6.3V6-K

0.1U_0402_10V7-K

1

2

1

2

+3VM_VCCSPI

1

2

+3VALW

+3V_PCH

+RTCVCC

1

CH62

CH62 1U_0402_6.3V6-K

1U_0402_6.3V6-K

2

1 2

RH122 0_0402_5%@RH122 0_0402_5%@

1 2

RH126 0_0402_5%RH126 0_0402_5%

+3V_PCH

1

CH60

0.1U_0402_10V7-K

2

+3VS

+3VM

B B

A A

+1.05VM

+1.05VS

4.7UH_LQM18FN4R7M00D_20%

1 2

RH188 0_0402_5%@RH188 0_0402_5%@

1 2

RH120 0_0402_5%@RH120 0_0402_5%@

LH2

5

+1.05VM_PCH_DCPSUS2

1

CH69

@ CH69

@

1U_0402_6.3V6-K

2

+PCH_VCC +PCH_VCCCLK3_3 +PCH_VCCCFUSE

12

CH78

1

2

+PCH_VCC

CH79

1U_0402_6.3V6-K

10U_0603_6.3V6-M

1

2

+1.05VS

+3VS

4

RH189

1 2

0_0805_5%

RH192

1 2

0_0805_5%

CH70

1U_0402_6.3V6-K

1

2

Place near pin Y32,AA30,AA32

CH80

1U_0402_6.3V6-K

1

2

Place near pin M29

CH71

Place near pin AD34

CH81

Place near pin L29

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

1U_0402_6.3V6-K

1

2

1U_0402_6.3V6-K

1

2

Issued Date

CH72

Place near pin AD35,AD36

CH82

Place near pin L26,M26

3

1U_0402_6.3V6-K

1

2

Place near pin AG30,AG32,AE30,AE32

1U_0402_6.3V6-K

1

2

Place near pin U32,V32

CH73

CH83

1U_0402_6.3V6-K

1

2

1U_0402_6.3V6-K

1

2

2012/12/05

CH74

CH84

1U_0402_6.3V6-K

1

2

1U_0402_6.3V6-K

1

2

+PCH_VCCCLK

+PCH_VCCCLK3_3

LC Future Center Secret Data

Deciphered Date

+1.05VS_PCH_VPROC

2014/12/05

2

CH75

+PCH_VCCCFUSE

0.1U_0402_10V7-K

1

2

+1.05VS_PCH_VPROC

CH77

CH76

1U_0402_6.3V6-K

0.1U_0402_10V7-K

1

2

CH85

1U_0402_6.3V6-K

1

20130125 --> Need connect to +1.05VS

2

Title

PCH_POWER-2

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

RH190

1 2

0_0805_5%

1 2

RH191 0_0805_5%@RH191 0_0805_5%@

1 2

RH193 0_0805_5%RH193 0_0805_5%

E440 NM-A151

E440 NM-A151E440 NM-A151

+1.05VS

+3VS

+1.05VS

1.0

21 57

1

21 57

1.0

of

+1.05VM_PCH_DCPSUS2 +PCH_VCCCLK +V_VPROC

Lenovo ThinkPad E440 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual