Lenovo ThinkPad E440 Schematic

A

1 1

B

C

D

E

2 2

NM-A151 Rev1.0 Schematic

Intel Haswell Processor with DDRIII + Lynx point PCH

nVIDIA N14P-GV2/ N14M-GL

2013-07-11 Rev 1.0

3 3

www.rosefix.com

4 4

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

C

2012/12/05

LC Future Center Secret Data

Deciphered Date

D

2014/12/05

Title

Cover Page

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

E440 NM-A151

E440 NM-A151E440 NM-A151

E

1 57

of

1.0

A

B

C

D

E

N14P-GV2 2G N14M-GL 1G

VRAM 128M*16 *4 VRAM 256M*16 *4

1 1

Page 23,24,25,26,27,28,29,30,31,32,33

Small Board

2 2

Realtek RTL8111G

LAN Board

Realtek RTS5227 USB Charge Port

Card Reader Board

ODD Board For 15"

Card Reader Board

3 3

Power Circuit DC/DC

Page 52,53,54,55,56,57, 58,59,60,61,62

DC/DC Interface CKT.

Finger Print Conn

POWER/B Conn.

ODD/B Conn.

4 4

Touch Pad Conn

Page 51

Page 56

Page 40

page 41

Page 56

Page 55

A

SIM Conn

Track Point ConnClick Pad Conn

Page 54

Page 53

PCI-Express 16X Gen3

PEG 0~7

HDMI Conn.

HDMI1.4b

Page 36

eDP Conn.

Page 35

CRT Conn.

Page 35

JRJ45 Conn.

PCIe port 4

Page 42

JUCR Conn.

PCIe port 3

SATA ODD For 15"

SATA Port 2

SATA ODD For 14"

SATA Port 2

SATA HDD

SATA Port 1

Page 43

Page 44

Page 45

Page 44

SPI ROM (4MB+8MB)

Page 17

B

HDMI

1.65GT/s

eDP

3.3V 5.4GT/s

CRT

PCIe Gen1

1.5V 2.5GT/s

PCIe Gen1

1.5V 2.5GT/S

SATA Gen1 Port2 5V 3GHz(150MB/s)

SATA Gen3 Port 0 5V 6GHz(600MB/s)

SPI BUS

3.3V 33MHz

Debug Port

Page 39

G-Sensor LIS34ALTR

Intel CPU Haswell

rPGA-989

37.5mm*37.5mm

Page 5,6,7,8,9,10,11

DMI *4 5GT/s

Intel PCH Lynx point

695 ball FCBGA 20mm*20mm

Page 14,15,16,17,18,19,20,21,22

LPC BUS

3.3V 33MHz

EC ITE IT8586E-CX

Int.KBD

Issued Date

Int. K/B

Page 46

C

ADC

Page 47

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

FDI *2 5GT/s

USB 3.0 5V 500MB/S

USB 2.0 5V 60MB/S

PCIe Gen1 5V 2.5GT/S

SATA Gen3

5V 6GHz(600MB/s)

HD Audio

3.3V 24MHz

SMBus

PS2

Page 47

SMBus

Thermal Sensor EMC 1403

2012/12/05

SMBus Port3

Page 40

LC Future Center Secret Data

Memory BUS (DDRIII) Dual Channel

1.35V DDRIIIL 1066/1333/1600 MT/s

DP

Docking Conn

USB 3.0 Port 1

Page 51

USB Left

USB 3.0 Port 2 USB 3.0 Port 5

Page 50

Touch panel

USB 2.0 Port 4

PCIeMini Card WLAN

PCIe Port 5

USB 2.0 Port 10

Page 39

Sub Board

Codec COX 20751

Page 45

Security EEPROM

SMBus Port3

Page 41

Click Pad

SMBus Port3

Page 47 Page 48

2014/12/05

Deciphered Date

2014/12/05

D

DDR3-SO-DIMM X2

BANK 0, 1, 2, 3

UP TO 16G

USB Right

USB 2.0 Port 5

Page 50

mSATA SSD

SATA Port 0

Page 37

PCIeMini Card WWAN

USB 2.0 Port 11

Page 38

SPK Conn.

Int. Comb Conn. (Ext MIC & HP)

Track Point

Title

Block Diagram

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

Int. Camera

USB 2.0 Port 13

Page 46

Page 34

SMBus

E440 NM-A151

E440 NM-A151E440 NM-A151

Page 34Page 51

E

2 57

of

1.0

A

B

C

D

E

Voltage Rails

Power Plane

1 1

State

S0

S3

2 2

S5 S4/AC Only

S5 S4 Battery only

S5 S4 AC & Battery don't exist

SMBUS Control Table

3 3

EC_SMB_DA1

EC_SMB_CK2

EC_SMB_DA2

PM_SMBCLK PM_SMBDATA

( O --> Means ON , X --> Means OFF )

+3VALW

B+

+1.5V

+5VALW

O

O O O

O

X X

SOURCE

IT8580EEC_SMB_CK1

+3VALW

IT8580E

+3VS

PCH

+3V_PCH

Main VGA

+3VS +3VS

2nd VGA

X

V

BATT SODIMM

X X XV

+3VALW

V

X

IT8580E

X X X X X

+5VS

+3VS

+1.5VS

+VCCSA

+V1.5S_VCCP

+CPU_CORE

+VGA_CORE

+GFX_CORE

+1.8VS

+1.05VS

+0.75VS

+3.3VS_VGA

+1.5VS_VGA

+1.05VS_VGA

OO

X

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

USB Port Table

EHCI1

X

EHCI2

X

V V

+3VS

WLAN WiMAX

X

V

X

Thermal Sensor

V

+3VS

PCH

V

+3V_PCH

+3V_PCH+3VS

CP Module

XX

X

V

+3VS

SIGNAL

SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

HIGH HIGH HIGH HIGH

USB 3.0USB 2.0 Port

XHCI

1

2

3

4

0

1

5 6

7 8

9 10 11 12 13

PCIE PORT LIST

Port Device

1 2 3 4 5 6 7 8

LOW

LOW LOW LOW LOW

HIGH

LOWLOWLOW

HIGHHIGHHIGH

HIGH

4 External USB Port

Camera

USB Port (Right Side)

USB Port (Left Side)

USB Port (Right Side)

Mini Card(WLAN)

Blue Tooth

LAN WLAN

Card Reader

ON

OFF

ON ON

ON

OFF

ON

BOM Structure Table

HDMI@ CHG@

NOCHG@ CMOS@ 8171@

8171S@

SURGE@

X76@ GC6@ NOGC6@

AOAC@ KBL@ ME@

SLI@

DS3@

S3@

GT@

@

EDP@

daul@

LOW

OFF

BTO ItemBOM Structure

HDMI part

USB charger part

No USB charger part

NV no CG6 support part

CMOS Camera part

QCA8171 LAN part

QCA8171 LAN surge part

QCA8171&8172 LAN surge part

X76 Level part for VRAM

NV CG6 support part

AOAC support part

K/B Light part

ME part

For SLI function part

Deep S3 support part

For S3 function part

NV chip part

Unpop

Support EDP panel function

Support daul channel panel function

A

Address

0001 011X b

EC SM Bus2 address

B

Address

1001_101xb

0x9E 0x9C

Device

Thermal Sensor EMC1403-2

Master VGA

Slave VGA

PCH SM Bus address

Device Address

DDR DIMM0

DDR DIMM2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

C

1001 000Xb

1001 010Xb

2012/12/05

LC Future Center Secret Data

Deciphered Date

D

2014/12/05

4 4

EC SM Bus1 address

Device

Smart Battery

ZZZ1

DA80000TV00

Title

Notes List

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

E440 NM-A151

E440 NM-A151E440 NM-A151

E

3 57

of

1.0

5

4

3

2

1

Hot plug detect for IFP link E

VGA and GDDR5 Voltage Rails (N13Px GPIO)

GPIO I/O ACTIVE Function Description

GPIO0

D D

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

GPIO8

GPIO9

GPIO10

C C

GPIO11

GPIO12

GPIO13

GPIO14

GPIO15

GPIO16

GPIO17

GPIO18

GPIO19

B B

+1.05VS_VGA

OUT GPU VID4-

OUT

I/O

OUT

IN

OUT

IN

OUT

IN

+3VS_VGA

+VGA_CORE

+1.5VS_VGA

GPU VID3OUT

-

VGA_BL_PWM

-

VGA_ENVDD

- VGA_ENBKL

-

GPU VID1

-

GPU VID2

DPRSLPVR_VGA

-

Thermal Catastrophic Over Temperature

-

GPIO9

-

Memory VREF Control

GPU VID0-OUT

AC Power Detect Input

GPU VID5-

FB_CLAMP_TOGGLE_REQ#

-

N/A (100K pull low)

FRMLCK#

-

N/A

-

dGPU_HDMI_HPD

HPD_IRQ

-

tNVVDD >0

tFBVDDQ >0

tPEX_VDD >0

1. all power rail ramp up time should be larger than 40us

(10K pull High)

Performance Mode P0 TDP at Tj = 102 C* (GDDR5)

GPU Mem NVCLK (4) (1,5) (6)

Products

N13X 128bit 1GB GDDR5

Physical Strapping pin ROM_SCLK

(W) (W) (MHz)

ROM_SI

ROM_SO FB[0]

STRAP0

STRAP1

STRAP2

STRAP3

STRAP4

/MCLK NVVDD

(V) (A) (W) (A) (W)

TBD TBDTBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

Power Rail

+3VS_VGA

Logical Strapping Bit3

PCI_DEVID[4]

FB[1]

PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]

SOR3_EXPOSED

RESERVED PCIE_SPEED_

Device ID

N13P-GT (28nm)

0x0FDB

SMB_ALT_ADDR

(ROM_SO Bit 1)

FBVDD

Logical Strapping Bit2 SUB_VENDOR

USER[2] USER[1] USER[0]USER[3]

3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1]3GIO_PAD_CFG_ADR[3]

SOR2_EXPOSED SOR1_EXPOSED

CHANGE_GEN3

setting

0

1

ROM_SO ROM_SCLK

GPU

N13P-GT1 28nm

GPU

FB Memory (GDDR5)

Samsung 2500MHz

Hynix 2500MHz

Samsung 2500MHz

2500MHz

PU 25K

PU 45KPU 10K PD 10K

PU 25K PD 35KPU 45KPU 20K PD 10K PD 5K PD 10K

K4G10325FG-HC04

32Mx32

H5GQ1H24BFR-T2C

32Mx32 PD 35K

K4G20325FD-FC04

64Mx32

H5GQ2H24MFR-T2CHynix

64Mx32

PD 35K

N13P-GT

ROM_SI

PD 45K

PD 30K

PD 25K

FBVDDQ PCI Express I/O and (GPU+Mem) (1.35V)(1.35V)

(A) (W) (W)(mA) (W) (W) (W)(mA) (mA) (mA)

I2C Slave addrees ID

0x9E

0x9C

STRAP2STRAP1STRAP0

STRAP3

PU 5K PD 10K

(1.05V)

Logical Strapping Bit1

SLOT_CLK_CFG

RAM_CFG[1]RAM_CFG[3] RAM_CFG[2]

PLLVDD

I/O and PLLVDD

Logical Strapping Bit0

PEX_PLL_EN_TERM

RAM_CFG[0]

VGA_DEVICESMB_ALT_ADDR

3GIO_PAD_CFG_ADR[0]

PCIE_MAX_SPEED DP_PLL_VDD33V

SOR0_EXPOSED

STRAP4

Master

Slave

Other

(3.3V)(1.05V)(1.8V)

Other Power rail

A A

+3VS_VGA

Tpower-off <10ms

1.all GPU power rails should be turned off within 10ms

2. Optimus system VDD33 avoids drop down earlier than NVDD and FBVDDQ

5

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/12/05

LC Future Center Secret Data

Deciphered Date

2

2014/12/05

Title

VGA Notes List

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

E440 NM-A151

E440 NM-A151E440 NM-A151

1

4 57

of

1.0

5

4

3

2

1

D D

Haswell rPGA EDS

JCPU1A

ME@

DMI_CRX_PTX_N[3:0]<15>

DMI_CRX_PTX_P[3:0]<15>

DMI_CTX_PRX_N[3:0]<15>

DMI_CTX_PRX_P[3:0]<15>

C C

FDI_CSYNC<15> FDI_INT<15>

B B

DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3

DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3

DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3

DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3

FDI_CSYNC FDI_INT

D21

DMI_RXN_0

C21

DMI_RXN_1

B21

DMI_RXN_2

A21

DMI_RXN_3

D20

DMI_RXP_0

C20

DMI_RXP_1

B20

DMI_RXP_2

A20

DMI_RXP_3

D18

DMI_TXN_0

C17

DMI_TXN_1

B17

DMI_TXN_2

A17

DMI_TXN_3

D17

DMI_TXP_0

C18

DMI_TXP_1

B18

DMI_TXP_2

A18

DMI_TXP_3

H29

FDI_CSYNC

J29

DISP_INT

INTEL_HASWELL_HASWELL

DMI FDI

PEG

1 OF 9

PEG_RCOMP

PEG_RXN_10 PEG_RXN_11 PEG_RXN_12 PEG_RXN_13 PEG_RXN_14 PEG_RXN_15

PEG_RXP_10 PEG_RXP_11 PEG_RXP_12 PEG_RXP_13 PEG_RXP_14 PEG_RXP_15

PEG_TXN_10 PEG_TXN_11 PEG_TXN_12 PEG_TXN_13 PEG_TXN_14 PEG_TXN_15

PEG_TXP_10 PEG_TXP_11 PEG_TXP_12 PEG_TXP_13 PEG_TXP_14 PEG_TXP_15

PEG_RXN_0 PEG_RXN_1 PEG_RXN_2 PEG_RXN_3 PEG_RXN_4 PEG_RXN_5 PEG_RXN_6 PEG_RXN_7 PEG_RXN_8 PEG_RXN_9

PEG_RXP_0 PEG_RXP_1 PEG_RXP_2 PEG_RXP_3 PEG_RXP_4 PEG_RXP_5 PEG_RXP_6 PEG_RXP_7 PEG_RXP_8 PEG_RXP_9

PEG_TXN_0 PEG_TXN_1 PEG_TXN_2 PEG_TXN_3 PEG_TXN_4 PEG_TXN_5 PEG_TXN_6 PEG_TXN_7 PEG_TXN_8 PEG_TXN_9

PEG_TXP_0 PEG_TXP_1 PEG_TXP_2 PEG_TXP_3 PEG_TXP_4 PEG_TXP_5 PEG_TXP_6 PEG_TXP_7 PEG_TXP_8 PEG_TXP_9

E23 M29 K28 M31 L30 M33 L32 M35 L34 E29 D28 E31 D30 E35 D34 E33 E32 L29 L28 L31 K30 L33 K32 L35 K34 F29 E28 F31 E30 F35 E34 F33 D32 H35 H34 J33 H32 J31 G30 C33 B32 B31 A30 B29 A28 B27 A26 B25 A24 J35 G34 H33 G32 H31 H30 B33 A32 C31 B30 C29 B28 C27 B26 C25 B24

PEG_COMP PCIE_CRX_GTX_N0 PCIE_CRX_GTX_N1 PCIE_CRX_GTX_N2 PCIE_CRX_GTX_N3 PCIE_CRX_GTX_N4 PCIE_CRX_GTX_N5 PCIE_CRX_GTX_N6 PCIE_CRX_GTX_N7

PCIE_CRX_GTX_P0 PCIE_CRX_GTX_P1 PCIE_CRX_GTX_P2 PCIE_CRX_GTX_P3 PCIE_CRX_GTX_P4 PCIE_CRX_GTX_P5 PCIE_CRX_GTX_P6 PCIE_CRX_GTX_P7

PCIE_CTX_GRX_N0 PCIE_CTX_GRX_N1 PCIE_CTX_GRX_N2 PCIE_CTX_GRX_N3 PCIE_CTX_GRX_N4 PCIE_CTX_GRX_N5 PCIE_CTX_GRX_N6 PCIE_CTX_GRX_N7

PCIE_CTX_GRX_P0 PCIE_CTX_GRX_P1 PCIE_CTX_GRX_P2 PCIE_CTX_GRX_P3 PCIE_CTX_GRX_P4 PCIE_CTX_GRX_P5 PCIE_CTX_GRX_P6 PCIE_CTX_GRX_P7

PEG_COMP

CAD Note: Trace width=12 mils ,Spacing=15mils Max length= 400 mils.

CC1 0.22U_0 402_10V6-KDIS@CC1 0.22U_0402_10V6-KDIS@ CC2 0.22U_0 402_10V6-KDIS@CC2 0.22U_0402_10V6-KDIS@ CC3 0.22U_0 402_10V6-KDIS@CC3 0.22U_0402_10V6-KDIS@ CC4 0.22U_0 402_10V6-KDIS@CC4 0.22U_0402_10V6-KDIS@ CC5 0.22U_0402_10V6-KDIS@CC5 0.22U_0402_10V6-KDIS@ CC6 0.22U_0 402_10V6-KDIS@CC6 0.22U_0402_10V6-KDIS@ CC7 0.22U_0 402_10V6-KDIS@CC7 0.22U_0402_10V6-KDIS@ CC8 0.22U_0 402_10V6-KDIS@CC8 0.22U_0402_10V6-KDIS@

CC9 0.22U_0 402_10V6-KDIS@CC9 0.22U_0402_10V6-KDIS@ CC10 0.22U_0402_10V6-KDIS@CC10 0.22U_0402_10V6-KDIS@ CC11 0.22U_0402_10V6-KDIS@CC11 0.22U_0402_10V6-KDIS@ CC12 0.22U_0402_10V6-KDIS@CC12 0.22U_0402_10V6-KDIS@ CC13 0.22U_0402_10V6-KDIS@CC13 0.22U_0402_10V6-KDIS@ CC14 0.22U_0402_10V6-KDIS@CC14 0.22U_0402_10V6-KDIS@ CC15 0.22U_0402_10V6-KDIS@CC15 0.22U_0402_10V6-KDIS@ CC16 0.22U_0402_10V6-KDIS@CC16 0.22U_0402_10V6-KDIS@

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

1 2

RC1 24.9_0402_1%RC1 24.9_0402_1%

PCIE_CRX_GTX_N[7:0] <23>

PCIE_CRX_GTX_P[7:0] <23>

PCIE_CTX_C_GRX_N0 PCIE_CTX_C_GRX_N1 PCIE_CTX_C_GRX_N2 PCIE_CTX_C_GRX_N3 PCIE_CTX_C_GRX_N4 PCIE_CTX_C_GRX_N5 PCIE_CTX_C_GRX_N6 PCIE_CTX_C_GRX_N7

PCIE_CTX_C_GRX_P0 PCIE_CTX_C_GRX_P1 PCIE_CTX_C_GRX_P2 PCIE_CTX_C_GRX_P3 PCIE_CTX_C_GRX_P4 PCIE_CTX_C_GRX_P5 PCIE_CTX_C_GRX_P6 PCIE_CTX_C_GRX_P7

+VCCIOA_OUT

PCIE_CTX_C_GRX_N[7:0] <23>

PCIE_CTX_C_GRX_P[7:0] <23>

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/12/05

LC Future Center Secret Data

Deciphered Date

2

2014/12/05

Title

CPU_DMI/PEG/FDI

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

E440 NM-A151

E440 NM-A151E440 NM-A151

1

5 57

of

1.0

5

D D

4

3

2

1

Reserve for VCCST

+1.05VS_PCH_VPROC

+VCCIO_OUT

C C

1 2

RC3 62_0402_5%RC3 62_0402_5%

1 2

RC7 10K_0402_5%RC7 10K_0402_5%

Buffered Reset to CPU, 1.5V

135MHz

100 MHz PCIe 3.0

H_PROCHOT#

H_CPUPWRGD_R

CLK_CPU_DPLL#<16> CLK_CPU_DPLL<16> CLK_CPU_SSC_DPLL#<16> CLK_CPU_SSC_DPLL<16> CLK_CPU_DMI#<16> CLK_CPU_DMI<16>

H_PECI<48>

H_PROCHOT#<48> H_THERMTRIP#<19>

H_PM_SYNC<15> H_CPUPWRGD<19>

PLTRST_PROC#<19>

1 2

RC8 56_0402_5%RC8 56_0402_5%

1 2

RC10 0_0402_5%RC10 0_0402_5%

1 2

RC11 0_0402_5%RC11 0_0402_5%

1 2

RC12 0_0402_5%RC12 0_0402_5%

1 2

RC13 0_0402_5%RC13 0_0402_5%

1 2

RC14 0_0402_5%RC14 0_0402_5%

1 2

RC15 0_0402_5%RC15 0_0402_5%

1

CC41

@ CC41

@

0.1U_0402_25V6-K

2

H_PECI

H_PROCHOT#_R H_THERMTRIP#

H_PM_SYNC H_CPUPWRGD_R SM_DRAMPWROK CPU_PLTRSTIN#

CPU_DPLL# CPU_DPLL CPU_SSC_DPLL# CPU_SSC_DPLL CLK_CPU_DMI# CLK_CPU_DMI

Haswell rPGA EDS

JCPU1B

ME@

JCPU1B

ME@

MISC

AP32

1

T1T1

SKTOCC

AN32

CATERR

AR27

PECI

AK31

FC_AK31

AM30

PROCHOT

AM35

THERMTRIP

AT28

PM_SYNC

AL34

PWRGOOD

AC10

SM_DRAMPWROK

AT26

PLTRSTIN

G28

DPLL_REF_CLKN

H28

DPLL_REF_CLKP

F27

SSC_DPLL_REF_CLKN

E27

SSC_DPLL_REF_CLKP

D26

BCLKN

E26

BCLKP

INTEL_HASWELL_HASWELL

MISC

2 OF 9

DDR3

CLOCK

SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2

SM_DRAMRST

JTAG

BPM_N_0 BPM_N_1 BPM_N_2 BPM_N_3 BPM_N_4 BPM_N_5 BPM_N_6 BPM_N_7

PRDY PREQ

TCK TMS

TRST

TDO DBR

TDI

THERMAL

PWR

DDR3 COMPENSATION SIGNALS CAD Note: Trace width=12~15 mil, Spcing=20 mils Max trace length= 500 mil

AP3

SM_RCOMP0

AR3

SM_RCOMP1

AP2

SM_RCOMP2

AN3

H_DRAMRST# DDR3_DRAMRST#

AR29

XDP_PRDY#

AT29

XDP_PREQ#

AM34

XDP_TCLK

AN33

XDP_TMS

AM33

XDP_TRST#

AM31

XDP_TDI

AL33

XDP_TDO

AP33

XDP_DBRESET#

AR30 AN31 AN29 AP31 AP30 AN28 AP29 AP28

TP closer to CPU XDP Connector reserve test point

1 2

RC2 100_ 0402_1%RC2 100_0402_1%

1 2

RC4 75_0 402_1%RC4 75_0 402_1%

1 2

RC5 100_ 0402_1%RC5 100_0402_1%

1 2

RC6 0_04 02_5%RC6 0_0402_5%

1

T3 @T3 @

1

T4 @T4 @

1

T5 @T5 @

1

T6 @T6 @

1

CC43

CC43 330P_0402_50V7-K

330P_0402_50V7-K

2

XDP_TDO

XDP_TCLK

XDP_TRST#

DDR3_DRAMRST# <11,12>

ESD

1 2

RC16 51_0402_1%RC16 51_0402_1%

1 2

RC17 51_0402_1%RC17 51_0402_1%

1 2

RC18 51_0402_1%RC18 51_0402_1%

+1.05VS

XDP_DBRESET#

PU/PD for JTAG signals Place R closer to CPU

B B

1 2

RC9 1K_0402_1%RC9 1K_0402_1%

+3VS

SM_DRAMPWROK Topology for platforms supporting Deep S3

+1.35V

12

RC21

1.8K_0402_1%

1 2

RC22 0_0402_5%RC22 0_0402_5%

SM_DRAMPWROK rise and fall time must be < 50ns

12

measured between VDDQ *0.15 and VDDQ *0.47.

RC23

3.3K_0402_1%

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Issued Date

Close to JCPU. AC10

SM_DRAMPWROK

1

CC44

CC44 330P_0402_50V7-K

330P_0402_50V7-K

2

LC Future Center Secret Data

2012/12/05

3

Deciphered Date

2

SM_DRAMPWROK

2014/12/05

ESD

Title

CPU_JTAG/XDP/CLK

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

E440 NM-A151

E440 NM-A151E440 NM-A151

1

6 57

of

1.0

RC20

RC20 100K_0402_5%

100K_0402_5%

RC24 0_0402_5%@RC24 0_0402_5%@

+3V_PCH+3V_PCH

5

1

B

2

A

3

1 2

P

G

1

@

CC17

0.1U_0402_25V6-K

2

4

O

UC1

UC1 74AHC1G09GW_TSSOP5

74AHC1G09GW_TSSOP5

4

DRAMPWROK_AND

+3V_PCH

12

RC19

RC19 200_0402_1%

200_0402_1%

DRAMPWROK<15>

A A

5

12

5

4

3

2

1

D D

DDRA_DQ[0..63]<11>

C C

B B

+V_SM_VREF +VREF_DQA_M3 +VREF_DQB_M3

DDRA_DQ0 DDRA_DQ1 DDRA_DQ2 DDRA_DQ3 DDRA_DQ4 DDRA_DQ5 DDRA_DQ6 DDRA_DQ7 DDRA_DQ8 DDRA_DQ9 DDRA_DQ10 DDRA_DQ11 DDRA_DQ12 DDRA_DQ13 DDRA_DQ14 DDRA_DQ15 DDRA_DQ16 DDRA_DQ17 DDRA_DQ18 DDRA_DQ19 DDRA_DQ20 DDRA_DQ21 DDRA_DQ22 DDRA_DQ23 DDRA_DQ24 DDRA_DQ25 DDRA_DQ26 DDRA_DQ27 DDRA_DQ28 DDRA_DQ29 DDRA_DQ30 DDRA_DQ31 DDRA_DQ32 DDRA_DQ33 DDRA_DQ34 DDRA_DQ35 DDRA_DQ36 DDRA_DQ37 DDRA_DQ38 DDRA_DQ39 DDRA_DQ40 DDRA_DQ41 DDRA_DQ42 DDRA_DQ43 DDRA_DQ44 DDRA_DQ45 DDRA_DQ46 DDRA_DQ47 DDRA_DQ48 DDRA_DQ49 DDRA_DQ50 DDRA_DQ51 DDRA_DQ52 DDRA_DQ53 DDRA_DQ54 DDRA_DQ55 DDRA_DQ56 DDRA_DQ57 DDRA_DQ58 DDRA_DQ59 DDRA_DQ60 DDRA_DQ61 DDRA_DQ62 DDRA_DQ63

JCPU1C

AR15

SA_DQ_0

AT14

SA_DQ_1

AM14

SA_DQ_2

AN14

SA_DQ_3

AT15

SA_DQ_4

AR14

SA_DQ_5

AN15

SA_DQ_6

AM15

SA_DQ_7

AM9

SA_DQ_8

AN9

SA_DQ_9

AM8

SA_DQ_10

AN8

SA_DQ_11

AR9

SA_DQ_12

AT9

SA_DQ_13

AR8

SA_DQ_14

AT8

SA_DQ_15

AJ9

SA_DQ_16

AK9

SA_DQ_17

AJ6

SA_DQ_18

AK6

SA_DQ_19

AJ10

SA_DQ_20

AK10

SA_DQ_21

AJ7

SA_DQ_22

AK7

SA_DQ_23

AF4

SA_DQ_24

AF5

SA_DQ_25

AF1

SA_DQ_26

AF2

SA_DQ_27

AG4

SA_DQ_28

AG5

SA_DQ_29

AG1

SA_DQ_30

AG2

SA_DQ_31

J1

SA_DQ_32

J2

SA_DQ_33

J5

SA_DQ_34

H5

SA_DQ_35

H2

SA_DQ_36

H1

SA_DQ_37

J4

SA_DQ_38

H4

SA_DQ_39

F2

SA_DQ_40

F1

SA_DQ_41

D2

SA_DQ_42

D3

SA_DQ_43

D1

SA_DQ_44

F3

SA_DQ_45

C3

SA_DQ_46

B3

SA_DQ_47

B5

SA_DQ_48

E6

SA_DQ_49

A5

SA_DQ_50

D6

SA_DQ_51

D5

SA_DQ_52

E5

SA_DQ_53

B6

SA_DQ_54

A6

SA_DQ_55

E12

SA_DQ_56

D12

SA_DQ_57

B11

SA_DQ_58

A11

SA_DQ_59

E11

SA_DQ_60

D11

SA_DQ_61

B12

SA_DQ_62

A12

SA_DQ_63

AM3

SM_VREF

F16

SA_DIMM_VREFDQ

F13

SB_DIMM_VREFDQ

INTEL_HASWELL_HASWELL

ME@

Haswell rPGA EDS

SA_CK_N_0 SA_CK_P_0

SA_CKE_0 SA_CK_N_1 SA_CK_P_1

SA_CKE_1 SA_CK_N_2 SA_CK_P_2

SA_CKE_2 SA_CK_N_3 SA_CK_P_3

SA_CKE_3

SA_CS_N_0 SA_CS_N_1 SA_CS_N_2 SA_CS_N_3

SA_ODT_0

SA_ODT_1

SA_ODT_2

SA_ODT_3

SA_BS_0 SA_BS_1 SA_BS_2

SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8

SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14 SA_MA_15

SA_DQS_N_0 SA_DQS_N_1 SA_DQS_N_2 SA_DQS_N_3 SA_DQS_N_4 SA_DQS_N_5 SA_DQS_N_6 SA_DQS_N_7 SA_DQS_P_0 SA_DQS_P_1 SA_DQS_P_2 SA_DQS_P_3 SA_DQS_P_4 SA_DQS_P_5 SA_DQS_P_6 SA_DQS_P_7

3 OF 9

RSVD_1

VSS_1

SA_RAS

SA_WE

SA_CAS

AC7 U4 V4 AD9 U3 V3 AC9 U2 V2 AD8 U1 V1 AC8

M7 L9 M9 M10 M8 L7 L8 L10 V5 U5 AD1

V10 U6 U7 U8

V8 AC6 V9 U9 AC5 AC4 AD6 AC3 AD5 AC2 V6 AC1 AD4 V7 AD3 AD2

AP15 AP8 AJ8 AF3 J3 E2 C5 C11 AP14 AP9 AK8 AG3 H3 E3 C6 C12

DDRA_CLK0# DDRA_CLK0 DDRA_CKE0 DDRA_CLK1# DDRA_CLK1 DDRA_CKE1

DDRA_CS0# DDRA_CS1#

DDRA_ODT0 DDRA_ODT1

DDRA_BS0# DDRA_BS1# DDRA_BS2#

DDRA_RAS# DDRA_WE# DDRA_CAS#

DDRA_MA0 DDRA_MA1 DDRA_MA2 DDRA_MA3 DDRA_MA4 DDRA_MA5 DDRA_MA6 DDRA_MA7 DDRA_MA8 DDRA_MA9 DDRA_MA10 DDRA_MA11 DDRA_MA12 DDRA_MA13 DDRA_MA14 DDRA_MA15

DDRA_DQS#0 DDRA_DQS#1 DDRA_DQS#2 DDRA_DQS#3 DDRA_DQS#4 DDRA_DQS#5 DDRA_DQS#6 DDRA_DQS#7 DDRA_DQS0 DDRA_DQS1 DDRA_DQS2 DDRA_DQS3 DDRA_DQS4 DDRA_DQS5 DDRA_DQS6 DDRA_DQS7

DDRA_CLK0# <11> DDRA_CLK0 <11> DDRA_CKE0 <11> DDRA_CLK1# <11> DDRA_CLK1 <11> DDRA_CKE1 <11>

DDRA_CS0# <11> DDRA_CS1# <11>

DDRA_ODT0 <11> DDRA_ODT1 <11>

DDRA_BS0# <11> DDRA_BS1# <11> DDRA_BS2# <11>

DDRA_RAS# <11> DDRA_WE# <11> DDRA_CAS# <11>

DDRA_DQS#[0..7] <11>

DDRA_DQS[0..7] <11>

Haswell rPGA EDS

JCPU1D

ME@

JCPU1D

DDRB_DQ[0..63]<12>

DDRB_DQ0 DDRB_DQ1 DDRB_DQ2 DDRB_DQ3 DDRB_DQ4 DDRB_DQ5 DDRB_DQ6 DDRB_DQ7 DDRB_DQ8 DDRB_DQ9 DDRB_DQ10 DDRB_DQ11 DDRB_DQ12 DDRB_DQ13 DDRB_DQ14 DDRB_DQ15 DDRB_DQ16 DDRB_DQ17 DDRB_DQ18 DDRB_DQ19 DDRB_DQ20 DDRB_DQ21 DDRB_DQ22 DDRB_DQ23 DDRB_DQ24 DDRB_DQ25 DDRB_DQ26 DDRB_DQ27 DDRB_DQ28 DDRB_DQ29 DDRB_DQ30 DDRB_DQ31 DDRB_DQ32 DDRB_DQ33 DDRB_DQ34 DDRB_DQ35 DDRB_DQ36 DDRB_DQ37 DDRB_DQ38 DDRB_DQ39 DDRB_DQ40 DDRB_DQ41 DDRB_DQ42 DDRB_DQ43 DDRB_DQ44 DDRB_DQ45 DDRB_DQ46 DDRB_DQ47 DDRB_DQ48 DDRB_DQ49 DDRB_DQ50 DDRB_DQ51 DDRB_DQ52 DDRB_DQ53 DDRB_DQ54 DDRB_DQ55 DDRB_DQ56 DDRB_DQ57 DDRB_DQ58 DDRB_DQ59 DDRB_DQ60 DDRB_DQ61 DDRB_DQ62 DDRB_DQ63

AR18 AT18 AM17 AM18 AR17 AT17 AN17 AN18 AT12 AR12 AN12 AM11 AT11 AR11 AM12 AN11

AR5 AR6 AM5 AM6 AT5 AT6 AN5 AN6

AK4

AM1 AN1 AK2 AK1

G10

D15

D14

AJ4

AJ1 AJ2

L2

M2

L4

M4

L1

M1

L5 M5 G7

J8 G8 G9

J7

J9

J10

A8

B8

A9

B9 D8

E8 D9

E9

E15

A15 B15 E14

A14 B14

ME@

SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63

INTEL_HASWELL_HASWELL

Haswell rPGA EDS

SB_CKE_0

SB_CKE_1

SB_CKE_2

SB_CKE_3

SB_CS_N_0 SB_CS_N_1 SB_CS_N_2 SB_CS_N_3

SB_ODT_0 SB_ODT_1 SB_ODT_2 SB_ODT_3

SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14 SB_MA_15

SB_DQS_N_0 SB_DQS_N_1 SB_DQS_N_2 SB_DQS_N_3 SB_DQS_N_4 SB_DQS_N_5 SB_DQS_N_6 SB_DQS_N_7 SB_DQS_P_0 SB_DQS_P_1 SB_DQS_P_2 SB_DQS_P_3 SB_DQS_P_4 SB_DQS_P_5 SB_DQS_P_6 SB_DQS_P_7

4 OF 9

RSVD_2

SB_CKN0

SB_CK0

SB_CKN1

SB_CK1

SB_CKN2

SB_CK2

SB_CKN3

SB_CK3

SB_BS_0 SB_BS_1 SB_BS_2

VSS_2

SB_RAS

SB_WE

SB_CAS

SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9

AG8 Y4 AA4 AF10 Y3 AA3 AG10 Y2 AA2 AG9 Y1 AA1 AF9

P4 R2 P3 P1

R4 R3 R1 P2 R7 P8 AA9

R10 R6 P6 P7

R8 Y5 Y10 AA5 Y7 AA6 Y6 AA7 Y8 AA10 R9 Y9 AF7 P9 AA8 AG7

AP18 AP11 AP5 AJ3 L3 H9 C8 C14 AP17 AP12 AP6 AK3 M3 H8 C9 C15

DDRB_CLK0# DDRB_CLK0 DDRB_CKE0 DDRB_CLK1# DDRB_CLK1 DDRB_CKE1

DDRB_CS0# DDRB_CS1#

DDRB_ODT0 DDRB_ODT1

DDRB_BS0# DDRB_BS1# DDRB_BS2#

DDRB_RAS# DDRB_WE# DDRB_CAS#

DDRB_MA0 DDRB_MA1 DDRB_MA2 DDRB_MA3 DDRB_MA4 DDRB_MA5 DDRB_MA6 DDRB_MA7 DDRB_MA8 DDRB_MA9 DDRB_MA10 DDRB_MA11 DDRB_MA12 DDRB_MA13 DDRB_MA14 DDRB_MA15

DDRB_DQS#0 DDRB_DQS#1 DDRB_DQS#2 DDRB_DQS#3 DDRB_DQS#4 DDRB_DQS#5 DDRB_DQS#6 DDRB_DQS#7

DDRB_DQS0 DDRB_DQS1 DDRB_DQS2 DDRB_DQS3 DDRB_DQS4 DDRB_DQS5 DDRB_DQS6 DDRB_DQS7

DDRB_CLK0# <12> DDRB_CLK0 <12> DDRB_CKE0 <12> DDRB_CLK1# <12> DDRB_CLK1 <12> DDRB_CKE1 <12>

DDRB_CS0# <12> DDRB_CS1# <12>

DDRB_ODT0 <12> DDRB_ODT1 <12>

DDRB_BS0# <12> DDRB_BS1# <12> DDRB_BS2# <12>

DDRB_RAS# <12>DDRA_MA[0..15] <11> DDRB_WE# <12> DDRB_CAS# <12>

DDRB_MA[0..15] <12>

DDRB_DQS#[0..7] <12>

DDRB_DQS[0..7] <12>

A A

+VREF_DQA_M3 +VREF_DQB_M3

1

CC45

0.1U_0402_25V6-K

2

1

CC46

0.1U_0402_25V6-K

2

ESD

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/12/05

LC Future Center Secret Data

Deciphered Date

2

2014/12/05

Title

CPU_DDR3 INTERFACE

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

E440 NM-A151

E440 NM-A151E440 NM-A151

1

7 57

of

1.0

5

4

3

2

1

Haswell rPGA EDS

JCPU1H

ME@

JCPU1H

To HDMI

CPU_HDMI_TX2-<34> CPU_HDMI_TX2+<34>

D D

CPU_HDMI_TX1-<34> CPU_HDMI_TX1+<34> CPU_HDMI_TX0-<34> CPU_HDMI_TX0+<34> CPU_HDMI_CLK-<34> CPU_HDMI_CLK+<34>

CPU_DOCK_TX0-<42> CPU_DOCK_TX0+<42> CPU_DOCK_TX1-<42> CPU_DOCK_TX1+<42>

CPU_HDMI_TX2CPU_HDMI_TX2+ CPU_HDMI_TX1CPU_HDMI_TX1+ CPU_HDMI_TX0CPU_HDMI_TX0+ CPU_HDMI_CLKCPU_HDMI_CLK+

CPU_DOCK_TX0CPU_DOCK_TX0+ CPU_DOCK_TX1CPU_DOCK_TX1+

Docking DP

C C

ME@

T28

DDIB_TXBN_0

U28

DDIB_TXBP_0

T30

DDIB_TXBN_1

U30

DDIB_TXBP_1

U29

DDIB_TXBN_2

V29

DDIB_TXBP_2

U31

DDIB_TXBN_3

V31

DDIB_TXBP_3

T34

DDIC_TXCN_0

U34

DDIC_TXCP_0

U35

DDIC_TXCN_1

V35

DDIC_TXCP_1

U32

DDIC_TXCN_2

T32

DDIC_TXCP_2

U33

DDIC_TXCN_3

V33

DDIC_TXCP_3

P29

DDID_TXDN_0

R29

DDID_TXDP_0

N28

DDID_TXDN_1

P28

DDID_TXDP_1

P31

DDID_TXDN_2

R31

DDID_TXDP_2

N30

DDID_TXDN_3

P30

DDID_TXDP_3

INTEL_HASWELL_HASWELL

eDP

EDP_AUXN

EDP_RCOMP

EDP_DISP_UTIL

EDP_TXN_0 EDP_TXP_0 EDP_TXN_1 EDP_TXP_1

8 OF 9

EDP_AUXP

EDP_HPD

FDI_TXN_0 FDI_TXP_0 FDI_TXN_1 FDI_TXP_1

DDI

M27

CPU_EDP_AUX#

N27

CPU_EDP_AUX

P27

EDP_HPD_IN#

E24

EDP_COMP

R27

1

T10 @T10 @

P35

CPU_EDP_TX0-

R35

CPU_EDP_TX0+

N34

CPU_EDP_TX1- EDP_HPD_IN#

P34

CPU_EDP_TX1+

P33

FDI_CTX_PRX_N0

R33

FDI_CTX_PRX_P0

N32

FDI_CTX_PRX_N1

P32

FDI_CTX_PRX_P1

COMPENSATION PU FOR eDP CAD Note:Trace width=20 mils, Spacing=25mil, Max length=100 mils.

CPU_EDP_AUX# <36> CPU_EDP_AUX <36>

1 2

RC25 24.9_0402_1%RC25 24.9_0402_1%

CPU_EDP_TX0- <36> CPU_EDP_TX0+ <36> CPU_EDP_TX1- <36> CPU_EDP_TX1+ <36> FDI_CTX_PRX_N0 <15> FDI_CTX_PRX_P0 <15> FDI_CTX_PRX_N1 <15> FDI_CTX_PRX_P1 <15>

+VCCIOA_OUT

To eDP Panel

HPD INVERSION FOR EDP

CPU_EDP_HPD<36>

CPU_EDP_HPD

12

RC27

RC27 100K_0402_5%

100K_0402_5%

+VCCIO_OUT

12

RC26

RC26 10K_0402_5%

10K_0402_5%

13

D

2

G

S

It is an output from eDP sink device and it is a active high signal. However, the HPD processor input is a low voltage active low signal.

Pull up resistor on DP_HPD modified to 10kOhms from 1kOhms .

QC1

QC1 BSS138_NL_SOT23-3

BSS138_NL_SOT23-3

SB50138002J 2nd --> SB50138000T

CFG STRAPS For CPU

Haswell rPGA EDS

JCPU1I

ME@

JCPU1I

ME@

AT1

RSVD_TP_5

AT2

RSVD_TP_6

AD10

RSVD_17

A34

RSVD_TP_7

A35

RSVD_TP_8

W29

RSVD_TP_9

RC33

1 2

49.9_0402_1%

+VCC_CORE

B B

RC34

1 2

49.9_0402_1%

A A

T34@T34@

T41@T41@

CPU_TESTLO_G26

+VCC_CORE

CPU_TESTLO_W34

CFG2

1

CFG3 CFG4 CFG5 CFG6 CFG7

1

CFG9

W28

RSVD_TP_10

G26

TESTLO_G26

W33

RSVD_18

AL30

RSVD_19

AL29

RSVD_20

F25

VCC

C35

RSVD_TP_11

B35

RSVD_TP_12

AL25

RSVD_TP_13

W30

RSVD_TP_14

W31

RSVD_TP_15

W34

TESTLO

AT20

CFG_0

AR20

CFG_1

AP20

CFG_2

AP22

CFG_3

AT22

CFG_4

AN22

CFG_5

AT25

CFG_6

AN23

CFG_7

AR24

CFG_8

AT23

CFG_9

AN20

CFG_10

AP24

CFG_11

AP26

CFG_12

AN25

CFG_13

AN26

CFG_14

AP25

CFG_15

INTEL_HASWELL_HASWELL

9 OF 9

RSVD_TP_16 RSVD_TP_17 RSVD_TP_18 RSVD_TP_19

CFG_RCOMP

RSVD_TP_20

RSVD_TP_21 RSVD_TP_22

CFG_16 CFG_18 CFG_17 CFG_19

RSVD_21

FC_G6 RSVD_22 RSVD_23 RSVD_24 RSVD_25 RSVD_26

RSVD_27

RSVD_28 RSVD_29

RSVD_30

RSVD_31 RSVD_32

VSS_342 VSS_343

C23 B23 D24 D23

AT31 AR21 AR23 AP21 AP23

AR33 G6 AM27 AM26 F5 AM2 K6

E18

U10 P10

B1

NC

A2 AR1

E21 E20

AP27 AR26

AL31 AL32

12

RC44

@ RC44

@

2K_0402_1%

12

RC45

@ RC45

@

1K_0402_1%

CPU_CFG_RCOMP

PCH_PWROK

RC35

12

49.9_0402_1%

PCH_PWROK <15,48>

(CFG[17:0] internal pull high 5～～～～15K to VCCIO)

PEG Static Lane Reversal - CFG2 is for the 16x

1: (Default) Normal Operation;

*

CFG2

Display Port Presence Strap

CFG4

PCIE Port Bifurcation Straps

CFG[6:5]

PEG DEFER TRAINING

CFG7

Lane# definition matches socket pin map definition 0: Lane Reversed

1 : Disabled No Physical Display Port attached to Embedded Display Port 0 : Enabled;

*

An external Display Port device is connected to the Embedded Display Port

11 : Func 1 Disabled, Func 2 Disabled (x16,---,---) 10 : Func 1 Enabled, Func 2 Disabled (x8,x8,---)

*

01 : Func 1 Disabled, Func 2 Enabled 00 : Func 1 Enabled, Func 2 Enabled (x8,x4,x4)

1: (Default)

*

PEG Train Immediately Following XXRESETB Deassertion 0 : PEG Wait for BIOS for Training

CFG2

CFG4

CFG5

CFG6

CFG7

1 2

RC28 1K_0402_1%@RC28 1K_0402_1%@

1 2

RC29 1K_0402_1%RC29 1K_0402_1%

1 2

RC30 1K_0402_1%@RC30 1K_0402_1%@

1 2

RC31 1K_0402_1%@RC31 1K_0402_1%@

1 2

RC32 1K_0402_1%@RC32 1K_0402_1%@

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/12/05

LC Future Center Secret Data

Deciphered Date

2

2014/12/05

Title

CPU_eDP/DDI/RSVD/CFG

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

E440 NM-A151

E440 NM-A151E440 NM-A151

1

8 57

of

1.0

5

4

3

2

1

AA26 AA28 AA34 AA30 AA32 AB26 AB29 AB25 AB27 AB28 AB30 AB31 AB33 AB34 AB32 AC26 AB35 AC28 AD25 AC30 AD28 AC32 AD31 AC34 AD34 AD26 AD27 AD29 AD30 AD32 AD33 AD35 AE26 AE32 AE28 AE30 AG28 AG34 AE34 AF25 AF26 AF27 AF28 AF29 AF30 AF31 AF32 AF33 AF34 AF35 AG26 AH26 AH29 AG30 AG32 AH32 AH35 AH25 AH27 AH28 AH30 AH31 AH33 AH34 AJ25 AJ26 AJ27 AJ28 AJ29 AJ30 AJ31 AJ32 AJ33 AJ34 AJ35 G25 H25 J25 K25 L25 M25 N25 P25 R25 T25

U25 U26 V25 V26

W26 W27

+VCC_CORE

Haswell rPGA EDS

JCPU1E

ME@

JCPU1E

CPU VDDQ DECOUPLING

D D

C C

+1.35V

CC18

CC28

CC19

10U_0603_6.3V6-M

1

2

CC29

22U_0805_6.3V6-M

1

2

CC21

CC20

10U_0603_6.3V6-M

1

2

CC31

CC30

22U_0805_6.3V6-M

1

2

CC23

CC22

10U_0603_6.3V6-M

22U_0805_6.3V6-M

CC32

1

2

CC33

22U_0805_6.3V6-M

1

2

CC25

CC24

10U_0603_6.3V6-M

1

2

CC35

CC34

22U_0805_6.3V6-M

1

2

CC27

CC26

10U_0603_6.3V6-M

22U_0805_6.3V6-M

CC36

1

2

CC39

CC38

CC37

22U_0805_6.3V6-M

1

2

1

2

CC39

CC40

330U_D2_2VM_R6M

22U_0805_6.3V6-M

330U_D2_2VM_R6M

1

+

@

2

+VCC_CORE

+1.35V

VDDQ Decoupling :

1. MB Bottom Socket Edge --> 2* 330uf, 6mΩ

2. 6x MB Bottom Socket Cavity --> 11* 22 μF (0805), 3mΩ 5x MB Top Socket Cavity

3. 5x MB Bottom Socket Cavity --> 10 x 10 μF (0805), 3mΩ 5x MB Top Socket Cavity

Reserve for VCCST

+1.05VS_PCH_VPROC

1 2

RC43 0_0402_5%@RC43 0_0402_5%@

1

CC42

@ CC42

@

4.7U_0603_6.3V6K

2

VR_SVID_ALRT#<64> VR_SVID_CLK<64> VR_SVID_DAT<64>

Pull high resistor on VR side

+VCCIO_OUT

+VCCIOA_OUT

1 2

RC36 43_0402_1%RC36 43_0402_1%

1 2

RC37 0_0402_5%RC37 0_0402_5%

1 2

RC38 0_0402_5%RC38 0_0402_5%

1 2

RC42 130_0402_1%RC42 130_0402_1%

VCCSENSE

+VCCST_A23

H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT

T54@ T54@

VCC/VSS SENSE

+VCC_CORE

B B

VCCSENSE<64>

VSSSENSE<10,64 >

12

RC39

RC39 100_0402_1%

100_0402_1%

12

RC41

RC41 100_0402_1%

100_0402_1%

Reserve 0-Ohm on Power Side

VCCSENSE

VSSSENSE

RC40

1 2

0_0603_5%

RESISTOR STUFFING OPTIONS ARE PROVIDED FOR TESTING PURPOSES

Close to CPU

+VCCIO_OUT+1.05VS

@

+VCC_CORE

K27

L27 T27 V27

AB11

AB2 AB5 AB8

AE11

AE2 AE5 AE8

AH11

K11 N11

N8

T11

T2 T5 T8

W11

W2 W5 W8

N26 K26

AL27

AK27

AL35

E17

AN35

A23 F22

W32

AL16

J27

AL13

AM28 AM29

AL28

AP35

1

H27

AP34 AT35 AR35 AR32

AL26

AT34

AL22 AT33 AM21 AM25 AM22 AM20 AM24

AL19 AM23 AT32

Y25 Y26 Y27 Y28 Y29 Y30 Y31 Y32 Y33 Y34 Y35

ME@

RSVD_3 RSVD_4 RSVD_5 RSVD_6

4.2A

VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 VDDQ_10 VDDQ_11 VDDQ_12 VDDQ_13 VDDQ_14 VDDQ_15 VDDQ_16 VDDQ_17 VDDQ_18 VDDQ_19 VDDQ_20

RSVD_7 VCC_1 RSVD_8 RSVD_9

VCC_SENSE RSVD_10

300mA

VCCIO_OUT RSVD_11

300mA

VCOMP_OUT RSVD_12 RSVD_13 RSVD_14 RSVD_15

VIDALERT VIDSCLK VIDSOUT

VSS_3 PWR_DEBUG VSS_4 RSVD_TP_1 RSVD_TP_2 RSVD_TP_3 RSVD_TP_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15

VCC_2 VCC_3 VCC_4 VCC_5 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12

INTEL_HASWELL_HASWELL

5 OF 9

57W, 95A 47W, 85A 37W, 55A

VCC_13 VCC_14 VCC_15 VCC_16 VCC_17 VCC_18 VCC_19 VCC_20 VCC_21 VCC_22 VCC_23 VCC_24 VCC_25 VCC_26 VCC_27 VCC_28 VCC_29 VCC_30 VCC_31 VCC_32 VCC_33 VCC_34 VCC_35 VCC_36 VCC_37 VCC_38 VCC_39 VCC_40 VCC_41 VCC_42 VCC_43 VCC_44 VCC_45 VCC_46 VCC_47 VCC_48 VCC_49 VCC_50 VCC_51 VCC_52 VCC_53 VCC_54 VCC_55 VCC_56 VCC_57 VCC_58 VCC_59 VCC_60 VCC_61 VCC_62 VCC_63 VCC_64 VCC_65 VCC_66 VCC_67 VCC_68 VCC_69 VCC_70 VCC_71 VCC_72 VCC_73 VCC_74 VCC_75 VCC_76 VCC_77 VCC_78 VCC_79 VCC_80 VCC_81 VCC_82 VCC_83 VCC_84 VCC_85 VCC_86 VCC_87 VCC_88 VCC_89 VCC_90 VCC_91 VCC_92 VCC_93 VCC_94 VCC_95 VCC_96 VCC_97

VCC_98

VCC_99 VCC_100 VCC_101

VCC_102 VCC_103

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/12/05

LC Future Center Secret Data

Deciphered Date

2

2014/12/05

Title

CPU_POWER

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

E440 NM-A151

E440 NM-A151E440 NM-A151

1

9 57

of

1.0

5

4

3

2

1

D D

C C

B B

AA11 AA25 AA27 AA31 AA29

AB10 AA33 AA35

AC25 AC27

AC11 AD11 AC29 AC31 AC33 AC35

AD7

AE1 AE10 AE25 AE29

AE3 AE27 AE35

AE4

AE6

AE7

AE9 AF11

AF6

AF8 AG11 AG25 AE31 AG31 AE33

AG6

AH1 AH10

AH2 AG27 AG29

AH3 AG33 AG35

AH4

AH5

AH6

AH7

AH8

AH9 AJ11

AK11 AK25 AK26 AK28 AK29 AK30 AK32

A10 A13 A16 A19 A22 A25 A27 A29

A3 A31 A33

A4

A7

AB1

AB3

AB4 AB6 AB7 AB9

AJ5

E19

Haswell rPGA EDS

JCPU1F

VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105

INTEL_HASWELL_HASWELL

ME@

6 OF 9

VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184

AK34 AK5 AL1 AL10 AL11 AL12 AL14 AL15 AL17 AL18 AL2 AL20 AL21 AL23 E22 AL3 AL4 AL5 AL6 AL7 AL8 AL9 AM10 AM13 AM16 AM19 E25 AM32 AM4 AM7 AN10 AN13 AN16 AN19 AN2 AN21 AN24 AN27 AN30 AN34 AN4 AN7 AP1 AP10 AP13 AP16 AP19 AP4 AP7 W25 AR10 AR13 AR16 AR19 AR2 AR22 AR25 AR28 AR31 AR34 AR4 AR7 AT10 AT13 AT16 AT19 AT21 AT24 AT27 AT3 AT30 AT4 AT7 B10 B13 B16 B19 B2 B22

Haswell rPGA EDS

JCPU1G

B34

VSS_185

B4

VSS_186

B7

VSS_187

C1

VSS_188

C10

VSS_189

C13

VSS_190

C16

VSS_191

C19

VSS_192

C2

VSS_193

C22

VSS_194

C24

VSS_195

C26

VSS_196

C28

VSS_197

C30

VSS_198

C32

VSS_199

C34

VSS_200

C4

VSS_201

C7

VSS_202

D10

VSS_203

D13

VSS_204

D16

VSS_205

D19

VSS_206

D22

VSS_207

D25

VSS_208

D27

VSS_209

D29

VSS_210

D31

VSS_211

D33

VSS_212

D35

VSS_213

D4

VSS_214

D7

VSS_215

E1

VSS_216

E10

VSS_217

E13

VSS_218

E16

VSS_219

E4

VSS_220

E7

VSS_221

F10

VSS_222

F11

VSS_223

F12

VSS_224

F14

VSS_225

F15

VSS_226

F17

VSS_227

F18

VSS_228

F20

VSS_229

F21

VSS_230

F23

VSS_231

F24

VSS_232

F26

VSS_233

F28

VSS_234

F30

VSS_235

F32

VSS_236

F34

VSS_237

F4

VSS_238

F6

VSS_239

F7

VSS_240

F8

VSS_241

F9

VSS_242

G1

VSS_243

G11

VSS_244

G2

VSS_245

G27

VSS_246

G29

VSS_247

G3

VSS_248

G31

VSS_249

G33

VSS_250

G35

VSS_251

G4

VSS_252

G5

VSS_253

H10

VSS_254

H26

VSS_255

H6

VSS_256

H7

VSS_257

J11

VSS_258

J26

VSS_259

J28

VSS_260

J30

VSS_261

J32

VSS_262

J34

VSS_263

J6

VSS_264

K1

VSS_265

INTEL_HASWELL_HASWELL

ME@

VSS_SENSE

RSVD_17

VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325 VSS_326 VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341

7 OF 9

K10 K2 K29 K3 K31 K33 K35 K4 K5 K7 K8 K9 L11 L26 L6 M11 M26 M28 M30 M32 M34 M6 N1 N10 N2 N29 N3 N31 N33 N35 N4 N5 N6 N7 N9 P11 P26 P5 R11 R26 R28 R30 R32 R34 R5 T1 T10 T29 T3 T31 T33 T35 T4 T6 T7 T9 U11 U27 V11 V28 V30 V32 V34 W1 W10 W3 W35 W4 W6 W7 W9 Y11 H11 AL24 F19 T26 AK35 AK33

VSSSENSE

VSSSENSE <64 ,9>

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/12/05

LC Future Center Secret Data

Deciphered Date

2

2014/12/05

Title

CPU_GND

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

E440 NM-A151

E440 NM-A151E440 NM-A151

1

10 57

of

1.0

5

DDR3 SO-DIMM A

3A@1.5V

D D

C C

B B

A A

+VREF_DQA

CD1

Close to JDDR3H.1

DDRA_CKE0<7>

DDRA_BS2#<7>

DDRA_CLK0<7> DDRA_CLK0#<7>

DDRA_BS0#<7>

DDRA_WE#<7> DDRA_CAS#<7>

DDRA_CS1#<7>

SPD setting (SA0, SA1) PU/PD by Channel A/B

->Channel A 00

->Channel B 01

+3VS

CD22

2.2U_0603_6.3V6-K

1

2

CD2

0.1U_0402_10V7-K

1

2

5

1

2

2.2U_0402_6.3V6-M

1

CD23

0.1U_0402_10V6-K

2

DDRA_DQ0 DDRA_DQ1

DDRA_DQ2 DDRA_DQ3

DDRA_DQ8 DDRA_DQ9

DDRA_DQS#1 DDRA_DQS1

DDRA_DQ10 DDRA_DQ11

DDRA_DQ16 DDRA_DQ17

DDRA_DQS#2 DDRA_DQS2

DDRA_DQ18 DDRA_DQ19

DDRA_DQ24 DDRA_DQ25

DDRA_DQ26 DDRA_DQ27

DDRA_CKE0

DDRA_BS2#

DDRA_MA12 DDRA_MA9

DDRA_MA8 DDRA_MA5

DDRA_MA3 DDRA_MA1

DDRA_CLK0 DDRA_CLK0#

DDRA_MA10 DDRA_BS0#

DDRA_WE# DDRA_CAS# DDRA_ODT0

DDRA_MA13 DDRA_CS1#

DDRA_DQ32 DDRA_DQ33

DDRA_DQS#4 DDRA_DQS4

DDRA_DQ34 DDRA_DQ35

DDRA_DQ40 DDRA_DQ41

DDRA_DQ42 DDRA_DQ43

DDRA_DQ48 DDRA_DQ49

DDRA_DQS#6 DDRA_DQS6

DDRA_DQ50 DDRA_DQ51

DDRA_DQ56 DDRA_DQ57

DDRA_DQ58 DDRA_DQ59

RD1

1 2

10K_0402_5%

12

RD2

RD2 10K_0402_5%

10K_0402_5%

JDIMM1

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET# VSS1131VSS12

33

DQ10

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

TYCO_2-2013287-1

ME@JDIMM1

ME@

VSS3

DQS#0

DQS0

VSS6

VSS8 DQ12 DQ13

VSS10

DQ14 DQ15

DQ20 DQ21

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

VTT2

DQ4 DQ5

DQ6 DQ7

DM1

DM2

CK1

BA1

NC2

DM4

DM6

SDA SCL

4

+1.35V+1.35V

2 4

DDRA_DQ4

6

DDRA_DQ5

8 10

DDRA_DQS#0

12

DDRA_DQS0

14 16

DDRA_DQ6

18

DDRA_DQ7

20 22

DDRA_DQ12

24

DDRA_DQ13

26 28 30

DDR3_DRAMRST#

32 34

DDRA_DQ14

36

DDRA_DQ15

38 40

DDRA_DQ20

42

DDRA_DQ21

44 46 48 50

DDRA_DQ22

52

DDRA_DQ23

54 56

DDRA_DQ28

58

DDRA_DQ29

60 62

DDRA_DQS#3

64

DDRA_DQS3

66 68

DDRA_DQ30

70

DDRA_DQ31

72

74

DDRA_CKE1

76 78

A15 A14

A11

A7

A6 A4

A2 A0

S0#

G2

DDRA_MA15

80

DDRA_MA14

82 84

DDRA_MA11

86

DDRA_MA7

88 90

DDRA_MA6

92

DDRA_MA4

94 96

DDRA_MA2

98

DDRA_MA0

100 102

DDRA_CLK1

104

DDRA_CLK1#

106 108

DDRA_BS1#

110

DDRA_RAS#

112 114

DDRA_CS0#

116 118 120

DDRA_ODT1

122 124 126 128 130

DDRA_DQ36

132

DDRA_DQ37

134 136 138 140

DDRA_DQ38

142

DDRA_DQ39

144 146

DDRA_DQ44

148

DDRA_DQ45

150 152

DDRA_DQS#5

154

DDRA_DQS5

156 158

DDRA_DQ46

160

DDRA_DQ47

162 164

DDRA_DQ52

166

DDRA_DQ53

168 170 172 174

DDRA_DQ54

176

DDRA_DQ55

178 180

DDRA_DQ60

182

DDRA_DQ61

184 186

DDRA_DQS#7

188

DDRA_DQS7

190 192

DDRA_DQ62

194

DDRA_DQ63

196 198 200

PM_SMBDATA

202

PM_SMBCLK

204

206

4

0.65A@0.75V

0.65A@0.75V0.65A@0.75V

DDR3_DRAMRST# <12,6>

DDRA_CKE1 <7>

DDRA_CLK1 <7> DDRA_CLK1# <7>

DDRA_BS1# <7> DDRA_RAS# <7>

DDRA_CS0# <7> DDRA_ODT0 <7>

DDRA_ODT1 <7>

1

CD20

2

0.1U_0402_10V7-K

close to JDDR3L.126

PM_SMBDATA <12,17,39,43> PM_SMBCLK <12,17,39,43>

+0.675VS

CD21

1

2

3

2

DDR Decoupling

+1.35V

CD3

CD4

1U_0402_6.3V6-K

1

2

1U_0402_6.3V6-K

1

2

CD5

CD6

Layout Note :

1U_0402_6.3V6-K

1

2

1. Placed near JDDR3L

2

2. Place these 4 Caps near Command and Control signals of DIMMA

CD8

CD9

CD17

CD9

10U_0603_6.3V6-M

1

2

1

2

10U_0603_6.3V6-M

1

2

CD18

1U_0402_6.3V6-K

1

2

2014/12/05

2

CD7

10U_0603_6.3V6-M

1

2

+0.675VS

CD16

1U_0402_6.3V6-K

1

+V_SM_VREF_CNT

2.2U_0402_6.3V6-M

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/12/05

2

LC Future Center Secret Data

Deciphered Date

CD11

CD10

CD19

1

2

1

2

10U_0603_6.3V6-M

1

2

Layout Note : Placed near

1U_0402_6.3V6-K

JDDR3L1.Pin203, 204

1

DDRA_DQ[0..63] <7>

DDRA_DQS[0..7] <7>

DDRA_DQS#[0..7] <7>

DDRA_MA[0..15] <7>

1uF *4, 10uF *7, 330uF *1

CD15

CD13

CD14

CD12

10U_0603_6.3V6-M

1

2

Title

DDR3 SO-DIMMA/1

Size Document Number Rev

Custom

Date: Sheet

CD14

10U_0603_6.3V6-M

1

2

Thursday, July 11, 2013

10U_0603_6.3V6-M

1

2

CD15

330U_D2_2VM_R9M

1

+

2

E440 NM-A151

E440 NM-A151E440 NM-A151

1

11 57

of

1.0

5

DDR3 SO-DIMM B

+1.35V +1.35V

3A@1.5V

JDIMM2

ME@

+VREF_DQB

1

D D

CD25

1

CD24

2

0.1U_0402_10V7-K

2.2U_0402_6.3V6-M

Close to JDDR3L.1

C C

DDRB_CKE0<7>

DDRB_BS2#<7>

DDRB_CLK0<7> DDRB_CLK0#<7>

DDRB_BS0#<7>

DDRB_WE#<7> DDRB_CAS#<7>

DDRB_CS1#<7>

B B

SPD setting (SA0, SA1) PU/PD by Channel A/B

A A

->Channel A 00

->Channel B 01

+3VS

2.2U_0603_6.3V6-K

CD48

1

2

5

1

CD49

0.1U_0402_10V6-K

2

DDRB_DQ0 DDRB_DQ1

DDRB_DQ2 DDRB_DQ3

DDRB_DQ8 DDRB_DQ9

DDRB_DQS#1 DDRB_DQS1

DDRB_DQ10 DDRB_DQ11

DDRB_DQ16 DDRB_DQ17

DDRB_DQS#2 DDRB_DQS2

DDRB_DQ18 DDRB_DQ19

DDRB_DQ24 DDRB_DQ25

DDRB_DQ26 DDRB_DQ27

DDRB_CKE0

DDRB_BS2#

DDRB_MA12 DDRB_MA9

DDRB_MA8 DDRB_MA5

DDRB_MA3 DDRB_MA1

DDRB_CLK0 DDRB_CLK0#

DDRB_MA10 DDRB_BS0#

DDRB_WE# DDRB_CAS#

DDRB_MA13 DDRB_CS1#

DDRB_DQ32 DDRB_DQ33

DDRB_DQS#4 DDRB_DQS4

DDRB_DQ34 DDRB_DQ35

DDRB_DQ40 DDRB_DQ41

DDRB_DQ42 DDRB_DQ43

DDRB_DQ48 DDRB_DQ49

DDRB_DQS#6 DDRB_DQS6

DDRB_DQ50 DDRB_DQ51

DDRB_DQ56 DDRB_DQ57

DDRB_DQ58 DDRB_DQ59

1 2

RD14

10K_0402_5%

1 2

RD16

10K_0402_5%

11 13 15 17 19 21 23 25 27

33 35

39 41

45 47 49 51 53 55 57 59

63

67 69

73 75 77 79 81 83 85 87 89 91 93 95 97

99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203

205

ME@

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS129RESET# VSS1131VSS12 DQ10 DQ11 VSS1337VSS14 DQ16 DQ17 VSS1543VSS16 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS2261DQS#3 DM3 VSS2365VSS24 DQ26 DQ27 VSS2571VSS26

CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1

G1

LCN_DAN06-K4806-0103

DQS#0

VSS10

VSS17

VSS19

VSS21

VDD10

VDD12

VDD14

VDD16

VDD18

VREF_CA

VSS28

VSS30

VSS31

VSS33

VSS35 DQS#5

VSS38

VSS40

VSS42

VSS43

VSS45

VSS47 DQS#7

VSS50

VSS52

EVENT#

DQ4 DQ5

VSS3

DQS0

VSS6

DQ6 DQ7

VSS8 DQ12 DQ13

DM1

DQ14 DQ15

DQ20 DQ21

DM2

DQ22 DQ23

DQ28 DQ29

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

CK1#

RAS#

ODT0

ODT1

DQ36 DQ37

DM4

DQ38 DQ39

DQ44 DQ45

DQS5

DQ46 DQ47

DQ52 DQ53

DM6

DQ54 DQ55

DQ60 DQ61

DQS7

DQ62 DQ63

SDA

VTT2

CK1

BA1

NC2

SCL

4

2 4

DDRB_DQ4

6

DDRB_DQ5

8 10

DDRB_DQS#0

12

DDRB_DQS0

14 16

DDRB_DQ6

18

DDRB_DQ7

20 22

DDRB_DQ12

24

DDRB_DQ13

26 28 30

DDR3_DRAMRST#

32 34

DDRB_DQ14

36

DDRB_DQ15

38 40

DDRB_DQ20

42

DDRB_DQ21

44 46 48 50

DDRB_DQ22

52

DDRB_DQ23

54 56

DDRB_DQ28

58

DDRB_DQ29

60 62

DDRB_DQS#3

64

DDRB_DQS3

66 68

DDRB_DQ30

70

DDRB_DQ31

72

74

DDRB_CKE1

76 78

A15 A14

A11

A7

A6 A4

A2 A0

S0#

G2

DDRB_MA15

80

DDRB_MA14

82 84

DDRB_MA11

86

DDRB_MA7

88 90

DDRB_MA6

92

DDRB_MA4

94 96

DDRB_MA2

98

DDRB_MA0

100 102

DDRB_CLK1

104

DDRB_CLK1#

106 108

DDRB_BS1#

110

DDRB_RAS#

112 114

DDRB_CS0#

116

DDRB_ODT0

118 120

DDRB_ODT1

122 124 126 128 130

DDRB_DQ36

132

DDRB_DQ37

134 136 138 140

DDRB_DQ38

142

DDRB_DQ39

144 146

DDRB_DQ44

148

DDRB_DQ45

150 152

DDRB_DQS#5

154

DDRB_DQS5

156 158

DDRB_DQ46

160

DDRB_DQ47

162 164

DDRB_DQ52

166

DDRB_DQ53

168 170 172 174

DDRB_DQ54

176

DDRB_DQ55

178 180

DDRB_DQ60

182

DDRB_DQ61

184 186

DDRB_DQS#7

188

DDRB_DQS7

190 192

DDRB_DQ62

194

DDRB_DQ63

196 198 200

PM_SMBDATA

202

PM_SMBCLK

204

206

0.65A@0.75V

0.65A@0.75V0.65A@0.75V

4

DDR3_DRAMRST# <11,6>

DDRB_CKE1 <7>

DDRB_CLK1 <7> DDRB_CLK1# <7>

DDRB_BS1# <7> DDRB_RAS# <7>

DDRB_CS0# <7> DDRB_ODT0 <7>

DDRB_ODT1 <7>

1

CD44

CD43

2

0.1U_0402_10V7-K

2.2U_0402_6.3V6-M

Close to JDDR3H.126

PM_SMBDATA <11,17,39,43> PM_SMBCLK <11,17,39,43>

+0.675VS

+V_SM_VREF_CNT

3

2

DDR Decoupling

+1.35V

CD26

CD27

CD28

CD29

1U_0402_6.3V6-K

1

2

1U_0402_6.3V6-K

1

2

Layout Note :

1U_0402_6.3V6-K

1

1. Placed near JDDR3H

2

2. Place these 4 Caps near Command and Control signals of DIMMA

CD30

CD31

CD32

CD33

CD34

CD35

10U_0603_6.3V6-M

1

2

CD42

1U_0402_6.3V6-K

1

2

+0.675VS

CD39

1

2

CD41

CD40

1U_0402_6.3V6-K

1

2

1U_0402_6.3V6-K

1

2

All VREF traces should have 20 mil trace width

+1.35V

12

+VREF_DQA_M3

RD6

1 2

1

2_0402_1%

CD45

0.022U_0402_25V7-K

2

12

RD15

24.9_0402_1%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

12

2012/12/05

+VREF_DQA +1.35V

RD3

RD3 1K_0402_0.5%

1K_0402_0.5%

RD9

RD9 1K_0402_0.5%

1K_0402_0.5%

LC Future Center Secret Data

+VREF_DQB_M3

Deciphered Date

RD7

1 2

1

2_0402_1%

CD46

0.022U_0402_25V7-K

2

12

RD12

24.9_0402_1%

2

12

RD4

RD4 1K_0402_0.5%

1K_0402_0.5%

12

RD10

RD10 1K_0402_0.5%

1K_0402_0.5%

2014/12/05

CD35

10U_0603_6.3V6-M

1

2

Layout Note : Placed near JDDR3H.Pin203, 204

+VREF_DQB +1.35V

1

DDRB_DQ[0..63] <7>

DDRB_DQS[0..7] <7>

DDRB_DQS#[0..7] <7>

DDRB_MA[0..15] <7>

1uF *4, 10uF *7, 330uF *1

CD38

CD36

CD37

10U_0603_6.3V6-M

1

2

+V_SM_VREF

1

CD47

0.022U_0402_25V7-K

2

12

RD13

24.9_0402_1%

Thursday, July 11, 2013

CD37

10U_0603_6.3V6-M

1

2

RD8

1 2

2_0402_1%

10U_0603_6.3V6-M

1

2

Title

DDR3 SO-DIMMB/2

Size Document Number Rev

Custom

Date: Sheet

CD38

330U_D2_2VM_R9M

1

+

2

12

RD5

RD5 1K_0402_0.5%

1K_0402_0.5%

12

RD11

RD11 1K_0402_0.5%

1K_0402_0.5%

E440 NM-A151

E440 NM-A151E440 NM-A151

1

12 57

+V_SM_VREF_CNT

of

1.0

5

4

3

2

1

JCMOS, JME Setting, Need Under DDR Door

+RTCVCC

D D

1

CH9

CH9 18P_0402_50V8-J

18P_0402_50V8-J

2

C C

RH1

1 2

20K_0402_5%

1 2

20K_0402_5%

1 2

10M_0402_5%

1 2

32.768KHZ_12.5PF_9H03200019

SJ10000DM0J

Y_CM31532768DZFT_2P

PCH_RTCRST#

RH4

PCH_SRTCRST#

RH3

YH1

JCMOS1 @JCMOS1 @

1 2

CH1 1U_0603_10V6-KCH1 1U_0603_10V6-K

JME1 @JME1 @

1 2

CH2 1U_0603_10V6-KCH2 1U_0603_10V6-K

PCH_RTCX1

PCH_RTCX2

1

CH10

CH10 18P_0402_50V8-J

18P_0402_50V8-J

2

1. INTVRMEN, should always be pull high HIntegrated VRM enable (Default)

*

LIntegrated VRM disable

2. Internal Voltage Regulator Enable: This signal enables the internal 1.05 V regulators.

+RTCVCC

ME_FLASH<48>

EC_WAKE#<48>

During Reset", Immediately after Reset and S3/S4/S5

1. JTAG_TDI, JTAG_TMS --> Int. PU 20K

2. JTAG_TCK --> Int. PD 20K

3. JTAG_TDO --> High-Z

+3V_PCH

1 2

RH5 1M_0402_5%RH5 1M_0402_5%

1 2

RH2 330K_0402_5%RH2 330K_0402_5%

HDA_SDIN0<46>

1 2

RH6 0_0402_5%RH6 0_0402_5%

1 2

RH7 10K_0402_5%RH7 10K_0402_5%

LPT_PCH_M_EDS

UH1A

PCH_RTCX1

PCH_RTCX2

PCH_SRTCRST#

SM_INTRUDER#

PCH_INTVRMEN

PCH_RTCRST#

HDA_BCLK

HDA_SYNC

HDA_SPKR<47>

HDA_SPKR

HDA_RST#

HDA_SDIN0

HDA_SDOUTME_FLASH

EC_WAKE#

1

PCH_JTAG_TCK

T64@T64@

1

PCH_JTAG_TMS

T65@T65@

1

PCH_JTAG_TDI

T66@T66@

1

PCH_JTAG_TDO

T67@T67@

B5

RTCX1

B4

RTCX2

B9

SRTCRST#

A8

INTRUDER#

G10

INTVRMEN

D9

RTCRST#

B25

HDA_BCLK

A22

HDA_SYNC

AL10

SPKR

C24

HDA_RST#

L22

HDA_SDI0

K22

HDA_SDI1

G22

HDA_SDI2

F22

HDA_SDI3

A24

HDA_SDO

B17

DOCKEN#/GPIO33

C22

HDA_DOCK_RST#/GPIO13

AB3

JTAG_TCK

AD1

JTAG_TMS

AE2

JTAG_TDI

AD3

JTAG_TDO

F8

TP25

C26

TP22

AB6

TP20

LYNX-POINT-DH82LPMS_BGA695

SA00005U830

LPT_PCH_M_EDS

JTAGRTC AZALIA

REV = 5

1 OF 11

BC8

TP9

TP8

SATA_PRX_DTX_N0

BE8

SATA_PRX_DTX_P0

AW8

SATA_PTX_DRX_N0

AY8

SATA_PTX_DRX_P0

BC10

SATA_PRX_DTX_N1

BE10

SATA_PRX_DTX_P1

AV10

SATA_PTX_DRX_N1

AW10

SATA_PTX_DRX_P1

BB9

SATA_PRX_DTX_N2

BD9

SATA_PRX_DTX_P2

AY13

SATA_PTX_DRX_N2

AW13

SATA_PTX_DRX_P2

BC12 BE12

AR13 AT13

BD13 BB13

AV15 AW15

BC14 BE14

SATA Impedance Compensation :

AP15

--> Place the resistor within 500 mils of the PCH.

AR15

Avoid routing next to clock pins.

AY5

SATA_RCOMP

AP3

SATALED#

AT1

PCH_GPIO21

AU2

PCH_GPIO19

BD4

+1.5VS

BA2

BB2

SATA_RXN_0 SATA_RXP_0

SATA_TXN_0 SATA_TXP_0

SATA_RXN_1 SATA_RXP_1

SATA_TXN_1 SATA_TXP_1

SATA

SATA_RXN_2 SATA_RXP_2

SATA_TXN_2 SATA_TXP_2

SATA_RXN_3 SATA_RXP_3

SATA_TXN_3 SATA_TXP_3

SATA_RXN4/PERN1

SATA_RXP4/PERP1

SATA_TXN4/PETN1

SATA_TXP4/PETP1

SATA_RXN5/PERN2

SATA_RXP5/PERP2

SATA_TXN5/PETN2

SATA_TXP5/PETP2

SATA_RCOMP

SATALED#

SATA0GP/GPIO21

SATA1GP/GPIO19

SATA_IREF

SATA_PRX_DTX_N0 <38> SATA_PRX_DTX_P0 <38>

SATA_PTX_DRX_N0 <38> SATA_PTX_DRX_P0 <38>

SATA_PRX_DTX_N1 <40> SATA_PRX_DTX_P1 <40>

SATA_PTX_DRX_N1 <40> SATA_PTX_DRX_P1 <40>

SATA_PRX_DTX_N2 <38> SATA_PRX_DTX_P2 <38>

SATA_PTX_DRX_N2 <38> SATA_PTX_DRX_P2 <38>

1 2

RH8 7.5K_0402_1%RH8 7.5K_0 402_1%

1 2

RH9 10K_0402_5%RH9 10K_0402_5%

1 2

RH10 10K_0402_5%RH10 10K_0402_5%

1 2

RH12 10K_0402_5%RH12 10K_0402_5%

+1.5VS

1. RH12

HDD

SSD(NGFF)

ODD

+1.5VS

+3VS

B B

HDA AUDIO SIGNAL

HDA AUDIO For Codec

HDA_BCLK HDA_RST# HDA_SDOUT

Isolation

HDA_SYNC

A A

1 2

RH21 33_0402_5%RH21 33_0402_5%

1 2

RH24 33_0402_5%RH24 33_0402_5%

1 2

RH25 33_0402_5%RH25 33_0402_5%

+5VS

QH4

@

QH4

@

2

G

BSS138_NL_SOT23-3

1 3

HDA_SYNC_R

D

S

D

S

1 2

RH128 0_0402_5%RH128 0_0402_5%

5

HDA_BITCLK_AUDIO <46> HDA_RST_AUDIO# <46> HDA_SDOUT_AUDIO <46>

RH26

1 2

12

33_0402_5%

R422

@ R422

@

1M_0402_5%

HDA_SYNC_AUDIO <46>

4

HDA STRAP

2012/12/05

+3V_PCH+3VS

*

1 2

RH22 1K_0402_5%@RH22 1K_0402_5%@

HIGH= Enable ( No Reboot ) LOW= Disable (Default)

*

1. The internal pull-down is disabled after PLTRST# deasserts.

2. When Sampled : Rising edge of PWROK

+3V_PCH

1. This signal has a weak internal pull-down 15K

2. The internal pull-down on AZA_SYNC and AZA_SDO are enabled during reset.

1 2

RH27 1K_0402_5%@RH27 1K_0402_5%@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

HDA_SPKR HDA_SDOUT

HDA_SYNC

3

1 2

RH23 1K_0402_5%@RH23 1K_0402_5%@

Low = Disabled (Default) High = Enabled [Flash Descriptor Security Overide]

LC Future Center Secret Data

Deciphered Date

2

2014/12/05

RTCVCC Circuit

1 2

RH20 1K_0402_5%RH20 1K_0402_5%

+RTCBATT, +RTCVCC Trace width = 20mils

RTC External SRTCRST# Circuit

Title

PCH_RTC/HDA/SATA

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

+RTCVCC+RTCBATT

1

CH11

CH11 1U_0603_10V6-K

1U_0603_10V6-K

2

E440 NM-A151

E440 NM-A151E440 NM-A151

1

13 57

of

1.0

5

D D

+3VS

1 2

RH32 2.2K_0402_5%RH32 2.2K_0402_5%

1 2

RH33 2.2K_0402_5%RH33 2.2K_0402_5%

1 2

RH34 150_0402_1%RH34 150_0402_1%

1 2

RH35 150_0402_1%RH35 150_0402_1%

1 2

RH36 150_0402_1%RH36 150_0402_1%

+3VS

1 2

RH37 10K_0402_5%RH37 10K_0402_5%

1 2

RH38 10K_0402_5%RH38 10K_0402_5%

1 2

RH39 10K_0402_5%RH39 10K_0402_5%

1 2

C C

B B

RH40 10K_0402_5%RH40 10K_0402_5%

1 2

RH41 10K_0402_5%@RH41 10K_0402_5%@

1 2

RH42 10K_0402_5%RH42 10K_0402_5%

1 2

RH43 10K_0402_5%RH43 10K_0402_5%

1 2

RH44 10K_0402_5%RH44 10K_0402_5%

1 2

RH45 10K_0402_5%RH45 10K_0402_5%

1 2

RH46 100K_0402_5%RH46 100K_0402_5%

1 2

RH47 10K_0402_5%RH47 10K_0402_5%

1 2

RH48 10K_0402_5%RH48 10K_0402_5%

1 2

RH49 10K_0402_5%RH49 10K_0402_5%

1 2

RH50 10K_0402_5%@RH50 10K_0402_5%@

1 2

RH51 649_0402_1%RH51 649_0402_1%

1 2

RH52 100K_0402_5%RH52 100K_0402_5%

1 2

RH54 1K_0402_5%@RH54 1K_0402_5%@

1 2

RH55 10K_0402_5%@RH55 10K_0402_5%@

1 2

RH56 10K_0402_5%@RH56 10K_0402_5%@

PCH_CRT_DDC_CLK PCH_CRT_DDC_DAT

PCH_CRT_B PCH_CRT_G PCH_CRT_R

DGPU_RST#

NVDD_PWR_EN

DGPU_PWR_EN

PCH_GPIO51

PCH_GPIO55

PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#

PCH_GS_ON#

PCH_ODD_DA#

ODD_DETECT#_DP_R

SATA1_DEVSLP#

DGPU_GC6_EN

CRT_IREF

PCH_ENBKL

DGPU_PWR_EN

DGPU_GC6_EN

DGPU_RST#

4

PCH_CRT_B<35>

PCH_CRT_R<35>

PCH_CRT_DDC_CLK<35>

PCH_CRT_DDC_DAT<35>

PCH_CRT_HSYNC<35>

PCH_CRT_VSYNC<35>

PCH_EDP_PWM<36>

PCH_ENBKL<48>

PCH_ENVDD<36>

+VGA_CORE

+3VS_VGA

NVDD_PWR_EN<63>

DGPU_PWR_EN<23,54>

DGPU_GC6_EN<27>

PLT_RST#

DGPU_RST#

+3VS

2

B

1

A

3

PCH_CRT_B

PCH_CRT_G

PCH_CRT_R

PCH_CRT_DDC_CLK

PCH_CRT_DDC_DAT

PCH_CRT_HSYNC

PCH_CRT_VSYNC

CRT_IREF

PCH_EDP_PWM

PCH_ENBKL

PCH_ENVDD

PCI_PIRQA#

PCI_PIRQB#

PCI_PIRQC#

PCI_PIRQD#

DGPU_RST#

NVDD_PWR_EN

DGPU_PWR_EN

PCH_GPIO51

DGPU_GC6_EN

PCH_GPIO55

5

P

4

Y

G

UH2 NC7SZ08P5X_NL_SC70-5

NC7SZ08P5X_NL_SC70-5

3

DIS@UH2

DIS@

UH1E

T45

VGA_BLUE

U44

VGA_GREEN

V45

VGA_RED

M43

VGA_DDC_CLK

M45

VGA_DDC_DATA

N42

VGA_HSYNC

N44

VGA_VSYNC

U40

DAC_IREF

U39

VGA_IRTN

N36

EDP_BKLTCTL

K36

EDP_BKLTEN

G36

EDP_VDDEN

H20

PIRQA#

L20

PIRQB#

K17

PIRQC#

M20

PIRQD#

A12

GPIO50

B13

GPIO52

C12

GPIO54

C10

GPIO51

A10

GPIO53

AL6

GPIO55

LYNX-POINT-DH82LPMS_BGA695

SA00005U830

PLTRST_VGA# <23>

LPT_PCH_M_EV

LVDSCRT

PCI

5 OF 11

REV = 5

DISPLAY

2

DDPB_CTRLCLK

DDPB_CTRLDATA

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPB_AUXN

DDPC_AUXN

DDPD_AUXN

DDPB_AUXP

DDPC_AUXP

DDPD_AUXP

DDPB_HPD

DDPC_HPD

DDPD_HPD

PIRQE#/GPIO2

PIRQF#/GPIO3

PIRQG#/GPIO4

PIRQH#/GPIO5

PME#

PLTRST#

R40

R39

R35

R36

N40

N38

H45

K43

J42

H43

K45

J44

K40

K38

H39

G17

F17

L15

M15

AD10

Y11

PCH_HDMI_CLK PCH_HDMI_DATA

PCH_DOCK_CLK PCH_DOCK_DATA

PCH_HDMI_CLK

PCH_HDMI_DATA

PCH_DOCK_CLK

PCH_DOCK_DATA

PCH_DOCK_AUX#

PCH_DOCK_AUX

PCH_HDMI_HPD

PCH_DOCK_HPD

ODD_DETECT#_DP_R

PCH_ODD_DA#

SATA1_DEVSLP#

PCH_GS_ON#

PCI_PME#

PLT_RST#

12

RH53

RH53 100K_0402_5%

100K_0402_5%

1

1 2

RH28 2.2K_0402_5%RH28 2.2K_0402_5%

1 2

RH29 2.2K_0402_5%RH29 2.2K_0402_5%

1 2

RH136 2.2K_0402_5%RH136 2.2K_0402_5%

1 2

RH138 2.2K_0402_5%RH138 2.2K_0402_5%

PCH_HDMI_CLK <34>

PCH_HDMI_DATA <34>PCH_CRT_G<35>

PCH_DOCK_AUX# <42>

PCH_DOCK_AUX <42>

PCH_HDMI_HPD <34>

PCH_DOCK_HPD <42>

ODD_DETECT#_DP_R <38>

PCH_ODD_DA# <38>

SATA1_DEVSLP# <40>

PCH_GS_ON# <33>

PCI_PME# <42>

PLT_RST# <17,39,41,42,44,48>

To JIMIN1.Pin38

Integrated Pull-Up 20K

+3VS

A16 swap overide Strap/Top-Block Swap Override jumper

Low = A16 swap override/Top-Block

PCI_GNT3#

A A

1. The signal has a weak internal pull-up, which is disabled after PLTRST# deasserts.

2. When sampled : Rising edge of PWROK

Swap Override enabled

**High=Default

*

5

Boot BIOS Straps (BBS)

BBS_BIT1 (GPIO51)

1. GPIO51/19 has weak internal pull-up via 20kohm

2. The internal pull-up is disabled after PLTRST# deasserts.

3. GPIO51 (bit 11) at the rising edge of PWROK SATA1GP/GPIO19 (bit 10) at the rising edge of PWROK.

BBS_BIT0 (GPIO19)

Boot BIOS Location

00 LPC

0 1 Reserved (NAND)

1 0

11 SPI

PCI

*

4

For ESD

PCH_ODD_DA#

1

CH12

@ CH12

@

220P_0402_50V8-J

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/12/05

LC Future Center Secret Data

Deciphered Date

2

2014/12/05

Title

PCH_CRT/EDP/DDP

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

E440 NM-A151

E440 NM-A151E440 NM-A151

1

14 57

of

1.0

5

4

3

2

1

1 2

RH57 10K_0402_5%RH57 10K_0402_5%

D D

C C

B B

+3VALW

Stuff RH289 if EC does not want to involve in the handshake mechanism for the DeepSX state entry and exit

1 2

RH58 200K_0402_5%RH58 200K_0402_5%

1 2

RH59 10K_0402_5%RH59 10K_0402_5%

1 2

RH61 0_0402_5%@RH61 0_0402_5%@

DMI_CTX_PRX_N[3:0]<5>

DMI_CTX_PRX_P[3:0]<5>

DMI_CRX_PTX_N[3:0]<5>

DMI_CRX_PTX_P[3:0]<5>

EC to PCH

APWROK may come up earlier than PWROK but no later

PCH to EC

PCH_PWROK<48,8>

PCH_APWROK<48>

SUSWARN#<48>

+1.5VS

SUSACK#<48>

+3VS

+3VALW

+3V_PCH

SUSWARN#_R

AC_PRESENT

EC_RSMRST#

SUSWARN#_RSUSACK#_R

+1.5VS

1 2

RH67 7.5K_0402_1%RH67 7.5K_0402_1%

1 2

RH68 0_0402_5%RH68 0_0402_5%

1 2

RH70 10K_0402_5%RH70 10K_0402_5%

1 2

RH73 0_0402_5%RH73 0_0402_5%

1 2

RH74 0_0402_5%RH74 0_0402_5%

DRAMPWROK<6>

EC_RSMRST#<48>

1 2

RH75 0_0402_5%RH75 0_0402_5%

PBTN_OUT#<48>

AC_PRESENT<48>

1 2

RH76 10K_0402_5%RH76 10K_0402_5%

1 2

RH78 10K_0402_5%RH78 10K_0402_5%

DMI_CTX_PRX_N0 DMI_CTX_PRX_N1

DMI_CTX_PRX_N2 DMI_CTX_PRX_N3

DMI_CTX_PRX_P0 DMI_CTX_PRX_P1

DMI_CTX_PRX_P2 DMI_CTX_PRX_P3

DMI_CRX_PTX_N0 DMI_CRX_PTX_N1

DMI_CRX_PTX_N2 DMI_CRX_PTX_N3

DMI_CRX_PTX_P0 DMI_CRX_PTX_P1

DMI_CRX_PTX_P2 DMI_CRX_PTX_P3

DMI_RCOMP

SUSACK#_R

SYS_RESET#

SYS_PWROK

PWROK

APWROK

DRAMPWROK

EC_RSMRST#

SUSWARN#_R

PBTN_OUT#

AC_PRESENT

PCH_BATLOW#

RI#

VGATE<64>

UH1B

AW22

DMI_RXN_0

AR20

DMI_RXN_1

AP17

DMI_RXN_2

AV20

DMI_RXN_3

AY22

DMI_RXP_0

AP20

DMI_RXP_1

AR17

DMI_RXP_2

AW20

DMI_RXP_3

BD21

DMI_TXN_0

BE20

DMI_TXN_1

BD17

DMI_TXN_2

BE18

DMI_TXN_3

BB21

DMI_TXP_0

BC20

DMI_TXP_1

BB17

DMI_TXP_2

BC18

DMI_TXP_3

BE16

DMI_IREF

AW17

TP12

AV17

TP7

AY17

DMI_RCOMP

R6

SUSACK#

AM1

SYS_RESET#

AD7

SYS_PWROK

F10

PWROK

AB7

APWROK

H3

DRAMPWROK

J2

RSMRST#

J4

SUSWARN#/SUSPWRNACK/GPIO30

K1

PWRBTN#

E6

ACPRESENT/GPIO31

K7

BATLOW#/GPIO72

N4

RI#

AB10

TP21

D2

SLP_WLAN#/GPIO29

LYNX-POINT-DH82LPMS_BGA695

SA00005U830

VGATE

PCH_PWROK

12

LPT_PCH_M_EDS

APWROK only for A phase

A A

PWROK APWROK

1 2

RH13 0_0402_5%@RH13 0_0402_5%@

5

4

+3VS+3V_PCH

1

CH13

CH13 .1U_0402_16V4-Z

.1U_0402_16V4-Z

2

5

2

P

B

4

Y

1

A

G

UH3

3

MC74VHC1G08DFT2G SC70 5P

RH62

RH62 10K_0402_5%

10K_0402_5%

DMI

System Power

Management

MC74VHC1G08DFT2G SC70 5P

REV = 5

FDI

4 OF 11

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

FDI_RXN_0

FDI_RXN_1

FDI_RXP_0

FDI_RXP_1

TP16

TP5

TP15

TP10

FDI_CSYNC

FDI_INT

FDI_IREF

TP17

TP13

FDI_RCOMP

DSWVRMEN

DPWROK

WAKE#

CLKRUN#

SUS_STAT#/GPIO61

SUSCLK/GPIO62

SLP_S5#/GPIO63

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

SLP_LAN#

3

SYS_PWROK

12

R1

@ R1

@

100K_0402_5%

AJ35

FDI_CTX_PRX_N0

AL35

FDI_CTX_PRX_N1

AJ36

FDI_CTX_PRX_P0

AL36

FDI_CTX_PRX_P1

AV43

AY45

AV45

AW44

AL39

FDI_CSYNC

AL40

FDI_INT

AT45

FDI_IREF

AU42

AU44

AR44

FDI_RCOMP

C8

DSWVRMEN

L13

DPWROK EC_DPWROK

K3

WAKE#

AN7

PM_CLKRUN#

U7

Y6

Y7

C6

H1

F3

F1

AY3

G5

Can be left NC if no use integrated LAN. 10/06 Test point request

2012/12/05

1

SUS_STAT#

1

SUSCLK

PM_SLP_S5#

PM_SLP_S4#

PM_SLP_S3#

PM_SLP_A#

PM_SLP_SUS#_R

H_PM_SYNC

1

PCH_SLPLAN#

LC Future Center Secret Data

Deciphered Date

FDI_CTX_PRX_N0 <8>

FDI_CTX_PRX_N1 <8>

FDI_CTX_PRX_P0 <8>

FDI_CTX_PRX_P1 <8>

FDI_CSYNC <5>

FDI_INT <5>

1 2

RH65 0_0402_5%RH65 0_0402_5%

1 2

RH66 7.5K_0402_1%RH66 7.5K_040 2_1%

1 2

RH69 330K_0402_5%RH69 330K_0402_5%

1 2

RH71 0_0402_5%RH71 0_0402_5%

1 2

RH72 0_0402_5%@RH72 0_0402_5%@

PM_CLKRUN# <44>

T72 @T72 @

T73 @T73 @

PM_SLP_S5# <48>

PM_SLP_S4# <48>

PM_SLP_S3# <48>

PM_SLP_A# <48>

1 2

RH77 0_0402_5%RH77 0_0402_5%

H_PM_SYNC <6>

T74 @T74 @

2

+1.5VS

+RTCVCC

WLAN_WAKE#

PM_SLP_SUS#

Can be left NC when IAMT is not support on the platfrom

2014/12/05

DPWROK

1 2

RH60 100K_0402_5%RH60 100K_0402_5%

100 kOhms ±1% pull-down to GND

DSWVREN must be always pulled high to +RTCVCC DSWVREN - Internal Deep Sleep 1.05V regulator

：：：：

Enable

**H

*

：：：：

Disable

L

EC_DPWROK <48>

WLAN_WAKE# <39>

WAKE#

PM_CLKRUN#

For Deep S3

PM_SLP_SUS# <48,55>

RH63 10K_0402_5%RH63 10K_0402_5%

RH64 10K_0402_5%RH64 10K_0402_5%

For Deep S3

For WLAN WAKE# (Disable)

1 2

SUSCLK/GPIO62

This signal has a weak internal pull-up. 0 = Disable PLL On-Die voltage regulator. 1 = Enable PLL On-Die voltage regulator.

*

NOTES:

1. The internal pull-up is disabled after RSMRST# deasserts.

2. This signal is in the Suspend well.

Title

PCH_DMI/FDI/PM

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

E440 NM-A151

E440 NM-A151E440 NM-A151

1

15 57

+3VALW

of

+3VS

1.0

5

D D

1 2

RH80 10K_0402_5%RH80 10K_0402_5%

+3V_PCH

1. No use Native function

2. When configured as GPIO, default direction is Output (GPO).

CardReader, Core

LAN, Suspend

WLAN, Suspend

+3V_PCH

C C

+3V_PCH

When configured as GPIO, default direction is Input (GPI).RH87, 90 and 94

CLK_PCI_EC<48>

CLK_PCI_DB<39>

CLK_PCI_TPM<44>

CLK_PCIE_CR#<41>

CLK_PCIE_CR<41>

CLKREQ_CR#<41>

CLK_PCIE_LAN#<42> CLK_PCIE_LAN<42> CLKREQ_LAN#<42>

CLK_PCIE_WLAN#<39> CLK_PCIE_WLAN<39> CLKREQ_WLAN#<39>

1 2

RH87 10K_0402_5%RH87 10K_0402_5%

1 2

RH90 10K_0402_5%RH90 10K_0402_5%

1 2

RH94 10K_0402_5%RH94 10K_0402_5%

1 2

RH96 22_0402_5%RH96 22_0402_5%

1 2

RH97 22_0402_5%@RH97 22_0402_5%@

1 2

RH98 22_0402_5%TPM@RH98 22_0402_5%TPM@

1 2

RH99 22_0402_5%RH99 22_0402_5%

CLK_PCI_LOOPBACK

4

PCH_GPIO73

CLK_PCIE_CR#

CLK_PCIE_CR

CLKREQ_CR#

CLK_PCIE_LAN# CLK_PCIE_LAN CLKREQ_LAN#

CLK_PCIE_WLAN# CLK_PCIE_WLAN CLKREQ_WLAN#

PCH_GPIO44

PCH_GPIO45

PCH_GPIO46

Remove TP

CLK_PCI_EC_R

PCH_CLK_PCI_DB

CLK_PCI_TPM_R

PCI_LOOPBACKOUT

UH1C

Y43

CLKOUT_PCIE_N_0

Y45

CLKOUT_PCIE_P_0

AB1

PCIECLKRQ0#/GPIO73

AA44

CLKOUT_PCIE_N_1

AA42

CLKOUT_PCIE_P_1

AF1

PCIECLKRQ1#/GPIO18

AB43

CLKOUT_PCIE_N_2

AB45

CLKOUT_PCIE_P_2

AF3

PCIECLKRQ2#/GPIO20/SMI#

AD43

CLKOUT_PCIE_N_3

AD45

CLKOUT_PCIE_P_3

T3

PCIECLKRQ3#/GPIO25

AF43

CLKOUT_PCIE_N_4

AF45

CLKOUT_PCIE_P_4

V3

PCIECLKRQ4#/GPIO26

AE44

CLKOUT_PCIE_N5

AE42

CLKOUT_PCIE_P_5

AA2

PCIECLKRQ5#/GPIO44

AB40

CLKOUT_PCIE_N_6

AB39

CLKOUT_PCIE_P_6

AE4

PCIECLKRQ6#/GPIO45

AJ44

CLKOUT_PCIE_N_7

AJ42

CLKOUT_PCIE_P_7

Y3

PCIECLKRQ7#/GPIO46

AH43

CLKOUT_ITPXDP_N

AH45

CLKOUT_ITPXDP_P

D44

CLKOUT_33MHZ0

E44

CLKOUT_33MHZ1

B42

CLKOUT_33MHZ2

F41

CLKOUT_33MHZ3

A40

CLKOUT_33MHZ4

CLOCK SIGNAL

LYNX-POINT-DH82LPMS_BGA695

SA00005U830

LPT_PCH_M_EDS

REV = 5

PEG_A_CLKRQ#/GPIO47

PEG_B_CLKRQ#/GPIO56

CLKIN_33MHZLOOPBACK

2 OF 11

3

CLKOUT_PEG_A_N

CLKOUT_PEG_A_P

CLKOUT_PEG_B_N

CLKOUT_PEG_B_P

CLKOUT_DMI_N

CLKOUT_DMI_P

CLKOUT_DP_N CLKOUT_DP_P

CLKOUT_DPNS_N CLKOUT_DPNS_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_GND_N

CLKIN_GND_P

CLKIN_DOT96N CLKIN_DOT96P

CLKIN_SATA_N CLKIN_SATA_P

REFCLK14IN

XTAL25_IN

XTAL25_OUT

CLKOUTFLEX0/GPIO64

CLKOUTFLEX1/GPIO65

CLKOUTFLEX2/GPIO66

CLKOUTFLEX3/GPIO67

ICLK_IREF

TP19 TP18

DIFFCLK_BIASREF

AB35

AB36

AF6

Y39

Y38

U4

AF39

AF40

AJ40 AJ39

AF35 AF36

AY24 AW24

AR24 AT24

H33 G33

BE6 BC6

F45 D17

AM43 AL44

C40

F38

F36

F39

AM45

AD39 AD38

AN44

CLK_PCIE_VGA#

CLK_PCIE_VGA

CLK_REQ_GPU#_R

PCH_GPIO56

CLK_CPU_DMI#

CLK_CPU_DMI

CLK_CPU_SSC_DPLL# CLK_CPU_SSC_DPLL

CLK_CPU_DPLL# CLK_CPU_DPLL

CLK_BUF_CPU_DMI# CLK_BUF_CPU_DMI

CLKIN_BUF_DMI2# CLKIN_BUF_DMI2

CLK_BUF_DREF_96M# CLK_BUF_DREF_96M

CLK_BUF_PCIE_SATA# CLK_BUF_PCIE_SATA

CLK_BUF_ICH_14M CLK_PCI_LOOPBACK

PCH_XTAL25_IN PCH_XTAL25_OUT

PCH_GPIO64

PCH_GPIO65

LAN_25M

PCH_GPIO67

+1.5VS

PCH_CLK_BIASREF

2

CLK_PCIE_VGA# <23>

CLK_PCIE_VGA <23>

CLK_REQ_GPU#_R <23>

CLK_CPU_DMI# <6>

CLK_CPU_DMI <6>

CLK_CPU_SSC_DPLL# <6> CLK_CPU_SSC_DPLL <6>

CLK_CPU_DPLL# <6> CLK_CPU_DPLL <6>

1 2

RH83 10K_0402_5%RH83 10K_0402_5%

1 2

RH84 10K_0402_5%RH84 10K_0402_5%

1 2

RH85 10K_0402_5%RH85 10K_0402_5%

1 2

RH86 10K_0402_5%RH86 10K_0402_5%

1 2

RH88 10K_0402_5%RH88 10K_0402_5%

1 2

RH89 10K_0402_5%RH89 10K_0402_5%

1 2

RH91 10K_0402_5%RH91 10K_0402_5%

1 2

RH92 10K_0402_5%RH92 10K_0402_5%

1 2

RH93 10K_0402_5%RH93 10K_0402_5%

1 2

RH95 0_0402_5%@RH95 0_0402_5%@

PCH_GPIO67 <19>

+1.5VS

1 2

RH100 7.5K_0402_1%RH100 7.5K_0402_1%

Reseve for SKU ID

CLK_REQ_GPU#_R

PCH_GPIO56

PCH_LAN_25M <42>

+1.05VS_+1.5VS_RUN

1

1 2

RH79 10K_0402_5%RH79 10K_0402_5%

1 2

RH81 10K_0402_5%RH81 10K_0402_5%

+1.5VS

+3V_PCH

B B

+3V_PCH

1 2

RH101 10K_0402_5%RH101 10K_0402_5%

1 2

RH103 10K_0402_5%RH103 10K_0402_5%

+3VS

A A

Reserve for EMI please close to PCH

CLK_PCI_LOOPBACK

5

1 2

RH105 10K_0402_5%RH105 10K_0402_5%

RH102

1 2

@

33_0402_5%

CLKREQ_LAN#

CLKREQ_WLAN#

CLKREQ_CR#

CH14

1 2

@

22P_0402_50V8-J

4

PCH Crystal Project Phase ID

PCH_XTAL25_IN

PCH_XTAL25_OUT

CH15

12P_0402_50V8-J

1

2

1 2

RH104 1M_0402_5%RH104 1M_0402_5%

YH2

1

OSC1

GND12OSC2

25MHZ_10PF_7V25000014

GND2

4

3

1

CH16

CH16 12P_0402_50V8-J

12P_0402_50V8-J

2

SDV, FVT

SIT2 (R 0.5)

SIT (R 0.4)

SVT

*

Change to 7V25000014 (TXC),. Cap 15pF*2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/12/05

LC Future Center Secret Data

Deciphered Date

PCH_GPIO64Project Phase

0 0

0 1

1 0

1 1

2014/12/05

2

PCH_GPIO65

+3VS

1 2

RH31 10K_0402_5%RH31 10K_0402_5%

1 2

RH82 10K_0402_5%RH82 10K_0402_5%

1 2

RH152 10K_0402_5%@RH152 10K_0402_5%@

1 2

RH162 10K_0402_5%@RH162 10K_0402_5%@

Title

PCH_PCIE/CLK

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

E440 NM-A151

E440 NM-A151E440 NM-A151

1

PCH_GPIO64

PCH_GPIO65

PCH_GPIO64

PCH_GPIO65

16 57

of

1.0

5

EC, MINI CARD and TPM Module debug port

LPC_AD[3:0]<39,44,48>

D D

+3VS

C C

1 2

RH110 10K_0402_5%RH110 10K_0402_5%

1 2

RH119 10K_0402_5%RH119 10K_0402_5%

SERIRQ

PCH_GPIO23

SPI_CLK_8MB SPI_CLK_4MB

SPI_CS0#_8MB

SPI_CS1#_4MB

SPI_SI_8MB SPI_SI_4MB SPI_SI

SPI_SO_8MB SPI_SO_4MB

SPI_IO2_8MB SPI_IO2_4MB

SPI_IO3_8MB SPI_IO3 SPI_IO3_4MB

+3V_SPI

RH111 33_0402_5%RH111 33_0402_5% RH112 33_0402_5%RH112 33_0402_5%

RH113 0_0402_5%RH113 0_0402_5%

RH114 0_0402_5%RH114 0_0402_5%

RH115 33_0402_5%RH115 33_0402_5% RH116 33_0402_5%RH116 33_0402_5%

RH117 33_0402_5%RH117 33_0402_5% RH118 33_0402_5%RH118 33_0402_5%

RH129 33_0402_5%RH129 33_0402_5% RH130 33_0402_5%RH130 33_0402_5%

RH131 33_0402_5%RH131 33_0402_5% RH132 33_0402_5%RH132 33_0402_5%

Near U4M1 and U8M1

RH16 1K_0402_5%RH16 1K_0402_5% RH17 1K_0402_5%RH17 1K_0402_5%

1 2 1 2

1 2

1 2 1 2

LPC_FRAME#<39,44,48>

Near U4M1

8MB + 4MB SPI ROM, 5MB ME(SBA), Security EEPROM

Security EEPROM

SBA Fun. Power rail

B B

+3VS

PLT_RST#<14,39,41,42,44,48>

+3VS

+3VM

8MB(64Mb) 4MB(32Mb)

CH17

VCC

CLK

DI

CH17

1 2

10P_0402_50V8-J

8

7

6

5

RH133

1 2

@

10_0402_5%

U8M1

SPI_CS0#_8MB

SPI_SO_8MB

A A

SPI_IO2_8MB

1

CS#

2

DO

3

WP#

4

GND

W25Q64FVSSIG_SO8

SA000039A2J

5

HOLD#

RH124

1 2

@

0_0402_5%

1 2

RH125 0_0402_5%@RH125 0_0402_5%@

1 2

RH127 0_0402_5%RH127 0_0402_5%

For EMI For EMI

@

SPI_IO3_8MB SPI_IO2_4MB

SPI_CLK_8MB

SPI_SI_8MB

PLT_RST#

+3V_SPI +3V_SPI

2

CH19

0.1U_0402_10V7-K

1

4

UH1D

LPC_AD0

LPC_AD1

LPC_AD2

LPC_AD3

LPC_FRAME#

PCH_GPIO23

SERIRQ<44,48>

SERIRQ

SPI_CLK

SPI_CS0#

SPI_CS1#

SPI_SO

SPI_IO2

SPI_IO2 SPI_IO3

A20

LAD_0

C20

LAD_1

A18

LAD_2

C18

LAD_3

B21

LFRAME#

D21

LDRQ0#

G20

LDRQ1#/GPIO23

AL11

SERIRQ

AJ11

SPI_CLK

AJ7

SPI_CS0#

AL7

SPI_CS1#

AJ10

SPI_CS2#

AH1

SPI_MOSI

AH3

SPI_MISO

AJ4

SPI_IO2

AJ2

SPI_IO3

LYNX-POINT-DH82LPMS_BGA695

SA00005U830

SPILPC

LPT_PCH_M_EDS

REV = 5

SMBus

C-Link

Thermal

3 OF 11

3

SML1ALERT#/PCHHOT#/GPIO74

SMBALERT#/GPIO11

SMBCLK

SMBDATA

SML0ALERT#/GPIO60

SML0CLK

SML0DATA

SML1CLK/GPIO58

SML1DATA/GPIO75

CL_CLK

CL_DATA

CL_RST#

TD_IREF

SM Bus

2

N7

PCH_SMBALERT#

R10

PCH_SMBCLK

U11

PCH_SMBDATA

N8

PCH_GPIO60

U8

PCH_SML0CLK

R7

PCH_SML0DATA

H6

PCH_GPIO74

K6

PCH_SML1CLK

N11

PCH_SML1DATA

AF11

AF10

AF7

BA45

TP1

BC45

TP2

BE43

TP4

BE44

TP3

AY43

PCH_TD_IREF

Touch Panel

PCH_SMBALERT#

PCH_GPIO60

PCH_GPIO74

PCH_TD_IREF

RH106 10K_0402_5%RH106 10K_0402_5%

RH107 1K_0402_5%RH107 1K_0402_5%

RH108 10K_0402_5%RH108 10K_0402_5%

RH109 8.2K_0402_1%RH109 8.2K_0402_1%

PCH_SML1CLK PCH_SML1DATA PCH_SMBDATA PCH_SMBCLK

PCH_SML0CLK PCH_SML0DATA

1 2

RPH3

1 8 2 7 3 6 4 5

2.2K_0804_5%

SD30922010T

RPH4

1 8 2 7 3 6 4 5

2.2K_0804_5%

SD30922010T

1

+3V_PCH

DIMM1, DIMM2, WLAN(@), CP, Security EEPROM

+3VS

Touch Panel

SMB_CLK_TPANEL <44>

SMB_DATA_TPANEL <44>

17 57

of

1.0

USROM1

1

NC_1

2 3 4

VCC

NC_2

WP

SCL

PROT#

SDA

GND

PCA24S08AD_SO8

SA00004MK00/SA00004ML00

+3V_SPI

0.085 A

SPI_CLK_4MBSPI_CLK_8MB

SPI_CS1#_4MB SPI_SO_4MB

SA00005P500 SA00003K80J --> EOL

4

8 7 6

PM_SMBCLK

5

PM_SMBDATA

U4M1

1

CS#

2

DO

3

WP#

4

GND

W25Q32FVSSIQ_SO8

SA00005P500

RH134

1 2

@

10_0402_5%

VCC

HOLD#

CLK

8 7 6 5

DI

+3VS

1

C1

0.1U_0402_16V4Z

2

CH18

1 2

@

10P_0402_50V8-J

SPI_IO3_4MB SPI_CLK_4MB SPI_SI_4MB

+3VS

2

G

PCH_SMBCLK

PCH_SMBDATA

PCH_SML1DATA EC_SMB_DA3

2

CH20

0.1U_0402_10V7-K

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/12/05

PCH_SML0CLK

PCH_SML0DATA

LC Future Center Secret Data

Deciphered Date

2

2014/12/05

6 1

D

5

QH1A

G

2N7002KDWH_SOT363-6

SB00000YR00

3 4

S

D

QH1B

QH1B 2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

SB00000YR00

+3VS

2

G

6 1

D

5

QH2A

G

2N7002KDWH_SOT363-6

SB00000YR00

3 4

SB00000YR00

S

D

QH2B

QH2B 2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

SB00000YR00

+3VS +3VS

2

G

6 1

D

5

QH3A

G

2N7002KDWH_SOT363-6

SB00000YR00

S

D

QH3B

QH3B 2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

SB00000YR00

1 2

RH121 4.7K_0402_5%RH121 4.7K_0402_5%

1 2

RH123 4.7K_0402_5%RH123 4.7K_0402_5%

PM_SMBCLK

S

PM_SMBDATA

PM_SMBCLK <11,12,39,43>

PM_SMBDATA <11,12,39,43>

GPU, EC, Thermal Sensor

2N7002KDWH Vth= min 1V, max 2.5V ESD 2KV

EC_SMB_CK3PCH_SML1CLK

S

RH135 2.2K_0402_5%RH135 2.2K_0402_5%

RH137 2.2K_0402_5%RH137 2.2K_0402_5%

SMB_CLK_TPANEL

S

SMB_DATA_TPANEL

Title

PCH_LPC/SPI/SM BUS

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

EC_SMB_CK3 <23,32,48>

EC_SMB_DA3 <23,32,48>

1 2

E440 NM-A151

E440 NM-A151E440 NM-A151

1

5

D D

PCIE_PRX_DTX_N3<41>

CardReader

C C

LAN

WLAN

B B

PCIE_PRX_DTX_P3<41>

PCIE_PTX_C_DRX_N3<41> PCIE_PTX_C_DRX_P3<41>

PCIE_PRX_DTX_N4<42> PCIE_PRX_DTX_P4<42>

PCIE_PTX_C_DRX_N4<42> PCIE_PTX_C_DRX_P4<42>

PCIE_PRX_DTX_N5<39> PCIE_PRX_DTX_P5<39>

PCIE_PTX_C_DRX_N5<39> PCIE_PTX_C_DRX_P5<39>

1 2

CH21 0.1U_0402_10V7-KCH21 0.1U_0402_10V7-K

1 2

CH22 0.1U_0402_10V7-KCH22 0.1U_0402_10V7-K

1 2

CH23 0.1U_0402_10V7-KCH23 0.1U_0402_10V7-K

1 2

CH24 0.1U_0402_10V7-KCH24 0.1U_0402_10V7-K

1 2

CH25 0.1U_0402_10V7-KCH25 0.1U_0402_10V7-K

1 2

CH26 0.1U_0402_10V7-KCH26 0.1U_0402_10V7-K

+1.5VS

4

+1.5VS

R2

1 2

7.5K_0402_1%

PCIE_PRX_DTX_N3 PCIE_PRX_DTX_P3

PCIE_PTX_DRX_N3 PCIE_PTX_DRX_P3

PCIE_PRX_DTX_N4 PCIE_PRX_DTX_P4

PCIE_PTX_DRX_N4 PCIE_PTX_DRX_P4

PCIE_PRX_DTX_N5 PCIE_PRX_DTX_P5

PCIE_PTX_DRX_N5 PCIE_PTX_DRX_P5

PCIE_RCOMP

UH1I

AW31

PERN1/USB3RN3

AY31

PERP1/USB3RP3

BE32

PETN1/USB3TN3

BC32

PETP1/USB3TP3

AT31

PERN2/USB3RN4

AR31

PERP2/USB3RP4

BD33

PETN2/USB3TN4

BB33

PETP2/USB3TP4

AW33

PERN_3

AY33

PERP_3

BE34

PETN_3

BC34

PETP_3

AT33

PERN_4

AR33

PERP_4

BE36

PETN_4

BC36

PETP_4

AW36

PERN_5

AV36

PERP_5

BD37

PETN_5

BB37

PETP_5

AY38

PERN_6

AW38

PERP_6

BC38

PETN_6

BE38

PETP_6

AT40

PERN_7

AT39

PERP_7

BE40

PETN_7

BC40

PETP_7

AN38

PERN_8

AN39

PERP_8

BD42

PETN_8

BD41

PETP_8

BE30

PCIE_IREF

BC30

TP11

BB29

TP6

BD29

PCIE_RCOMP

LYNX-POINT-DH82LPMS_BGA695

SA00005U830

LPT_PCH_M_EDS

PCIe

9 OF 11

3

REV = 5

USB

USB2N0 USB2P0 USB2N1 USB2P1 USB2N2 USB2P2 USB2N3 USB2P3 USB2N4 USB2P4 USB2N5 USB2P5 USB2N6 USB2P6 USB2N7 USB2P7 USB2N8 USB2P8 USB2N9

USB2P9 USB2N10 USB2P10 USB2N11 USB2P11 USB2N12 USB2P12 USB2N13 USB2P13

USB3RN1

USB3RP1 USB3TN1 USB3TP1

USB3RN2

USB3RP2 USB3TN2 USB3TP2

USB3RN5

USB3RP5 USB3TN5 USB3TP5

USB3RN6

USB3RP6 USB3TN6 USB3TP6

USBRBIAS#

USBRBIAS

TP24 TP23

OC0#/GPIO59 OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43

OC5#/GPIO9 OC6#/GPIO10 OC7#/GPIO14

2

B37

USB20_N0

D37

USB20_P0

A38

USB20_N1

C38

USB20_P1

A36 C36 A34

USB20_N3

C34

USB20_P3

B33

USB20_N4

D33

USB20_P4

F31

USB20_N5

G31

USB20_P5

K31 L31

Some PCH config not support USB port 6 & 7.

G29 H29 A32 C32 A30

USB20_N9

C30

USB20_P9

B29

USB20_N10

D29

USB20_P10

A28

USB20_N11

C28

USB20_P11

G26

USB20_N12

F26

USB20_P12

F24

USB20_N13

G24

USB20_P13

AR26

USB30_RX_N1

AP26

USB30_RX_P1

BE24

USB30_TX_N1

BD23

USB30_TX_P1

AW26

USB30_RX_N2

AV26

USB30_RX_P2

BD25

USB30_TX_N2

BC24

USB30_TX_P2

AW29

USB30_RX_N5

AV29

USB30_RX_P5

BE26

USB30_TX_N5

BC26

USB30_TX_P5

AR29 AP29 BD27 BE28

K24

USBRBIAS

K26

Within 500 mils

M33 L33

P3

USB_OC0#

V1

USB_OC1#

U2

USB_OC2#

P1

USB_OC3#

M3

USB_OC4#

T1

USB_OC5#

N2

PCH_3G_DET#

M1

USB_OC7#

USB20_N0 <37> USB20_P0 <37> USB20_N1 <37> USB20_P1 <37>

USB20_N3 <42> USB20_P3 <42> USB20_N4 <44> USB20_P4 <44>

1

T77 @T77 @

1

T78 @T78 @

USB20_N9 <41> USB20_P9 <41>

USB20_N10 <39> USB20_P10 <39> USB20_N11 <40> USB20_P11 <40> USB20_N12 <44> USB20_P12 <44> USB20_N13 <36> USB20_P13 <36>

USB30_RX_N1 <4 2> USB30_RX_P1 <42>

USB30_TX_N1 <42>

USB30_TX_P1 <42> USB30_RX_N2 <3 7> USB30_RX_P2 <37>

USB30_TX_N2 <37>

USB30_TX_P2 <37> USB30_RX_N5 <3 7> USB30_RX_P5 <37>

USB30_TX_N5 <37>

USB30_TX_P5 <37>

1 2

RH139 22.6_0402_1%RH139 22.6_0402_1%

USB_OC0# <37>

USB_OC5# <41> PCH_3G_DET# <40>

LEFT USB20 (Front)

LEFT USB20 (Back)

Docking USB3.0

Touch Panel

RIGHT USB20 Sleep&charge (S/B), Debug port,

WLAN

WWAN

FingerPrint (S/B)

CAMERA

RIGHT Docking

LEFT USB30 (Front)

LEFT USB30 (Back)

USB Port0, 1 (LEFT USB)

USB Port5 (Sleep&Charge)

USB_OC1# USB_OC2# USB_OC5# USB_OC0#

USB_OC3# PCH_3G_DET# USB_OC7# USB_OC4#

1

RPH1

1 8 2 7 3 6 4 5

10K_0804_8P4R_5%

SD300002P0T

RPH2

1 8 2 7 3 6 4 5

10K_0804_8P4R_5%

SD300002P0T

+3V_PCH

USB2.0 : OC#0-3 --> Port 0-7 OC#4-7 --> Port 8-13

A A

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

OC[3:0]# should be connected with USB 2.0 ports 0 - 7 and any 4 of USB 3.0 ports 1 - 6.

LC Future Center Secret Data

Issued Date

2012/12/05

3

LC Future Center Secret Data

Deciphered Date

2

2014/12/05

Port1

Port2

Port5

X Sleep&Charge (Right)

USB2.0USB3.0

Port3

Port0

Port1

Port9

Title

PCH_PCIE/USB/OC#

Size Document Number Rev

Custom

Date: Sheet

OC#

X

OC0#

OC5#

Thursday, July 11, 2013

Note

Docking (Right)

LEFT USB (Front)

LEFT USB (Back)

E440 NM-A151

E440 NM-A151E440 NM-A151

1

18 57

1.0

of

5

+3VS

1 2

RH141 10K_0402_5%RH141 10K_0402_5%

1 2

D D

C C

+3VALW

RH143 10K_0402_5%RH143 10K_0402_5%

RH144 10K_0402_5%RH144 10K_0402_5%

RH145 10K_0402_5%RH145 10K_0402_5%

RH146 10K_0402_5%RH146 10K_0402_5%

RH147 10K_0402_5%RH147 10K_0402_5%

RH148 10K_0402_5%RH148 10K_0402_5%

RH149 10K_0402_5%RH149 10K_0402_5%

RH150 10K_0402_5%RH150 10K_0402_5%

RH151 200K_0402_5%RH151 200K_0402_5%

RH153 10K_0402_5%@RH153 10K_0402_5%@

RH154 10K_0402_5%RH154 10K_0402_5%

RH155 10K_0402_5%RH155 10K_0402_5%

RH157 10K_0402_5%RH157 10K_0402_5%

RH158 10K_0402_5%RH158 10K_0402_5%

RH15 10K_0402_5%RH15 10K_0402_5%

+3V_PCH

RH159 10K_0402_5%@RH159 10K_0402_5%@

RH160 10K_0402_5%RH160 10K_0402_5%

RH163 10K_0402_5%RH163 10K_0402_5%

RH177 10K_0402_5%RH177 10K_0402_5%

RH161 10K_0402_5%RH161 10K_0402_5%

RH14 10K_0402_5%RH14 10K_0402_5%

RH165 10K_0402_5%@RH165 10K_0402_5%@

1 2

FN_LED#_R

F1_LED#_R

F4_LED#_R

GC6_EVENT#_R

EC_SCI#

PCH_BT_DISABLE#

BT_DET#

3G_OFF#

GPS_OFF#

ODD_DETECT#

ODD_DETECT#_R

PCH_GPIO35

CMOS_ON#

GATEA20

KBRST#

PCH_GPIO37

WWAN_ON

DOCK_DETECT#

PCH_GPIO57

PCH_MSATA_DET

WWAN_ON

TRACKP_ON

PCH_GPIO37

4

1 2

GC6_EVENT#<23,48>

FN_LED#<45>

F1_LED#<45>

RH194 0_0402_5%@RH194 0_0402_5%@

1 2

RH140 0_0402_5%RH140 0_0402_5%

1 2

RH142 0_0402_5%RH142 0_0402_5%

EC_SCI#<48>

DOCK_DETECT#<42>

WWAN_ON<39>

DGPU_PWROK<27,54,62,63>

PCH_BT_DISABLE#<39>

ODD_EN<38>

For tempo detect

TRACKP_ON<43>

1 2

PCH_BT_ON#<39>

ODD_DETECT#_DP<38>

F4_LED#<45>

RH18 0_0402_5%@RH18 0_0402_5%@

1 2

RH19 0_0402_5%@RH19 0_0402_5%@

3G_OFF#<40>

GPS_OFF#<40>

CMOS_ON#<36>

1 2

RH164 0_0402_5%RH164 0_0402_5%

Reseve for SKU ID

BT_DET#<39>

ODD_DETECT#_R ODD_DETECT#

1 2

RH30 0_0402_5%RH30 0_0402_5%

GC6_EVENT#_R

FN_LED#_R

F1_LED#_R

EC_SCI#

DOCK_DETECT#

WWAN_ON

PCH_GPIO16

DGPU_PWROK

PCH_BT_DISABLE#

ODD_EN

PCH_MSATA_DET

TRACKP_ON

ODD_DETECT#_R

PCH_GPIO35

ODD_DETECT#

PCH_GPIO37

PCH_GPIO38

3G_OFF#

GPS_OFF#

PCH_GPIO49

PCH_GPIO57

CMOS_ON#

F4_LED#_R

PCH_GPIO70

BT_DET#

3

LPT_PCH_M_EDS

Output

LPT_PCH_M_EDS

Input

GPIO

NCTF

6 OF 11

REV = 5

UH1F

AT8

BMBUSY#/GPIO0

F13

TACH1/GPIO1

A14

TACH2/GPIO6

G15

TACH3/GPIO7

Y1

GPIO8

K13

LAN_PHY_PWR_CTRL/GPIO12

AB11

GPIO15

AN2

SATA4GP/GPIO16

C14

TACH0/GPIO17

BB4

SCLOCK/GPIO22

Y10

GPIO24

R11

GPIO27

AD11

GPIO28

AN6

GPIO34

AP1

GPIO35/NMI#

AT3

SATA2GP/GPIO36

AK1

SATA3GP/GPIO37

AT7

SLOAD/GPIO38

AM3

SDATAOUT0/GPIO39

AN4

SDATAOUT1/GPIO48

AK3

SATA5GP/GPIO49

U12

GPIO57

C16

TACH4/GPIO68

D13

TACH5/GPIO69

G13

TACH6/GPIO70

H15

TACH7/GPIO71

BE41

VSS_NCTF_1

BE5

VSS_NCTF_2

C45

VSS_NCTF_3

A5

VSS_NCTF_4

LYNX-POINT-DH82LPMS_BGA695

SA00005U830

2

CPU/Misc

RCIN#

PROCPWRGD

THRMTRIP#

PLTRST_PROC#

VSS_N10

VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8

VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21 VSS_NCTF_22 VSS_NCTF_23 VSS_NCTF_24

TP14

PECI

AN10

GATEA20

AY1

AT6

KBRST#

AV3

H_CPUPWRGD

AV1

PCH_THERMTRIP#

AU4

PLTRST_PROC#

N10

PCH_THERMTRIP#

A2 A41 A43 A44 B1 B2 B44 B45 BA1 BC1 BD1 BD2 BD44 BD45 BE2 BE3 D1 E1 E45 A4

GATEA20 <48>

KBRST# <48>

H_CPUPWRGD <6>

PLTRST_PROC# <6>

1 2

RH156 390_0402_5%RH156 390_0402_5%

1 2

RH11 0_0402_5%@RH11 0_0402_5%@

1

H_THERMTRIP# <6>

VGA_THERMTRIP# <23>

B B

PCH_MSATA_DET#<40>

2

G

PCH_MSATA_DET

13

D

QH5

QH5 2N7002KW_SOT323-3

2N7002KW_SOT323-3

S

CONFIG

USB X4,PCIEX8,SATAX6

*

GPIO16, 49

11

01USB X6,PCIEX8,SATAX4

+3VS

1 2

RH167 10K_0402_5%RH167 10K_0402_5%

1 2

RH169 10K_0402_5%RH169 10K_0402_5%

PCH_GPIO16 PCH_GPIO49

No use Flexible I/O pin, delete RH172, RH174

SKU ID

PCH_GPIO38

*

Optimus

Reserve

A A

DIS

UMA

*

14"

*

15"

*

PCH_GPIO67

0 0

0 1

1 0

1 1

5

PCH_GPIO70Function

+3VS

1 2

RH166 10K_0402_5%UMA@RH166 10K_0402_5%UMA@

1 2

RH168 10K_0402_5%UMA@RH168 10K_0402_5%UMA@

1 2

RH170 10K_0402_5%NM15@RH170 10K_0402_5%NM15@

1 2

RH171 10K_0402_5%DIS@RH171 10K_0402_5%DIS@

1 2

RH173 10K_0402_5%DIS@RH173 10K_0402_5%DIS@

1 2

0

RH175 10K_0402_5%NM14@RH175 10K_0402_5%NM14@

1

4

PCH_GPIO38

PCH_GPIO67

PCH_GPIO70

PCH_GPIO38

PCH_GPIO67

PCH_GPIO70

PCH_GPIO67 <16>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/12/05

LC Future Center Secret Data

Deciphered Date

2

2014/12/05

Title

PCH_GPIO/CPU-MISC

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

E440 NM-A151

E440 NM-A151E440 NM-A151

1

19 57

of

1.0

5

4

3

2

1

LH1

RH178

+1.5VS_VCCADAC

D D

LPT_PCH_M_EDS

0.67 A

LPT_PCH_M_EDS

CRT DAC

HVCMOS

Core

PCIe/DMI

SATA

VCCMPHY

REV = 5

FDI

USB3

7 OF 11

0.07 A

0.0133 A

0.183 A

0.133 A

0.261 A

3.269 A

VCCADAC1_5

VSSADAC

VCCADACBG3_3

VCCVRM[1]

VCCIO[1]

VCCIO[2]

VCC3_3_R30 VCC3_3_R32

DCPSUS1

VCCSUS3_3_AJ30 VCCSUS3_3_AJ32

DCPSUS3_AJ26 DCPSUS3_AJ28

VCCIO[3] VCCVRM[2] VCCVRM[3]

VCCVRM[4]

VCCIO[4]

VCCVRM[5]

VCCIO[5]

VCCIO[6]

VCCIO[7]

VCCIO[8]

VCCIO[9]

VCCIO[10] VCCIO[11]

P45

P43

M31

BB44

AN34

AN35

R30 R32

Y12

AJ30 AJ32

AJ26 AJ28 AK20 AK26 AK28

BE22

AK18

AN11

AK22

AM18 AM20 AM22 AP22 AR22 AT22

+3VS

+1.05VS_+1.5VS_RUN

+1.05VS

+3VS

+1.05VM_PCH_DCPSUS1

+3V_PCH

+1.05VM_PCH_DCPSUS3

+1.05VS

+1.05VS_+1.5VS_RUN

+1.05VS

+1.05VS_+1.5VS_RUN

+1.05VS

UH1G

+1.05VS

CH30

CH32

CH31

10U_0603_6.3V6-M

1

2

1U_0402_6.3V6-K

1

2

CH33

+1.05VS

1U_0402_6.3V6-K

1

2

Layout note: Fanout : 5mil

+1.05VM_PCH_VCCASW

C C

12

1

2

+PCH_VCCDSW

RH179

5.11_0402_1%

CH48

CH48 1U_0402_6.3V6-K

1U_0402_6.3V6-K

CH38

22U_0805_6.3V6-M

1

2

CH39

CH40

1U_0402_6.3V6-K

1

2

Breakout : 10mil

+PCH_VCCDSW +1.05VM_PCH_VCCASW

UH1G

AA24

VCC[1]

AA26

VCC[2]

AD20 AD22 AD24 AD26 AD28 AE18 AE20 AE22 AE24 AE26 AG18 AG20 AG22 AG24

AA18

1.312 A

VCC[3] VCC[4] VCC[5] VCC[6] VCC[7] VCC[8] VCC[9] VCC[10] VCC[11] VCC[12] VCC[13] VCC[14] VCC[15] VCC[16]

Y26

VCC[17]

U14

DCPSUSBYP VCCASW[1]

U18

VCCASW[2]

U20

VCCASW[3]

U22

VCCASW[4]

U24

VCCASW[5]

V18

VCCASW[6]

V20

VCCASW[7]

V22

VCCASW[8]

V24

VCCASW[9]

Y18

VCCASW[10]

Y20

VCCASW[11]

Y22

VCCASW[12]

LYNX-POINT-DH82LPMS_BGA695

SA00005U830

+3VS

CH27

CH43

.01U_0402_16V7-K

1

2

+3V_PCH

+1.05VS

1U_0402_6.3V6-K

1

2

CH28

CH44

CH29

0.1U_0402_10V7-K

1

2

CH45

1U_0402_6.3V6-K

1

2

1 2

0_0603_5%

10U_0603_6.3V6-M

1

2

+3VS

1

2

+1.05VS_+1.5VS_RUN

1

@ CH42

@

2

CH46

CH47

1U_0402_6.3V6-K

10U_0603_6.3V6-M

1

2

10U_0603_6.3V6-M

1

2

LH1

1 2

BLM18PG181SN1D_2P

CH36

0.1U_0402_10V7-K

CH42 10U_0603_6.3V6-M

10U_0603_6.3V6-M

+1.05VS

1

CH35

CH35 1U_0402_6.3V6-K

1U_0402_6.3V6-K

2

+1.05VS_+1.5VS_RUN

1

CH41

@ CH41

@

10U_0603_6.3V6-M

2

+1.05VS

+1.5VS

+1.05VS_+1.5VS_RUN

1

CH34

@ CH34

@

10U_0603_6.3V6-M

2

+1.05VS_+1.5VS_RUN

1

CH37

@ CH37

@

10U_0603_6.3V6-M

2

PCH Power Rail Table (EDS Rev1.0)

Voltage Rail

Voltage

S0 Iccmax Current (A)

1.05V 1.312 AVCC

B B

VCCIO

1.05V

3.629 A

VCCADAC1_5 1.5V 0.07 A

VCCADAC3_3 0.0133 A3.3V

VCCCLK

VCCCLK3_3

+1.05VS_PCH_VCC +1.05VS_PCH_VCCIO

RH180

1

CH51

@ CH51

@

10U_0603_6.3V6-M

2

1 2

0_0402_5%

RH183

1 2

0_0402_5%

+1.05VM_PCH_DCPSUS1

1

CH49

@ CH49

@

1U_0402_6.3V6-K

+1.05VM_PCH_VCCASW +1.05VS_+1.5VS_RUN

+1.05VS +1.05VM_PCH_VCCASW

A A

+1.05VM

1 2

RH181 0_0603_5%@RH181 0_0603_5%@

1 2

RH184 0_0603_5%RH184 0_0603_5%

5

0.67 A

+1.5VS +1.05VS_+1.5VS_RUN

+1.05VS

4

1 2

RH182 0_0603_5%RH182 0_0603_5%

1 2

RH185 0_0603_5%@RH185 0_0603_5%@

0.183 A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/12/05

2

+1.05VM_PCH_DCPSUS3

1

CH50

@ CH50

@

0.1U_0402_10V7-K

2

LC Future Center Secret Data

Deciphered Date

@

2

+1.05VM_PCH_VCCASW

2014/12/05

Title

Size Document Number Rev

Custom

Date: Sheet

VCCVRM 0.183 A

VCC3_3 3.3V 0.133 A

VCCASW 1.05V

VCCSUSHDA 3.3V 0.01 A

VCCSUS3_3 3.3V 0.261 A

VCCDSW3_3

V_PROC_IO 1.05V 0.004 A

PCH_POWER-1

Thursday, July 11, 2013

1.05V 0.306 A

3.3V

0.055 A

1.5V

0.67 A

3.3V 0.022 AVCCSPI

3.3V 0.015 A

E440 NM-A151

E440 NM-A151E440 NM-A151

1

20 57

1.0

of

5

4

3

2

1

CH52

1 2

+3VS

1

CH68

0.1U_0402_10V7-K

2

+3V_PCH

1

2

+1.05VS

1

CH67

CH67 1U_0402_6.3V6-K

1U_0402_6.3V6-K

2

1

CH53

0.1U_0402_10V7-K

2

1

CH58

0.1U_0402_10V7-K

2

CH64

+1.05VM_PCH_VCCASW

+1.05VS_+1.5VS_RUN

LPT_PCH_M_EDS

0.261 A

0.306 A

0.055 A

0.306 A

LPT_PCH_M_EDS

USB

ICC

REV = 5

8 OF 11

GPIO/LPC

Azalia

RTC

CPU

SPI

Fuse

Thermal

0.015 A

0.01 A

0.004 A

0.022 A

VCCSUS3_3_R20 VCCSUS3_3_R22

VCCDSW3_3

DCPSST

VCC3_3_AE14 VCC3_3_AF12

VCC3_3_AG14

VCCIO[16]

VCCSUSHDA

VCCSUS3_3_K8

VCCRTC

DCPRTC[1] DCPRTC[2]

V_PROC_IO[1] V_PROC_IO[2]

VCCSPI

VCC[19] VCC[20]

VCCASW[13]

VCCASW[14]

VCCVRM[7]

VCC3_3_AK30

VCC3_3_AK32

UH1H

D D

C C

+3V_PCH

1

2

CH54

0.1U_0402_10V7-K

+1.05VS

+3V_PCH

CH56

0.1U_0402_10V7-K

+3VS

1

CH57

0.1U_0402_10V7-K

2

1

+1.05VS

CH59

2

CH59

1U_0402_6.3V6-K

+1.05VS_+1.5VS_RUN

1

2

1

2

CH61

10U_0603_6.3V6-M

+PCH_VCC

+PCH_VCCCLK

+PCH_VCCCLK3_3

+PCH_VCCCLK

+1.05VS

+3VS

+1.05VS

+1.05VM_PCH_DCPSUS2

+PCH_VCC

+PCH_VCCCLK

+PCH_VCCCLK3_3

+PCH_VCCCLK

CPI, 14" only

+1.05VS_+1.5VS_RUN +1.05VS

1

CH86

CH86 10P_0402_50V8-J

10P_0402_50V8-J

2

1

CH87

CH87 10P_0402_50V8-J

10P_0402_50V8-J

2

UH1H

R24

VCCSUS3_3_R24

R26

VCCSUS3_3_R26

R28

VCCSUS3_3_R28

U26

VCCSUS3_3_U26

M24

VSS_USB

U35

VCCUSBPLL

L24

VCC3_3_L24

U30

VCCIO[12]

V28

VCCIO[13]

V30

VCCIO[14]

Y30

VCCIO[15]

Y35

DCPSUS2

AF34

VCCVRM[6]

AP45

VCC[18]

Y32

VCCCLK[1]

M29

VCCCLK3_3[1]

L29

VCCCLK3_3[2]

L26

VCCCLK3_3[3]

M26

VCCCLK3_3[4]

U32

VCCCLK3_3[5]

V32

VCCCLK3_3[6]

AD34

VCCCLK[2]

AA30

VCCCLK[3]

AA32

VCCCLK[4]

AD35

VCCCLK[5]

AG30

VCCCLK[6]

AG32

VCCCLK[7]

AD36

VCCCLK[8]

AE30

VCCCLK[9]

AE32

VCCCLK[10]

LYNX-POINT-DH82LPMS_BGA695

SA00005U830

+3V_PCH

R20 R22

A16

AA14

AE14 AF12 AG14

U36

A26

K8

A6

P14 P16

AJ12 AJ14

AD12

P18 P20

L17

R18

AW40

AK30

AK32

0.1U_0402_10V7-K

+3VALW_VCCDSW3_3

CH55 0.1U_0402_10V7-KCH55 0.1U_0402_10V7-K

+3VS

+1.05VS

+3V_PCH

+RTCVCC

CH63 0.1U_0402_10V7-KCH63 0.1U_0402_10V7-K

+1.05VS_PCH_VPROC

+3VM_VCCSPI

+PCH_VCCCFUSE

+1.05VM_PCH_VCCASW

+1.05VS_+1.5VS_RUN

1 2

RH186 0_0402_5%RH186 0_0402_5%

1 2

RH187 0_0402_5%@RH187 0_0402_5%@

+3VS

CH66

CH65

1U_0402_6.3V6-K

0.1U_0402_10V7-K

1

2

1

2

+3VM_VCCSPI

1

2

+3VALW

+3V_PCH

+RTCVCC

1

CH62

CH62 1U_0402_6.3V6-K

1U_0402_6.3V6-K

2

1 2

RH122 0_0402_5%@RH122 0_0402_5%@

1 2

RH126 0_0402_5%RH126 0_0402_5%

+3V_PCH

1

CH60

0.1U_0402_10V7-K

2

+3VS

+3VM

B B

A A

+1.05VM

+1.05VS

4.7UH_LQM18FN4R7M00D_20%

1 2

RH188 0_0402_5%@RH188 0_0402_5%@

1 2

RH120 0_0402_5%@RH120 0_0402_5%@

LH2

5

+1.05VM_PCH_DCPSUS2

1

CH69

@ CH69

@

1U_0402_6.3V6-K

2

+PCH_VCC +PCH_VCCCLK3_3 +PCH_VCCCFUSE

12

CH78

1

2

+PCH_VCC

CH79

1U_0402_6.3V6-K

10U_0603_6.3V6-M

1

2

+1.05VS

+3VS

4

RH189

1 2

0_0805_5%

RH192

1 2

0_0805_5%

CH70

1U_0402_6.3V6-K

1

2

Place near pin Y32,AA30,AA32

CH80

1U_0402_6.3V6-K

1

2

Place near pin M29

CH71

Place near pin AD34

CH81

Place near pin L29

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

1U_0402_6.3V6-K

1

2

1U_0402_6.3V6-K

1

2

Issued Date

CH72

Place near pin AD35,AD36

CH82

Place near pin L26,M26

3

1U_0402_6.3V6-K

1

2

Place near pin AG30,AG32,AE30,AE32

1U_0402_6.3V6-K

1

2

Place near pin U32,V32

CH73

CH83

1U_0402_6.3V6-K

1

2

1U_0402_6.3V6-K

1

2

2012/12/05

CH74

CH84

1U_0402_6.3V6-K

1

2

1U_0402_6.3V6-K

1

2

+PCH_VCCCLK

+PCH_VCCCLK3_3

LC Future Center Secret Data

Deciphered Date

+1.05VS_PCH_VPROC

2014/12/05

2

CH75

+PCH_VCCCFUSE

0.1U_0402_10V7-K

1

2

+1.05VS_PCH_VPROC

CH77

CH76

1U_0402_6.3V6-K

0.1U_0402_10V7-K

1

2

CH85

1U_0402_6.3V6-K

1

20130125 --> Need connect to +1.05VS

2

Title

PCH_POWER-2

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

RH190

1 2

0_0805_5%

1 2

RH191 0_0805_5%@RH191 0_0805_5%@

1 2

RH193 0_0805_5%RH193 0_0805_5%

E440 NM-A151

E440 NM-A151E440 NM-A151

+1.05VS

+3VS

+1.05VS

1.0

21 57

1

21 57

1.0

of

+1.05VM_PCH_DCPSUS2 +PCH_VCCCLK +V_VPROC

5

D D

C C

B B

4

LPT_PCH_M_EDS

UH1J

AL34

VSS[1]

AL38

AM14 AM24 AM26 AM28 AM30 AM32 AM16 AN36 AN40 AN42

AN8 AP13 AP24 AP31 AP43

AR2 AK16 AT10 AT15 AT17 AT20 AT26 AT29 AT36 AT38

AV13 AV22 AV24 AV31 AV33 BB25 AV40

AV6

AW2

AY10 AY15 AY20 AY26 AY29

AY7

AL8

D42

F43

B11 B15

REV = 5

VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47]

LYNX-POINT-DH82LPMS_BGA695

SA00005U830

VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79] VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS[91] VSS[92]

K39 L2 L44 M17 M22 N12 N35 N39 N6 P22 P24 P26 P28 P30 P32 R12 R14 R16 R2 R34 R38 R44 R8 T43 U10 U16 U28 U34 U38 U42 U6 V14 V16 V26 V43 W2 W44 Y14 Y16 Y24 Y28 Y34 Y36 Y40 Y8

10 OF 11

3

LPT_PCH_M_EDS

UH1K

AA16 AA20 AA22 AA28

AA4 AB12 AB34 AB38

AB8

AC2 AC44 AD14 AD16 AD18 AD30 AD32 AD40

AD6

AD8 AE16 AE28 AF38

AF8

AG16

AG2

AG26 AG28 AG44

AJ16 AJ18 AJ20 AJ22 AJ24 AJ34 AJ38

AJ6

AJ8 AK14 AK24 AK43 AK45

AL12

AL2 BC22 BB42

LYNX-POINT-DH82LPMS_BGA695

SA00005U830

VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98] VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129 VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137]

REV = 5

VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182]

11 OF 11

B19 B23 B27 B31 B35 B39 B7 BA40 BD11 BD15 BD19 AY36 AT43 BD31 BD35 BD39 BD7 D25 AV7 F15 F20 F29 F33 BC16 D4 G2 G38 G44 G8 H10 H13 H17 H22 H24 H26 H31 H36 H40 H7 K10 K15 K20 K29 K33 BC28

2

1

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/12/05

LC Future Center Secret Data

Deciphered Date

2

2014/12/05

Title

PCH_GND

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

E440 NM-A151

E440 NM-A151E440 NM-A151

1

22 57

of

1.0

5

4

3

2

1

VGA_THERMTRIP#

UV1A

PCIE_CTX_C_GRX_P0 PCIE_CTX_C_GRX_N0 PCIE_CTX_C_GRX_P1 PCIE_CTX_C_GRX_N1 PCIE_CTX_C_GRX_P2 PCIE_CTX_C_GRX_N2 PCIE_CTX_C_GRX_P3 PCIE_CTX_C_GRX_N3 PCIE_CTX_C_GRX_P4 PCIE_CTX_C_GRX_N4 PCIE_CTX_C_GRX_P5 PCIE_CTX_C_GRX_N5 PCIE_CTX_C_GRX_P6 PCIE_CTX_C_GRX_N6 PCIE_CTX_C_GRX_P7 PCIE_CTX_C_GRX_N7

PCIE_CRX_C_GTX_P0 PCIE_CRX_C_GTX_N0 PCIE_CRX_C_GTX_P1 PCIE_CRX_C_GTX_N1 PCIE_CRX_C_GTX_P2 PCIE_CRX_C_GTX_N2 PCIE_CRX_C_GTX_P3 PCIE_CRX_C_GTX_N3 PCIE_CRX_C_GTX_P4

PCIE_CRX_C_GTX_P5 PCIE_CRX_C_GTX_N5 PCIE_CRX_C_GTX_P6 PCIE_CRX_C_GTX_N6 PCIE_CRX_C_GTX_P7PCIE_CRX_GTX_P7 PCIE_CRX_C_GTX_N7

CLK_PCIE_VGA CLK_PCIE_VGA# CLK_REQ_GPU#

PEX_TSTCLK_OUT PEX_TSTCLK_OUT#

PLTRST_VGA# PEX_TERMP

RV28

DIS@ RV28

DIS@

2.49K_0402_1%

1 2

CV1 0.22U_0402_10V6KDIS@CV1 0.22U_0402_10V6KDIS@ CV2 0.22U_0402_10V6KDIS@CV2 0.22U_0402_10V6KDIS@ CV3 0.22U_0402_10V6KDIS@CV3 0.22U_0402_10V6KDIS@ CV4 0.22U_0402_10V6KDIS@CV4 0.22U_0402_10V6KDIS@ CV5 0.22U_0402_10V6KDIS@CV5 0.22U_0402_10V6KDIS@ CV6 0.22U_0402_10V6KDIS@CV6 0.22U_0402_10V6KDIS@ CV7 0.22U_0402_10V6KDIS@CV7 0.22U_0402_10V6KDIS@ CV8 0.22U_0402_10V6KDIS@CV8 0.22U_0402_10V6KDIS@ CV9 0.22U_0402_10V6KDIS@CV9 0.22U_0402_10V6KDIS@ CV10 0.22U_0402_10V6KDIS@CV10 0.22U_0402_10V6KDIS@ CV11 0.22U_0402_10V6KDIS@CV11 0.22U_0402_10V6KDIS@ CV12 0.22U_0402_10V6KDIS@CV12 0.22U_0402_10V6KDIS@ CV13 0.22U_0402_10V6KDIS@CV13 0.22U_0402_10V6KDIS@ CV14 0.22U_0402_10V6KDIS@CV14 0.22U_0402_10V6KDIS@ CV15 0.22U_0402_10V6KDIS@CV15 0.22U_0402_10V6KDIS@ CV16 0.22U_0402_10V6KDIS@CV16 0.22U_0402_10V6KDIS@

Differential signal

PCIE_CTX_C_GRX_N[0..7]

PCIE_CTX_C_GRX_P[0..7]

PCIE_CRX_GTX_N[0..7]

PCIE_CRX_GTX_P[0..7]

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

CLK_PCIE_VGA<16> CLK_PCIE_VGA#<16>

1 2

RV25 200_0402_1%@RV25 200_0402_1%@

12

RV97

DIS@ RV97

DIS@

10K_0402_5%

PCIE_CTX_C_GRX_N[0..7]<5>

PCIE_CTX_C_GRX_P[0..7]<5>

PCIE_CRX_GTX_N[0..7]<5>

PCIE_CRX_GTX_P[0..7]<5>

D D

PCIE_CRX_GTX_P0 PCIE_CRX_GTX_N0 PCIE_CRX_GTX_P1 PCIE_CRX_GTX_N1 PCIE_CRX_GTX_P2

C C

PCIE_CRX_GTX_N2 PCIE_CRX_GTX_P3 PCIE_CRX_GTX_N3 PCIE_CRX_GTX_P4 PCIE_CRX_GTX_N4 PCIE_CRX_C_GTX_N4 PCIE_CRX_GTX_P5 PCIE_CRX_GTX_N5 PCIE_CRX_GTX_P6 PCIE_CRX_GTX_N6

PCIE_CRX_GTX_N7

B B

PLTRST_VGA#<14>

AG6

PEX_RX0

AG7

PEX_RX0_N

AF7

PEX_RX1

AE7

PEX_RX1_N

AE9

PEX_RX2

AF9

PEX_RX2_N

AG9

PEX_RX3

AG10

PEX_RX3_N

AF10

PEX_RX4

AE10

PEX_RX4_N

AE12

PEX_RX5

AF12

PEX_RX5_N

AG12

PEX_RX6

AG13

PEX_RX6_N

AF13

PEX_RX7

AE13

PEX_RX7_N

AE15

NC1

AF15

NC2

AG15

NC3

AG16

NC4

AF16

NC5

AE16

NC6

AE18

NC7

AF18

NC8

AG18

NC9

AG19

NC10

AF19

NC11

AE19

NC12

AE21

NC13

AF21

NC14

AG21

NC15

AG22

NC16

AC9

PEX_TX0

AB9

PEX_TX0_N

AB10

PEX_TX1

AC10

PEX_TX1_N

AD11

PEX_TX2

AC11

PEX_TX2_N

AC12

PEX_TX3

AB12

PEX_TX3_N

AB13

PEX_TX4

AC13

PEX_TX4_N

AD14

PEX_TX5

AC14

PEX_TX5_N

AC15

PEX_TX6

AB15

PEX_TX6_N

AB16

PEX_TX7

AC16

PEX_TX7_N

AD17

NC17

AC17

NC18

AC18

NC19

AB18

NC20

AB19

NC21

AC19

NC22

AD20

NC23

AC20

NC24

AC21

NC25

AB21

NC26

AD23

NC27

AE23

NC28

AF24

NC29

AE24

NC30

AG24

NC31

AG25

NC32

AE8

PEX_REFCLK

AD8

PEX_REFCLK_N

AC6

PEX_CLKREQ_N

AF22

PEX_TSTCLK_OUT

AE22

PEX_TSTCLK_OUT_N

AC7

PEX_RST_N

AF25

PEX_TERMP

N14M-LP-S-A2_FCBGA595

N14PGV2@

N14PGV2@ SA00005NC10

SA00005NC10

For GPU CLKREQU#

RV33

DGPU_PWR_EN

A A

To PCH

1 2

@

CV21

0.1U_0402_16V4Z

10K_0402_5%

CLK_REQ_GPU#_R<16>

0.1U_0402_16V4Z

1

@

2

CV22

0.1U_0402_16V4Z

1

@

5

RV37 0_0402_5%@RV37 0_0402_5%@

2

1 3

D

1 2

0_0402_5%

G

QV7

QV7 2N7002KW_SOT323-3

2N7002KW_SOT323-3

S

RV96

DIS@

+3VS_VGA

12

DIS@ RV34

DIS@

12

@ RV36

@

RV34 10K_0402_5%

10K_0402_5%

CLK_REQ_GPU#

RV36 10K_0402_5%

10K_0402_5%

Part 1 of 6

DACsI2C GPIO

PCI EXPRESS

52mA

71mA

41mA

CLK

Load BOMUV1

N14M-GL-S-A2_FCBGA595

N14MGL@

N14MGL@ SA00005N900

SA00005N900

4

GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8

GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21

DACA_RED

DACA_GREEN

DACA_BLUE

DACA_HSYNC DACA_VSYNC

DACA_VDD DACA_VREF DACA_RSET

I2CA_SCL

I2CA_SDA

I2CB_SCL

I2CB_SDA

I2CC_SCL

I2CC_SDA

I2CS_SCL

I2CS_SDA

CORE_PLLVDD

SP_PLLVDD

VID_PLLVDD

XTAL_IN

XTAL_OUT

XTAL_SSIN

XTAL_OUTBUFF

UV1

C6

FB_CLAMP_MON

B2 D6 C7 F9 A3 A4

FB_CLAMP_TGL_REQ#

B6 A6

OVERT#

F8

THERM#_VGA

C5 E7

NVVDD_PWM_VID

D7 B4

DPRSLPVR_VGA

B3 C3 D5 D4 C2 F7 E6 C4

AB6

NC33

AG3 AF4 AF3

AE3 AE4

W5 AE2 AF2

B7

I2CA_SCL

A7

I2CA_SDA

C9

I2CB_SCL

C8

I2CB_SDA

A9

I2CC_SCL

B9

I2CC_SDA

D9

I2CS_SCL

D8

I2CS_SDA

L6 M6

N6

C11

XTALIN

B10

XTAL_OUT

A10

XTALSSIN

C10

XTALOUT

Internal Thermal Sensor

DPRSLPVR_VGA

OVERT#

THERM#_VGA

VGA_AC_DET_R

NVVDD_PWM_VID <63>

DPRSLPVR_VGA <63>

For GC6 (FB_CLAMP_TGL_REQ#, GC6_EVEVT#), just for N14P

+3VS_VGA

N14PGV2@ RV12

N14PGV2@

FB_CLAMP_TGL_REQ#

GPIO 6 of GPU connect to EC GPIO

1 2

RV13 10K_0402_5%@RV13 10K_0402_5%@

1 2

RV14 2.2K_0402_5%DIS@RV14 2.2K_0402_5%DIS@

1 2

RV15 2.2K_0402_5%DIS@RV15 2.2K_0402_5%DIS@

1 2

RV16 2.2K_0402_5%DIS@RV16 2.2K_0402_5%DIS@

1 2

RV17 2.2K_0402_5%DIS@RV17 2.2K_0402_5%DIS@

1 2

RV18 2.2K_0402_5%DIS@RV18 2.2K_0402_5%DIS@

1 2

RV19 2.2K_0402_5%DIS@RV19 2.2K_0402_5%DIS@

1 2

RV21 2.2K_0402_5%DIS@RV21 2.2K_0402_5%DIS@

1 2

RV22 2.2K_0402_5%DIS@RV22 2.2K_0402_5%DIS@

1 2

0_0402_5%

RV12

100K_0402_5%

1 2

RV93

+3VS_VGA

RV3 10K_0402_5%DIS@RV3 10K_0402_5%DIS@

RV6 100K_0402_5%DIS@RV6 100K_0402_5%DIS@

RV8 100K_0402_5%DIS@RV8 100K_0402_5%DIS@

RV9 100K_0402_5%DIS@RV9 100K_0402_5%DIS@

@

1 2

DIS@

DV1 RB751V-40_SOD323-2

SCS00006S00

RV94

1 2

@

0_0402_5%

1

2

G

2

13

D

S

D

S

QV3

QV3 2N7002KW_SOT323-3

2N7002KW_SOT323-3

CV19

1

DIS@

2

Under GPU Near GPU

+PLLVDD

+SP_PLLVDD

RV23

1 2

+PLLVDD +SP_PLLVDD

@

0_0402_5%

1 2

RV26 10K_0402_5%DIS@RV26 10K_0402_5%DIS@

1 2

RV29 10K_0402_5%DIS@RV29 10K_0402_5%DIS@

I2CS_SCL

RV20 0_0402_5%@RV20 0_0402_5%@

5

I2CS_SDA

1 2

RV24 0_0402_5%@RV24 0_0402_5%@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

CV23

1

DIS@

2

+3VS_VGA

2

61

1 2

QV4B

DIS@QV4B

DIS@

2N7002KDWH_SOT363-6

34

2012/12/05

CV24

22U_0805_6.3V6M

1

DIS@

2

QV4A

DIS@QV4A

DIS@

2N7002KDWH_SOT363-6

PU +3VS AT EC SIDE, +3VS AND 4.7K

LC Future Center Secret Data

+3VS_VGA

12

VGA_AC_DETVGA_AC_DET_R

DGPU_PWR_EN

N14PGV2@

1 2

RV95 10K_0402_5%

CV116

N14PGV2@CV116

N14PGV2@

0.1U_0402_10V7K

N14PGV2@

CV20

22U_0805_6.3V6M

0.1U_0402_10V7K

4.7U_0402_6.3V6M

DIS@

22U_0805_6.3V6M

1

DIS@

2

CV25

CV26

0.1U_0402_10V7K

1

DIS@

2

EC_SMB_CK3 <17,32,48>

EC_SMB_DA3 <17,32,48>

Deciphered Date

VGA_AC_DET <48>

DGPU_PWR_EN <14,54>

PLTRST_VGA#

To EC

GC6_EVENT# <19,48>

LV1

DIS@LV1

DIS@

1 2

BLM18PG181SN1D_2P

30 ohms @100MHz (ESR=0.05)

LV2

DIS@LV2

0.1U_0402_10V7K

150mA

DIS@

1 2

BLM18PG330SN1_2P

180ohms (ESR=0.2) Bead

Under GPU(below 150mils)

For GC6 (FB_CLAMP_MON, FB_CLAMP)

DGPU_PWR_EN

NV recommend add RV2 1KOhm to avoid giltich issue

2014/12/05

2

27MHz X'TAL

+3VS

12

RV31

N14PGV2@ RV31

N14PGV2@

10K_0402_5%

13

D

2

G

QV6

S

2N7002KW_SOT323-3

OVERT#

PLTRST_VGA#

XTALIN

2

CV17 10P_0402_50V8-J

10P_0402_50V8-J

1

+1.05VS_VGA

N14PGV2@

RV2

1 2

1K_0402_5%

N14PGV2@

Title

Size Document Number Rev

Custom

Date: Sheet

+3VS_VGA

12

RV10

DIS@ RV10

DIS@

10K_0402_5%

34

QV1B

DIS@QV1B

5

2

G

1

CV117

@ CV117

@

0.1U_0402_10V7K

2

RV30 10M_0402_5%DIS@RV30 10M_0402_5%DIS@

DIS@CV17

DIS@

To PCH

N14PGV2@

N14P_PCIe/GPIO/I2C

Thursday, July 11, 2013

DIS@

2N7002KDWH_SOT363-6

13

D

QV2

DIS@

QV2

DIS@

2N7002KW_SOT323-3

S

1 2

YV1

DIS@

Crystal

4

OUT

GND

1

IN

GND

27MHZ_10PF_7V27000050

SJ10000G700

FB_CLAMP_MON

N14PGV2@ RV27

N14PGV2@

2

CV115

0.1U_0402_10V7K

1

2

VGA_THERMTRIP# <19>

61

QV1A

2

2N7002KDWH_SOT363-6

1

CV118

@ CV118

@

0.1U_0402_10V7K

2

3

XTAL_OUT

2

RV27 0_0402_5%

0_0402_5%

1 2

N14PGV2@

1 2

RV32 10K_0402_5%

QV5

N14PGV2@

QV5

N14PGV2@

AP2301GN-HF_SOT23-3

SB00000YL00

3 1

FB_CLAMP <2 7,48>

12

RV35

DIS@ RV35

DIS@

10K_0402_5%

E440 NM-A151

E440 NM-A151E440 NM-A151

1

23 57

DIS@QV1A

DIS@

2

CV18

DIS@CV18

DIS@

10P_0402_50V8-J

1

From EC

of

1.0

5

D D

C C

B B

4

AC3 AC4

AA3 AA2 AB1 AA1 AA4 AA5

AB5 AB4 AB3 AB2 AD3 AD2 AE1 AD1 AD4 AD5

R1 R2 R3 N2 N3

U3 U4

R4 R5

N1 M1 M2 M3

M4 M5

N4 N5

H3 H4

UV1C

IFPA_TXC IFPA_TXC_N

Y4

IFPA_TXD0

Y3

IFPA_TXD0_N IFPA_TXD1 IFPA_TXD1_N IFPA_TXD2 IFPA_TXD2_N IFPA_TXD3 IFPA_TXD3_N

IFPB_TXC IFPB_TXC_N IFPB_TXD4 IFPB_TXD4_N IFPB_TXD5 IFPB_TXD5_N IFPB_TXD6 IFPB_TXD6_N IFPB_TXD7 IFPB_TXD7_N

T2

IFPC_L0

T3

IFPC_L0_N

T1

IFPC_L1 IFPC_L1_N IFPC_L2 IFPC_L2_N IFPC_L3 IFPC_L3_N

V3

IFPD_L0

V4

IFPD_L0_N IFPD_L1 IFPD_L1_N

T4

IFPD_L2

T5

IFPD_L2_N IFPD_L3 IFPD_L3_N

NC34 NC35 NC36 NC37

K2

NC38

K3

NC39

K1

NC40

J1

NC41

NC42 NC43

L3

NC44

L4

NC45

K4

NC46

K5

NC47

J4

NC48

J5

NC49 IFPC_AUX_I2CW_SCL IFPC_AUX_I2CW_SDA_N

P3

IFPD_AUX_I2CX_SCL

P4

IFPD_AUX_I2CX_SDA_N

J2

IFPE_AUX_I2CY_SCL

J3

IFPE_AUX_I2CY_SDA_N

IFPF_AUX_I2CZ_SCL IFPF_AUX_I2CZ_SDA_N

N14M-LP-S-A2_FCBGA595

N14PGV2@

N14PGV2@ SA00005NC10

SA00005NC10

Part 3 of 6

NC

BUFRST_N

STRAP0 STRAP1

GENERAL

STRAP2 STRAP3 STRAP4

MULTI_STRAP_REF0_GND

LVDS/TMDS

THERMDP

THERMDN

VDD_SENSE

GND_SENSE

TEST

TESTMODE

JTAG_TCK

JTAG_TDI JTAG_TDO JTAG_TMS

JTAG_TRST_N

SERIAL

ROM_CS_N

ROM_SO

ROM_SCLK

NC50 NC51 NC52 NC53 NC54 NC55 NC56 NC57 NC58 NC59 NC60 NC61 NC62 NC63 NC64 NC65 NC66 NC67 NC68

NC69

NC70

NC71

NC72

NC73

NC74 NC75

ROM_SI

3

F11 AD10 AD7 B19 V5 V6 G1 G2 G3 G4 G5 G6 G7 V1 V2 W1 W2 W3 W4

D11

D10

E9

E10

F10

D1 D2 E4 E3 D3 C1

F6 F4 F5

F12

E12

F2

F1

AD9 AE5 AE6 AF6 AD6 AG4

D12 B12 A12 C12

1 2

RV38 10K_0402_5%DIS@RV38 10K_0402_5%DIS@

STRAP0 STRAP1 STRAP2 STRAP3 STRAP4

N14PGV2@

1 2

RV39 40.2K_0402_1%

VCCSENSE_VGA

VSSSENSE_VGA

TESTMODE

RV40 10K_0402_5%DIS@RV40 10K_0402_5%DIS@

1

TV1TV1

1

TV2TV2

1

TV3TV3

1

TV4TV4

RV41 10K_0402_5%DIS@RV41 10K_0402_5%DIS@

ROM_CS#

RV42 10K_0402_5%DIS@RV42 10K_0402_5%DIS@

ROM_SI ROM_SO ROM_SCLK

STRAP0 <30> STRAP1 <30> STRAP2 <30> STRAP3 <30> STRAP4 <30>

VCCSENSE_VGA <63>

trace width: 16mils differential voltage sensing. differential signal routing.

VSSSENSE_VGA <63>

1 2

ROM_SI <30> ROM_SO <30> ROM_SCLK <30 >

+3VS_VGA

2

1

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/12/05

LC Future Center Secret Data

Deciphered Date

2

2014/12/05

Title

N14P_SPI ROM/SENSE

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

E440 NM-A151

E440 NM-A151E440 NM-A151

1

24 57

of

1.0

5

+1.5VS_VGA

D D

CV32

CV36

DIS@

CV28

CV37

CV29

CV27

0.1U_0402_10V7K

DIS@

1

2

1

2

CV29

0.1U_0402_10V7K

DIS@

1

2

CV31

CV30

0.1U_0402_10V7K

DIS@

1

2

CV32

CV38

0.1U_0402_10V7K

DIS@

1

2

CV39

1U_0603_10V6K

0.1U_0402_10V7K

1U_0603_10V6K

DIS@

1

2

Under GPU(below 150mils)

rise 1.5v system source voltage to 1.55-1.57V

Cost Down Plan

C C

B B

CV33

4.7U_0603_6.3V6K

DIS@

1

2

RV44 10K_0402_5%@RV44 10K_0402_5%@

RV45 10K_0402_5%@RV45 10K_0402_5%@

RV48 10K_0402_5%@RV48 10K_0402_5%@

RV50 10K_0402_5%@RV50 10K_0402_5%@

RV51 10K_0402_5%@RV51 10K_0402_5%@

RV52 10K_0402_5%@RV52 10K_0402_5%@

CV40

DIS@

4

1

2

CV41

4.7U_0603_6.3V6K

Near GPU

3

UV1D

CV34

10U_0805_6.3V6M

DIS@

1

2

12

10U_0805_6.3V6M

DIS@

1

2

22U_0805_6.3V6M

DIS@

1

2

+IFPAB_PLLVDD

+IFPAB_IOVDD

+IFPC_PLLVDD

+IFPC_IOVDD

+IFPD_PLLVDD

+IFPD_IOVDD

3.5A

CV42

CV35

CV34

UV1D

B26

FBVDDQ_01

C25

FBVDDQ_02

E23

FBVDDQ_03

E26

FBVDDQ_04

F14

FBVDDQ_05

F21

FBVDDQ_06

G13

FBVDDQ_07

G14

FBVDDQ_08

G15

FBVDDQ_09

G16

FBVDDQ_10

G18

FBVDDQ_11

G19

FBVDDQ_12

G20

FBVDDQ_13

G21

FBVDDQ_14

H24

FBVDDQ_15

H26

FBVDDQ_16

J21

FBVDDQ_17

K21

FBVDDQ_18

L22

FBVDDQ_19

L24

FBVDDQ_20

L26

FBVDDQ_21

M21

FBVDDQ_22

N21

FBVDDQ_23

R21

FBVDDQ_24

T21

FBVDDQ_25

V21

FBVDDQ_26

W21

FBVDDQ_27

V7

IFPAB_PLLVDD_1

W7

IFPAB_PLLVDD_2

AA6

IFPAB_RSET

W6

IFPA_IOVDD

Y6

IFPB_IOVDD

M7

IFPC_PLLVDD_1

N7

IFPC_PLLVDD_2

T6

IFPC_RSET

P6

IFPC_IOVDD

T7

IFPD_PLLVDD_2

R7

IFPD_PLLVDD_1

U6

IFPD_RSET

R6

IFPD_IOVDD

J7

NC76

K7

NC77

K6

NC78

H6

NC79

J6

NC80

N14M-LP-S-A2_FCBGA595

N14PGV2@

N14PGV2@ SA00005NC10

SA00005NC10

Part 4 of 6

FB_CAL_TERM_GND

PEX_IOVDDQ_1 PEX_IOVDDQ_2 PEX_IOVDDQ_3 PEX_IOVDDQ_4 PEX_IOVDDQ_5 PEX_IOVDDQ_6 PEX_IOVDDQ_7 PEX_IOVDDQ_8

PEX_IOVDDQ_9 PEX_IOVDDQ_10 PEX_IOVDDQ_11 PEX_IOVDDQ_12 PEX_IOVDDQ_13 PEX_IOVDDQ_14

PEX_IOVDD_1 PEX_IOVDD_2 PEX_IOVDD_3 PEX_IOVDD_4 PEX_IOVDD_5 PEX_IOVDD_6

VDD33_1 VDD33_2 VDD33_3 VDD33_4

FB_CAL_PD_VDDQ

FB_CAL_PU_GND

PEX_PLL_HVDD_1 PEX_PLL_HVDD_2

PEX_SVDD_3V3

PEX_PLLVDD_1

PEX_PLLVDD_2

2000mA

AA10 AA12 AA13 AA16 AA18 AA19 AA20 AA21 AB22 AC23 AD24 AE25 AF26 AF27

AA22 AB23 AC24 AD25 AE26 AE27

G10 G12 G8 G9

D22

RV46 40.2_0402_1%DIS@RV46 40.2_0402_1%DIS@

C24

RV47 42.2_0402_1%DIS@RV47 42.2_0402_1%DIS@

B25

RV49 51.1_0402_1%DIS@RV49 51.1_0402_1%DIS@

Place near balls

AA8 AA9

AB8

120mA

AA14 AA15

CV43

CV44

1U_0402_6.3V6K

DIS@

1

2

Under GPU(below 150mils)

+VDD33

1 2

+PEX_PLLHVDD

+PEX_PLLVDD

CV66

0.1U_0402_10V7K

1

DIS@CV66

DIS@

2

CV46

CV45

DIS@

CV46

1U_0402_6.3V6K

DIS@

1

2

CV47

1U_0402_6.3V6K

DIS@

1

2

1

2

Near GPU

CV57

DIS@

+1.5VS_VGA

1

2

Under GPU Near GPU

1 2

RV53 0_0402_5%RV53 0_0402_5%

CV67

1U_0603_10V6K

CV68

4.7U_0805_10V4Z

1

DIS@CV67

DIS@

DIS@CV68

DIS@

2

CV49

CV50

10U_0603_6.3V6M

4.7U_0603_6.3V6K

DIS@

1

2

CV59

0.1U_0402_10V7K

DIS@

1

2

N14MGL@

1 2

CV50

DIS@

CV60

DIS@

CV51

CV52

10U_0603_6.3V6M

DIS@

1

2

1

2

DIS@

1

2

CV61

1U_0402_6.3V6K

0.1U_0402_10V7K

DIS@

1

2

CV48

4.7U_0603_6.3V6K

DIS@

1

2

CV58

0.1U_0402_10V7K

DIS@

1

2

LV3 BLM18PG121SN1D_0603

120ohms @100MHz (ESR=0.18)

N14PGV2@

1 2

RV54 0_0603_5%

CV53

CV54

22U_0805_6.3V6M

10U_0603_6.3V6M

DIS@

1

2

RV43 0_0603_5%RV43 0_0603_5%

CV62

4.7U_0603_6.3V6K

DIS@

1

2

+1.05VS_VGA

1

+1.05VS_VGA

CV56

CV55

22U_0805_6.3V6M

1

2

CV63

DIS@CV63

DIS@

22U_0805_6.3V6M

DIS@

1

2

1 2

CV64

0.1U_0402_10V7K

1

DIS@CV64

DIS@

2

DIS@

1

2

1

2

22U_0805_6.3V6M

+3VS_VGA

CV65

4.7U_0603_6.3V6K

DIS@CV65

DIS@

+3VS_VGA

4.7U_0603_6.3V6K

1

2

Near GPU(below 150mils)

Under GPU

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/12/05

LC Future Center Secret Data

Near GPU

Deciphered Date

2

2014/12/05

CALIBRATION PIN

FB_CAL_x_PD_VDDQ

FB_CAL_x_PU_GND

FB_CAL_xTERM_GND

Title

N14P_POWER

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

E440 NM-A151

E440 NM-A151E440 NM-A151

1

DDR3

40.2Ohm

42.2Ohm

51.1Ohm

25 57

of

1.0

5

UV1E

A2

A26 AB11 AB14 AB17 AB20

D D

C C

AB24

AC2 AC22 AC26

AC5

AC8 AD12 AD13 AD15 AD16 AD18 AD19 AD21 AD22 AE11 AE14 AE17 AE20

AF11 AF14 AF17 AF20 AF23

AG2 AG26

AF1

AF5 AF8

B1 B11 B14 B17 B20 B23 B27

B5

B8 E11 E14 E17

E2 E20 E22 E25

E5

E8

H2 H23 H25

H5

GND_001 GND_002 GND_003 GND_004 GND_005 GND_006 GND_007 GND_008 GND_009 GND_010 GND_011 GND_012 GND_013 GND_014 GND_015 GND_016 GND_017 GND_018 GND_019 GND_020 GND_021 GND_022 GND_023 GND_024 GND_025 GND_026 GND_027 GND_028 GND_029 GND_030 GND_031 GND_032 GND_033 GND_034 GND_035 GND_036 GND_037 GND_038 GND_039 GND_040 GND_041 GND_042 GND_043 GND_044 GND_045 GND_046 GND_047 GND_048 GND_049 GND_050 GND_051 GND_052 GND_053 GND_054 GND_055 GND_056

Part 5 of 6

GND_057 GND_058 GND_059 GND_060 GND_061 GND_062 GND_063 GND_064 GND_065 GND_066 GND_067 GND_068 GND_069 GND_070 GND_071 GND_072 GND_073 GND_074 GND_075 GND_076 GND_077 GND_078 GND_079 GND_080 GND_081 GND_082 GND_083 GND_084 GND_085 GND_086 GND_087 GND_088 GND_089 GND_090 GND_091 GND_092 GND_093 GND_094 GND_095 GND_096 GND_097 GND_098 GND_099 GND_100 GND_101 GND_102 GND_103 GND_104 GND_105 GND_106 GND_107 GND_108 GND_109 GND_110 GND_111 GND_112

K11 K13 K15 K17 L10 L12 L14 L16 L18 L2 L23 L25 L5 M11 M13 M15 M17 N10 N12 N14 N16 N18 P11 P13 P15 P17 P2 P23 P26 P5 R10 R12 R14 R16 R18 T11 T13 T15 T17 U10 U12 U14 U16 U18 U2 U23 U26 U5 V11 V13 V15 V17 Y2 Y23 Y26 Y5

4

3

+VGA_CORE +VGA_CORE

UV1F

K10

VDD_001

K12

VDD_002

K14

VDD_003

K16

VDD_004

K18

VDD_005

L11

VDD_006

L13

VDD_007

L15

VDD_008

L17

VDD_009

M10

VDD_010

M12

VDD_011

M14

VDD_012

M16

VDD_013

M18

VDD_014

N11

VDD_015

N13

VDD_016

N15

VDD_017

N17

VDD_018

P10

VDD_019

P12

VDD_020

N14M-LP-S-A2_FCBGA595

N14PGV2@

N14PGV2@ SA00005NC10

SA00005NC10

Part 6 of 6

VDD_041 VDD_040 VDD_039 VDD_038 VDD_037 VDD_036 VDD_035 VDD_034 VDD_033 VDD_032 VDD_031 VDD_030 VDD_029 VDD_028 VDD_027 VDD_026 VDD_025 VDD_024 VDD_023 VDD_022 VDD_021

2

V18 V16 V14 V12 V10 U17 U15 U13 U11 T18 T16 T14 T12 T10 R17 R15 R13 R11 P18 P16 P14

1

CV69

DIS@CV69

DIS@

47U_0805_4V6

2

Place near balls

1

AA7

GND_113

AB7

GND_114

N14M-LP-S-A2_FCBGA595

N14PGV2@

N14PGV2@ SA00005NC10

SA00005NC10

B B

VDD33 (+3VS_VGA)

IFPx_IOVDD

NVVDD (+VGA_CORE)

tIFPx_IOVDD

tNVVDD

tFBVDDQ

FBVDDQ (+1.5VS_VGA)

tPEX_VDD

PEX_VDD (+1.05VS_VGA)

tIFPy_IOVDD

IFPy_IOVDD

NV Recommended Power On Sequencing Order

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

X=A and B Y=C,D,E and F

2012/12/05

LC Future Center Secret Data

Deciphered Date

2

2014/12/05

Title

N14P_VDD/GND

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

E440 NM-A151

E440 NM-A151E440 NM-A151

1

26 57

of

1.0

5

FBA_D[0..63]<28,29>

FBA_DQM[7..0]<28,29>

FBA_DQS[7..0]<28,29>

D D

C C

FBA_DQS#[7..0]<28,29>

+1.05VS_VGA +FB_PLLAVDD

LV4 MPZ1608S300AT_2P~D

FBA_D[0..63]

FBA_DQM[7..0]

FBA_DQS[7..0]

FBA_DQS#[7..0]

FBA_MA[15..0]

FBA_BA[2..0]

1. 30ohms (ESR=0.01) Bead

2. Place close to BGA

DIS@

1 2

SM01003110J

+FB_PLLAVDD

FBA_MA[15..0] <28,29>

FBA_BA[2..0] <28,29>

CV70

0.1U_0402_10V7K

1

DIS@CV70

DIS@

2

600mA

+FB_PLLAVDD

CV71

1U_0402_6.3V6K

1

DIS@CV71

DIS@

2

Near GPUUnder GPU

Under GPU

+FB_PLLAVDD

B B

+1.5VS_VGA

For GC6

FB_CLAMP<23,48>

+1.5VS_VGA

CV72

DIS@CV72

DIS@

22U_0805_6.3V6M

1

2

4

1 2

RV55 60.4_0402_1%@RV55 60. 4_0402_1%@

1 2

RV56 60.4_0402_1%@RV56 60. 4_0402_1%@

12

FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8 FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63

CV730.1U_0402_10V7K DIS@ CV730.1U_0402_10V7K DIS@

FB_CLAMP

AA24

AA23 AD27 AB25 AD26 AC25 AA27 AA26

W26

W27 W25

E18

F18

E16

F17 D20 D21

F20 E21 E15 D15

F15

F13 C13 B13 E13 D13 B15 C16 A13 A15 B18 A18 A19 C19 B24 C23 A25 A24 A21 B21 C20 C21 R22 R24

T22 R23 N25 N26 N23 N24 V23 V22

T23 U22 Y24

Y22

Y25 R26

T25 N27 R27 V26 V27

F16 P22

D23

H22

F3

F22

J22

UV1B

FBA_D00 FBA_D01 FBA_D02 FBA_D03 FBA_D04 FBA_D05 FBA_D06 FBA_D07 FBA_D08 FBA_D09 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63

FB_PLLAVDD_1 FB_PLLAVDD_2

FB_VREF_PROBE

FB_DLLAVDD

FB_CLAMP

FBA_DEBUG0 FBA_DEBUG1

Part 2 of 6

MEMORY

FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8

FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30 FBA_CMD31

FBA_DQM0

FBA_DQM1

FBA_DQM2

FBA_DQM3

FBA_DQM4

FBA_DQM5

FBA_DQM6

FBA_DQM7

FBA_DQS_RN0 FBA_DQS_RN1

INTERFACE A

FBA_DQS_RN2 FBA_DQS_RN3 FBA_DQS_RN4 FBA_DQS_RN5 FBA_DQS_RN6 FBA_DQS_RN7

FBA_DQS_WP0 FBA_DQS_WP1 FBA_DQS_WP2 FBA_DQS_WP3 FBA_DQS_WP4 FBA_DQS_WP5 FBA_DQS_WP6 FBA_DQS_WP7

FBA_CLK0_N

FBA_CLK1_N

FBA_WCK01

FBA_WCK01_N

FBA_WCK23

FBA_WCK23_N

FBA_WCK45

FBA_WCK45_N

FBA_WCK67

FBA_WCK67_N

3

FBA_CLK0

FBA_CLK1

C27 C26 E24 F24 D27 D26 F25 F26 F23 G22 G23 G24 F27 G25 G27 G26 M24 M23 K24 K23 M27 M26 M25 K26 K22 J23 J25 J24 K27 K25 J27 J26

D19 D14 C17 C22 P24 W24 AA25 U25

F19 C14 A16 A22 P25 W22 AB27 T27

E19 C15 B16 B22 R25 W23 AB26 T26

D24 D25

N22 M22

D18 C18 D17 D16 T24 U24 V24 V25

FBA_CS0#_L

FBA_ODT_L FBA_CKE_L FBA_MA14 FBA_RST# FBA_MA9 FBA_MA7 FBA_MA2 FBA_MA0 FBA_MA4 FBA_MA1 FBA_BA0 FBA_WE# FBA_MA15 FBA_CAS# FBA_CS0#_H

FBA_ODT_H FBA_CKE_H FBA_MA13 FBA_MA8 FBA_MA6 FBA_MA11 FBA_MA5 FBA_MA3 FBA_BA2 FBA_BA1 FBA_MA12 FBA_MA10 FBA_RAS#

FBA_DQM0 FBA_DQM1 FBA_DQM2 FBA_DQM3 FBA_DQM4 FBA_DQM5 FBA_DQM6 FBA_DQM7

FBA_DQS#0 FBA_DQS#1 FBA_DQS#2 FBA_DQS#3 FBA_DQS#4 FBA_DQS#5 FBA_DQS#6 FBA_DQS#7

FBA_DQS0 FBA_DQS1 FBA_DQS2 FBA_DQS3 FBA_DQS4 FBA_DQS5 FBA_DQS6 FBA_DQS7

FBA_CLK0 FBA_CLK0#

FBA_CLK1 FBA_CLK1#

FBA_CS0#_L <28>

FBA_ODT_L <28> FBA_CKE_L <28>

FBA_RST# <28,29>

FBA_WE# <28,29>

FBA_CAS# <28,29> FBA_CS0#_H <29>

FBA_ODT_H <29> FBA_CKE_H <29>

FBA_RAS# <28,29>

FBA_CLK0 <28> FBA_CLK0# <28>

FBA_CLK1 <29> FBA_CLK1# <29>

2

1

Mode D - Mirror Mode Mapping

Address

FBx_CMD0

FBx_CMD1

FBx_CMD2

FBx_CMD3

FBx_CMD4

FBx_CMD5

FBx_CMD6

FBx_CMD7

FBx_CMD8

FBx_CMD9

FBx_CMD10

FBx_CMD11

FBx_CMD12

FBx_CMD13

FBx_CMD14

FBx_CMD15

FBx_CMD16

FBx_CMD17

FBx_CMD18

FBx_CMD19

FBx_CMD20

FBx_CMD21

FBx_CMD22

FBx_CMD23

FBx_CMD24

FBx_CMD25

FBx_CMD26

FBx_CMD27

FBx_CMD28

FBx_CMD29

FBx_CMD30

DATA Bus

0..31

CS0#_L

ODT_L

CKE_L

A14

RST

A9

A7

A2

A0

A4

A1

BA0

WE#

A15

CAS#

A13

A8

A6

A11

A5

A3

BA2

BA1

A12

A10

RAS#

32..63

A14

RST

A9

A7

A2

A0

A4

A1

BA0

WE#

A15

CAS#

CS0#_H

ODT_H

CKE_H

A13

A8

A6

A11

A5

A3

BA2

BA1

A12

A10

RAS#

N14M-LP-S-A2_FCBGA595

N14PGV2@ SA00005NC10

For GC6 (+1.5VS_VGA)

+3VS

13

D

From PCH

From EC

A A

DGPU_GC6_EN<14>

FB_CLAMP

DGPU_GC6_EN

1 2

RV57 0_0402_5%@RV57 0_0402_5%@

1 2

RV58 0_0402_5%RV58 0_0402_5%

12

RV59

@ RV59

@

10K_0402_5%

2

G

DGPU_PWROK<19,54,62,63>

QV8

@

QV8

@

2N7002KW_SOT323-3

S

GC6_EN

DGPU_PWROK

RV61 0_0402_5%@RV61 0_0402_5%@

N14PGV2@ SA00005NC10

DV2

DIS@

DV2

DIS@

2

1

3

DAN202UT106_SOT323-3

SC600001U00

1 2

FBVDDQ_PWR_EN

DIS@ RV60

DIS@

+1.5VS_VGA

12

RV60 200K_0402_5%

200K_0402_5%

FBVDDQ_PWR_EN <54>

From +VGA_CORE IC (follow +3VS)

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/12/05

LC Future Center Secret Data

Deciphered Date

2

2014/12/05

Title

N14P_MEM IF/FB CLAMP

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

E440 NM-A151

E440 NM-A151E440 NM-A151

1

27 57

of

1.0

5

4

3

2

1

Memory Partition A - Lower 32 bits

UV3

X76@

UV3

UV2

X76@

UV2

+1.5VS_VGA

D D

C C

B B

12

RV64

RV64 160_0402_1%

160_0402_1%

DIS@

RV62

1.1K_0402_1%

DIS@

RV63

1.1K_0402_1%

DIS@

FBA_CLK0

FBA_CLK0#

12

+FBA_VREF0

CV74

0.01U_0402_16V7K

12

1

DIS@CV74

DIS@

2

FBA_CLK0<27> FBA_CLK0#<27> FBA_CKE_L<27>

FBA_ODT_L<27> FBA_CS0#_L<27> FBA_RAS#<27,29> FBA_CAS#<27,29> FBA_WE#<27,29>

FBA_RST#<27,29>

RV67

RV67 10K_0402_5%

10K_0402_5%

DIS@

+1.5VS_VGA +1.5VS_VGA

CV75

0.1U_0402_10V7K

CV76

0.1U_0402_10V7K

1

DIS@CV75

DIS@

DIS@CV76

DIS@

2

U1406 SIDE U1407 SIDE

CV77

1

DIS@CV77

DIS@

2

CV79

0.1U_0402_10V7K

CV78

0.1U_0402_10V7K

1

DIS@CV79

DIS@

DIS@CV78

DIS@

2

12

0.1U_0402_10V7K

RV68

RV68 243_0402_1%

243_0402_1%

DIS@

CV80

1U_0402_6.3V6K

1

DIS@CV80

DIS@

2

+FBA_VREF0

FBA_MA0 FBA_MA1 FBA_MA2 FBA_MA3 FBA_MA4 FBA_MA5 FBA_MA6 FBA_MA7 FBA_MA8 FBA_MA9 FBA_MA10 FBA_MA11 FBA_MA12 FBA_MA13 FBA_MA14 FBA_MA15

FBA_BA0 FBA_BA1 FBA_BA2

FBA_CLK0 FBA_CLK0# FBA_CKE_L

FBA_ODT_L FBA_CS0#_L FBA_RAS# FBA_CAS# FBA_WE#

FBA_DQS0 FBA_DQS3

FBA_DQM0 FBA_DQM3

FBA_DQS#0 FBA_DQS#3

FBA_RST#

12

CV81

1U_0402_6.3V6K

1

DIS@CV81

DIS@

2

CV83

CV82

1U_0402_6.3V6K

1

DIS@CV83

DIS@

DIS@CV82

DIS@

2

X76@

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

K4W4G1646B-HC11_FBGA96

1U_0402_6.3V6K

CV84

1U_0402_6.3V6K

1

DIS@CV84

DIS@

2

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8

VSS9 VSS10 VSS11 VSS12

VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8

VSSQ10

E3

FBA_D4

F7

FBA_D1

F2

FBA_D7

F8

FBA_D0

H3

FBA_D6 FBA_D3 FBA_D5 FBA_D2

FBA_D29 FBA_D25 FBA_D30 FBA_D26 FBA_D28 FBA_D24 FBA_D31 FBA_D27

Group0 (IN3)

Group3 (BOT)

+1.5VS_VGA

CV86

CV85

0.1U_0402_10V7K

1

DIS@CV86

DIS@

DIS@CV85

DIS@

2

H8 G2 H7

D7 C3 C8 C2 A7 A2 B8 A3

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

+FBA_VREF0

FBA_MA0 FBA_MA1 FBA_MA2 FBA_MA3 FBA_MA4 FBA_D22 FBA_MA5 FBA_MA6 FBA_MA7 FBA_MA8 FBA_MA9 FBA_MA10 FBA_MA11 FBA_MA12 FBA_MA13 FBA_MA14 FBA_MA15

FBA_BA0 FBA_BA1 FBA_BA2

FBA_CLK0 FBA_CLK0# FBA_CKE_L

FBA_ODT_L FBA_CS0#_L FBA_RAS# FBA_CAS# FBA_WE#

FBA_DQS2 FBA_DQS1

FBA_DQM2 FBA_DQM1

FBA_DQS#2 FBA_DQS#1

FBA_RST#

12

RV69

RV69 243_0402_1%

243_0402_1%

DIS@

CV89

0.1U_0402_10V7K@CV89

0.1U_0402_10V7K

CV90

1U_0402_6.3V6K

0.1U_0402_10V7K

CV87

0.1U_0402_10V7K

CV88

0.1U_0402_10V7K

1

2

0.1U_0402_10V7K

1

DIS@CV87

DIS@

DIS@CV88

DIS@

2

1U_0402_6.3V6K

1

DIS@CV90

DIS@

@

2

X76@

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

K4W4G1646B-HC11_FBGA96

CV92

1U_0402_6.3V6K@CV92

1U_0402_6.3V6K

CV91

1U_0402_6.3V6K

1

DIS@CV91

DIS@

@

2

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8

VSS9 VSS10 VSS11 VSS12

VSSQ1 VSSQ2

VSSQ3

VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8

VSSQ10

CV93

1

DIS@CV93

DIS@

2

E3

FBA_D19

F7

FBA_D20

F2

FBA_D17

F8

FBA_D21

H3

FBA_D16

H8

FBA_D23

G2

FBA_D18

H7

D7

FBA_D10

C3

FBA_D15

C8

FBA_D8

C2

FBA_D13

A7

FBA_D9

A2

FBA_D12

B8

FBA_D11

A3

FBA_D14

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

1U_0402_6.3V6K

CV94

1U_0402_6.3V6K

1

DIS@CV94

DIS@

2

+1.5VS_VGA

FBA_ODT_L

FBA_CKE_L

Group2 (IN1)

Group1 (TOP)

RV65

RV65 10K_0402_5%

10K_0402_5%

DIS@

Mode D - Mirror Mode Mapping

12

RV66

RV66 10K_0402_5%

10K_0402_5%

DIS@

FBA_MA[15..0] <27,29>

FBA_BA[2..0] <27,29>

FBA_D[0..63] <27,29>

FBA_DQM[7..0] <27,29>

FBA_DQS[7..0] <27,29>

FBA_DQS#[7..0] <27,29>

Address

FBx_CMD0

FBx_CMD1

FBx_CMD2

FBx_CMD3

FBx_CMD4

FBx_CMD5

FBx_CMD6

FBx_CMD7

FBx_CMD8

FBx_CMD9

FBx_CMD10

FBx_CMD11

FBx_CMD12

FBx_CMD13

FBx_CMD14

FBx_CMD15

FBx_CMD16

FBx_CMD17

FBx_CMD18

FBx_CMD19

FBx_CMD20

FBx_CMD21

FBx_CMD22

FBx_CMD23

FBx_CMD24

FBx_CMD25

FBx_CMD26

FBx_CMD27

FBx_CMD28

FBx_CMD29

FBx_CMD30

DATA Bus

0..31

CS0#_L

ODT_L

CKE_L

A14

RST

A9

A7

A2

A0

A4

A1

BA0

WE#

A15

CAS#

A13

A8

A6

A11

A5

A3

BA2

BA1

A12

A10

RAS#

32..63

A14

RST

A9

A7

A2

A0

A4

A1

BA0

WE#

A15

CAS#

CS0#_H

ODT_H

CKE_H

A13

A8

A6

A11

A5

A3

BA2

BA1

A12

A10

RAS#

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/12/05

LC Future Center Secret Data

Deciphered Date

2

2014/12/05

Title

N14P_DDR3-A LOWER

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

E440 NM-A151

E440 NM-A151E440 NM-A151

1

28 57

of

1.0

5

4

3

2

1

Memory Partition A - Upper 32 bits

UV4

X76@

UV4

+1.5VS_VGA

D D

C C

B B

A A

1.1K_0402_1%

RV72

160_0402_1%

DIS@

FBA_CKE_H

FBA_ODT_H

RV73

10K_0402_5%

DIS@

+1.5VS_VGA +1.5VS_VGA

RV70

DIS@

RV71

DIS@

CV96

DIS@CV96

DIS@

12

+FBA_VREF1

CV95

0.01U_0402_16V7K

12

1

DIS@CV95

DIS@

2

FBA_CLK1

12

FBA_CLK1#

12

RV74

10K_0402_5%

DIS@

FBA_CLK1<27> FBA_CLK1#<27> FBA_CKE_H<27>

FBA_ODT_H<27> FBA_CS0#_H<27> FBA_RAS#<27,28> FBA_CAS#<27,28> FBA_WE#<27,28>

FBA_RST#<27,28>

U1409 SIDE

CV100

0.1U_0402_10V7K

CV98

0.1U_0402_10V7K

CV97

0.1U_0402_10V7K

1

2

1

DIS@CV98

DIS@

DIS@CV97

DIS@

2

0.1U_0402_10V7K

CV99

0.1U_0402_10V7K

CV101

1

DIS@CV99

DIS@

2

1

DIS@CV100

DIS@

DIS@CV101

DIS@

2

CV103

1U_0402_6.3V6K

CV102

1

DIS@CV102

DIS@

2

CV104

1U_0402_6.3V6K

1

DIS@CV103

DIS@

DIS@CV104

DIS@

2

+FBA_VREF1

FBA_MA0 FBA_MA1 FBA_MA2 FBA_MA3 FBA_MA4 FBA_MA5 FBA_MA6 FBA_MA7 FBA_MA8 FBA_MA9 FBA_MA10 FBA_MA11 FBA_MA12 FBA_MA13 FBA_MA14 FBA_MA15

FBA_BA0 FBA_BA1 FBA_BA2

FBA_CLK1 FBA_CLK1# FBA_CKE_H

FBA_ODT_H FBA_CS0#_H FBA_RAS# FBA_CAS# FBA_WE#

FBA_DQS4 FBA_DQS5

FBA_DQM4 FBA_DQM5

FBA_DQS#4 FBA_DQS#5

FBA_RST# FBA_RST#

12

RV75

243_0402_1%

DIS@

1U_0402_6.3V6K

CV105

1U_0402_6.3V6K

1

DIS@CV105

DIS@

2

X76@

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

K4W4G1646B-HC11_FBGA96

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8

VSS9 VSS10 VSS11 VSS12

VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8

VSSQ10

E3

FBA_D36

F7

FBA_D34

F2

FBA_D37

F8

FBA_D35

H3

FBA_D39

H8

FBA_D32

G2

FBA_D38

H7

FBA_D33

D7

FBA_D44

C3

FBA_D42

C8

FBA_D46

C2

FBA_D41

A7

FBA_D47

A2

FBA_D43

B8

FBA_D45

A3

FBA_D40

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

Group4 (IN1)

Group5 (TOP)

+1.5VS_VGA

+FBA_VREF1 FBA_D63

FBA_MA0 FBA_MA1 FBA_MA2 FBA_MA3 FBA_MA4 FBA_MA5 FBA_MA6 FBA_MA7 FBA_MA8 FBA_MA9 FBA_MA10 FBA_MA11 FBA_MA12 FBA_MA13 FBA_MA14 FBA_MA15

FBA_BA0 FBA_BA1 FBA_BA2

FBA_CLK1 FBA_CLK1# FBA_CKE_H

FBA_ODT_H FBA_CS0#_H FBA_RAS# FBA_CAS# FBA_WE#

FBA_DQS7 FBA_DQS6

FBA_DQM7 FBA_DQM6

FBA_DQS#7 FBA_DQS#6

12

RV76

243_0402_1%

DIS@

U1408 SIDE

UV6

0.1U_0402_10V7K@UV6

0.1U_0402_10V7K

CV109

0.1U_0402_10V7K@CV109

CV107

0.1U_0402_10V7K

CV106

0.1U_0402_10V7K

1

DIS@CV107

DIS@

DIS@CV106

DIS@

2

0.1U_0402_10V7K

CV108

0.1U_0402_10V7K

1

DIS@CV108

DIS@

2

1

@

2

CV111

CV110

1U_0402_6.3V6K@CV110

1U_0402_6.3V6K

1

@

2

CV113

1U_0402_6.3V6K@CV111

1U_0402_6.3V6K

CV112

1U_0402_6.3V6K@CV112

1U_0402_6.3V6K

1

@

2

M8 H1

N3

P7 P3

N2

P8

P2 R8 R2

T8 R3

L7 R7 N7

T3

T7 M7

M2 N8 M3

J7

K7

K9

K1

L2

J3

K3

L3

F3 C7

E7 D3

G3

B7

T2

L8

J1

L1

J9

L9

1U_0402_6.3V6K@CV113

1U_0402_6.3V6K

CV114

1U_0402_6.3V6K@CV114

1U_0402_6.3V6K

1

@

2

UV5

X76@

UV5

X76@

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8

VSS9 VSS10 VSS11 VSS12

VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8

VSSQ10

VREFCA VREFDQ

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3

BA0 BA1 BA2

CK CK CKE/CKE0

ODT/ODT0 CS/CS0 RAS CAS WE

DQSL DQSU

DML DMU

DQSL DQSU

RESET

ZQ/ZQ0

NC/ODT1 NC/CS1 NC/CE1 NCZQ1

K4W4G1646B-HC11_FBGA96

E3 F7

FBA_D58

F2

FBA_D60

F8

FBA_D59

H3

FBA_D61

H8

FBA_D56

G2

FBA_D62

H7

FBA_D57

D7

FBA_D55

C3

FBA_D51

C8

FBA_D54

C2

FBA_D49

A7

FBA_D52

A2

FBA_D50

B8

FBA_D53

A3

FBA_D48

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

Group7 (IN3)

Group6 (BOT)

+1.5VS_VGA

Mode D - Mirror Mode Mapping

Address

FBx_CMD0

FBx_CMD1

FBx_CMD2

FBx_CMD3

FBx_CMD4

FBx_CMD5

FBx_CMD6

FBx_CMD7

FBx_CMD8

FBx_CMD9

FBx_CMD10

FBx_CMD11

FBx_CMD12

FBx_CMD13

FBx_CMD14

FBx_CMD15

FBx_CMD16

FBx_CMD17

FBx_CMD18

FBx_CMD19

FBx_CMD20

FBx_CMD21

FBx_CMD22

FBx_CMD23

FBx_CMD24

FBx_CMD25

FBx_CMD26

FBx_CMD27

FBx_CMD28

FBx_CMD29

FBx_CMD30

FBA_D[0..63] <27,28>

FBA_MA[15..0] <27,28>

FBA_BA[2..0] <27,28>

FBA_DQM[7..0] <27,28>

FBA_DQS[7..0] <27,28>

FBA_DQS#[7..0] <27,28>

DATA Bus

0..31

CS0#_L

ODT_L

CKE_L

A14

RST

A9

A7

A2

A0

A4

A1

BA0

WE#

A15

CAS#

A13

A8

A6

A11

A5

A3

BA2

BA1

A12

A10

RAS#

32..63

A14

RST

A9

A7

A2

A0

A4

A1

BA0

WE#

A15

CAS#

CS0#_H

ODT_H

CKE_H

A13

A8

A6

A11

A5

A3

BA2

BA1

A12

A10

RAS#

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/12/05

LC Future Center Secret Data

Deciphered Date

2

2014/12/05

Title

N14P_DDR3-A UPPER

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

E440 NM-A151

E440 NM-A151E440 NM-A151

1

29 57

of

1.0

5

4

3

2

1

D D

12

RV77

45.3K_0402_1%

N14PGV2@

STRAP0<24> STRAP1<24> STRAP2<24> STRAP3<24> STRAP4<24>

STRAP0 STRAP1 STRAP2 STRAP3 STRAP4

12

RV82

RV82 10K_0402_5%

10K_0402_5%

@

N14M @ N14P @

12

RV78

RV78 10K_0402_5%

10K_0402_5%

X76@

12

RV83

RV83 10K_0402_5%

10K_0402_5%

X76@

12

RV79

29.4K_0402_1%

X76@

12

RV84

RV84 10K_0402_5%

10K_0402_5%

X76@

12

RV80

RV80 10K_0402_5%

10K_0402_5%

X76@

12

RV85

4.99K_0402_1%

X76@

+3VS_VGA

12

RV81

RV81 10K_0402_5%

10K_0402_5%

@

N14M @ N14P @

RV86

RV86 10K_0402_5%

10K_0402_5%

N14MGL@

Physical Strapping pin ROM_SCLK

ROM_SI

ROM_SO FB[0]

STRAP0

STRAP1

STRAP2

STRAP3

STRAP4

Power Rail

+3VS_VGA

Resistor Values

5K

10K

C C

+3VS_VGA

15K

20K

25K

12

RV87

RV87 10K_0402_5%

10K_0402_5%

@

ROM_SI<24> ROM_SO<24> ROM_SCLK<24>

ROM_SI ROM_SO ROM_SCLK

N14M @ N14P @

12

RV90

RV90 10K_0402_5%

10K_0402_5%

X76@

12

RV88

4.99K_0402_1%

N14PGV2@

12

RV91

RV91 10K_0402_5%

10K_0402_5%

N14MGL@

12

RV89

4.99K_0402_1%

N14PGV2@

12

RV92

RV92 10K_0402_5%

10K_0402_5%

N14MGL@

30K

35K

45K

SUB_VENDOR

0

No VBIOS ROM

1

BIOS ROM is present (Default)

Logical Strapping Bit3

PCI_DEVID[4]

FB[1]

PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]

SOR3_EXPOSED

RESERVED PCIE_SPEED_

Pull-up to +3VS_VGA

1000

Pull-down to Gnd

1001

1010

1011

1100

1101

1110

1111

3GIO_PADCFG[3:0]

0110

0000

Logical Strapping Bit2 SUB_VENDOR

RAM_CFG[2]

USER[2] USER[1] USER[0]USER[3]

3GIO_PADCFG[2] 3GIO_PADCFG[1]3GIO_PADCFG[3]

SOR2_EXPOSED SOR1_EXPOSED

CHANGE_GEN3

0000

0001

0010

0011

0100

0101

0110

0111

Gen1/Gen2 support only

Gen3 support

Logical Strapping Bit1

PCI_DEVID[5]

RAM_CFG[1]RAM_CFG[3]

Logical Strapping Bit0

PEX_PLL_EN_TERM

RAM_CFG[0]

VGA_DEVICESMB_ALT_ADDR

3GIO_PADCFG[0]

SOR0_EXPOSED

PCIE_MAX_SPEED DP_PLL_VDD33V

B B

ZZZ2

MT41J128M16JT

M1G@

SA00005M110

ZZZ3

K4W2G1646E

S1G@

SA00005SH20

ZZZ4

K4W4G1646B

S2G@

S2G@ SA00005OM00

SA00005OM00

ZZZ5

MT41K256M16HA

M2G@

M2G@ SA00005ON00

SA00005ON00

For N14P-GV2 QS Sample ROM_SO change from PU 10K to PU 5K ROM_SCLK change from PD 15K to PU 5K STRAP1 change from PD 5K to PD 45K STRAP2 change from PU 30K to PD 15K STRAP4 change from PD 5K to PD 45K

FB[1:0]

0

Reserved

1

Reserved

2

256MB (Default)

3

Reserved

USER Straps

RV77

10K_0402_5%

N14MGL@

SD02810028T

ZZZ6

A A

Micron

M1G@

X7600108001

5

RV86

45.3K_0402_1%

N14PGV2@

SD03445328T

ZZZ7

Samsung

S2G@

S2G@ X7600108004

X7600108004

Load BOMRV86, RV77

ZZZ9

ZZZ8

Micron

M2G@

M2G@ X7600108005

X7600108005

ZZZ9

Samsung

S1G@

S1G@ X7600108002

X7600108002

4

User[3:0]

1000-1100

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

Customer defined

2012/12/05

SMBUS_ALT_ADDR

0

0x9E (Default)

1

0x9C (Multi-GPU usage)

PCIE_MAX_SPEED

0

Limit booting to PCIE Gen1

1

Allow booting to PCIE Gen 2/3

PCIE_SPEED_CHANGE_GEN3

0

Disable PCIE Gen3 operation

1

Enable PCIE Gen3 operation

LC Future Center Secret Data

Deciphered Date

2

2014/12/05

VGA_DEVICE

0

3D Device (Class Code 302h)

1

VGA Device (Default)

PEX_PLL_EN_TERM

0

Disable (Default)

1

Enable

DP_PLL_VDD33V

0

Reserved

1

Default

Title

N14P_MISC(1/2)

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

E440 NM-A151

E440 NM-A151E440 NM-A151

1

30 57

of

1.0

5

D D

4

3

2

1

X76 RV90

GPU

N14P-GV2 S2G, X76~04 SA00005OM00

M2G, X76~05

C C

SA00005ON00

GPU

S1G, X76~02 SA00005SH20

M1G, X76~01

B B

SA00005M110

N14M-GL

FB Memory GDDR3

Samsung 1000MHz

Micron 1000MHz

*

Samsung 900MHz

*

Micron 900MHz

FB Memory GDDR3

*

Samsung 1000MHz

Hynix 1000MHz

*

Micron 1000MHz

Samsung 900MHz

Hynix 900MHz

Micron 900MHz

K4W2G1646E-BC1A

128Mx16

MT41J128M16JT-093G

128Mx16

K4W4G1646B-HC11

256Mx16

MT41K256M16HA-107G

256Mx16

K4W2G1646E-BC1A

128Mx16

H5TQ2G63DFR-N0C

128Mx16

MT41J128M16JT-093G

128Mx16

K4W4G1646B-HC11

256Mx16

H5TQ4G63MFR-11C

256Mx16

MT41K256M16HA-107G

256Mx16

ROM_SO ROM_SIROM_SCLK STRAP1

PD 45K

PD 30K

PU 5K

PD 20K

PD 10K

ROM_SO ROM_SIROM_SCLK STRAP0 STRAP1

PD 10K

RV77

PU, RV78 PD, RV83

PU, RV79 PD, RV84

STRAP2STRAP0

PU, RV80 PD, RV85

STRAP3 STRAP4

PU 45.3K PD 45.3K PD 15K PD 5K

PU, RV78 PD, RV83

RV77

PU 10K

PD 10K

PU 10K

PU 10K PU 10K PU 10K

PU 10K PU 10K

PU, RV79 PD, RV84

STRAP2

PD 10K

PU 10K PD 10K

PU 10K PU 10K

PD 10K

PU 10K

PD 10K

PU 10K PU 10KPD 10K

PU, RV80 PD, RV85

STRAP3 STRAP4

PD 10K

PD, RV86

PD 45.3K

PD, RV86

PD 10K

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/12/05

LC Future Center Secret Data

Deciphered Date

2

2014/12/05

Title

N14P_MISC(2/2)

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

E440 NM-A151

E440 NM-A151E440 NM-A151

1

31 57

of

1.0

A

1 1

B

C

D

E

Thermal Sensor

Thermal Sensor placed near by VRAM

U1

+3VS

2 2

1

C2

C2 .1U_0402_16V4-Z

.1U_0402_16V4-Z

2

REMOTE1+

REMOTE1-

REMOTE2+

REMOTE2-

U1

1

VDD

2

DP1

3

DN1

4

DP2/DN3

5

DN2/DP3

F75303M_MSOP10

SMCLK

SMDATA

ALERT#

THERM#

GND

10

EC_SMB_CK3

9

EC_SMB_DA3

8

7

R3 1 0K_0402_5%@R3 10K_0402_5%@

6

Address 1001_101xb

Internal pull up 1.2K to 1.5V R for initial thermal shutdown temp

1 2

EC_SMB_CK3 <17,23,48>

EC_SMB_DA3 <17,23,48>

+3VS

Close to U2

REMOTE1+

1

C3

C3 2200P_0402_50V7-K

2200P_0402_50V7-K

2

3 3

4 4

A

REMOTE1-

B

REMOTE2+

1

C4

C4 2200P_0402_50V7-K

2200P_0402_50V7-K

2

REMOTE2-

REMOTE1+ REMOTE2+

100P_0402_50V8-J

REMOTE1- REMOTE2-

1

C5

@C5

@

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

C

2

Q1

B

MMST3904-7-F_SOT323-3

E

SB000010U00

3 1

2012/12/05

Close to +CPU_COREClose to BOTTOM DDR3

1

C6

@C6

100P_0402_50V8-J

LC Future Center Secret Data

Deciphered Date

@

2

D

2

B

2014/12/05

C

Q2

MMST3904-7-F_SOT323-3

E

SB000010U00

3 1

REMOTE2+/-: Trace width/space:10/10 mil Trace length:<8"

Title

THERMAL SENSOR

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

E440 NM-A151

E440 NM-A151E440 NM-A151

E

32 57

of

1.0

5

D D

4

3

2

1

APS G-Sensor

+3VALW_GS

1 2

R84 0_0402_5%@R84 0_0402_5%@

W=40 mils

1 2

+3VALW

+3VS

C C

B B

PCH_GS_ON#<14>

EC_GS_ON#<48>

R4 0_0402_5%R4 0_0402_5%

1 2

R73 0_0402_5%@R73 0_0402_5%@

1 2

R85 0_0402_5%@R85 0_0402_5%@

1 2

R90 0_0402_5%R90 0_0402_5%

GS_SELFTEST<48>

+3V_GS

R8 100K_0402_5%R8 100K_0402_5%

1

C15

C15 10U_0603_6.3V6M

10U_0603_6.3V6M

2

+3VALW_GS +3V_GS

1

C7

C7 .1U_0402_16V4-Z

.1U_0402_16V4-Z

2

R7

1 2

100K_0402_5%

1 2

1

2

APS_GND

C16

C16 .1U_0402_16V7K

.1U_0402_16V7K

UGSEN1

2

14 15

3 5 6 7

LIS34ALTR_LGA16_4X4

SA000037F0J

ST

VDD_1 VDD_2

GND1 GND2 GND3 GND4

JAPS1

2MM

3 1

Q3

2

AP2301GN-HF_SOT23-3

SB00000YL00

1

C10

@ C10

@

0.01U_0402_16V7K

2

12

VoutX

10

VoutY

8

VoutZ

1

NC1

4

NC2

9

NC3

11

NC4

13

NC5

16

NC6

@JAPS1

@

21

1

C8

C8 .01U_0402_16V7-K

.01U_0402_16V7-K

2

VOUTXGS_SELFTEST GS_VOUTX VOUTY

1

C11

C11 .1U_0402_16V7K

.1U_0402_16V7K

2

APS_GND

+3V_GS

1

C9

@ C9

@

10U_0603_6.3V6M

2

1 2

R9 56K_0402_5%R9 56K_ 0402_5%

1 2

R10 56K_0402_5%R10 56K_0402_5%

1

C12

C12 .1U_0402_16V7K

.1U_0402_16V7K

2

APS_GND

1

C13

C13 .1U_0402_16V7K

.1U_0402_16V7K

2

GS_VOUTY

1

C14

C14 .1U_0402_16V7K

.1U_0402_16V7K

2

GS_VOUTX <48> GS_VOUTY <48>

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/12/05

LC Future Center Secret Data

Deciphered Date

2

2014/12/05

Title

APS G-SENSOR

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

E440 NM-A151

E440 NM-A151E440 NM-A151

1

33 57

of

1.0

5

4

3

2

1

+3VS

G

2

D D

PCH_HDMI_CLK<14>

PCH_HDMI_DATA<14>

CPU_HDMI_CLK+<8>

CPU_HDMI_CLK-<8>

CPU_HDMI_TX0+<8>

C C

CPU_HDMI_TX0-<8>

CPU_HDMI_TX1+<8>

CPU_HDMI_TX1-<8>

CPU_HDMI_TX2+<8>

CPU_HDMI_TX2-<8>

B B

PCH_HDMI_CLK

PCH_HDMI_DATA

CPU_HDMI_CLK+

CPU_HDMI_TX0+

CPU_HDMI_TX0-

CPU_HDMI_TX1+

CPU_HDMI_TX1-

CPU_HDMI_TX2+

CPU_HDMI_TX2-

1 2

C17 0.1U_0402_10V7-KC17 0.1U_0402_10V7-K

1 2

C18 0.1U_0402_10V7-KC18 0.1U_0402_10V7-K

1 2

C20 0.1U_0402_10V7-KC20 0.1U_0402_10V7-K

1 2

C23 0.1U_0402_10V7-KC23 0.1U_0402_10V7-K

1 2

C24 0.1U_0402_10V7-KC24 0.1U_0402_10V7-K

1 2

C25 0.1U_0402_10V7-KC25 0.1U_0402_10V7-K

1 2

C26 0.1U_0402_10V7-KC26 0.1U_0402_10V7-K

1 2

C27 0.1U_0402_10V7-KC27 0.1U_0402_10V7-K

S

61

D

G

S

Q4B

2N7002KDWH_SOT363-6

SB00000YR00

D

5

Q4A

2N7002KDWH_SOT363-6

SB00000YR00

34

D

HDMI_CLK+_CHDMI_CLK+_C HDMI_CLK+_CON

HDMI_TX0+_CHDMI_TX0+_C

HDMI_TX0-_CHDMI_TX0-_C HDMI_TX0-_CON

HDMI_TX1+_CHDMI_TX1+_C

HDMI_TX1-_CHDMI_TX1-_C HDMI_TX1-_CON

HDMI_TX2+_CHDMI_TX2+_C

HDMI_TX2-_CHDMI_TX2-_C HDMI_TX2-_CON

12

R11

2.2K_0402_5%

R17 0_0402_5%@R17 0_0402_5%@

1

4

R18 0_0402_5%@R18 0_0402_5%@

R19 0_0402_5%@R19 0_0402_5%@

1

4

R20 0_0402_5%@R20 0_0402_5%@

R21 0_0402_5%@R21 0_0402_5%@

1

4

R22 0_0402_5%@R22 0_0402_5%@

R23 0_0402_5%@R23 0_0402_5%@

1

4

R24 0_0402_5%@R24 0_0402_5%@

1 2

12

R12

2.2K_0402_5%

HDMI_CLK_CON HDMI_DET_CON

HDMI_DAT_CON

2

L1 WCM-2012-900T_4P

3

SM070003100

3

2

L2 WCM-2012-900T_4P

3

SM070003100

3

2

L3 WCM-2012-900T_4P

3

SM070003100

3

2

L4 WCM-2012-900T_4P

3

SM070003100

3

HDMI_CLK-_CONHDMI_CLK-_CHDMI_CLK-_CCPU_HDMI_CLK-

HDMI_TX0+_CON

HDMI_TX1+_CON

HDMI_TX2+_CON

PCH_HDMI_HPD<14>

PCH_HDMI_HPD

1

C21

C21 2200P_0402_50V7-K

2200P_0402_50V7-K

2

+5VS_HDMI

12

R13

R13 1M_0402_5%

1M_0402_5%

+5VS +5VS_HDMI

1

C22

0.1U_0402_10V7-K

2

HDMI_DET_CON

HDMI_DAT_CON HDMI_CLK_CON

HDMI_CLK-_CON

HDMI_CLK+_CON HDMI_TX0-_CON

HDMI_TX0+_CON HDMI_TX1-_CON

HDMI_TX1+_CON HDMI_TX2-_CON

HDMI_TX2+_CON

+3VS+5VS_HDMI

G

2

D

S

D

S

U2

1

VOUT

VIN

SA00004ZB0J

GND

APL3517AI-TRG_SOT23-3

19 18 17 16 15 14 13 12 11 10

Q5

Q5 2N7002KW_SOT323-3

2N7002KW_SOT323-3

13

12

3

2

HDMI CONN.

JHDMI1

ME@JHDMI1

ME@

HP_DET +5V DDC/CEC_GND SDA SCL Reserved CEC CK-

GND1

CK_shield

GND2

CK+

GND3

9

D0-

GND4

8

D0_shield

7

D0+

6

D1-

5

D1_shield

4

D1+

3

D2-

2

D2_shield

1

D2+

CONCR_099ATAC19NBLCNF

R15

R15 20K_0402_5%

20K_0402_5%

1

C19

0.1U_0402_10V7-K

2

20 21 22 23

For ESD

D3

D2

D1

RP1

HDMI_CLK-_CON HDMI_CLK+_CON HDMI_TX0-_CON HDMI_TX0+_CON

HDMI_TX1-_CON HDMI_TX1+_CON HDMI_TX2-_CON HDMI_TX2+_CON

A A

5

1 8 2 7 3 6 4 5

470_0804_8P4R_5%

SD300002O0T

RP2

1 8 2 7 3 6 4 5

470_0804_8P4R_5%

SD300002O0T

+3VS

HDMI_GND

2

G

13

D

Q6

Q6 2N7002KW_SOT323-3

2N7002KW_SOT323-3

S

4

+5VS_HDMI +5VS_HDMI

HDMI_DET_CON HDMI_DET_CON

HDMI_DAT_CON HDMI_DAT_CON

HDMI_CLK_CON HDMI_CLK_CON

1

2

4

5

3

8

AZ1045-04F_DFN2510P10E-10-9

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

9

10

8

9

7

6

65

2012/12/05

3

HDMI_CLK-_CON HDMI_CLK-_CON

HDMI_CLK+_CON HDMI_CLK+_CON

HDMI_TX0-_CON HDMI_TX0-_CON

HDMI_TX0+_CON HDMI_TX0+_CON

LC Future Center Secret Data

D2

1

2

4

5

3

8

AZ1045-04F_DFN2510P10E-10-9

Deciphered Date

9

10

8

9

7

6

65

2014/12/05

2

HDMI_TX1-_CON HDMI_TX1-_CON

HDMI_TX1+_CON HDMI_TX1+_CON

HDMI_TX2-_CON HDMI_TX2-_CON

HDMI_TX2+_CON HDMI_TX2+_CON

Title

Size Document Number Rev

Custom

Date: Sheet

D3

1

2

4

5

3

8

AZ1045-04F_DFN2510P10E-10-9

HDMI CONN.

Thursday, July 11, 2013

9

10

8

9

7

6

65

E440 NM-A151

E440 NM-A151E440 NM-A151

1

34 57

of

1.0

5

4

3

2

1

D4

3

I/O2

2

D D

GND

1

I/O1

AZC099-04S.R7G_SOT23-6

VDD

6

I/O4

5

4

I/O3

CRT_G_CON

VSYNC_CON HSYNC_CONCRT_B_CON CRT_R_CON

D5

3

2

1

AZC099-04S.R7G_SOT23-6

I/O2

GND

I/O1

I/O4

VDD

I/O3

6

5

4

+CRT_VCC+CRT_VCC

CRT_DDC_DAT_CONCRT_DDC_DAT_CONCRT_DDC_CLK_CON

1

C157

C157 2200P_0402_50V7-K

2200P_0402_50V7-K

2

+5VS +CRT_VCC

W=40mils

1

2

U8

1

C82

APL3517AI-TRG_SOT23-3

0.1U_0402_10V7-K

VIN

VOUT

SA00004ZB0J

GND

3

2

W=40mils

1

C28

0.1U_0402_10V7-K

2

closer to JCRT

CRT Connector

JCRT1

ME@JCRT1

ME@

From PCH

PCH_CRT_R<14>

PCH_CRT_G<14>

PCH_CRT_B<14>

C C

PCH_CRT_R

PCH_CRT_G

PCH_CRT_B

12

R34

R33

150_0402_1%

12

R35

150_0402_1%

1

C29

2

10P_0402_50V8-J

1

C31

C30

2

10P_0402_50V8-J

L5

1 2

NBQ100505T-800Y-N_2P

L6

1 2

NBQ100505T-800Y-N_2P

L7

1 2

NBQ100505T-800Y-N_2P

10P_0402_50V8-J

SM01000MC00

CRT_R_CON

CRT_G_CON

CRT_B_CON

1

C32

2

10P_0402_50V8-J

1

C34

C33

2

10P_0402_50V8-J

CRT_DDC_DAT_CON

HSYNC_CON

+CRT_VCC VSYNC_CON

CRT_DDC_CLK_CON

T79@T79@

closer to JCRT

+CRT_VCC

1 2

C35 0.1U_0402_16V7-KC35 0.1U_0402_16V7-K

From PCH

PCH_CRT_HSYNC<14>

B B

PCH_CRT_VSYNC<14>

PCH_CRT_HSYNC

1 2

C37 0.1U_0402_16V7-KC37 0.1U_0402_16V7-K

PCH_CRT_VSYNC

OE#

1

5

P

OE#

A2Y

G

U3

U3 SN74AHCT1G125DCKR_SC70-5

SN74AHCT1G125DCKR_SC70-5

3

+CRT_VCC

1

5

P

OE#

A2Y

G

U4

U4 SN74AHCT1G125DCKR_SC70-5

SN74AHCT1G125DCKR_SC70-5

3

4

1 2

R36 1K_0402_5%R36 1K_0402_5%

CRT_HSYNC_1 CRT_HSYNC_2

CRT_VSYNC_1

1 2

R37 33_0603_5%R37 33_0603_5%

1 2

R38 33_0603_5%R38 33_0603_5%

CRT_VSYNC_2

L8

1 2

NBQ100505T-800Y-N_2P

L9

1 2

NBQ100505T-800Y-N_2P

For CostDown

SM01000MC00

1

C36

@ C36

@

10P_0402_50V8-J

2

1

C38

@ C38

@

10P_0402_50V8-J

2

1

HSYNC_CON

VSYNC_CON

6

11

1 7

12

2 8

13

3 9

14

4 10 15

5

TE_2041480-1

16 17

+3VS

G

2

From PCH

PCH_CRT_DDC_DAT<14>

PCH_CRT_DDC_CLK<14>

A A

5

PCH_CRT_DDC_DAT

PCH_CRT_DDC_CLK

1 2

R41 0_0402_5%R41 0_0402_5%

1 2

R42 0_0402_5%R42 0_0402_5%

4

DDC_DAT_R

DDC_CLK_R

G

5

S

61

D

S

Q7A

Q7A 2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

SB00000YR00

34

D

Q7B

Q7B 2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

SB00000YR00

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

+CRT_VCC

12

R39

4.7K_0402_5%

1

C39

@ C39

@

100P_0402_50V8-J

2

2012/12/05

3

12

R40

4.7K_0402_5%

1

C40

@ C40

@

100P_0402_50V8-J

2

LC Future Center Secret Data

CRT_DDC_DAT_CONCRT_DDC_DAT_CON

CRT_DDC_CLK_CONCRT_DDC_CLK_CON

Deciphered Date

2

2014/12/05

Title

CRT CONN.

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

E440 NM-A151

E440 NM-A151E440 NM-A151

1

35 57

of

1.0

5

4

3

2

1

LCDVDD Circuit

+3VS

From PCH

1

C41

C41 1U_0402_6.3V6-K

1U_0402_6.3V6-K

2

PCH_ENVDD<14>

CMOS USB Port10

USB20_N13<18>

USB20_P13<18>

B+

2A 80 mil

+3VALW

LOGO_LED<48>

D D

C C

B B

U5

5

IN2

IN14EN

G5243AT11U_SOT23-5

SA00005XJ00

1 2

R50 0_0805_5%R50 0_0805_5%

1 2

R51 4.99K_0402_1%R51 4.99K_0402_1%

1

OUT

2

GND

3

1 2

R45 0_0402_5%R45 0_0402_5%

USB20_N13

USB20_P13

LOGO_LED

2

G

+LCDVDD_CON

LCD_ENVDD

R47 0_0402_5%@R47 0_0402_5%@

1

4

R48 0_0402_5%@R48 0_0402_5%@

1

C50

4.7U_0805_25V6-K

2

13

D

S

+LCDVDD_CON

1 2

1

2

4

3

1 2

2A 80 mil

+LEDVDD

+3VALW_LOGO

LOGO_LED#

Q9

Q9 2N7002KW_SOT323-3

2N7002KW_SOT323-3

1

C42

4.7U_0603_6.3V6-K

2

LCD_ENVDD

12

R46

R46 100K_0402_5%

100K_0402_5%

2

L10 WCM-2012-900T_4P

3

SM070003100

LOGO_LED# <4 1>

USB20_N13_CMOS

USB20_P13_CMOS

CPU_EDP_AUX#<8> CPU_EDP_AUX<8>

CPU_EDP_TX0+<8> CPU_EDP_TX0-<8>

CPU_EDP_TX1+<8> CPU_EDP_TX1-<8>

CMOS Camera

CMOS_ON#<19>

CPU_EDP_AUX# CPU_EDP_AUX

CPU_EDP_TX0+ CPU_EDP_TX0-

CPU_EDP_TX1+ CPU_EDP_TX1-

W=40 mils W=40mils

+3VS

R44

1 2

100K_0402_5%

+LEDVDD

R49 100K_0402_5%R49 100K_0402_5%

R158 0_0402_5%R158 0_0402_5%

+3VS

+3VS_CMOS

+LCDVDD_CON

DMIC_DATA<46>

DMIC_CLK<46>

1 2

C48 0.1U_0402_25V7-KC48 0.1U_0402_25V7-K

1 2

C49 0.1U_0402_25V7-KC49 0.1U_0402_25V7-K

1 2

C51 0.1U_0402_25V7-KC51 0.1U_0402_25V7-K

1 2

C52 0.1U_0402_25V7-KC52 0.1U_0402_25V7-K

1 2

C53 0.1U_0402_25V7-KC53 0.1U_0402_25V7-K

1 2

C54 0.1U_0402_25V7-KC54 0.1U_0402_25V7-K

CPU_EDP_HPD<8>

PCH_EDP_PWM<14> BKOFF#<48>

1

C43

@ C43

@

.1U_0402_16V4-Z

2

1

C47

C47 .1U_0402_16V4-Z

.1U_0402_16V4-Z

2

1 2

Q8

Q8 AO3413_SOT23-3

AO3413_SOT23-3

D

S

D

S

13

G

2

W= 80 mil

W= 40 mil

W= 20 mil W= 60 mil

+3VALW_LOGO LOGO_LED#

USB20_N13_CMOS USB20_P13_CMOS

DMIC_DATA DMIC_CLK

CPU_EDP_AUX#_CON CPU_EDP_AUX_CON

CPU_EDP_TX0+_CON CPU_EDP_TX0-_CON

CPU_EDP_TX1+_CON CPU_EDP_TX1-_CON

CPU_EDP_HPD

PCH_EDP_PWM BKOFF#

12

R53

R53 100K_0402_5%

100K_0402_5%

1

C44

@ C44

@

.01U_0402_16V7-K

2

JLCD1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

I-PEX_20374-030E-31

ME@JLCD1

ME@

G1 G2

31 32

1

C45

C45 .1U_0402_16V4-Z

.1U_0402_16V4-Z

2

+3VS_CMOS

1

C46

@ C46

@

10U_0603_6.3V6-M

2

ESD request

2

3

D6

D6 PESD5V0U2BT_SOT23-3

PESD5V0U2BT_SOT23-3

1

+3VALW_LOGO

LOGO_LED#

5

A A

EMI

+LEDVDD +3VALW_LOGO

1

C174

C174 47P_0402_50V8-J

47P_0402_50V8-J

2

Location : -4495,-1075 (BOT) Location : -4833,-1502 (BOT)

1

C175

C175 2200P_0402_50V7-K

2200P_0402_50V7-K

2

4

1

C176

C176 47P_0402_50V8-J

47P_0402_50V8-J

2

1

C177

C177 2200P_0402_50V7-K

2200P_0402_50V7-K

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/12/05

LC Future Center Secret Data

Deciphered Date

2

2014/12/05

Title

LCD/CMOS CONN.

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

E440 NM-A151

E440 NM-A151E440 NM-A151

1

36 57

of

1.0

A

+5VALW +USB_VCCA

W=80mils

1 1

USB_ON#<48> USB_OC0# <18>

USB_ON# USB_OC0#

1

C56

0.1U_0402_16V7-K

2

U6

1

GND

Vout1

2

Vout2

VIN1 VIN23Vout3

4

FLG

EN

G547I2P81U_MSOP8

Low Active 2.5A

8 7 6 5

B

W=80mils

1 2

C55 1000P_0402_50V7-K@C55 1000P_0402_50V7-K@

1

C57

@ C57

@

1000P_0402_50V7-K

2

For EMI

C

D

E

USB30 Front

D10

L12

L11

USB20_P0

USB20_N0

2 2

2

3

WCM-2012-900T_4P

SM070003100

USB30_TX_P2<18>

USB30_TX_N2<18>

USB20_P0<18>

USB20_N0<18> USB30_RX_P2<18>

USB30_RX_N2<18>

L11

2

1

USB20_P0_C

1

4

USB20_N0_C

4

USB30_TX_P2

USB30_TX_N2 USB20_P0 USB20_P0_C

USB30_RX_P2

USB30_RX_N2

USB3TXDP2

USB3TXDN2 USB3_TX2_C_N

1 2

C58 0.1U_0402_10V6-KC58 0.1U_0402_10V6-K

1 2

C59 0.1U_0402_10V6-KC59 0.1U_0402_10V6-K

L12

3

2

WCM-2012HS-900T_4P

SM070003100

4

USB3_TX2_C_P USB30_RX_P2

4

1

USB3TXDP2 USB3_TX2_C_P

USB3TXDN2

R54 0_0402_5%@R54 0_0402_5%@

R55 0_0402_5%@R55 0_0402_5%@ R56 0_0402_5%@R56 0_0402_5%@

R57 0_0402_5%@R57 0_0402_5%@ R58 0_0402_5%@R58 0_0402_5%@

R59 0_0402_5%@R59 0_0402_5%@

USB30_RX_N2 USB3_RX2_C_N

1 2

1 2 1 2

1 2

L13

3

2

WCM-2012HS-900T_4P

SM070003100

USB3_TX2_C_N

USB20_N0_CUSB20_N0 USB3_RX2_C_P

USB3_RX2_C_N

D9

4

USB3_RX2_C_P USB2 0_P0_C USB20_N0_C

4

1

+USB_VCCA

JUSB3

ME@JUSB3

ME@

9

StdA_SSTX+

1

VBUS

8

StdA_SSTX-

3

D+

7

GND_DRAIN

2

D-

6

StdA_SSRX+

4

GND_5

5

StdA_SSRX-

TAITW_PUBAU1-09FNLSCNN4H0

GND_1 GND_2 GND_3 GND_4

10 11 12 13

D9

1

V_I/O1

Ground2VBUS

3

V_I/O2

IP4223CZ6_SO6-6

+USB_VCCA

6

V_I/O4

5

4

V_I/O3

1

+

C60

C60 150U_B2_6.3VM_R35M

150U_B2_6.3VM_R35M

2

+USB_VCCA

1

2

C61

C61 470P_0402_50V7K

470P_0402_50V7K

USB3_TX2_C_P USB3_TX2_C_P

USB3_TX2_C_N

USB3_RX2_C_P

USB3_RX2_C_N

D10

1

2

4

5

3

8

AZ1045-04F_DFN2510P10E-10-9

1

C62

0.1U_0402_16V4Z

2

For ESD, Close to JUSB1

9

10

8

9

7

6

65

USB3_TX2_C_N

USB3_RX2_C_P

USB3_RX2_C_N

USB30 Back

D12

L14

3 3

4 4

USB20_P1

USB20_N1

L14

2

3

WCM-2012-900T_4P

SM070003100

USB30_TX_P5<18>

USB30_TX_N5<18>

USB20_P1<18>

USB20_N1<18> USB30_RX_P5<18>

USB30_RX_N5<18>

A

1

USB20_P1_C

1

4

USB20_N1_C

4

USB30_TX_P5

USB30_TX_N5 USB20_P1 USB20_P1_C

USB30_RX_P5

USB30_RX_N5

USB3TXDP5

USB3TXDN5 USB3_TX5_C_N

1 2

C63 0.1U_0402_10V6-KC63 0.1U_0402_10V6-K

1 2

C65 0.1U_0402_10V6-KC65 0.1U_0402_10V6-K

L15

3

2

WCM-2012HS-900T_4P

SM070003100

B

L16

4

USB3_TX5_C_P USB30_RX_P5

4

1

USB3TXDP5 USB3_TX5_C_P

USB3TXDN5

R60 0_0402_5%@R60 0_0402_5%@

R62 0_0402_5%@R62 0_0402_5%@ R61 0_0402_5%@R61 0_0402_5%@

R63 0_0402_5%@R63 0_0402_5%@ R64 0_0402_5%@R64 0_0402_5%@

R65 0_0402_5%@R65 0_0402_5%@

USB30_RX_N5 USB3_RX5_C_N

1 2

1 2 1 2

1 2

L16

3

2

WCM-2012HS-900T_4P

SM070003100

USB3_TX5_C_N

USB20_N1_CUSB20_N1 USB3_RX5_C_P

USB3_RX5_C_N

D11

4

USB3_RX5_C_P USB2 0_P1_C

4

1

+USB_VCCA

JUSB2

ME@JUSB2

ME@

9

StdA_SSTX+

1

VBUS

8

StdA_SSTX-

3

D+

7

GND_DRAIN

2

D-

6

StdA_SSRX+

4

GND_5

5

StdA_SSRX-

TAITW_PUBAU1-09FNLSCNN4H0

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

C

GND_1 GND_2 GND_3 GND_4

10 11 12 13

2012/12/05

1

V_I/O1

Ground2VBUS

3

V_I/O2

IP4223CZ6_SO6-6

LC Future Center Secret Data

6

V_I/O4

5

4

V_I/O3

+USB_VCCA

1

C64

0.1U_0402_16V4Z

2

For ESD, Close to JUSB2

Deciphered Date

USB20_N1_C

+USB_VCCA

D

2014/12/05

USB3_TX5_C_P USB3_TX5_C_P

USB3_TX5_C_N

USB3_RX5_C_P

USB3_RX5_C_N

D12

1

2

4

5

3

8

AZ1045-04F_DFN2510P10E-10-9

Title

USB30 PORT CONN.

Size Document Number Rev

Custom

Date: Sheet

9

10

8

USB3_TX5_C_N

9

7

USB3_RX5_C_P

7

6

USB3_RX5_C_N

65

Thursday, July 11, 2013

E440 NM-A151

E440 NM-A151E440 NM-A151

E

37 57

of

1.0

5

4

3

2

1

SATA HDD CONN.

+5VS

D D

C C

1

C66

C66 10U_0805_10V6-K

10U_0805_10V6-K

2

SATA_PTX_DRX_P0<13> SATA_PTX_DRX_N0<13>

SATA_PRX_DTX_N0<13> SATA_PRX_DTX_P0<13>

HDD_DETECT#<48>

1

C67

C67 10U_0805_10V6-K

10U_0805_10V6-K

2

SATA_PTX_DRX_P0 SATA_PTX_DRX_N0

SATA_PRX_DTX_N0 SATA_PRX_DTX_P0

HDD_DETECT#

1

C68

C68 1U_0603_10V6-K

1U_0603_10V6-K

2

1

C69

0.1U_0402_25V7-K

2

1 2

C138 .01U_0402_16V7-KC138 .01U_0402_16V7-K

1 2

C147 .01U_0402_16V7-KC147 .01U_0402_16V7-K

1 2

C71 .01U_0402_16V7-KC71 .01U_0402_16V7-K

1 2

C72 .01U_0402_16V7-KC72 .01U_0402_16V7-K

1

C70

C70 1000P_0402_50V7-K

1000P_0402_50V7-K

2

Pin18 connect to GND for SATA Gen3

SATA_PTX_C_DRX_P0 SATA_PTX_C_DRX_N0

SATA_PRX_C_DTX_N0 SATA_PRX_C_DTX_P0

+3VS

+5VS_HDD

+5VS +5VS_HDD

PJ1

112

JUMP_43X79

JHDD1

1

GND1

2

A+

3

A-

4

GND2

5

B-

6

B+

7

GND3

8

V33_1

9

V33_2

10

V33_3

11

GND4

12

GND5

13

GND6

14

V5_1

15

V5_2

16

V5_3

17

GND7

18

Reserved

19

GND8

20

V12_1

21

V12_2

22

V12_3

SANTA_198003-1

@PJ1

@

2

ME@JHDD1

ME@

23

GND9

24

GND10

SATA ODD CONN & ODD Power Control

JODD1

ME@JODD1

ME@

1

SATA_PTX_DRX_P2<13>

B B

A A

SATA_PTX_DRX_N2<13>

SATA_PRX_DTX_N2<13> SATA_PRX_DTX_P2<13>

ODD_DETECT#_DP_R<14>

ODD_DETECT#_DP<19>

PCH_ODD_DA#<14>

To PCH

SATA_PTX_DRX_P2 SATA_PTX_C_DRX_P2 SATA_PTX_DRX_N2

SATA_PRX_DTX_N2 SATA_PRX_DTX_P2

ODD_DETECT#_DP_R

ODD_DETECT#_DP

T2T2

5

1 2

C164 .01U_0402_16V7-KC164 .01U_0402_16V7-K

1 2

C165 .01U_0402_16V7-KC165 .01U_0402_16V7-K

1 2

C76 .01U_0402_16V7-KC76 .01U_0402_16V7-K

1 2

C78 .01U_0402_16V7-KC78 .01U_0402_16V7-K

1 2

R93 0_0402_5%R93 0_0402_5%

+5VS_ODD

1 2

R69 0_0402_5%R69 0_0402_5%

1 2

1

R70 0_0402_5%@R70 0_0402_5%@

SATA_PTX_C_DRX_N2

SATA_PRX_C_DTX_N2 SATA_PRX_C_DTX_P2

ODD_DA#

4

GND1

2

A+_RX+

3

A-_RX-

4

GND2

5

B-_TX-

6

B+_TX+

7

GND3

8

DP

9

+5V_1

10

+5V_2

11

MD

12

GND4

13

GND6

GND5

GND7

SUYIN_127382FB013M283ZR

+5VS_ODD

1

C185

@ C185

@

47P_0402_50V8-J

2

14 15

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

RF

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

+5VS TO +5VS_ODD

2012/12/05

3

1 2

R68 0_0805_5%@R68 0_0805_5%@

U11

5

1

C73

C73 1U_0402_6.3V6-K

1U_0402_6.3V6-K

2

LC Future Center Secret Data

Deciphered Date

IN2

IN14EN

G5243AT11U_SOT23-5

SA00005XJ00

2

1

OUT

2

GND

3

2014/12/05

+5VS_ODD+5VS

+5VS_ODD

ODD_EN

12

R66

R66 100K_0402_5%

100K_0402_5%

Title

SATA HDD/ODD CONN.

Size Document Number Rev

Custom

Date: Sheet

80 mils80 mils

From PCH

ODD_EN <19>

Thursday, July 11, 2013

1

C74

4.7U_0603_6.3V6-K

2

E440 NM-A151

E440 NM-A151E440 NM-A151

1

38 57

of

1.0

2

Mini-Express Card(WLAN/WiMAX)

1

1 2

+3VALW

1 2

+3VALW

+3V_WLAN

To PCH (X)

B B

BT_CTRL

PCH_BT_DISABLE#<19>

For EMI

PCH_BT_ON#<19>

CLK_PCI_DB_R

1 2

R74 0_0402_5%R74 0_0402_5%

1 2

R76 1K_0402_5%R76 1K_0402_5%

For isolate Intel Rainbow Peak and Compal debug card.

R79

1 2

@

10_0402_5%

R83

1 2

0_0402_5%

SB00000YR00

1

C83

@ C83

@

10P_0402_50V8-J

2

BT_CTRL

61

Q12A

@

Q12A

@

D

2N7002KDWH_SOT363-6

2

2N7002KDWH_SOT363-6

G

S

BT_CTRL_R

BT_DISABLE#

34

Q12B

D

2N7002KDWH_SOT363-6

S

SB00000YR00

To EC

@

5

G

WLAN_WAKE#<15>

WLAN_WAKE#_EC<48>

SUSP <55,60,63>

R126 0_0402_5%R126 0_0402_5%

BT_DET#<19>

EC_TX<48>

EC_RX<48>

R80 1K_0402_5%R80 1K_0402_5%

PCIE_PRX_DTX_N5<18> PCIE_PRX_DTX_P5<18>

PCIE_PTX_C_DRX_N5<18> PCIE_PTX_C_DRX_P5<18>

R81 100_0402_1%R81 100_0402_1% R107 100_0402_1%R107 100_0402_1%

R124 10K_0402_5%R124 10K_0402_5%

R125 10K_0402_5%@R125 10K_0402_5%@

1 2

CLKREQ_WLAN#<16>

CLK_PCIE_WLAN#<16> CLK_PCIE_WLAN<16>

1 2

+3V_WLAN

1 2 1 2

1 2

WLAN_WAKE#

BT_CTRL_R CLKREQ_WLAN#

PCI_RST#_R CLK_PCI_DB_R

PCIE_PRX_DTX_N5 PCIE_PRX_DTX_P5

PCIE_PTX_C_DRX_N5 PCIE_PTX_C_DRX_P5

+3V_WLAN

BT_DISABLE#

100K_0402_5%

For EC to detect debug card insert.

JMINI2

ME@JMINI2

ME@

1

3 5 7 9

12

R82

2

3

4

5

6

7

8

9

10 111112 131314 151516 171718 191920 212122 232324 252526 272728 292930 313132 333334 353536 373738 393940 414142 434344 454546 474748 494950 515152

GND153GND2

BELLW_80003-3041

+3V_WLAN

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52

54

+1.5VS LPC_FRAME#_R LPC_AD3_R LPC_AD2_R LPC_AD1_R LPC_AD0_R

BTRF_OFF# PLT_RST#

PM_SMBCLK_R PM_SMBDATA_R

USB20_N10 USB20_P10

+1.5VS

@ C186

@

+3VS

+1.5VS

1

2

BTRF_OFF# <48> PLT_RST# <14,17,41,42,44,48>

R77 0_0402_5%@R77 0_0402_5%@ R78 0_0402_5%@R78 0_0402_5%@

USB20_N10 <18> USB20_P10 <18>

1

C186 47P_0402_50V8-J

47P_0402_50V8-J

2

R27 0_0805_5%@R27 0_0805_5%@

R28 0_0805_5%@R28 0_0805_5%@

C81

0.1U_0402_25V7-K

1 2 1 2

RF

1 2

PM_SMBCLK <11,12,17,43> PM_SMBDATA <11,12,17,43>

WLAN&BT Combo module circuits

BT on module Enable

*

PCH_BT_DISABLE#

PCH_BT_ON#

+3V_WLAN

H

L

+3V_WLAN

1

2

C80

C80 10U_0805_10V6-K

10U_0805_10V6-K

BT on module Disable

L

H

Load Switch +3VALW To +3V_WLAN +3VALW To +3V_WWAN

A A

SUSP#<48,55,61,62>

WWAN_ON<19>

1. softstart (RC) will check on EVT PCB

2. if AOAC enable +3V_WLAN always ON if AOAC disable +3V_WLAN is same as +3VS

+3VALW

1

C150

@ C150

@

1U_0402_6.3V6-K

2

SUSP#

WWAN_ON

+3VALW

@ C151

@

AOAC_ON<48>

+5VALW

1

C151 1U_0402_6.3V6-K

1U_0402_6.3V6-K

2

1 2

R29 0_0402_5%@R29 0_0402_5%@

1 2

R30 0_0402_5%R30 0_0402_5%

2

VIN 5V and 3.3V (VBIAS=5V), IMAX(per channel)=6A, Rds=18mohm

AOAC_ON

WWAN_ON_R

U10

1

VIN1_1

2

VIN1_2

3

ON1

4

VBIAS

5

ON2

6

VIN2_1

7

VIN2_2

TPS22966DPUR_WSON14_2X3

+3V_WLAN, C165 --> 1.5ms +3V_WWAN, C163 --> 2.5ms

VOUT1_2 VOUT1_1

CT1

GND

CT2

VOUT2_2 VOUT2_1

GPAD

14 13

12

11

10

9 8

15

+3V_WLAN_LS

1 2

C84 1000P_0402_25V7-KC84 1000P_0402_25V7-K

1 2

C85 2200P_0402_25V7-KC85 2200P_0402_25V7-K

+3V_WWAN_LS

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Issued Date

PJ10

@PJ10

@

112

JUMP_43X79

PJ11

@PJ11

@

112

JUMP_43X79

2

+3V_WWAN

2

@ C153

@

2012/12/05

+3V_WLAN

@ C152

@

1

C153

0.1U_0402_10V7-K

2

1

C152

0.1U_0402_10V7-K

2

LC Future Center Secret Data

Deciphered Date

Reserve for SW mini-pcie debug card. Series resistors closed to KBC side.

LPC_FRAME#_R LPC_AD3_R LPC_AD2_R LPC_AD1_R LPC_AD0_R PCI_RST#_R CLK_PCI_DB_R CLK_PCI_DB

2014/12/05

1 2

R86 0_0402_5%@R86 0_0402_5%@

1 2

R87 0_0402_5%@R87 0_0402_5%@

1 2

R88 0_0402_5%@R88 0_0402_5%@

1 2

R89 0_0402_5%@R89 0_0402_5%@

1 2

R91 0_0402_5%@R91 0_0402_5%@

1 2

R92 0_0402_5%@R92 0_0402_5%@

1 2

R106 0_0402_5%@R106 0_0402_5%@

1

Size Document Number Rev

Date: Sheet

Title

PCIe-WLAN SLOT

Custom

Thursday, July 11, 2013

LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 PLT_RST#

LPC_FRAME# <17,44,48> LPC_AD3 <17,44,48> LPC_AD2 <17,44,48> LPC_AD1 <17,44,48> LPC_AD0 <17,44,48>

CLK_PCI_DB <16>

E440 NM-A151

E440 NM-A151E440 NM-A151

39 57

1.0

of

5

NGFF(SSD) & SIM CARD CONN.

4

3

2

1

D D

PJ8

@PJ8

@

2

@PJ9

@

2

W_DISABLE#

W_DISABLE2#

RESERVED3 RESERVED4 RESERVED5 RESERVED6 RESERVED7

SIM_DETECT

+3V_WWAN

3.3VAUX1

3.3VAUX2

LED#

NC

NC NC

NC

GPIO_5 GPIO_6 GPIO_7

UIM-RFU

UIM-RESET

UIM-CLK

UIM-DATA

UIM-PWR

DEVSLP

GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4

COEX3 COEX2 COEX1

SUSCLK

3.3VAUX3

3.3VAUX4

3.3VAUX5

PEG2

2 4 6 8 10

12

12 14

14 16

16 18

18

20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74

77

+3V_WWAN

+3VALW

12

R145

R145 10K_0402_5%

10K_0402_5%

PCH_MSATA_DET#<19>

PCH_3G_DET#<18> EC_3G_DET#<48>

C C

SATA_PRX_DTX_P1<13> SATA_PRX_DTX_N1<13>

SATA_PTX_DRX_N1<13> SATA_PTX_DRX_P1<13>

PCH_MSATA_DET#

T8T8

PCH_3G_DET# EC_3G_DET# 3G_DET#

SATA_PRX_DTX_P1 SATA_PRX_DTX_N1

SATA_PTX_DRX_N1

C90 .01U_0402_16V7-KC90 .01U_0402_16V7-K C93 .01U_0402_16V7-KC93 .01U_0402_16V7-K

C149 .01U_0402_16V7-KC149 .01U_0402_16V7-K C163 .01U_0402_16V7-KC163 .01U_0402_16V7-K

1 2

R94 0_0402_5%R94 0_0402_5%

1

1 2

R95 0_0402_5%@R95 0_0402_5%@

USB20_P11<18> USB20_N11<18>

1 2

R98 0_0402_5%R98 0_0402_5%

1 2

R96 0_0402_5%@R96 0_0402_5%@

1 2

R99 10K_0402_5%3G@R99 10K_0402_5%3G@

1 2 1 2

1 2

R102 10K_0402_5%3G@R102 10K_0402_5%3G@

1 2

R104 10K_0402_5%3G@R104 10K_0402_5%3G@

MSATA_DET#

USB20_P11 USB20_N11

SATA_PRX_C_DTX_P1 SATA_PRX_C_DTX_N1

SATA_PTX_C_DRX_N1 SATA_PTX_C_DRX_P1SATA_PTX_DRX_P1

+3VS

JMINI1

1

CONFIG_3

3

GND1

5

GND2

7

USB_D+

9

USBD-

11

GND3

13

NC

15

NC

17

NC

19

NC

21

CONFIG_0

23

WAKE_ON_WWAN#

25

DPR

27

GND4

29

USB3.0-TX-(Device)

31

USB3.0-TX+(Device)

33

GND5

35

USB3.0-RX-(Device)

37

USB3.0-RX+(Device)

39

GND6

41

SATA-B+/HRX+

43

SATA-B-/HRX-

45

GND7

47

SATA-A-/HTX-

49

SATA-A+/HTX+

51

GND8

53

RESERVED1

55

RESERVED2

57

GND9

59

ANTCTRL0

61

ANTCTRL1

63

ANTCTRL2

65

ANTCTRL3

67

RESET#

69

CONFIG_1

71

GND10

73

GND11

75

CONFIG_2

76

PEG1

FOX_AS0BC21-S30BB-7H

112

JUMP_43X118

PJ9

112

JUMP_43X118

ME@

FULL_CARD_POWER_OFF#

SSD Active:4.5W(1.5A)

2

C86

C86 .01U_0402_16V7-K

.01U_0402_16V7-K

1

R97 10K_0402_5%3G@R97 10K_0402_5%3G@

3G_OFF#

GPS_OFF#

UIM_RST UIM_CLK UIM_DATA +UIM_PWR SATA1_DEVSLP#_R SATA1_DEVSLP#

UIM_DET

1 2

+1.8VS

12

R101

3G@ R101

3G@

10K_0402_5%

12

R103

3G@ R103

3G@

10K_0402_5%

1

C87

0.1U_0402_25V7-K

2

3G_OFF# <19>

GPS_OFF# <19>

R100 20K_0402_5%3G@R100 20K_0402_5%3G@

R52 0_0402_5%@R52 0_0402_5%@

1 2

1

C89

C89 10U_0805_10V6-K

10U_0805_10V6-K

2

+3V_WWAN

@ C88

@

1

C88 10U_0805_10V6-K

10U_0805_10V6-K

2

1

3G@ C91

3G@

2

+3V_WWAN

C91

0.1U_0402_25V7-K

1

3G@ C92

3G@

2

40mil

C92

4.7U_0603_6.3V6K

+UIM_PWR

SATA1_DEVSLP# <14>

1 2

R105 10K_0402_5%@R105 10K_0402_5%@

D13 @

3

1

2

DAN217T146_SC59-3

+3VS

+UIM_PWR+UIM_VPP

B B

1. PCH_MSATA_DET# --> +3V_PCH EC_MSATA_DET# --> +3VL

2. PCH_3G_DET# --> +3VS EC_3G_DET# --> +3VL ECPCH

3. EC don't have GPIO pin for DET# pin as below a. PCH_3G_DET# b. PCH_MSATA_DET#

Only for 15"

UIM_DATA

+UIM_VPP

D14

@D14

@

1

2

3

AZC099-04S.R7G_SOT23-6

I/O1

GND

I/O2

I/O3

VDD

I/O4

4

UIM_CLK

5

+3VS

6

UIM_RST

UIM_DET +UIM_PWR

UIM_RST +UIM_VPP UIM_CLK UIM_DATA

C94

3G@ C94

3G@

0.1U_0402_25V7-K

1

2

JSIM1

ME@JSIM1

ME@

1

CD

2

C1

3

C5

4

C2

5

C6

6

C3

7

C7

8

GND1

9

GND2

PLAST_CE1S-148-H-N_7P-T

NGFF Detect Desc.

A A

No Card

WWAN CARD

SSD CARD

MSATA_DET#

1 1

1 0

0 0

5

3G_DET#

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/12/05

LC Future Center Secret Data

Deciphered Date

2

2014/12/05

Title

PCIe-WWAN/SIM SLOT

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

E440 NM-A151

E440 NM-A151E440 NM-A151

1

40 57

of

1.0

A

1 1

B

C

D

E

F

G

H

USB2.0, CR & LOGO Board

JUCR ME@

+5VALW

2 2

AOU_DET#<48>

LOGO_LED#<36>

USB_OC5#<18>

AOU_EN<48>

AOU_CTL1<48> AOU_CTL3<48>

USB20_N9<18> USB20_P9<18>

PCIE_PRX_DTX_P3<18> PCIE_PRX_DTX_N3<18>

PCIE_PTX_C_DRX_P3<18> PCIE_PTX_C_DRX_N3<18>

CLK_PCIE_CR<16> CLK_PCIE_CR#<16>

CLKREQ_CR#<16> PLT_RST#<14,17,39,42,44,48>

+3VALW +3VS

AOU_DET# LOGO_LED# USB_OC5# AOU_EN AOU_CTL1 AOU_CTL3

USB20_N9 USB20_P9

PCIE_PRX_DTX_P3 PCIE_PRX_DTX_N3

PCIE_PTX_C_DRX_P3 PCIE_PTX_C_DRX_N3

CLK_PCIE_CR CLK_PCIE_CR#

CLKREQ_CR# PLT_RST#

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

GND1

30

GND2

ACES_88194-2841

3 3

4 4

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

D

2012/12/05

E

LC Future Center Secret Data

Deciphered Date

F

2014/12/05

Title

PCIe-CR/USB-Charge CONN.

Size Document Number Rev

Custom

Thursday, July 11, 2013

G

Thursday, July 11, 2013

Date: Sheet

E440 NM-A151

E440 NM-A151E440 NM-A151

H

41 57

of

1.0

5

4

3

2

1

LAN (Port4) USB3.0/2.0 (Port1/3) DP(DDIC)

D D

To PCH

PCI_PME#<14>

C C

+5VS

1

C95

0.1U_0402_10V7-K

B B

+3VS

5

2

A2Y

3

R115 2.2K_0402_5%R115 2.2K_0402_5%

DOCK_HPD

1

P

4

PCH_DOCK_HPD

OE#

G

U7

U7 74AHCT1G125GW_SOT353-5

74AHCT1G125GW_SOT353-5

1 2

R109 1K_0402_5%R109 1K_0402_5%

PCH_DOCK_HPD <14>

PCH_DOCK_HPD

DOCK_HPD_CONN

1

C96

0.1U_0402_10V7-K

2

12

R112

R112 100K_0402_5%

100K_0402_5%

CPU_DOCK_TX0+<8> CPU_DOCK_TX0-<8> CPU_DOCK_TX1+<8> CPU_DOCK_TX1-<8>

PCH_DOCK_AUX<14> PCH_DOCK_AUX#<14>

DOCK_DETECT#<19>

USB3.0 Port1

CPU_DOCK_TX0+ CPU_DOCK_TX0CPU_DOCK_TX1+ CPU_DOCK_TX1-

USB2.0 Port3

1 2

C79 0.1U_0402_10V7-KC79 0.1U_0402_10V7-K

1 2

C148 0.1U_0402_10V7-KC148 0.1U_0402_10V7-K

+3VALW

+3VS +RTCBATT

+5VALW

PCIE_PRX_DTX_N4<18> PCIE_PRX_DTX_P4<18>

PCIE_PTX_C_DRX_N4<18> PCIE_PTX_C_DRX_P4<18>

CLK_PCIE_LAN#<16> CLK_PCIE_LAN<16> CLKREQ_LAN#<16> PLT_RST#<14,17,39,41,44,48>

LAN_WAKE#<48> PCH_LAN_25M<16>

PCI_PME#

USB30_TX_P1<18> USB30_TX_N1<18>

USB30_RX_P1<18> USB30_RX_N1<18>

1 2

R110 0_0402_5%R110 0_0402_5%

1 2

R111 0_0402_5%R111 0_0402_5%

1 2

R113 0_0402_5%R113 0_0402_5%

1 2

R114 0_0402_5%R114 0_0402_5%

USB20_P3<18> USB20_N3<18>

1 2

R43 0_0402_5%R43 0_0402_5%

DOCK_CONSUMP<58>

ON/OFFBTN#<45,48>

PCIE_PRX_DTX_N4 PCIE_PRX_DTX_P4

PCIE_PTX_C_DRX_N4 PCIE_PTX_C_DRX_P4

CLK_PCIE_LAN# CLK_PCIE_LAN CLKREQ_LAN# PLT_RST#

LAN_WAKE# PCH_LAN_25M

12

R1080_0402_5% @ R1080_ 0402_5% @

USB30_TX_P1 USB30_TX_N1

USB30_RX_P1 USB30_RX_N1

CPU_DOCK_TX0+_CON CPU_DOCK_TX0-_CON CPU_DOCK_TX1+_CON CPU_DOCK_TX1-_CON

USB20_P3 USB20_N3

PCH_DOCK_AUX_CONN PCH_DOCK_AUX#_CONN DOCK_DETECT#_CONNDOCK_DETECT# DOCK_CONSUMP DOCK_HPD_CONN ON/OFFBTN#

LAN CONN. (FFC)

JRJ45 ME@

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

GND1

22

GND2

ACES_88194-2041

DCIN CONN. (Coaxial)

JDCIN2

ME@JDCIN2

ME@

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

G1

22

G2

23

G3

24

G4

ACES_50406-02071-001

+3VS

PCH_DOCK_AUX#_CONN

PCH_DOCK_AUX_CONN

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/12/05

LC Future Center Secret Data

Deciphered Date

2

1 2

R16 100K_0402_5%R16 100K_0402_5%

1 2

R14 100K_0402_5%R14 100K_0402_5%

2014/12/05

Title

PCIe-RJ45/RTC/Docking CONN.

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

E440 NM-A151

E440 NM-A151E440 NM-A151

42 57

1

of

1.0

5

4

3

2

1

Click Pad

D D

PM_SMBCLK<11,12,17,39>

PM_SMBDATA<11,12,17,39>

CP_RESET#<48> TP_CLK<48> TP_DATA<48> TP4RST<48>

C C

+5VS

R116 4.7K_0402_5%R116 4.7K_0402_5%

R117 4.7K_0402_5%R117 4.7K_0402_5%

R119 100K_0402_5%R119 100K_0402_5%

1 2

PM_SMBCLK

TP_DATA2 TP_CLK2 PM_SMBDATA

CP_RESET# TP_CLK TP_DATA TP4RST BYPASS_PAD

4.7K_0402_5%

TP_CLK2

TP_DATA2

CP_RESET#

R123

100P_0402_50V8J

1 2

C98

+5VS

12 11 10

9 8 7 6 5 4 3 2 1

1

C99

@ C99

@

@C98

@

100P_0402_50V8J

2

1 2

R75 0_0402_5%R75 0_0402_5%

1 2

R71 0_0402_5%@R71 0_0402_5%@

TP_CLK TP_DATA

2

3

D15

D15 PESD5V0U2BT_SOT23-3

PESD5V0U2BT_SOT23-3

1

JCP1

ME@JCP1

ME@

14

12

GND2

13

11

GND1 10 9 8 7 6 5 4 3 2 1

ACES_51522-01201-001

TP_RESETTP4RST

BYPASS_PAD

TP_DATA2 TP_CLK2

2

3

D16

D16 PESD5V0U2BT_SOT23-3

PESD5V0U2BT_SOT23-3

1

Track point

+5VS

R118

1 2

4.7K_0402_5%

+5VS_TRACKP

4.7K_0402_5%

1

C97

0.1U_0402_16V4Z

2

JTP1

ME@JTP1

ME@

TP_DATA2 TP_RESET

TP_CLK2

+5VS +5VS_TRACKP

1

C75

C75 1U_0402_6.3V6-K

1U_0402_6.3V6-K

2

1

2

3

4

5

6

7

8

9

10

11 12

R5 0_0603_5%R5 0_0603_5%

5

13

11

GND1

14

12

GND2

JAE_FL10S012HA1

1 2

U12

@U12

@

1

OUT

IN2

IN14EN

G5243AT11U_SOT23-5

SA00005XJ00

GND

2

3

+5VS_TRACKP

TRACKP_ON

12

R67

@ R67

@

100K_0402_5%

80 mils80 mils

From PCH

TRACKP_ON <19>

1

C77

4.7U_0603_6.3V6-K

2

B B

A A

FAN CONN.

5

R120 0_0603_5%R120 0_0603_5%

+5VS

EC_FAN_PWM<48>

EC_FAN_SPEED<48>

FAN_ID<48>

1 2

40mil

1

C100

@ C100

@

1U_0402_6.3V6K

2

1

C101

C101 1000P_0402_50V7K

1000P_0402_50V7K

@

2

4

+VCC_FAN1

JFAN1

1

2

3

4

G1

5

G2

ACES_85205-05001

ME@JFAN1

ME@

6 7

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/12/05

LC Future Center Secret Data

Deciphered Date

2

2014/12/05

Title

CP/TP/FAN CONN.

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

E440 NM-A151

E440 NM-A151E440 NM-A151

1

43 57

of

1.0

5

4

3

2

1

D D

C C

TPM IC

UTPM1

TPM@UTPM1

TPM@

1 2 3 7

6 9

4 11 18

5

8 12 13 14

ST33ZP24AR28PVSP_TSSOP28

SA00005C010

NC_1 NC_2 NC_3 PP

NC_4 VNC_1

GND_1 GND_2 GND_3

NC_5 VNC_2 NC_6 NC_7 NC_8

VPS_1 VPS_2

LPCPD# SERIRQ

LAD0 LAD1

LFRAME#

LAD2 LAD3

NC_11

LCLK

NC_10

NC_9

LRESET#

24 10

28 27 26 23 22 20 17

25 21 19 15

16

1 2

R32 10K_0402_5%TPM@R32 10K_0402_5%TPM@

SERIRQ LPC_AD0 LPC_AD1 LPC_FRAME# LPC_AD2 LPC_AD3

CLK_PCI_TPM

PM_CLKRUN#

PLT_RST#

SERIRQ <17,48> LPC_AD0 <17,39,48> LPC_AD1 <17,39,48>

LPC_FRAME# <17,39,48> LPC_AD2 <17,39,48> LPC_AD3 <17,39,48>

CLK_PCI_TPM <16>

PM_CLKRUN# <15>

PLT_RST# <14,17,39,41,42,48>

1

TPM@

C102

C102 .1U_0402_16V4-Z

.1U_0402_16V4-Z

2

+3VS

1

TPM@

C103

C103 10U_0603_6.3V6-M

10U_0603_6.3V6-M

2

Touch Panel CONN.FingerPrint CONN.

+3VS

USB20_P12<18> USB20_N12<18>

B B

USB20_P12 USB20_N12

D17

AZC199-02SPR7G_SOT23-3

D17

3

1

223

C104

0.1U_0402_10V6-K

1

2

1

JFPB1

ME@JFPB1

ME@

8

GND2

7

GND1

6

5

4

3

2

1

ACES_88514-0060N-071

SMB_DATA_TPANEL<17> SMB_CLK_TPANEL<17>

USB20_N4<18> USB20_P4<18>

SMB_DATA_TPANEL SMB_CLK_TPANEL

USB20_N4 USB20_P4

1

C146

0.1U_0402_10V6-K

2

+3VS

1

C105

0.1U_0402_10V6-K

2

JTOUCH

1

2

3

4

5

6

7

8

9

10

11

GND1

12

GND2

ACES_50463-0104A-P01

ME@JTOUCH

ME@

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/12/05

LC Future Center Secret Data

Deciphered Date

2

2014/12/05

Title

TPM/TPanel/FP CONN.

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

E440 NM-A151

E440 NM-A151E440 NM-A151

1

44 57

of

1.0

5

PWR BTN/LID SW CONN.

4

3

2

1

D D

ON/OFF switch

SW1

@SW1

@

SMT1-05_4P

5

6

J3

1 2

SHORT PADS

@

3

4

1

Power Button TOP Side

2

Bottom Side

C C

+3VL

12

R121

R121 100K_0402_5%

100K_0402_5%

ON/OFFBTN#

ON/OFFBTN# <42,48>

1. Power Button/B link to Function/B Conn. 10pin

2. Lid Switch

+3VL

JPWR1

1

ON/OFFBTN#

LID_SW#<48>

LID_SW#

2

3

4

5

GND1

6

GND2

ACES_88514-0401

ME@JPWR1

ME@

KeyBoard CONN.(14")

KSI[0..7]

KSO[0..17]

KSI0

C108 @ 100P_0402_50V8JC108 @ 100P_0402_50V8J

KSI1

C110 @ 100P_0402_50V8JC110 @ 100P_0402_50V8J

KSI2

B B

C106 @ 100P_0402_50V8JC106 @ 100P_0402_50V8J

KSI3

C107 @ 100P_0402_50V8JC107 @ 100P_0402_50V8J

KSI4

C114 @ 100P_0402_50V8JC114 @ 100P_0402_50V8J

KSI5

C116 @ 100P_0402_50V8JC116 @ 100P_0402_50V8J

KSI6

C118 @ 100P_0402_50V8JC118 @ 100P_0402_50V8J

KSI7

C120 @ 100P_0402_50V8JC120 @ 100P_0402_50V8J

Fn_LED#

C124 @ 100P_0402_50V8JC124 @ 100P_0402_50V8J

F1_LED#

C126 @ 100P_0402_50V8JC126 @ 100P_0402_50V8J

F4_LED#

C128 @ 100P_0402_50V8JC128 @ 100P_0402_50V8J

KB_FN

C130 @ 100P_0402_50V8JC130 @ 100P_0402_50V8J

CONN PIN define need double check

A A

1 2

KSI[0..7] <48>

KSO[0..17] <48>

KSO0

KSO1

KSO2

KSO3

KSO4

KSO5

KSO6

KSO7

KSO8

KSO9

KSO10

KSO11

KSO12

KSO13

KSO14

KSO15

KSO16

KSO17

1 2

C109 @ 100P_0402_50V8JC109 @ 100P_0402_50V8J

1 2

C111 @ 100P_0402_50V8JC111 @ 100P_0402_50V8J

1 2

C112 @ 100P_0402_50V8JC112 @ 100P_0402_50V8J

1 2

C113 @ 100P_0402_50V8JC113 @ 100P_0402_50V8J

1 2

C115 @ 100P_0402_50V8JC115 @ 100P_0402_50V8J

1 2

C117 @ 100P_0402_50V8JC117 @ 100P_0402_50V8J

1 2

C119 @ 100P_0402_50V8JC119 @ 100P_0402_50V8J

1 2

C121 @ 100P_0402_50V8JC121 @ 100P_0402_50V8J

1 2

C122 @ 100P_0402_50V8JC122 @ 100P_0402_50V8J

1 2

C123 @ 100P_0402_50V8JC123 @ 100P_0402_50V8J

1 2

C125 @ 100P_0402_50V8JC125 @ 100P_0402_50V8J

1 2

C127 @ 100P_0402_50V8JC127 @ 100P_0402_50V8J

1 2

C129 @ 100P_0402_50V8JC129 @ 100P_0402_50V8J

1 2

C131 @ 100P_0402_50V8JC131 @ 100P_0402_50V8J

1 2

C132 @ 100P_0402_50V8JC132 @ 100P_0402_50V8J

1 2

C133 @ 100P_0402_50V8JC133 @ 100P_0402_50V8J

1 2

C134 @ 100P_0402_50V8JC134 @ 100P_0402_50V8J

1 2

C135 @ 100P_0402_50V8JC135 @ 100P_0402_50V8J

+3VS

FN_LED#<19> F1_LED#<19> F4_LED#<19>

KB_FN<48>

1 2

R122 300_0402_5%R122 300_0402_5%

KSI1 KSI7 KSI6 KSO9 KSI4 KSI5 KSO0 KSI2 KSI3 KSO5 KSO1 KSI0 KSO2 KSO4 KSO7 KSO8 KSO6 KSO3 KSO12 KSO13 KSO14 KSO11 KSO10 KSO15

Fn_LED# F1_LED# F4_LED# KB_FN

KSO16 KSO17

JKB1

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

JAE_FL10S032HA1

ME@JKB1

ME@

GND2 GND1

34 33

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/12/05

LC Future Center Secret Data

Deciphered Date

2

2014/12/05

Title

KB/PWR BTN CONN.

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

E440 NM-A151

E440 NM-A151E440 NM-A151

1

45 57

of

1.0

A

+5VS

RA1

1 2

0_0805_5%

1 1

CA2

4.7U_0603_10V6-K

1

@

2

CA4

CA3

0.1U_0402_10V7-K

4.7U_0603_10V6-K

1

2

Close to Pin13,16

B

+1.8V_LDO

+5VS_CLASSD

CA5

0.1U_0402_10V7-K

1

2

CA6 0.1U_0402_10V7-KCA6 0.1U_0402_10V7-K

2

1

C

LDO 1V8

CA7 4.7U_0402_6.3V6-MCA7 4.7U_0402_6.3V6-M

2

1

X5R CAP X5R CAP

+1.65V_LDO

CA8 0.1U_0402_10V7-KCA8 0.1U_0402_10V7-K

1

2

D

VREF 1V65

CA9 1U_0402_6.3V6-KCA9 1U_0402_6.3V6-K

1

2

X5R CAP

+3V_LDO

CA10 0.1U_0402_10V7-KCA10 0.1U_0402_10V7-K

1

2

1

CA11 2.2U_0603_6.3V6-KCA11 2.2U_0603_6.3V6-K

E

LDO 3V3

F

G

+3VS

1

2

+3VS

1

2

+3V_AVDD_HP

12/3 For PH noise

1

CA13

CA13 1U_0402_6.3V6-K

1U_0402_6.3V6-K

2

CA1

0.1U_0402_10V7-K

CA12

0.1U_0402_10V7-K

C3505 close Pin7

1 2

RA28 0_0402_5%RA28 0_0402_5%

CA12 close Pin2

C3537 close Pin24

H

+3VS_VDDO

RA2 0_0805_5%RA2 0_0805_5%

RA3 0_0805_5%@RA3 0_0805_5%@

12

+3VALW

+3VS

RA4 0_0805_5%RA4 0_0805_5%

UA1

2 2

HDA_SDIN0<13>

DMIC_CLK<36> DMIC_DATA<36>

HDA_SDIN0

DMIC_CLK DMIC_DATA

HDA_RST_AUDIO#<13>

HDA_BITCLK_AUDIO<13>

HDA_SYNC_AUDIO<13>

1 2

RA5 33_0402_5%RA5 33_ 0402_5%

HDA_SDOUT_AUDIO<13>

PC_BEEP<47> EC_MUTE#<48>

JSENSE<47>

1 2

RA7 33_0402_5%RA7 33_ 0402_5%

+5VS_CLASSD

W= 80mils

3 3

+AVEE

HP indicate

HDA_RST_AUDIO#

HDA_BITCLK_AUDIO

HDA_SYNC_AUDIO

HDA_SDIN0_AUDIO HDA_SDOUT_AUDIO

PC_BEEP EC_MUTE#

JSENSE

DMIC_CLK_RDMIC_CLK_R

1 2

CA16 0.1U_0 402_10V7-KCA16 0.1U_0402_10V7-K

1 2

CA17 1U_040 2_6.3V6-KCA17 1U_0402_6.3V6-K

1

CA18

2.2U_0603_6.3V6-K

2

Should be connect to GNDA

UA1

9

RESET#

5

BIT_CLK

8

SYNC

6

SDATA_IN

4

SDATA_OUT

CX20751-11Z

10 39

38 37

40

1

11

13 16

19 20

21

41

CX20751-11Z_QFN40_5X5

SA00005ZT0J

CX20751-11Z

PC_BEEP SPKR_MUTE#

JSENSE GPIO1/PORTC_R_MIC

MUSIC_REQ/GPIO0/PORTC_L_MIC36MICBIASC DMIC_CLK/MUSIC_REQ/GPIO0 DMIC_DAT/GPIO1

CLASS-D_REF

LPWR_5.0 RPWR_5.0

FLY_P FLY_N

AVEE

GND

PORTB_R_LINE PORTB_L_LINE

PORTD_A_MIC PORTD_B_MIC

CX20751-21Z

FILT_1.8V

VDD_IO

VDDO_3.3

DVDD_3.3

AVDD_3.3

VREF_1.65V

AVDD_5V

LEFT+

LEFT-

RIGHT+

RIGHT-

MICBIASB

HGNDA HGNDB

AVDD_HP

PORTA_R

PORTA_L

3 7 2 18

27 29 28

12

SPK_L2+

14

SPK_L1-

17

SPK_R2+

15

SPK_R1-

35 34

33

PORTB_R

32

PORTB_L

30

EXT_MIC_A

31

EXT_MIC_B

25

HGNDA

26

HGNDB

24

23

HP_OUTR

22

HP_OUTL

+1.8V_LDO +3VS_VDDIO

+3VS_VDDO

+3VS_DVDD

+3V_LDO +1.65V_LDO +5VS_AVDD

SPK_L2+ <47> SPK_L1- <47>

SPK_R2+ <47> SPK_R1- <47>

+MICBIASB

PORTB_R <47> PORTB_L <47>

EXT_MIC_A <47> EXT_MIC_B <47>

HGNDA <47> HGNDB <47>

+3V_AVDD_HP

HP_OUTR <47> HP_OUTL <47>

Apple --> EXT_MIC_A, HGNDB Nokia --> EXT_MIC_B, HGNDA

+3VS

+3V_PCH

X5R CAP, Please Close Pin18

1

CA14

CA14 1U_0402_6.3V6-K

1U_0402_6.3V6-K

2

+5VS_AVDD

RA6 0_0805_5%RA6 0_0805_5%

1

CA15

CA15 1U_0402_6.3V6-K

1U_0402_6.3V6-K

2

1 2

RA25 0_0402_5%@RA25 0_0402_5%@

1 2

RA27 0_0402_5%RA27 0_0402_5%

12

Please Close Pin28

GND

+3VS+3VS_DVDD

+5VS

+3VS_VDDIO

1

CA42

4.7U_0402_6.3V6-M

2

+3VS_VDDIO

CA42 close Pin7

EMI, close to UA1

RA26

HDA_BITCLK_AUDIO_C HDA_BITCLK_AUDIO

1

CA41

@ CA41

@

4 4

22P_0402_50V8-J

2

HDA_RST_AUDIO# HDA_SYNC_AUDIO HDA_SDOUT_AUDIO

1

CA37

@ CA37

@

22P_0402_50V8-J

2

A

1 2

@

33_0402_5%

1

CA38

@ CA38

@

22P_0402_50V8-J

2

B

1

CA39

@ CA39

@

22P_0402_50V8-J

2

RF, close to RA7

DMIC_CLK

1

CA40

@ CA40

@

47P_0402_50V8-J

2

DMIC_DATA

1

CA43

@ CA43

@

47P_0402_50V8-J

2

C

W= 300mils

1 2

CA19 0.1U_0402_10V7-K@CA19 0.1U_0402_10V7-K@

1 2

CA20 0.1U_0402_10V7-K@CA20 0.1U_0402_10V7-K@

1 2

CA21 0.1U_0402_10V7-K@CA21 0.1U_0402_10V7-K@

GND

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

D

GNDA

2012/12/05

E

LC Future Center Secret Data

Deciphered Date

F

2014/12/05

Title

HDA-CX20751-CX

Size Document Number Rev

Custom

Thursday, July 11, 2013

G

Thursday, July 11, 2013

Date: Sheet

E440 NM-A151

E440 NM-A151E440 NM-A151

46 57

H

of

1.0

5

4

3

2

1

PC Beep Speaker OUT

D D

EC Beep

BEEP#<48>

PCH Beep

HDA_SPKR<13>

C C

EXT. MIC/LINE IN

EXT_MIC_A<46>

EXT_MIC_B<46>

B B

SCS00006S00

1 2

SCS00006S00

12

DA1 RB751V-40_SOD323-2

CA22 0.1U_0402_10V7-K@CA22 0.1U_0402_10V7-K@

CA23 0.1U_0402_10V7-K@CA23 0.1U_0402_10V7-K@

DA2 RB751V-40_SOD323-2

Apple --> EXT_MIC_A, HGNDB Nokia --> EXT_MIC_B, HGNDA

EXT_MIC_A

EXT_MIC_B

1 2

RA14 100_0402_5%RA14 100_0402_5%

1 2

RA15 100_0402_5%RA15 100_0402_5%

1 2

33_0402_5%

12

RA13

RA13 10K_0402_5%

10K_0402_5%

RA11

CA24

1 2

0.1U_0402_10V7-K

PC_BEEP

1 2

CA29 2.2U_0402_6.3V6-KCA29 2.2U_0402_6.3V6-K

1 2

CA30 2.2U_0402_6.3V6-KCA30 2.2U_0402_6.3V6-K

PC_BEEP <46 >

HGNDB

HGNDA

Changed CA29 & CA30 from 1uF to 2.2uF/X5R to meet Port-D(headset-Mic) THD+N <= -65 dB

SPK_L1-<46>

SPK_L2+<46>

SPK_R1-<46>

SPK_R2+<46>

SPK_L1-

SPK_L2+

SPK_R1-

SPK_R2+

CA25 1000P_0402_50V7-K@CA25 1000P_0402 _50V7-K@

CA26 1000P_0402_50V7-K@CA26 1000P_0402 _50V7-K@

CA27 1000P_0402_50V7-K@CA27 1000P_0402 _50V7-K@

CA28 1000P_0402_50V7-K@CA28 1000P_0402 _50V7-K@

JSENSE<46>

1 2

RA8 0_0603_5%RA8 0_0603_5%

1 2

RA9 0_0603_5%RA9 0_0603_5%

1 2

RA10 0_0603_5%RA10 0_0603_5%

1 2

RA12 0_0603_5%RA12 0_0603_5%

1 2

+3VS

12

RA18

5.11K_0402_1%

JSENSE

RA20 20K_0402_1%RA2 0 20K_0402_1%

RA21 39.2K_0402_1%RA21 39.2K_0402_1%

12

SPK_L1-_CON

SPK_L2+_CON

SPK_R1-_CON

SPK_R2+_CON

SPK_L1-_CON

SPK_L2+_CON

SPK_R1-_CON

SPK_R2+_CON

HGNDB<46> HGNDA<46>

HGNDB HGNDA

HP_OUTL_CON

HP_OUTR_CON JSENSE_CON

SPK CONN.

SPK_L1-_CON SPK_L2+_CON

SPK_R1-_CON SPK_R2+_CON

3 6

1

2 4

5

GNDA

JSPK1

1

2

3

G1

4

G2

ACES_85205-02001

JSPK2

1

2

3

G1

4

G2

ACES_85204-02001

Audio Jack

JAUHP ME@

SINGA_2SJ2326-001111

ME@JSPK1

ME@

ME@JSPK2

ME@

HeadPhone/LINE OUT

1 2

RA16 2.2K_0402_5%RA16 2.2K_0402_5%

HP_OUTL<46>

PORTB_L<46>

HP_OUTR<46>

PORTB_R<46>

HP_OUTL

PORTB_L

HP_OUTR

PORTB_R

RA19

1 2

100_0402_5%

RA24

1 2

100_0402_5%

CA31

1 2

4.7U_0402_6.3V6-M

CA32

1 2

4.7U_0402_6.3V6-M

1 2

RA17 5.1_0402_1%RA17 5.1_040 2_1%

1 2

RA22 2.2K_0402_5%RA22 2.2K_0402_5%

1 2

RA23 5.1_0402_1%RA23 5.1_040 2_1%

CA31, CA32 change to 4.7U for Quality requirement

A A

5

4

+MICBIASB

HP_OUTL_CON

+MICBIASB

HP_OUTR_CON

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

ESD Diode, close to JAUHP

DA3

2

1

PESD5V0U2BT_SOT23-3

HGNDB

3

HGNDA

EMI, close to JAUHP

HGNDB HGNDA HP_OUTL_CON HP_OUTR_CON

1

CA33

CA33 220P_0402_50V8-J

220P_0402_50V8-J

2

LC Future Center Secret Data

2012/12/05

LC Future Center Secret Data

1

2

Deciphered Date

CA34

CA34 220P_0402_50V8-J

220P_0402_50V8-J

2

DA4

2

1

3

PESD5V0U2BT_SOT23-3

1

2

2014/12/05

DA5

HP_OUTL_CON

HP_OUTR_CON

1

CA36

CA35

CA35 220P_0402_50V8-J

220P_0402_50V8-J

Title

Size Document Number Rev

Custom

Date: Sheet

CA36 220P_0402_50V8-J

220P_0402_50V8-J

2

HDA-HP/EXT MIC/SPK CONN.

Thursday, July 11, 2013

2

1

3

PESD5V0U2BT_SOT23-3

E440 NM-A151

E440 NM-A151E440 NM-A151

1

JSENSE_CON

47 57

of

1.0

5

4

3

2

1

+3VL

Close to EC

CE1

KBRST# SERIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 CLK_PCI_EC

HDD_DETECT# EC_RX EC_TX PLT_RST# EC_SCI# GATEA20

KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17

ON/OFFBTN#

EC_SMB_CK1 EC_SMB_DA1 H_PECI_R ADP_PROTECT EC_SMB_CK3 EC_SMB_DA3

+3VL_VSTBY0 VR_ON

USB_ON# EC_DPWROK EC_RSMRST#

EC_WAKE#

AC_PRESENT_R

1 2

0.1U_0402_25V7-K

4 5 6 7 8

9 10 13 14 15 16 17 22 23

126

58 59 60 61 62 63 64 65 36 37 38 39 40 41 42 43 44 45 46 51 52 53 54 55 56 57

110 111 115 116 117 118

94 95

112 125

33 35 93

2

128

UE1

IT8586E-AX_LQFP128_14X14

SA00005W940

KBRST#/GPB6 SERIRQ/GPM6 LFRAME#/GPM5 LAD3/GPM3 LAD2/GPM2 LAD1/GPM1 LAD0/GPM0 LPCCLK/GPM4 WRST# ECSMI#/GPD4 PWUREQ#/BBO/SMCLK2ALT/GPC7 LPCPD#/GPE6 LPCRST#/GPD2 ECSCI#/GPD3 GA20/GPB5

KSI0/STB# KSI1/AFD# KSI2/INIT# KSI3/SLIN# KSI4 KSI5 KSI6 KSI7 KSO0/PD0 KSO1/PD1 KSO2/PD2 KSO3/PD3 KSO4/PD4 KSO5/PD5 KSO6/PD6 KSO7/PD7 KSO8/ACK# KSO9/BUSY KSO10/PE KSO11/ERR# KSO12/SLCT KSO13 KSO14 KSO15 KSO16/SMOSI/GPC3 KSO17/SMISO/GPC5

PWRSW# XLP_OUT SMCLK1/GPC1 SMDAT1/GPC2 SMCLK2/PECI/GPF6 SMDAT2/PECIRQT#/GPF7 CRX1/SIN1/SMCLK3/GPH1/ID1 CTX1/SOUT1/GPH2/SMDAT3/ID2

VSTBY0 GPE4

GINT/CTS0#/GPD5 RTS1#/GPE5 CLKRUN#/GPH0/ID0

CK32KE/GPJ7 CK32K/GPJ6

D D

KBRST#<19>

SERIRQ<17,44>

LPC_FRAME#<17,39,44>

LPC_AD3<17,39,44>

+3VL

RE4

1 2

100K_0402_5%

+3VL

1 2

RE10 2.2K_0402_5%RE10 2.2K_0402_5%

1 2

C C

B B

RE11 2.2K_0402_5%RE11 2.2K_0402_5%

+3VALW

1 2

RE18 10K_0402_5%RE18 10K_0402_5%

1 2

RE19 10K_0402_5%RE19 10K_0402_5%

1 2

RE38 100K_0402_5%RE38 100K_0402_5%

1 2

RE16 10K_0402_5%RE16 10K_0402_5%

+3VS

1 2

RE13 2.2K_0402_5%RE13 2.2K_0402_5%

1 2

RE14 2.2K_0402_5%RE14 2.2K_0402_5%

1 2

RE7 10K_0402_5%RE7 10K_0402_5%

WRST# WRST#

1

CE12

CE12 1U_0603_10V6-K

1U_0603_10V6-K

2

EC_SMB_CK1 EC_SMB_DA1

KSO1 KSO2

HDD_DETECT#

KB_FN

EC_SMB_CK3 EC_SMB_DA3

LPC_FRAME#

RE37

H_PECI<6>

AC_PRESENT<15>

VGA_AC_DET<23>

1 2

43_0402_5%

+3VL

AC_PRESENT

VGA_AC_DET

LPC_AD2<17,39,44> LPC_AD1<17,39,44> LPC_AD0<17,39,44>

CLK_PCI_EC<16>

HDD_DETECT#<38>

EC_RX<39>

EC_TX<39>

PLT_RST#<14,17,39,41,42,44>

EC_SCI#<19> GATEA20<19>

KSI[0..7]<45>

KSO[0..17]<45>

KSI[0..7]

KSO[0..17]

ON/OFFBTN#<42,45>

EC_SMB_CK1<57,58> EC_SMB_DA1<57,58>

ADP_PROTECT<57>

EC_SMB_CK3<17,23,32> EC_SMB_DA3<17,23,32>

1 2

RE20 0_0402_5%RE20 0_0402_5%

USB_ON#<37> EC_DPWROK<15> EC_RSMRST#<15>

EC_WAKE#<13>

1 2

RE25 0_0402_5%RE25 0_0402_5%

1 2

RE26 0_0402_5%RE26 0_0402_5%

VR_ON<64>

+VCOREVCC

3

Int. K/B

Int. K/B Matrix

Matrix

VBAT

+3VS

11

12

VCC

VCORE

IT8586E/AX

IT8586E/AX LQFP-128L

LQFP-128L

WAKE UP

Clock

+3VL_AVCC

50

92

114

121

127

VSTBY2

VSTBY3

VSTBY4

VSTBY126VSTBY5

VSTBY(PLL)

LPC

EXTERNAL SERIAL FLASH

SPI Flash ROM

SM Bus

GPIO

VSS1

VSS2

VSS4

VSS349VSS6

1

27

91

113

All capacitors close to EC

+3VL

CE3

CE4

0.1U_0402_25V7-K

1

2

74

minimum trace width 12 mil

AVCC

PWM0/GPA0 PWM1/GPA1 PWM2/GPA2

PWM

UART

AVSS

VSS5

75

122

PWM3/GPA3 PWM4/GPA4 PWM5/GPA5

PWM6/SSCK/GPA6

PWM7/RIG1#/GPA7

TMRI0/GPC4 TMRI1/GPC6

ADC0/GPI0 ADC1/GPI1 ADC2/GPI2

ADC

ADC3/GPI3 ADC4/GPI4

ADC5/DCD1#/GPI5

ADC6/DSR1#/GPI6 ADC7/CTS1#/GPI7

DAC2/TACH0B/GPJ2 DAC3/TACH1B/GPJ3

DAC

DAC4/DCD0#/GPJ4

DAC5/RIG0#/GPJ5

PS2CLK0/TMB0/CEC/GPF0

PS2DAT0/TMB1/GPF1

PS2

PS2CLK2/GPF4

PS2DAT2/GPF5

EGAD/GPE1 EGCS#/GPE2 EGCLK/GPE3

GPIO

SSCE0#/GPG2 SSCE1#/GPG0

DSR0#/GPG6

DTR1#/SBUSY/GPG1/ID7

CRX0/GPC0

CTX0/TMA0/GPB2

RI1#/GPD0 RI2#/GPD1

TACH2/GPJ0

TACH1A/TMA1/GPD7

TACH0A/GPD6

L80HLAT/BAO/GPE0

L80LLAT/GPE7

IT8586E/FX LQFP

EC_AGND

GPF2 GPF3

GPH3/ID3 GPH4/ID4 GPH5/ID5 GPH6/ID6

AC_IN#

LID_SW#

GPJ1

CE5

CE6

CE7

CE8

0.1U_0402_25V7-K

1

2

24

LOGO_LED

25

AOU_DET#

28

CP_RESET#

29

LAN_WAKE#

30

GS_SELFTEST

31

EC_FAN_PWM

32

BEEP#

34

VDDQ_PGOOD

120

BATT_LEN#

124

SUSP#

66

GS_VOUTX

67

GS_VOUTY

68

BATT_TEMP

69

IMVP_IMON

70

EC_ON

71

ADP_I

72

FAN_ID

73

ADP_ID

78

SUSWARN#

79

MAINPWON

80

H_PROCHOT_EC

81

PCH_ENBKL

85

AOU_EN

86

PBTN_OUT#

87

PM_SLP_SUS#

88

SUSACK#

89

TP_CLK

90

TP_DATA

96

PCH_APWROK

97

PCH_PWR_EN

98

ACOFF

99

PCH_PWROK

101

BTRF_OFF#

NC1

102

EC_GS_ON#

NC2

103

EC_3G_DET#

NC3

105

VM_PWRON

NC4

108

AC_IN#

109

LID_SW#

82

FB_CLAMP

83

GC6_EVENT#

84

AOU_CTL1

77

PM_SLP_S5#

100

EC_MUTE#

106

TP4RST

104

ME_FLASH

107

SYSON

119

BKOFF#

123

AOAC_ON

18

PM_SLP_S3#

21

PM_SLP_S4#

76

PM_SLP_A#

48

AOU_CTL3

47

EC_FAN_SPEED

19

WLAN_WAKE#_EC

20

KB_FN

Please don't place any PU Resistor on GPG[7:2] (Reserve hardware strapping)

CE8

0.1U_0402_25V7-K

1

2

0.1U_0402_25V7-K

1

2

+3VL +3VL_AVCC

LOGO_LED <36>

AOU_DET# <41>

CP_RESET# <43>

LAN_WAKE# <42>

GS_SELFTEST <33> EC_FAN_PWM <43> BEEP# <47>

VDDQ_PGOOD <60>

BATT_LEN# <57> SUSP# <39,55,61,62>

GS_VOUTX <33> GS_VOUTY <33> BATT_TEMP <56,57> IMVP_IMON <64>

EC_ON <59> ADP_I <57,58> FAN_ID <43> ADP_ID <56>

SUSWARN# <15>

MAINPWON <56,57,59>

PCH_ENBKL <14>

AOU_EN <41>

PBTN_OUT# <15>

PM_SLP_SUS# <15,55>

SUSACK# <15>

TP_CLK <43>

TP_DATA <43>

PCH_APWROK <15>

PCH_PWR_EN <55> ACOFF <58>

PCH_PWROK <15,8>

BTRF_OFF# <39>

EC_GS_ON# <33> EC_3G_DET# <40>

VM_PWRON <53,67>

LID_SW# <45>

FB_CLAMP <23,27> GC6_EVENT# <19,23>

AOU_CTL1 <41>

PM_SLP_S5# <15>

EC_MUTE# <46>

TP4RST <43>

ME_FLASH <13>

SYSON <60>

BKOFF# <36>

AOAC_ON <39> PM_SLP_S3# <15> PM_SLP_S4# <15> PM_SLP_A# <15>

AOU_CTL3 <41> EC_FAN_SPEED <43> WLAN_WAKE#_EC <39> KB_FN <45>

LE1

1 2

BLM18PG181SN1D_0603

+3VL_AVCC

1

CE9

0.1U_0402_25V7-K

2

AC IN

1

CE10

CE10 1000P_0402_50V7-K

1000P_0402_50V7-K

2

EC_AGND

*

AC_IN#

RE21 10K_0402_5%RE21 10K_0402_5% RE23 0_0402_5%RE23 0_0402_5%

DV3 RB751V-40_SOD323-2@DV3 RB751V-40_SOD323-2@

CE15 100P_0402_50V8-JCE15 100P_0402_50V8-J

LE2

1 2

BLM18PG181SN1D_0603

USB_ON#

TP_CLK TP_DATA

EC_FAN_PWM

EC_FAN_SPEED

GC6_EVENT#

LID_SW#

GC6_EVENT#

AOU_DET#

FAN_ID

LAN_WAKE#

AOAC_ON

EC_MUTE#

1. Version CX : Don't Support Mirror Code Version DX/EX/FX : Support Mirror Code

2. For Mirror Code "H" --> Enable "L" --> Disable (Default)

1 2 1 2

12

1 2

RE12 10K_0402_5%RE12 10K_0402_5%

1 2

RE2 4.7K_0402_5%RE2 4.7K_0402_5%

1 2

RE3 4.7K_0402_5%RE3 4.7K_0402_5%

1 2

RE5 10K_0402_5%@RE5 10K_0402_5%@

1 2

RE6 10K_0402_5%RE6 10K_0402_5%

1 2

RE39 10K_0402_5%@RE39 10K_0402_5%@

1 2

RE22 10K_0402_5%RE22 10K_0402_5%

1 2

RE40 10K_0402_5%RE40 10K_0402_5%

1 2

RE15 10K_0402_5%RE15 10K_0402_5%

1 2

RE17 10K_0402_5%RE17 10K_0402_5%

1 2

RE36 10K_0402_5%RE36 10K_0402_5%

1 2

RE31 100K_0402_5%RE31 100K_0402_5%

1 2

RE35 10K_0402_5%@RE35 10K_0402_5%@

1 2

RE41 10K_0402_5%RE41 10K_0402_5%

+3VL

ACPRN <58>

+5VALW

+5VS

+3VS

+3VL

+3VALW

2014/12/05

SYSON, SUSP#

SUSP#

SYSON

1 2

RE29 100K_0402_5%RE29 100K_0402_5%

1 2

RE30 100K_0402_5%RE30 100K_0402_5%

1 2

CE16 0.1U_0402_25V7-K@CE16 0.1U_0402_25V7-K@

For EMC

Title

EC_IT8586E-CX LQFP_128P

Size Document Number Rev

C

Date: Sheet

E440 NM-A151

E440 NM-A151E440 NM-A151

Thursday, July 11, 2013

48 57

of

1

of

1.0

For factory EC flash

IT0 PADIT0 PAD

PROCHOT#

A A

For ESD

1 2

CE2 220P_0402_50V7-K@CE2 220P_0402_50V7-K@

For EMI

1 2

CE11 10P_0402_50V8-J@CE11 10P_0402_50V8-J@

12

CE14 100P_0402_50V8-JCE14 100P_0402_50V8-J

1 2

10_0402_5%

PLT_RST#

RE1

CLK_PCI_EC

@

BATT_TEMP

BATT_TEMPECADC pin

5

(EC asserts PROCHOT# signal by driving high, the level shifter must invert it and drive the processor side PROCHOT# low.)

VR_HOT#<56,57,64>

H_PROCHOT_EC

1 2

RE27 0_0402_5%RE27 0_0402_5%

QE1

QE1 2N7002KW_SOT323-3

2N7002KW_SOT323-3

1 2

RE8 0_0402_5%@RE8 0_0402_5%@

4

H_PROCHOT#

13

D

2

G

S

1

CE13

CE13 47P_0402_50V8-J

47P_0402_50V8-J

2

H_PROCHOT# <6>

PROCHOT <57>

3

IT1 PADIT1 PAD IT2 PADIT2 PAD IT3 PADIT3 PAD IT4 PADIT4 PAD

IT5 PADIT5 PAD IT6 PADIT6 PAD IT7 PADIT7 PAD

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

EC_SMB_CK1 EC_SMB_DA1

KSI7 KSI6 WRST#

2012/12/05

LC Future Center Secret Data

Deciphered Date

2

5

D D

C C

4

JDB1

ME@JDB1

ME@

1

2

3

4

5

6

7

8

9

10

11

GND1

12

GND2

ACES_85201-1205N

3

13 14

2

1

B B

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/12/05

LC Future Center Secret Data

Deciphered Date

2

2014/12/05

Title

BLANK

Size Document Number Rev

Custom

Date: Sheet

Thursday, July 11, 2013

E440 NM-A151

E440 NM-A151E440 NM-A151

1

49 57

of

1.0

A

+3VALW +3VALW +3VALW +3VALW

B

C

D

E

1

C166

0.1U_0402_10V7-K

1 1

2

1

C167

0.1U_0402_10V7-K

2

1

C168

0.1U_0402_10V7-K

2

1

C169

0.1U_0402_10V7-K

2

Location : 560.00 -6055.00 Location :1010.00 -130.00 Location : -2490.00 -5940.00 Location : -1880.00 142.00

+0.675VS +0.675VS

1

C170

C170 47P_0402_50V8-J

47P_0402_50V8-J

2

close to JDDR3L and Pin .203/.204

1. 47P --> Location : -3885,-5914 (BOT)

2 2

2. 2200P --> Location : -3885,-5877 (BOT)

1

C171

C171 2200P_0402_50V7-K

2200P_0402_50V7-K

2

1

C172

C172 47P_0402_50V8-J

47P_0402_50V8-J

2

close to JDDR3H and Pin .203/.204

1. 47P --> Location : -4198,-5416 (TOP)

2. 2200P --> Location : -4204,-5384 (Top)

1

C173

C173 2200P_0402_50V7-K

2200P_0402_50V7-K

2

3 3

4 4

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

C

2012/12/05

LC Future Center Secret Data

Deciphered Date

D

2014/12/05

Title

BLANK

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

E440 NM-A151

E440 NM-A151E440 NM-A151

E

50 57

of

1.0

5

D D

C C

4

3

2

1

B B

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/12/05

LC Future Center Secret Data

Deciphered Date

2

2014/12/05

Title

BLANK

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

E440 NM-A151

E440 NM-A151E440 NM-A151

1

51 57

of

1.0

Screw Hole

H9

H_4P0

@

1

H11

H_2P5

H20

H_2P5X3P0N

@

1

H16

@

1

H17

H_2P5

1

H_2P5

@

1

CPU Screw

H13

H_4P0

@

1

@

H21

@

1

H1

H_4P0

@

1

GPU Screw

H7

H_4P0

H10

H_4P0

@

1

H14

H_4P0

@

1

H_2P5

H_4P0

1

H_2P5

H22

H4

@

1

H_2P5N

H_2P5

H15

H_2P5

1

H18

H_2P5X3P0N

@

1

H19

H_2P5

1

H4

@

1

H6

H5

H_2P5

@

1

@

1

@

H23

H_2P5

@

1

H3

H2

@

1

@

H12

@

1

@

1

H_2P5

H3

@

1

H8

H8 H_3P3

H_3P3

LED3 LED2 LED1 LED4

POWER BATTERY T/P CapsLK

PCB Fedical Mark PAD

FD1FD1

FD2FD21FD3FD3

1

FD4FD4

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2012/12/05

LC Future Center Secret Data

Deciphered Date

2014/12/05

Title

LED

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

E440 NM-A151

E440 NM-A151E440 NM-A151

52 57

of

1.0

+3VALW to +3VM

FOR SBA Function POWER(always mount)

+3VALW +3VM

1

C136

C136 1U_0402_6.3V6-K

1U_0402_6.3V6-K

2

From EC

VM_PWRON<48,67>

U14

5

OUT

IN2

GND

IN14EN

G5243AT11U_SOT23-5

SA00005XJ00

1

+3VM

2

3

VM_PWRON_R

1 2

R25 0_0402_5%R25 0_0402_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

1

C137

4.7U_0603_6.3V6-K

2

VM_PWRON_R

12

R31

R31 100K_0402_5%

100K_0402_5%

already have 1M PD to GND on Power side

LC Future Center Secret Data

2012/12/05

Deciphered Date

2014/12/05

Title

ONOFF SW/ PWR-B CONN/ ISPD

Size Document Number Rev

Custom

Date: Sheet

JITR1_LA-4141P

Thursday, July 11, 2013

E540 NM-A161

E540 NM-A161E540 NM-A161

53 57

of

1.0

+1.5V to +1.5VS_VGA

+1.5VS +1.5VS_VGA

+VSB

12

R128

DIS@ R128

DIS@

100K_0402_5%

+1.5VS_VGA_GATE

61

D

FBVDDQ_PWR_EN# FBVDDQ_PWR_EN#

1 2

R132 0_0402_5%R132 0_0402_5%

12

R135

@ R135

@

100K_0402_5%

2

G

S

R131

1 2

DIS@

0_0402_5%

Q20A

DIS@

Q20A

DIS@

2N7002KDWH_SOT363-6

SB00000YR00

JUMP_43X79

Q18 AO4430L_SO8

AO4430L_SO8

8 7 6 5

DIS@ C142

DIS@

J4

112

DIS@Q18

DIS@

@J4

@

2

1 2 3

4

12

C142

0.01U_0603_50V7K

+1.5VS_VGA+1.5VS

12

R129

DIS@ R129

DIS@

150_0603_1%

34

D

S

C139

1

@

2

R134

5

1 2

G

0_0402_5%

DIS@

0_0402_5%

Q20B

Q20B 2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

SB00000YR00

C140

C141

10U_0603_6.3V6M

DIS@

C141

10U_0603_6.3V6M

1

DIS@

2

1. Mount 470 ohm of R129 (Speed up discharge electric time by 1.5VS_VGA).

+3VS to +3VS_VGA

+3VS +3VS_VGA

J5

112

JUMP_43X79

@J5

@

2

+5VALW

12

R127

DIS@ R127

12

R133 100K_0402_5%

100K_0402_5%

DIS@

2

G

100K_0402_5%

FBVDDQ_PWR_EN#

13

D

Q19

DIS@

Q19

DIS@

2N7002KW_SOT323-3

S

0.1U_0402_10V7K

From GPU

FBVDDQ_PWR_EN<27>

R130

1 2

DIS@

10K_0402_5%

@ R133

@

From GPU

1 2

R142 0_0402_5%DIS@R142 0_0402_5%DIS@

+5VALW

12

R139

DIS@ R139

DIS@

20K_0402_5%

DGPU_PWR_EN#

2

G

12

R144

DIS@ R144

DIS@

100K_0402_5%

1. R140 from 470 change to 150 (Speed up discharge electric time by 3VS_VGA).

2. R139 form 100K change to 20K (Let fall time rapider for 3VS_VGA).

+3VS +3VS_VGA

S

G

R141

1 2

DIS@

10K_0402_5%

61

D

S

Q23A

DIS@

Q23A

DIS@

2N7002KDWH_SOT363-6

SB00000YR00

C144

DIS@ C144

DIS@

0.01U_0402_16V7K

1 2

Q23B

Q23B 2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

SB00000YR00

D

13

Q22

Q22 AO3413_SOT23-3

AO3413_SOT23-3

2

DIS@

12

R140

DIS@ R140

DIS@

150_0603_1%

34

D

S

Power Up --> +3VS_VGA (En:DGPU_PWR_EN) +VGA_CORE (En:NVDD_PWR_EN, POK:DGPU_PWROK) +1.5VS_VGA (En:FBVDDQ_PWR_EN# = FB_CLAMP and DGPU_PWROK) +1.05VS_VGA (En:DGPU_PWROK#)

5

G

DIS@ C145

DIS@

1

C143

DIS@C143

DIS@

10U_0603_6.3V6M

2

R143

DIS@R143

DIS@

1 2

10K_0402_5%

1

C145

0.1U_0402_10V7K

2

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Issued Date

DGPU_PWR_EN#

2012/12/05

From +VGA_CORE IC

DGPU_PWROK<19,27,62,63>DGPU_PWR_EN<14 ,23>

LC Future Center Secret Data

Deciphered Date

R137

1 2

DIS@

10K_0402_5%

2014/12/05

@ R138

@

+5VALW

12

R136

DIS@ R136

DIS@

100K_0402_5%

DGPU_PWROK#

13

D

2

Q21

DIS@

Q21

DIS@

2N7002KW_SOT323-3

G

S

12

R138 100K_0402_5%

100K_0402_5%

S

Title

DOCKING USB30/DP

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

DGPU_PWROK# <63>

E440 NM-A151

E440 NM-A151E440 NM-A151

of

54 57

1.0

A

B

C

D

E

Load Switch +5VALW To +5VS

1 1

CPI, 14" only

+3VALW To +3VS

+5VALW

1

C187

C187 10P_0402_50V8-J

10P_0402_50V8-J

2

+5VALW

1

C178

0.1U_0402_25V7-K

2

1

C179

0.1U_0402_25V7-K

2

1

C180

0.1U_0402_25V7-K

2

+5VALW

1

C161

@ C161

@

1U_0402_6.3V6-K

2

+3VALW

@ C162

@

1

2

+5VALW

C162 1U_0402_6.3V6-K

1U_0402_6.3V6-K

ESD

2 2

+3VALW To +3V_PCH

From EC

From PCH

PCH_PWR_EN<48>

PM_SLP_SUS#<15,48>

PCH_PWR_EN

PM_SLP_SUS#

1 2

R152 0_0402_5%R152 0_0402_5%

1 2

R153 0_0402_5%@R153 0_0402_5%@

VIN 5V and 3.3V (VBIAS=5V), IMAX(per channel)=6A, Rds=18mohm

SUSP#

U9

1

VOUT1_2

VIN1_1

2

VOUT1_1

VIN1_2

3

ON1

4

VBIAS

5

ON2

6

VIN2_1

7

VIN2_2

TPS22966DPUR_WSON14_2X3

GND

VOUT2_2 VOUT2_1

GPAD

CT1

CT2

14

+5VS_LS

13

1 2

12

C159 1000P_0402_25V7-KC159 1000P_0402_25V7-K

11

1 2

10

C160 2200P_0402_25V7-KC160 2200P_0402_25V7-K

9 8

+3VS_LS

15

+5VS, C159 --> 1.5ms +3VS, C160 --> 2.5ms

1 2

R72 0_0805_5%@R72 0_0805_5%@

U13

5

1

C154

C154 1U_0402_6.3V6-K

1U_0402_6.3V6-K

2

IN2

IN14EN

G5243AT11U_SOT23-5

SA00005XJ00

OUT

GND

PJ6

@PJ6

@

112

JUMP_43X118

PJ7

@PJ7

@

112

JUMP_43X118

1

2

3

2

+3VS

2

1

@ C158

@

2

+3V_PCHPCH_PWR_EN_R

PCH_PWR_EN_R

+5VS

1

C156

@ C156

@

0.1U_0402_10V7-K

2

C158

0.1U_0402_10V7-K

12

R154

R154 100K_0402_5%

100K_0402_5%

+5VS

1

C181

0.1U_0402_25V7-K

2

1

C182

0.1U_0402_25V7-K

2

1

C183

C183 33P_0402_50V8-J

33P_0402_50V8-J

2

1

C184

C184 33P_0402_50V8-J

33P_0402_50V8-J

2

ESD

+3V_PCH+3VALW

80 mils80 mils

0.271 A

1

C155

4.7U_0603_6.3V6-K

2

3 3

For DisCharge

+5VALW +0.675VS

12

R156

100K_0402_5%

SUSP<39,60,63>

SUSP#<39,48,61,62>

4 4

A

SUSP

61

Q30A

D

2

SUSP# SUSP

G

S

2N7002KDWH_SOT363-6

SB00000YR00

S

12

R157

R157 22_0805_5%

22_0805_5%

34

Q30B

D

5

G

S

2N7002KDWH_SOT363-6

SB00000YR00

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

C

2012/12/05

LC Future Center Secret Data

Deciphered Date

D

2014/12/05

Title

DC V TO V/VS INTERFACE

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

E440 NM-A151

E440 NM-A151E440 NM-A151

E

55 57

of

1.0

5

PR101

PR101 750_0402_1%

750_0402_1%

+3VALW

PJDCIN

D D

PJDCIN

1 2 3 4 5

8

6

GND1

9

7

GND2

ACES_50271-00701-001

@

1 2

APDIN

PF1

3 4 5 6 7

1 2

7A_32V_0437007.WR

1 2

APDIN1

12

PC101

0.1U_0402_6.3V7-K

1 2

SMB3025500YA_2P

12

1000P_0402_50V7-K

PC103

PC104

100P_0402_50V8-J

12

PL101

4

3

2

1

ADP_ID

AC Adapter 90W 65W

ADP_ID <48>

A/D

PC102

680P_0603_50V7K

VIN

12

100P_0402_50V8J

PC105

R(K ohm) open 10 ADP_ID(V) 3.3 1.65

Detection voltage >2.64 1.32~1.98

PC106

1000P_0402_50V7-K

540_0402NEW_30%_PRF15BB541NB6RC

+5VALW

VL

2013-05-21

12

+5VALW

VL

12

@

PR1215

10K_0402_5%

12

RT2

540_0402NEW_30%_PRF15BB541NB6RC

12

RT5

12

RT4

RT3

RT7

RT4

540_0402NEW_30%_PRF15BB541NB6RC

12

RT8

12

PR1214

PR1209

@

12

PR1208

10K_0402_5%

100K_0402_1%

PU1203

PR1210

100K_0402_1%

PU1203

1

IN+

VCC+

2

GND

OUT

3

IN-

LMV331IDCKRG4_SC70-5

Thermal protect

VL

12

PC1226

1U_0603_10V6K

5

4

PR1211

1 2

0_0402_5%

MAINPWON <48,57,59>

RT2 place to closed PQ401 with PU401 RT3 place to closed PQ402 with PU401

540_0402NEW_30%_PRF15BB541NB6RC

C C

540_0402NEW_30%_PRF15BB541NB6RC

RT4 place to closed PQ501 with PU501 RT5 place to closed PQ312 with PU301 RT7 place to closed PQ804 with PU801 RT8 place to closed PQ1001 with PU901

2013-04-18

VR_HOT#

VIN

13

D

PQ103

PD104

LL4148_LL34-2

PR123

13

@

LL4148_LL34-2

@

1 2

51ON-1

12

PC115

0.1U_0603_25V7K

@

PR124

PR124 68_1206_5%

68_1206_5%

@

PD105

LL4148_LL34-2

100K_0402_1%

RTCVREF

3.3V

12

PC116

PC116 10U_0603_6.3V6M

10U_0603_6.3V6M

12

PR128

@

PQ101

68_1206_5%

TP0610K-T1-GE3_SOT23-3

51ON-2

12

@

PC114

1 2

0.22U_0603_25V7K

51ON-3

68_1206_5%

2

BATT+

B B

2013-05-17

+CHGRTC

PR132

PD106

@

+RTCBATT

A A

1 2

RB751V-40_SOD323-2

PD107

1 2

RB751V-40_SOD323-2

PR132

560_0603_5%

1 2

+3VLP

@

PR133

560_0603_5%

1 2

@

VS

2013-04-18

VR_HOT#<48,57,64>

2013-04-18

PQ103

2N7002BKW_SOT323-3

PQ102

2N7002BKW_SOT323-3

2

G

S

12

PD102

PD102 LL4148_LL-34-2

LL4148_LL-34-2

13

D

2

G

S

12

PD101

PD101 LL4148_LL-34-2

LL4148_LL-34-2

PC108

1 2

0.022U_0402_25V7-K

12

PR106

1.5M_0402_5%

PC109

1 2

0.022U_0402_25V7-K

12

PR107

1.5M_0402_5%

12

PR104

PR104 47K_0402_1%

47K_0402_1%

LM393DMR2G MICRO8 8P

2013-04-25

12

PR105

PR105 47K_0402_1%

47K_0402_1%

LM393DMR2G MICRO8 8P

2013-04-25

PU101A

PU101B

+5VS

8

3

P

+

1

O

2

-

G

4

+5VS

8

5

P

+

7

O

6

-

G

4

+3VALW

12

BATT_TEMP <48,57>

1

12

2

PC107

100P_0402_50V8-J

PACIN <58>

PR103

PR103 10K_0402_1%

10K_0402_1%

PR102

PR102 100K_0402_1%

100K_0402_1%

2013-05-14

Title

Security Classification

Issued Date

RTC Battery

5

4

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/07/01

LC Future Center Secret Data

Deciphered Date

2

2014/07/01

Title

PWR-DCIN / Vin Detector

Size Document Number Rev

Custom

Date: Sheet

Thursday, July 11, 2013

E440 NM-A151

E440 NM-A151E440 NM-A151

1

56 69

of

1.0

5

4

3

2

1

PH1 under CPU botten side : CPU thermal protection at 93 +-3 degree C Recovery at 56 +-3 degree C

12

PQ203

PR201

100_0402_1%

PR222

PR222 100K_0402_1%

100K_0402_1%

1 2

PQ204

+3VLP

PR226

1 2

12

VMB

SMB3025500YA_2P

1 2

12

PC201

PC201 1000P_0402_50V7-K

1000P_0402_50V7-K

+3VALW

+3VALW+3VLP

2

G

12

PR214

100K_0402_1%

2013-04-18

PL201

1 2

PC202

.01U_0402_25V7-K

EC_SMB_CK1 <48,58>

EC_SMB_DA1 <48,58>

A/D

BATT_TEMP <48,56>

+1.05VS

PR220

PR220 100K_0402_1%

100K_0402_1%

1 2

13

D

S

2013-04-18

13

D

2

G

PC204

PQ205

2N7002BKW_SOT323-3

S

PQ202

TP0610K-T1-GE3_SOT23-3

2

0.22U_0603_25V7K

4

PR223

0.01_1206_1%

1

2

DCP

@ PC214

@

0.1U_0402_25V6

PR250

@ PR250

@

1 2

1K_0402_1%

@

1 2

PR251

1K_0402_1%

BATT_OUT <58>

VR_HOT#

MAINPWON

13

+VSBP

4

BATT+

3

DCN

2013-04-18

PC214

12

PR254 0_0402_5%@PR254 0_0402_5%@

@

12

PC205

0.1U_0603_25V7K

+1.05VS

DCN

@ PC212

@

0.1U_0402_25V6

PR255

12

@

0_0402_5%

12

PR261

374K_0402_1%

+VSBP

0.1U_0603_16V7K

VR_HOT#<48,56,64>

2N7002BKW_SOT323-3

PROCHOT<48>

VMB

PC212

1 2

@

PC215

0.1U_0402_25V6

1 2

10

PVIN2

9

PVIN1

8

SVIN1

5

EN

GND

11

PR259

20K_0402_1%

@

PJ201

PJ201 JUMP_43X39

JUMP_43X39

@

112

VL

1 2

PR227

2.1K_0402_1%

PR205

1 2

4.42K_0402_1%

2013-07-08

12

PR228

0_0402_5%

PR229

1 2

0_0402_5%

PR236

20K_0402_1%

VCP

1 2

3

2

12

PC208

220P_0402_50V7-K

Battery Protection Circuit for Turbo Mode

PR240

20K_0402_1%

1 2

PR245

PR245 10K_0402_1%

10K_0402_1%

5

6

12

PC210

220P_0402_50V7-K

PC203

PQ201

VCP

PU102

1

3

INA199A1DCKR_SC70-6

12

PR249

PR249 10K_0402_1%

10K_0402_1%

@

4

LX1

PG

LX2

LX3

FB

NC

PU203

7

RT9553

@

12

10K_0402_1%

13

D

S

PR248

PR248 0_0402_5%

0_0402_5%

1 2

REF

GND2IN-

V+

1

2

3

6

PR258

@

12

OUT

IN+

PR260

12

G

+3VS

PR209

1 2

2

ADP_OCP_1

PR212 0_0402_5%

0_0402_5%

1 2

@

6

5

DCN

4

DCP

PC213

1 2

0.1U_0402_25V6

@

1 2

PR257

13K_0402_1%

12

20K_0402_1%

@

@ PR252

@

1 2

10K_0402_1%

@ PR253

@

1 2

10K_0402_1%

ADP_I<48,58>

PU201

1

VCC

2

GND

3

OT1

4

100K_0402_1%

@PR212

@

G718TM1U_SOT23-8

2013-07-08

PR213

OTP_N_003

0_0402_5%

PR247

1 2

150K_0402_1%

OT2

@

TMSNS1

RHYST1

TMSNS2

RHYST2

12

8

7

OTP_N_002

6

5

ADP_OCP_2

MAINPWON <48,56,59>

PR246

@

12

100K_0402_1%

1 2

27.4K_0402_1%

T135@ T135@

T136@ T136@

PR210

1

Turbo_V_1

@

Turbo_V

NTC_V

+3VS

@PC213

@

2013-05-15

+5VALW

12

@

+3VALW

12

PR256

2.2_0402_5%

0.1U_0402_25V6

@

PC218

PR237

100K_0402_1%

PR238

100K_0402_1%

1 2

12

PC209

1 2

100P_0402_50V8-J

+3VS

PR252

PR253

+3VALW

150K_0402_1%

84.5K_0402_1%

2013-07-01

PR243

PR244

Turbo_V_1

1 2

12

PC211

1 2

100P_0402_50V8-J

Adaptor Protection Circuit for Turbo Mode

2

+VSB

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/07/01

LC Future Center Secret Data

Deciphered Date

2

2014/07/01

2013-04-18

PQ206

PQ206 2N7002BKW_SOT323-3

2N7002BKW_SOT323-3

13

D

2

G

S

PR230

0_0402_5%

ADP_PROTECT <48>

12

2013-07-08

+3VLP

PR211

10K_0402_1%

+5VS

+

-

1 2

PR231

47K_0402_1%

PR235

1 2

1.78M_0402_1%

8

P

1

O

G

PU1204A

LM393DMR2G MICRO8 8P

4

@

12

2013-04-25

+5VS

12

PR239

1 2

1.78M_0402_1%

8

P

+

7

O

-

G

PU1204B

LM393DMR2G MICRO8 8P

4

2013-04-25

Title

PWR-BATTERY CONN/OTP

Size Document Number Rev

Custom

Date: Sheet

Thursday, July 11, 2013

NTC_V_1

+3VALW

PR232

47K_0402_1%

PR234

221K_0402_1%

PR242

221K_0402_1%

+3VLP

12

@

12

PH201

100K_0402_1%_NCP15WF104F03RC

1 2

2013-04-18

13

D

2

PQ207

PQ207 2N7002BKW_SOT323-3

2N7002BKW_SOT323-3

G

S

PR241

PR241 0_0402_5%

0_0402_5%

1 2

2013-04-18

13

D

2

PQ208

PQ208 2N7002BKW_SOT323-3

2N7002BKW_SOT323-3

G

S

E440 NM-A151

E440 NM-A151E440 NM-A151

1

PR206

12.7K_0402_1%

PR208

499K_0402_1%

PR233

PR233 0_0402_5%

0_0402_5%

VR_HOT#

12

PR207

30K_0402_1%

2013-05-23

12

VR_HOT#

57 69

of

1.0

JBATT1

1

2

3

4

5

D D

C C

5

6

7

8

G1

9

G2

10

G3

11

G4

@

SUYIN_200082GR007M211ZR

2011_0823 change 9P JBATT1

VMB2

PR224

PR224 255K_0402_1%

255K_0402_1%

1 2

PR221

B B

PR221 150K_0402_1%

150K_0402_1%

1 2

EC_SMDA

12

PR202

100_0402_1%

PR202

100_0402_1%

2

3

PESD5V0U2BT_SOT23-3

PESD5V0U2BT_SOT23-3 PD806

PD806

@

1

2011_0731 add circuit for battery learning function 2011_1119 change circuit to unmount from mount

P2

1 2

PC207

.01U_0402_25V7-K

PR219

10K_0402_1%

.01U_0402_25V7-K

8

3

P

+

2

-

G

4

PR225

PR225 10K_0402_1%

10K_0402_1%

2013-04-18

VL

PR216

100K_0402_1%

VMB2

SPOK<59>

100K_0402_1%

1 2

PR217

PR217 1K_0402_5%

1K_0402_5%

1 2

5

A A

PF201

PF201 12A_65V_451012MRL

12A_65V_451012MRL

EC_SMCA

2

3

PESD5V0U2BT_SOT23-3

PESD5V0U2BT_SOT23-3 PD805

PD805

@

1

PR203

100K_0402_1%

12

1 2

PR204

PR204 750_0402_5%

750_0402_5%

PR218

10M_0402_5%

1 2

1

O

PU202A

LM393DMR2G MICRO8 8P

2013-04-25

+3VLP

12

BATT_LEN#<48>

B+

13

D

2

G

2N7002BKW_SOT323-3

S

12

PC206

1U_0402_10V6K

2011_1005 PQ105 change form SB000006800(2N7002W T/R7 1N SOT-323) to SB000009Q80( 2N7002KW 1N SOT323-3)

21

2N7002BKW_SOT323-3

100K_0402_1%

PR215

22K_0402_1%

1 2

5

2013-07-01

1 2 36

12

PC301

0.1U_0603_25V7K

PR309

150K_0402_1%

PQ310B

5

13

2013-04-18

P2

12

PR306

P2-1

12

P2-2

34

SI4483ADY 1P SO8

1 2 3 6

200K_0402_1%

12

PR331

20K_0402_1%

PQ317

13

D

2N7002BKW_SOT323-3

2

G

S

PR319

64.9K_0603_1%

1 2

PC323 0.1U_0603_25V7KPC323 0.1U_0603_25V7K

2N7002KDW-2N_SOT363-6

PQ304

4

2200P_0402_25V

2013-07-01

2013-04-18

PR314

EC_SMB_DA1<48,57>

EC_SMB_CK1<48,57>

PQ301

PQ301 AO4407AL_SO8

AO4407AL_SO8

VIN

D D

2013-04-18

C C

B B

12

PR301

61

2

2N7002KDW-2N_SOT363-6

PACIN<56>

ACOFF<48>

2013-07-08

8 7

5

PQ305

LTA044EUBFS8TL_UMT3F

47K_0402_5%

2

13

2

PQ310A

1 2

10K_0402_5%

BATT_OUT

PQ307

LTC015EUBFS8TL_UMT3F

PR318

47K_0402_1%

1 2

PACIN

PQ313

LTC015EUBFS8TL_UMT3F

PR321

ACOFF-1

PR332

0_0402_5%

2

G

4

1 3

2013-07-01

2013-04-18

2

12

13

D

PQ318

PQ318 2N7002BKW_SOT323-3

2N7002BKW_SOT323-3

S

CHGVADJ=(Vcell-4)/0.10627

Vcell

4V

4.2V

4.35V

CC=0.25A~3A

IREF=1.016*Icharge

IREF=0.254V~3.048V

VCHLIM need over 95mV

A A

CHGVADJ

0V

1.882V

3.2935V

5

2013-05-21

@

PR328

47K_0402_1%

ACPRN

2013-04-18

BQ24737_VDD

12

PQ311B

5

4

P3

8 7

5

1 2

PC302

BATT_OUT <57>

VIN

12

432K_0603_1%

12

PR329

PR329 10K_0402_1%

10K_0402_1%

34

SH00000AA00

1 2

PL301

1 2

PC303

10U_0805_25V6-K

PR323

1 2

316K_0402_1%

100K_0402_1%

PR334

10K_0402_1%

1 2

PACIN

12

PR335

12K_0402_1%

PL301

ADP_I<48,57>

100P_0603_50V8

PR325

1UH_PCMB061H-1R0MS_7A_20%

+3VALW

2N7002KDW-2N_SOT363-6

For disable pre-charge circuit.

4

PC313

1 2

PC304

12

PR302

0.01_1206_1%

1

2

1 2

PC309

1 2

10U_0805_25V6-K

1U_0603_25V6M

ACPRN<48>

PR338

@PR338

@

12

39.2K_0402_1%

6

ACDET

7

IOUT

8

SDA

BQ24737RGRR_VQFN20_3P5X3P5

9

SCL

10

ILIM

PR330

1 2

84.5K_0402_1%

2013-06-25

1

T_ACIN

3

B+

4

3

PC310

12

0.1U_0603_25V7K

12

PC312

0.1U_0603_25V7K

+3VALWP

@PR337

@

PR337

100K_0402_1%

PR339

@PR339

@ 1 2 1 2

4.7M_0603_1%

5

4

ACOK

CMPIN

PU301

12

PR336

3

CMPOUT

PR303

0_0402_5%

10K_0603_1%

@

PR304

12

ACP

ACN

1

2

ACP

ACN

PHASE

SA000051W00

PR327

10_0603_5%

LODRV

GND

15

14

SRN12BM

SRP

12

11

13

12

PR326

6.8_0603_5%

6.8_0603_5% PC320

PC320

0.1U_0603_25V7K

12

PC321

0.1U_0603_25V7K

TACIN@TACIN

@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

10_0402_1%

TP

VCC

HIDRV

BTST

REGN

DL_CHG

12

3

1 2

2013-05-09

PR310

1 2

10_0402_1%

PC110

1 2

@

100P_0402_50V8-J

21

20

BQ24727VCC-1

19

LX_CHG

18

DH_CHG

17

BST_CHG

16

12

PC322

0.1U_0603_25V7K

2012/07/01

1 2

PC306

PC305

4.7U_0805_25V6-K

P2

PR317

10_1206_5%

3.3_0603_5%

PD301

12

RB751V-40_SOD323-2

BQ24737_VDD

PC318

PC318 1U_0603_25V6M

1U_0603_25V6M

2013-05-16

1

PC308

1 2

2

PRFC32

PC307

4.7U_0805_25V6-K

1 2

PC314

1 2

1U_0603_25V6M

PR324

1 2

LC Future Center Secret Data

PRFC32

47P_0402_50V8-J

2200P_0402_25V7-K

DOCK_CONSUMP <42>

PQ312

SIS412DN-T1-GE3

12

PC315

0.047U_0603_25V7M

PQ314

SIS412DN-T1-GE3

Deciphered Date

2

AO4407AL_SO8

1 2 3 6

B+

PRFC33

68P_0402_50V8-J

3 5

241

3 5

241

4

1 2

PR307

10K_0402_1%

DISCHG_G-1

13

PQ308

LTC015EUBFS8TL_UMT3F

2014/07/01

2

PD302

2

12

24727_SN

12

PQ302

8 7

5

VIN

PR305

47K_0402_1%

1 2

ACOFF-1

1SS355_SOD323-2

1 2

PD303

PD303 1SS355_SOD323-2

1SS355_SOD323-2

10UH_PCMB104T-100MS_6A_20%

1 2

PR322

4.7_1206_5%

PC319

680P_0603_50V7K

PC319

680P_0603_50V7K

1 2

12

PC311

0.1U_0603_25V7K

PL302

Title

PWR-CHARGER-BQ24737

Size Document Number Rev

Custom

Date: Sheet

PR308

PR308 200K_0402_1%

200K_0402_1%

2013-04-18

61

PQ311A

2

2N7002KDW-2N_SOT363-6

PR320

0.01_1206_1%

1

CHG

2

SRP

Thursday, July 11, 2013

1

Only 14" need.

For EMC team request

PC330

PACIN

4

3

SRN

1 2

E440 NM-A151

E440 NM-A151E440 NM-A151

1

2013-06-24

B+ +5VALW

10P_0402_50V8-J

PC331

PC332

1

2

1

2

BATT+

1 2

PC317

PC316

10U_0805_25V6-K

58 69

of

10P_0402_50V8-J

1.0

5

D D

TPS51225_B+

PJ401

2

B+

PC401

C C

0.1U_0603_25V7K

+3VALWP

B B

112

JUMP_43X118@

12

PC403

0.1U_0603_25V7K

4.7UH +-20% PCMB063T-4R7MS 5.5A

1

+

PC414

PC414 150U_B2_6.3VM_R45M

150U_B2_6.3VM_R45M

2

12

PC405

4.7U_0805_25V6-K

PL401

1 2

PC404

4.7U_0805_25V6-K

12

PC406

2200P_0402_25V7-K

PR401

PC416

2013-05-16

1

2

PRFC34

47P_0402_50V8-J

12

4.7_1206_5%

SNUB_3V

12

680P_0603_50V7K

PQ401

PQ401 SIS412DN-T1-GE3

SIS412DN-T1-GE3

3 5

241

PQ403

PQ403 SIS412DN-T1-GE3

SIS412DN-T1-GE3

3 5

241

4

PC412

0.1U_0603_25V7K

1 2

TPS51225_B+

2013-04-18

EC_ON<48>

SPOK<57>

PR408

2.2_0603_5%

1 2

499K_0402_1%

1 2

@

BST_3V

UG_3V

LX_3V

LG_3V

PC420

0.1U_0603_25V7K

1 2

PR413

PR402

13K_0402_1%

PC411

0.1U_0402_25V6

1 2

PR404

20K_0402_1%

1 2

TPS51225_B+

PR406

100K_0402_1%

1 2

6

PGOOD

7

BOOT2

8

UGATE2

9

PHASE2

10

LGATE2

12

1 2

PR420

2.2K_0402_1%

2013-05-09

12

ENTRIP2

4

5

FB2

ENTRIP2

VIN11ENLDO12ENM

PC421

1U_0603_10V6K

PR414 71.5K_04021_1%PR414 71.5K_04021_1%12PR418 147K_0402_1%PR418 147K_0402_1%

3V5V TON

3

13

3

12

PR407

ENTRIP1

2

TON

14

12

PC419

1U_0603_10V5K

PC425

0.1U_0402_25V6

@

1 2

30K_0402_1%

1 2

20K_0402_1%

1 2

82K_0402_1%

FB_5V

1

FB1

GND

ENTRIP1

BYP1

BOOT1

UGATE1

PHASE1

LGATE1

LDO3

LDO5

15

2013-07-08

PR412

0_0603_5%

1 2

PR403

PR405

PU401

PU401 RT8243AZQW_WQFN20_3X3

RT8243AZQW_WQFN20_3X3

21

20

19

BST_5V

18

UG_5V

17

LX_5V

16

LG_5V

PR419

PR419 0_0603_5%~D

0_0603_5%~D

12

PC402

1U_0603_10V6K

VL

PR409

2.2_0603_5%

1 2

+3VL+3VLP

12

SIS412DN-T1-GE3

PC413

0.1U_0603_25V7K

1 2

SIS472DN-T1-GE3

2

PQ402

PQ404

1

PJ402

+3VALWP +3VALW

+5VALWP +5VALW

2013-05-16

1

12

PC410

2

PRFC35

47P_0402_50V8-J

0.1U_0402_25V6

3 5

241

12

PR410

4.7_1206_5%

3 5

12

241

PC417

680P_0603_50V7K

2

112

JUMP_43X118@

PJ403

2

112

JUMP_43X118@

TPS51225_B+

12

PC409

2200P_0402_25V7-K

PL402

1 2

2.2UH_PCMB063T-2R2MS_8A_20%

12

PC408

PC407

10U_0805_25V6-K

+5VALWP

2013-05-09

1

+

PC415

PC415 220U_B2_6.3VM_R25M

220U_B2_6.3VM_R25M

2

2013-05-14

MAINPWON<48,56,57>

PD401

1 2

RB751V-40_SOD323-2

PC426

1U_0402_6.3V6-K

12

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/07/01

LC Future Center Secret Data

Deciphered Date

2014/07/01

2

Title

PWR-3VALWP/5VALWP

Size Document Number Rev

Custom

Date: Sheet

Thursday, July 11, 2013

E440 NM-A151

E440 NM-A151E440 NM-A151

59 69

1

of

1.0

A

112

2013-05-16

1

12

PC519

2

PC519

PRFC36

68P_0402_50V8J

47P_0402_50V8-J

1 2

PL501

0.68UH_PCMB063T-R68MS_16A_+-20%

1

+

PC508

PC508 330U_D2_2V_R9M

330U_D2_2V_R9M

2

2013-05-09

B+_1.35V

12

PC504

PC505

PC502

PC503

0.1U_0402_25V6

2200P_0402_25V7-K

10U_0805_25V6-K

PQ501

PQ501 SIS472DN-T1-GE3

SIS472DN-T1-GE3

3 5

241

12

PR504

4.7_1206_5%

PQ502

3 5

SNB_1.35V

12

PC509

241

SISA12DN-T1-GE3

PR511

680P_0603_50V7K

PR511

VDDQ_PGOOD<48>

PJ501

2

B+

JUMP_43X79@

1 1

+1.35VP

2 2

SYSON<48>

SUSP<39,55,63>

3 3

+3VALW

1 2

100K_0402_1%

2013-07-08

PR501

0_0402_5%

1 2

49.9K_0402_1%

1 2

B

PR701

5.1_0603_5%

1 2

@PR505

@

PR505

47K_0402_5%

PR510

1 2

12

PC511

0.1U_0402_6.3V7-K

+5VALW

PC506

0.22U_0402_10V6-K

1 2

2013-05-09

PR503

6.19K +-1% 0402

1 2

PC701

PC701 1U_0603_10V6K

1U_0603_10V6K

PC501

0.1U_0402_16V7-K

13

D

2

G

S

PR502

2.2_0603_5%

1 2

15

DL_1.35V

14

13

CS_1.35V

12

+5VALW

11

VDD_1.35V

12

PC702

PC702 1U_0603_10V6K

1U_0603_10V6K

PR506

PR506 887K_0402_1%

887K_0402_1%

1 2

B+_1.35V

+5VALW

PR509

PR509 100K_0402_5%

100K_0402_5%

1 2

PQ503

PQ503 2N7002BKW_SOT323-3

2N7002BKW_SOT323-3

2013-04-18

DH_1.35V

LX_1.35V

16

17

PHASE

LGATE

PGND

CS

VDDP

VDD

UGATE

RT8207MZQW_WQFN20_3X3

PGOOD

TON

9

10

TON_1.35V

C

D

+1.35VP

+0.675VSP

PJ502

2

12

+1.35VP

+0.675VSP

BST_1.35V

18

20

19

PU501

21

VTT

BOOT

S5

8

S5_1.35V

PAD

VTTGND

VTTSNS

GND

VTTREF

VDDQ

FB

6

FB_1.35V

1

2

+0.675VSP

3

4

VTTREF_0.675V

5

+1.35VP

+1.35VP+5VALW

PR507

8.06K_0402_1%

1 2

PC510

1 2

@

470P_0402_50V7K

VLDOIN

S3

7

S3_1.35V

12

PC703

PC704

10U_0805_6.3V6-K

+1.35VP

12

PC507

0.033U_0402_16V7K

+1.35VP

2013-04-18

12

PR508

PR508 10K_0402_1%

10K_0402_1%

2013-07-01

JUMP_43X118

@

PJ503

2

JUMP_43X118@

PJ504

2

JUMP_43X39

@

112

+1.35V

+0.675VS+0.675VSP

4 4

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2012/07/01

LC Future Center Secret Data

Deciphered Date

C

2014/07/01

Title

PWR-+1.35VP/+0.675VSP

Size Document Number Rev

Custom

Date: Sheet

Thursday, July 11, 2013

E440 NM-A151

E440 NM-A151E440 NM-A151

D

60 69

of

1.0

5

4

3

2

1

D D

SUSP#<39,48,55,62>

PJ601

B+

2

JUMP_43X79

@

+3VS

2013-05-09

C C

2013-07-08

112

PR605

@

1 2

PR601

0_0402_5%

1 2

PR607

1M_0402_5%

12

PC606

10U_0805_25V6-K

0_0402_5%

1 2

12

PC604

0.1U_0402_25V6

12

PR608

100K_0402_5%

12

1 2

PC601

0.1U_0402_16V7-K

PR606

PR606 0_0402_5%

0_0402_5%

2013-05-09

PU601

SY8208DQNC_QFN10_3X3

8

IN

9

GND

3

ILMT

2

PG

EN

BS

LX

FB

BYP

LDO

1

6

BST 1.5VS

10

SW 1.5VS

4

7

5

PC605

12

PC607

4.7U_0402_6.3V6-M

+3VALW

PC602

0.1U_0603_25V7K

1 2

PL601

12

@

12

@

PL601

0.68UH_PCMB063T-R68MS_16A_+-20%

PR610

4.7_1206_5%

PC609

680P_0603_50V7K

12

+1.5VSP

1

2

PC610

PC612

22U_0805_6.3V6-M

12

PC611

PR603

30.1K_0402_1%

330P_0402_50V7-K

12

PR604

20K_0402_1%

1

2

PC614

PC613

22U_0805_6.3V6-M

@

PJ602

2

@

JUMP_43X118

112

+1.5VS+1.5VSP

B B

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2012/07/01

3

LC Future Center Secret Data

Deciphered Date

2014/07/01

2

Title

PWR-+1.5VSP

Size Document Number Rev

Custom

Date: Sheet

Thursday, July 11, 2013

E440 NM-A151

E440 NM-A151E440 NM-A151

1

61 69

of

1.0

5

PR708

0_0402_5%

SUSP#<39,48,55,61>

0_0402_5%

1 2

4

3

2

1

2013-07-08

D D

PJ603

B+

C C

PR831

2

@

JUMP_43X79

DGPU_PWROK <19,27,54,63>

10K_0402_5%

+3VS

12

PC713

0.1U_0402_16V7-K

24

+5VALW

PC706

PC707

47P_0402_50V8-J

PC706

.01U_0402_25V7-K

1 2

PR702

0_0402_5%

1

2

PRFC37

PR705

0_0402_5%

1 2

@

12

PC715

1U_0603_10V6K

68P_0402_50V8J

12

PC717

1U_0603_10V6K

12

PC710

10U_0805_25V6-K

12

PC709

PC708

0.1U_0402_25V6

2200P_0402_25V7-K

112

12

2013-05-16

12

VIN 1.05VS

23

GSNS

22

VSNS

21

SLEW

20

TRIP

19

GND1

18

V5

17

VIN3

16

VIN2

15

VIN1

14

PC705

1 2

0.1U_0402_6.3V7-K

26RA27EN28

25

REFIN

REFIN2

29

VREF

GND2

1

PGOOD

MODE

PGND510PGND411PGND312PGND213PGND1

PGOOD 1.05VS

2

LP#

3

4

NC

5

BST 1.05VS

BST

6

SW 1.05VS

SW1

7

SW2

8

SW3

9

SW4

TPS51363RVER_QFN28_3P5X4P5

TPS51363RVER_QFN28_3P5X4P5 PU701

PU701

+3VS

PR707

5.1_0603_5%

1 2

PR704

PR704 100K_0402_5%

100K_0402_5%

1 2

PC712

0.1U_0603_25V7K

1 2

PL701

12

@

12

680P_0603_50V7K

@

PL701

0.68UH_PCMB063T-R68MS_16A_+-20%

PR710

4.7_1206_5%

PC716

B+

1

+

PC711

2

68U_25V_M_R0.36

+1.05VS_VCCPP

1

2

PC719

1

2

PC726

PC727

22U_0805_6.3V6-M

PJ703

2

JUMP_43X118

@

112

+1.05VS+1.05VS_VCCPP

B B

PL702

PU702

4

IN

5

PG

FB6EN

SY8032ABC_SOT23-6

12

PC721

0.1U_0402_6.3V7-K

PC728

22U_0805_6.3V6-M

+5VALW

1

2

PR703

0_0402_5%

1 2

PC720

@

22U_0805_6.3V6-M

EN_1.8VSP

PR716

1M_0402_5%

@

1 2

4

+5VALW

1

2

SUSP#

2013-07-08

A A

5

3

1.8VSP_LX

LX

2

GND

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

12

PL702

1UH_PH041H-1R0MS_3.8A_20%

1 2

12

PR717

680P_0603_50V7K

2012/07/01

3

4.7_1206_5%

PC722

PR718

20K_0402_1%

PR719

10K_0402_1%

12

LC Future Center Secret Data

12

PC723

68P_0402_50V8J

Deciphered Date

+1.8VSP

1

PC725

PC724

2

PC725

2

22U_0805_6.3V6-M

2014/07/01

2

Title

PWR-+1.05VS_VCCPP/+1.8VSP

Size Document Number Rev

Custom

Date: Sheet

Thursday, July 11, 2013

PJ704

2

112

JUMP_43X39

@

E440 NM-A151

E440 NM-A151E440 NM-A151

1

+1.8VS+1.8VSP

of

62 69

1.0

A

+VGA_CORE

1 1

+VGA_CORE

PR833

3K_0402_1%

N14MGL@

PR833

39K_0402_1%

N14MGL@

PR834

2 2

Under VGA Core

12

PC834

PC835

4.7U_0603_6.3V6M

12

PC818

PC819

0.1U_0402_6.3V7-K

Near VGA Core

1

12

PC824

PC825

2

47U_0805_6.3V6M

22U_0805_6.3V6-M

PR832

30K_0402_1%

N14MGL@

12

PC836

4.7U_0603_6.3V6M

12

PC817

0.1U_0402_6.3V7-K

12

PC826

4.7U_0603_6.3V6M

PR844

3K_0402_1%

N14MGL@

PC837

4.7U_0603_6.3V6M

PC816

0.1U_0402_6.3V7-K

12

PC838

4.7U_0603_6.3V6M

12

PC827

4.7U_0603_6.3V6M

PR846

24K_0402_1%

N14MGL@

12

PC839

12

PC1216

4.7U_0603_6.3V6M

PRV11 = 71.5K ==>Fsw = 450KHz

PR859 0_0402_5%PR859 0_0402_5%

VSSSENSE_VGA<24>

VCCSENSE_VGA<24>

3 3

1 2

PC853

1000P_0402_50V7-K

1 2

PR865 0_0402_5%PR865 0_0402_5%

12

47P_0402_50V8-J

N14P-GT 35W Ipeak=50A Imax=35A Iocp=64.8A Fsw=450KHz bulk cap 330uF 9m *4

2011_1007 N13M-GE1 VID: 0110100

0.85V

PR818

PR818 0_0402_5%

4 4

DGPU_PWROK#<54>

SUSP<39,55,60>

A

SUSP

0_0402_5%

1 2

GB4-128 package

12

PC840

PC1209

4.7U_0603_6.3V6M

PC1217

4.7U_0603_6.3V6M

PC863

1 2

12

PC1218

1 2

PR854

10K_0402_1%

4.7U_0603_6.3V6M

12

PC1219

@

4.7U_0603_6.3V6M

PR844

0_0402_5%

N14PGV2@

PC855

1 2

0.01U_0603_50V7K

PR852

51_0402_1%

1 2

N14P-GS 25W Ipeak=36A Imax=25A Iocp=64.8A Fsw=450KHz bulk cap 330uF 9m *3

+5VALW

PC801

10U_0805_6.3V6-K

1 2

13

D

2

G

PR819

@PR819

@

S

0_0402_5%

S

12

PC1212

PC1210

12

4.7U_0603_6.3V6M

Thermistor near MOSFET trigger point 97 degree C.

PR814

PR814 20K_0402_1%

20K_0402_1%

2011_0727 PR816 modfiy 10K to 100K.

PQ808

PQ808 2N7002BKW_SOT323-3

2N7002BKW_SOT323-3

PC1212

PC1211

4.7U_0603_6.3V6M

12

PC1221

PC1220

@

4.7U_0603_6.3V6M

VREF

PR846

18K_0402_1%

12

N14PGV2@

1 2

PC854 2200P_0402_25V7-KPC854 2200P_0402_25V7-K

34K_0402_1%

PC843 10P_0402_50V8-JPC843 10P_0402_50V8-J

1 2

PC841

100P_0402_50V8J

+1.05VS +1.05VS_VGA

8 7

12

6 5

PR816

100K_0402_5%

1 2

2013-04-18

12

4.7U_0603_6.3V6M

PC1222

@

PR849

1 2

FB2_VGA

PC1213

4.7U_0603_6.3V6M

12

@

4.7U_0603_6.3V6M

N14PGV2@

PR832

20K_0402_1%

12

1 2

82K_0402_1%

12

PC1223

4

12

PR845

12

PC1214

PC1215

4.7U_0603_6.3V6M

PC2428

1

@

2

4.7U_0603_6.3V6M

N14PGV2@

PR833

20K_0402_1%

12

PR834

PR834 2K_0402_1%

2K_0402_1%

N14PGV2@

VREF

FS

FB_VGA

COMP_VGAFB1_VGA

PC865

0.1U_0402_6.3V7-K

1 2 3

PQ802TPC8A03-H_SO8PQ802TPC8A03-H_SO8

PC804

0.01U_0603_50V7K

B

4.7U_0603_6.3V6M

470P_0402_50V7K@PC2428

470P_0402_50V7K

2013-07-08

12

PC830

@

2200P_0402_25V7-K

1 2

PR835 0_0402_5%PR835 0_0402_5%

GPU_VID

12

VIDBUF

7

REFIN

8

VREF

9

NCP81172MNTWG_QFN24_4X4

FS

10

FBRTN

11

FB

12

COMP

GND

25

12

PH801

PR858 5.9K_0402_1%PR858 5.9K_0402_1%

100K_0402_1%_NCP15WF104F03RC

12

PC803

10U_0805_6.3V6-K

B

12

PD801

RB751V-40_SOD323-2

+3VS

2013-07-08

@

1 2

PR836 10K_0402_5%@PR836 10K_0402_5%

PR837 0_0402_5%PR837 0_0402_5%

UGATE1_VGA

PSI_VGA

EN_VGA

1

2EN3

4

5

6

PSI

VID

HG1

VIDBUF

TSNS13TALERT#14VCC15PGOOD16HG217BST2

12

VREF

12

PC810

1U_0603_10V6-K

BST1

PU801

VCC_VGA

1 2

PR840 10K_0402_5%PR840 10K_0402_5%

Confirm with HW

PH1

LG1

PGND

PVCC

LG2

PH2

18

PR853 2.2_0402_5%PR853 2.2_0402_5%

PC856

1U_0402_10V6K

+3VS

12

+1.05VS +1.05VS_VGA

PR813

PR813 75_0603_5%

75_0603_5%

1 2

13

D

PQ803

2

G

S

2N7002BKW_SOT323-3

2013-05-21

C

NVVDD_PWM_VID <23>

DPRSLPVR_VGA <23>

NVDD_PWR_EN <14>

12

PC802

PR864

1 2

27.4K_0402_1%

0.1U_0402_6.3V7-K

PR821

0_0603_5%

BOOT1_VGA

PHASE1_VGA

24

23

22

21

PVCC_VGA

20

19

BOOT2_VGA

DGPU_PWROK <19,27,54,62>

+5VS

12

BOOT1_2_VGA

LGATE1_VGA

PC809

0.22U_0603_10V7K

1 2

PC815

4.7U_0603_10V6

1 2

PR843 0_0402_5%PR843 0_0402_5%

2013-07-08

PR857

0_0603_5%

12

PHASE2_VGA

LGATE2_VGA

10K_0402_5%

+5VS

BOOT2_2_VGA

PR812

UGATE2_VGA

PC862

0.22U_0603_10V7K

1 2

MDU1512, Rdson(max)=5mohm

PJ802

2

112

@

JUMP_43X118

PR813, PQ803 and PR815 --> "Stuff"

PR815

0_0402_5%

1 2

DGPU_PWROK#DGPU_PWROK#

1 2

SUSP

PR817

@PR817

@

0_0402_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2012/07/01

C

5

PQ804

4

123

5

4

12

@

123

5

PQ806

4

123

5

4

123

LC Future Center Secret Data

Deciphered Date

SIR472DP-T1-GE3

PQ805

SIRA06DP-T1-GE3

PQ807

D

+VGA_B+

12

PC805

0.1U_0402_25V6

12

@

PR1212

SNUB1_VGA

12

PC1224

680P_0402_50V7-K

@

12

PC858

0.1U_0402_25V6

SIR472DP-T1-GE3

@

SIRA06DP-T1-GE3

@

12

PC806

2200P_0402_25V7-K

1

2

4.7_1206_5%

PC859

1 2

2200P_0402_25V7-K

12

PR1207

4.7_1206_5%

SNUB2_VGA

12

PC1225

680P_0402_50V7-K

2014/07/01

2013-05-16

12

PC807

10U_0805_25V6-K

12

PC860

1

2

PL802PL802

10U_0805_25V6-K

12

PC808

4

3

12

PL801PL801

PL1202

HCB2012KF-121T50_0805

1 2

PL1203

HCB2012KF-121T50_0805

1 2

1

2

PRFC38

47P_0402_50V8-J

47P_0402_50V8-J 10U_0805_25V6-K

10U_0805_25V6-K

+VGA_CORE

1

+

2

+VGA_B+

1

PC861

2

10U_0805_25V6-K

4

3

Title

PWR-VGA_COREP-ISL62883

Size Document Number Rev

C

Date: Sheet

PC811

2

330U_B2_2.5V_M_R9M

2013-05-16

PRFC39

47P_0402_50V8-J

1

+

2

Thursday, July 11, 2013

PC812

330U_B2_2.5V_M_R9M

1

+

PC866

2

330U_B2_2.5V_M_R9M

D

B+

+VGA_CORE

PC867

330U_B2_2.5V_M_R9M

E440 NM-A151

E440 NM-A151E440 NM-A151

63 69

of

1.0

5

D D

12

PH901

PR901

75K_0402_1%

1 2

Place close to phase 1 inductir

C C

PC914

390P_0402_50V7-K

1 2

PR920

49.9_0402_1%

1 2

PR921

1K_0402_1%

1 2

PR922

0_0402_5%

B B

VSSSENSE<10,9>

VCCSENSE<9>

0_0402_5%

1 2

PR923

0_0402_5%

1 2

PC915

1000P_0402_50V7-K

220K_0402_5%_ERTJ0EV224J

1K_0402_1%

PC913

10P_0402_50V8-J

1 2

37W=10K 47W=7.5K

1 2

PR919

10K_0402_1%

VSP

+5VALW

PR918

+VCCIO_OUT

PR933

PR934

75_0402_1%

130_0402_1%

1 2

PR937

PR937 0_0402_5%

0_0402_5%

2013-07-08

1 2

PR936

PR936 0_0402_5%

0_0402_5%

PR935

A A

VR_SVID_DAT<9>

VR_SVID_ALRT#<9>

VR_SVID_CLK<9>

5

PR935 0_0402_5%

0_0402_5%

1 2

4

PR902

165K_0402_1%

1 2

CPU_B+

1 2

12

PC912

1 2

PR924

1K_0402_5%

1 2

PC916

2200P_0402_25V7-K

1 2

PR925

2_0603_5%

PR932

54.9_0402_1%

1 2

VR_SVID_DAT_1

VR_SVID_ALRT#_1

VR_SVID_CLK_1

4

PC901

2013-07-08

PR912

23.7K_0402_1%

1 2

PC911

470P_0402_50V7-K

12

.01U_0402_25V7-K

PC917

1 2

2.2U_0603_10V7-K

1 2

1200P_0402_50V7-K

PR952

0_0402_5%

VSN_2VSN_1

VR_ON<48>

VR_HOT#<48,56,57>

1 2

PC902

1 2

470P_0402_50V7-K

IMVP_IMON

12

37W=10K 47W=15.4K

PR917

10K_0402_1%

1 2

PC918

0.1U_0402_6.3V7-K

<48>

CSCOMP

28

ILIM

29

IOUT

30

VRMP

31

COMP

32

FB

33

DIFFOUT

34

VSN

35

VSP

36

VCC

37

GND

PR926

PR926 0_0402_5%

0_0402_5%

1 2

PR927

PR927 0_0402_5%

0_0402_5%

2013-07-08

3

PR903

162K_0402_1%

1 2

PC903

1 2

1000P_0402_50V7-K

CSP3

CSP2

CSP1

CSSUM

DRON

81103_PWM

PU901

24

19

22

21

23

20

NCP81103MNTWG_QFN36_5X5

BST3

CSP3

CSP1

CSP2

DRON

CSREF

PWM2/IMAX

PVCC

PGND

VR_RDY

TSENSE

INT_SEL

5

6

8

9

TSENSE

VR_RDY

VR_SVID_ALRT#_1

VR_SVID_CLK_1

PR929

52.3K_0402_1%

1 2

12

PR930

1.91K_0402_1%

+3VS

VGATE

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2013-07-08

<15>

27

26

CSSUM

CSCOMP

EN1VRHOT#2SDIO3ALERT#4ROSC7SCLK

VR_HOT#_1

PR931

25

VR_SVID_DAT_1

0_0402_5%

PR905

162K_0402_1%

1 2

PR906

43K_0402_1%

1 2

18

HG3

17

SW3

16

LG3

15 14 13

LG1

12

SW1

11

HG1

10

BST1

PR928

45.3K_0402_1%

1 2

PC910

0.1U_0402_6.3V7-K

1 2

3

SWN3

SWN1

CSREF <65>

1

T138 @T138 @

T137 @T137 @

2012/12/05

37W=43K 47W=66.5K

PR915

2.2_0603_5%

1 2

HG3 <65>

LG3 <65>

LG1 <65>

HG1 <65>

PR916

2.2_0603_5%

1 2

TSENSE

1 2

CSREF

CSP3

CSREF

CSP1

PC907

0.22U_0402_10V6-K

1 2

PC908

1 2

2.2U_0603_10V7-K

PC909

0.22U_0402_10V6-K

1 2

12

PR938

PH802

15K_0402_1%

100K_0402_1%_NCP15WF104F03RC

LC Future Center Secret Data

Deciphered Date

2

12

PC904

PR907

1 2

0.047U_0402_25V7-K

12

PC906

PR909

@

1 2

0.047U_0402_25V7-K

SW3 <65>

PR951

PR951 0_0402_5%

0_0402_5%

1 2

SW1 <65>

Place close to phase 2 MOSFET

2014/12/05

2

20K_0402_1%

PR910

6.65K_0402_1%

12

PR913

6.65K_0402_1%

12

2013-07-08

+5VALW

1

SWN3 <65>

SWN1 <65>

+5VALW

2013-07-08

12

PR914

PR914 0_0402_5%

0_0402_5%

CSP2

Mount for 37W

Title

CPU_CORE

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

E440 NM-A151

E440 NM-A151E440 NM-A151

64 69

1

of

1.0

5

D D

4

3

2

1

2013-05-16

5

PQ1001

PR939

2.2_0603_1%

12

HG1<64>

SW1<64>

LG1<64>

C C

B B

4

SIR472DP-T1-GE3

123

PQ1002

SIRA06DP-T1-GE3

12

SNUB_CPU1

12

5

4

123

CPU_B+

1

2

12

PC920

PRFC40

PR940

4.7_1206_5%

PC919

680P_0402_50V7-K

PC920

10U_0805_25V6-K

47P_0402_50V8-J

10U_0805_25V6-K

PL902

0.36UH +-20% PCME103T-R36MSR 33A

1

2

1 2

PL901

FBMA-L11-453215-800LMA90T_1812

12

PC921

10U_0805_25V6-K

12

PC922

PC923

10U_0805_25V6-K

0.1U_0402_25V6-K

PC924

2200P_0402_25V7-K

FBMA-L11-453215-800LMA90T_1812

B+

+VCC_CORE

4

3

V1N_CPU

PR941

PR941 10_0402_1%

10_0402_1%

12

PC925

PC926

12

CSREF <64>

SWN1 <64>

68P_0402_50V8-J

220P_0402_50V7-K

@

HG3<64>

SW3<64>

LG3<64>

PR942

2.2_0603_1%

12

PQ1003

5

4

123

5

4

123

SIR472DP-T1-GE3

PQ1004

SIRA06DP-T1-GE3

12

PC927

PC928

10U_0805_25V6-K

12

SNUB_CPU3

12

CPU_B+

12

PC931

PC930

PC929

10U_0805_25V6-K

0.1U_0402_25V6-K

0.1U_0402_25V6-K 2200P_0402_25V7-K

2200P_0402_25V7-K

PL903

0.36UH +-20% PCME103T-R36MSR 33A

1

2

PR943

4.7_1206_5%

PC935

680P_0402_50V7-K

2013-05-16

1

+

2

1

+

PC933

PC932

2

PRFC41

47P_0402_50V8-J

68U_25V_M_R0.36

+VCC_CORE

4

3

PR944

12

V3N_CPU

10_0402_1%

CSREF

SWN3 <64>

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/12/05

LC Future Center Secret Data

Deciphered Date

2

2014/12/05

Title

CPU_CORE

Size Document Number Rev

Thursday, July 11, 2013

Date: Sheet

E440 NM-A151

E440 NM-A151E440 NM-A151

1

65 69

of

1.0

5

4

3

2

1

+VCC_CORE

D D

+VCC_CORE

1

PC1001

10U_0805_6.3V6-K

2

1

PC1011

10U_0805_6.3V6-K

2

1

PC1002

10U_0805_6.3V6-K

2

1

PC1010

10U_0805_6.3V6-K

2

1

PC1003

10U_0805_6.3V6-K

2

1

PC1009

10U_0805_6.3V6-K

2

1

PC1004

10U_0805_6.3V6-K

2

1

PC1008

10U_0805_6.3V6-K

2

1

PC1005

10U_0805_6.3V6-K

2

1

PC1007

10U_0805_6.3V6-K

2

1

PC1006

10U_0805_6.3V6-K

2

1

+

PC1030

330U_D2_2VM_R9M

2

1

+

PC1034

330U_D2_2VM_R9M

2

1

+

PC1031

330U_D2_2VM_R9M

2

@

1

+

PC1035

330U_D2_2VM_R9M

2

@

1

+

PC1032

330U_D2_2VM_R9M

2

1

+

PC1033

330U_D2_2VM_R9M

2

+VCC_CORE

1

PC1016

22U_0805_6.3V6-M

C C

B B

2

1

PC1017

22U_0805_6.3V6-M

2

1

PC1026

22U_0805_6.3V6-M

2

1

PC1027

22U_0805_6.3V6-M

2

1

PC1015

22U_0805_6.3V6-M

2

1

PC1018

22U_0805_6.3V6-M

2

1

PC1025

22U_0805_6.3V6-M

2

1

PC1028

22U_0805_6.3V6-M

2

1

PC1014

22U_0805_6.3V6-M

2

1

PC1019

22U_0805_6.3V6-M

2

1

PC1024

22U_0805_6.3V6-M

2

1

PC1029

22U_0805_6.3V6-M

2

1

PC1013

22U_0805_6.3V6-M

2

1

PC1020

22U_0805_6.3V6-M

2

1

PC1023

22U_0805_6.3V6-M

2

1

PC1036

22U_0805_6.3V6-M

2

1

PC1012

22U_0805_6.3V6-M

2

1

PC1021

22U_0805_6.3V6-M

2

1

PC1022

22U_0805_6.3V6-M

2

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2012/07/01

3

LC Future Center Secret Data

Deciphered Date

2014/07/01

2

Title

PWR-PROCESSOR DECOUPLING

Size Document Number Rev

Custom

Date: Sheet

Thursday, July 11, 2013

E440 NM-A151

E440 NM-A151E440 NM-A151

1

66 69

of

1.0

A

B

C

D

1 1

PJ1202

2

JUMP_43X39

@

1.05VMP max current=1A

PJ1201

+5VALW

VM_PWRON<48,53>

2 2

2

JUMP_43X39

@

112

2013-07-08

@

PR1203

0_0402_5%

1 2

1

PC1207

2

22U_0805_6.3V6-M

EN_1.05VMP

2011_0923 JUMP form 43X79 change to 43X79

1

PC1201

2

PR1204

1M_0402_5%

1.05VMP_VIN

22U_0805_6.3V6-M

1 2

PU1201

4

IN

5

PG

FB6EN

SY8032ABC_SOT23-6

12

PC1206

0.1U_0402_6.3V7-K

GND

3

LX

2

1

1.05VMP_LX

FB=0.6Volt

PL1201

1UH_PH041H-1R0MS_3.8A_20%

1 2

12

PR1202

7.5K_0402_1%

PR1201

4.7_1206_5%

12

PC1203

680P_0603_50V7K

1.05VMP_FB

PR1205

10K_0402_1%

12

+1.05VMP

12

PC1202

1

68P_0402_50V8J

12

1

PC1204

PC1205

2

PC1205

2

22U_0805_6.3V6-M

112

2013-05-16

1

2

PRFC55

47P_0402_50V8-J

+1.05VM+1.05VMP

1

2

PRFC56

47P_0402_50V8-J

3 3

4 4

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2012/07/01

LC Future Center Secret Data

Deciphered Date

C

2014/07/01

Title

PWR-+1.05VMP

Size Document Number Rev

Custom

Date: Sheet

Thursday, July 11, 2013

E440 NM-A151

E440 NM-A151E440 NM-A151

D

67 69

of

1.0

5

4

3

2

1

POWER PIR (Product Improve Record)

AILE1 NM-A151 SCHEMATIC CHANGE LIST REVISION CHANGE: 0.1 GERBER-OUT DATE: 2013/01/16

NO DATE PAGE MODIFICATION LIST PURPOSE

---------------------------------------------------------------------------------------------------------------------

B+

D D

Adaptor

C C

TI

BQ24737RGRR

Battery Charger

Switch Mode

PAGE 58

B+

RICHTEK

+5VALW/8A

RT8243AZQW

EC_ON

WQFN20_3X3

Switch Mode

EN1

FOR System

EN2

PAGE 59

PGOOD

VREG5

VREG3

+3VALW/6A

SPOK

VL

+3VLP

SUSP#

RICHTEK

RT8068AZQW

WDFN10_3X3

EN

converter

PAGE 62

RICHTEK

+1.8VSP/2A

PGOOD

+1.05VMP/2A

RT8068AZQW

SYSON

SUSP#

RICHTEK

RT8207MZQW WQFN20_3X3

Switch Mode

S5

FOR DDR3/3L

S3

PAGE 60

PGOOD

+1.35VP/12A

+0.675VSP/2A

VDDQ_PGOOD

VM_PWRON

WDFN10_3X3

EN

converter

PAGE 67

PGOOD

TI

TPS51212DSCR

+1.5V/8A

SON10_3X3

Switch Mode

FOR FCH

SUSP#

EN

PAGE 61

PGOOD

TI

SMBus

TPS51212DSCR

SON10_3X3

+1.05VS_VCCPP/10A

Switch Mode

FOR FCH

B B

SUSP#

Battery

Li-ion

EN

PAGE 62

ONSEMI

NCP81172MNTWG_ QFN24_4X4

NVVDD_PWM_VID

NVDD_PWR_EN

VIDs

Switch Mode

EN

FOR GPU VDDC

PAGE 63

PGOOD

+VGA_CORE/40A

DGPU_PWROK

ONSEMI

NCP81103MNTWG

QFN36_5X5

+CPU_CORE/56A

Switch Mode

A A

5

4

VR_ON

FOR CPU Core

EN PGOOD

PAGE 64

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/12/05

VGATE

LC Future Center Secret Data

Deciphered Date

2

2014/12/05

Title

HW-PIR

Size Document Number Rev

Custom

Thursday, July 11, 2013

Date: Sheet

Thursday, July 11, 2013

E440 NM-A151

E440 NM-A151E440 NM-A151

1

68 69

of

1.0

5

4

3

2

1

HW PIR (Product Improve Record)

AILE1 NM-A151 SCHEMATIC CHANGE LIST REVISION CHANGE: 0.1 GERBER-OUT DATE: 2013/01/16

NO DATE PAGE MODIFICATION LIST PURPOSE

D D

---------------------------------------------------------------------------------------------------------------------

01) 03/14 10 R64 Change R64 BOM structure from "@" to "DS3@" For Deep S3 Function

C C

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/12/05 2014/12/05

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PIR (PWR)

Y490-LA8691P

69 69Thursday, July 11, 2013

1

1.0

of

Lenovo ThinkPad E440 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual