Lenovo miix700-12isk Schematic
A
1 1
B
C
D
E
LCFC Confidential
2 2
Chelsea -SKY M/B Schematics Document
INTEL SKYLAKE Mobile ULT Platform
INTEL SKY Y-series CPU + LPDDR3 Memory
2015-08-13
REV:1.0
3 3
4 4
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.
C
2014/11/15
2014/11/15
2014/11/15
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
2013/11/08
2013/11/08
2013/11/08
Title
Cover Page
Cover Page
Cover Page
Size
Size
Size
Document Number Rev
Document Number Rev
Document Number Rev
C
C
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
Monday, August 17, 2015
Monday, August 17, 2015
Monday, August 17, 2015
Miix4
Miix4
Miix4
E
1 37
1 37
1 37
1.0
1.0
1.0
5
4
3
2
1
D D
Micro SIM Conn
C C
SPK Conn.
(1W x 2)
Array D-MIC Conn.
Audio Combo Conn.
iphone type
Flash LED
Rear Camera Conn
B B
I2C
LCFC-Chelsea Refresh Block diagram
Micro HDMI Conn.
eDP Conn.
NGFF SSD
NGFF WWAN
Internal GPS/GNSS
NGFF Wlan&BT
Codec ALC3240
Front Camera Conn
Camera PMIC
TPS6847 0A
DDI-Port1
eDP-Port[0:3]
SATA Gen3 Port 1
USB20-Port5+I2C
PCIe Port3
USB20-Port6
HD Audio
CSI2+I2C
I2C
CSI2
Intel Skylake-Y Platform
20*16.5*0.91
BGA 1515
LPC BUS
EC
IT85 86VG-AX _VFBGA1 28
Memory BUS-ChannelA&B
1.2V LPDDR3 1866MT/S
USB 2.0-Port1
USB 3.0-Port1
USB 3.0-Port4
G-Sensor
BMA222E
DC_IN Combo USB
Docking Conn
Cardreader
USB 2.0-Port2
USB20-Port3
PCIE-Port4
I2C
SPI BUS
I2C
SMBUS
3D Camera
BH611FJ1LN
Touch Screen
SPI ROM
(8MB)
ALS
AL3010
Battery
LPDDR3-1866
16Gbx3 2
USB30
Micro SD Conn
Sub-board
ReservedReserved
I2C
G-Sensor
BMA222E
Hall Sensor
Thermal Sensor
F75303M
Flash LED FPC
ALS
AL3010
I2C
A A
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.
3
2014/11/15
2014/11/15
2014/11/15
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2013/11/08
2013/11/08
2013/11/08
Title
Block Diagram
Block Diagram
Block Diagram
Size
Size
Size
Document Number Rev
Document Number Rev
Document Number Rev
C
C
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
Monday, August 17, 2015
Monday, August 17, 2015
Monday, August 17, 2015
Miix4
Miix4
Miix4
1
2 37
2 37
2 37
1.0
1.0
1.0
Voltage Rails
A
Power Plane
B+
+3VL
State
1 1
+5VLP
OS0O O O
S3
DS3
S5 S4/AC Only
S5 S4
Battery only
S5 S4
AC & Battery
2 2
don't exist
STATE SLP_S3#SLP_S1#
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
DS3 (Suspend to RAM) ON OFF OFFLOW LOW HIGH LOW
S4 (Suspend to Disk) ON
S5 (Soft OFF)
O O X
O O X X
O
SIGNAL
LOW
LOW HIGH
LOW
LOW LOW
, X --> Means OFF )( O --> Means ON
+3VAL W
+5VAL W
+3VALW_PCH
+1.0VA LW
+1.8VA LW
+CPU_VCCPRIM
O
O
X
O
O
X
XX
X
SLP_S4# +VS+V
+VALW
HIGHHIGHHIGH
HIGH HIGH
LOW
LOW LOW
ON
ON
ON
ON
ON
LOW OFF
ON
+DDR_1.2V
+DDR_1.8V
OO O X
XX
X
+VALW_ PCH
ONONON
ONONON
ON
OFF
B
+5VS
+3VS
+1.8VS
+DDR_0.6VS
+CPU_CORE
+CPU_VCCIO
+CPU_VCCGT
+CPU_VCCSA
X
X
ON
OFF OFF
OFF
OFF
Clock
ONON
LOW
OFF
OFF
BOM Structure Table
C
BOM Structure
TI@
TI MIPI camera mount
TPM@ TPM module
DEBUG@ DEBUG CARD Part
ME@ ME part(connector, hole)
RF@
RF request
EMC@
EMC request
CD@ COST DOWN Part
REV@ RESERVER Part
BOM Configuration Table
SKU Description
SKU1
SKU2
X76&VGA Configuration Table
SKU Description
BOM Structure
MIRROR@ EC Mirror-code enable
EC Mirror-code disableUNMIRROR@
DA8@ PCB
UPI@ UPI MIPI camera mount
D
Board ID Table
DescriptionBoard ID
E
PCB Revision
BOM Config
BOM Config
SMBUS Control Table
Sensor
3 3
EC_SMB_CLK1
EC_SMB_DAT1
EC_SMB_CLK3
EC_SMB_DAT3
EC_SMB_CLK0
EC_SMB_DAT0 +3VS
SOURCE
IT8586
+3VALW_EC
IT8586
+3VS
IT8586
+3VS
X
V
X
SM Bus address
addre ss
Device
Battery
EC1
Charger
4 4
Sensor
EC3
ALS
Thermal Sensor
EC0
PCH THM
TP
PCH
0001 011X b
1001_100xb
A
BATTALS Thermal
V
X
V
X
+3VS
X
X
PCIE PORT LIST
Devic ePort
1
2
WLAN
3
CR
4
5
Sensor
X
X
V
+3VS
charger
V
X
X
USB Port Table
USB20 USB30
USB
1
BT
EXHCI/ XHCI
2
EC
3
DC in combine
5
POGO USB
7
WWAN
9
B
1
2
3
4
USB
WWAN
X
3D camera
PCB And LOGO Config
PCB
ZZZ9
M3@
PCB 10K NM-A641 REV0 M/B
ZZZ16
CPU
SR2EN
ZZZ6
HY8G@ ZZZ7
VRAM
HYNIX 8G
Security Classification
Security Classification
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.
C
ZZZ3
SR2EM
MICRON8G
Issued Date
Issued Date
Issued Date
ZZZ15
NUVOTON@
S IC NPCT650LAAWX TSSOP 28P TPM
ZZZ17
MIC8G@
M7@
SR2EM
ZZZ8
SAMSUNG 8G
SAM8G@ ZZZ12
2014/11/15
2014/11/15
2014/11/15
ZZZ13
HY4G@
MICRON 4G
HYNIX 4G
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
MIC4G@
ZZZ14
SAM4G@
SAMSUNG 4G
Title
Title
2013/11/08
2013/11/08
2013/11/08
D
Title
Size
Size
Size
Document Number Rev
Document Number Rev
Document Number Rev
C
C
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
M5@
ZZZ4
Notes List
Notes List
Notes List
Monday, August 17, 2015
Monday, August 17, 2015
Monday, August 17, 2015
HDMI@
HDMI LOGO
LOGO
Miix4
Miix4
Miix4
E
3 37
3 37
3 37
1.0
1.0
1.0
5
D D
C C
B B
4
UC1A
CPU_HDMI_TX2-18
CPU_HDMI_TX2+18
CPU_HDMI_TX1-18
CPU_HDMI_TX1+18
CPU_HDMI_TX0-18
CPU_HDMI_TX0+18
CPU_HDMI_CLK-18
CPU_HDMI_CLK+18
HDMI_DDC_CLK18
HDMI_DDC_DATA18
TC171@
A46
DDI1_TXN[0]
C46
DDI1_TXP[0]
C48
DDI1_TXN[1]
A48
DDI1_TXP[1]
B45
DDI1_TXN[2]
D45
DDI1_TXP[2]
B47
DDI1_TXN[3]
D47
DDI1_TXP[3]
A42
DDI2_TXN[0]
C42
DDI2_TXP[0]
A44
DDI2_TXN[1]
C44
DDI2_TXP[1]
B41
DDI2_TXN[2]
D41
DDI2_TXP[2]
B43
DDI2_TXN[3]
D43
DDI2_TXP[3]
L6
GPP_E18/DDPB_CTRLCLK
H6
GPP_E19/DDPB_CTRLDATA
H4
1
GPP_E20/DDPC_CTRLCLK
F4
GPP_E21/DDPC_CTRLDATA
M5
GPP_E22
L4
GPP_E23
A50
eDP_RCOMP
SKYLAKE-Y_FCBGA1515
REV = 1 ?
@
DDI
DISPLAY SIDEBANDS
SKYLAKE_ULX
DISPLAY
3
?
eDP
GPP_E13/DDPB_HPD0
GPP_E14/DDPC_HPD1
GPP_E15/DDPD_HPD2
GPP_E16/DDPE_HPD3
1 OF 20
EDP_TXN[0]
EDP_TXP[0]
EDP_TXN[1]
EDP_TXP[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]
EDP_AUXN
EDP_AUXP
EDP_DISP_UTIL
DDI1_AUXN
DDI1_AUXP
DDI2_AUXN
DDI2_AUXP
GPP_E17/EDP_HPD
eDP_BKLEN
eDP_BKLCTL
eDP_VDDEN
H45
F45
J44
G44
J46
G46
H43
F43
J42
G42
EDP_DISP_ULT
A40
H41
F41
J40
G40
PCH_HDMI_HPD
C11
L10
M7
F6
A7
D4
PCH_BKLT_CTRL
B6
PCH_LCD_VDDENEDP_COMP
D3
RC3026
1 2
@
2
CPU_EDP_TX0- 17
CPU_EDP_TX0+ 17
CPU_EDP_TX1- 17
CPU_EDP_TX1+ 17
CPU_EDP_TX2- 17
CPU_EDP_TX2+ 17
CPU_EDP_TX3- 17
CPU_EDP_TX3+ 17
CPU_EDP_AUX- 17
CPU_EDP_AUX+ 17
1
@
TC166
PCH_HDMI_HPD 18
0_0402_5%
PCH_EDP_HPD 17
PCH_BKLT_EN 17,25
PCH_BKLT_CTRL 17
PCH_LCD_VDDEN 17
EC_SCI# 9,25
1
DDP*_CTRLDATA
This signal has a weak internal pull-down.
0 = Port B is not detected.
1 = Port B is detected.
*
pull up at HDMI side.
24.9_0402_1%
EDP_COMP
+VCCIOA_OUT & EDP_COMP :
Trace Width: 20mil
Space: 25mil
Max length: 100mil
RC4
1 2
+CPU_VCCIO
A A
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.
3
2014/11/15
2014/11/15
2014/11/15
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2013/08/05
2013/08/05
2013/08/05
Title
MCP (DDI,EDP)
MCP (DDI,EDP)
MCP (DDI,EDP)
Size
Size
Size
Document Number Rev
Document Number Rev
Document Number Rev
C
C
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
Monday, August 17, 2015
Monday, August 17, 2015
Monday, August 17, 2015
Miix4
Miix4
Miix4
1
4 37
4 37
4 37
1.0
1.0
1.0
5
4
3
2
1
+CPU_VCCSTG
CPU_PROCHOT#
12
RC19 1K_0402_1%
+CPU_VCCST
D D
12
RC143 1K_0402_1%
THRMTRIP#
130 degree output ,for breakpoint and performance monitor signal
TPM_ID1 Description
0
NO physical TPM
CPU_PECI25
CPU_PROCHOT#
CPU_PROCHOT#25
1 2
RC20 499_0402_1%
1 2
RC57 0_0402_5%
1 2
RC155 49.9_0402_1%
1 2
RC156 49.9_0402_1%
TC15 @
TC11 @
TC12 @
TC13 @
TC14 @
1
1
1
1
1
CATERR#
PROCHOT#
THRMTRIP#
SKTOCC#
XDP_BPM0#
XDP_BPM1#
XDP_BPM2#
XDP_BPM3#
TPM_ID1
TPM_ID2
1 physical TPM
H49
F49
J48
H47
B62
H51
J50
F51
G50
E11
M9
BD8
BC11
BN17
BP16
CATERR#
PECI
PROCHOT#
THERMTRIP#
SKTOCC#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
GPP_E3/CPU_GP0
GPP_E7/CPU_GP1
GPP_B3/CPU_GP2
GPP_B4/CPU_GP3
PROC_POPIRCOMP
PCH_OPIRCOMP
@
UC1D
SKYLAKE-Y_FCBGA1515
CPU MISC
SKYLAKE_ULX
?
JTAG
PCH_JTAG_TCK
PCH_JTAG_TDO
PCH_JTAG_TMS
4 OF 20
PROC_TCK
PROC_TDI
PROC_TDO
PROC_TMS
PROC_TRST#
PCH_JTAG_TDI
PCH_TRST#
JTAGX
?REV = 1
D53
C54
G48
C59
F47
B53
C50
B51
A52
C52
B49
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
PCH_JTAG_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
XDP_TCK
For Boundary Scan
Debug Port DG
Merged MCP XDP-SFF-26Pin Connector Pinout
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TCK
PCH_JTAG_TCK
XDP_TRST#
12
RC1546 51_0402_5%
12
RC1543 51_0402_5%
12
RC1547 51_0402_5%
1 2
RC1551 51_0402_5%
1 2
@
RC1552 51_0402_5%
1 2
@
RC1553 51_0402_5%
+CPU_VCCSTG
TPM_ID2 Description
0
NATIONZ TPM
1 NUVOTON TPM
C C
TPM@
TPM_ID1
TPM_ID2
UNTPM@
B B
+3VS
1 2
1 2
@
10K_0402_5%
10K_0402_5%
RC3029
RC3031
1 2
1 2
@
10K_0402_5%
10K_0402_5%
RC3030
RC3032
A A
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.
3
2014/11/15
2014/11/15
2014/11/15
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2013/08/05
2013/08/05
2013/08/05
Title
MCP (XDP,JATG)
MCP (XDP,JATG)
MCP (XDP,JATG)
Size
Size
Size
Document Number Rev
Document Number Rev
Document Number Rev
C
C
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
Tuesday, August 18, 2015
Tuesday, August 18, 2015
Tuesday, August 18, 2015
Miix4
Miix4
Miix4
1
5 37
5 37
5 37
1.0
1.0
1.0
5
15
16
DDRA_DQS#[0..7]
DDRA_DQS[0..7]15
DDRB_DQS#[0..7]
DDRB_DQS[0..7]16
DDRA_DQ[0..7]15
D D
DDRA_DQ[8..15]15
DDRA_DQ[16..23]15
DDRA_DQ[24..31]15
DDRA_DQ[32..39]15
DDRA_DQ[40..47]15
C C
DDRA_DQ[48..55]15
DDRA_DQ[56..63]15
DDRA_DQS#[0..7]
DDRA_DQS[0..7]
DDRB_DQS#[0..7]
DDRB_DQS[0..7]
DDRA_DQ0
DDRA_DQ1
DDRA_DQ2
DDRA_DQ3
DDRA_DQ4
DDRA_DQ5
DDRA_DQ6
DDRA_DQ7
DDRA_DQ8
DDRA_DQ9
DDRA_DQ10
DDRA_DQ11
DDRA_DQ12
DDRA_DQ13
DDRA_DQ14
DDRA_DQ15
DDRA_DQ16
DDRA_DQ17
DDRA_DQ18
DDRA_DQ19
DDRA_DQ20
DDRA_DQ21
DDRA_DQ22
DDRA_DQ23
DDRA_DQ24
DDRA_DQ25
DDRA_DQ26
DDRA_DQ27
DDRA_DQ28
DDRA_DQ29
DDRA_DQ30
DDRA_DQ31
DDRA_DQ32
DDRA_DQ33
DDRA_DQ34
DDRA_DQ35
DDRA_DQ36
DDRA_DQ37
DDRA_DQ38
DDRA_DQ39
DDRA_DQ40
DDRA_DQ41
DDRA_DQ42
DDRA_DQ43
DDRA_DQ44
DDRA_DQ45
DDRA_DQ46
DDRA_DQ47
DDRA_DQ48
DDRA_DQ49
DDRA_DQ50
DDRA_DQ51
DDRA_DQ52
DDRA_DQ53
DDRA_DQ54
DDRA_DQ55
DDRA_DQ56
DDRA_DQ57
DDRA_DQ58
DDRA_DQ59
DDRA_DQ60
DDRA_DQ61
DDRA_DQ62
DDRA_DQ63
UC1B
AG61
DDR0_DQ[0]
AH60
DDR0_DQ[1]
AK62
DDR0_DQ[2]
AK60
DDR0_DQ[3]
AH62
DDR0_DQ[4]
AG63
DDR0_DQ[5]
AL61
DDR0_DQ[6]
AL63
DDR0_DQ[7]
AM60
DDR0_DQ[8]
AM62
DDR0_DQ[9]
AT60
DDR0_DQ[10]
AR61
DDR0_DQ[11]
AN61
DDR0_DQ[12]
AN63
DDR0_DQ[13]
AR63
DDR0_DQ[14]
AT62
DDR0_DQ[15]
AT56
DDR1_DQ[0]/DDR0_DQ[16]
AR55
DDR1_DQ[1]/DDR0_DQ[17]
AN57
DDR1_DQ[2]/DDR0_DQ[18]
AN55
DDR1_DQ[3]/DDR0_DQ[19]
AR57
DDR1_DQ[4]/DDR0_DQ[20]
AT58
DDR1_DQ[5]/DDR0_DQ[21]
AM58
DDR1_DQ[6]/DDR0_DQ[22]
AM56
DDR1_DQ[7]/DDR0_DQ[23]
AL55
DDR1_DQ[8]/DDR0_DQ[24]
AL57
DDR1_DQ[9]/DDR0_DQ[25]
AH58
DDR1_DQ[10]/DDR0_DQ[26]
AH56
DDR1_DQ[11]/DDR0_DQ[27]
AK58
DDR1_DQ[12]/DDR0_DQ[28]
AK56
DDR1_DQ[13]/DDR0_DQ[29]
AG55
DDR1_DQ[14]/DDR0_DQ[30]
AG57
DDR1_DQ[15]/DDR0_DQ[31]
BE55
DDR0_DQ[16]/DDR0_DQ[32]
BC55
DDR0_DQ[17]/DDR0_DQ[33]
BG53
DDR0_DQ[18]/DDR0_DQ[34]
BE53
DDR0_DQ[19]/DDR0_DQ[35]
BC53
DDR0_DQ[20]/DDR0_DQ[36]
BG55
DDR0_DQ[21]/DDR0_DQ[37]
BD52
DDR0_DQ[22]/DDR0_DQ[38]
BF52
DDR0_DQ[23]/DDR0_DQ[39]
BC51
DDR0_DQ[24]/DDR0_DQ[40]
BE51
DDR0_DQ[25]/DDR0_DQ[41]
BC49
DDR0_DQ[26]/DDR0_DQ[42]
BE49
DDR0_DQ[27]/DDR0_DQ[43]
BG51
DDR0_DQ[28]/DDR0_DQ[44]
BG49
DDR0_DQ[29]/DDR0_DQ[45]
BF48
DDR0_DQ[30]/DDR0_DQ[46]
BD48
DDR0_DQ[31]/DDR0_DQ[47]
BJ55
DDR1_DQ[16]/DDR0_DQ[48]
BL55
DDR1_DQ[17]/DDR0_DQ[49]
BJ53
DDR1_DQ[18]/DDR0_DQ[50]
BL53
DDR1_DQ[19]/DDR0_DQ[51]
BN55
DDR1_DQ[20]/DDR0_DQ[52]
BN53
DDR1_DQ[21]/DDR0_DQ[53]
BM52
DDR1_DQ[22]/DDR0_DQ[54]
BK52
DDR1_DQ[23]/DDR0_DQ[55]
BL51
DDR1_DQ[24]/DDR0_DQ[56]
BJ51
DDR1_DQ[25]/DDR0_DQ[57]
BL49
DDR1_DQ[26]/DDR0_DQ[58]
BJ49
DDR1_DQ[27]/DDR0_DQ[59]
BN49
DDR1_DQ[28]/DDR0_DQ[60]
BN51
DDR1_DQ[29]/DDR0_DQ[61]
BK48
DDR1_DQ[30]/DDR0_DQ[62]
BM48
DDR1_DQ[31]/DDR0_DQ[63]
SKYLAKE-Y_FCBGA1515
@
?
SKYLAKE_ULX
DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]
DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]
DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#
DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]
DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]
DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]
DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]
DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]
DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]
DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]
DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]
DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]
DDR CH - A
2 OF 20
4
DDR0_CKN[0]
DDR0_CKP[0]
DDR0_CKN[1]
DDR0_CKP[1]
DDR0_CKE[0]
DDR0_CKE[1]
DDR0_CKE[2]
DDR0_CKE[3]
DDR0_CS#[0]
DDR0_CS#[1]
DDR0_ODT[0]
DDR0_MA[3]
DDR0_MA[4]
DDR0_DQSN[0]
DDR0_DQSP[0]
DDR0_DQSN[1]
DDR0_DQSP[1]
DDR1_DQSN[0]/DDR0_DQSN[2]
DDR1_DQSP[0]/DDR0_DQSP[2]
DDR1_DQSN[1]/DDR0_DQSN[3]
DDR1_DQSP[1]/DDR0_DQSP[3]
DDR0_DQSN[2]/DDR0_DQSN[4]
DDR0_DQSP[2]/DDR0_DQSP[4]
DDR0_DQSN[3]/DDR0_DQSN[5]
DDR0_DQSP[3]/DDR0_DQSP[5]
DDR1_DQSN[2]/DDR0_DQSN[6]
DDR1_DQSP[2]/DDR0_DQSP[6]
DDR1_DQSN[3]/DDR0_DQSN[7]
DDR1_DQSP[3]/DDR0_DQSP[7]
DDR0_ALERT#
DDR0_PAR
DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ
DDR_VTT_CNTL
BC62
BC60
BA60
BA62
BB57
BC58
BE57
AW61
AW63
BJ57
BN61
AW59
AW55
BF62
AV56
AW57
AV58
BA56
BD59
BD61
BG61
BK59
BL62
BJ61
AV60
BN62
BB61
BL61
BM59
BN58
AV62
BB63
BL57
DDRA_DQS#0
AJ61
DDRA_DQS0
AJ63
DDRA_DQS#1
AP62
DDRA_DQS1
AP60
DDRA_DQS#2
AP56
DDRA_DQS2
AP58
DDRA_DQS#3
AJ57
DDRA_DQS3
AJ55
DDRA_DQS#4
BD54
DDRA_DQS4
BF54
DDRA_DQS#5
BF50
DDRA_DQS5
BD50
DDRA_DQS#6
BM54
DDRA_DQS6
BK54
DDRA_DQS#7
BK50
DDRA_DQS7
BM50
BG57
BM56
AR53
AN53
AW53
DDR_VTT_CNTL
BN47
SMVREF
WIDTH:20MIL
SPACING: 20MIL
?REV = 1
1
@
TC90
3
Non-interleave ballmap
DDRA_CLK0# 15
DDRA_CLK0 15
DDRA_CLK1# 15
DDRA_CLK1 15
DDRA_CKE0 15
DDRA_CKE1 15
DDRA_CKE2 15
DDRA_CKE3 15
DDRA_CS0# 15
DDRA_CS1# 15
DDRA_ODT0 15
DDRA_CAA0 15
DDRA_CAA1 15
DDRA_CAA2 15
DDRA_CAA3 15
DDRA_CAA4 15
DDRA_CAA5 15
DDRA_CAA6 15
DDRA_CAA7 15
DDRA_CAA8 15
DDRA_CAA9 15
DDRA_CAB0 15
DDRA_CAB1 15
DDRA_CAB2 15
DDRA_CAB3 15
DDRA_CAB4 15
DDRA_CAB5 15
DDRA_CAB6 15
DDRA_CAB7 15
DDRA_CAB8 15
DDRA_CAB9 15
DDR_SM_VREFCA 15
DDR_SA_VREFDQ 15
DDR_SB_VREFDQ 16
DDRB_DQ[0..7]16
DDRB_DQ[8..15]16
DDRB_DQ[16..23]16
DDRB_DQ[24..31]16
DDRB_DQ[32..39]16
DDRB_DQ[40..47]16
DDRB_DQ[48..55]16
DDRB_DQ[56..63]16
DDRB_DQ0
DDRB_DQ1
DDRB_DQ2
DDRB_DQ3
DDRB_DQ4
DDRB_DQ5
DDRB_DQ6
DDRB_DQ7
DDRB_DQ8
DDRB_DQ9
DDRB_DQ10
DDRB_DQ11
DDRB_DQ12
DDRB_DQ13
DDRB_DQ14
DDRB_DQ15
DDRB_DQ16
DDRB_DQ17
DDRB_DQ18
DDRB_DQ19
DDRB_DQ20
DDRB_DQ21
DDRB_DQ22
DDRB_DQ23
DDRB_DQ24
DDRB_DQ25
DDRB_DQ26
DDRB_DQ27
DDRB_DQ28
DDRB_DQ29
DDRB_DQ30
DDRB_DQ31
DDRB_DQ32
DDRB_DQ33
DDRB_DQ34
DDRB_DQ35
DDRB_DQ36
DDRB_DQ37
DDRB_DQ38
DDRB_DQ39
DDRB_DQ40
DDRB_DQ41
DDRB_DQ42
DDRB_DQ43
DDRB_DQ44
DDRB_DQ45
DDRB_DQ46
DDRB_DQ47
DDRB_DQ48
DDRB_DQ49
DDRB_DQ50
DDRB_DQ51
DDRB_DQ52
DDRB_DQ53
DDRB_DQ54
DDRB_DQ55
DDRB_DQ56
DDRB_DQ57
DDRB_DQ58
DDRB_DQ59
DDRB_DQ60
DDRB_DQ61
DDRB_DQ62
DDRB_DQ63
UC1C
BC41
DDR0_DQ[32]/DDR1_DQ[0]
BC39
DDR0_DQ[33]/DDR1_DQ[1]
BG41
DDR0_DQ[34]/DDR1_DQ[2]
BE39
DDR0_DQ[35]/DDR1_DQ[3]
BF42
DDR0_DQ[36]/DDR1_DQ[4]
BD42
DDR0_DQ[37]/DDR1_DQ[5]
BG39
DDR0_DQ[38]/DDR1_DQ[6]
BE41
DDR0_DQ[39]/DDR1_DQ[7]
BC43
DDR0_DQ[40]/DDR1_DQ[8]
BD46
DDR0_DQ[41]/DDR1_DQ[9]
BG43
DDR0_DQ[42]/DDR1_DQ[10]
BG45
DDR0_DQ[43]/DDR1_DQ[11]
BC45
DDR0_DQ[44]/DDR1_DQ[12]
BE43
DDR0_DQ[45]/DDR1_DQ[13]
BE45
DDR0_DQ[46]/DDR1_DQ[14]
BF46
DDR0_DQ[47]/DDR1_DQ[15]
BM28
DDR1_DQ[32]/DDR1_DQ[16]
BN27
DDR1_DQ[33]/DDR1_DQ[17]
BK28
DDR1_DQ[34]/DDR1_DQ[18]
BL25
DDR1_DQ[35]/DDR1_DQ[19]
BN25
DDR1_DQ[36]/DDR1_DQ[20]
BL27
DDR1_DQ[37]/DDR1_DQ[21]
BJ25
DDR1_DQ[38]/DDR1_DQ[22]
BJ27
DDR1_DQ[39]/DDR1_DQ[23]
BM24
DDR1_DQ[40]/DDR1_DQ[24]
BK24
DDR1_DQ[41]/DDR1_DQ[25]
BN21
DDR1_DQ[42]/DDR1_DQ[26]
BJ23
DDR1_DQ[43]/DDR1_DQ[27]
BL23
DDR1_DQ[44]/DDR1_DQ[28]
BN23
DDR1_DQ[45]/DDR1_DQ[29]
BJ21
DDR1_DQ[46]/DDR1_DQ[30]
BL21
DDR1_DQ[47]/DDR1_DQ[31]
BN45
DDR0_DQ[48]/DDR1_DQ[32]
BM46
DDR0_DQ[49]/DDR1_DQ[33]
BL43
DDR0_DQ[50]/DDR1_DQ[34]
BK46
DDR0_DQ[51]/DDR1_DQ[35]
BN43
DDR0_DQ[52]/DDR1_DQ[36]
BL45
DDR0_DQ[53]/DDR1_DQ[37]
BJ45
DDR0_DQ[54]/DDR1_DQ[38]
BJ43
DDR0_DQ[55]/DDR1_DQ[39]
BM42
DDR0_DQ[56]/DDR1_DQ[40]
BN41
DDR0_DQ[57]/DDR1_DQ[41]
BJ41
DDR0_DQ[58]/DDR1_DQ[42]
BN39
DDR0_DQ[59]/DDR1_DQ[43]
BK42
DDR0_DQ[60]/DDR1_DQ[44]
BL41
DDR0_DQ[61]/DDR1_DQ[45]
BL39
DDR0_DQ[62]/DDR1_DQ[46]
BJ39
DDR0_DQ[63]/DDR1_DQ[47]
BF28
DDR1_DQ[48]
BD28
DDR1_DQ[49]
BG25
DDR1_DQ[50]
BC27
DDR1_DQ[51]
BG27
DDR1_DQ[52]
BE27
DDR1_DQ[53]
BE25
DDR1_DQ[54]
BC25
DDR1_DQ[55]
BF24
DDR1_DQ[56]
BD24
DDR1_DQ[57]
BG21
DDR1_DQ[58]
BC23
DDR1_DQ[59]
BE23
DDR1_DQ[60]
BG23
DDR1_DQ[61]
BC21
DDR1_DQ[62]
BE21
DDR1_DQ[63]
SKYLAKE-Y_FCBGA1515
@
2
?
SKYLAKE_ULX
DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]
DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]
DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#
DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]
DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]
DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]
DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]
DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[4]
DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]
DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]
DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]
DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
DDR0_DQSN[4]/DDR1_DQSN[0]
DDR0_DQSP[4]/DDR1_DQSP[0]
DDR0_DQSN[5]/DDR1_DQSN[1]
DDR0_DQSP[5]/DDR1_DQSP[1]
DDR1_DQSN[4]/DDR1_DQSN[2]
DDR1_DQSP[4]/DDR1_DQSP[2]
DDR1_DQSN[5]/DDR1_DQSN[3]
DDR1_DQSP[5]/DDR1_DQSP[3]
DDR0_DQSN[6]/DDR1_DQSN[4]
DDR0_DQSP[6]/DDR1_DQSP[4]
DDR0_DQSN[7]/DDR1_DQSN[5]
DDR0_DQSP[7]/DDR1_DQSP[5]
DDR CH - B
3 OF 20
DDR1_CKN[0]
DDR1_CKP[0]
DDR1_CKN[1]
DDR1_CKP[1]
DDR1_CKE[0]
DDR1_CKE[1]
DDR1_CKE[2]
DDR1_CKE[3]
DDR1_CS#[0]
DDR1_CS#[1]
DDR1_ODT[0]
DDR1_MA[3]
DDR1_MA[4]
DDR1_DQSN[6]
DDR1_DQSP[6]
DDR1_DQSN[7]
DDR1_DQSP[7]
DDR1_ALERT#
DDR1_PAR
DRAM_RESET#
DDR_RCOMP[0]
DDR_RCOMP[1]
DDR_RCOMP[2]
BK36
BM36
BD32
BF32
BN33
BK32
BG33
BH30
BM30
BJ33
BC35
BK30
BN31
BM32
BL37
BG31
BN37
BJ37
BJ35
BM34
BN35
BG37
BE37
BC37
BF34
BC33
BF30
BD36
BG35
BC31
BF36
BJ31
BK34
BD40
BF40
BD44
BF44
BK26
BM26
BM22
BK22
BK44
BM44
BM40
BK40
BD26
BF26
BF22
BD22
BD34
BD30
BP20
BF64
BJ64
BC64
?REV = 1
1
DDRB_CLK0# 16
DDRB_CLK0 16
DDRB_CLK1# 16
DDRB_CLK1 16
DDRB_CKE0 16
DDRB_CKE1 16
DDRB_CKE2 16
DDRB_CKE3 16
DDRB_CS0# 16
DDRB_CS1# 16
DDRB_ODT0 16
DDRB_CAA0 16
DDRB_CAA1 16
DDRB_CAA2 16
DDRB_CAA3 16
DDRB_CAA4 16
DDRB_CAA5 16
DDRB_CAA6 16
DDRB_CAA7 16
DDRB_CAA8 16
DDRB_CAA9 16
DDRB_CAB0 16
DDRB_CAB1 16
DDRB_CAB2 16
DDRB_CAB3 16
DDRB_CAB4 16
DDRB_CAB5 16
DDRB_CAB6 16
DDRB_CAB7 16
DDRB_CAB8 16
DDRB_CAB9 16
DDRB_DQS#0
DDRB_DQS0
DDRB_DQS#1
DDRB_DQS1
DDRB_DQS#2
DDRB_DQS2
DDRB_DQS#3
DDRB_DQS3
DDRB_DQS#4
DDRB_DQS4
DDRB_DQS#5
DDRB_DQS5
DDRB_DQS#6
DDRB_DQS6
DDRB_DQS#7
DDRB_DQS7
SM_RCOMP_0
1 2
SM_RCOMP_1
1 2
SM_RCOMP_2
1 2
RC26 200_0402_1%
RC25 80.6_0402_1%
RC24 162_0402_1%
Need to check the resistor value
1 2
1K_0402_5%
RC49
10K_0402_5%
+3VALW
12
RC50
100K_0402_5%
C
2
QC14
B
E
3 1
MMBT3904WH_SOT323-3
@
1 2
CPU_DRAMPG_CNTL 35
4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.
3
2014/11/15
2014/11/15
2014/11/15
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2013/08/05
2013/08/05
2013/08/05
Title
Title
Title
MCP (DDR)
MCP (DDR)
MCP (DDR)
Size
Size
Size
Document Number Rev
Document Number Rev
Document Number Rev
C
C
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
Monday, August 17, 2015
Monday, August 17, 2015
Monday, August 17, 2015
Miix4
Miix4
Miix4
1
6 37
6 37
6 37
B B
+CPU_VDDQ
RC48
DDR_VTT_CNTL
A A
5
1.0
1.0
1.0
5
+VCCHDA
1 2
RC47 1K_0402_5%@
HDA_SDO This signal has a w eak internal pull-down.
0 = Enable security measures defined in the Flash Descriptor.
*
1 = Disable Flash Descriptor Security(override). This strap
should only be asserted high during external pull-up in
manufacturing/debug environments ONLY.
D D
For EMI
1
@
CC7
10P_0402_50V8J
2
The signal has a weak internal pull-down.
0 = Disable “ Top Swap” mode. (Default)
+3VS
1 = Enable “ Top Swap” mode.
R684 2.2K_0402_5%
@
PCH_SPI_CS0#25
PCH_SPI_SI25
PCH_SPI_SO25
PCH_SPI_CLK25
C C
SPI_WP#
1 2
RC54 15_0402_5%
@
SPI_HOLD#
1 2
RC55 15_0402_5%
@
SPI_HOLD# for SKL ES Sample
1. 1K PD, unmont 1K PU with HOLD functionality disabled
* 2. 100ohm PD, 1K PU, disabled after RSMRST# de-assertion
HDA_SDOUT
PCH_HDA_SDIN0
PCH_BEEP
12
PCH_SPI_CS0# SPI_CS0#
PCH_SPI_SI
PCH_SPI_SO
PCH_SPI_CLK
1K_0402_5%
RC61
1 2
RC64 0_0402_5%
1 2
RC52 15_0402_5%
1 2
RC53 15_0402_5%
1 2
RC65 15_0402_5%
+3V_SPI
12
12
RC60
1K_0402_5%
@
1 2
R3005 100_0402_1%
PCH_SPI_WP#
PCH_SPI_HOLD#
SPI_SI
SPI_SO
SPI_CLK
PCH_HDA_SDIN023
PCH_HDA_SDOUT23
PCH_ME_PROTECT25
4
TC124@
SPI_CLK
SPI_SO
SPI_SI
SPI_WP#
SPI_HOLD#
SPI_CS0#
EC_KBRST#
PCH_HDA_SDIN0
HDA_SDOUT
PCH_BEEP
HDA_SYNC
HDA_BCLK
HDA_SDOUT
1
AU10
AU12
AT3
AV11
AV13
AU4
AU6
AU8
P9
N8
P3
W12
V7
N6
F12
D12
B12
BL10
BN8
@
BJ19
BK18
BK16
BL15
BL17
BL19
V5
BL12
BK14
AT13
AT11
AP11
AT5
V3
V11
U12
U8
AV3
UC1E
SPI0_CLK
SPI0_MISO
SPI0_MOSI
SPI0_IO2
SPI0_IO3
SPI0_CS0#
SPI0_CS1#
SPI0_CS2#
GPP_D1
GPP_D2
GPP_D3
GPP_D21
GPP_D22
GPP_D0
CL_CLK
CL_DATA
CL_RST#
GPP_A0/RCIN#
GPP_A6/SERIRQ
SKYLAKE-Y_FCBGA1515
REV = 1
1 2
PCH_BEEP23
EC_KBRST#25
EC_INT_SERIRQ25,26
RC43 33_0402_5%
1 2
RC42 33_0402_5%
1 2
RC45 33_0402_5%
1 2
RC46 0_0402_5%
PCH_HDA_SYNC23
PCH_HDA_BCLK23
3
?
UC1G
HDA_SYNC/I2S0_SFRM
HDA_BLK/I2S0_SCLK
HDA_SDO/I2S0_TXD
HDA_SDI0/I2S0_RXD
HDA_SDI1/I2S1_RXD
HDA_RST#/I2S1_SCLK
GPP_D23/I2S_MCLK
I2S1_SFRM
I2S1_TXD
GPP_F1/I2S2_SFRM
GPP_F0/I2S2_SCLK
GPP_F2/I2S2_TXD
GPP_F3/I2S2_RXD
GPP_D19/DMIC_CLK0
GPP_D20/DMIC_DATA0
GPP_D17/DMIC_CLK1
GPP_D18/DMIC_DATA1
GPP_B14/SPKR
SKYLAKE-Y_FCBGA1515
REV = 1 ?
@
SPI - FLASH
SPI - TOUCH
SKYLAKE_ULX
SDIO/SDXC
AUDIO
SKYLAKE_ULX
SMBUS, SMLINK
LPC
C LINK
7 OF 20
?
5 OF 20
GPP_A17/SD_PWR_EN#/ISH_GP7
GPP_B23/SML1ALERT#/PCHHOT#
GPP_A5/LFRAME#/ESPI_CS#
GPP_A14/SUS_STAT#/ESPI_RESET#
GPP_A9/CLKOUT_LPC0/ESPI_CLK
GPP_G0/SD_CMD
GPP_G1/SD_DATA0
GPP_G2/SD_DATA1
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3
GPP_G5/SD_CD#
GPP_G6/SD_CLK
GPP_G7/SD_WP
GPP_A16/SD_1P8_SEL
SD_RCOMP
GPP_F23
GPP_C0/SMBCLK
GPP_C1/SMBDATA
GPP_C2/SMBALERT#
GPP_C3/SML0CLK
GPP_C4/SML0DATA
GPP_C5/SML0ALERT#
GPP_C6/SML1CLK
GPP_C7/SML1DATA
GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3
GPP_A10/CLKOUT_LPC1
GPP_A8/CLKRUN#
2
AH9
AH11
AG12
AF9
AF11
AG8
AG10
AE12
BL4
PCH_WWAN_OFF#
BN4
SD_RCOMP
BF1
AJ8
PCH_SMB_CLK
AC12
PCH_SMB_DATA
W6
SMB_ALERT#
W8
SML0_CLK
W4
SML0_DATA
AC10
SML0_ALERT#
AA6
PCH_SML1_CLK
AA4
PCH_SML1_DAT
W10
SML1_ALERT#
BB6
BK11
BJ8
BG10
BP5
BP7
SUS_STAT#
BJ6
BJ10
CLKOUT0
BF5
CLKOUT1
PM_CLKRUN#
BH11
?
1 2
RC1537
1
200_0402_1%
@
1
@
TC82
P_IRQ 26
LPC_AD0 25,26
LPC_AD1 25,26
LPC_AD2 25,26
LPC_AD3 25,26
LPC_FRAME# 25,26
RC173 22_0402_5%
TC81
1 2
1 2
RC174 22_0402_5%TPM@
PCH_WWAN_OFF# 21
PCH_PCI_CLK 25
PCH_TPM_CLK 26
1
SML0_ALERT#
SMB_ALERT#
SML1_ALERT#
PCH_SML1_CLK
PCH_SML1_DAT
RPC27 10K_0404_4P2R_5%
SML0_CLK
SML0_DATA
PCH_SMB_CLK
PCH_SMB_DATA
PM_CLKRUN#
@
12
R687 2.2K_0402_5%
12
R688 2.2K_0402_5%
1 2
R689 150K_0402_5%
1 4
2 3
@
RPC25
1 8
2 7
3 6
4 5
10K_0804_8P4R_5%
@
1 2
R3024 8.2K_0402_5%
+3VALW_PCH
+3VALW_PCH
+3VS
B B
+3VALW_PCH
RC171 0_0402_5%
+3VS
RC172
+3V_SPI
1. If support DS3, connect to +3VS and don't support EC mirror code;
2. If don't support DS3, connect to +3VALW_PCH and support EC mirror code.
A A
PCH_SPI_CS0#
PCH_SPI_SO
PCH_SPI_WP#
1 2
1 2
@
0_0402_5%
UC4
1
/CS
2
DO(IO1)
/HOLD(IO3)
3
/WP(IO2)
GND4DI(IO0)
W25Q64FVZPIG_WSON8_6X5
5
+3V_SPI
PAD_GND
for signal SMB_ALERT#:
This signal has a weak internal pull-down.
0 = Disable Intel ME Crypto Transport Layer Security
(TLS) cipher suite (no confidentiality). (Default)
1 = Enable Intel ME Crypto Transport Layer Security
(TLS) cipher suite (with confidentiality). Must be
pulled up to support Intel AMT with TLS and Intel
SBA (Small Business Advantage) with TLS.
PCH_SPI_HOLD#
PCH_SPI_CLK
PCH_SPI_SI
+3V_SPI
1
CC8
.1U_0402_10V6-K
2
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.
3
2014/11/15
2014/11/15
2014/11/15
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2013/08/05
2013/08/05
2013/08/05
Title
MCP (RTC&AUDIO&SATA&SMBUS)
MCP (RTC&AUDIO&SATA&SMBUS)
MCP (RTC&AUDIO&SATA&SMBUS)
Size
Size
Size
Document Number Rev
Document Number Rev
Document Number Rev
C
C
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
Monday, August 17, 2015
Monday, August 17, 2015
Monday, August 17, 2015
Miix4
Miix4
Miix4
1
7 37
7 37
7 37
8
VCC
7
6
CLK
5
9
1.0
1.0
1.0
5
+3VS
RPC3
@
1 8
2 7
3 6
4 5
10K_0804_8P4R_5%
RPC4
1 8
2 7
3 6
4 5
D D
10K_0804_8P4R_5%
RC92 100K_0402_5%
+3VALW_PCH
not need reserve
1 2
RC79 10K_0402_5%@
C C
1 2
RC81 10K_0402_5%
RPC5
1 8
2 7
3 6
4 5
10K_0804_8P4R_5%
EMC_NS@
1 2
CC104 1000P_0402_50V7K
EMC_NS@
1 2
CC101 1000P_0402_50V7K
PCIE_CLKREQ#1
PCIE_CLKREQ#2
PCIE_CLKREQ#0
PCIE_CLKREQ#5
SYS_RESET#
SATAGP1
PIRQA#
PCH_PLT_RST#
12
SUSPWRDNACK
AC_PRESENT
BATLOW#
PCIE_WAKE#
LAN_WAKE#
PCH_EXTPWR_GATE#
SATAGP1 9
PIRQA# 9,20
EC_SYS_PWROK25
EC_PCH_PWROK25
TC129 @
PCH_EXTPWR_GATE# :Reserve pull up only?
EC_PCH_PWROK
EC_SYS_PWROK
CLK_PCIE_WLAN#21
CLK_PCIE_WLAN21
WLAN_CLKREQ#9,21
CLK_PCIE_CR#24
CLK_PCIE_CR24
CR_CLKREQ#9,24
PCH_PLT_RST#21,22,24,25,26
EC_RSMRST#25
1
TC189 @
VCCST_PWRGD VCCST_PWRGD_R
1 2
RC145 0_0402_5%
1 2
RC146 0_0402_5%
EC_RSMRST# EC_PBTN_OUT#_R
SUSPWRDNACK25
1
PCIE_WAKE#21
4
1 2
R3031 60.4_0402_1%
SUSACK#_R
+CPU_VCCST
RC137
1K_0402_5%
1 2
VCCST_PWRGD
PCIE_CLKREQ#1
PCIE_CLKREQ#2
WLAN_CLKREQ#
CR_CLKREQ#
PCIE_CLKREQ#5
PCIE_CLKREQ#0
PCH_PLT_RST#
SYS_RESET#
EC_RSMRST#
EC_SYS_PWROK_R
EC_PCH_PWROK_R
1 2
RC140 0_0402_5%
PCIE_WAKE#
LAN_WAKE#
UC1J
H35
CLKOUT_PCIE_N1
F35
CLKOUT_PCIE_P1
AV9
GPP_B6/SRCCLKREQ1#
J36
CLKOUT_PCIE_N2
G36
CLKOUT_PCIE_P2
BD10
GPP_B7/SRCCLKREQ2#
J38
CLKOUT_PCIE_N3
G38
CLKOUT_PCIE_P3
AV5
GPP_B8/SRCCLKREQ3#
H37
CLKOUT_PCIE_N4
F37
CLKOUT_PCIE_P4
AV7
GPP_B9/SRCCLKREQ4#
H39
CLKOUT_PCIE_N5
F39
CLKOUT_PCIE_P5
BC5
GPP_B10/SRCCLKREQ5#
BB10
GPP_B5/SRCCLKREQ0#
SKYLAKE-Y_FCBGA1515
@
UC1K
BB8
GPP_B13/PLTRST#
H2
SYS_RESET#
BJ12
RSMRST#
A62
PROCPWRGD
B61
VCCST_PWRGD
J1
SYS_PWROK
BP14
PCH_PWROK
BN15
DSW_PWROK
BL6
GPP_A13/SUSWARN#/SUSPWRDNACK
BF9
GPP_A15/SUSACK#
BP9
WAKE#
BE15
GPD2/LAN_WAKE#
BC15
GPD11/LANPHYPC
BB16
GPD7/RSVD
SKYLAKE-Y_FCBGA1515
@
RC139
1 2
0_0402_5%
?
SKYLAKE_ULX
CLOCK SIGNALS
10 OF 20
SKYLAKE_ULX
SYSTEM POWER MANAGEMENT
EC_VCCST_PWRGD 25
?
11 OF 20
3
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
GPD8/SUSCLK
XTAL24_IN
XTAL24_OUT
XCLK_BIASREF
RTCX1
RTCX2
SRTCRST#
RTCRST#
GPP_B12/SLP_S0#
GPD4/SLP_S3#
GPD5/SLP_S4#
GPD10/SLP_S5#
GPD9/SLP_WLAN#
GPD6/SLP_A#
GPD3/PWRBTN#
GPD1/ACPRESENT
GPD0/BATLOW#
GPP_A11/PME#
GPP_B11/EXT_PWR_GATE#
GPP_B2/VRALERT#
J34
G34
BA15
M1
L2
P1
BN19
BP18
BH18
BN12
?REV = 1
SLP_SUS#
SLP_LAN#
INTRUDER#
CLK_PCIE_XDP#
CLK_PCIE_XDP
SUSCLK
XTAL24_IN
XTAL24_OUT
DIFFCLK_BIASREF
RTC_X1
RTC_X2
SRTC_RST#
RTC_RST#
PCH_SLP_S0#_R
BC9
PCH_SLP_S3#_R
AY14
PCH_SLP_S4#_R
BF16
PCH_SLP_S5#
BH14
BN10
BP11
BH16
BE17
BF14
AC_PRESENT
BD14
BD16
BATLOW#
BF7
PME#
BG19
INTRUDER#
PCH_EXTPWR_GATE#
BC7
BD6
VRALERT#
?REV = 1
1
TC85@
1
TC87@
SUSCLK 21
1 2
RC72 2.7K_0402_1%
RTC_RST# 25
1 2
RC161 0_0402_5%
1 2
RC142 0_0402_5%
1 2
RC144 0_0402_5%
1
TC39@
1 2
RC141 0_0402_5%
1
TC89@
1
TC138@
2
+VCCCLK5
Differential Clock Bias Reference:
Width: 12-15Mil
Space:12Mil
Length: 500Mil
need to check R value
PCH_SLP_S0# 12,25
PCH_SLP_S3# 25
PCH_SLP_S4# 25
EC_PBTN_OUT# 25
PCH_EXTPWR_GATE# 13
RC71 1M_0402_5%
YC2
XTAL24_IN
GND12OSC2
1
OSC1
24MHZ_6PF_7V24000032
1
CC12
2.7P_0402_50V9-B
2
RC32 10M_0402_5%
YC1
1 2
32.768KHZ_9PF_X1A000141000200
2
CC4
9P_0402_50V8J
1
CRYSTAL
1, Space 15MIL
2, No trace under crystal
3, Place on oppsosit side of MCP for temp influence
SRTC_RST#
RTC_RST#
1U_0402_10V6K
1
1
CC6
1
2
2
TP71
@
INTRUDER#
SUSCLK
1
12
3
4
GND2
1
2
12
2
1
1U_0402_10V6K
CC9
RC41 1M_0402_5%
CRB use 330K
1 2
@
XTAL24_OUT
CC11
2.7P_0402_50V9-B
RTC_X1
RTC_X2
CC5
9P_0402_50V8J
12
RC3320K_0402_1%
12
RC3420K_0402_1%
12
RC661K_0402_5%
VCCRTC
VCCRTC
2
@
CC140
1000P_0402_50V7K
1
B B
EC_PCH_ACIN25
A A
5
RC88 0_0402_5%
4
1 2
AC_PRESENT
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.
3
2014/11/15
2014/11/15
2014/11/15
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
RTC_VCC
2013/08/05
2013/08/05
2013/08/05
RC1491
1 2
DC1
SDM10U45LP-7_DFN1006-2-2
2 1
+3VL
DC37
BAT_D
2 1
SDM10U45LP-7_DFN1006-2-2
0_0402_5%
Title
Title
Title
MCP (Clock,PM)
MCP (Clock,PM)
MCP (Clock,PM)
Size
Size
Size
Document Number Rev
Document Number Rev
Document Number Rev
C
C
C
Monday, August 17, 2015
Monday, August 17, 2015
Monday, August 17, 2015
Date: Sheet of
Date: Sheet of
Date: Sheet of
RC35
1 2
1.5K_0402_5%
Miix4
Miix4
Miix4
1
VCCRTC
12
RC36
45.3K_0402_1%
CC17
1
2
8 37
8 37
8 37
1U_0402_10V6K
CC26
.1U_0402_10V6-K
2
1
@
1.0
1.0
1.0
5
+3VS
+1.8VALW
D D
+3VALW_PCH
PCH_I2C_SCL0
+3VS
PCH_I2C_SDA0
C C
PCH_I2C_SCL1
+3VS
PCH_I2C_SDA1
PCH_I2C_SCL2
+1.8VS
PCH_I2C_SDA2
B B
PCH_I2C_SCL3
+1.8VS
PCH_I2C_SDA3
PCH_I2C_SCL4
+1.8VS
A A
PCH_I2C_SDA4
The signal has a weak internal pull-down.
0 = Disable “ No Reboot” mode. (Default)
1 = Enable “ No Reboot” mode
@
GPP_B18
12
R685 2.2K_0402_5%
@
GPP_B22
12
R686 2.2K_0402_5%
RPC46
@
14
23
2.2K_0404_4P2R_5%
RPC48
1 8
@
2 7
3 6
4 5
2.2K_0804_8P4R_5%
RPC49
@
1 8
2 7
3 6
4 5
2.2K_0804_8P4R_5%
AO5804EL_SC89-6
QC45A
6 1
@
2
5
@
3 4
AO5804EL_SC89-6
QC45B
QC47A
AO5804EL_SC89-6
6 1
@
2
5
@
3 4
QC47B
AO5804EL_SC89-6
QC43A
6 1
@
2
5
@
3 4
QC43B
AO5804EL_SC89-6
QC46A
6 1
@
2
5
@
3 4
QC46B
AO5804EL_SC89-6
QC173A
6 1
@
2
5
@
3 4
QC173B
AO5804EL_SC89-6
PCH_I2C_SCL1
PCH_I2C_SDA1
PCH_I2C_SDA0
PCH_I2C_SCL0
AO5804EL_SC89-6
AO5804EL_SC89-6
AO5804EL_SC89-6
5
12
PCH_I2C_SDA2
PCH_I2C_SCL2
PCH_I2C_SDA3
PCH_I2C_SCL3
PCH_I2C_SDA4
PCH_I2C_SCL4
RPC28
1 4
2 3
1K_0404_4P2R_5%
RPC29
2.2K_0404_4P2R_5%
R690
2.2K_0402_5%
@
WLAN
PM_I2C_SCL0 26
ISH@
PM_I2C_SDA0 26
14
23
RPC21
2.2K_0404_4P2R_5%
RPC26
2.2K_0404_4P2R_5%
RPC30
2.2K_0404_4P2R_5%
@
The signal has a weak internal pull-down.
0 = boot from SPI. (Default)
1 = enable boot to LPC,
PCIE_PRX_DTX_N321
PCIE_PRX_DTX_P321
PCIE_PTX_DRX_N321
PCIE_PTX_DRX_P321
PCIE_PRX_DTX_N424
PCIE_PRX_DTX_P424
CR
PCIE_PTX_DRX_N424
PCIE_PTX_DRX_P424
SATA_PRX_DTX_N120
SATA_PRX_DTX_P120
SSD
+3VS
PM_I2C_SCL1 25,28
PM_I2C_SDA1 25,28
PM_I2C_SCL2 22
14
23
PM_I2C_SDA2 22
SATA_PTX_DRX_N120
SATA_PTX_DRX_P120
Impedance Compensation Inputs
Width 12~15Mil
Space >12Mil
Length 500Mil
PIRQA#8,20
+3VS
PCH_WLAN_OFF#21
PCH_BT_OFF#21
+1.8VS
reserved
touch panel
WF Camera
PM_I2C_SCL3 22
+1.8VS
PM_I2C_SDA3 22
PM_I2C_SCL4 26
+1.8VS
PM_I2C_SDA4 26
UF Camera
P Sensor
14
23
14
23
RC119
1 2
100_0402_1%
UART_RX_DEBUG21
UART_TX_DEBUG21
TC169@
TC170@
PCH_WLAN_OFF#
PCH_BT_OFF#
ISH_I2C0_SCL
PCH_I2C_SCL0
PCH_I2C_SDA0
ISH_I2C0_SDA
PCH_I2C_SCL1
PCH_I2C_SDA1
PCH_I2C_SCL2
PCH_I2C_SDA2
PCH_I2C_SCL3
PCH_I2C_SDA3
PCH_I2C_SCL4
PCH_I2C_SDA4
4
4
PCIE_RCOMPN
PCIE_RCOMPP
PROC_PRDY#
1
PROC_PREQ#
1
PIRQA#
GPP_B18
GPP_B22
BOARD_ID0
BOARD_ID1
BOARD_ID2
BOARD_ID3
PCH_I2C_SDA0
PCH_I2C_SCL0
PCH_I2C_SDA1
PCH_I2C_SCL1
PCH_I2C_SDA2
PCH_I2C_SCL2
PCH_I2C_SDA3
PCH_I2C_SCL3
PCH_I2C_SDA4
PCH_I2C_SCL4
UC1H
C20
PCIE1_RXN/USB3_5_RXN
A20
PCIE1_RXP/USB3_5_RXP
G20
PCIE1_TXN/USB3_5_TXN
J20
PCIE1_TXP/USB3_5_TXP
B19
PCIE2_RXN/USB3_6_RXN
D19
PCIE2_RXP/USB3_6_RXP
F19
PCIE2_TXN/USB3_6_TXN
H19
PCIE2_TXP/USB3_6_TXP
C22
PCIE3_RXN
A22
PCIE3_RXP
G22
PCIE3_TXN
J22
PCIE3_TXP
B21
PCIE4_RXN
D21
PCIE4_RXP
F21
PCIE4_TXN
H21
PCIE4_TXP
C24
PCIE5_RXN
A24
PCIE5_RXP
G24
PCIE5_TXN
J24
PCIE5_TXP
B23
PCIE6_RXN
D23
PCIE6_RXP
F23
PCIE6_TXN
H23
PCIE6_TXP
C26
PCIE7_RXN/SATA0_RXN
A26
PCIE7_RXP/SATA0_RXP
G26
PCIE7_TXN/SATA0_TXN
J26
PCIE7_TXP/SATA0_TXP
B25
PCIE8_RXN/SATA1A_RXN
D25
PCIE8_RXP/SATA1A_RXP
F25
PCIE8_TXN/SATA1A_TXN
H25
PCIE8_TXP/SATA1A_TXP
C28
PCIE9_RXN
A28
PCIE9_RXP
G28
PCIE9_TXN
J28
PCIE9_TXP
B27
PCIE10_RXN
D27
PCIE10_RXP
F27
PCIE10_TXN
H27
PCIE10_TXP
A9
PCIE_RCOMPN
B10
PCIE_RCOMPP
D51
PROC_PRDY#
B55
PROC_PREQ#
BF3
GPP_A7/PIRQA#
SKYLAKE-Y_FCBGA1515
@
UC1F
BC3
GPP_B15/GSPI0_CS#
AW10
GPP_B16/GSPI0_CLK
AW6
GPP_B17/GSPI0_MISO
BB4
GPP_B18/GSPI0_MOSI
BB2
GPP_B19/GSPI1_CS#
AW12
GPP_B20/GSPI1_CLK
AW4
GPP_B21/GSPI1_MISO
AW8
GPP_B22/GSPI1_MOSI
AC8
GPP_C8/UART0_RXD
AA8
GPP_C9/UART0_TXD
AA10
GPP_C10/UART0_RTS#
AA12
GPP_C11/UART0_CTS#
AD5
GPP_C20/UART2_RXD
AD7
GPP_C21/UART2_TXD
AD3
GPP_C22/UART2_RTS#
AD9
GPP_C23/UART2_CTS#
AD11
GPP_C16/I2C0_SDA
AB3
GPP_C17/I2C0_SCL
AB9
GPP_C18/I2C1_SDA
AB11
GPP_C19/I2C1_SCL
AP3
GPP_F4/I2C2_SDA
AP7
GPP_F5/I2C2_SCL
AP5
GPP_F6/I2C3_SDA
AT7
GPP_F7/I2C3_SCL
AN4
GPP_F8/I2C4_SDA
AN6
GPP_F9/I2C4_SCL
SKYLAKE-Y_FCBGA1515
@
0_0402_5%
1 2
RC159
@
1 2
RC147 0_0402_5%
1 2
RC148 0_0402_5%
@
0_0402_5%
1 2
RC160
0_0402_5%
1 2
0_0402_5%
RC149
1 2
RC150
0_0402_5%
1 2
RC151
0_0402_5%
1 2
RC152
0_0402_5%
1 2
RC153
0_0402_5%
1 2
RC154
1 2
RC157 0_0402_5%
@
1 2
RC158 0_0402_5%@
3
?
SKYLAKE_ULX
SSIC / USB3
PCIE/USB3/S ATA
REV = 1 ?
SKYLAKE_ULX
REV = 1
PM_I2C_SCL0
PM_I2C_SDA0
PM_I2C_SCL1
PM_I2C_SDA1
PM_I2C_SCL2
PM_I2C_SDA2
PM_I2C_SCL3
PM_I2C_SDA3
PM_I2C_SCL4
PM_I2C_SDA4
6 OF 20
USB2
8 OF 20
?
ISHLPSS
GPP_F10/I2C5_SDA/ISH_I2C2_SDA
GPP_F11/I2C5_SCL/ISH_I2C2_SCL
GPP_D13/ISH_UART0_RXD/SML0BDATA
GPP_D14/ISH_UART0_TXD/SML0BCLK
GPP_D16/ISH_UART0_CTS#/SML0BALERT#
GPP_C12/UART1_RXD/ISH_UART1_RXD
GPP_C13/UART1_TXD/ISH_UART1_TXD
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
GPP_C15/UART1_CTS#/ISH_UART1_CTS#
Sx_EXIT_HOLDOFF#/GPP_A12/BM_BUSY#/ISH_GP6
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.
3
USB3_1_RXN
USB3_1_RXP
USB3_1_TXN
USB3_1_TXP
USB3_2_RXN/SSIC_1_RXN
USB3_2_RXP/SSIC_1_RXP
USB3_2_TXN/SSIC_1_TXN
USB3_2_TXP/SSIC_1_TXP
USB3_3_RXN/SSIC_2_RXN
USB3_3_RXP/SSIC_2_RXP
USB3_3_TXN/SSIC_2_TXN
USB3_3_TXP/SSIC_2_TXP
USB3_4_RXN
USB3_4_RXP
USB3_4_TXN
USB3_4_TXP
USB2N_1
USB2P_1
USB2N_5
USB2P_5
USB2N_7
USB2P_7
USB2N_3
USB2P_3
USB2N_9
USB2P_9
USB2N_2
USB2P_2
USB2_COMP
USB2_ID
USB2_VBUSSENSE
GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#
GPP_E4/DEVSLP0
GPP_E5/DEVSLP1
GPP_E6/DEVSLP2
GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2
GPP_E8/SATALED#
GPP_D9
GPP_D10
GPP_D11
GPP_D12
GPP_D5/ISH_I2C0_SDA
GPP_D6/ISH_I2C0_SCL
GPP_D7/ISH_I2C1_SDA
GPP_D8/ISH_I2C1_SCL
GPP_D15/ISH_UART0_RTS#
GPP_A18/ISH_GP0
GPP_A19/ISH_GP1
GPP_A20/ISH_GP2
GPP_A21/ISH_GP3
GPP_A22/ISH_GP4
GPP_A23/ISH_GP5
?
2014/11/15
2014/11/15
2014/11/15
2
USB20_N1 19
USB20_P1 19
USB20_N2 32
USB20_P2 32
USB20_N3 28
USB20_P3 28
USB20_N4 21
USB20_P4 21
USB20_N5 21
USB20_P5 21
USB20_N6 25
USB20_P6 25
1 2
1 2
R3002 113_0402_1%
RC105 0_0402_5%
RC106 1K_0402_5%
SATAGP1 8
1 2
0_0402_5%
PCH_GNSS_DISABLE# 21
Deciphered Date
Deciphered Date
Deciphered Date
2
USB3.0 stand port
USB30_RX_N1 19
USB30_RX_P1 19
USB30_TX_N1 19
USB30_TX_P1 19
USB30_RX_N2 21
USB30_RX_P2 21
USB30_TX_N2 21
USB30_TX_P2 21 CR_CLKREQ#8,24
reserve for WWAN
USB30_RX_N4 22
USB30_RX_P4 22
USB30_TX_N4 22
USB30_TX_P4 22
USB2.0 stand port
DC IN combine port
POGO
BT
WWAN
Reserved for EC
12
USB_OC0# 19
USB_OC2# 32
FULL_CARD_POWER_OFF# 21
PCH_SATA_DEVSLP 20
EC_SENSOR_INT 25
ISH_I2C0_SDA 28
ISH_I2C0_SCL 28
ISH_I2C1_SDA 28
ISH_I2C1_SCL 28
ISH_GP0 28
PCH_3D_PWREN# 22
G_INT1 26
G_INT2 28
PCH_THS_RST# 28
THS_IRQ 28
ISH_GP6 28
2013/08/05
2013/08/05
2013/08/05
C16
A16
G16
J16
B15
D15
F15
H15
C18
A18
G18
J18
B17
D17
F17
H17
AJ6
AJ4
AH5
AH3
AF5
AF3
AL6
AL4
AG6
AG4
AM3
AM5
USB2_COMP_R
N2
AF7
AE6
USB_OC0#
N12
USB_OC1#
M11
USB_OC2#
F8
USB_OC3#
B8
F10
H10
L8
G11
SATAGP0
J11
SATAGP1
N10
SATAGP2
H8
RC3027
P11
T7
T5
T11
ISH_I2C0_SDA
P7
ISH_I2C0_SCL
P5
ISH_I2C1_SDA
T9
ISH_I2C1_SCL
T3
PCH_GNSS_DISABLE#
AM7
AT9
U10
U4
U6
V9
AC6
AC4
AB7
AB5
BF11
BD2
G_INT1
BJ1
G_INT2
BL3
PCH_THS_RST#
BJ3
THS_IRQ
BD4
BJ4
GPIO Mapping
GroupA/B/C/D/E/G -- Usued for 3.3V power plane
GroupF-Used for 1.8V Power Plane
I2C Mapping
GroupC -- Usued for 3.3V power plane
GroupF-Used for 1.8V Power Plane
I2C Assignment
I2C0--senso r
I2C1--Touch panel
I2C2--WF camera
I2C3--UF camera
I2C4--P sensor
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
WLAN_CLKREQ#8,21
3D camera
+3VS
+1.8VS
EC_SCI# 4,25
G Sensor
Light sensor
sensor debug hooks
G sensor interrupt
light sensor interrupt
Title
Title
Title
MCP (GPIO,USB,PCIE)
MCP (GPIO,USB,PCIE)
MCP (GPIO,USB,PCIE)
Size
Size
Size
Document Number Rev
Document Number Rev
Document Number Rev
C
C
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
USB_OC1#
USB_OC0#
USB_OC3#
USB_OC2#
ISH_I2C0_SDA
ISH_I2C0_SCL
SATAGP0
WLAN_CLKREQ#
SATAGP2
CR_CLKREQ#
ISH_I2C1_SDA
ISH_I2C1_SCL
1 4
2 3
RPC51 10K_0404_4P2R_5%
RPC45
1 8
2 7
3 6
4 5
10K_0804_8P4R_5%
WWAN@
12
RC103
10K_0402_5%
1 2
1 2
RC83
10K_0402_5%
@
LTE@
BOARD_ID0
BOARD_ID1
BOARD_ID2
BOARD_ID3
1 2
1 2
RC84
10K_0402_5%
@
UN_LTE@
BOARD_ID3 Description
0
1 LTE SKU
BOARD ID table
BOARD_ID2 BOARD_ID1 BOARD_ID0
0 0
0
0 0
0
0011 1
1 0 0
0
1 0
1
1 1
1
PCH_THS_RST#
Miix4
Miix4
Miix4
Monday, August 17, 2015
Monday, August 17, 2015
Monday, August 17, 2015
1
RPC17
10K_0804_8P4R_5%
RPC50
1 4
2 3
1K_0404_4P2R_5%
RPC44
10K_0804_8P4R_5%
RPC47
1 4
2 3
1K_0404_4P2R_5%
PCH_3D_PWREN#
PCH_WLAN_OFF#
PCH_GNSS_DISABLE#
1 2
RC85
RC86
10K_0402_5%
@
1 2
RC89
RC90
10K_0402_5%
@
NO LTE SKU
1
11
9 37
9 37
9 37
G_INT1
G_INT2
PCH_BT_OFF#
1 2
10K_0402_5%
@
1 2
10K_0402_5%
@
DRAM
4G SK HYNIX
4G MICRON
4G SAMSUNG
8G SK HYNIX
8G MICRON
8G SAMSUNG
+3VALW_PCH
18
27
36
45
@
18
27
36
45
THS_IRQ
+3VS
RC87
10K_0402_5%
RC91
10K_0402_5%
12
RC9410K_0402_5% @
12
RC9510K_0402_5% @
+3VS
+3VS
+3VS
1.0
1.0
1.0
5
4
3
2
1
CPU_CFG4
D D
?
SKYLAKE_ULX
CSI-2
SKYLAKE_ULX
RESERVED SIGNALS
?
eMMC
9 OF 20
20 OF 20
CSI2_CLKN0
CSI2_CLKP0
CSI2_CLKN1
CSI2_CLKP1
CSI2_CLKN2
CSI2_CLKP2
CSI2_CLKN3
CSI2_CLKP3
CSI2_COMP
GPP_D4/FLASHTRIG
GPP_F13/EMMC_DATA0
GPP_F14/EMMC_DATA1
GPP_F15/EMMC_DATA2
GPP_F16/EMMC_DATA3
GPP_F17/EMMC_DATA4
GPP_F18/EMMC_DATA5
GPP_F19/EMMC_DATA6
GPP_F20/EMMC_DATA7
GPP_F21/EMMC_RCLK
GPP_F22/EMMC_CLK
GPP_F12/EMMC_CMD
EMMC_RCOMP
RSVD_TP_04
RSVD_TP_03
RSVD_TP_02
RSVD_TP_01
H31
F31
D31
B31
C34
A34
D39
B39
A11
N4
AN12
AP9
AN10
AJ10
AM9
AL12
AJ12
AN8
AL10
AL8
AM11
BC1
RSVD_37
RSVD_36
TP5
TP6
RSVD_35
RSVD_34
RSVD_33
RSVD_32
RSVD_31
RSVD_30
RSVD_29
RSVD_28
RSVD_27
RSVD_26
RSVD_25
RSVD_24
RSVD_23
TP4
RSVD_22
RSVD_21
RSVD_20
RSVD_19
RSVD_18
RSVD_17
RSVD_16
TP1
TP2
CSI2_COMP_R
EMMC_RCOMP_R
BL64
BG47
BA17
AY18
BF18
BE19
BA23
AY22
R12
P13
M15
L16
L18
M17
AH7
K12
H12
BN3
BP3
L22
M23
BN1
AY20
BA21
BB14
M25
L24
L28
M27
BJ15
BJ17
CPU_CFG0
1
TC142@
CPU_CFG2
1
TC143@
CPU_CFG4
1 2
R3006
49.9_0402_1%
C C
VCCST
12
R3007
150_0402_5%
12
R3008
@
10K_0402_5%
B B
PCH_CSI2_DN222
PCH_CSI2_DP222
WF
PCH_CSI2_DN322
PCH_CSI2_DP322
PCH_CSI2_DN022
PCH_CSI2_DP022
UF
PCH_CSI2_DN122
PCH_CSI2_DP122
A A
CFG_RCOMP_R
RSVD_L20
UC1T
G52
CFG[0]
F53
CFG[1]
J52
CFG[2]
H53
CFG[3]
H55
CFG[4]
D55
CFG[5]
C56
CFG[6]
F55
CFG[7]
D61
CFG[8]
G58
CFG[9]
D57
CFG[10]
F61
CFG[11]
J60
CFG[12]
J58
CFG[13]
H61
CFG[14]
H59
CFG[15]
J54
CFG[16]
G54
CFG[17]
G56
CFG[18]
J56
CFG[19]
A54
CFG_RCOMP
A60
ITP_PMODE
B4
RSVD_01
B3
RSVD_02
F3
RSVD_03
F1
RSVD_04
L36
RSVD_05
L38
RSVD_06
BA19
RSVD_07
BB18
RSVD_08
BC19
RSVD_09
BD18
RSVD_10
D49
RSVD_11
M21
RSVD_12
L20
RSVD_13
M19
RSVD_14
L26
RSVD_15
SKYLAKE-Y_FCBGA1515
REV = 1 ?
@
UC1I
H29
CSI2_DN0
F29
CSI2_DP0
F33
CSI2_DN1
H33
CSI2_DP1
J30
CSI2_DN2
G30
CSI2_DP2
J32
CSI2_DN3
G32
CSI2_DP3
D29
CSI2_DN4
B29
CSI2_DP4
C32
CSI2_DN5
A32
CSI2_DP5
C30
CSI2_DN6
A30
CSI2_DP6
D33
CSI2_DN7
B33
CSI2_DP7
D35
CSI2_DN8
B35
CSI2_DP8
C36
CSI2_DN9
A36
CSI2_DP9
D37
CSI2_DN10
B37
CSI2_DP10
C38
CSI2_DN11
A38
CSI2_DP11
SKYLAKE-Y_FCBGA1515
REV = 1 ?
@
CFG4 Setting:
1K PD, used for Enable EDP Panel
RSVD_BB14
PCH_CSI2_CLKN1 22
PCH_CSI2_CLKP1 22
PCH_CSI2_CLKN0 22
PCH_CSI2_CLKP0 22
1 2
PCH_FLASH__STROBE 22
1 2
R3004 200_0402_1%
R3009
WF
U
R3003
100_0402_1%
RC67 1K_0402_1%
1 2
F
1 2
0_0402_5%
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.
5
4
3
2014/11/15
2014/11/15
2014/11/15
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2013/08/05
2013/08/05
2013/08/05
Title
MCP (OTHER)
MCP (OTHER)
MCP (OTHER)
Size
Size
Size
Document Number Rev
Document Number Rev
Document Number Rev
C
C
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
Monday, August 17, 2015
Monday, August 17, 2015
Monday, August 17, 2015
Miix4
Miix4
Miix4
10 37
10 37
10 37
1
1.0
1.0
1.0
CPU_CORE
D D
C C
CPU_SVID_ALRT#
CPU_SVID_CLK36
CPU_SVID_DAT36
B B
5
?
SKYLAKE_ULX
UC1L
A64
VCC_01
AE32
VCC_02
AE40
VCC_03
AH41
VCC_04
AN32
VCC_05
AT33
VCC_06
AT41
VCC_07
J64
VCC_08
L48
VCC_09
M33
VCC_10
M43
VCC_11
M53
VCC_12
M64
VCC_13
N40
VCC_14
N59
VCC_15
P60
VCC_16
R57
VCC_17
T41
VCC_18
AA32
VCC_19
AE33
VCC_20
AE41
VCC_21
AK32
VCC_22
AN41
VCC_23
AT35
VCC_24
B64
VCC_25
L40
VCC_26
L50
VCC_27
M35
VCC_28
M45
VCC_29
M56
VCC_30
N32
VCC_31
N42
VCC_32
N61
VCC_33
P62
VCC_34
R59
VCC_35
V32
VCC_36
AA41
VCC_37
AE35
VCC_38
AF32
VCC_39
AK41
VCC_40
AR32
VCC_41
AT36
VCC_42
D64
VCC_43
L42
VCC_44
L52
VCC_45
M37
VCC_46
M47
VCC_47
R63
VCC_48
P56
VCC_49
R32
VCC_50
Y32
VCC_51
CPU POWER 1 OF 4
SKYLAKE-Y_FCBGA1515
@
1 2
RC135 0_0402_5%
12 OF 20
VCCST
@
12
12
RC131
1 2
RC132
RC1544
56_0402_5%
100_0402_1%
54.9_0402_1%
1, Alert# Route Between CLK and Data
CPU_CORE
M58
VCC_90
N34
VCC_89
N54
VCC_88
N63
VCC_87
P64
VCC_86
R61
VCC_85
V41
VCC_84
AC41
VCC_83
AE38
VCC_82
AH32
VCC_81
AL41
VCC_80
AT32
VCC_79
AT40
VCC_78
H63
VCC_77
L46
VCC_76
L63
VCC_75
M41
VCC_74
M51
VCC_73
M62
VCC_72
N38
VCC_71
N57
VCC_70
P58
VCC_69
R41
VCC_68
T32
VCC_67
Y41
VCC_66
AC32
VCC_65
AE36
VCC_64
AF41
VCC_63
AL32
VCC_62
AR41
VCC_61
AT38
VCC_60
F64
VCC_59
L44
VCC_58
L54
VCC_57
M39
VCC_56
M49
VCC_55
M60
VCC_54
N36
VCC_53
N55
VCC_52
CPU_VCC_SENSE
L34
VCC_SENSE
CPU_VSS_SENSE
L32
VSS_SENSE
SVID_ALERT#
B58
VIDALERT#
SVID_CLK
A56
VIDSCK
SVID_DAT
A58
VIDSOUT
AA26
VCCSTG_02
AC26
VCCSTG_01
?REV = 1
@
12
CC42
.1U_0402_10V6-K
1 2
RC133 220_0402_5%
1 2
RC134 0_0402_5%
4
24A 2
CPU_CORE
RC3015
100_0402_1%
SVID_ALERT#
SVID_CLK
SVID_DAT
1 2
1 2
100_0402_1%
RC3017
CPU_VCC_SENSE 36
CPU_VSS_SENSE 36
VCCSTG
+CPU_VCCGT
AA53
VCCGT_01
AB62
VCCGT_02
AC47
VCCGT_03
AC55
VCCGT_04
AD54
VCCGT_05
AD64
VCCGT_06
AE61
VCCGT_07
AF47
VCCGT_08
AJ53
VCCGT_09
AK49
VCCGT_10
AN46
VCCGT_11
AT43
VCCGT_12
AT50
VCCGT_13
N50
VCCGT_14
T46
VCCGT_15
T54
VCCGT_16
U61
VCCGT_17
V60
VCCGT_18
W57
VCCGT_19
Y44
VCCGT_20
Y51
VCCGT_21
Y62
VCCGT_22
AB54
VCCGT_23
AB64
VCCGT_24
AC49
VCCGT_25
AC57
VCCGT_26
AD56
VCCGT_27
AE53
VCCGT_28
AE63
VCCGT_29
AF49
VCCGT_30
AK43
VCCGT_31
AK50
VCCGT_32
AN47
VCCGT_33
AT44
VCCGT_34
AT51
VCCGT_35
R51
VCCGT_36
T47
VCCGT_37
U53
VCCGT_38
U63
VCCGT_39
V62
VCCGT_40
W59
VCCGT_41
Y46
VCCGT_42
Y54
VCCGT_43
Y64
VCCGT_44
AB58
VCCGT_45
AC44
VCCGT_46
AC51
VCCGT_47
AC61
VCCGT_48
AD60
VCCGT_49
AE57
VCCGT_50
AF44
VCCGT_51
AF51
VCCGT_52
AK46
VCCGT_53
AB60
VCCGT_54
AC46
VCCGT_55
@
UC1M
SKYLAKE-Y_FCBGA1515
3
?
SKYLAKE_ULX
VCCGT_107
VCCGT_106
VCCGT_105
VCCGT_104
VCCGT_103
VCCGT_102
VCCGT_101
VCCGT_100
VCCGT_99
VCCGT_98
VCCGT_97
VCCGT_96
VCCGT_95
VCCGT_94
VCCGT_93
VCCGT_92
VCCGT_91
VCCGT_90
VCCGT_89
VCCGT_88
VCCGT_87
VCCGT_86
VCCGT_85
VCCGT_84
VCCGT_83
VCCGT_82
VCCGT_81
VCCGT_80
VCCGT_79
VCCGT_78
VCCGT_77
VCCGT_76
VCCGT_75
VCCGT_74
VCCGT_73
VCCGT_72
VCCGT_71
VCCGT_70
VCCGT_69
VCCGT_68
VCCGT_67
VCCGT_66
VCCGT_65
VCCGT_64
VCCGT_63
VCCGT_62
VCCGT_61
VCCGT_60
VCCGT_59
VCCGT_58
VCCGT_57
VCCGT_56
VCCGT_SENSE
VSSGT_SENSE
CPU POWER 2 OF 4
13 OF 20
REV = 1 ?
+CPU_VCCGT
AC53
AC63
AD62
AE59
AF46
AG53
AK47
AN44
AN51
AT49
N48
T44
T51
U59
V58
W55
Y43
Y50
Y60
AB56
AC43
AC50
AC59
AD58
AE55
AF43
AF50
AK44
AK51
AN49
AT46
N44
R53
T49
U55
V54
V64
W61
Y47
Y56
AN50
AT47
N46
T43
T50
U57
V56
W53
W63
Y49
Y58
AN43
CPU_VCCGT_SENSE
N52
CPU_VSSGT_SENSE
P52
2
+CPU_VCCGT
Place on secondary side, underneath the package
4A
+CPU_VCCGT
RC3018
100_0402_1%
1 2
CPU_VCCGT_SENSE 36
CPU_VSSGT_SENSE 36
1 2
100_0402_1%
RC3019
x12
0.1u_0201_10V6K
CC1110
CC1111
1
1
2
2
CD@
+CPU_VCCGT
Place on secondary side, underneath the package
x12 placeholder--not Stuff
0.1u_0201_10V6K
CC1182
CC1183
1
1
@
2
2
+CPU_VCCGT
Place on secondary side, underneath the package
x12 placeholder--not Stuff
0.1u_0201_10V6K
CC1212
CC1213
1
1
@
@
2
2
+CPU_VCCGT
Place on the same side
1U x2>10U x2>47U x9
1
1
CC1122
2
2
1U_0201_6.3V6-K
CPU_CORE
Place on secondary side, underneath the package
X20
CC1095
1
2
CC1103
1
2
CD@
CPU_CORE
Place on secondary side, underneath the package
X12 placeholder not stuff
CC1206
1
@
2
0.1u_0201_10V6K
0.1u_0201_10V6K
0.1u_0201_10V6K
CC1113
CC1112
1
1
1
2
2
2
0.1u_0201_10V6K
0.1u_0201_10V6K
0.1u_0201_10V6K
CC1184
CC1185
1
1
@
0.1u_0201_10V6K
@
@
CC1123
1U_0201_6.3V6-K
0.1u_0201_10V6K
CD@
0.1u_0201_10V6K
0.1u_0201_10V6K
@
1
@
@
2
2
2
0.1u_0201_10V6K
0.1u_0201_10V6K
CC1214
CC1215
1
1
1
@
@
2
2
2
1
1
1
@
CC1125
CC1124
2
2
2
10U_0402_6.3V6-M
10U_0402_6.3V6-M
0.1u_0201_10V6K
0.1u_0201_10V6K
CC1097
CC1096
1
1
1
2
2
2
0.1u_0201_10V6K
0.1u_0201_10V6K
CC1105
CC1104
1
1
1
2
2
2
CD@
0.1u_0201_10V6K
0.1u_0201_10V6K
CC1207
CC1208
1
1
1
@
@
2
2
2
0.1u_0201_10V6K
0.1u_0201_10V6K
CC1115
CC1114
1
2
0.1u_0201_10V6K
0.1u_0201_10V6K
CC1187
CC1186
1
@
2
0.1u_0201_10V6K
0.1u_0201_10V6K
CC1216
CC1217
1
@
2
22U_0603_6.3V6-M
22U_0603_6.3V6-M
1
CC1179
CC1151
2
0.1u_0201_10V6K
0.1u_0201_10V6K
CC1098
CC1099
1
2
0.1u_0201_10V6K
0.1u_0201_10V6K
CC1106
CC1107
1
2
0.1u_0201_10V6K
0.1u_0201_10V6K
CC1209
CC1210
1
2
1
0.1u_0201_10V6K
0.1u_0201_10V6K
0.1u_0201_10V6K
0.1u_0201_10V6K
0.1u_0201_10V6K
CC1118
CC1117
CC1116
1
2
0.1u_0201_10V6K
CC1188
1
@
@
2
0.1u_0201_10V6K
CC1219
1
@
@
2
22U_0603_6.3V6-M
1
CC1194
2
0.1u_0201_10V6K
CC1100
1
2
0.1u_0201_10V6K
CC1108
1
2
0.1u_0201_10V6K
CC1201
1
@
2
1
1
1
2
2
2
0.1u_0201_10V6K
0.1u_0201_10V6K
CC1189
CC1190
1
1
1
@
@
2
2
2
0.1u_0201_10V6K
0.1u_0201_10V6K
CC1218
CC1221
1
1
1
@
@
2
2
2
22U_0603_6.3V6-M
1
CC1172
2
0.1u_0201_10V6K
0.1u_0201_10V6K
CC1101
CC1102
1
1
1
2
2
2
0.1u_0201_10V6K
0.1u_0201_10V6K
CC1198
CC1109
1
1
1
2
2
2
0.1u_0201_10V6K
0.1u_0201_10V6K
CC1202
CC1203
1
1
1
@
@
2
2
2
CC1121
CC1120
CC1119
1
1
2
2
CD@
0.1u_0201_10V6K
0.1u_0201_10V6K
CC1191
CC1192
CC1193
1
1
@
2
2
0.1u_0201_10V6K
0.1u_0201_10V6K
CC1220
CC1222
CC1223
1
1
@
@
2
2
0.1u_0201_10V6K
0.1u_0201_10V6K
CC1196
CC1197
1
2
0.1u_0201_10V6K
0.1u_0201_10V6K
CC1199
CC1200
1
2
0.1u_0201_10V6K
0.1u_0201_10V6K
CC1204
CC1205
1
@
2
0.1u_0201_10V6K
0.1u_0201_10V6K
0.1u_0201_10V6K
CPU_CORE
Place on secondary side, underneath the package
X8
1
1
CC1086
CC1085
2
2
10U_0402_6.3V6M
10U_0402_6.3V6M
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.
3
2014/11/15
2014/11/15
2014/11/15
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2013/08/05
2013/08/05
2013/08/05
1
1
1
1
CC1082
CC1084
CC1080
CC1083
2
2
2
2
10U_0402_6.3V6-M
10U_0402_6.3V6M
10U_0402_6.3V6M
CD@
Title
Title
Title
MCP (Power)
MCP (Power)
MCP (Power)
Size
Size
Size
Document Number Rev
Document Number Rev
Document Number Rev
C
C
C
Monday, August 17, 2015
Monday, August 17, 2015
Monday, August 17, 2015
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
1
CC1081
CC1087
2
2
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
Miix4
Miix4
Miix4
11 37
11 37
11 37
1
1.0
1.0
1.0
5
+CPU_VDDQ +CPU_VCCIO +CPU_VCCSA
2A
AH64
BA27
BA37
BA49
BP32
BP50
AK64
BA29
BA41
BA51
BP34
BP56
AT64
BA31
BA43
BN64
VDDQC
VCCST
VCCSTG
VCCPLL_OC
VCCPLL
BP40
BP58
AV64
BA33
BA45
BP24
BP42
BP64
BA25
BA35
BA47
BP26
BP48
BA39
V26
Y26
R26
T26
AE27
AF27
R27
T27
@
D D
1.0V 100mA
1.0V 100mA
SKYLAKE_ULX
UC1N
VDDQ_01
VDDQ_02
VDDQ_03
VDDQ_04
VDDQ_05
VDDQ_06
VDDQ_07
VDDQ_08
VDDQ_09
VDDQ_10
VDDQ_11
VDDQ_12
VDDQ_13
VDDQ_14
VDDQ_15
VDDQ_16
VDDQ_17
VDDQ_18
VDDQ_19
VDDQ_20
VDDQ_21
VDDQ_22
VDDQ_23
VDDQ_24
VDDQ_25
VDDQ_26
VDDQ_27
VDDQ_28
VDDQ_29
VDDQC
VCCST_01
VCCST_02
VCCSTG_03
VCCSTG_04
VCCPLL_OC_01
VCCPLL_OC_02
VCCPLL_01
VCCPLL_02
CPU POWER 3 OF 4
SKYLAKE-Y_FCBGA1515
?
14 OF 20
VCCIO_13
VCCIO_12
VCCIO_11
VCCIO_10
VCCIO_09
VCCIO_08
VCCIO_07
VCCIO_06
VCCIO_05
VCCIO_04
VCCIO_03
VCCIO_02
VCCIO_01
VCCIO_DDR_26
VCCIO_DDR_25
VCCIO_DDR_24
VCCIO_DDR_23
VCCIO_DDR_22
VCCIO_DDR_21
VCCIO_DDR_20
VCCIO_DDR_19
VCCIO_DDR_18
VCCIO_DDR_17
VCCIO_DDR_16
VCCIO_DDR_15
VCCIO_DDR_14
VCCIO_DDR_13
VCCIO_DDR_12
VCCIO_DDR_11
VCCIO_DDR_10
VCCIO_DDR_09
VCCIO_DDR_08
VCCIO_DDR_07
VCCIO_DDR_06
VCCIO_DDR_05
VCCIO_DDR_04
VCCIO_DDR_03
VCCIO_DDR_02
VCCIO_DDR_01
VCCIO_SENSE
VSSIO_SENSE
Sustain voltage for processor standby modes
+DDR_1.2V +CPU_VDDQ
Need short
JC1
@
2
112
JUMP_43X79
Processor PLLs power rails
C C
+CPU_VDDQ VCCPLL_OC
+CPU_VDDQ VDDQC
B B
RC275
1 2
0_0402_5%
UN_PLL_OC@
system memory clk power
1 2
R30100_0603_5%
EC_VCCST_PWREN25
0.1u_0201_10V6K
CC1173
1
2
When PCH is idle and processor is in C10 state,
PCH_SLP_S0#8,25
EC_SUS_VCCP25,34
VCCST : Sustain voltage for processor in Standby modes
VCCPLL : CPU PLL power rails
A A
VCCPLL_OC: CPU digital PLL power rails
VCCSTG : Gated version of VCCST
EC_SUS_VCCP
Slp_S3 enable
5
+CPU_VCCST VCCST
Processor PLLs power rails
+CPU_VCCST VCCPLL
+5VALW
RC1577 0_0402_5%
B+
RC63
EN_VCCST#
1 2
47K_0402_5%
1 2
RC62 0_0402_5%
0.1U_0402_16V4Z @
UC5
1
5
A
VCC
2
B
4
GND3Y
74LVC1G08SE-7_SOT353-5
1 2
@
R3011 0_0603_5%
R3013 0_0603_5%
QC167B
5
G
1
CC228
2
+3VALW
0.1U_0402_16V4Z
RC77 0_0402_5%
AC23
AF24
AN26
AC24
AF26
AR26
AE23
AH26
AT26
AE24
AK26
AE26
AL26
AV26
AV36
AV46
AW31
AW41
AW51
AV28
AV38
AV48
AW33
AW43
AV30
AV40
CPU_VCCSA_SENSE36
AV50
CPU_VSSSA_SENSE36
AW35
AW45
AV32
AV42
AW27
AW37
AW47
AV34
AV44
AW29
AW39
AW49
AT24
AR24
?REV = 1
12
12
0.1U_0402_16V4Z @
RC69
1 2
10K_0402_5%
QC167A
2
G
34
D
2N7002KDWH_SOT363-6
S
1
CC233
2
1 2
0.1U_0402_16V4Z @
4
+CPU_VCCIO
3A
CC1174
1
2
0.1u_0201_10V6K
CC1178
1
2
1
CC222
2
61
D
2N7002KDWH_SOT363-6
S
+5VALW
1
CC229
2
+CPU_VCCSA
RC3020
100_0402_1%
1 2
1 2
100_0402_1%
RC3021
0.1u_0201_10V6K
AON7408L_DFN8-5
QC12
5
D
RC75
1 2
47K_0402_5%
+CPU_VCCSA_DDR
RC3022
100_0402_1%
12
12
100_0402_1%
RC3023
+CPU_VCCIO
CPU_VCCIO_SENSE 34
CPU_VSSIO_SENSE 34
Gated sustain voltage for processor standby modes
+CPU_VCCSTG VCCSTG
R3012 0_0603_5%
+CPU_VCCSA +CPU_VCCSA_DDR
RC1501 0_0603_5%
1
S1
2
S2
3
S3
G
4
1
@
CC223
0.01U_0402_25V7K
2
EN_VCCST#
0.1U_0402_16V4Z @
B+
RC74
1 2
10K_0402_5%
EN_VCCSTG#
2
34
D
QC170B
5
G
2N7002KDWH_SOT363-6
S
PCH_SLP_S0#
EC_SUS_VCCP
Slp_S3 enable
4
4
.1A
CPU_VCCSA_SENSE
CPU_VSSSA_SENSE
12
12
12
R3028
62K_0402_5%
AO5804EL_SC89-6
1
2
61
D
QC170A
G
S
RC1578
AA29
VCCSA_01
AF30
VCCSA_02
AN29
VCCSA_03
L30
VCCSA_04
T30
VCCSA_05
AC29
VCCSA_06
AH29
VCCSA_07
AN30
VCCSA_08
M31
VCCSA_09
V29
VCCSA_10
AC30
VCCSA_11
AK29
VCCSA_12
AR29
VCCSA_13
N30
VCCSA_14
Y29
VCCSA_15
AE29
VCCSA_16
AK30
VCCSA_17
R29
VCCSA_18
Y30
VCCSA_19
AF29
VCCSA_20
AL29
VCCSA_21
T29
VCCSA_22
AT29
VCCSA_DDR_01
AT30
VCCSA_DDR_02
M29
VCCSA_SENSE
N28
VSSSA_SENSE
@
1
2
+CPU_VCCST+1.0VALW
12
RC70
470_0603_5%
@
6
QC168A
@
2
1
AON7408L_DFN8-5
QC13
5
D
CC224
2N7002KDWH_SOT363-6
UC6
1
A
VCC
2
B
GND3Y
74LVC1G08SE-7_SOT353-5
VCCPLL_OC@
1 2
@
SKYLAKE_ULX
UC1O
CPU POWER 4 OF 4
SKYLAKE-Y_FCBGA1515
0.1u_0201_10V6K
CC1175
1
S1
2
S2
3
S3
G
4
1
CC225
0.01U_0402_25V7K
2
EN_VCCSTG#
+3VALW
0.1U_0402_16V4Z
5
4
0_0402_5%
3
?
15 OF 20
VCCG0_12
VCCG0_11
VCCG0_10
VCCG0_09
VCCG0_08
VCCG0_07
VCCG0_06
VCCG0_05
VCCG0_04
VCCG0_03
VCCG0_02
VCCG0_01
VCCG1_12
VCCG1_11
VCCG1_10
VCCG1_09
VCCG1_08
VCCG1_07
VCCG1_06
VCCG1_05
VCCG1_04
VCCG1_03
VCCG1_02
VCCG1_01
+CPU_VCCG0
AA35
R38
Y35
AA38
T35
Processor IA cores gated power rail,
Y38
connects to board capacitors for filtering.
AC35
T38
AC38
V35
R35
V38
+CPU_VCCG1
AF35
AK38
AR35
AF38
AL35
AR38
AH35
AL38
AH38
AN35
AK35
AN38
?REV = 1
2
Place as close to the package as possible
+CPU_VCCIO
1U_0201_6.3V6-K
1
@
CC1152
2
+CPU_VDDQ
Place on secondary side, underneath the package
x9
0.1u_0201_10V6K
0.1u_0201_10V6K
0.1u_0201_10V6K
CC1162
CC1985
CC1986
1
1
1
2
2
2
+CPU_VDDQ
Place on secondary side, underneath the package
x9
0.1u_0201_10V6K
0.1u_0201_10V6K
0.1u_0201_10V6K
CC1987
CC1988
CC1232
1
1
1
2
2
2
CD@
+CPU_VCCSTG+1.0VALW
12
RC76
12
470_0603_5%
R3029
@
62K_0402_5%
@
3
QC168B
5
1
CC234
VCCPLL_OC@
2
0_0402_5%
VCCPLL_OC@
Issued Date
Issued Date
Issued Date
@
4
+5VALW
1
CC230
2
AO5804EL_SC89-6
1 2
RC98
0.1U_0402_16V4Z @
Security Classification
Security Classification
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.
3
+CPU_VCCIO
1
2
1
2
1
2
22U_0603_6.3V6-M
CC1153
0.1u_0201_10V6K
CC1163
0.1u_0201_10V6K
CC1233
1 2
2014/11/15
2014/11/15
2014/11/15
1U_0201_6.3V6-K
1
CC1224
2
0.1u_0201_10V6K
0.1u_0201_10V6K
0.1u_0201_10V6K
CC1165
CC1164
1
1
2
2
0.1u_0201_10V6K
CC1234
CC1235
1
1
2
2
+CPU_VCCG1
Place on secondary side, underneath the package
x6
0.1u_0201_10V6K
CC1969
1
1
2
2
+CPU_VCCG1
CD@
Place on secondary side, underneath the package
x6
0.1u_0201_10V6K
CC1970
1
1
2
2
B+
VCCPLL_OC@
RC80
EN_VCCPLL_OC#
47K_0402_5%
VCCPLL_OC@
VCCPLL_OC@
0.1u_0201_10V6K
CC1166
CC1167
1
1
2
2
CD@
0.1u_0201_10V6K
0.1u_0201_10V6K
0.1u_0201_10V6K
CC1236
CC1237
1
1
2
2
CD@
0.1u_0201_10V6K
0.1u_0201_10V6K
CC1974
CC1975
CC1971
1
1
2
2
CD@
0.1u_0201_10V6K
0.1u_0201_10V6K
CC1972
CC1973
CC1976
1
1
2
2
0.1U_0402_16V4Z @
RC82
1 2
10K_0402_5%
QC171A
2
G
34
D
QC171B
5
G
2N7002KDWH_SOT363-6
S
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
0.1u_0201_10V6K
CC1229
1
2
0.1u_0201_10V6K
CC1238
1
2
0.1u_0201_10V6K
0.1u_0201_10V6K
CC1977
1
2
CD@
0.1u_0201_10V6K
0.1u_0201_10V6K
CC1978
1
2
1
CC226
2
61
D
2N7002KDWH_SOT363-6
S
VCCPLL_OC@
+CPU_VCCIO
lace on secondary side, underneath the package
P
x9
0.1u_0201_10V6K
0.1u_0201_10V6K
0.1u_0201_10V6K
0.1u_0201_10V6K
CC1160
CC1158
CC1159
CC1161
1
1
1
2
2
CD@
+CPU_VCCIO
Place on secondary side, underneath the package
x4
0.1u_0201_10V6K
0.1u_0201_10V6K
CC1156
CC1155
1
1
2
2
+CPU_VCCIO
Place on secondary side, underneath the package
x7 palceholder
0.1u_0201_10V6K
0.1u_0201_10V6K
CC1246
CC1247
1
1
@
@
@
2
2
+CPU_VCCIO
0.1u_0201_10V6K
CC1243
CC1244
1
1
@
@
2
2
+CPU_VCCSA
Place on secondary side, underneath the package
x10 placeholder
0.1u_0201_10V6K
0.1u_0201_10V6K
CC1139
CC1140
1
1
@
@
@
2
2
+CPU_VCCSA
0.1u_0201_10V6K
0.1u_0201_10V6K
CC1230
CC1231
1
1
0.1u_0201_10V6K
CC1979
CC1980
2
1
2
0.1u_0201_10V6K
0.1u_0201_10V6K
+CPU_VCCSA_DDR
0.1u_0201_10V6K
CC1239
S1
S2
S3
G
4
1
CC227
0.01U_0402_25V7K
2
1
2
CD@
1
2
3
VCCPLL_OC@
EN_VCCPLL_OC#
2
CC1240
1
2
1
2
1
2
AON7408L_DFN8-5
QC15
5
D
VCCPLL_OC@
2013/08/05
2013/08/05
2013/08/05
1
1
2
2
2
0.1u_0201_10V6K
0.1u_0201_10V6K
CC1242
CC1157
1
1
2
2
CD@
0.1u_0201_10V6K
0.1u_0201_10V6K
CC1248
CC1249
1
1
1
@
@
2
2
2
Place on secondary side, underneath the package
x3 palceholder
0.1u_0201_10V6K
0.1u_0201_10V6K
CC1245
1
@
2
0.1u_0201_10V6K
0.1u_0201_10V6K
CC1141
CC1142
1
1
1
@
@
2
2
2
Place as close to the package as possible
1U_0201_6.3V6-K
1
@
CC1195
22U_0402_4V6-M
CC1211
2
Place on secondary side, underneath the package
for VCCSA_DDR
0.1u_0201_10V6K
0.1u_0201_10V6K
CC1255
CC1256
1
1
@
2
2
+CPU_VCCG0
Place on secondary side, underneath the package
x6
0.1u_0201_10V6K
0.1u_0201_10V6K
CC1959
CC1957
1
1
2
2
+CPU_VCCG0
CD@
Place on secondary side, underneath the package
x6
0.1u_0201_10V6K
0.1u_0201_10V6K
CC1958
CC1960
1
1
2
2
VCCPLL_OC+CPU_VDDQ
12
R3030
@
62K_0402_5%
QC172A
2
AO5804EL_SC89-6
Title
Title
Title
MCP(Power1)
MCP(Power1)
MCP(Power1)
Size
Size
Size
Document Number Rev
Document Number Rev
Document Number Rev
Custom
Custom
Custom
Monday, August 17, 2015
Monday, August 17, 2015
Monday, August 17, 2015
Date: Sheet of
Date: Sheet of
Date: Sheet of
0.1u_0201_10V6K
CC1168
0.1u_0201_10V6K
CC1250
0.1u_0201_10V6K
CC1143
1
2
1
2
1
2
12
6
1
RC93
470_0603_5%
@
CC1169
1
2
CD@
CC1251
1
@
2
CC1144
1
@
2
CC1150
22U_0402_4V6-M
0.1u_0201_10V6K
CC1961
1
2
0.1u_0201_10V6K
CC1962
1
2
350mA
@
1
0.1u_0201_10V6K
1
2
0.1u_0201_10V6K
1
@
2
0.1u_0201_10V6K
1
@
2
0.1u_0201_10V6K
CC1963
0.1u_0201_10V6K
CC1964
Miix4
Miix4
Miix4
1
0.1u_0201_10V6K
0.1u_0201_10V6K
0.1u_0201_10V6K
CC1171
CC1241
CC1170
1
1
2
2
0.1u_0201_10V6K
CC1252
0.1u_0201_10V6K
0.1u_0201_10V6K
0.1u_0201_10V6K
CC1154
CC1253
CC1145
1
@
2
0.1u_0201_10V6K
CC1965
1
2
CD@
0.1u_0201_10V6K
CC1966
1
2
1
@
2
0.1u_0201_10V6K
CC1967
1
2
0.1u_0201_10V6K
CC1968
1
2
12 37
12 37
12 37
CC1254
1
@
2
1.0
1.0
1.0
0.1u_0201_10V6K
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