Lenovo LG X13 Schematics

5

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GRATIS - FOR FREE

4

3

2

1

VTERM(+0.9V)

UL1 NB Block Diagram

2009.05.06

VTT(+1.05V)
+1.5VSUS

D D

+1.5V
+1.8VSUS
+1.8V
+2.5V
+3VPCU
+3.3V
+3.3VSUS
LCD_3.3V

CRT

P 19

LCD_5V
+5V

C C

10/100 Ethernet

RTL8103EL-GR

B B

RJ-45

P 16

P 16

10.1" panel

P 15

Mini PCI-E Card

Wireless LAN

P 20

LVDS

PCI-E

Diamondville

VCORE:+1.196 ~ +0.748
VCCP:+1.05V
VCCA:+1.8V or +1.5V

P 4,5

FSB

945GMS

HOST P 6
DDR P 7
LVDS, DMI, DDR CLK P 8
POWER P 9
GND P 10

P 6,7,8,9,10

DMI

ICH7M

RTC, AC97, SATA, IDE, LPC, CPU P 11
PCI-E, USB, DMI, PCI P 12
SMB, GPIO, CLK P 13

VID[0:6]

+/- CPU_CLK

+/- HCLK

CHA

DDRII-SODIMM

USB2.0

Camera

P 15

Bluetooth

P 19

SATA

CPU VCORE

Clock Gengerator

RTM875N-606-VD-GRT

P 14

USB PORT X 3

P 18,19

SATA HDD

Card Reader

Realtek RTS5159

P 18

P 19

P 27

P 3

WWAN

P 20

HDA CODEC

ALC272

HD Audio

P 19

Audio
Amplifier

A A

Digital MIC

P 15

5

Audio CONN
(Phone/ MIC)

P 19

SPEAKER
CONN

P 19 P 16 P 21

4

Int. KB T/P

P 11,12,13

LPC BUS

EC

KB3926QF

P 21

3

Charger

P 23

SPI
Flash

P 21

Battery

P 23

2

Quanta Computer Inc.

Size Document Number R ev

Block Diagram

Date: Sheet of

PROJECT :

UL1

1

1 30Friday, May 08, 2009

1A

5

4

3

2

1

+5VPCU

SW

D D

SUSON

+5VSUS

SW

+5V

MAINON

SW

+5VPCU

VIN

C C

Always ON

PWM

+3VPCU

+3VPCU

SW

+3VSUS

S5_ON

+5V_S5

SUSON

SW

+3V

MAINON

LDO

+2.5V

MAINON

B B

SW

S5_ON

VIN

VIN

VRON

PWM

MAINON

+3V_S5

VCC_CORE

+1.05V

PWM

+1.5V

A A

VIN

SUSON

5

4

SUSON

PWM

+1.8VSUS

3

Quanta Computer Inc.

Size Document Number R ev

Block Diagram

2

Date: Sheet of

PROJECT :

UL1

1

2 30Friday, May 08, 2009

1A

5

[e-mail]
GRATIS - FOR FREE

4

3

2

1

Clock Generator

PM_STPPCI#

+1.05V_VDD

+3V

L10

D D

C C

PBY160808T-301Y-N_6

PCLK_DEBUG21

LCLK_EC22

PCLK_ICH12

CLKUSB_4813

14M_ICH13

C192

0.1u/10V_4
C159

0.1u/10V_4 R228 10K_4
C206
10u/10V_8
C174

0.1u/10V_4
C183

0.1u/10V_4
C191

0.1u/10V_4
C190

0.1u/10V_4
C197
10u/10V_8

R261 33_4

T29

R266 33_4

R267 33_4

R254 22_4

CLK_BSEL0

R244 2.2K_4
R259 10K_4

R260 33_4

C345

CG_XIN

27p/50V_4

21

CL=20p

C341
27p/50V_4

14.318MHZ

CG_XOUT

27M_SEL

CG_XIN
CG_XOUT

Y3

C156
10u/10V_8

+1.05V_VDD

PCLK_DEBUG_R
PCLK_PCM_R

PCLK_OZ129_R

PCLK_591_R

PCLK_ICH_R

FSA
FSBCLK_BSEL1
FSC

VDD

VDD

VDD

VDD

VDD

VDD

C155
10u/10V_8

9
16
23

4
46

62
19

27
33
52
43
56

8
10
11
12
13
14

3

2
17
64

5
65
15
18
22
26
59
30
36
49

1

RTM875N-606-VD-GRT,SLG8SP513VTR ,ICS9LPRS365BKLFT

C182

0.1u/10V_4

U14

VDD_PCI
VDD_48
VDD_PLL3
VDD_REF

VDD_SRC
VDD_CPU

VDD_96_IO
VDD_PLL3_IO
VDD_SRC_IO_1
VDD_SRC_IO_3
VDD_SRC_IO_2
VDD_CPU_IO

PCI0/CR#_A
PCI1/CR#_B
PCI2/TME
PCICLK3
PCICLK4/27_SELECT
PCIF5/ITP_EN
XTAL_IN
XTAL_OUT
USB_48/FSA
FSB/TEST/MODE
REF0/FSC/TESTSEL

VSS_BODY
VSS_PCI
VSS_48
VSS_IO
VSS_PLL3
VSS_CPU
VSS_SRC1
VSS_SRC2
VSS_SRC3
VSS_REF

CK505

SRC5/PCI_STOP#

SRC5#/CPU_STOP#

CKPWRGD/PWRDWN#

IO_VOUT

SCLK

SDA

CPU0

CPU0#

CPU1

CPU1#

SRC8/ITP

SRC8#/ITP#

SRC10

SRC10#

SRC11/CR#_H

SRC9

SRC9#

SRC7/CR#_F

SRC7#/CR#_E

SRC6

SRC6#

SRC4

SRC4#

SRC3/CR#_C

SRC3#/CR#_D

SRC2/SATA

SRC2#/SATA#

SRC1/SE1

SRC1#/SE2

SRC0/DOT96

C172

0.1u/10V_4

C160

0.1u/10V_4

SRC11#/CR#_G

SRC0#/DOT96#

RTM875N-606-VD-GRT

55

SMBCK1

7

SMBDT1

6

PM_STPPCI#

45

PM_STPCPU#

44

CLK_CPU_BCLK

61

CLK_CPU_BCLK#

60

CLK_MCH_BCLK

58

CLK_MCH_BCLK#

57

CLK_PCIE_MINI2&4_R

54

CLK_PCIE_MINI2&4#_R

53

CLK_PCIE_3GPLL

41

CLK_PCIE_3GPLL#

42

CLK_MCH_OE#_R

40

NEW_CLKREQ#_R

39

PE2CLK+

37

PE2CLK-

38

CLK_PCIE_W WAN

51

CLK_PCIE_W WAN#

50

PE1CLK+

48

PE1CLK-

47
34

35

CLK_PCIE_ICH

31

CLK_PCIE_ICH#CLK_BSEL2

32

CLK_PCIE_SATA

28

CLK_PCIE_SATA#

29

DREFSSCLK

24

DREFSSCLK#

25

DREFCLK

20

DREFCLK#

21
63

C157

0.1u/10V_4

C173

0.1u/10V_4

T43
T42

R229 475/F_4
R231 475/F_4

L8

PBY160808T-301Y-N_6

C169

0.1u/10V_4

PM_STPPCI# 13
PM_STPCPU# 13

CLK_CPU_BCLK 4
CLK_CPU_BCLK# 4

CLK_MCH_BCLK 6
CLK_MCH_BCLK# 6

CLK_PCIE_3GPLL 8
CLK_PCIE_3GPLL# 8

MCH_CLKREQ# 8
CLKREQ_WLAN# 21

PE2CLK+ 21
PE2CLK- 21

CLK_PCIE_W WAN 21

CLK_PCIE_W WAN# 21

PE1CLK+ 16
PE1CLK- 16

CLK_PCIE_ICH 12
CLK_PCIE_ICH# 12

CLK_PCIE_SATA 11
CLK_PCIE_SATA# 11

DREFSSCLK 8
DREFSSCLK# 8

DREFCLK 8

DREFCLK# 8
VR_PW RGD_CK410 13

+1.05V

To SB

To CPU

To NB

To NB

To WLAN

To WWAN

To LAN

To SB

To SB

To NB

To NB

PM_STPCPU#

NEW_CLKREQ#_R

CLK_MCH_OE#_R

CLKUSB_48

14M_ICH

PCLK_ICH

FSC FSB FSA CPU SRC PCI

1 0 1 100 100 33
0 0 1 133 100 33
0 1 1 166 100 33
0 1 0 200 100 33
0 0 0 266 100 33
1 0 0 333 100 33
1 1 0 400 100 33
1 1 1 Reserved

R226 2.2K_4

R227 2.2K_4

R230 10K_4

C338 15p/50V_4

C342 *33p/50V_4

C349 *33p/50V_4

SEL0SEL1SEL2

+3V

Frequence select

03

Default

B B

R143 10K_4

ICS9LPRS365
(ALPRS365K13)

Pin 11

PCI2/TME

PCI-3

Pin 12

Pin 13

PCI-4/27M_SEL

Pin 14

PCIF-5/ITP_EN

Clock Gen I2C

A A

SMBDT13 SMBCK13SMBDT1 14,21 SMBCK1 14,21

RTM875T-606
(AL000875K06)

PCI2/TME
internal PD

PCI-3/SRC5_EN
internal PD

PCI-4/27M_SEL
internal PD

PCIF-5/ITP_EN
internal PD

2

Q13

3 1

2N7002E

PULL HIGH PULL DOWN

NO OVERCLOCKING NORMAL RUN

PIN37/38 IS SRC5

PIN 17/18 IS 27MHz

PIN 46/47 IS CPUITP PIN 46/47 IS SRC8

<MAIN>:RTM875N-606-VD-GRT QCI:AL000875000
<SECOND>:SLG8SP512TTR: QCI:AL8SP512K05

+3V +3V

R270

4.7K_4

SMBDT1 SMBCK1

(default)

PIN37/38 IS
PCI_STOP/CPU_STOP

PIN 17/18
IS SRC/DOT

(default)

(default)

(default)

+3V

+3V

+3V

2

3 1

2N7002E

R136 *10K_4

R258 *10K_4

R264 10K_4

R257 *10K_4

R263 10K_4

R262

4.7K_4

Q12

PCLK_OZ129_R

PCLK_ICH_R

PCLK_591_R

+3V

R128
*10K/F_4

1 2

R135
*10K/F_4

1 2

27M_SEL

To NB

CPU_BSEL04

CPU_BSEL14

CPU_BSEL24 MCH_BSEL2 8

+1.05V

+1.05V

+1.05V

R129 56_4

R251 *0_4
R124 *1K/F_4
R246 *1K/F_4

R247 *0_4
R245 *0_4/S
R268 *1K/F_4

R272 *0_4
R271 *0_4/S

CLK_BSEL0

CLK_BSEL1

CLK_BSEL2

R120 1K_4

R248 1K_4

R269 1K_4

MCH_BSEL0 8

MCH_BSEL1 8

Quanta Computer Inc.

Size Document Number R ev

CLOCK GENERATOR

5

4

3

2

Date: Sheet of

PROJECT :

UL1

1

3 30Friday, May 08, 2009

1A

CPU

5

4

3

2

1

04

H_A#[31:3]6

D D

H_ADSTB#06
H_REQ#[4:0]6

H_A#[31:3]6

C C

H_ADSTB#16

H_A20M#11

H_FERR#11
H_IGNNE#11
H_STPCLK#11
H_INTR11
H_NMI11
H_SMI#11

R66 *1K_4

+1.05V

R21 *1K_4

+1.05V

CAD Note: Place near CPU

B B

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16

H_AP0

T16

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

H_AP1

T17

H_IGNNE#

H_IGNNE#

U10A

P21

A[3]#

H20

A[4]#

N20

A[5]#

R20

A[6]#

J19

A[7]#

N19

A[8]#

G20

A[9]#

M19

A[10]#

H21

A[11]#

L20

A[12]#

M20

A[13]#

K19

A[14]#

J20

A[15]#

L21

A[16]#

K20

ADSTB[0]#

D17

AP0

N21

REQ[0]#

J21

REQ[1]#

G19

REQ[2]#

P20

REQ[3]#

R19

REQ[4]#

C19

A[17]#

F19

A[18]#

E21

A[19]#

A16

A[20]#

D19

A[21]#

C14

A[22]#

C18

A[23]#

C20

A[24]#

E20

A[25]#

D20

A[26]#

B18

A[27]#

C15

A[28]#

B16

A[29]#

B17

A[30]#

C16

A[31]#

A17

A[32]#

B14

A[33]#

B15

A[34]#

A14

A[35]#

B19

ADSTB[1]#

M18

AP1

U18

A20M#

T16

FERR#

J4

IGNNE#

R16

STPCLK#

T15

LINT0

R15

LINT1

U17

SMI#

D6

NC1

G6

NC2

H6

NC3

K4

NC4

K5

NC5

M15

NC6

L16

NC7

Diamondville_SC_Rev1

ADDR GROUP 1

GROUP

0

NC

ADS#
BNR#
BPRI#

ADDR

DEFER#

DRDY#
DBSY#

BR0#

IERR#

INIT#

LOCK#

CONTROL

RESET#

RS[0]#
RS[1]#
RS[2]#

TRDY#

HIT#

HITM#

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#

PRDY#
PREQ#

TCK
TDO

TMS

TRST#

BR1#

XDP/ITP SIGNALS

PROCHOT#

THRMDA

THRMDC

THERM

THERMTRIP#

BCLK[0]
BCLK[1]

H CLK

RSVD3
RSVD2
RSVD1

TDI

V19
Y19
U21

T21
T19
Y18

T20
F16

V16
W20
D15

W18
Y17
U20
W19

AA17
V20

K17
J18
H15
J15
K18
J16
M17
N16
M16
L17
K16
V15

G17
E4
E5

H17

V11
V12

C21
C1
A3

.

IER R#

R40 56_4

H_INIT#R

R44
1K/F_4

H_RS#0
H_RS#1
H_RS#2

XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
BR1#

R34 *0_4

H_PROCHOT#_R

H_ADS# 6
H_BNR# 6
H_BPRI# 6

H_DEFER# 6
H_ DRDY# 6
H_DBSY# 6

H_BREQ#0 6

R45 330_4

H_LOCK# 6
H_CPURST# 6
H_RS#[2:0] 6

H_TRDY# 6
H_HIT# 6

H_HITM# 6

T18
T10

T19

XDP_BPM#5
XDP_TCK
XDP_TDI

T15

R74 68_4

R6822_4

H_THERMDA 18
H_THERMDC 18

PM_THRMTRIP# 8,11

CLK_CPU_BCLK 3
CLK_CPU_BCLK# 3

+1.05V

H_INIT# 11

+1.05V

PV

add test point for ICT requirement

T56
T57

XDP_TMS
XDP_TRST#

PM_SYSRST# 13

+1.05V

H_PROCHOT# 25

H_D#[63:0]6

H_DSTBN#06
H_DSTBP#06
H_DINV#06

H_D#[63:0]6

H_DSTBN#16
H_DSTBP#16
H_DINV#16

R29 *1K/F_4
R27 *1K/F_4

T14
T6

T11
T8
T13
T7

CPU_BSEL03
CPU_BSEL13
CPU_BSEL23

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15

H_DP#0

T9

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31

H_DP#1

T2

H_GTLREF
ACLKPH
DCLKPH
H_BINIT#
EDM
EXTGBREF
FORCEPR#
H_HFPLL
H_MCERR
H_RSP#

U10B

Y11

D[0]#

W10

D[1]#

Y12

D[2]#

AA14

D[3]#

AA11

D[4]#

W12

D[5]#

AA16

D[6]#

Y10

D[7]#

Y9

D[8]#

Y13

D[9]#

W15

D[10]#

AA13

D[11]#

Y16

D[12]#

W13

D[13]#

AA9

D[14]#

W9

D[15]#

Y14

DSTBN[0]#

Y15

DSTBP[0]#

W16

DINV[0]#

V9

DP#0

AA5

D[16]#

Y8

D[17]#

W3

D[18]#

U1

D[19]#

W7

D[20]#

W6

D[21]#

Y7

D[22]#

AA6

D[23]#

Y3

D[24]#

W2

D[25]#

V3

D[26]#

U2

D[27]#

T3

D[28]#

AA8

D[29]#

V2

D[30]#

W4

D[31]#

Y4

DSTBN[1]#

Y5

DSTBP[1]#

Y6

DINV[1]#

R4

DP#1

A7

GTLREF

U5

ACLKPH

V5

DCLKPH

T17

BINIT#

R6

EDM

M6

EXTBGREF

N15

FORCEPR#

N6

HFPLL

P17

MCERR#

T6

RSP#

J6

BSEL[0]

H5

BSEL[1]

G5

BSEL[2]

Diamondville_SC_Rev1

H_D#32

R3

D[32]#

H_D#33

R2

D[33]#

H_D#34

P1

D[34]#

H_D#35

DATA GRP 0 DATA GRP 1

MISC

N1

D[35]#

H_D#36

M2

D[36]#

H_D#37

P2

D[37]#

H_D#38

J3

D[38]#

H_D#39

N3

D[39]#

H_D#40

G3

D[40]#

H_D#41

H2

D[41]#

H_D#42

N2

D[42]#

H_D#43

L2

D[43]#
D[44]#
D[45]#
D[46]#
D[47]#

DP#2

D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#

DP#3

SLP#

H_D#44

M3

H_D#45

J2

H_D#46

H1

H_D#47

J1
K2
K3
L1

H_DP#2

M4

H_D#48

C2

H_D#49

G2

H_D#50

F1

H_D#51

D3

H_D#52

B4

H_D#53

E1

H_D#54

A5

H_D#55

C3

H_D#56

A6

H_D#57

F2

H_D#58

C6

H_D#59

B6

H_D#60

B3

H_D#61

C4

H_D#62

C7

H_D#63

D2
E2
F3
C5

H_DP#3

D4

COMP0

T1

COMP1

T2

COMP2

F20

COMP3

F21
R18

R17
U4
V17
N18

CORE_DET

A13

CPU_CMREF

B7

Layout note:

.

T3

T4
R206 27.4/F_4
R207 54.9/F_4
R220 27.4/F_4
R219 54.9/F_4

DATA GRP 2

DSTBN[2]#
DSTBP[2]#

DINV[2]#

DATA GRP 3

DSTBN[3]#
DSTBP[3]#

DINV[3]#

COMP[0]
COMP[1]
COMP[2]
COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD
CORE_DET

CMREF[1]

Comp0,2 connect with Zo=27.4ohm, make
trace length shorter than 0.5"

Comp1,3 connect with Zo=55ohm, make
trace length shorter than 0.5"

H_D#[63:0] 6

H_DSTBN#2 6
H_DSTBP#2 6

H_DINV#2 6

H_D#[63:0] 6

H_DSTBN#3 6
H_DSTBP#3 6

H_DINV#3 6

H_DPRSTP# 11
H_DPSLP# 11
H_DPW R# 6
H_PW RGD 11
H_CPUSLP# 6,11

T39

R23
*1K_4

R24
*1K/F_4

+1.05V

H_GTLREF

Layout note:
Zo=55ohm, 0.5" max
for GTLREF

+1.05V

R36 *1K_4
R67 *1K_4
R35 *1K_4
R71 *1K_4
R65 *1K_4
R69 *1K_4
R54 *1K_4

A A

For defensive design
reservation only in this
initial release

H_NMI
H_SMI#
H_INTR
H_STPCLK#
H_DPSLP# H_DPWR#
H_DPRSTP#
H_PWRGD

+1.05V

R210
1K/F_4

R211
2K/F_4

0.1u/10V_4

+1.05V +1.05V

R22
1K/F_4

C293

R31
2K/F_4

1u/10V_4

Layout note:
Zo=55ohm, 0.5"
max for EXTGBREF

C62

R209
1K/F_4

CPU_CMREFEXTGBREF

R208
2K/F_4

Layout note:
Zo=55ohm, 0.5"
max for GTLREF

C292

0.1u/10V_4

+1.05V

XDP_TMS
XDP_TDI
XDP_BPM#5
XDP_TCK
XDP_TRST#

R64 1K/F_4
R55 1K/F_4
R61 1K/F_4
R50 1K/F_4

R39 56_4
R53 56_4
R75 56_4
R47 56_4
R38 56_4

H_A#32
H_A#33
H_A#34
H_A#35

+1.05V

Quanta Computer Inc.

Size Document Number R ev

Diamondville(1/2)

5

4

3

2

Date: Sheet of

PROJECT :

UL1

1

4 30Friday, May 08, 2009

1A

5

[e-mail]
GRATIS - FOR FREE

4

3

2

1

CPU-2 05

+1.05V

3A

VCC_CORE

U10C

V10

VCCF

A9

VCCQ1

B9

VCCQ2

A10

VCCP1

A11

VCCP2

A12

VCCP3

B10

VCCP4

B11

VCCP5

B12

VCCP6

C10

VCCP7

C11

VCCP8

C12

VCCP9

D10

VCCP10

D11

VCCP11

D12

VCCP12

E10

VCCP13

E11

VCCP14

E12

VCCP15

F10

VCCP16

F11

VCCP17

F12

VCCP18

G10

VCCP19

G11

VCCP20

G12

VCCP21

H10

VCCP22

H11

VCCP23

H12

VCCP24

J10

VCCP25

J11

VCCP26

J12

VCCP27

K10

VCCP28

K11

VCCP29

K12

VCCP30

L10

VCCP31

L11

VCCP32

L12

VCCP33

M10

VCCP34

M11

VCCP35

M12

VCCP36

N10

VCCP37

N11

VCCP38

N12

VCCP39

P10

VCCP40

P11

VCCP41

P12

VCCP42

R10

VCCP43

R11

VCCP44

R12

VCCP45

Diamondville_SC_Rev1

VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8

VTT9
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25
VTT26
VTT27
VTT28
VTT29
VTT30
VTT31
VTT32

VCCPC64
VCCPC63
VCCPC62
VCCPC61

VCCA

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

VCCSENSE

VSSSENSE

U10D

A2

VSS1

A4

G13
G21

M13
M21

VSS2

A8

VSS4

A15

VSS5

A18

VSS6

A19

VSS7

A20

VSS8

B1

VSS9

B2

VSS10

B5

VSS11

B8

VSS12

B13

VSS13

B20

VSS14

B21

VSS15

C8

VSS16

C17

VSS17

D1

VSS18

D5

VSS19

D8

VSS20

D14

VSS21

D18

VSS22

D21

VSS23

E3

VSS24

E6

VSS25

E7

VSS26

E8

VSS27

E15

VSS28

E16

VSS29

E19

VSS30

F4

VSS31

F5

VSS32

F6

VSS33

F7

VSS34

F17

VSS35

F18

VSS36

G1

VSS37

G4

VSS38

G7

VSS39

G9

VSS41
VSS42
VSS45

H3

VSS46

H4

VSS48

H7

VSS49

H9

VSS51

H13

VSS52

H16

VSS53

H18

VSS54

H19

VSS55

J5

VSS56

J7

VSS57

J9

VSS58

J13

VSS59

J17

VSS60

K1

VSS61

K6

VSS62

K7

VSS63

K9

VSS64

K13

VSS65

K15

VSS66

K21

VSS67

L3

VSS68

L4

VSS69

L5

VSS70

L6

VSS71

L7

VSS72

L9

VSS73

L13

VSS74

L15

VSS75

L18

VSS76

L19

VSS77

M1

VSS78

M5

VSS79

M7

VSS80

M9

VSS81
VSS82
VSS83

N4

VSS84

D D

C C

B B

VSS162
VSS161
VSS160
VSS159
VSS158
VSS157
VSS156
VSS155
VSS154
VSS153
VSS152
VSS151
VSS149
VSS148
VSS147
VSS146
VSS145
VSS144
VSS143
VSS142
VSS141
VSS140
VSS139
VSS138
VSS137
VSS136
VSS135
VSS134
VSS133
VSS132
VSS131
VSS130
VSS129
VSS128
VSS127
VSS126
VSS125
VSS124
VSS123
VSS122
VSS121
VSS120
VSS119
VSS118
VSS117
VSS116
VSS115
VSS114
VSS113
VSS112
VSS111
VSS110
VSS109
VSS108
VSS107
VSS106
VSS105
VSS104
VSS103
VSS102
VSS101
VSS100

VSS99
VSS98
VSS97
VSS96
VSS95

N5
N7
N9
N13
N17
P3
P4
P5
P6
P7
P9
P13
P15
P16
P18
P19
R1
R5
R7
R9
R13
R21
T4
T5
T7
T9
T10
T11
T12
T13
T18
U3
U6
U7
U15
U16
U19
V1
V4
V6
V7
V8
V13
V14
V18
V21
W1
W5
W8
W11
W14
W17
W21
Y1
Y2
Y20
Y21
AA2
AA3
AA4
AA7
AA10
AA12
AA15
AA18
AA19
AA20

.

C9
D9
E9
F8
F9
G8
G14
H8
H14
J8
J14
K8
K14
L8
L14
M8
M14
N8
N14
P8
P14
R8
R14
T8
T14
U8
U9
U10
U11
U12
U13
U14

F14
F13
E14
E13

D7

F15
D16
E18
G15
G16
E17
G18

C13

D13

2.5A

C127

0.1u/10V_4

VCC_CORE

130mA

+V1.5S_VCCA

C84

0.1u/10V_4

.

C102

1u/10V_4

R37
100/F_4

R46
100/F_4

C128

0.1u/10V_4

C83

10u/6.3V_6

C104

1u/10V_4

R32 * 0_4/S
C79
10u/10V_8

C110

10u/6.3V_6

C105

1u/10V_4

+1.5V

TO PWR

VID0 25
VID1 25
VID2 25
VID3 25
VID4 25
VID5 25
VID6 25

VCC_CORE

VCC_SENSE 25

VSS_SENSE 25

C111
1u/10V_4

PLACE IN CAVITY

C75

10u/6.3V_6

C101

1u/10V_4

C130
1u/10V_4

C117
1u/10V_4

C115
1u/10V_4

PLACE IN CORRIDOR AND CLOSE TO CPU

C66

10u/6.3V_6

C100

1u/10V_4

C74

10u/6.3V_6

C99

1u/10V_4

C61

10u/6.3V_6

C96

1u/10V_4

C86

10u/6.3V_6

C97

1u/10V_4

10u/6.3V_6

C95

1u/10V_4

C73

PLACE IN CAVITY

C78
10u/6.3V_6

C77

10u/6.3V_6

C92

1u/10V_4

C76
10u/6.3V_6

C56

10u/6.3V_6

C103

1u/10V_4

+1.05V

+

C90

10u/6.3V_6

C106

1u/10V_4

C143
330u/2.5V_7343

C109

10u/6.3V_6

C98

1u/10V_4

C94

1u/10V_4

C93

1u/10V_4

C91

1u/10V_4

Diamondville_SC_Rev1

A A

<NO_STUFF>

Quanta Computer Inc.

Size Document Number R ev

Diamondville(2/2)

5

4

3

2

Date: Sheet of

PROJECT :

UL1

1

5 30Friday, May 08, 2009

1A

945GMS

5

4

3

2

1

06

D D

C C

B B

H_D#[63:0]4 H_A#[31:3] 4

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_XRCOMP
H_XSCOMP
H_XSWING
H_YR COMP
H_YSCOMP
H_YS WING

U9A

C4

HD0#

F6

HD1#

H9

HD2#

H6

HD3#

F7

HD4#

E3

HD5#

C2

HD6#

C3

HD7#

K9

HD8#

F5

HD9#

J7

HD10#

K7

HD11#

H8

HD12#

E5

HD13#

K8

HD14#

J8

HD15#

J2

HD16#

J3

HD17#

N1

HD18#

M5

HD19#

K5

HD20#

J5

HD21#

H3

HD22#

J4

HD23#

N3

HD24#

M4

HD25#

M3

HD26#

N8

HD27#

N6

HD28#

K3

HD29#

N9

HD30#

M1

HD31#

V8

HD32#

V9

HD33#

R6

HD34#

T8

HD35#

R2

HD36#

N5

HD37#

N2

HD38#

R5

HD39#

U7

HD40#

R8

HD41#

T4

HD42#

T7

HD43#

R3

HD44#

T5

HD45#

V6

HD46#

V3

HD47#

W2

HD48#

W1

HD49#

V2

HD50#

W4

HD51#

W7

HD52#

W5

HD53#

V5

HD54#

AB4

HD55#

AB8

HD56#

W8

HD57#

AA9

HD58#

AA8

HD59#

AB1

HD60#

AB7

HD61#

AA2

HD62#

AB5

HD63#

A10

HXRCOMP

A6

HXSCOMP

C15

HXSWING

J1

HYRCOMP

K1

HYSCOMP

H1

HYSWING

945GMS

HA3#
HA4#
HA5#
HA6#
HA7#
HA8#

HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#

HADS#
HADSTB0#
HADSTB1#

H_AVREF

HBNR#

HBPRI#

HBREQ0#

HCPURST#

HDVREF

HCLKN

HCLKP

HOST

HDBSY#

HDEFER#

HDINV0#
HDINV1#
HDINV2#
HDINV3#
HDPWR#

HDRDY#
HDSTBN0#
HDSTBN1#
HDSTBN2#
HDSTBN3#
HDSTBP0#
HDSTBP1#
HDSTBP2#
HDSTBP3#

HHIT#

HHITM#
HLOCK#
HREQ0#
HREQ1#
HREQ2#
HREQ3#
HREQ4#

HRS0#
HRS1#
HRS2#

HCPUSLP#

HTRDY#

F8
D12
C13
A8
E13
E12
J12
B13
A13
G13
A12
D14
F14
J13
E17
H15
G15
G14
A15
B18
B15
E14
H13
C14
A17
E15
H17
D17
G17

F10
C12
H16
E2
B9
C7
G8
B10
E1

AA6
AA5
C10
C6
H5
J6
T9
U6
G7
E6
F3
M8
T1
AA3
F4
M7
T2
AB3

C8
B4
C5
G9
E9
G12
B8
F12
A5
B6
G10
E8
E10

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_DVREF

H_DVREF

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2

H_ADS# 4
H_ADSTB#0 4
H_ADSTB#1 4

H_BNR# 4
H_BPRI# 4
H_BREQ#0 4
H_CPURST# 4

H_CPURST# has T topology

CLK_MCH_BCLK# 3
CLK_MCH_BCLK 3
H_DBSY# 4
H_DEFER# 4
H_DINV#0 4
H_DINV#1 4
H_DINV#2 4
H_DINV#3 4
H_DPWR# 4
H_ DRDY# 4
H_DSTBN#0 4
H_DSTBN#1 4
H_DSTBN#2 4
H_DSTBN#3 4
H_DSTBP#0 4
H_DSTBP#1 4
H_DSTBP#2 4
H_DSTBP#3 4

H_HIT# 4
H_HITM# 4
H_LOCK# 4

H_REQ#[4:0] 4

H_RS#[2:0] 4

H_CPUSLP# 4,11
H_TRDY# 4

H_XSCOMP
H_YSCOMP
H_XRCOMP
H_YR COMP

+1.05V

R51
221/F_4

H_XSWING

C129

R70

100/F_4

0.1u/10V_4

10mil wide, 20mil spacing

+1.05V

R215
221/F_4

H_YS WING

R216

C302

100/F_4

0.1u/10V_4

10mil wide, 20mil spacing

+1.05V

R217
100/F_4

H_DVREF

R218

C305

200/F_4

0.1u/10V_4

+1.05V

R222 54.9/F_4
R213 54.9/F_4
R76 24.9/F_4
R214 24.9/F_4

10mil wide, 20mil spacing
10mil wide, 20mil spacing

C304
*0.1u/10V_4

A A

Quanta Computer Inc.

Size Document Number R ev

945GMS HOST

5

4

3

2

Date: Sheet of

PROJECT :

UL1

1

6 30Friday, May 08, 2009

1A

5

[e-mail]
GRATIS - FOR FREE

945GMS DDR

D D

MDA0

AC31

MDA1

MDA[63:0]14

C C

B B

MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63

AB28
AE33

AF32
AC33
AB32
AB31
AE31
AH31
AK31

AL28
AK27
AH30

AL32

AJ28

AJ27
AH32

AF31
AH27

AF28

AJ32
AG31
AG28
AG27
AN27
AM26

AJ26

AJ25

AL27
AN26
AH25
AG26
AM12

AL11

AH9

AK9
AM11
AK11

AM8

AK8

AG9

AF9

AF8

AK6

AF7
AG11

AH6

AN6

AM6

AK3

AM5

AG2

AF3

AE7

AF6

AH5

AG3

AG5

AF5

AG19
AG21
AG20

AJ6

AL2
AL5

AJ3
AJ2

U9C

SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

SB_CAS#
SB_RAS#
SB_WE#

4

945GMS

DDR2 SYSTEM MEMORY

SA_RCVENINB

SA_RCVENOUTB

SA_BS_0
SA_BS_1
SA_BS_2

SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7

SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7

SA_DQS0#
SA_DQS1#
SA_DQS2#
SA_DQS3#
SA_DQS4#
SA_DQS5#
SA_DQS6#
SA_DQS7#

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8

SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13

SA_CAS#
SA_RAS#

SA_WEB
SB_BS_0

SB_BS_1
SB_BS_2

SB_MA0

SB_MA1

SB_MA2

SB_MA3

SB_MA4

SB_MA5

SB_MA6

SB_MA7

SB_MA8

SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13

BAA0

AK12

BAA1

AH11

BAA2

AG17

DQMA0

AB30

DQMA1

AL31

DQMA2

AF30

DQMA3

AK26

DQMA4

AL9

DQMA5

AG7

DQMA6

AK5

DQMA7

AH3

DQSA0+

AC28

DQSA1+

AJ30

DQSA2+

AK33

DQSA3+

AL25

DQSA4+

AN9

DQSA5+

AH8

DQSA6+

AM2

DQSA7+

AE3

DQSA0-

AC29

DQSA1-

AK30

DQSA2-

AJ33

DQSA3-

AM25

DQSA4-

AN8

DQSA5-

AJ8

DQSA6-

AM3

DQSA7-

AE2

MAA0

AJ15

MAA1

AM17

MAA2

AM15

MAA3

AH15

MAA4

AK15

MAA5

AN15

MAA6

AJ18

MAA7

AF19

MAA8

AN17

MAA9

AL17

MAA10

AG16

MAA11

AL18

MAA12

AG18

MAA13

AL14

SCASA#

AJ17

SRASA#

AK18

TP_SA_RCVENIN#

AN28

TP_SA_RCVENOUT#

AM28

SWEA#

AH17
AH21

AJ20
AE27

AN20
AL21
AK21
AK22
AL22
AH22
AG22
AF21
AM21
AE21
AL20
AE22
AE26
AE20

BAA[2:0] 14

DQMA0 14
DQMA1 14
DQMA2 14
DQMA3 14
DQMA4 14
DQMA5 14
DQMA6 14
DQMA7 14

DQSA0+ 14
DQSA1+ 14
DQSA2+ 14
DQSA3+ 14
DQSA4+ 14
DQSA5+ 14
DQSA6+ 14
DQSA7+ 14

DQSA0- 14
DQSA1- 14
DQSA2- 14
DQSA3- 14
DQSA4- 14
DQSA5- 14
DQSA6- 14
DQSA7- 14

MAA[12:0] 14

T38

MAA13 14

SCASA# 14
SRASA# 14

T36
T35

SWEA# 14

3

+1.05V +1.5V

+1.05V

W22

W21

W20

W14

AB10
AA10

M25
N24

M24

U22
R22
N22

M22

U21
R21
N21

M21

U20
R20
N20

M20

N19
M19

N18
M18

N17
M17

N16
M16

N15
M15

U14
R14
N14

M14

R10
N10

M10

T25
R25
P25
N25

P24

Y22
V22
T22
P22

Y21
V21
T21
P21

Y20
V20
T20
P20

Y19
P19

Y18
P18

Y17
P17

Y16
P16

Y15
P15

Y14
V14
T14
P14

T10
P10
L10

D1

A18

U9H

VCC_NCTF1
VCC_NCTF2
VCC_NCTF3
VCC_NCTF4
VCC_NCTF5
VCC_NCTF6
VCC_NCTF7
VCC_NCTF8
VCC_NCTF9
VCC_NCTF10
VCC_NCTF11
VCC_NCTF12
VCC_NCTF13
VCC_NCTF14
VCC_NCTF15
VCC_NCTF16
VCC_NCTF17
VCC_NCTF18
VCC_NCTF19
VCC_NCTF20
VCC_NCTF21
VCC_NCTF22
VCC_NCTF23
VCC_NCTF24
VCC_NCTF25
VCC_NCTF26
VCC_NCTF27
VCC_NCTF28
VCC_NCTF29
VCC_NCTF30
VCC_NCTF31
VCC_NCTF32
VCC_NCTF33
VCC_NCTF34
VCC_NCTF35
VCC_NCTF36
VCC_NCTF37
VCC_NCTF38
VCC_NCTF39
VCC_NCTF40
VCC_NCTF41
VCC_NCTF42
VCC_NCTF43
VCC_NCTF44
VCC_NCTF45
VCC_NCTF46
VCC_NCTF47
VCC_NCTF48
VCC_NCTF49
VCC_NCTF50
VCC_NCTF51
VCC_NCTF52
VCC_NCTF53
VCC_NCTF54
VCC_NCTF55
VCC_NCTF56
VCC_NCTF57
VCC_NCTF58
VCC_NCTF59
VCC_NCTF60
VCC_NCTF61
VCC_NCTF62
VCC_NCTF63
VCC_NCTF64

VTT_NCTF1
VTT_NCTF2
VTT_NCTF3
VTT_NCTF4
VTT_NCTF5
VTT_NCTF6

MCH_RSVD3
MCH_RSVD4
MCH_RSVD5
MCH_RSVD6

NCTF

945GMS

VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8

VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36
VCCAUX_NCTF37
VCCAUX_NCTF38

VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8

VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12
VSS_NCTF13
VSS_NCTF14
VSS_NCTF15
VSS_NCTF16
VSS_NCTF17
VSS_NCTF18
VSS_NCTF19

CFG19

MCH_RSVD10
MCH_RSVD11
MCH_RSVD12
MCH_RSVD13
MCH_RSVD14
MCH_RSVD15
MCH_RSVD16
MCH_RSVD17
MCH_RSVD18
MCH_RSVD19
MCH_RSVD20
MCH_RSVD21
MCH_RSVD22
MCH_RSVD23
MCH_RSVD24
MCH_RSVD25

2

AD25
AC25
AB25
AD24
AC24
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
K14
AD13
Y13
W13
V13
U13
T13
R13
P13
N13
M13
AD12
Y12
W12
V12
U12
T12
R12
P12
N12
M12
AD11
AD10
K10
AN33
AA25
V25
U25
AA22
AA21
AA20
AA19
AA18
AA17
AA16
AA15
AA14
AA13
A4
A33
B2
AN1
C1

K28

GMS CFG19: LOW=Normal

K25
K26
R24
T24
K21
K19
K20
K24
K22
J17
K23
K17
K12
K13
K16
K15

+3V

GMS_CFG19

R52
*1K_4

High=LANES
REVERSED(945GMS not
support)

1

07

A A

Quanta Computer Inc.

Size Document Number R ev

945GMS DDR

5

4

3

2

Date: Sheet of

PROJECT :

UL1

1

7 30Friday, May 08, 2009

1A

5

4

3

2

1

DMI, LVDS, DDR CLK

D D

U9B

DMI_TXN012
DMI_TXN112
DMI_TXP012
DMI_TXP112

DMI_RXN012
DMI_RXN112
DMI_RXP012
DMI_RXP112

MCLKOA0+14
MCLKOA1+14

MCLKOA0-14

C C

B B

MCLKOA1-14

DDR _VREF

R26 *0_6

DMI_TXN0
DMI_TXN1
DMI_TXP0
DMI_TXP1

DMI_RXN0
DMI_RXN1
DMI_RXP0
DMI_RXP1

T37

CKEA014
CKEA114

T1

CSA#014
CSA#114

T5

ODTA014
ODTA114

M_RCOMP#
M_RCOMP

+1.8VSUS

R25
10K_6

SB_DDR_VREF

R28
10K_6

Y29
Y32
Y28
Y31

V28
V31
V29
V32

AF33

AG1

AJ1

AM30
AG33

AF1

AK1

AN30
AN21

AN22

AF26
AF25

AG14

AF12
AK14
AH12

AJ21

AF11
AE12

AF14

AJ14

AJ12
AN12

AN14
AA33

AE1

C57

0.1u/10V_4

DMI_RXN0
DMI_RXN1
DMI_RXP0
DMI_RXP1

DMI_TXN0
DMI_TXN1
DMI_TXP0
DMI_TXP1

SM_CK0
SM_CK1

SM_CK2
SM_CK3

SM_CK0#
SM_CK1#

SM_CK2#
SM_CK3#

SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3

SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#

SMOCDCOMP0
SMOCDCOMP1

SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3

SMRCOMPN
SMRCOMPP
SMVREF0
SMVREF1

945GMS

C71

0.1u/10V_4

DMI

MCH_RSVD1
MCH_RSVD2
MCH_RSVD7
MCH_RSVD8
MCH_RSVD9

CFG/RSVD

DDR2 MUXING

ICHSYNC#

BM_BUSY#

EXT_TS0#

PM

EXT_TS1#/DPRSLPVR

THRMTRIP#

PWROK

RSTIN#

DREF_CLKN
DREF_CLKP

CLK

DREF_SSCLKN
DREF_SSCLKP

CLKREQB

C18

CFG0

E18

CFG1

G20

CFG2

G18

CFG3

GMS_CFG5

J20

CFG5

J18

CFG6

K32
K31
C17
F18
A3

CFG3 RESERVE
CFG5 L OW DMIX2 Default, HIGH DMIX4(945GMS not support)

CFG6 RESERVE

E31
G21

R_PM_EXTTS#0

F26

PM_EXTTS#1

H26
J15
AB29

RST_IN#_MCH

W27

A27
A26
J33
H33
J22

R48
*2.2K_4

M_RCOMP#
M_RCOMP

MCH_BSEL0 3
MCH_BSEL1 3
MCH_BSEL2 3

R41

R57

2.2K_4

*2.2K_4

DV-2

R63 *0_4
R59 0_4

R30 100_4

R205 80.6/F_4
R204 80.6/F_4

MCH _ICH_SYNC# 12
PM_BMBUSY# 13
PM_EXTTS#0 14
PM_DPRSLPVR 13,25
PM_THRMTRIP# 4,11
IMVP_PWRGD 13,25
PLTRST# 12,13,21,22

DREFCLK# 3
DREFCLK 3
DREFSSCLK# 3
DREFSSCLK 3
MCH_CLKREQ# 3

+1.8VSUS

CLK_PCIE_3GPLL#3
CLK_PCIE_3GPLL3

CRT_VSYNC20
CRT_HSYNC20

INT_LVDS_PWM15

INT_LVDS_BLON15

L_CTLA_CLK

L_CTLB_DATA

PHL_CLK15
PHL_DATA15

INT_LVDS_DIGON15

CRT_SCL20
CRT_SDA20

CRT_B20

R79 150/F_4

CRT_G20

R78 150/F_4

CRT_R20

R80 150/F_4

VS YNC

R56 39_4

HSYNC

R60 39_4

CRTREFSET

R49 255/F_4

L_CTLA_CLK
L_CTLB_DATA

L_IBG

R42 1 .5K/F_4

TXLCLKOUT-15
TXLCLKOUT+15

TXLOUT0-15
TXLOUT1-15
TXLOUT2-15

TXLOUT0+15
TXLOUT1+15
TXLOUT2+15

AA26

H27

J27

Y26

H20
H22
A24
A23
E25

F25
C25
D25

F27
D27
H25

H30
G29

F28
E28
G28
H28
K30
K27

J29

J30
K29

D30
C30
A30
A29

G31

F32
D31

H31
G32
C31

F33
D33

F30
E33

D32

F29

U9F

SDVOCTRL_DATA
SDVOCTRL_CLK
GCLKN
GCLKP

DDCCLK
DDCDATA
BLUE
BLUE#
GREEN
GREEN#
RED
RED#
VSYNC
HSYNC
REFSET

LBKLT_CTRL
LBKLT_EN
LCTLA_CLK
LCTLB_CLK
LDDC_CLK
LDDC_DATA
LVDD_EN
LIBG
LVBG
LVREFH
LVREFL

LACLKN
LACLKP
LBCLKN
LBCLKP

LADATAN0
LADATAN1
LADATAN2

LADATAP0
LADATAP1
LADATAP2

LBDATAN0
LBDATAN1
LBDATAN2

LBDATAP0
LBDATAP1
LBDATAP2

SDV0_TVCLKIN#

SDVO_FLDSTALL#

MISC

SDVO_TVCLKIN

SDVO_FLDSTALL

SDVO

SDVOB_GREEN#

SDVOB_BLUE#

SDVOB_GREEN

LVDS VGA

TV_DCONSEL0
TV_DCONSEL1

945GMS

EXP_COMPI

EXP_ICOMPO

SDVO_INT#

SDVO_INT

SDVOB_RED#

SDVOB_CLKN

SDVOB_RED

SDVOB_BLUE
SDVOB_CLKP

TVDAC_A
TVDAC_B
TVDAC_C

TV_REFSET

TV_IRTNA

TV

TV_IRTNB

TV_IRTNC

R28
M28

N30
R30
T29

M30
P30
T30

P28
N32
P32
T32

N28
M32
P33
R32

A21
C20
E20
G23
B21
C21
D21

G26
J26

PEG_COMP

+1.5V

+V1.5S_PCIE

R43

24.9/F_4

08

1% RES

A A

+3V

R62 10K_4
R58 *10K_4

R72 4.7K_4
R73 4.7K_4

R_PM_EXTTS#0
PM_EXTTS#1

L_CTLA_CLK
L_CTLB_DATA

Quanta Computer Inc.

Size Document Number R ev

945GMS LVDS, DMI, DDR CLK

5

4

3

2

Date: Sheet of

PROJECT :

UL1

1

8 30Friday, May 08, 2009

1A

5

[e-mail]
GRATIS - FOR FREE

945GMS POWER

+1.05V

C87

D D

C C

B B

A A

220u/2.5V_3528

+

+

C107

220u/2.5V_3528

+1.5V +V1.5S_DPLLA

BLM18PG181SN1D_6

10u/6.3V_6

L5
BLM18PG181SN1D_6

330u/2.5V_7343

L16
BLM18PG181SN1D_6

22u/6.3V_8

L17
BLM18PG181SN1D_6

22u/6.3V_8

PLACE CLOSE TO GMCH

+1.5V +V1.5S_PCIE

220u/2.5V_3528

L4
BLM18PG181SN1D_6

R33
10_4

L19 BLM18PG181SN1D_6

L7

L6
91nH

C298

C108

10u/10V_8

C141

C139

C295

C116

10u/6.3V_6

+

+

10u/10V_8

20mils

4.7u/10V_6

C140

+V1.5S_DPLLB

0.1u/10V_4

+V1.5S_HPLL

0.1u/10V_4

+V1.5S_MPLL

0.1u/10V_4

C112

10u/10V_8

4.7u/10V_6

C81

C120

C296

C297

C113

+V1.5S_3GPLL

D5

CH500H-40

C311

4.7u/10V_6

0.1u/10V_4

C118

10u/10V_8

47U/6.3V_1206

+V2.5_CRTDAC

10u/6.3V_6

C124

0.1u/10V_4

C126

C69

0.1u/10V_4

place under BGA

+1.05V

12

C123

4.7u/10V_6

+1.05V+2.5V

C312

4

C114

C82

C125

0.1u/10V_4

C67

0.1u/10V_4

PLACE IN CAVITY

C89

4.7u/10V_6

0.47u/6.3V_4

0.47u/6.3V_4C301

0.47u/6.3V_4C303

C122

0.1u/10V_4

C306

0.1u/10V_4

C134

0.47u/6.3V_4

C307

800mA

1.25A

+1.5V

2.94A

R26
P26
N26
M26
V19
U19

W18

V18
R18

W17

U17
R17

W16

V16
R16

V15
U15

AD33
AD32
AD31
AD30
AD29
AD28
AD27
AC27
AD26
AC26
AB26
AE19
AE18
AF17
AE17
AF16
AE16
AF15
AE15

H10
AE9
AD9

AD8
AD7
AD6

A14
D10

AA1

T26

T19

T18

T16

T15

J14
J10

U9

P9

L9
D9
P8

L8
D8
P7

L7
D7
A7
P6

L6

G6

D6
U5
P5

L5

G5

D5
Y4
U4
P4

L4

G4

D4
Y3
U3
P3

L3

G3

D3
Y2
U2
P2

L2

G2

D2
F1

U9D

VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21

VCC_AUX1
VCC_AUX2
VCC_AUX3
VCC_AUX4
VCC_AUX5
VCC_AUX6
VCC_AUX7
VCC_AUX8
VCC_AUX9
VCC_AUX10
VCC_AUX11
VCC_AUX12
VCC_AUX13
VCC_AUX14
VCC_AUX15
VCC_AUX16
VCC_AUX17
VCC_AUX18
VCC_AUX19
VCC_AUX20
VCC_AUX21
VCC_AUX22
VCC_AUX23
VCC_AUX24
VCC_AUX25
VCC_AUX26
VCC_AUX27
VCC_AUX28

VTT0
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25
VTT26
VTT27
VTT28
VTT29
VTT30
VTT31
VTT32
VTT33
VTT34
VTT36
VTT35
VTT37
VTT38
VTT39
VTT40

945GMS

VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1

VCCA_TVBG

VSSA_TVBG

VCCD_TVDAC

VCCDQ_TVDAC

VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2

VCCHV0
VCCHV1
VCCHV2
VCCSM0
VCCSM1
VCCSM2
VCCSM3
VCCSM4
VCCSM5
VCCSM6
VCCSM7
VCCSM8

VCCSM9
VCCSM10
VCCSM11
VCCSM12
VCCSM13
VCCSM14
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCCSM20
VCCSM21
VCCSM22
VCCSM23
VCCSM24
VCCSM25
VCCSM26
VCCSM27
VCCSM28
VCCSM29
VCCSM30
VCCSM31
VCCSM32
VCCSM33
VCCSM34
VCCSM35
VCCSM36
VCCSM37
VCCSM38
VCCSM39
VCCSM40
VCCSM41
VCCSM42
VCCSM43
VCCSM44
VCCSM45
VCCSM46
VCCSM47
VCCSM48
VCCSM49
VCCSM50
VCCSM51

VCCA_MPLL
VCCA_HPLL

VCCA_DPLLA

POWER

VCCA_DPLLB
VCCD_HMPLL1
VCCD_HMPLL2
VCCTX_LVDS0
VCCTX_LVDS1

VCC3G0
VCC3G1

VCCA_3GPLL

VCCA_3GBG
VSSA_3GBG

VCC_SYNC
VCCA_CRTDAC0
VCCA_CRTDAC1

VSSA_CRTDAC

VCCA_LVDS

VSSALVDS

3

VTT41
VTT42
VTT43
VTT44
VTT45

B20
A20
B22
A22
D22
C22
D23
E23
F20
F22
C28
B28
A28
E26
D26
C26
AB33
AM32
AN29
AM29
AL29
AK29
AJ29
AH29
AG29
AF29
AE29
AN24
AM24
AL24
AK24
AJ24
AH24
AG24
AF24
AE24
AN18
AN16
AM16
AL16
AK16
AJ16
AN13
AM13
AL13
AK13
AJ13
AH13
AG13
AF13
AE13
AN4
AM10
AL10
AK10
AH1
AH10
AG10
AF10
AE10
AN7
AM7
AL7
AK7
AJ7
AH7
AN10
AJ10
AD1
AD2
B26
J32
AE5
AD5
D29
C29
U33
T33
V26
N33
M33
J23
C24
B24
B25
B31
B32

P1
L1
G1
U1
Y1

120+24mA

DISABLE TV

20mA

40mA

+V3 .3S_VCCHY

C52

1u/10V_4

1.72A

C53

1u/10V_4

C289

1u/10V_4

C287

1u/10V_4

45mA

+V1.5S_MPLL

45mA

+V1.5S_HPLL

50mA

+V1.5S_DPLLA

50mA

+V1.5S_DPLLB

150mA

+1.5V

+V1.5S_PCIE

+1.05V

+1.5V

+1.5V

C121

0.1u/10V_4

C64

C131

1u/10V_4

0.1u/10V_4

PLACE IN CAVITY

C68

4.7u/10V_6

C290

1u/10V_4

60mA

0.4A

2mA

70mA

+2.5V +V2.5_CRTDAC +2.5V

10mA

C137

0.1u/10V_4

C119

0.01u/16V_4

+1.8VSUS

C63

4.7u/10V_6

+2.5V

C136

0.1u/10V_4

C309

0.1u/10V_4

C310

0.022u/16V_4

C72
10u/10V_8

+3V

R77 *0_4/S

C142
10u/10V_8

+

C50

330u/2.5V_7343

C132

4.7u/10V_6

C135

0.1u/10V_4

C88

0.1u/10V_4

0.1u/10V_4

+2.5V

C138

10u/10V_8

C65

+V1.5S_3GPLL

C85

0.1u/10V_4

2

C51

0.1u/10V_4

C80
10u/10V_8

C288

0.1u/10V_4

1

09

C55

0.1u/10V_4

Quanta Computer Inc.

Size Document Number R ev

945GMS POWER

5

4

3

2

Date: Sheet of

PROJECT :

UL1

1

9 30F riday, May 08, 2009

1A