Lenovo Legion Y750 Schematic

A

1 1

B

C

D

E

Compal Confidential

2 2

CML-H MB Schematic Document

LA-J561P

3 3

Rev: 1.0

2020.02.26

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2020/7/31 2020/7/31

2020/7/31 2020/7/31

2020/7/31 2020/7/31

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Cover Sheet

Cover Sheet

Cover Sheet

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Custom

Custom

Custom

LA-J561P

LA-J561P

LA-J561P

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

1 100Wednesd ay, February 26, 2020

1 100Wednesd ay, February 26, 2020

1 100Wednesd ay, February 26, 2020

E

0.2

0.2

0.2

5

Comet Lake H Block Diagram

4

3

2

1

FHD Panel
G-SYNC DD

D D

eDP x4

HDMI Conn.

eDP MUX

HDMI

eDP x4
eDP x4

Nvdia GPU

GTX 1660Ti
RTX 2060
RTX 2070 Max-Q
RTX 2080 Max-Q

DDI 1x4

DDI 1x4

PEG x16

Intel

Comet Lake- H6+2

TDP: 45W

CHA Memory Bus

1.2V DDR4 2666MHz

CHB Memory Bus

1.2V DDR4 2666MHz

A-ch DDR4-SO-DIMM X1

B-ch DDR4-SO-DIMM X 1

DMI x4

USB 2.0 x1

TBT1

Type-C Conn.

(TBT, DP, USB3.1)

USB 2.0 x1

(PCH)

Thunderbolt

PCIe x4

Titan Ridge SP

C C

CC

Power Delivery

TPS65988CE

CC

Type-C Conn.

(DP, USB3.1)

B B

USB 3.1(Gen1) x1

USB 2.0 x1

(PCH)

I2C

Parade

PS8812

NGFF (TYPE E)

WLAN/BT5.0

(Killer 1650i)

NGFF (TYPE M)

M.2 PCIE SSD(Gen3)

NGFF (TYPE M)

M.2 PCIE SSD(Gen3)

DDI (E)

USB 3.1(Gen1) x1

CNVi

PCIe x1

USB2.0.x1

PCIe x4

PCIe x4

(GPU)

Cannon Lake PCH-H

HM470

24mm x 25mm
BGA 874-Pin

0.5mm Ball Pitch

USB 3.1(Gen2) x1

USB 3.1(Gen2) x1

SPI

I2C

USB 3.1(Gen1) x1

HDA

Camera 1.0M HD

USB3.1 Gen2

Dual-port Re-driver

PI3EQX1004B1ZHEX

SPI ROM

W25Q128JVSIQ

16MB

Touch Pad

USB3.0 Redriver

Audio Codec
Realtek ALC3306

(PCH)

(PCH)

USB 3.1(Gen1) x1

HP

MIC

USB 2.0 x1

USB 3.1(Gen2) x1

USB 3.1(Gen2) x1

USB 2.0 x1

USB 2.0 x1

Combo Jack

Int. Array Mic

USB 3.1 Gen2 Conn.

USB 3.1 Gen2 Conn.

Sub Board

USB 3.1 Gen1 Conn.

I2S

RJ45 Conn.

A A

Realtek RTL8111H

(PCH)

USB 2.0 x1

MCU with LED Controller

IT8296

RGB KBL

LAN

5

4

PCIe x1

Int. KBD

I2C

LPC Bus

EC

ENE KB9542B

17" only

SATA

SATA
Redriver

I2C

I2C

3

Hall Sensor

Thermal
Sensor

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NTDI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NTDI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NTDI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTPRIOR WRI TTEN CONSENT OFCOMPA L ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTPRIOR WRI TTEN CONSENT OFCOMPA L ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTPRIOR WRI TTEN CONSENT OFCOMPA L ELECTRONICS, INC.

HDD Conn.

Compal Secret Data

Compal Secret Data

2020/7/31 2020/7/31

2020/7/31 2020/7/31

2020/7/31 2020/7/31

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Smart AMP
TAS2770

Smart AMP
TAS2770

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

CFL-H 6+2 Block Diagram

CFL-H 6+2 Block Diagram

CFL-H 6+2 Block Diagram

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

LA-J561P

LA-J561P

LA-J561P

Date: Sheet of

Date: Sheet of

Date: Sheet of

Int. Speaker

Int. Speaker

1

1.0

1.0

2 100Wednesday, February 26, 2020

2 100Wednesday, February 26, 2020

2 100Wednesday, February 26, 2020

1.0

A

Board ID Table for AD channel

Vcc

Ra

PCB Revision

Board ID /

0 --> 0.1 0
1 --> 0.2
2 --> 0.3
3 --> 0.4
4 --> 0.5

5 --> 0.6

1 1

6 --> 0.7
7 --> 0.8

8 --> 0.9

9 --> 1.0
10 --> 1.1 130K +/- 1% 1.849 V
11 --> 1.2
12 --> 1.3
13 --> 1.4
14 --> 1.5
15 --> 1.6
16 --> 1.7
17 --> 1.8
18 --> 1.9
19 --> 2.0

BOM Structure Table (1/2)

Function Stuff Note

Unit SKU

2 2

Project SKU

CFL-H SKU

DGPU SKU

HM370

PCH SKU

N18 x SKU

3 3

VRAM 6G

VRAM 8G

Intel RTD3

eSPI I/F

Debug

Panel SKU

Intel TBT TR
Intel CNVi

LAN Mode

FIN FPC

4 4

OVRM

3.3V +/- 1%

100K +/- 1%

Rb

12K +/- 1% 0.347 V
15K +/- 1%
20K +/- 1%
27K +/- 1%
33K +/- 1%
43K +/- 1%
56K +/- 1%
75K +/- 1% 1.398 V

160K +/- 1%
200K +/- 1%
240K +/- 1%
270K +/- 1%
330K +/- 1%
430K +/- 1%
560K +/- 1%
750K +/- 1%
NC

UMA@
DIS@
15@
17@
CPU1@
CPU2@
CPU3@

N18G0@
N18G1@
N18G2@
N18G3@

PCH1@

GPU1@
GPU2@
GPU3@
GPU4@

M6G@
S6G@

M8G@
S8G@

i5-9400H-R1
i9-9880H-R1
i9-9980HK-R1

HM370 QNYF

1660Ti-G0-R1
2060-G1-R1
2070-G2-R1
2080-G3-R1

X7685138L01
X7685138L02

X7685138L03
X7685138L04

RTD3@

NORTD3@
ESPI@
LPC@
CMC@

GSYNC@
NOGSYNC@
TBT@
CNVI@
8111H_SW@
8111H_LDO@
FIN1@
FIN2@
ON@
UPI@

IT8296 Control

NCP45491
US5650PQKI

V min

AD_BID

0.423 V

0.978 V

2.015 V

2.395V

2.905 V

V TYP Max

AD_BID AD_BID

0 V 0.300 V

0.354 V

0.430 V 0.438 V

0.550 V 0.559 V

0.702 V 0.713 V

0.819 V 0.831 V

0.992 V 1.006 V

1.185 V 1.200 V

1.414 V

1.650 V

1.865 V

2.031 V

2.200 V

2.329V

2.408V

2.533V

2.677 V

2.800 V

2.912 V

3.000 V

HSIO Port Table(PCH)

HSIO Port Capable

0

USB3.1_1(OTG)

12USB3.1_2

USB3.1_3

3

USB3.1_4

4

USB3.0_5

5

USB3.0_6

USB3.0_7

6

USB3.0_8

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

/ GbE

PCIE_9

PCIE_10

PCIE_11

/ SATA_0A

PCIE_12

/ GbE

/ GbE

PCIE_13

/ SATA_1BPCIE_14

PCIE_15

PCIE_16

PCIE_17 / SATA_4

PCIE_18 / SATA_5

PCIE_19

PCIE_20

PCIE_21

PCIE_22

PCIE_23

PCIE_24

/ SATA_1A

/ SATA_0B

B

V

0.36 V 0x14 - 0x1E

1.430 V

1.667 V

1.881V

2.046 V

2.215 V

2.343V

2.421V

2.544 V

2.687 V

2.808 V

2.919 V

HM470

USB3.0 PCIE

SATA

1

2

3

4

5

6

7

8

9

10

11

0

12

1

13

0

14

1

15

2

16

3

17

4

18

5

19

20

21

22

23

24

HSIO Port Table(CPU)

EC AD3

0x00 - 0x13

0x1F - 0x25
0x26 - 0x300.541 V
0x31 - 0x3A0.691 V
0x3B - 0x450.807 V
0x46 - 0x54
0x55 - 0x641.169 V
0x65 - 0x76
0x77 - 0x871.634 V100K +/- 1%

0x88 - 0x96
0x97 - 0xA4
0xA5 - 0xAF2.185 V
0xB0 - 0xB72.316V

0xB8 - 0xBF
0xC0 - 0xC92.521 V
0xCA - 0xD42.667 V
0xD5 - 0xDD2.791 V

0xDE - 0xF0
0xF1 - 0xFF3.000 V

Device

USB3.1 PORT 2

USB3.1 PORT 1

USB3.1 PORT 3

USB3.1 PORT 4

NGFF SSD2 CLK5 & & CLKREQ#5

HDD

LAN

WLAN+BT NGFF CLK3 & & CLKREQ#3

Thunderbolt
Intel Titan Ridge SP

NGFF SSD1 CLK1 & & CLKREQ#1

HSIO Port Device

DGPUPEG

DDI1

NA

NA

DDI2

NA

DDI3

eDP Embedded Display

Power State

STATE

SIGNAL

S0 (Full ON)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

PCIE CLK&CLKREQ

CLK2 & & CLKREQ#2

CLK0 & & CLKREQ#0

(DIS)

PCIE CLK&CLKREQ

CLK4 & & CLKREQ#4

SLP_S4#

SLP_S3#

LOW HIGH

LOWLOW

LOW LOW

NOTE

Left Back

Right Back

Right Fornt

Left Fornt

C

+VALW

SLP_S5#

HIGH

HIGH

USB2.0 Port Table

USB2

10

11

12

13

14

HPD

NA

NA

NA

EDP_HPD

+V

ON ON ON ONHIGH HIGH HIGH

ONONON

OFF

ON

OFFLOW

Function

USB3.1 PORT 21

USB3.1 PORT 1

2

3

USB3.1 PORT 3

4

LED Controller IT8296

5

TBT TYPE-C

6

Camera

7

DP TYPE-C

8

9

WLAN+BT NGFF

+VS

OFF

OFF

OFF

Clock

OFF

OFF

OFF

D

PCH SMBUS Address Table

PCH_SMBUS Net Name

PCH_SMBCLK
PCH_SMBDATA

PCH_SML0CLK
PCH_SML0DATA

PCH_SML1CLK
PCH_SML1DATA

Power Rail

+3V_PCH_PRIM

+3VS

+3VS

Device

JDIMM1

JDIMM3 0X52

NA

EC

EC SMBUS Address Table

EC_SMBUS Port

SMBUS Port1

EC_SMB_CK1
EC_SMB_DA1

SMBUS Port2

EC_SMB_CK2
EC_SMB_DA2

SMBUS Port4

EC_SMB_CK4
EC_SMB_DA4

Power Rail Device Address (7 bit)

+3VLP_EC

BAT

CHGR 0x09 0x12 0x13

TBT TBC TBCReserved

+3VS

PCH

GPU

Type-C PS8812

THERMAL 0x4D

USB3.1 re-driver

KB/LED

+3VS

Controller

I2C Address Table

I2C Port

I2C_0_SCL
I2C_0_SDA

I2C_1_SCL
I2C_1_SDA

Voltage Rails

Power Plane Description

VIN
BATT+
+19VB
+VCC_CORE

+VCC_GT/+VCC_GTX Sliced graphics power rail
+0.6VS_VTT

+1.05VALW System +1.0V power rail ON*
+0.95VS_VCCIO +1.0VS IO power rail
+1.05V_VCCMPHY +1.0V power for PCH MODPHY rails
+0.95VS_DGPU +0.95VS power rail for GPU

+1.5VS_MEM_GFX +1.5VS power rail for GPU/VRAM
+1.8VALW
+1.8VS System +1.8VS power rail

+2.5V DDR4 +2.5Vpp power rail ONOFFONONON
+3VALW System +3VALW always on power rail
+3VALW +3VALW power for PCH suspend rails
+3VALW_DSW +3VALW power for PCH DSW rails
+3VLP +19VB to +3VLP power rail for suspend power
+3VS

+5VALW
+5VS System +5VS power rail
+3VL_RTC RTC power

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF

Power Rail Device Address (7 bit)

+3VS

EC KB9542

+3VS

Touch Pad

Adapter power supply
Battery power supply
AC or battery power rail for power circuit
Core voltage for CPU
System Agent voltage Supply+VCC_SA OFFOFFOFFOFFON

DDR +0.6VS power rail for DDR terminator

DDR4 +1.2V power rail+1.2V_VDDQ

System +1.8V power rail

+1.8VS power rail for GPU OFF

System +3VS power rail
+3VS power rail for GPU+3VGS
System +5VALW power rail

E

Address (7 bit)

Address (8bit)
Write

0X50 0XA0

0XA4

TBC

TBC TBC

Address (8bit)
Write

0x16 TBC TBC

TBC

0x9E/0x9F

TBC TBC

0x9A

0x29

0x1F

0x52 0x53

0x3E 0X3F

TBC

TBC TBC TBC

0x15 TBC TBC

S0ix

N/A
N/A
N/A
OFF

OFF
OFF

ON
ON

ON/OFF

OFF
ON
OFF
ON
ON

ON
ON
ON
ON
ON
OFF
ON
ON
ON

S3

N/A
N/A
N/A
OFF

OFF
OFF

ON
OFF

ON/OFF

OFF
ON
OFF
ON
OFF

ON
ON
ON
ON
OFF
OFF
ON
OFF
ON

S0

N/A
N/A
N/A
ON

ON
ON

ON
ON

ON/OFF

ON
ON
ON
ON
ON

ON
ON
ON
ON
ON
ON
ON
ON
ON

0XA1

0XA3

0x9B

Address (8bit)

Write Read

S4/S5

N/A
N/A
N/A
OFF

OFF
OFF
OFF OFFON OFF OFF+VCC_EOPIO/+VCC_EDRAM Processor EOPIO/EDRAM supply

OFF

ON/OFF

OFF
OFF
OFF
ON*
OFF

ON*
ON*
ON*
ON
OFF
OFF
ON*
OFF
ON

Read

Read

DS3

N/A
N/A
N/A
OFF

OFF
OFF

OFF
OFF
OFF
OFF
ON
OFF
OFF
OFF
OFFOFFOFFON+1.8VGS

ON

ON

ON
ON
OFF
OFF
ON
OFF
ON

ME Connector ME@

EMI Components EMI@ @EMI@

ESD Components ESD@ @ESD@
RF Components RF@ @RF@

A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NTDI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NTDI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NTDI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTPRIOR WRI TTEN CONSENT OFCOMPA L ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTPRIOR WRI TTEN CONSENT OFCOMPA L ELECTRONICS, INC.

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTPRIOR WRI TTEN CONSENT OFCOMPA L ELECTRONICS, INC.

2020/7/31 2020/7/31

2020/7/31 2020/7/31

2020/7/31 2020/7/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Notes List

Notes List

Notes List

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

LA-J561P

LA-J561P

LA-J561P

Date: Sheet of

Date: Sheet of

Date: Sheet of

E

3 100Wednesday, February 26, 2020

3 100Wednesday, February 26, 2020

3 100Wednesday, February 26, 2020

1.0

1.0

1.0

A

IMVP8 VR
NCP81215MNTXG
(PU8)

NCP302045MNTXG x4

+19VB_CPU

(PUZ2/PUZ4/PUZ5/PUZ6)

NCP302045MNTXG x1

+19VB_CPU

(PUZ3)

NCP81253MNTBG

+19VB_CPU

(PU27)

N:VR_ON

+19VB_1.2VP

VIN_+0.95VS_VCCIOP

+19VB_1.05VALW

E

RT8207PGQW
(PU501)

S5 EN:SYSON
S3 EN:DDR_VTT_PG_CTRL

SY8286RAC
(PU701)

EN:SUSP#&PM_SLP_S3#

SY8288RAC
(PU702)

EN:+1.8V_PG

1 1

CHARGER
ISL88739HRZ-T

PU301)

(

+12.6V_BATT

2 2

+19VB

128000mA

32000mA

11100mA

7430mA

1500mA

6400mA

5200mA

+VCC_CORE

+VCCGT

+VCCSA

+1.2V

(PJ501/PJ502)

+0.6VS

(PJ503)

+0.95VS_VCCIO

(PJ702)

+1.05VALW

(PJ704)

BATTERY

+19VB_3/5V

RV347

RT6575DGQW

PU401)

(

EN:EC_ON

+LEDVDD

+3VALW

(PJ403)

B

G9661MF11U
(PU502)

EN:PM_SLP_S4#

SY8032ABC
(PU601)

EN:3V/5VALW_PG

G
(PU1302)

9661MF11U

RC166

R621

EM5209VF
(UC5)

EN:SYSON

EM5201V
(UC3)

EN:SUSP#

RC74

RH55

RH54

3300mA

306mA

20mA

+2.5VP

(PJ605)

+1.8VALW

(PJ601)

+1.0VS_DGPUP

PJ1303)

(

+1.2V_VCCPLL_OC

+1.2V_U3RD

+1.05V_VCCSTU

+1.05VS_VCCSTG

+1.05V_XDP

+1.05V_PCH_PRIM

+1.05V_VCCMPHY

60mA

150mA

EM5209VF
(UC5)

EM5209VF
(UG1)

C

1.05V_VCCST

+

+1.05V_VCCSFR

+

1.8V_PRIMRH161

+1.8VS

+1V8_AON
+1V8_MAIN

RH88

RH87

RH86

RH85

RH83

RH61

RH84

RH59

RH58

RH57

RH56

RH119

RH120

RA13

RC72

'RTPM4

RT6575DGQW
(PU401)

D

+3VLP

+CHGRTC_R

JRTC1

+CHGRTC

R189

+1.05V_BCLKPLL2

+1.05V_OC

+1.05V_OCPLL1

+1.05V_SRC

+1.05V_XTAL

+1.05V_VCCAMPHYPLL

+1.05V_VCCAZPLL

+1.05V_VCCCLPLLEBB

+1.05V_VCCUSB

+1.05V_CNV_HVLDO

+1.05V_FUSE

+1.05V_FHV1

+1.05V_FHV0

+1.8VS_AUDIO

+1.8VS_3VS_PGPPA

+1.8VS_TPM

E

+RTCVCC

DH1

+3VALW_EC

3 3

RL18

QW10

EM5209VF

U21)

(

EN:SUSP#

G524B2T11U
(U47)

RH162

+5VALW

(PJ401
PJ405)

VR

4 4

A

+19VB_VGA_CORE

+19VB_+1.5VS_VRAMP

RT8813DGQW
(PU801)

AON6962 x2
(PQ801/PQ802)

EN:VGA_CORE_EN

RT8237EZQW
(PU1301)

EN:1.5VSDGPU_PWR_EN

+VGA_CORE

PU802+PQ1303 +VGA_CORE

11000mA

+1.5VGS

(PJ1301)

EN:USB_PWR_EN#

G524B2T11U

U46)

(

EN:USB_CHG_EN

TPS2544RTER
(U12)

EN:USB_PWR_EN#

B

+3VALW_DSW

+3V_LAN

+3V_WLAN

+3VS

(JP3V)

+5VS

(JP5V)

+5VALW_USB1

+5VALW_USB2

+

5V_CHGUSB

EN:SD_PWR_EN

AP2330W-7
(UV14)

RHD3

RC73

RS2

R622

+1.8VS_3VS_PGPPA

+3VS_SSD

+3VS_U3RD

+3VS_DPUV18

G5016KD1U

+HDMI_5V_OUT

+5VS_HDD

C

(UV20)

EN:PCH_ENVDD

RTH3

+LCDVDD_CONN

+3VS_THM

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

Compal Secret Data

Compal Secret Data

2020/7/31 2020/7/31

2020/7/31 2020/7/31

2020/7/31 2020/7/31

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Power Map

Power Map

Power Map

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
Custom

Custom

Custom

LA-J561P

LA-J561P

LA-J561P

Date: Sheet of

Date: Sheet of

Date: Sheet of

E

4 100Wednesday, February 26, 2020

4 100Wednesday, February 26, 2020

4 100Wednesday, February 26, 2020

1.0

1.0

1.0

A

B

C

D

E

[DDX03 PWR Sequence_CFL-H 6+2_DDR4]

->S0

S3

+3VL_RTC

PCH_RTCRST#

G3->S0 S0->S3

tPCH01_Min : 9 ms

+19VB

+3VLP/+5VLP

EC_ON

1 1

+5VALW/+3VALW

PM_BATLOW#

PCH_PWR_EN (SLP_SUS#)

+1.8VALW

+1.05VALW

+1.05V_PCH_PRIM

tPCH04_Min : 9 ms

Pull-up to DSW well if not implemented.

SLP_SUS# is ignored in Non-DSx systems

tPCH06_Min : 200 us

tPCH34_Max : 20 ms

+1.05V_VCCMPHY

SUSACK#

PCH_DPWROK

EC_RSMRST#

AC_PRESENT

ON/OFF

PBTN_OUT#

2 2

tPCH02_Min : 10 ms

tPCH03_Min : 10 ms

tPLT02_Min : 0 ms Max : 90 ms

tPCH43_Min : 95 ms

inimum duration of PWRBTN# assertion = 16mS. PWRBTN# can assert before or after RSMRST#

M

PM_SLP_S0# PM_SLP_S0#

PM_SLP_S5#

ESPI_RST#

tPCH18_Min : 90 us(DSx); 95 ms(Non-DSx)

PM_SLP_S4#

SYSON

+1.05V_VCCST/VCCPLL

+1.2V_VDDQ

PM_SLP_S3#

SUSP#

+1.05VS_VCCSTG/+1.2V_VCCPLL_OC

+0.95VS_VCCIO

3 3

+5VS/+3VS/+1.8VS

EC_VCCST_PG

VR_ON

SM_PG_CTRL

+0.6VS_VTT

+VCC_SA

tCPU04 Min : 100 ns

tCPU10 Min : 1 ms

T <=10msec

T <= 30msec

T <= 30msec

tCPU19 Max : 100 ns

tCPU18 Max : 35 us

tCPU09 Min : 1 ms

+VCC_CORE

+VCC_GT

VR_PWRGD

PCH_PWROK

tCPU16 Min : 0 ns

H_CPUPWRGD

SYS_PWROK

4 4

SUS_STAT#

PCH_PLTRST#

S0->S5

+3VL_RTC

PCH_RTCRST#

+19VB

+

3VLP/+5VLP

EC_ON

+5VALW/+3VALW/+3VALW_DSW

PM_BATLOW#

PCH_PWR_EN(SLP_SUS#)

+1.8VALW

+1.05VALW

+1.05V_PCH_PRIM

+

1.05V_VCCMPHY

SUSACK#

PCH_DPWROK

EC_RSMRST#

AC_PRESENT

ON/OFF

PBTN_OUT#

PM_SLP_S5#

ESPI_RST#

PM_SLP_S4#

SYSON

+2.5V+2.5V

+1.05V_VCCST/VCCPLL

+1.2V_VDDQ

PM_SLP_S3#

USP#

S

+1.05VS_VCCSTG/+1.2V_VCCPLL_OC

+0.95VS_VCCIO

+5VS/+3VS/+1.5VS/+1.05VS

EC_VCCST_PG

VR_ON

SM_PG_CTRL

+0.675VS_VTT

+VCC_SA

+VCC_CORE

VCC_GT

+

VR_PWRGD

PCH_PWROK

H_CPUPWRGD

SYS_PWROK

SUS_STAT#

PCH_PLTRST#

Security Classification

Security Classification Compal Secret Data

Security Classification Compal Secret Data

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORI ZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NO R THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORI ZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NO R THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORI ZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NO R THE INFORMATION IT CONTAINS
MAY BE USED BY OR D ISCLOSED TO ANY THIRD PA RTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELECTRONICS, INC.

MAY BE USED BY OR D ISCLOSED TO ANY THIRD PA RTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELECTRONICS, INC.

A

B

C

MAY BE USED BY OR D ISCLOSED TO ANY THIRD PA RTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELECTRONICS, INC.

Compal Secret Data

2020/7/31 2020/7/ 31

2020/7/31 2020/7/ 31

2020/7/31 2020/7/ 31

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Power Sequence

Power Sequence

Power Sequence

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

LA-J561P

LA-J561P

LA-J561P

Date: Sheet of

Date: Sheet of

Date: Sheet of

E

5 100Wednesday, February 26, 2020

5 100Wednesday, February 26, 2020

5 100Wednesday, February 26, 2020

1.0

1.0

1.0

A

1 1

2 2

B

UC1D

K36

DDI1_TXP_0

K37

DDI1_TXN_0

J35

DDI1_TXP_1

J34

DDI1_TXN_1

H37

DDI1_TXP_2

H36

DDI1_TXN_2

J37

DDI1_TXP_3

J38

DDI1_TXN_3

D27

DDI1_AUXP

E27

DDI1_AUXN

H34

DDI2_TXP_0

H33

DDI2_TXN_0

F37
G38
F34
F35
E37

E36

F26
E26

C34
D34
B36
B34
F33
E33
C33
B33

A27
B27

DDI2_TXP_1
DDI2_TXN_1
DDI2_TXP_2
DDI2_TXN_2
DDI2_TXP_3

DDI2_TXN_3

DDI2_AUXP
DDI2_AUXN

DDI3_TXP_0
DDI3_TXN_0
DDI3_TXP_1
DDI3_TXN_1
DDI3_TXP_2
DDI3_TXN_2
DDI3_TXP_3
DDI3_TXN_3

DDI3_AUXP
DDI3_AUXN

CML_H_IP_ EXT

EDP_DISP_UTIL

PROC_AUDIO_CLK

PROC_AUDIO_SDI

PROC_AUDIO_SDO

4 of 13

EDP_TXP_0
EDP_TXN_0
EDP_TXP_1
EDP_TXN_1
EDP_TXP_2
EDP_TXN_2
EDP_TXP_3
EDP_TXN_3

EDP_AUXP
EDP_AUXN

DISP_RCOMP

C

D29
E29
F28
E28
A29
B29
C28
B28

C26
B26

EDP_DISP_ UTIL

A33

DP_RCOM P

D37

Trace Width/Space: 15 mil/ 20 mil
Max Trace Length: 600 mil

G27
G25

CPU_DISPA _SDI

G29

@

RC1 24.9_0402_1%

EDP_TXP 0 <41>
EDP_TXN 0 <41>
EDP_TXP 1 <41>
EDP_TXN 1 <41>
EDP_TXP 2 <41>
EDP_TXN 2 <41>
EDP_TXP 3 <41>
EDP_TXN 3 <41>

EDP_AUX P <41>
EDP_AUX N < 41>

TC1 TP@

1 2

RC2 20_0402_5%

12

+0.95VS_ VCCIO

D

eDP

CPU_DISPA _BCLK_R < 18>
CPU_DISPA _SDO_R <1 8>

CPU_DISPA _SDI_R <18>

E

3 3

4 4

Security Classification

Security Classification

Security Classification

2020/7/31 2020/7/31

2020/7/31 2020/7/31

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2020/7/31 2020/7/31

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

CFL-H(1/8)DDI/eDP

CFL-H(1/8)DDI/eDP

CFL-H(1/8)DDI/eDP

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Custom

Custom

Custom

LA-J561P

LA-J561P

LA-J561P

Date: Sheet of

Date: Sheet of

D

Date: Sheet

E

of

6 1 00Wednesday, February 26, 202 0

6 1 00Wednesday, February 26, 202 0

6 1 00Wednesday, February 26, 202 0

1.0

1.0

1.0

A

B

C

D

E

CHANNEL-A

1 1

DDR_A_D [0..63]<22>

2 2

3 3

For ECC DIMM

Interleaved Memory

DDR_A_D 0
DDR_A_D 1
DDR_A_D 2
DDR_A_D 3
DDR_A_D 4
DDR_A_D 5
DDR_A_D 6
DDR_A_D 7
DDR_A_D 8
DDR_A_D 9
DDR_A_D 10
DDR_A_D 11
DDR_A_D 12
DDR_A_D 13
DDR_A_D 14
DDR_A_D 15
DDR_A_D 16
DDR_A_D 17
DDR_A_D 18
DDR_A_D 19
DDR_A_D 20
DDR_A_D 21
DDR_A_D 22
DDR_A_D 23
DDR_A_D 24
DDR_A_D 25
DDR_A_D 26
DDR_A_D 27
DDR_A_D 28
DDR_A_D 29
DDR_A_D 30
DDR_A_D 31
DDR_A_D 32
DDR_A_D 33
DDR_A_D 34
DDR_A_D 35
DDR_A_D 36
DDR_A_D 37
DDR_A_D 38
DDR_A_D 39
DDR_A_D 40
DDR_A_D 41
DDR_A_D 42
DDR_A_D 43
DDR_A_D 44
DDR_A_D 45
DDR_A_D 46
DDR_A_D 47
DDR_A_D 48
DDR_A_D 49
DDR_A_D 50
DDR_A_D 51
DDR_A_D 52
DDR_A_D 53
DDR_A_D 54
DDR_A_D 55
DDR_A_D 56
DDR_A_D 57
DDR_A_D 58
DDR_A_D 59
DDR_A_D 60
DDR_A_D 61
DDR_A_D 62
DDR_A_D 63

UC1A

BR6

DDR0_DQ_0/DDR0_DQ_0

BT6

DDR0_DQ_1/DDR0_DQ_1

BP3

DDR0_DQ_2/DDR0_DQ_2

BR3

DDR0_DQ_3/DDR0_DQ_3

BN5

DDR0_DQ_4/DDR0_DQ_4

BP6

DDR0_DQ_5/DDR0_DQ_5

BP2

DDR0_DQ_6/DDR0_DQ_6

BN3

DDR0_DQ_7/DDR0_DQ_7

BL4

DDR0_DQ_8/DDR0_DQ_8

BL5

DDR0_DQ_9/DDR0_DQ_9

BL2

DDR0_DQ_10/DDR0_DQ_10

BM1

DDR0_DQ_11/DDR0_DQ_11

BK4

DDR0_DQ_12/DDR0_DQ_12

BK5

DDR0_DQ_13/DDR0_DQ_13

BK1

DDR0_DQ_14/DDR0_DQ_14

BK2

DDR0_DQ_15/DDR0_DQ_15

BG4

DDR0_DQ_16/DDR0_DQ_32

BG5

DDR0_DQ_17/DDR0_DQ_33

BF4

DDR0_DQ_18/DDR0_DQ_34

BF5

DDR0_DQ_19/DDR0_DQ_35

BG2

DDR0_DQ_20/DDR0_DQ_36

BG1

DDR0_DQ_21/DDR0_DQ_37

BF1

DDR0_DQ_22/DDR0_DQ_38

BF2

DDR0_DQ_23/DDR0_DQ_39

BD2

DDR0_DQ_24/DDR0_DQ_40

BD1

DDR0_DQ_25/DDR0_DQ_41

BC4

DDR0_DQ_26/DDR0_DQ_42

BC5

DDR0_DQ_27/DDR0_DQ_43

BD5

DDR0_DQ_28/DDR0_DQ_44

BD4

DDR0_DQ_29/DDR0_DQ_45

BC1

DDR0_DQ_30/DDR0_DQ_46

BC2

DDR0_DQ_31/DDR0_DQ_47

AB1

DDR0_DQ_32/DDR1_DQ_0

AB2

DDR0_DQ_33/DDR1_DQ_1

AA4

DDR0_DQ_34/DDR1_DQ_2

AA5

DDR0_DQ_35/DDR1_DQ_3

AB5

DDR0_DQ_36/DDR1_DQ_4

AB4

DDR0_DQ_37/DDR1_DQ_5

AA2

DDR0_DQ_38/DDR1_DQ_6

AA1

DDR0_DQ_39/DDR1_DQ_7

V5

DDR0_DQ_40/DDR1_DQ_8

V2

DDR0_DQ_41/DDR1_DQ_9

U1

DDR0_DQ_42/DDR1_DQ_10

U2

DDR0_DQ_43/DDR1_DQ_11

V1

DDR0_DQ_44/DDR1_DQ_12

V4

DDR0_DQ_45/DDR1_DQ_13

U5

DDR0_DQ_46/DDR1_DQ_14

U4

DDR0_DQ_47/DDR1_DQ_15

R2

DDR0_DQ_48/DDR1_DQ_32

P5

DDR0_DQ_49/DDR1_DQ_33

R4

DDR0_DQ_50/DDR1_DQ_34

P4

DDR0_DQ_51/DDR1_DQ_35

R5

DDR0_DQ_52/DDR1_DQ_36

P2

DDR0_DQ_53/DDR1_DQ_37

R1

DDR0_DQ_54/DDR1_DQ_38

P1

DDR0_DQ_55/DDR1_DQ_39

M4

DDR0_DQ_56/DDR1_DQ_40

M1

DDR0_DQ_57/DDR1_DQ_41

L4

DDR0_DQ_58/DDR1_DQ_42

L2

DDR0_DQ_59/DDR1_DQ_43

M5

DDR0_DQ_60/DDR1_DQ_44

M2

DDR0_DQ_61/DDR1_DQ_45

L5

DDR0_DQ_62/DDR1_DQ_46

L1

DDR0_DQ_63/DDR1_DQ_47

BA2

NC/DDR0_ECC_0

BA1

NC/DDR0_ECC_1

AY4

NC/DDR0_ECC_2

AY5

NC/DDR0_ECC_3

BA5

NC/DDR0_ECC_4

BA4

NC/DDR0_ECC_5

AY1

NC/DDR0_ECC_6

AY2

NC/DDR0_ECC_7

CML_H_IP_ EXT

DDR0_CKP_0/DDR0_CKP_0
DDR0_CKN_0/DDR0_CKN_0
DDR0_CKP_1/DDR0_CKP_1
DDR0_CKN_1/DDR0_CKN_1

DDR0_CKE_0/DDR0_CKE_0
DDR0_CKE_1/DDR0_CKE_1
DDR0_CKE_2/DDR0_CKE_2
DDR0_CKE_3/DDR0_CKE_3

DDR0_CS#_0/DDR0_CS#_0
DDR0_CS#_1/DDR0_CS#_1

DDR0_ODT_0/DDR0_ODT_0

DDR0_CAB_4/DDR0_BA_0
DDR0_CAB_6/DDR0_BA_1
DDR0_CAA_5/DDR0_BG_0

DDR0_CAB_3/DDR0_MA_16
DDR0_CAB_2/DDR0_MA_14
DDR0_CAB_1/DDR0_MA_15

DDR0_CAB_9/DDR0_MA_0
DDR0_CAB_8/DDR0_MA_1
DDR0_CAB_5/DDR0_MA_2

DDR0_CAA_0/DDR0_MA_5
DDR0_CAA_2/DDR0_MA_6
DDR0_CAA_4/DDR0_MA_7
DDR0_CAA_3/DDR0_MA_8

DDR0_CAA_1/DDR0_MA_9
DDR0_CAB_7/DDR0_MA_10
DDR0_CAA_7/DDR0_MA_11
DDR0_CAA_6/DDR0_MA_12
DDR0_CAB_0/DDR0_MA_13

DDR0_CAA_9/DDR0_BG_1

DDR0_CAA_8/DDR0_ACT#

DDR0_DQSN_0/DDR0_DQSN_0
DDR0_DQSN_1/DDR0_DQSN_1
DDR0_DQSN_2/DDR0_DQSN_4
DDR0_DQSN_3/DDR0_DQSN_5
DDR0_DQSN_4/DDR1_DQSN_0
DDR0_DQSN_5/DDR1_DQSN_1
DDR0_DQSN_6/DDR1_DQSN_4
DDR0_DQSN_7/DDR1_DQSN_5

DDR0_DQSP_0/DDR0_DQSP_0
DDR0_DQSP_1/DDR0_DQSP_1
DDR0_DQSP_2/DDR0_DQSP_4
DDR0_DQSP_3/DDR0_DQSP_5
DDR0_DQSP_4/DDR1_DQSP_0
DDR0_DQSP_5/DDR1_DQSP_1
DDR0_DQSP_6/DDR1_DQSP_4
DDR0_DQSP_7/DDR1_DQSP_5

DDR0_DQSP_8/DDR0_DQSP_8

1 OF 13

DDR0_DQSN_8/DDR0_DQSN_8

DDR CHANNEL A

NC/DDR0_CKP_2
NC/DDR0_CKN_2
NC/DDR0_CKP_3
NC/DDR0_CKN_3

NC/DDR0_CS#_2
NC/DDR0_CS#_3

NC/DDR0_ODT_1
NC/DDR0_ODT_2
NC/DDR0_ODT_3

NC/DDR0_MA_3
NC/DDR0_MA_4

NC/DDR0_PAR

NC/DDR0_ALERT#

DDR_A_C LK0

AG1

DDR_A_C LK#0

AG2

DDR_A_C LK1

AK2

DDR_A_C LK#1

AK1
AL3
AK3
AL2
AL1

AT1
AT2
AT3
AT5

AD5
AE2
AD2
AE5

AD3
AE4
AE1
AD4

AH5
AH1
AU1

AH4
AG4
AD1

AH3
AP4
AN4
AP5
AP2
AP1
AP3
AN1
AN3
AT4
AH2
AN2
AU4
AE3
AU2
AU3

AG3
AU5

BR5
BL3
BG3
BD3
AA3
U3
P3
L3

BP5
BK3
BF3
BC3
AB3
V3
R3
M3

AY3
BA3

@

DDR_A_C KE0
DDR_A_C KE1

DDR_A_C S#0
DDR_A_C S#1

DDR_A_O DT0
DDR_A_O DT1

DDR_A_B A0
DDR_A_B A1
DDR_A_B G0

DDR_A_M A16_RAS#
DDR_A_M A14_WE#
DDR_A_M A15_CAS#

DDR_A_M A0
DDR_A_M A1
DDR_A_M A2
DDR_A_M A3
DDR_A_M A4
DDR_A_M A5
DDR_A_M A6
DDR_A_M A7
DDR_A_M A8
DDR_A_M A9
DDR_A_M A10
DDR_A_M A11
DDR_A_M A12
DDR_A_M A13
DDR_A_B G1
DDR_A_A CT#

DDR_A_P AR
DDR_A_A LERT#

DDR_A_D QS#0
DDR_A_D QS#1
DDR_A_D QS#2
DDR_A_D QS#3
DDR_A_D QS#4
DDR_A_D QS#5
DDR_A_D QS#6
DDR_A_D QS#7

DDR_A_D QS0
DDR_A_D QS1
DDR_A_D QS2
DDR_A_D QS3
DDR_A_D QS4
DDR_A_D QS5
DDR_A_D QS6
DDR_A_D QS7

DDR_A_C LK0 <22>
DDR_A_C LK#0 <22>
DDR_A_C LK1 <22>
DDR_A_C LK#1 <22>

DDR_A_C KE0 <22>
DDR_A_C KE1 <22>

DDR_A_C S#0 <22>
DDR_A_C S#1 <22>

DDR_A_O DT0 <22>
DDR_A_O DT1 <22>

DDR_A_B A0 <22>
DDR_A_B A1 <22>
DDR_A_B G0 <22>

DDR_A_M A16_RAS# < 22>
DDR_A_M A14_WE# <2 2>
DDR_A_M A15_CAS# < 22>

DDR_A_M A0 <22>
DDR_A_M A1 <22>
DDR_A_M A2 <22>
DDR_A_M A3 <22>
DDR_A_M A4 <22>
DDR_A_M A5 <22>
DDR_A_M A6 <22>
DDR_A_M A7 <22>
DDR_A_M A8 <22>
DDR_A_M A9 <22>
DDR_A_M A10 <22>
DDR_A_M A11 <22>
DDR_A_M A12 <22>
DDR_A_M A13 <22>
DDR_A_B G1 <22>
DDR_A_A CT# <22>

DDR_A_P AR <22>
DDR_A_A LERT# <22>

DDR_A_D QS#0 <2 2>
DDR_A_D QS#1 <2 2>
DDR_A_D QS#2 <2 2>
DDR_A_D QS#3 <2 2>
DDR_A_D QS#4 <2 2>
DDR_A_D QS#5 <2 2>
DDR_A_D QS#6 <2 2>
DDR_A_D QS#7 <2 2>

DDR_A_D QS0 <22 >
DDR_A_D QS1 <22 >
DDR_A_D QS2 <22 >
DDR_A_D QS3 <22 >
DDR_A_D QS4 <22 >
DDR_A_D QS5 <22 >
DDR_A_D QS6 <22 >
DDR_A_D QS7 <22 >

For ECC DIMM

4 4

Security Classification

Security Classification

Security Classification

2020/7/31 2020/7/31

2020/7/31 2020/7/31

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2020/7/31 2020/7/31

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

CFL-H(2/8)DIMMA

CFL-H(2/8)DIMMA

CFL-H(2/8)DIMMA

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Custom

Custom

Custom

LA-J561P

LA-J561P

LA-J561P

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

7 1 00Wednesday, February 26, 202 0

7 1 00Wednesday, February 26, 202 0

7 1 00Wednesday, February 26, 202 0

E

1.0

1.0

1.0

A

B

C

D

E

CHANNEL-B

1 1

2 2

3 3

DDR_B_D [0..63]<23>

For ECC DIMM

DDR_B_D 0
DDR_B_D 1
DDR_B_D 2
DDR_B_D 3
DDR_B_D 4
DDR_B_D 5
DDR_B_D 6
DDR_B_D 7
DDR_B_D 8
DDR_B_D 9
DDR_B_D 10
DDR_B_D 11
DDR_B_D 12
DDR_B_D 13
DDR_B_D 14
DDR_B_D 15
DDR_B_D 16
DDR_B_D 17
DDR_B_D 18
DDR_B_D 19
DDR_B_D 20
DDR_B_D 21
DDR_B_D 22
DDR_B_D 23
DDR_B_D 24
DDR_B_D 25
DDR_B_D 26
DDR_B_D 27
DDR_B_D 28
DDR_B_D 29
DDR_B_D 30
DDR_B_D 31
DDR_B_D 32
DDR_B_D 33
DDR_B_D 34
DDR_B_D 35
DDR_B_D 36
DDR_B_D 37
DDR_B_D 38
DDR_B_D 39

DDR_B_D 40
DDR_B_D 41
DDR_B_D 42
DDR_B_D 43
DDR_B_D 44
DDR_B_D 45
DDR_B_D 46
DDR_B_D 47
DDR_B_D 48
DDR_B_D 49
DDR_B_D 50
DDR_B_D 51
DDR_B_D 52
DDR_B_D 53
DDR_B_D 54
DDR_B_D 55
DDR_B_D 56
DDR_B_D 57
DDR_B_D 58
DDR_B_D 59
DDR_B_D 60
DDR_B_D 61
DDR_B_D 62
DDR_B_D 63

UC1B

BT11

DDR1_DQ_0/DDR0_DQ_16

BR11

DDR1_DQ_1/DDR0_DQ_17

BT9

DDR1_DQ_2/DDR0_DQ_18

BR8

DDR1_DQ_3/DDR0_DQ_19

BP11

DDR1_DQ_4/DDR0_DQ_20

BN11

DDR1_DQ_5/DDR0_DQ_21

BP8

DDR1_DQ_6/DDR0_DQ_22

BN8

DDR1_DQ_7/DDR0_DQ_23

BL12

DDR1_DQ_8/DDR0_DQ_24

BL11

DDR1_DQ_9/DDR0_DQ_25

BL8

DDR1_DQ_10/DDR0_DQ_26

BJ8

DDR1_DQ_11/DDR0_DQ_27

BJ11

DDR1_DQ_12/DDR0_DQ_28

BJ10

DDR1_DQ_13/DDR0_DQ_29

BL7

DDR1_DQ_14/DDR0_DQ_30

BJ7

DDR1_DQ_15/DDR0_DQ_31

BG11

DDR1_DQ_16/DDR0_DQ_48

BG10

DDR1_DQ_17/DDR0_DQ_49

BG8

DDR1_DQ_18/DDR0_DQ_50

BF8

DDR1_DQ_19/DDR0_DQ_51

BF11

DDR1_DQ_20/DDR0_DQ_52

BF10

DDR1_DQ_21/DDR0_DQ_53

BG7

DDR1_DQ_22/DDR0_DQ_54

BF7

DDR1_DQ_23/DDR0_DQ_55

BB11

DDR1_DQ_24/DDR0_DQ_56

BC11

DDR1_DQ_25/DDR0_DQ_57

BB8

DDR1_DQ_26/DDR0_DQ_58

BC8

DDR1_DQ_27/DDR0_DQ_59

BC10

DDR1_DQ_28/DDR0_DQ_60

BB10

DDR1_DQ_29/DDR0_DQ_61

BC7

DDR1_DQ_30/DDR0_DQ_62

BB7

DDR1_DQ_31/DDR0_DQ_63

AA11

DDR1_DQ_32/DDR1_DQ_16

AA10

DDR1_DQ_33/DDR1_DQ_17

AC11

DDR1_DQ_34/DDR1_DQ_18

AC10

DDR1_DQ_35/DDR1_DQ_19

AA7

DDR1_DQ_36/DDR1_DQ_20

AA8

DDR1_DQ_37/DDR1_DQ_21

AC8

DDR1_DQ_38/DDR1_DQ_22

AC7

DDR1_DQ_39/DDR1_DQ_23

W8

DDR1_DQ_40/DDR1_DQ_24

W7

DDR1_DQ_41/DDR1_DQ_25

V10

DDR1_DQ_42/DDR1_DQ_26

V11

DDR1_DQ_43/DDR1_DQ_27

W11

DDR1_DQ_44/DDR1_DQ_28

W10

DDR1_DQ_45/DDR1_DQ_29

V7

DDR1_DQ_46/DDR1_DQ_30

V8

DDR1_DQ_47/DDR1_DQ_31

R11

DDR1_DQ_48/DDR1_DQ_48

P11

DDR1_DQ_49/DDR1_DQ_49

P7

DDR1_DQ_50/DDR1_DQ_50

R8

DDR1_DQ_51/DDR1_DQ_51

R10

DDR1_DQ_52/DDR1_DQ_52

P10

DDR1_DQ_53/DDR1_DQ_53

R7

DDR1_DQ_54/DDR1_DQ_54

P8

DDR1_DQ_55/DDR1_DQ_55

L11

DDR1_DQ_56/DDR1_DQ_56

M11

DDR1_DQ_57/DDR1_DQ_57

L7

DDR1_DQ_58/DDR1_DQ_58

M8

DDR1_DQ_59/DDR1_DQ_59

L10

DDR1_DQ_60/DDR1_DQ_60

M10

DDR1_DQ_61/DDR1_DQ_61

M7

DDR1_DQ_62/DDR1_DQ_62

L8

DDR1_DQ_63/DDR1_DQ_63

AW11

NC/DDR1_ECC_0

AY11

NC/DDR1_ECC_1

AY8

NC/DDR1_ECC_2

AW8

NC/DDR1_ECC_3

AY10

NC/DDR1_ECC_4

AW10

NC/DDR1_ECC_5

AY7

NC/DDR1_ECC_6

AW7

NC/DDR1_ECC_7

DDR1_CKP_0/DDR1_CKP_0
DDR1_CKN_0/DDR1_CKN_0
DDR1_CKP_1/DDR1_CKP_1
DDR1_CKN_1/DDR1_CKN_1

NC/DDR1_CKP_2
NC/DDR1_CKN_2
NC/DDR1_CKP_3
NC/DDR1_CKN_3

DDR1_CKE_0/DDR1_CKE_0
DDR1_CKE_1/DDR1_CKE_1
DDR1_CKE_2/DDR1_CKE_2
DDR1_CKE_3/DDR1_CKE_3

DDR1_CS#_0/DDR1_CS#_0
DDR1_CS#_1/DDR1_CS#_1

NC/DDR1_CS#_2
NC/DDR1_CS#_3

DDR1_ODT_0/DDR1_ODT_0

NC/DDR1_ODT_1
NC/DDR1_ODT_2
NC/DDR1_ODT_3

DDR1_CAB_3/DDR1_MA_16
DDR1_CAB_2/DDR1_MA_14

DDR1_CAB_1/DDR1_MA_15

DDR1_CAB_4/DDR1_BA_0
DDR1_CAB_6/DDR1_BA_1

DDR1_CAA_5/DDR1_BG_0

DDR1_CAB_9/DDR1_MA_0
DDR1_CAB_8/DDR1_MA_1
DDR1_CAB_5/DDR1_MA_2

NC/DDR1_MA_3

NC/DDR1_MA_4
DDR1_CAA_0/DDR1_MA_5
DDR1_CAA_2/DDR1_MA_6
DDR1_CAA_4/DDR1_MA_7

DDR1_CAA_3/DDR1_MA_8
DDR1_CAA_1/DDR1_MA_9

DDR1_CAB_7/DDR1_MA_10
DDR1_CAA_7/DDR1_MA_11
DDR1_CAA_6/DDR1_MA_12
DDR1_CAB_0/DDR1_MA_13

DDR1_CAA_9/DDR1_BG_1
DDR1_CAA_8/DDR1_ACT#

NC/DDR1_PAR

NC/DDR1_ALERT#

DDR1_DQSN_0/DDR0_DQSN_2
DDR1_DQSN_1/DDR0_DQSN_3
DDR1_DQSN_2/DDR0_DQSN_6
DDR1_DQSN_3/DDR0_DQSN_7
DDR1_DQSN_4/DDR1_DQSN_2
DDR1_DQSN_5/DDR1_DQSN_3
DDR1_DQSN_6/DDR1_DQSN_6
DDR1_DQSN_7/DDR1_DQSN_7

DDR1_DQSP_0/DDR0_DQSP_2
DDR1_DQSP_1/DDR0_DQSP_3
DDR1_DQSP_2/DDR0_DQSP_6
DDR1_DQSP_3/DDR0_DQSP_7
DDR1_DQSP_4/DDR1_DQSP_2
DDR1_DQSP_5/DDR1_DQSP_3
DDR1_DQSP_6/DDR1_DQSP_6
DDR1_DQSP_7/DDR1_DQSP_7

DDR1_DQSP_8/DDR1_DQSP_8
DDR1_DQSN_8/DDR1_DQSN_8

AM9
AN9
AM7
AM8
AM11
AM10
AJ10
AJ11

AT8
AT10
AT7
AT11

AF11
AE7
AF10
AE10

AF7
AE8
AE9
AE11

AH10
AH11
AF8

AH8
AH9
AR9

AJ9
AK6
AK5
AL5
AL6
AM6
AN7
AN10

AN8
AR11
AH7
AN11
AR10
AF9
AR7
AT9

AJ7
AR8

BN9
BL9
BG9
BC9
AC9
W9
R9
M9

BP9
BJ9
BF9
BB9
AA9
V9
P9
L9

AW9
AY9

DDR_B_C LK0
DDR_B_C LK#0
DDR_B_C LK1
DDR_B_C LK#1

DDR_B_C KE0
DDR_B_C KE1

DDR_B_C S#0
DDR_B_C S#1

DDR_B_O DT0
DDR_B_O DT1

DDR_B_M A16_RAS#
DDR_B_M A14_WE#
DDR_B_M A15_CAS#

DDR_B_B A0
DDR_B_B A1
DDR_B_B G0

DDR_B_M A0
DDR_B_M A1
DDR_B_M A2
DDR_B_M A3
DDR_B_M A4
DDR_B_M A5
DDR_B_M A6
DDR_B_M A7

DDR_B_M A8
DDR_B_M A9
DDR_B_M A10
DDR_B_M A11
DDR_B_M A12
DDR_B_M A13
DDR_B_B G1
DDR_B_A CT#

DDR_B_P AR
DDR_B_A LERT#

DDR_B_D QS#0
DDR_B_D QS#1
DDR_B_D QS#2
DDR_B_D QS#3
DDR_B_D QS#4
DDR_B_D QS#5
DDR_B_D QS#6
DDR_B_D QS#7

DDR_B_D QS0
DDR_B_D QS1
DDR_B_D QS2
DDR_B_D QS3
DDR_B_D QS4
DDR_B_D QS5
DDR_B_D QS6
DDR_B_D QS7

DDR_B_C LK0 <23>
DDR_B_C LK#0 <23>
DDR_B_C LK1 <23>
DDR_B_C LK#1 <23>

DDR_B_C KE0 <23>
DDR_B_C KE1 <23>

DDR_B_C S#0 <23>
DDR_B_C S#1 <23>

DDR_B_O DT0 <23>
DDR_B_O DT1 <23>

DDR_B_M A16_RAS# < 23>
DDR_B_M A14_WE# <2 3>
DDR_B_M A15_CAS# < 23>

DDR_B_B A0 <23>
DDR_B_B A1 <23>
DDR_B_B G0 <23>

DDR_B_M A0 <23>
DDR_B_M A1 <23>
DDR_B_M A2 <23>
DDR_B_M A3 <23>
DDR_B_M A4 <23>
DDR_B_M A5 <23>
DDR_B_M A6 <23>
DDR_B_M A7 <23>

DDR_B_M A8 <23>
DDR_B_M A9 <23>
DDR_B_M A10 <23>
DDR_B_M A11 <23>
DDR_B_M A12 <23>
DDR_B_M A13 <23>
DDR_B_B G1 <23>
DDR_B_A CT# <23>

DDR_B_P AR <23>
DDR_B_A LERT# <23>

DDR_B_D QS#0 <2 3>
DDR_B_D QS#1 <2 3>
DDR_B_D QS#2 <2 3>
DDR_B_D QS#3 <2 3>
DDR_B_D QS#4 <2 3>
DDR_B_D QS#5 <2 3>
DDR_B_D QS#6 <2 3>
DDR_B_D QS#7 <2 3>

DDR_B_D QS0 <23 >
DDR_B_D QS1 <23 >
DDR_B_D QS2 <23 >
DDR_B_D QS3 <23 >
DDR_B_D QS4 <23 >
DDR_B_D QS5 <23 >
DDR_B_D QS6 <23 >
DDR_B_D QS7 <23 >

For ECC DIMM

Interleaved Memory

SM_RCOM P0

1 2

RC3 12 1_0402_1%

1 2

RC4 75_0402_1%

1 2

RC5 100_0402_1%

Trace Width/Space: 15 mil/ 25 mil

4 4

A

Max Trace Length: 500 mil

B

SM_RCOM P1
SM_RCOM P2

G1

DDR_RCOMP_0

H1

DDR_RCOMP_1

J2

DDR_RCOMP_2

CML_H_IP_ EXT

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2 OF 13

DDR CHANNEL B

DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ

2020/7/31 2020/7/31

2020/7/31 2020/7/31

2020/7/31 2020/7/31

C

@

Compal Secret Data

Compal Secret Data

Compal Secret Data

BN13
BP13
BR13

Deciphered Date

Deciphered Date

Deciphered Date

+0.6V_VR EFCA
+0.6V_A_ VREFDQ
+0.6V_B_ VREFDQ

+0.6V_VR EFCA

TC2TP@

+0.6V_B_ VREFDQ

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

CFL-H(3/8)DIMMB

CFL-H(3/8)DIMMB

CFL-H(3/8)DIMMB

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Custom

Custom

Custom

LA-J561P

LA-J561P

LA-J561P

Date: Sheet of

Date: Sheet of

Date: Sheet of

8 1 00Wednesday, February 26, 202 0

8 1 00Wednesday, February 26, 202 0

8 1 00Wednesday, February 26, 202 0

E

1.0

1.0

1.0

A

B

C

D

E

PEG&DMI

1 1

To DGPU

(reversed)

PEG_CRX _GTX_P15<24>
PEG_CRX _GTX_N15<24>

PEG_CRX _GTX_P14<24>
PEG_CRX _GTX_N14<24>

PEG_CRX _GTX_P13<24>
PEG_CRX _GTX_N13<24>

PEG_CRX _GTX_P12<24>
PEG_CRX _GTX_N12<24>

PEG_CRX _GTX_P11<24>
PEG_CRX _GTX_N11<24>

PEG_CRX _GTX_P10<24>
PEG_CRX _GTX_N10<24>

PEG_CRX _GTX_P9<24>

2 2

3 3

PEG_CRX _GTX_N9<24>

PEG_CRX _GTX_P8<24>
PEG_CRX _GTX_N8<24>

PEG_CRX _GTX_P7<24>
PEG_CRX _GTX_N7<24>

PEG_CRX _GTX_P6<24>
PEG_CRX _GTX_N6<24>

PEG_CRX _GTX_P5<24>
PEG_CRX _GTX_N5<24>

PEG_CRX _GTX_P4<24>
PEG_CRX _GTX_N4<24>

PEG_CRX _GTX_P3<24>
PEG_CRX _GTX_N3<24>

PEG_CRX _GTX_P2<24>
PEG_CRX _GTX_N2<24>

PEG_CRX _GTX_P1<24>
PEG_CRX _GTX_N1<24>

PEG_CRX _GTX_P0<24>
PEG_CRX _GTX_N0<24>

+0.95VS_ VCCIO

CC1 0.22U_0 201_6.3VDIS@
CC3 0.22U_0 201_6.3VDIS@

CC5 0.22U_0 201_6.3VDIS@
CC7 0.22U_0 201_6.3VDIS@

CC16 0.22U_ 0201_6.3VDIS@
CC17 0.22U_ 0201_6.3VDIS@

CC18 0.22U_ 0201_6.3VDIS@
CC20 0.22U_ 0201_6.3VDIS@

CC11 0.22U_ 0201_6.3VDIS@
CC12 0.22U_ 0201_6.3VDIS@

CC14 0.22U_ 0201_6.3VDIS@
CC15 0.22U_ 0201_6.3VDIS@

CC25 0.22U_ 0201_6.3VDIS@
CC27 0.22U_ 0201_6.3VDIS@

CC29 0.22U_ 0201_6.3VDIS@
CC31 0.22U_ 0201_6.3VDIS@

CC33 0.22U_ 0201_6.3VDIS@
CC35 0.22U_ 0201_6.3VDIS@

CC37 0.22U_ 0201_6.3VDIS@
CC39 0.22U_ 0201_6.3VDIS@

CC41 0.22U_ 0201_6.3VDIS@
CC43 0.22U_ 0201_6.3VDIS@

CC45 0.22U_ 0201_6.3VDIS@
CC47 0.22U_ 0201_6.3VDIS@

CC49 0.22U_ 0201_6.3VDIS@
CC51 0.22U_ 0201_6.3VDIS@

CC53 0.22U_ 0201_6.3VDIS@
CC55 0.22U_ 0201_6.3VDIS@

CC57 0.22U_ 0201_6.3VDIS@
CC59 0.22U_ 0201_6.3VDIS@

CC61 0.22U_ 0201_6.3VDIS@
CC63 0.22U_ 0201_6.3VDIS@

1 2

RC6 24.9_0402_1%

To PCH

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

DMI_CRX_P TX_P0<14>
DMI_CRX_P TX_N0<14>

DMI_CRX_P TX_P1<14>
DMI_CRX_P TX_N1<14>

DMI_CRX_P TX_P2<14>
DMI_CRX_P TX_N2<14>

DMI_CRX_P TX_P3<14>
DMI_CRX_P TX_N3<14>

PEG_CRX _C_GTX_P15
PEG_CRX _C_GTX_N15

PEG_CRX _C_GTX_P14
PEG_CRX _C_GTX_N14

PEG_CRX _C_GTX_P13
PEG_CRX _C_GTX_N13

PEG_CRX _C_GTX_P12
PEG_CRX _C_GTX_N12

PEG_CRX _C_GTX_P11
PEG_CRX _C_GTX_N11

PEG_CRX _C_GTX_P10
PEG_CRX _C_GTX_N10

PEG_CRX _C_GTX_P9
PEG_CRX _C_GTX_N9

PEG_CRX _C_GTX_P8
PEG_CRX _C_GTX_N8

PEG_CRX _C_GTX_P7
PEG_CRX _C_GTX_N7

PEG_CRX _C_GTX_P6
PEG_CRX _C_GTX_N6

PEG_CRX _C_GTX_P5
PEG_CRX _C_GTX_N5

PEG_CRX _C_GTX_P4
PEG_CRX _C_GTX_N4

PEG_CRX _C_GTX_P3
PEG_CRX _C_GTX_N3

PEG_CRX _C_GTX_P2
PEG_CRX _C_GTX_N2

PEG_CRX _C_GTX_P1
PEG_CRX _C_GTX_N1

PEG_CRX _C_GTX_P0
PEG_CRX _C_GTX_N0

PEG_RCO MP

Trace Width/Space: 15 mil/ 15 mil
Max Trace Length: 600 mil

DMI_CRX_P TX_P0
DMI_CRX_P TX_N0

DMI_CRX_P TX_P1
DMI_CRX_P TX_N1

DMI_CRX_P TX_P2
DMI_CRX_P TX_N2

DMI_CRX_P TX_P3
DMI_CRX_P TX_N3

E25
D25

E24
F24

E23
D23

E22
F22

E21
D21

E20
F20

E19
D19

E18
F18

D17
E17

F16
E16

D15
E15

F14
E14

D13
E13

F12
E12

D11
E11

F10
E10

G2

D8
E8

E6
F6

D5
E5

J8
J9

UC1C

PEG_RXP_0
PEG_RXN_0

PEG_RXP_1
PEG_RXN_1

PEG_RXP_2
PEG_RXN_2

PEG_RXP_3
PEG_RXN_3

PEG_RXP_4
PEG_RXN_4

PEG_RXP_5
PEG_RXN_5

PEG_RXP_6
PEG_RXN_6

PEG_RXP_7
PEG_RXN_7

PEG_RXP_8
PEG_RXN_8

PEG_RXP_9
PEG_RXN_9

PEG_RXP_10
PEG_RXN_10

PEG_RXP_11
PEG_RXN_11

PEG_RXP_12
PEG_RXN_12

PEG_RXP_13
PEG_RXN_13

PEG_RXP_14
PEG_RXN_14

PEG_RXP_15
PEG_RXN_15

PEG_RCOMP

DMI_RXP_0
DMI_RXN_0

DMI_RXP_1
DMI_RXN_1

DMI_RXP_2
DMI_RXN_2

DMI_RXP_3
DMI_RXN_3

CML_H_IP_ EXT

3 OF 13

PEG_TXP_0
PEG_TXN_0

PEG_TXP_1
PEG_TXN_1

PEG_TXP_2
PEG_TXN_2

PEG_TXP_3
PEG_TXN_3

PEG_TXP_4
PEG_TXN_4

PEG_TXP_5
PEG_TXN_5

PEG_TXP_6
PEG_TXN_6

PEG_TXP_7
PEG_TXN_7

PEG_TXP_8
PEG_TXN_8

PEG_TXP_9
PEG_TXN_9

PEG_TXP_10
PEG_TXN_10

PEG_TXP_11
PEG_TXN_11

PEG_TXP_12
PEG_TXN_12

PEG_TXP_13
PEG_TXN_13

PEG_TXP_14
PEG_TXN_14

PEG_TXP_15
PEG_TXN_15

DMI_TXP_0
DMI_TXN_0

DMI_TXP_1
DMI_TXN_1

DMI_TXP_2
DMI_TXN_2

DMI_TXP_3
DMI_TXN_3

B25
A25

B24
C24

B23
A23

B22
C22

B21
A21

B20
C20

B19
A19

B18
C18

A17
B17

C16
B16

A15
B15

C14
B14

A13
B13

C12
B12

A11
B11

C10
B10

B8
A8

C6
B6

B5
A5

D4
B4

@

PEG_CTX _GRX_P15
PEG_CTX _GRX_N15

PEG_CTX _GRX_N14

PEG_CTX _GRX_P13
PEG_CTX _GRX_N13

PEG_CTX _GRX_P12
PEG_CTX _GRX_N12

PEG_CTX _GRX_P11
PEG_CTX _GRX_N11

PEG_CTX _GRX_P10
PEG_CTX _GRX_N10

PEG_CTX _GRX_P9
PEG_CTX _GRX_N9

PEG_CTX _GRX_P8
PEG_CTX _GRX_N8

PEG_CTX _GRX_P7
PEG_CTX _GRX_N7

PEG_CTX _GRX_N6

PEG_CTX _GRX_P5
PEG_CTX _GRX_N5

PEG_CTX _GRX_P4
PEG_CTX _GRX_N4

PEG_CTX _GRX_P3
PEG_CTX _GRX_N3

PEG_CTX _GRX_P2
PEG_CTX _GRX_N2

PEG_CTX _GRX_P1
PEG_CTX _GRX_N1

PEG_CTX _GRX_P0
PEG_CTX _GRX_N0

DMI_CTX_P RX_P0
DMI_CTX_P RX_N0

DMI_CTX_P RX_P1
DMI_CTX_P RX_N1

DMI_CTX_P RX_P2
DMI_CTX_P RX_N2

DMI_CTX_P RX_P3
DMI_CTX_P RX_N3

CC2 0.22U_0 201_6.3VDIS@
CC4 0.22U_0 201_6.3VDIS@

CC6 0.22U_0 201_6.3VDIS@
CC8 0.22U_0 201_6.3VDIS@

CC9 0.22U_0 201_6.3VDIS@
CC10 0.22U_ 0201_6.3VDIS@

CC19 0.22U_ 0201_6.3VDIS@
CC21 0.22U_ 0201_6.3VDIS@

CC22 0.22U_ 0201_6.3VDIS@
CC13 0.22U_ 0201_6.3VDIS@

CC23 0.22U_ 0201_6.3VDIS@
CC24 0.22U_ 0201_6.3VDIS@

CC26 0.22U_ 0201_6.3VDIS@
CC28 0.22U_ 0201_6.3VDIS@

CC30 0.22U_ 0201_6.3VDIS@
CC32 0.22U_ 0201_6.3VDIS@

CC34 0.22U_ 0201_6.3VDIS@
CC36 0.22U_ 0201_6.3VDIS@

CC38 0.22U_ 0201_6.3VDIS@
CC40 0.22U_ 0201_6.3VDIS@

CC42 0.22U_ 0201_6.3VDIS@
CC44 0.22U_ 0201_6.3VDIS@

CC46 0.22U_ 0201_6.3VDIS@
CC48 0.22U_ 0201_6.3VDIS@

CC50 0.22U_ 0201_6.3VDIS@
CC52 0.22U_ 0201_6.3VDIS@

CC54 0.22U_ 0201_6.3VDIS@
CC56 0.22U_ 0201_6.3VDIS@

CC58 0.22U_ 0201_6.3VDIS@
CC60 0.22U_ 0201_6.3VDIS@

CC62 0.22U_ 0201_6.3VDIS@
CC64 0.22U_ 0201_6.3VDIS@

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

DMI_CTX_P RX_P0 <1 4>
DMI_CTX_P RX_N0 <14>

DMI_CTX_P RX_P1 <1 4>
DMI_CTX_P RX_N1 <14>

DMI_CTX_P RX_P2 <1 4>
DMI_CTX_P RX_N2 <14>

DMI_CTX_P RX_P3 <1 4>
DMI_CTX_P RX_N3 <14>

PEG_CTX _C_GRX_P15
PEG_CTX _C_GRX_N15

PEG_CTX _C_GRX_P14PEG_CTX _GRX_P14
PEG_CTX _C_GRX_N14

PEG_CTX _C_GRX_P13
PEG_CTX _C_GRX_N13

PEG_CTX _C_GRX_P12
PEG_CTX _C_GRX_N12

PEG_CTX _C_GRX_P11
PEG_CTX _C_GRX_N11

PEG_CTX _C_GRX_P10
PEG_CTX _C_GRX_N10

PEG_CTX _C_GRX_P9
PEG_CTX _C_GRX_N9

PEG_CTX _C_GRX_P8
PEG_CTX _C_GRX_N8

PEG_CTX _C_GRX_P7
PEG_CTX _C_GRX_N7

PEG_CTX _C_GRX_P6PEG_CTX _GRX_P6
PEG_CTX _C_GRX_N6

PEG_CTX _C_GRX_P5
PEG_CTX _C_GRX_N5

PEG_CTX _C_GRX_P4
PEG_CTX _C_GRX_N4

PEG_CTX _C_GRX_P3
PEG_CTX _C_GRX_N3

PEG_CTX _C_GRX_P2
PEG_CTX _C_GRX_N2

PEG_CTX _C_GRX_P1
PEG_CTX _C_GRX_N1

PEG_CTX _C_GRX_P0
PEG_CTX _C_GRX_N0

To PCH

PEG_CTX _C_GRX_P15 <24>
PEG_CTX _C_GRX_N15 <24>

PEG_CTX _C_GRX_P14 <24>
PEG_CTX _C_GRX_N14 <24>

PEG_CTX _C_GRX_P13 <24>
PEG_CTX _C_GRX_N13 <24>

PEG_CTX _C_GRX_P12 <24>
PEG_CTX _C_GRX_N12 <24>

PEG_CTX _C_GRX_P11 <24>
PEG_CTX _C_GRX_N11 <24>

PEG_CTX _C_GRX_P10 <24>
PEG_CTX _C_GRX_N10 <24>

PEG_CTX _C_GRX_P9 <24>
PEG_CTX _C_GRX_N9 <24>

PEG_CTX _C_GRX_P8 <24>
PEG_CTX _C_GRX_N8 <24>

PEG_CTX _C_GRX_P7 <24>
PEG_CTX _C_GRX_N7 <24>

PEG_CTX _C_GRX_P6 <24>
PEG_CTX _C_GRX_N6 <24>

PEG_CTX _C_GRX_P5 <24>
PEG_CTX _C_GRX_N5 <24>

PEG_CTX _C_GRX_P4 <24>
PEG_CTX _C_GRX_N4 <24>

PEG_CTX _C_GRX_P3 <24>
PEG_CTX _C_GRX_N3 <24>

PEG_CTX _C_GRX_P2 <24>
PEG_CTX _C_GRX_N2 <24>

PEG_CTX _C_GRX_P1 <24>
PEG_CTX _C_GRX_N1 <24>

PEG_CTX _C_GRX_P0 <24>
PEG_CTX _C_GRX_N0 <24>

To DGPU

(reversed)

4 4

Security Classification

Security Classification

Security Classification

2020/7/31 2020/7/31

2020/7/31 2020/7/31

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2020/7/31 2020/7/31

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PEG/DMI

PEG/DMI

PEG/DMI

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Custom

Custom

Custom

LA-J561P

LA-J561P

LA-J561P

Date: Sheet of

Date: Sheet of

D

Date: Sheet

E

of

9 1 00Wednesday, February 26, 202 0

9 1 00Wednesday, February 26, 202 0

9 1 00Wednesday, February 26, 202 0

1.0

1.0

1.0

A

1 1

Near CPU side

From ESD Team Request

2 2

VCCST_P WRGD<48>

@RF@

03/14 From RF Team Request

ESD@

1 2

ESD@

1 2

CPU_SVID_ CLK

12

CC6510P_0402_50 V8J

VCCST_P WRGD

CC66100P_04 02_50V8J

H_CPUPW RGD

CC67100P_04 02_50V8J

H_CPUPW RGD<18>
H_PLTRS T_CPU#<17>
H_PM_SYNC _R<17>
H_PM_DO WN_R<17>

H_PECI<17,48>

PCH_THE RMTRIP#_R<17>

pulled high in PCH side

+1.05V_V CCST

12

RC10
1K_0402 _5%

VCCST_P WRGD EC_VCCST_P G

+1.05VS_ VCCSTG

1 2

RC11 6 0.4_0402_1%

B

PCH_CPU _BCLK_P<15>
PCH_CPU _BCLK_N<15>

PCH_CPU _PCIBCLK_P<15>
PCH_CPU _PCIBCLK_N<1 5>

PCH_CPU _24M_CLK_P<15>
PCH_CPU _24M_CLK_N<1 5>

1 2

RC7 20_0402_5%

1 2

RC8 0_040 2_5%@

Sensitive

Sensitive

PCH_CPU _BCLK_P
PCH_CPU _BCLK_N

PCH_CPU _PCIBCLK_P
PCH_CPU _PCIBCLK_N

PCH_CPU _24M_CLK_P
PCH_CPU _24M_CLK_N

CPU_SVID_ ALERT#
CPU_SVID_ CLK
CPU_SVID_ DAT
H_PROCH OT#_R

DDR_PG_ CTRL

EC_VCCS T_PG

H_CPUPW RGD
H_PLTRS T_CPU#
H_PM_SYNC _R
H_PM_DO WNH_P M_DOWN_R

H_THERM TRIP#

SKTOCC#

TC7TP@

PROC_SE LECT#

TC8TP@

CATERR#

TC9TP@

TC10TP@
TC11TP@

B31
A32

D35
C36

E31
D31

BH31
BH32
BH29
BR30

BT13

H13

BT31
BP35
BM34
BP31
BT34

BR33

BN1

BM30

AT13

AW13

AU13
AY13

J31

UC1E

BCLKP
BCLKN

PCI_BCLKP
PCI_BCLKN

CLK24P
CLK24N

VIDALERT#
VIDSCK
VIDSOUT
PROCHOT#

DDR_VTT_CNTL

VCCST_PWRGD

PROCPWRGD
RESET#
PM_SYNC
PM_DOWN
PECI
THERMTRIP#

SKTOCC#
PROC_SELECT#

CATERR#

ZVM#
MSM#

RSVD1
RSVD2

5 OF 13

CML_H_IP_ EXT

C

PROC_TDO

PROC_TDI
PROC_TMS
PROC_TCK

PROC_TRST#

PROC_PREQ#

PROC_PRDY#

CFG_RCOMP

BN25

CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8

CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15

CFG_17
CFG_16
CFG_19
CFG_18

BPM#_0
BPM#_1
BPM#_2
BPM#_3

CFG0

BN27
BN26

CFG2

BN28
BR20

CFG4

BM20

CFG5

BT20

CFG6

BP20

CFG7

BR23
BR22
BT23
BT22
BM19
BR19
BP19
BT19

BN23
BP23
BP22
BN22

XDP_BPM #0

BR27

XDP_BPM #1

BT27

XDP_BPM #2

BM31

XDP_BPM #3

BT30

CPU_XDP _TDO

BT28

CPU_XDP _TDI

BL32

CPU_XDP _TMS

BP28

CPU_XDP _TCK0

BR28

CPU_XDP _TRST#

BP30

XDP_PRE Q#

BL30

XDP_PRD Y#

BP27

CFG_RCO MP

BT25

@

1 2

Trace Width/Space: 4 mil/ 12 mil
Max Trace Length: 600 mil

TMS/TDI pin CPU on-die termination

Place to PCH side

TC3 TP@
TC4 TP@
TC5 TP@
TC6 TP@

CPU_XDP _TDO <18>
CPU_XDP_TDI <18>
CPU_XDP_TMS <18>
CPU_XDP_TCK0 <18>

XDP_PREQ# <21>
XDP_PRD Y# < 21>

RC9

49.9_040 2_1%

D

+1.05VS_ VCCSTG

E

The CFG signals have a default value of '1' if not terminated on the board.

CFG[0]: Stall reset sequence after PCU PLL lock until de-asserted

1 = (Default) Normal Operation;
0 = Stall.

CFG[2]: PCI Express* Static x16 Lane Numbering Reversal.

1 = Normal operation
0 = Lane numbers reversed.

CFG[4]: eDP enable:

1 = Disabled.
0 = Enabled.

CFG[6:5]: PCI Express* Bifurcation:

00 = 1 x8, 2 x4 PCI Express*
01 = reserved
10 = 2 x8 PCI Express*
11 = 1 x16 PCI Express*

CFG[7]: PEG Training:

1 = (default) PEG Train immediately following RESET# de assertion.
0 = PEG Wait for BIOS for training.

*CFG Pin Use CMC debug on DDX03 R02 Schematic.

XDP_PRE Q#
XDP_PRD Y#

CFG0

CFG2

@

T1

@

T2

1 2

RC12 1 K_0402_5%@

1 2

RC13 1 K_0402_5%

RC16
1K_0402 _5%

H_PROCH OT#<48>

3 3

SVID ALERT

VR_SVID_ALERT#<88>

H_PROCH OT#

SVID DATA

VR_SVID_S DIO<88>

SVID CLK

4 4

VR_SVID_S CLK<88>

571391_CFL_H_PDG_Rev0p5

. The total Length of Data and Clock (from CPU to each VR) must be equal (±0.1

1
inch).

2. Route the Alert signal between the Clock and the Data signals.

3. Place those resistors close CPU side.

A

1 2

RC21 499_ 0402_1%

+1.05V_V CCST

12

RC24
56_0402 _1%

1 2

RC25 220_ 0402_5%

+1.05V_V CCST

RC27
100_040 2_5%

1 2

1 2

RC28 0_04 02_5%@

1 2

RC29 0_04 02_5%@

12

H_PROCH OT#_R

CPU_SVID_ ALERT#

CPU_SVID_ DAT

CPU_SVID_ CLK

B

DDR_PG_ CTRL

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2020/7/31 2020/7/31

2020/7/31 2020/7/31

2020/7/31 2020/7/31

C

CPU_XDP _TDO

1 2

RC6551_0402 _5%

Place to CPU side

CPU_XDP _TCK0

1 2

RC2251_0402 _5%

If need debug with INTEL. this cmc@ need pop

CPU_XDP _TRST#

NC1VCC

2

A

3

GND

74AUP1G 07GW_TSSO P5

Compal Secret Data

Compal Secret Data

Compal Secret Data

1 2

R1 0_0402_ 5%@

UC2

5

4

Y

@

PM_SLP_ S3#<18,48,86>

Deciphered Date

Deciphered Date

Deciphered Date

+1.2V

CC68

@

12

0.1U_020 1_10V6K

DDR_VTT _PG_CTRL_R

PCH_XDP _TRST# <21>

D

+3VS

RC26

100K_04 02_5%

@

12

RC610_0402_ 5%

12

@

RC620_0402_5%

Title

Title

Title

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

CFG4

CFG5

CFG6

CFG7

12

@

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

CFL-H(5/8)CFG,SVID

CFL-H(5/8)CFG,SVID

CFL-H(5/8)CFG,SVID

LA-J561P

LA-J561P

LA-J561P

1 2

RC17 1 K_0402_5%

1 2

RC19 1 K_0402_5%@

1 2

RC20 1 K_0402_5%

@

1 2

RC23 1 K_0402_5%@

DDR_VTT _PG_CTRL <85>

E

1.0

1.0

1.0

10 10 0Wednesday, February 26, 2020

10 10 0Wednesday, February 26, 2020

10 10 0Wednesday, February 26, 2020

A

B

C

D

E

GT
32000mA(Hexa Core GT2)

+VCCGT +VCCGT

1 1

2 2

3 3

4 4

AT14
AT31
AT32
AT33
AT34
AT35
AT36
AT37
AT38
AU14
AU29
AU30
AU31
AU32
AU35
AU36
AU37
AU38
AV29
AV30
AV31
AV32
AV33
AV34
AV35

AV36
AW14
AW31
AW32
AW33
AW34
AW35
AW36
AW37
AW38

AY29

AY30

AY31

AY32

AY35

AY36

AY37

AY38

BA13

BA14

BA29

BA30

BA31

BA32

BA33

BA34

BA35

BA36

BB13

BB14

BB31

BB32

BB33

BB34

BB35

BB36

BB37

BB38

BC29

BC30

BC31

BC32

BC35

BC36

BC37

BC38

BD13

BD14

BD29

BD30

BD31

BD32

BD33

BD34

BP37

BP38

BR15

BR16

BR17

UC1K

VCCGT1
VCCGT2
VCCGT3
VCCGT4
VCCGT5
VCCGT6
VCCGT7
VCCGT8
VCCGT9
VCCGT10
VCCGT11
VCCGT12
VCCGT13
VCCGT14
VCCGT15
VCCGT16
VCCGT17
VCCGT18
VCCGT19
VCCGT20
VCCGT21
VCCGT22
VCCGT23
VCCGT24
VCCGT25
VCCGT26
VCCGT27
VCCGT28
VCCGT29
VCCGT30
VCCGT31
VCCGT32
VCCGT33
VCCGT34
VCCGT35
VCCGT36
VCCGT37
VCCGT38
VCCGT39
VCCGT40
VCCGT41
VCCGT42
VCCGT43
VCCGT44
VCCGT45
VCCGT46
VCCGT47
VCCGT48
VCCGT49
VCCGT50
VCCGT51
VCCGT52
VCCGT53
VCCGT54
VCCGT55
VCCGT56
VCCGT57
VCCGT58
VCCGT59
VCCGT60
VCCGT61
VCCGT62
VCCGT63
VCCGT64
VCCGT65
VCCGT66
VCCGT67
VCCGT68
VCCGT69
VCCGT70
VCCGT71
VCCGT72
VCCGT73
VCCGT74
VCCGT75
VCCGT76
VCCGT77
VCCGT78
VCCGT79
VCCGT159
VCCGT160
VCCGT161
VCCGT162
VCCGT163

CML_H_IP_ EXT

VSSGT_SENSE
VCCGT_SENSE

11 OF 13

VCCGT80
VCCGT81
VCCGT82
VCCGT83
VCCGT84
VCCGT85
VCCGT86
VCCGT87
VCCGT88
VCCGT89
VCCGT90
VCCGT91
VCCGT92
VCCGT93
VCCGT94
VCCGT95
VCCGT96
VCCGT97
VCCGT98

VCCGT99
VCCGT100
VCCGT101
VCCGT102
VCCGT103
VCCGT104
VCCGT105
VCCGT106
VCCGT107
VCCGT108
VCCGT109
VCCGT110
VCCGT111
VCCGT112
VCCGT113
VCCGT114
VCCGT115
VCCGT116
VCCGT117
VCCGT118
VCCGT119
VCCGT120
VCCGT121
VCCGT122
VCCGT123
VCCGT124
VCCGT125
VCCGT126
VCCGT127
VCCGT128
VCCGT129
VCCGT130
VCCGT131
VCCGT132
VCCGT133
VCCGT134
VCCGT135
VCCGT136
VCCGT137
VCCGT138
VCCGT139
VCCGT140
VCCGT141
VCCGT142
VCCGT143
VCCGT144
VCCGT145
VCCGT146
VCCGT147
VCCGT148
VCCGT149
VCCGT150
VCCGT151
VCCGT152
VCCGT153
VCCGT154
VCCGT155
VCCGT156
VCCGT157
VCCGT158
VCCGT164
VCCGT165
VCCGT166
VCCGT167
VCCGT168

BD35
BD36
BE31
BE32
BE33
BE34
BE35
BE36
BE37
BE38
BF13
BF14
BF29
BF30
BF31
BF32
BF35
BF36
BF37
BF38
BG29
BG30
BG31
BG32
BG33
BG34
BG35
BG36
BH33
BH34
BH35
BH36
BH37
BH38
BJ16
BJ17
BJ19
BJ20
BJ21
BJ23
BJ24
BJ26
BJ27
BJ37
BJ38
BK16
BK17
BK19
BK20
BK21
BK23
BK24
BK26
BK27
BL15
BL16
BL17
BL23
BL24
BL25
BL26
BL27
BL28
BL36
BL37
BM15
BM16
BM17
BM36
BM37
BN15
BN16
BN17
BN36
BN37
BN38
BP15
BP16
BP17
BR37
BT15
BT16
BT17
BT37

AH37
AH38

@

+VCCGT

12

RC33
100_040 2_1%

RC32
100_040 2_1%

1 2

+VCCCOR E

UC1I

AA13

VCC1

AA31

VCC2

AA32

VCC3

AA33

VCC4

AA34

VCC5

AA35

VCC6

AA36

VCC7

AA37

VCC8

AA38

VCC9

AB29

VCC10

AB30

VCC11

AB31

VCC12

AB32

VCC13

AB35

VCC14

AB36

VCC15

AB37

VCC16

AB38

VCC17

AC13

VCC18

AC14

VCC19

AC29

VCC20

AC30

VCC21

AC31

VCC22

AC32

VCC23

AC33

VCC24

AC34

VCC25

AC35

VCC26

AC36

VCC27

AD13

VCC28

AD14

VCC29

AD31

VCC30

AD32

VCC31

AD33

VCC32

AD34

VCC33

AD35

VCC34

AD36

VCC35

AD37

VCC36

AD38

VCC37

AE13

VCC38

AE14

VCC39

AE30

VCC40

AE31

VCC41

AE32

VCC42

AE35

VCC43

AE36

VCC44

AE37

VCC45

AE38

VCC46

AF29

VCC47

AF30

VCC48

AF31

VCC49

AF32

VCC50

AF33

VCC51

AF34

VCC52

AF35

VCC53

AF36

VCC54

AF37

VCC55

AF38

VCC56

AG14

VCC57

AG31

VCC58

AG32

VCC59

AG33

VCC60

AG34

VCC61

AG35

VCC62

AG36

VCC63

9 OF 13

CML_H_IP_ EXT

1. VccGT_SENSE / VssGT_SENSE Trace Length M atch < 25 mils

2. Maintain 25- mil separation distance away from any other dynamic sign als.

3. RC12, RC13 should be placed within 2 in ches (50.8 mm) of CPU

VSSGT_S ENSE <88>

VCCGT_S ENSE <88>

VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98

VCC99
VCC100
VCC101
VCC102
VCC103
VCC104
VCC105
VCC106
VCC107
VCC108
VCC109
VCC110
VCC111
VCC112
VCC113
VCC114
VCC115
VCC116
VCC117
VCC118
VCC119
VCC120
VCC121
VCC122
VCC123
VCC124

VCC_SENSE

VSS_SENSE

+VCCCOR E

AH13
AH14
AH29
AH30
AH31
AH32
AJ14
AJ29
AJ30
AJ31
AJ32
AJ33
AJ34
AJ35
AJ36
AK31
AK32
AK33
AK34
AK35
AK36
AK37
AK38
AL13
AL29
AL30
AL31
AL32
AL35
AL36
AL37
AL38
AM13
AM14
AM29
AM30
AM31
AM32
AM33
AM34
AM35
AM36
AN13
AN14
AN31
AN32
AN33
AN34
AN35
AN36
AN37
AN38
AP13
AP30
AP31
AP32
AP35
AP36
AP37
AP38
K13

AG37
AG38

@

+VCCCOR E

128000mA(Hexa Core GT2)

RC30
100_040 2_1%

1 2

12

RC31
100_040 2_1%

VCCCORE _SENSE <88>
VSSCORE _SENSE <8 8>

1. Vcc_SENSE/ V ss_SENSE Trace Length Match < 25 mils

2. Maintain 25- mil separation distance away from any other dynamic sign als.

3. RC10, RC11 should be placed within 2 in ches (50.8 mm) of CPU

+VCCCOR E

K14

L13

L14
N13
N14
N30
N31
N32
N35
N36
N37
N38
P13
P14
P29
P30
P31
P32
P33
P34
P35
P36
R13
R31
R32
R33
R34
R35
R36
R37
R38
T29
T30
T31
T32
T35
T36
T37
T38
U29
U30
U31
U32
U33
U34
U35
U36
V13
V14
V31
V32
V33
V34
V35
V36
V37
V38

W13
W14
W29
W30
W31
W32

UC1J

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63

CML_H_IP_ EXT

10 OF 13

VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75

@

+VCCCOR E

W35
W36
W37
W38
Y29
Y30
Y31
Y32
Y33
Y34
Y35
Y36

Security Classification

Security Classification

Security Classification

2020/7/31 2020/7/31

2020/7/31 2020/7/31

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2020/7/31 2020/7/31

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

CFL-H(6/8)VCC_CORE/GT

CFL-H(6/8)VCC_CORE/GT

CFL-H(6/8)VCC_CORE/GT

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Custom

Custom

Custom

LA-J561P

LA-J561P

LA-J561P

Date: Sheet of

Date: Sheet of

D

Date: Sheet

E

of

11 10 0Wednesday, February 26, 2020

11 10 0Wednesday, February 26, 2020

11 10 0Wednesday, February 26, 2020

1.0

1.0

1.0

A

B

C

D

E

+VCCSA

+VCC_SA
M

ax: 11100mA

1 1

+0.95VS_VCCIO

+VCC_IO
Max: 6400mA

2 2

I (Max) : 0.1 A(+1.2V_VCCSFR_O C)
RON(Max) : 35 mohm
Output PD R:250 ohm
V drop : 0.003 V

3 3

For Power consumption Measurement

4 4

UC1L

J30

VCCSA1

K29

VCCSA2

K30

VCCSA3

K31

VCCSA4

K32

VCCSA5

K33

VCCSA6

K34

VCCSA7

K35

VCCSA8

L31

VCCSA9

L32

VCCSA10

L35

VCCSA11

L36

VCCSA12

L37

VCCSA13

L38

VCCSA14

M29

VCCSA15

M30

VCCSA16

M31

VCCSA17

M32

VCCSA18

M33

VCCSA19

M34

VCCSA20

M35

VCCSA21

M36

VCCSA22

AG12

VCCIO1

G15

VCCIO2

G17

VCCIO3

G19

VCCIO4

G21

VCCIO5

H15

VCCIO6

H16

VCCIO7

H17

VCCIO8

H19

VCCIO9

H20

VCCIO10

H21

VCCIO11

H26

VCCIO12

H27

VCCIO13

J15

VCCIO14

J16

VCCIO15

J17

VCCIO16

J19

VCCIO17

J20

VCCIO18

J21

VCCIO19

J26

VCCIO20

J27

VCCIO21

CML_H_IP_EXT @

+ 1.2V_VCCSFR_OC Load switch timing meet intel spec<=
240μs

SYSON<48,56,85>

SUSP#<48,57,60,65,85,86,98>

VCCSA_SENSE

12 OF 13

RC63 0_0201_5%@

RC57 0_0201_5%@

+1.05VALW

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21
VDDQ22
VDDQ23
VDDQ24
VDDQ25

VCCPLL_OC1
VCCPLL_OC2
VCCPLL_OC3

VCCST

VCCSTG2

VCCSTG1

VCCPLL1
VCCPLL2

VSSSA_SENSE

VCCIO_SENSE
VSSIO_SENSE

1 2

1 2

1U_0201_6.3V6M

CC105

1

2

@

AA6
AE12
AF5
AF6
AG5
AG9
AJ12
AL11
AP6
AP7
AR12
AR6
AT12
AW6
AY6
J5
J6
K12
K6
L12
L6
R6
T6
W6
Y12

Max: 130mA

BH13
BJ13
G11

H30

H29

G30

H28
J28

M38
M37

VCCIO_SENSE

H14

VSSIO_SENSE

J14

+1.2V_VDDQ_CPU
Max: 3300mA

+1.2V_VCCPLL_OC

Max: 60mA

Max: 20mA

Max: 150mA

VCCSA_SENSE
VSSSA_SENSE

+1.2V

+5VALW

CC99

1

2

+1.2V

+1.05V_VCCST

+1.05VS_VCCSTG

+VCCSA

+1.05V_VCCSFR

TC12 TP@
TC13 TP@

1 2

RC59 0_0402_5%@

For NON-S0IX

1 2

12

BSC Side

RC34
100_0402_1%

RC35
100_0402_1%

+1.2V_VCCPLL_OC

1

2

+1.0V_PRIM to +VCCST_S3

+1.05VALW

1U_0201_6.3V6M

1U_0201_6.3V6M

CC100

1

I (Max) : 0.04 A(+1.0V_VCCSTU)
RON(Max) : 25 mohm
Output PD R=220 ohm

2

@

V drop : 0.001 V

UC8

1

VOUT1

VIN1

2

VOUT1

EN_VCCST_S3

VCCSTG_EN

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2

7

VIN2

EM5209VF_DFN14_3X2

VOUT2
VOUT2

GPAD

CT1

GND

CT2

+1.0V_PRIM TO +1.0V_VCCSTG

VCCSA_SENSE <88>
VSSSA_SENSE <88>

CC109

0.1U_0201_10V6K

14
13

10P_0402_50V8J

12

1 2

CC102

11

1000P_0402_50V7K

10

1 2

CC103

9
8

15

+VCCST_S3

1

CC101

0.1U_0402_25V6

2

+1.05VS_VCCSTG

CC104

1

2

+1.2V

10U_0402_10V6M

1

2

+0.95VS_VCCIO

10U_0402_10V6M

1

2

1. VccGT_SENSE / VssGT_SENSE Trace Length Match < 25 mils

2. Maintain 25-mil separation distance away from any other dynamic signals.

3. RC15, RC16 should be placed within 2 inches (50.8 mm) of CPU

10U_0402_10V6M

10U_0402_10V6M

1

CC69

2

571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.2V_VDDQ_CPU: 10uF * 11 22uF * 4

10U_0402_10V6M

1

CC85

2

571483_CFL_H_RVP_CRB_TDK_Rev0p5
+0.95VS_VCCIO: 10uF * 4

+VCCST_S3

10U_0402_10V6M

1

1

1

CC71

@

2

10U_0402_10V6M

1

2

1 2

CC87

60mA

CC72

2

2

10U_0402_10V6M

1

@

CC88

2

CC70

CC86

RC36 0_0402_5%@

571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.05V_VCCST: 1uF * 1

10U_0402_10V6M

10U_0402_10V6M

10U_0402_10V6M

1

1

CC74

CC73

2

2

PLACE CAP BACKSIDE

+1.2V_VCCPLL_OC

1U_0201_6.3V6M

1

CC89

2

571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.2V_VCCPLL_OC: 1uF * 2

PLACE CAP BACKSIDE

+1.05V_VCCST

1U_0201_6.3V6M

1

2

10U_0402_10V6M

1

CC75

2

1U_0201_6.3V6M

1

CC90

2

CC92

10U_0402_10V6M

10U_0402_10V6M

1

CC76

2

10U_0402_10V6M

@

1

CC93

2

10U_0402_10V6M

1

1

CC78

CC77

2

2

@

CC79

571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.05VS_VCCSTG: 1uF * 1

1

2

+1.05VS_VCCSTG

1U_0201_6.3V6M

1

CC91

2

22U_0603_6.3V6M

22U_0603_6.3V6M

1

CC81

2

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

CC84

CC83

CC82

2

2

PLACE CAP BACKSIDE

150mA

1 2

RC37 0_0402_5%@

571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.05V_VCCSFR: 1uF * 1

+1.05V_VCCSFR

1U_0201_6.3V6M

1

2

10U_0402_10V6M

10U_0402_10V6M

@

@

1

1

CC94

2

CC96

CC95

2

PLACE CAP BACKSIDE

0.1U_0402_25V6

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

A

B

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

C

2020/7/31 2020/7/31

2020/7/31 2020/7/31

2020/7/31 2020/7/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

CFL-H(7/8)VCCSA/VCCIO/VDDQ

CFL-H(7/8)VCCSA/VCCIO/VDDQ

CFL-H(7/8)VCCSA/VCCIO/VDDQ

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

LA-J561P

LA-J561P

LA-J561P

Date: Sheet of

Date: Sheet of

Date: Sheet of

E

12 100Wednesday, February 26, 2020

12 100Wednesday, February 26, 2020

12 100Wednesday, February 26, 2020

1.0

1.0

1.0

A

B

C

D

E

UC1G

UC1F

A10

VSS_1

A12

VSS_2

A16

VSS_3

A18

VSS_4

A20

VSS_5

A22

VSS_6

A24

VSS_7

A26

VSS_8

1 1

2 2

3 3

A28
A30

AA12
AA29
AA30
AB33
AB34

AB6

AC1

AC12

AC2

AC3
AC37
AC38

AC4

AC5

AC6
AD10
AD11
AD12
AD29
AD30

AD6

AD8

AD9
AE33
AE34

AE6

AF1

AF12
AF13
AF14

AF2

AF3

AF4
AG10
AG11
AG13
AG29
AG30

AG6

AG7

AG8
AH12
AH33
AH34
AH35
AH36

AH6

AJ1

AJ13

AJ2

AJ3
AJ37
AJ38

AJ4

AJ5

AJ6

Y10

Y11

Y13

Y14

Y37

Y38

AK29
AK30

A6
A9

W4
W5

Y7
Y8
Y9

VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81

6 OF 13

CML_H_IP_ EXT

@

VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98

VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162

AK4
AL10
AL12
AL14
AL33
AL34
AL4
AL7
AL8
AL9
AM1
AM12
AM2
AM3
AM37
AM38
AM4
AM5
AN12
AN29
AN30
AN5
AN6
AP10
AP11
AP12
AP33
AP34
AP8
AP9
AR1
AR13
AR14
AR2
AR29
AR3
AR30
AR31
AR32
AR33
AR34
AR35
AR36
AR37
AR38
AR4
AR5
AT29
AT30
AT6
AU10
AU11
AU12
AU33
AU34
AU6
AU7
AU8
AU9
AV37
AV38
AW1
AW12
AW2
AW29
AW3
AW30
AW4
U6
V12
V29
V30
A14
AD7
V6
W1
W12
W2
W3
W33
W34

AW5
AY12
AY33
AY34

BA10
BA11
BA12
BA37
BA38

BA6
BA7
BA8
BA9
BB1

BB12

BB2

BB29

BB3

BB30

BB4
BB5

BB6
BC12
BC13
BC14
BC33
BC34

BC6
BD10
BD11
BD12
BD37

BD6

BD7

BD8

BD9

BE1

BE2
BE29

BE3
BE30

BE4

BE5

BE6
BF12
BF33
BF34

BF6
BG12
BG13
BG14
BG37
BG38

BG6

BH1
BH10
BH11
BH12
BH14

BH2

BH3

BH4

BH5

BH6

BH7

BH8

BH9

T33
T34

U37

U38

BJ12
BJ14

B9

T2
T3

T4
T5
T7
T8
T9

VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243

7 OF 13

CML_H_IP_ EXT

@

VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324

BJ15
BJ18
BJ22
BJ25
BJ29
BJ30
BJ31
BJ32
BJ33
BJ34
BJ35
BJ36
BK13
BK14
BK15
BK18
BK22
BK25
BK29
BK6
BL13
BL14
BL18
BL19
BL20
BL21
BL22
BL29
BL33
BL35
BL38
BL6
BM11
BM12
BM13
BM14
BM18
BM2
BM21
BM22
BM23
BM24
BM25
BM26
BM27
BM28
BM29
BM3
BM33
BM35
BM38
BM5
BM6
BM7
BM8
BM9
BN12
BN14
BN18
BN19
BN2
BN20
BN21
BN24
BN29
BN30
BN31
BN34
P38
P6
R12
R29
AY14
BD38
R30
T1
T10
T11
T12
T13
T14

BN4

BN7
BP12
BP14
BP18
BP21
BP24
BP25
BP26
BP29
BP33
BP34

BP7
BR12
BR14
BR18
BR21
BR24
BR25
BR26
BR29
BR34
BR36

BR7

BT12
BT14
BT18
BT21
BT24
BT26
BT29
BT32

BT5

C11

C13

C15

C17

C19

C21

C23

C25

C27

C29

C31

C37

D10

D12

D14

D16

D18

D20

D22

D24

D26

D28

D30

D33

E34

E35

E38

N33

N34

P12

P37

M14

F11
F13

C5
C8
C9

D3

D6
D9

E4
E9

N3

N4
N5
N6
N7
N8
N9

M6
N1

@

UC1H

VSS_325
VSS_326
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353
VSS_354
VSS_355
VSS_356
VSS_357
VSS_358
VSS_359
VSS_360
VSS_361
VSS_362
VSS_363
VSS_364
VSS_365
VSS_366
VSS_367
VSS_368
VSS_369
VSS_370
VSS_371
VSS_372
VSS_373
VSS_374
VSS_375
VSS_376
VSS_377
VSS_378
VSS_379
VSS_380
VSS_381
VSS_382
VSS_383
VSS_384
VSS_385
VSS_386
VSS_387
VSS_388
VSS_389
VSS_390
VSS_391
VSS_392
VSS_393
VSS_394
VSS_395
VSS_396
VSS_397
VSS_398
VSS_399
VSS_400
VSS_401
VSS_402
VSS_403
VSS_404
VSS_405
VSS_406
VSS_407
VSS_408

8 OF 13

CML_H_IP_ EXT

VSS_409
VSS_410
VSS_411
VSS_412
VSS_413
VSS_414
VSS_415
VSS_416
VSS_417
VSS_418
VSS_419
VSS_420
VSS_421
VSS_422
VSS_423
VSS_424
VSS_425
VSS_426
VSS_427
VSS_428
VSS_429
VSS_430
VSS_431
VSS_432
VSS_433
VSS_434
VSS_435
VSS_436
VSS_437
VSS_438
VSS_439
VSS_440
VSS_441
VSS_442
VSS_443
VSS_444
VSS_445
VSS_446
VSS_447
VSS_448
VSS_449
VSS_450
VSS_451
VSS_452
VSS_453
VSS_454
VSS_455
VSS_456
VSS_457
VSS_458
VSS_459
VSS_460
VSS_461
VSS_462
VSS_463
VSS_464
VSS_465
VSS_466
VSS_467
VSS_468
VSS_469
VSS_470
VSS_471
VSS_472
VSS_473
VSS_474
VSS_475
VSS_476
VSS_477
VSS_478
VSS_479

VSS_A3

VSS_A34

VSS_A4
VSS_B3

VSS_B37

VSS_BR38

VSS_BT3
VSS_BT35
VSS_BT36

VSS_BT4

VSS_C2

VSS_D38

F15
F17
F19
F2
F21
F23
F25
F27
F29
F3
F31
F36
F4
F5
F8
F9
G10
G12
G14
G16
G18
G20
G22
G23
G24
G26
G28
G4
G5
G6
G8
G9
H11
H12
H18
H22
H25
H32
H35
J10
J18
J22
J25
J32
J33
J36
J4
J7
K1
K10
K11
K2
K3
K38
K4
K5
K7
K8
K9
L29
L30
L33
L34
M12
M13
N10
N11
N12
N2
BT8
BR9

A3
A34
A4
B3
B37
BR38
BT3
BT35
BT36
BT4
C2
D38

UC1M

E2

RSVD_TP5

E3

IST_TRIG

E1

RSVD_TP4

D1

RSVD_TP3

TC14TP@

TC15TP@

1 2

RC38 0_04 02_5%@

1 2

RC39 0_04 02_5%@

PCH_TRIGO UT_R<21>

CPU_TRIGO UT_R<21>

1 2

RC40 30_ 0402_5%

PCH_TRIGO UT_R
CPU_TRIGO UT

BR1
BT2

BN35

H24

BN33

BL34

N29

R14
AE29
AA14
AP29
AP14

A36

A37

H23

E30

B30

C30

BR35
BR31
BH30

J24

J23

F30

G3

J3

RSVD_TP1
RSVD_TP2

RSVD15

RSVD28
RSVD27
RSVD14
RSVD13

RSVD30
RSVD31
RSVD2
RSVD1
RSVD5
RSVD4
VSS_A36

VSS_A37

PROC_TRIGIN
PROC_TRIGOUT

RSVD24

RSVD23

RSVD7
RSVD21

RSVD26
RSVD29

RSVD19
RSVD18
RSVD9

13 OF 13

CML_H_IP_ EXT

@

RSVD11
RSVD10

RSVD12

RSVD3

RSVD25

RSVD22
RSVD20
RSVD17
RSVD16

RSVD8
RSVD6

BK28
BJ28

BL31
AJ8
G13

C38
C1
BR2
BP1
B38
B2

TC16 TP@

TC17 TP@
TC18 TP@
TC19 TP@

Add for Corner NCTF testing

4 4

Security Classification

Security Classification

Security Classification

2020/7/31 2020/7/31

2020/7/31 2020/7/31

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2020/7/31 2020/7/31

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

CFL-H(8/8)GND/RSVD

CFL-H(8/8)GND/RSVD

CFL-H(8/8)GND/RSVD

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Custom

Custom

Custom

LA-J561P

LA-J561P

LA-J561P

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

13 10 0Wednesday, February 26, 2020

13 10 0Wednesday, February 26, 2020

13 10 0Wednesday, February 26, 2020

E

1.0

1.0

1.0

A

DMI_CTX_P RX_N0<9>
DMI_CTX_P RX_P0<9>

DMI_CRX_P TX_N0<9>

DMI_CRX_P TX_P0<9>
DMI_CTX_P RX_N1<9>
DMI_CTX_P RX_P1<9>

DMI_CRX_P TX_N1<9>

DMI_CRX_P TX_P1<9>
DMI_CTX_P RX_N2<9>

1 1

2 2

3 3

4 4

DMI_CTX_P RX_P2<9>

DMI_CRX_P TX_N2<9>

DMI_CRX_P TX_P2<9>
DMI_CTX_P RX_N3<9>
DMI_CTX_P RX_P3<9>

DMI_CRX_P TX_N3<9>

DMI_CRX_P TX_P3<9>

DMI_CTX_P RX_N0
DMI_CTX_P RX_P0
DMI_CRX_P TX_N0
DMI_CRX_P TX_P0
DMI_CTX_P RX_N1
DMI_CTX_P RX_P1
DMI_CRX_P TX_N1
DMI_CRX_P TX_P1
DMI_CTX_P RX_N2
DMI_CTX_P RX_P2
DMI_CRX_P TX_N2
DMI_CRX_P TX_P2
DMI_CTX_P RX_N3
DMI_CTX_P RX_P3
DMI_CRX_P TX_N3
DMI_CRX_P TX_P3

G33

G30

G26

M26

M29

G17

G20

G24

K34

C33
B33

F34
C32
B32
K32

C31
B31

F30
C29
B29
A25
B25
P24
R24
C26
B26
F26

B27
C27
L26

D29
E28
K29

F16
A17
B17
R21
P21
B18
C18
K18

B19
C19
N18
R18
D20
C20
F20

B21
A22
K21

D21
C21
B23
C23

L24
F24

B24
C24

J35

J32

J18

J21

J24

B

UH1B

DMI0_RXN
DMI0_RXP
DMI0_TXN
DMI0_TXP
DMI1_RXN
DMI1_RXP
DMI1_TXN
DMI1_TXP
DMI2_RXN
DMI2_RXP
DMI2_TXN
DMI2_TXP
DMI3_RXN
DMI3_RXP
DMI3_TXN
DMI3_TXP
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

PCIE1_RXN/USB31_7_RXN
PCIE1_RXP/USB31_7_RXP
PCIE1_TXN/USB31_7_TXN
PCIE1_TXP/USB31_7_TXP
PCIE2_RXN/USB31_8_RXN
PCIE2_RXP/USB31_8_RXP
PCIE2_TXN/USB31_8_TXN
PCIE2_TXP/USB31_8_TXP
PCIE3_RXN/USB31_9_RXN
PCIE3_RXP/USB31_9_RXP
PCIE3_TXN/USB31_9_TXN
PCIE3_TXP/USB31_9_TXP
PCIE4_RXN/USB31_10_RXN
PCIE4_RXP/USB31_10_RXP
PCIE4_TXN/USB31_10_TXN
PCIE4_TXP/USB31_10_TXP
PCIE5_RXN
PCIE5_RXP
PCIE5_TXN
PCIE5_TXP
PCIE6_RXN
PCIE6_RXP
PCIE6_TXN
PCIE6_TXP
PCIE7_TXP
PCIE7_TXN
PCIE7_RXP
PCIE7_RXN
PCIE8_RXN
PCIE8_RXP
PCIE8_TXN
PCIE8_TXP

CML-H_BG A874

@

2 OF 13

CNP-H

GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#

GPP_F15/USB2_OC4#
GPP_F16/USB2_OC5#
GPP_F17/USB2_OC6#
GPP_F18/USB2_OC7#

USB2_VBUSSENSE

USB2N_1
USB2P_1
USB2N_2
USB2P_2
USB2N_3
USB2P_3
USB2N_4
USB2P_4
USB2N_5
USB2P_5
USB2N_6
USB2P_6
USB2N_7
USB2P_7
USB2N_8
USB2P_8
USB2N_9

USB2P_9
USB2N_10
USB2P_10
USB2N_11
USB2P_11
USB2N_12
USB2P_12
USB2N_13
USB2P_13
USB2N_14
USB2P_14

USB2_COMP

RSVD1

USB2_ID

GPD7

PCIE24_TXP

PCIE24_TXN
PCIE24_RXP
PCIE24_RXN

PCIE23_TXP

PCIE23_TXN
PCIE23_RXP
PCIE23_RXN

PCIE22_TXP

PCIE22_TXN
PCIE22_RXP
PCIE22_RXN

PCIE21_TXP

PCIE21_TXN
PCIE21_RXP
PCIE21_RXN

Rev1.0

J3
J2
N13
N15
K4
K3
M10
L9
M1
L2
K7
K6
L4
L3
G4
G5
M6
N8
H3
H2
R10
P9
G1
G2
N3
N2
E5
F6

AH36
AL40
AJ44
AL41
AV47
AR35
AR37
AV43

USB2_RC OMP

F4

USB2_VB USSENSE

F3
U13

USB2_ID

G3

GPD_7

BE41

G45
G46
Y41
Y40
G48
G49
W44
W43
H48
H47
U41
U40
F46
G47
R44
T43

USB20_N 1 <56>
USB20_P 1 <56 >
USB20_N 2 <56>
USB20_P 2 <56 >
USB20_N 3 <55>
USB20_P 3 <55 >
USB20_N 4 <64>
USB20_P 4 <64 >
USB20_N 5 <61>
USB20_P 5 <61 >
USB20_N 6 <42>
USB20_P 6 <42 >
USB20_N 7 <62>
USB20_P 7 <62 >

USB20_N 14
USB20_P 14

USB_OC0 #
USB_OC1 #
USB_OC2 #
USB_OC3 #

PCIE_PTX_ DRX_P24
PCIE_PTX_ DRX_N24
PCIE_PRX_ DTX_P24
PCIE_PRX_ DTX_N24
PCIE_PTX_ DRX_P23
PCIE_PTX_ DRX_N23
PCIE_PRX_ DTX_P23
PCIE_PRX_ DTX_N23
PCIE_PTX_ DRX_P22
PCIE_PTX_ DRX_N22
PCIE_PRX_ DTX_P22
PCIE_PRX_ DTX_N22
PCIE_PTX_ DRX_P21
PCIE_PTX_ DRX_N21
PCIE_PRX_ DTX_P21
PCIE_PRX_ DTX_N21

C

USB3.1 Port 2 (Left Back)

USB3.1 Port 1 (Right Back)

USB3.1 Port 3 (Right Front) with AOU support

To IT8296

F

or USB Type-C TBT port

Camera

For USB Type-C DP port

USB20_N 14 <49>
USB20_P 14 <4 9>

1 2

RH5 113_0402_1%

1 2

RH6 1K _0402_5%

1 2

RH7

The 30 HSIO lanes on PCH-H supports the following configurations:

1. Up to 24 PCIe* Lanes
—A maximum of 16 PCIe* Ports (or devices) can be enabled

‧

devices) that can be enabled reduces based off the following:
Max PCIe* Ports (or devices) = 16 - GbE (0 or 1)
— PCIe* Lanes 1-4 (PCIe* Controller #1), 5-8 (PCIe* Controller #2), 9-12 (PCIe*
Controller #3), 13-16 (PCIe* Controller #4), 17-20 (PCIe* Controller #5), and
21-24 (PCIe* Controller #6) can be individually configured

2. Up to 6 SATA Lanes
— A maximum of 6 SATA Ports (or devices) can be enabled
— SATA Lane 0 has the flexibility to be mapped to Flex I/O Lane 16 or 18
— SATA Lane 1 has the flexibility to be mapped to Flex I/O Lane 17 or 19

3. Up to 10 USB 3.1 Lanes
— A maximum of 10 USB 3.1 Ports (or devices) can be enabled

4. Up to 4 GbE Lanes
— A maximum of 1 GbE Port (or device) can be enabled

5. Supports up to 3 Remapped (IntelR Rapid Storage Technology) PCIe* storage
devices
— x2 and x4 PCIe* NVMe SSD
— x2 IntelR Optane? Memory Device
— See the “PCI Express* (PCIe*)” chapter for the PCH PCIe* Controllers,configurations
, and lanes that can be used for IntelR Rapid Storage Technology PCIe* storage support

6. For unused SATA/PCIe* Combo Lanes, Flex I/O Lanes that can be configured as PCIe* or SATA,
the lanes must be statically assigned to SATA or PCIe* via the SATA/PCIe Combo Port Soft
Straps discussed in the SPI Programming Guide and
through the IntelR Flash Image Tool (FIT) tool.

1K_0402 _5%

When a GbE Port is enabled, the maximum number of PCIe* Ports (or

USB2.0 P14 for integrated intel@Wireless-AC

BT

FOR CNVI follow 571906_CNL_PCH_TA_WW11.pdf

FOLLOW MP projects

PCIE_PTX_ DRX_P24 <49>
PCIE_PTX_ DRX_N24 <49>
PCIE_PRX_ DTX_P24 <49>
PCIE_PRX_ DTX_N24 <49>
PCIE_PTX_ DRX_P23 <49>
PCIE_PTX_ DRX_N23 <49>
PCIE_PRX_ DTX_P23 <49>
PCIE_PRX_ DTX_N23 <49>
PCIE_PTX_ DRX_P22 <49>
PCIE_PTX_ DRX_N22 <49>
PCIE_PRX_ DTX_P22 <49>
PCIE_PRX_ DTX_N22 <49>
PCIE_PTX_ DRX_P21 <49>
PCIE_PTX_ DRX_N21 <49>
PCIE_PRX_ DTX_P21 <49>
PCIE_PRX_ DTX_N21 <49>

D

USB_OC2 #

RH1 10K_0 402_5%

USB_OC3 #

RH2 10K_0 402_5%

USB_OC1 #

RH3 10K_0 402_5%

USB_OC0 #

RH4 10K_0 402_5%

1 2
1 2
1 2
1 2

To SSD1 M.2

+3VALW

GPD_7

STRAP

X'tal Input:
High: Differential
Low: Single ended

check its function

E

+PCH_DS W

12

RH8
10K_040 2_5%

12

RH9
10K_040 2_5%

@

Security Classification

Security Classification

Security Classification

2020/7/31 2020/7/31

2020/7/31 2020/7/31

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2020/7/31 2020/7/31

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PCH(1/8)DMI/PCIE/USB2

PCH(1/8)DMI/PCIE/USB2

PCH(1/8)DMI/PCIE/USB2

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Custom

Custom

Custom

LA-J561P

LA-J561P

LA-J561P

Date: Sheet of

Date: Sheet of

D

Date: Sheet

E

of

14 10 0Wednesday, February 26, 2020

14 10 0Wednesday, February 26, 2020

14 10 0Wednesday, February 26, 2020

1.0

1.0

1.0

A

B

C

D

E

PCH-H XTAL_IN/OUT POR is 24MHz for 571697_CNL_MOW_WW16_2017.pdf

1 2

RH12 1 M_0402_5%

24MHZ_1 8PF_XRCGB24M 000F2P51R0

3

27P_0402_50V8J

1 1

10P_0402_50V8J

2 2

+3VS

For DDX03 R02

+1.8V_PR IM

3 3

+1.8V_PR IM

+1.8V_PR IM

4 4

3

NC

1

2

1

CH3

2

RH16 10K_ 0402_5%

RH18 10K_ 0402_5%

RH19 10K_ 0402_5%

RH20 10K_ 0402_5%DIS@

RH143 10K_0402_5%

RH21 4.7K_0402_5%

This signal has a weak internal pull-down 20K.
0 = 38.4/19.2MHz XTAL frequency selected.
1 = 24MHz XTAL frequency selected. (DDX03)
Notes:

1. The internal pull-down is disabled after RSMRST#
de-asserts.

2. This signal is in the primary well.

RH27 4.7K_0402_5%

The signal has a weak internal pull-down 20K
0 = VCCPSPI is connected to 3.3V rail
1 = VCCPSPI is connected to 1.8V rail
Note: If VCCPSPI is connected to 1.8V rail, this pin
strap must be a ‘1’ for the proper functionality
of the SPI (Flash) I/Os

RH30 20K_040 2_1%

RH31 10K_ 0402_5%

An external pull-up or pull-down is required.

= Integrated CNVi enable.

0
1 = Integrated CNVi disable.

Pulled down by CRF CNVi RGI_DT pin

NC

YH1

CH1

RH14 1 0M_0402_5%

32.768KH Z_9PF_X1A000 141000200

Trace Space: 15 mil

ax Trace Length: 1000 mil

M

1 2

1 2

1 2

1 2

XTAL Frequency Select

1 2

VCCPSPI Select

@

1 2

M.2 CNV Mode Select

1 2

@

2

4

1 2

YH2

12

12

A

SJ10000 TP00

12

1

1

27P_0402_50V8J

10P_0402_50V8J

SSD_CLK REQ1#

LAN_CLK REQ2#

WLA N_CLKREQ3#

GPU_CLK REQ4#

SSD_CLK REQ5#

CNV_BRI_P TX_DRX

GPP_J9

CNV_RGI_P TX_DRX

XTAL_24 M_PCH_OUT

XTAL_24 M_PCH_IN

TXC SJ10000UJ00

Murata SJ10000UJ00

1

CH2

2

PCH_RTC X1

PCH_RTC X2

1

CH4

2

EPSON SJ10000PW00

TXC SJ10000Q400

36

STRAP

STRAP

2 34

3

STRAP

1 2

RH10 3 3_0402_5%EMI@

1 2

RH11 3 3_0402_5%EMI@

CNV_BRI_P TX_R_DRX<49>
CNV_BRI_P RX_DTX<49>
CNV_RGI_P TX_R_DRX<4 9>
CNV_RGI_P RX_DTX<49 >

+1.8V_PR IM

XTAL_24 M_PCH_OUT_R

XTAL_24 M_PCH_IN_R

PCH_CPU _24M_CLK_P<10>
PCH_CPU _24M_CLK_N<1 0>

PCH_CPU _BCLK_P<10>
PCH_CPU _BCLK_N<10>

1 2

XCLK_BIASREF
Trace Width/Space: 15mil /15 mil
Max Trace Length: 1000 mil

RH13 6 0.4_0402_1%

TBT_CLK REQ0#<5 7>
SSD_CLK REQ1#<4 9>
LAN_CLK REQ2#<50>
WLA N_CLKREQ3#<49>
GPU_CLK REQ4#<24>
SSD_CLK REQ5#<4 9>

1 2

RH206 22_0201_5%CNVI@

1 2

RH205 22_0201_5%CNVI@

VCCPSPI Select

@

1 2

RH28 2 0K_0402_1%

@

1 2

RH29 2 0K_0402_1%

B

UH1G

TH1 TP @

XTAL_24 M_PCH_OUT_R
XTAL_24 M_PCH_IN_R

XCLK_BIAS REF

PCH_RTC X1
PCH_RTC X2

CNV_BRI_P TX_DRX
CNV_BRI_P RX_DTX
CNV_RGI_P TX_DRX
CNV_RGI_P RX_DTX

GPP_J9

CNV_BRI_P RX_DTX

CNV_RGI_P RX_DTX

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

571391_CFL_H_PDG_Rev0p71

22

To avoid floating input at the I/O pin BRI_RSP and RGI_RSP it is recommended to add
a weak pull up resistor to the SoC pin with a recommended value of 20K ohm.

BE33

GPP_A16/CLKOUT_48

D7

CLKOUT_CPUNSSC_P

C6

CLKOUT_CPUNSSC#

B8

CLKOUT_CPUBCLK_P

C8

CLKOUT_CPUBCLK#

U9

XTAL_OUT

U10

XTAL_IN

T3

XCLK_BIASREF

BA49

RTCX1

BA48

RTCX2

BF31

GPP_B5/SRCCLKREQ0#

BE31

GPP_B6/SRCCLKREQ1#

AR32

GPP_B7/SRCCLKREQ2#

BB30

GPP_B8/SRCCLKREQ3#

BA30

GPP_B9/SRCCLKREQ4#

AN29

GPP_B10/SRCCLKREQ5#

AE47

GPP_H0/SRCCLKREQ6#

AC48

GPP_H1/SRCCLKREQ7#

AE41

GPP_H2/SRCCLKREQ8#

AF48

GPP_H3/SRCCLKREQ9#

AC41

GPP_H4/SRCCLKREQ10#

AC39

GPP_H5/SRCCLKREQ11#

AE39

GPP_H6/SRCCLKREQ12#

AB48

GPP_H7/SRCCLKREQ13#

AC44

GPP_H8/SRCCLKREQ14#

AC43

GPP_H9/SRCCLKREQ15#

V2

CLKOUT_PCIE_N15

V3

CLKOUT_PCIE_P15

T2

CLKOUT_PCIE_N14

T1

CLKOUT_PCIE_P14

AA1

CLKOUT_PCIE_N13

Y2

CLKOUT_PCIE_P13

AC7

CLKOUT_PCIE_N12

AC6

CLKOUT_PCIE_P12

CML-H_BG A874

@

UH1M

AW13

GPP_G0/SD_CMD

BE9

GPP_G1/SD_DATA0

BF8

GPP_G2/SD_DATA1

BF9

GPP_G3/SD_DATA2

BG8

GPP_G4/SD_DATA3

BE8

GPP_G5/SD_CD#

BD8

GPP_G6/SD_CLK

AV13

GPP_G7/SD_WP

AP3

GPP_I11/M2_SKT2_CFG0

AP2

GPP_I12/M2_SKT2_CFG1

AN4

GPP_I13/M2_SKT2_CFG2

AM7

GPP_I14/M2_SKT2_CFG3

AV6

GPP_J0/CNV_PA_BLANKING

AY3

GPP_J1/CPU_C10_GATE#

AR13

GPP_J11/A4WP_PRESENT

AV7

GPP_J10

AW3

GPP_J_2

AT10

GPP_J_3

AV4

GPP_J4/CNV_BRI_DT/UART0B_RTS#

AY2

GPP_J5/CNV_BRI_RSP/UART0B_RXD

BA4

GPP_J6/CNV_RGI_DT/UART0B_TXD

AV3

GPP_J7/CNV_RGI_RSP/UART0B_CTS#

AW2

GPP_J8/CNV_MFUART2_RXD

AU9

GPP_J9/CNV_MFUART2_TXD

CML-H_BG A874

@

2020/7/31 2020/7/31

2020/7/31 2020/7/31

2020/7/31 2020/7/31

C

CNP-H

CLKOUT_ITPXDP#

CLKOUT_ITPXDP_P

CLKOUT_CPUPCIBCLK#

CLKOUT_CPUPCIBCLK_P

CLKOUT_PCIE_N0
CLKOUT_PCIE_P0

CLKOUT_PCIE_N1
CLKOUT_PCIE_P1

CLKOUT_PCIE_N2
CLKOUT_PCIE_P2

CLKOUT_PCIE_N3
CLKOUT_PCIE_P3

CLKOUT_PCIE_N4
CLKOUT_PCIE_P4

CLKOUT_PCIE_N5
CLKOUT_PCIE_P5

CLKOUT_PCIE_N6
CLKOUT_PCIE_P6

CLKOUT_PCIE_N7
CLKOUT_PCIE_P7

CLKOUT_PCIE_N8
CLKOUT_PCIE_P8

CLKOUT_PCIE_N9
CLKOUT_PCIE_P9

CLKOUT_PCIE_N10

CLKOUT_PCIE_P10

CLKOUT_PCIE_N11

CLKOUT_PCIE_P11

7 OF 13

CLKIN_XTAL

CNP-H

3.3V

1.8V

GPPJ_RCOMP_1P81
GPPJ_RCOMP_1P82
GPPJ_RCOMP_1P83

13 OF 13

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Y3
Y4

B6
A6

AJ6
AJ7

AH9
AH10

AE14
AE15

AE6
AE7

AC2
AC3

AB2
AB3

W4
W3

W7
W6

AC14
AC15

U2
U3

AC9
AC11

AE9
AE11

R6

Rev1.0

CNV_WR_CLKN

CNV_WR_CLKP

CNV_WR_D0N

CNV_WR_D0P

CNV_WR_D1N

CNV_WR_D1P

CNV_WT_CLKN
CNV_WT_CLKP

CNV_WT_D0N
CNV_WT_D0P
CNV_WT_D1N
CNV_WT_D1P

CNV_WT_RCOMP

PCIE_RCOMPN

PCIE_RCOMPP
SD_1P8_RCOMP
SD_3P3_RCOMP

RSVD2
RSVD3

RSVD1

PCH_CPU _PCIBCLK_N
PCH_CPU _PCIBCLK_P

12

BD4
BE3

BB3
BB4
BA3
BA2

BC5
BB6

BE6
BD7
BG6
BF6
BA1

B12
A13
BE5
BE4
BD1
BE1
BE2

Y35
Y36

BC1
AL35

TP

Rev1.0

D

TH2TP@
TH3TP@

RH17

10K_040 2_5%

CLK_CNV _PRX_DTX_N
CLK_CNV _PRX_DTX_P

CNV_PRX _DTX_N0
CNV_PRX _DTX_P0
CNV_PRX _DTX_N1
CNV_PRX _DTX_P1

CLK_CNV _PTX_DRX_N
CLK_CNV _PTX_DRX_P

CNV_PTX _DRX_N0
CNV_PTX _DRX_P0
CNV_PTX _DRX_N1
CNV_PTX _DRX_P1
CNV_W T_RCOMP

PCIE_RCOM PN
PCIE_RCOM PP
SD_RCOM P_1P8
SD_RCOM P_3P3

GPPJ_RC OMP_1P8

RH22

RH23 1 00_0402_1%

RH24 2 00_0402_1%
RH25 2 00_0402_1%

RH26 2 00_0402_1%

#571483_CFL_H_RVP_CRB_TDK_Rev0p5

ecommend external test point

R

Custom

Custom

Custom

PCH_CPU _PCIBCLK_N <1 0>
PCH_CPU _PCIBCLK_P <10>

CLK_PCIE_ N0 <57 >
CLK_PCIE_ P0 <57>

CLK_PCIE_ N1 <49 >
CLK_PCIE_ P1 <49>

CLK_PCIE_ N2 <50 >
CLK_PCIE_ P2 <50>

CLK_PCIE_ N3 <49 >
CLK_PCIE_ P3 <49>

CLK_PEG _N4 <24>
CLK_PEG _P4 <24>

CLK_PCIE_ N5 <49 >
CLK_PCIE_ P5 <49>

REFCLK_ CNV <4 9>

1 2

1 2

1 2
1 2

1 2

TH4TP@

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PCH(2/8)CLK/CNVI/SD

PCH(2/8)CLK/CNVI/SD

PCH(2/8)CLK/CNVI/SD

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

LA-J561P

LA-J561P

LA-J561P

Date: Sheet of

Date: Sheet of

Date: Sheet of

1V@38.4MHZ

CLK_CNV _PRX_DTX_N <49>
CLK_CNV _PRX_DTX_P <49>

CNV_PRX _DTX_N0 <49>
CNV_PRX _DTX_P0 <49>
CNV_PRX _DTX_N1 <49>
CNV_PRX _DTX_P1 <49>

CLK_CNV _PTX_DRX_N <49>
CLK_CNV _PTX_DRX_P <49>

CNV_PTX _DRX_N0 <49>

CNV_PTX _DRX_P0 <49>

CNV_PTX _DRX_N1 <49>

CNV_PTX _DRX_P1 <49>

150_040 2_1%

Thunderbolt

NGFF SSD1

LAN

WLAN

GPU

NGFF SSD2

E

15 10 0Wednesday, February 26, 2020

15 10 0Wednesday, February 26, 2020

15 10 0Wednesday, February 26, 2020

1.0

1.0

1.0

A

UH1E

AT6

GPP_I0/DDPB_HPD0/DISP_MISC0

AN10

GPP_I1/DDPC_HPD1/DISP_MISC1

AP9

GPP_I2/DDPD_HPD2/DISP_MISC2

AL15

GPP_I3/DDPF_HPD3/DISP_MISC3

PCH_SPI_0 _CLK

CH510P_04 02_50V8J

EDP_HPD _CPU

100K_04 02_5%

EDP_HPD _CPU<41>

@RF@

1 2

RV1

AN6

GPP_I4/EDP_HPD/DISP_MISC4

12

CML-H_BG A874

@

03/14 From RF Team Request

UH1A

BE36

+3V_SPI

#610144-intel-400-series-chipset-pch-eds-vol1-rev1p0

1 2

RH32 1 00K_0402_5%

1 2

RH33 1 00K_0402_5%

RH34 1 00K_0402_5%

+3V_1.8V _PGPPHK

RH35 1 00K_0402_5%

#571182_CNL_PCH_H_EDS_V1_Rev0.7
External pull-up is required. Recommend 100K if pulled
up to 3.3V or 75K if pulled up to 1.8V.
571007_CFL_MOW_Archive_WW22_2017
STUFF R on GPP_H15

1 1

12

12

PCH_SPI_0 _D2_R

PCH_SPI_0 _D3_R

PCH_SPI_0 _D0

GPP_H15

STRAP

TH5 TP @

PCH_SPI_0 _D0
PCH_SPI_0 _D1
PCH_SPI_0 _CS#0
PCH_SPI_0 _CLK

TH6 TP @

PCH_SPI_0 _D2
PCH_SPI_0 _D3

GPP_A11/PME#/SD_VDD2_PWR_EN#

R15

RSVD2

R13

RSVD1

AL37

VSS

AN35

TP

AU41

SPI0_MOSI

BA45

SPI0_MISO

AY47

SPI0_CS0#

AW47

SPI0_CLK

AW48

SPI0_CS1#

AY48

SPI0_IO2

BA46

SPI0_IO3

AT40

SPI0_CS2#

BE19

GPP_D1/SPI1_CLK/SBK1_BK1

BF19

GPP_D0/SPI1_CS#/SBK0_BK0

BF18

GPP_D3/SPI1_MOSI/SBK3_BK3

BE18

GPP_D2/SPI1_MISO/SBK2_BK2

BC17

GPP_D22/SPI1_IO3

BD17

GPP_D21/SPI1_IO2

CML-H_BG A874

@

CNP-H

5 OF 13

CNP-H

GPP_K15/GSXSRESET#

GPP_H18/SML4ALERT#

GPP_H15/SML3ALERT#

GPP_H12/SML2ALERT#

1 OF 13

GPP_I5/DDPB_CTRLCLK

GPP_I6/DDPB_CTRLDATA

GPP_I7/DDPC_CTRLCLK

GPP_I8/DDPC_CTRLDATA

GPP_I9/DDPD_CTRLCLK
GPP_I10/DDPD_CTRLDATA
GPP_F23/DDPF_CTRLDATA

GPP_F22/DDPF_CTRLCLK

GPP_F14/PS_ON#

GPP_K23/IMGCLKOUT1
GPP_K22/IMGCLKOUT0

GPP_H23/TIME_SYNC0

GPP_B13/PLTRST#

GPP_K16/GSXCLK

GPP_K12/GSXDOUT

GPP_K13/GSXSLOAD

GPP_K14/GSXDIN

GPP_E3/CPU_GP0
GPP_E7/CPU_GP1
GPP_B3/CPU_GP2
GPP_B4/CPU_GP3

GPP_H17/SML4DATA

GPP_H16/SML4CLK

GPP_H14/SML3DATA

GPP_H13/SML3CLK

GPP_H11/SML2DATA

GPP_H10/SML2CLK

INTRUDER#

Rev1.0

GPP_K21
GPP_K20

AL13
AR8
AN13
AL10
AL9
AR3
AN40
AT49

AP41

M45
L48
T45
T46
AJ47

Rev1.0

AV29

Y47
Y46
Y48
W46
AA45

AL47
AM45
BF32
BC33

AE44
AJ46
AE43
AC47
AD48
AF47
AB47
AD47
AE48

BB44

RVP: 330K
A 1 M pull-up is used on the customer reference
board (CRB). This is needed to reduce leakage
from Coin Cell Battery in G3 state.

DGPU_HO LD_RST#

TBT_CIO_P LUG_EVENT#

PCH_PLT RST#

DGPU_PW ROK

BT_ON

TBT_FOR CE_PWR
RTD3_TB T_EN
GPP_H15
TBT_USB _FORCE_PW R

GPP_H12

SM_INTRUD ER#

PCH_PLT RST#

GPIO Serial Expander (GSX) is the capability
provided by the PCH to expand the GPIOs
on a platform that needs more GPIOs than the
ones provided by the PCH.

GPP_H12 <19>

DGPU_HO LD_RST# <24>

TBT_CIO_P LUG_EVENT# <57 >

1 2

CH6 100P_04 02_50V8J

ESD@

DGPU_PW ROK <34>

BT_ON <49>

TBT_FOR CE_PWR <5 7>
RTD3_TB T_EN < 57>

TBT_USB _FORCE_PW R <57>

+3VL_RT C

12

RH391M_0402 _5%

dGPU

DGU

DGPU_PW ROK

RH36 1 0K_0402_5%

12

+3VS

From EC

From SOC

EC_SPI_CL K<48>
EC_SPI_MO SI<48>
EC_SPI_CS 0#<48>

EC_SPI_MISO<48>

PCH_SPI_0 _CS#0

PCH_SPI_0 _D2_R

PCH_SPI_0 _D1
PCH_SPI_0 _CLK
PCH_SPI_0 _D0
PCH_SPI_0 _D3

PCH_SPI_0 _D2

RC45 56_ 0402_1%

EC_SPI_CL K
EC_SPI_MO SI
EC_SPI_CS 0#
EC_SPI_MISO

SPI ROM 16M Byte

UH3

1
2
3
4

VCC

CS#
DO(IO1)
IO2
GND

W25 Q128JVSIQ_SO8

CLK

DI(IO0)

IO

1 2

RC41 5 6_0402_1%

1 2

RC42 5 6_0402_1%EMI@

1 2

RC43 5 6_0402_1%

1 2

RC44 5 6_0402_1%

1 2

RC46 5 6_0402_1%EMI@
RC47 5 6_0402_1%
RC48 0 _0402_5%@
RC49 5 6_0402_1%

8
7
6
5

PCH_SPI_0 _D2_R

EMI@

1 2
1 2
1 2
1 2

+3V_SPI

@

1 2

CC97 0.1U_020 1_10V K X5R

PCH_SPI_0 _D3_RPCH_SPI_0 _D1_R
PCH_SPI_0 _CLK_R
PCH_SPI_0 _D0_R

PCH_SPI_0 _D1_R
PCH_SPI_0 _CLK_R
PCH_SPI_0 _D0_R
PCH_SPI_0 _D3_R

PCH_SPI_0 _CLK_R
PCH_SPI_0 _D0_R
PCH_SPI_0 _CS#0
PCH_SPI_0 _D1_R

RC64
33_0402 _5%

@EMI@

1 2

1

CC98
10P_040 2_50V8J

2

@EMI@

PCH PLTRST Buffer

PCH_PLT RST#

Security Classification

Security Classification

Security Classification

2020/7/31 2020/7/31

2020/7/31 2020/7/31

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2020/7/31 2020/7/31

A

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

1 2

RH41 0 _0402_5%@

+3VS

1

B

2

A

@

1 2

CH7

0.1U_040 2_10V6K

5

@

UH2

P

4

Y

G

TC7SH08 FU_SSOP5

3

Title

Title

Title

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

12

RH42
100K_02 01_1%

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

PCH(3/8)DDC/SPI

PCH(3/8)DDC/SPI

PCH(3/8)DDC/SPI

LA-J561P

LA-J561P

LA-J561P

PCI_RST# <24,48,49,50 ,57>

16 10 0Wednesday, February 26, 2020

16 10 0Wednesday, February 26, 2020

16 10 0Wednesday, February 26, 2020

1.0

1.0

1.0

A

B

C

D

E

USB3_PT X_DRX_N1<47 >
USB3_PT X_DRX_P1< 47>
USB3_PR X_DTX_N1<47 >

Rear Side

1 1

USB3.1 Gen2 x 2

IO board USB3.1 Gen1

Type-C DP MUX USB3.1 Gen1

2 2

For Intel CLINK

USB3_PR X_DTX_P1< 47>

USB3_PT X_DRX_N2<47 >
USB3_PT X_DRX_P2< 47>
USB3_PR X_DTX_N2<47 >
USB3_PR X_DTX_P2< 47>

USB3_PT X_DRX_P3< 55>
USB3_PT X_DRX_N3<55 >
USB3_PR X_DTX_P3< 55>
USB3_PR X_DTX_N3<55 >

USB3_PT X_DRX_P4< 60>
USB3_PT X_DRX_N4<60 >
USB3_PR X_DTX_P4< 60>
USB3_PR X_DTX_N4<60 >

TH8 TP @
TH10 TP@
TH9 TP @

To SSD2 M.2

PCIE_PTX_ DRX_P11<49>
PCIE_PTX_ DRX_N11<49>
PCIE_PRX_ DTX_P11<49>
PCIE_PRX_ DTX_N11<49>

3 3

LAN

To SSD2 M.2

PCIE_PTX_ C_DRX_N14<50>
PCIE_PTX_ C_DRX_P14<50>
PCIE_PRX_ DTX_N14<50>
PCIE_PRX_ DTX_P14<50>

HDD

PCIE_PTX_ DRX_P12<49>
PCIE_PTX_ DRX_N12<49>
PCIE_PRX_ DTX_P12<49>

PCIE_PTX_ TRX_P20<57>

PCIE_PTX_ TRX_N20<57>

PCIE_PRX_ TTX_P20<57>

PCIE_PRX_ TTX_N20<57>

PCIE_PTX_ TRX_P19<57>

PCIE_PTX_ TRX_N19<57>

PCIE_PRX_ TTX_P19<57>

PCIE_PRX_ TTX_N19<57>

PCIE_PRX_ DTX_N12<49>

SATA_PT X_DRX_P0< 54>
SATA_PR X_DTX_N0<54 >
SATA_PR X_DTX_P0< 54>

1 2

CH12 0.1U_020 1_10V6K

1 2

CH13 0.1U_020 1_10V6K

SATA_PT X_DRX_N0<54 >

1 2

CH14 0.22U_02 01_6.3VTBT@

1 2

CH15 0.22U_02 01_6.3VTBT@

1 2

CH16 0.22U_02 01_6.3VTBT@

1 2

CH17 0.22U_02 01_6.3VTBT@

USB3_PT X_DRX_N1
USB3_PT X_DRX_P1
USB3_PR X_DTX_N1
USB3_PR X_DTX_P1

USB3_PT X_DRX_N2
USB3_PT X_DRX_P2
USB3_PR X_DTX_N2
USB3_PR X_DTX_P2

USB3_PT X_DRX_P3
USB3_PT X_DRX_N3
USB3_PR X_DTX_P3
USB3_PR X_DTX_N3

USB3_PT X_DRX_P4
USB3_PT X_DRX_N4
USB3_PR X_DTX_P4
USB3_PR X_DTX_N4

CL_CLK
CL_DATA
CL_RST#

PCIE_PTX_ DRX_P11
PCIE_PTX_ DRX_N11
PCIE_PRX_ DTX_P11
PCIE_PRX_ DTX_N11

PCIE_PTX_ DRX_N14
PCIE_PTX_ DRX_P14
PCIE_PRX_ DTX_N14
PCIE_PRX_ DTX_P14

SATA_PT X_DRX_N0
SATA_PT X_DRX_P0
SATA_PR X_DTX_N0
SATA_PR X_DTX_P0

PCIE_PTX_ DRX_P12
PCIE_PTX_ DRX_N12
PCIE_PRX_ DTX_P12
PCIE_PRX_ DTX_N12

PCIE_PTX_ C_TRX_P20
PCIE_PTX_ C_TRX_N20

PCIE_PTX_ C_TRX_P19
PCIE_PTX_ C_TRX_N19

To Thunderbolt

4 4

A

B

UH1F

F9

USB31_1_TXN

F7

USB31_1_TXP

D11

USB31_1_RXN

C11

USB31_1_RXP

C3

USB31_2_TXN

D4

USB31_2_TXP

B9

USB31_2_RXN

C9

USB31_2_RXP

C17

USB31_6_TXN

C16

USB31_6_TXP

G14

USB31_6_RXN

F14

USB31_6_RXP

C15

USB31_5_TXN

B15

USB31_5_TXP

J13

USB31_5_RXN

K13

USB31_5_RXP

G12

USB31_3_TXP

F11

USB31_3_TXN

C10

USB31_3_RXP

B10

USB31_3_RXN

C14

USB31_4_TXP

B14

USB31_4_TXN

J15

USB31_4_RXP

K16

USB31_4_RXN

CML-H_BG A874

@

UH1C

AR2

CL_CLK

AT5

CL_DATA

AU4

CL_RST#

P48

GPP_K8

V47

GPP_K9

V48

GPP_K10

W47

GPP_K11

L47

GPP_K0

L46

GPP_K1

U48

GPP_K2

U47

GPP_K3

N48

GPP_K4

N47

GPP_K5

P47

GPP_K6

R46

GPP_K7

C36

PCIE11_TXP/SATA0A_TXP

B36

PCIE11_TXN/SATA0A_TXN

F39

PCIE11_RXP/SATA0A_RXP

G38

PCIE11_RXN/SATA0A_RXN

AR42

GPP_F10/SATA_SCLOCK

AR48

GPP_F11/SATA_SLOAD

AU47

GPP_F13/SATA_SDATAOUT0

AU46

GPP_F12/SATA_SDATAOUT1

C39

PCIE14_TXN/SATA1B_TXN

D39

PCIE14_TXP/SATA1B_TXP

D46

PCIE14_RXN/SATA1B_RXN

C47

PCIE14_RXP/SATA1B_RXP

B38

PCIE13_TXN/SATA0B_TXN

C38

PCIE13_TXP/SATA0B_TXP

C45

PCIE13_RXN/SATA0B_RXN

C46

PCIE13_RXP/SATA0B_RXP

E37

PCIE12_TXP/SATA1A_TXP

D38

PCIE12_TXN/SATA1A_TXN

J41

PCIE12_RXP/SATA_1A_RXP

H42

PCIE12_RXN/SATA1A_RXN

B44

PCIE20_TXP/SATA7_TXP

A44

PCIE20_TXN/SATA7_TXN

R37

PCIE20_RXP/SATA7_RXP

R35

PCIE20_RXN/SATA7_RXN

D43

PCIE19_TXP/SATA6_TXP

C44

PCIE19_TXN/SATA6_TXN

N42

PCIE19_RXP/SATA6_RXP

M44

PCIE19_RXN/SATA6_RXN

CML-H_BG A874

@

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

CNP-H

GPP_A1/LAD0/ESPI_IO0

1.8V

GPP_A2/LAD1/ESPI_IO1

(

eSPI)

GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS0#

GPP_A6/SERIRQ/ESPI_CS1#

GPP_A7/PIRQA#/ESPI_ALERT0#

GPP_A0/RCIN#/ESPI_ALERT1#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

GPP_K19/SMI#

GPP_K18/NMI#

GPP_E6/SATA_DEVSLP2
GPP_E5/SATA_DEVSLP1
GPP_E4/SATA_DEVSLP0
GPP_F9/SATA_DEVSLP7
GPP_F8/SATA_DEVSLP6
GPP_F7/SATA_DEVSLP5
GPP_F6/SATA_DEVSLP4
GPP_F5/SATA_DEVSLP3

6 OF 13

CNP-H

PCIE9_RXN
PCIE9_RXP
PCIE9_TXN

PCIE9_TXP

PCIE10_RXN

PCIE10_RXP
PCIE10_TXN
PCIE10_TXP

PCIE15_RXN/SATA2_RXN
PCIE15_RXP/SATA2_RXP

PCIE_15_SATA_2_TXN

PCIE15_TXP/SATA2_TXP

PCIE16_RXN/SATA3_RXN
PCIE16_RXP/SATA3_RXP
PCIE16_TXN/SATA3_TXN

PCIE16_TXP/SATA3_TXP

PCIE17_RXN/SATA4_RXN
PCIE17_RXP/SATA4_RXP
PCIE17_TXN/SATA4_TXN

PCIE17_TXP/SATA4_TXP

PCIE18_RXN/SATA5_RXN
PCIE18_RXP/SATA5_RXP
PCIE18_TXN/SATA5_TXN

PCIE18_TXP/SATA5_TXP

GPP_E8/SATA_LED#

GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2

GPP_F0/SATAXPCIE3/SATAGP_3

GPP_F1/SATAXPCIE4/SATAGP4
GPP_F2/SATAXPCIE5/SATAGP5
GPP_F3/SATAXPCIE6/SATAGP6
GPP_F4/SATAXPCIE7/SATAGP7

GPP_F21/EDP_BKLTCTL

GPP_F20/EDP_BKLTEN

GPP_F19/EDP_VDDEN

THRMTRIP#

3 OF 13

PLTRST_CPU#

PM_DOWN

2020/7/31 2020/7/31

2020/7/31 2020/7/31

2020/7/31 2020/7/31

C

BB39
AW37
AV37
BA38

BE38
AW35
BA36
BE39
BF38

BB36
BB34

T48
T47

AH40
AH35
AL48
AP47
AN37
AN46
AR47
AP48

Rev1.0

PECI

PM_SYNC

Rev1.0

Compal Secret Data

Compal Secret Data

Compal Secret Data

PCH_SER IRQ
PIRQA#

KB_RST#

HDMI_HPD_ PCH_K19

G36
F36
C34
D34

K37
J37
C35
B35

F44
E45
B40
C40

L41
M40
B41
C41

K43
K44

PCIE_PTX_ C_TRX_N17

A42

PCIE_PTX_ C_TRX_P17

B42

P41
R40

PCIE_PTX_ C_TRX_N18

C42

PCIE_PTX_ C_TRX_P18

D42

SATA_LE D#

AK48

AH41
AJ43
AK47
AN47
AM46
AM43
AM47
AM48

PCH_BKL _PWM

AU48

PCH_ENB KL

AV46

PCH_ENV DD

AV44

PCH_THE RMTRIP#

AD3

PCH_PEC I

AF2

H_PM_SYNC

AF3

H_PLTRS T_CPU#

AG5

H_PM_DO WN_R

AE2

Deciphered Date

Deciphered Date

Deciphered Date

LPC_AD0 <4 8>
LPC_AD1 <4 8>
LPC_AD2 <4 8>
LPC_AD3 <4 8>

LPC_FRA ME# <48>

1 2

RH195 0_0402_5%@

CLK_LPC

RH198

1 2

0_0402_ 5%@

RTD3_TB T_WAKE# <57>

PCIE_PRX_ DTX_N9
PCIE_PRX_ DTX_P9
PCIE_PTX_ DRX_N9
PCIE_PTX_ DRX_P9

PCIE_PRX_ DTX_N10
PCIE_PRX_ DTX_P10
PCIE_PTX_ DRX_N10
PCIE_PTX_ DRX_P10

PCIE_PRX_ DTX_N15
PCIE_PRX_ DTX_P15
PCIE_PTX_ DRX_N15
PCIE_PTX_ DRX_P15

EMI@

1 2

RH46 22_04 02_5%

To Thunderbolt

CH8 0 .22U_0201_6.3VTBT@
CH9 0 .22U_0201_6.3VTBT@

CH10 0.22U_0 201_6.3VTBT@
CH11 0.22U_0 201_6.3VTBT@

RH196 10K_0402_5%

1 2

RH48 620_0402_5%

1 2

RH49 13_0402_5%

1 2

RH50 3 0_0402_5%

1 2

#571391_CFL_H_PDG_Rev0p5

12.2.10 PM_DOWN Topology

12
12

12
12

12

RTD3_TB T_PERST# <57>

PCH_BKL _PWM <41>
PCH_ENB KL <25,41>
PCH_ENV DD <4 1>

@

RH51
13_0402 _5%

D

SERIRQ <48>

HDMI_HPD_ PCH <19,43 >

PCIE_PRX_ DTX_N9 <49>
PCIE_PRX_ DTX_P9 <49>
PCIE_PTX_ DRX_N9 <49>

PCIE_PRX_ DTX_N10 <49>
PCIE_PRX_ DTX_P10 <49>
PCIE_PTX_ DRX_N10 <49>

PCIE_PRX_ DTX_N15 <49>
PCIE_PRX_ DTX_P15 <49>
PCIE_PTX_ DRX_N15 <49>
PCIE_PTX_ DRX_P15 <49>

+3VS

#571391_CFL_H_PDG_Rev0p5.pdf

H_PECI
H_PM_SYNC _R

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PCIE/SATA/USB3/eSPI

PCIE/SATA/USB3/eSPI

PCIE/SATA/USB3/eSPI

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Custom

Custom

Custom

LA-J561P

LA-J561P

LA-J561P

Date: Sheet of

Date: Sheet of

Date: Sheet of

KB_RST#

SERIRQ

10P_0402_50V8J

PCIE_PTX_ DRX_P9 <49>

PCIE_PTX_ DRX_P10 <49>

PCH_THE RMTRIP#_R

1 2

RH44 10K_ 0402_5%

1 2

RH45 10K_ 0402_5%

1

CH55

@RF@

2

PCIE_PRX_ TTX_N17 <5 7>

PCIE_PRX_ TTX_P17 <57>
PCIE_PTX_ TRX_N17 <5 7>
PCIE_PTX_ TRX_P17 <57>

PCIE_PRX_ TTX_N18 <5 7>

PCIE_PRX_ TTX_P18 <57>
PCIE_PTX_ TRX_N18 <5 7>
PCIE_PTX_ TRX_P18 <57>

1 2

RH43 10K_ 0402_5%

PIRQA#

RH166 close to PCH

PCH_THE RMTRIP#_R <10>
H_PECI <10,48>
H_PM_SYNC _R < 10>
H_PLTRS T_CPU# <10>
H_PM_DO WN_R <10 >

Change Net Name and
Add Pull Down for vendor suggest
20190812

+1.8VS_3 VS_PGPPA

CLK_LPC _EC <48>

To SSD2 M.2

WLAN

+1.05V_V CCST

12

RH471K_0402_5%

PCH_ENB KL

12

RH192
10K_020 1_5%

17 10 0Wednesday, February 26, 2020

17 10 0Wednesday, February 26, 2020

17 10 0Wednesday, February 26, 2020

E

1.0

1.0

1.0

A

B

C

D

E

@RF@

1 2

CH18 2.2P_0 402_50V8C

@RF@

1 2

CH19 2.2P_0 402_50V8C

@RF@

1 2

CH20 2.2P_0 402_50V8C

3/16 From RF Team Request

T20 TP@

30_0402 _5%

30_0402 _5%

CLKREQ_ CNV#
CNV_RF_ RESET#

1 2

RH64 10K_ 0402_5%

1 2

RH65 10K_ 0402_5%

1 2

RH67 10K_ 0402_5%

1 2

RH68 10K_ 0402_5%

S

MB

HDA_BIT_C LKHDA_BIT_C LK_R
HDA_SDO UT
HDA_SYNC

HDA_SDIN0<45>

RH56

1 2

RH58

1 2

CLKREQ_ CNV#<4 9>
CNV_RF_ RESET#<49>

EC_CLEA R_CMOS#<4 8>

PCH_PW ROK<48>
EC_RSMR ST#<4 8>

SMBALER T#<1 9>
PCH_SMB CLK< 22,23>
PCH_SMB DATA<22,23>

PCH_SML 0ALERT#<1 9>

PCH_SML 1ALERT#<1 9>
EC_SMB_ CK2<25,41 ,48,51,60>
EC_SMB_ DA2<25,41 ,48,51,60>

+3VALW +3VALW

1 2

HDA_BIT_C LK_R<45>
HDA_SDO UT_R<45>

HDA_SYNC_ R<4 5>

1 1

FOR Jefferson Peak RESET pin is glitch free,it
is recommended that a pull-down resistor of 75K
ohm on GPP_D5(CNV_RF_RESET#)

+3VL_RT C

2 2

+PCH_DS W

3 3

+1.8VS_3 VS_PGPPA

+3VALW

RH59 2 0K_0402_1%

CH23 1 U_0201_6.3V6M

RH60 2 0K_0402_1%

CH24 1 U_0201_6.3V6M

CLRP1 SHOR T PADS

RH62 1 K_0402_5%

RH63 8 .2K_0402_5%

RH69 1 00K_0402_5%@

RH66 1 00K_0402_5%

LPC@

RH71 8 .2K_0402_5%

+3VS

RH73 1K_0 402_5%
RH74 1K_0 402_5%
RH75 1K_0 402_5%
RH76 1K_0 402_5%

RH78 1K_0 402_5%
RH79 1K_0 402_5%

1 2

1 2

1 2

1 2

1 2

12

12

12

12

12

1 2
1 2
1 2
1 2

1 2
1 2

HDA_SDO UT_R
HDA_SYNC_ R

CPU_DISPA _SDO_R<6>

CPU_DISPA _SDI_R<6>

CPU_DISPA _BCLK_R<6>

modified in 2017/12/03

RH53 3 3_0402_5%

1 2

RH54 3 3_0402_5%

1 2

RH55 3 3_0402_5%

CPU_DISPA _SDO_R

CPU_DISPA _BCLK_R

PCH_SRT CRST#

EC_CLEA R_CMOS#

ECLR CMOS
Delay 18~25 ms

SML1

(Link to EC,DGPU)

TBT_W AKE#

PM_BATL OW#

PBTN_OU T#_R

AC_PRES ENT

PM_CLKR UN#

PCH_SML 0CLK
PCH_SML 0DATA
EC_SMB_ CK2
EC_SMB_ DA2

PCH_SMB CLK
PCH_SMB DATA

(Link to DDR)

HDA_BIT_C LK_R

HDA_SYNC_ R

HDA_SDO UT_R

HDA_BIT_C LK
HDA_SDIN0
HDA_SDO UT
HDA_SYNC

HDA_RST #

CPU_DISPA _SDO
CPU_DISPA _SDI_R
CPU_DISPA _BCLK

PCH_SRT CRST#

PCH_PW ROK
EC_RSMR ST#

PCH_DPW ROK
SMBALER T#

PCH_SMB CLK
PCH_SMB DATA

PCH_SML 0ALERT#
PCH_SML 0CLK
PCH_SML 0DATA
PCH_SML 1ALERT#
EC_SMB_ CK2
EC_SMB_ DA2

UH1D

BD11

HDA_BCLK/I2S0_SCLK

BE11

HDA_SDI0/I2S0_RXD

BF12

HDA_SDO/I2S0_TXD

BG13

HDA_SYNC/I2S0_SFRM

BE10

HDA_RST#/I2S1_SCLK

BF10

HDA_SDI1/I2S1_RXD

BE12

I2S1_TXD/SNDW2_DATA

BD12

I2S1_SFRM/SNDW2_CLK

AM2

HDACPU_SDO

AN3

HDACPU_SDI

AM3

HDACPU_SCLK

AV18

GPP_D8/I2S2_SCLK

AW18

GPP_D7/I2S2_RXD

BA17

GPP_D6/I2S2_TXD/MODEM_CLKREQ

BE16

GPP_D5/I2S2_SFRM/CNV_RF_RESET#

BF15

GPP_D20/DMIC_DATA0/SNDW4_DATA

BD16

GPP_D19/DMIC_CLK0/SNDW4_CLK

AV16

GPP_D18/DMIC_DATA1/SNDW3_DATA

AW15

GPP_D17/DMIC_CLK1/SNDW3_CLK

BE47

RTCRST#

BD46

SRTCRST#

AY42

PCH_PWROK

BA47

RSMRST#

AW41

DSW_PWROK

BE25

GPP_C2/SMBALERT#

BE26

GPP_C0/SMBCLK

BF26

GPP_C1/SMBDATA

BF24

GPP_C5/SML0ALERT#

BF25

GPP_C3/SML0CLK

BE24

GPP_C4/SML0DATA

BD33

GPP_B23/SML1ALERT#/PCHHOT#

BF27

GPP_C6/SML1CLK

BE27

GPP_C7/SML1DATA

CML-H_BG A874

@

PCH_PW ROK
LAN_W AKE#
EC_RSMR ST#
SYS_RESET #

CNP-H

GPP_A12/BM_BUSY#/ISH_GP6/SX_EXIT_HOLDOFF#

GPP_B1/GSPI1_CS1#/TIME_SYNC1

1.8V

GPP_A13/SUSWARN#/SUSPWRDNACK

4 OF 13

1 2

RH70 0 _0402_5%@

1 2

From ESD Team R equest

GPP_A8/CLKRUN#

GPD11/LANPHYPC

GPD9/SLP_WLAN#

DRAM_RESET#

GPP_B2/VRALERT#

GPP_B0/GSPI0_CS1#

GPP_K17/ADR_COMPLETE

GPP_B11/I2S_MCLK

SYS_PWROK

WAKE#

GPD6/SLP_A#

SLP_LAN#

GPP_B12/SLP_S0#

GPD4/SLP_S3#
GPD5/SLP_S4#

GPD10/SLP_S5#

GPD8/SUSCLK

GPD0/BATLOW#

GPP_A15/SUSACK#

GPD2/LAN_WAKE#
GPD1/ACPRESENT

SLP_SUS#

GPD3/PWRBTN#

SYS_RESET#

GPP_B14/SPKR

CPUPWRGD

ITP_PMODE

PCH_JTAGX
PCH_JTAG_TMS
PCH_JTAG_TDO

PCH_JTAG_TDI

PCH_JTAG_TCK

PCH_DPW ROKEC_RS MRST#

PCH_DPW ROK

SYS_RESET #

SYS_PW ROK

PCH_PW ROK

@ESD@

1 2

@ESD@

1 2

@ESD@

1 2

RH72100K_0402 _5% @

CH25100P_04 02_50V8J

CH26100P_04 02_50V8J

CH27100P_04 02_50V8J

Near PCH side

SYS_PW ROK

Rev1.0

BF36

PM_CLKR UN#

AV32

BF41

BD42

DDR_DRA MRST#

BB46
BE32
BF33
BE29
R47
AP29

SYS_PW ROK

AU3

TBT_W AKE#

BB47
BE40
BF40

PM_SLP_ S0#

BC28

PM_SLP_ S3#

BF42

PM_SLP_ S4#

BE42

PM_SLP_ S5#

BC42

BE45

SUSCLK
PM_BATL OW#

BF44

SUSACK# _R

BE35
BC37

SUSW ARN#

LAN_W AKE#

BG44
BG42

SLP_SUS #

BD39

PBTN_OU T#_R PBTN_OU T#

BE46
AU2
AW29
AE3

AL3
AH4
AJ4
AH3
AH2
AJ3

SYS_RESET #
SPKR

H_CPUPW RGD

1K_0402 _5%

12

XDP_ITP_P MODE
CPU_XDP _TCK0
CPU_XDP _TMS
CPU_XDP _TDO
CPU_XDP _TDI
PCH_JTA G_TCK1

+1.8V_PR IM

12

RH91

RH77
100K_04 02_5%

RH61 0 _0402_5%@

PM_CLKR UN# <48>

SYS_PW ROK <48>

TBT_W AKE# <57>

T3T P@

PM_SLP_ S3# <10,48 ,86>
PM_SLP_ S4# <48,85 >

T4T P@

T5T P@
T6T P@

1 2

TP@

HDA_SDO UT_D

This signal has a weak internal Pull-down.
0 = Enable security measures defined in the Flash Descriptor. (Default)
1 = Disable Flash Descriptor Security (override). This
strap should only be asserted high using external
Pull-up in manufacturing/debug environments ONLY.
Notes:

1. The internal Pull-down is disabled after PCH_PWROK is high.

2. This signal is in the primary well.

TP@

SPKR <19,45,48 >

H_CPUPW RGD <10>

CPU_XDP _TCK0 <10>

CPU_XDP _TMS <10 >
CPU_XDP _TDO <10>

CPU_XDP _TDI <10>

T8

2

1 3

D

BSS138W _SOT323-3

+1.2V

RH57
470_040 2_1%

1 2

2

CH22
100P_04 02_50V8J

@ESD@

1

Near PCH

SUSCLK <49 >
PM_BATL OW# <57>

T7

--No Support Deep Sx

AC_PRES ENT <48>

PBTN_OU T# <48>

Connect CPU & PCH

ME_EN

1 2

@

0_0402_ 5%

G

QH1

RH194

S

@

1 2

ME_EN <48>

HDA_SDO UT

RH193
30K_040 2_5%

DDR_DRA MRST# <22,23>

4 4

+1.05VAL W

Security Classification

Security Classification

RH80 1K_0 402_5%CMC@

12

A

XDP_ITP_P MODE

B

Security Classification

2020/7/31 2020/7/31

2020/7/31 2020/7/31

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2020/7/31 2020/7/31

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PCH(5/8)PMU/HDA/SMBUS/DMIC

PCH(5/8)PMU/HDA/SMBUS/DMIC

PCH(5/8)PMU/HDA/SMBUS/DMIC

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Custom

Custom

Custom

LA-J561P

LA-J561P

LA-J561P

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

18 10 0Wednesday, February 26, 2020

18 10 0Wednesday, February 26, 2020

18 10 0Wednesday, February 26, 2020

E

1.0

1.0

1.0

A

B

C

D

E

+3VS

1 2

RH81 1K_0 402_5%

1 2

RH82 1K_0 402_5%

+3VS

1 2

1 2

1 2

1 2

1 2

1 2

@

1 2

1 2

12

12

12

12

12

@

12

A

1 1

2 2

3 3

4 4

RH37 100K_04 02_5%@

RH83 49.9K_04 02_1%

RH84 49.9K_04 02_1%

RH85 49.9K_04 02_1%@

RH86 49.9K_04 02_1%@

RH87 10K_040 2_5%@

RH88 10K_040 2_5%DIS@

+3V_1.8V _PGPPHK

RH89 4 .7K_0402_5%@

This signal has a weak internal pull-down.
0 = Master Attached Flash Sharing (MAFS) enabled (Default)
1 = Slave Attached Flash Sharing (SAFS) enabled.
Notes:

1. This signal is in the primary well.
Warning: This strap must be configured to ‘0’ if the
eSPI or LPC strap is configured to ‘0’

+3VALW

RH90 4 .7K_0402_5%ESP I@

This signal has a weak internal Pull-down.
0 = LPC is selected (for EC 9022).(Default)
1 = eSPI is selected (for EC 9042).
Notes:

1. The internal Pull-down is disabled after RSMRST#
de-asserts.

2. This signal is in the primary well.

RH96 4 .7K_0402_5%@

This signal has a weak internal Pull-down.
0 = Disable Intel ME Crypto Transport Layer Security
(TLS) cipher suite (no confidentiality). (Default)
1 = Enable Intel ME Crypto Transport Layer Security
(TLS) cipher suite (with confidentiality). Must be
pulled up to support Intel AMT with TLS.
Notes:

1. The internal Pull-down is disabled after RSMRST#
de-asserts.

2. This signal is in the primary well.

To stuff RH63 for ORB Debug used ,otherwise un-stuff.

RH103 150K_04 02_1%

This signal has an internal pull-down.
0

= Disable IntelR DCI-OOB (Default)

1 = Enable IntelR DCI-OOB

1. The internal pull-down is disabled after RSMRST# de-asserts.

2. When used as PCHHOT# and strap low, a 150K
pull-up is needed to ensure it does not override the
internal pull-down strap sampling.

CFL_H_PDG_REV0.71(SML1ALERT#)
>If USB 3.0 Port 1 is used for 4-wire DCI.OOB (BSSB), and alternate functionality is also
used on the pin, pull up to V3.3S with >100K resistor to avoid noise.
>If USB 3.0 Port 1 is used for DCI.OOB (BSSB) 4-wire BSSB, and NO alternate functionality
is used, leave float.
>If DCI.OOB (BSSB) 2+2 functionality is used, pull up to V3.3S with a 4.7K resistor.

+3VS

RH108 4.7K_04 02_5%@

The signal has a weak internal Pull-down.
0 = Disable “No Reboot” mode. (Default)
1 = Enable “No Reboot” mode (PCH will disable the
TCO Timer system reboot feature). This function is
useful when running ITP/XDP.
Notes:

1. The internal Pull-down is disabled after
PCH_PWROK is high.

2. This signal is in the primary well.

RH111 150K_04 02_1%

This Signal has a weak internal Pull-down.
0: SPI (Default)
1: LPC
Notes:

1. The internal Pull-down is disabled after PCH_PWROK is high.

2. This signal is in the primary well.

RH114 100K_0 402_5%@

Top Swap Override
0 = Disable “Top Swap” mode. (Default)
1 = Enable “Top Swap” mode.
The internal Pull-down is disabled after PCH_PWROK is high.

I2C_1_SCL
I2C_1_SDA

TP_INT#

UART_2_ PRXD_DTXD

UART_2_ PTXD_DRXD

UART_2_ PRTS_DCTS

UART_2_ PCTS_DRTS

DGPU_PW R_EN

GPP_H12

PCH_SML 0ALERT#

SMBALER T#

PCH_SML 1ALERT#

GSPI0_MOS I

GSPI1_MOS I

SPKR

Change GPIO NET NAME
20190812

Infrom BIOS Team

GPP_H12 <16>

STRAP

PCH_SML 0ALERT# <18>

STRAP

SMBALER T# <18>

STRAP

PCH_SML 1ALERT# <18>

STRAP

STRAP

STRAP

SPKR <18,45,48 >

STRAP

DGU

DGU

DGU

HDMI_HPD_ PCH<17 ,43>
TDP_HPD _PCH<6 0>

DGU

GSPI1_MOS I
GPU_ID
EC_SCI#

GPU_EVE NT#

GSPI0_MOS I
GPU_ID2
GPU_ID1

PCH_EDP _SW
EC_W L_OFF#
TBTA_HP D_PCH
TBTB_HP D_PCH

TP_INT#

TDP_HPD _PCH
DGPU_PW R_EN

UART_2_ PCTS_DRTS
UART_2_ PRTS_DCTS
UART_2_ PTXD_DRXD
UART_2_ PRXD_DTXD

RH201 10K _0201_5%@

RH202 10K _0201_5%@

RH95 10K_0 201_5%@

RH98 10K_0 201_5%@

RH100 10K _0201_5%@

RH102 10K _0201_5%@

N18G0@

N18G0

N18G1@

N18G1 N18G1

N18G1R@

GPU_GC6 _FB_EN_H<34>

UART_2_ PTXD_DRXD<49>

UART_2_ PRXD_DTXD<49>

TP

RH202

N18G0

10K_0201_5%

RH202

N18G1

10K_0201_5%

RH202

EC_SCI#<48>

GPU_EVENT#<25>

PCH_EDP_SW<4 1>

EC_WL_OFF #<49>
TBTA_HP D_PCH<57>
TBTB_HP D_PCH<57>

TP_INT#<52>

1 2

RH197 0_0402 _5%

DGPU_PWR_E N<34,48>

I2C_1_SCL<52>

I2C_1_SDA<52>

GPU_ID2

GPU_ID1

GPU_ID

RH98

N18G0@

10K_0201_5%

N18G1@ RH100

RH98

10K_0201_5%

N18G1R@

RH95

N18G1R N18G1R N18G1R

10K_0201_5%

RH202

N18G2R

10K_0201_5%

B

N18G2R@

10K_0201_5%

RH95

N18G2R@

N18G2R N18G2R

10K_0201_5%

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

HDMI_HPD_ PCH_C14

I2C_1_SCL
I2C_1_SDA

1 2

1 2

1 2

1 2

1 2

1 2

RH102

N18G0

10K_0201_5%

10K_0201_5%

RH102

10K_0201_5%

RH100

10K_0201_5%

N18G0@

N18G1@

N18G1R@

N18G2R@

UH1K

BA26

GPP_B22/GSPI1_MOSI

BD30

GPP_B21/GSPI1_MISO

AU26

GPP_B20/GSPI1_CLK

AW26

GPP_B19/GSPI1_CS0#

BE30

GPP_B18/GSPI0_MOSI

BD29

GPP_B17/GSPI0_MISO

BF29

GPP_B16/GSPI0_CLK

BB26

GPP_B15/GSPI0_CS0#

BB24

GPP_C9/UART0A_TXD

BE23

GPP_C8/UART0A_RXD

AP24

GPP_C11/UART0A_CTS#

BA24

GPP_C10/UART0A_RTS#

BD21

GPP_C15/UART1_CTS#/ISH_UART1_CTS#

AW24

GPP_C14/UART1_RTS#/ISH_UART1_RTS#

AP21

GPP_C13/UART1_TXD/ISH_UART1_TXD

AU24

GPP_C12/UART1_RXD/ISH_UART1_RXD

AV21

GPP_C23/UART2_CTS#

AW21

GPP_C22/UART2_RTS#

BE20

GPP_C21/UART2_TXD

BD20

GPP_C20/UART2_RXD

BE21

GPP_C19/I2C1_SCL

BF21

GPP_C18/I2C1_SDA

BC22

GPP_C17/I2C0_SCL

BF23

GPP_C16/I2C0_SDA

BE15

GPP_D4/ISH_I2C2_SDA/I2C3_SDA/SBK4_BK4

BE14

GPP_D23/ISH_I2C2_SCL/I2C3_SCL

CML-H_BG A874

@

+3VS

+3VS

+3VS

Function

N18G1 dGPU 0

N18G1R dGPU

N18G2R dGPU

N18G3R dGPU 1 00

RH201

N18G3R@

N18G3R

10K_0201_5%

Compal Secret Data

Compal Secret Data

2020/7/31 2020/7/31

2020/7/31 2020/7/31

2020/7/31 2020/7/31

C

Compal Secret Data

CNP-H

Rev1.0

GPP_B21

0N18G0 dGPU

1

01

1

BA20
BB20
BB16
AN18

BF14
AR18
BF17
BE17

AG45
AH46

AH47
AH48

AV34
AW32
BA33
BE34
BD34
BF35
BD38

PCH_LCD VDD_RST#

Add PCH GPIO and Pull High for vendor suggest
20190812

T10T P@
T11T P@

DGPU_PR SNT#
SKU_ID
PCH_LCD VDD_RST#
OD_ON_O FF

DDS_STR AP
GSYNC_STR AP

OD_ON_OFF connect between PCH and Panel
20190812

1 2

RH191 10K _0201_5%

PCH_LCD VDD_RST# <4 1>
OD_ON_O FF <42>

For BIOS setting dGPU present

+3VS

LOW - dGPU exist

DGPU_PR SNT#

UMA@

1 2

RH92 10K _0402_5%

1 2

DIS@

RH93 10K _0402_5%

Function

GPP_A17

GSYNC 1

GSYNC_STR AP

NOGSYNC

RH99 10K_0 201_5%

RH101 10K _0201_5%

Function

DDS

GSYNC@

1 2

1 2

NOGSYNC@

GPP_A18

0

1

NODDS 0

DDS_STR AP

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PCH(6/8)GPIO/I2C/UART/STRAP

PCH(6/8)GPIO/I2C/UART/STRAP

PCH(6/8)GPIO/I2C/UART/STRAP

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Custom

Custom

Custom

LA-J561P

LA-J561P

LA-J561P

Date: Sheet of

Date: Sheet of

Date: Sheet of

DDS@

1 2

RH199 10K _0201_5%

1 2

RH200 10K _0201_5%

NODDS@

E

+1.8VS_3 VS_PGPPA

+3VS

+3VS

19 10 0Wednesday, February 26, 2020

19 10 0Wednesday, February 26, 2020

19 10 0Wednesday, February 26, 2020

GPP_D9/ISH_SPI_CS#/GSPI2_CS0#

GPP_D11/ISH_SPI_MISO/GP_BSSB_CLK/GSPI2_MISO

GPP_D12/ISH_SPI_MOSI/GP_BSSB_DI/GSPI2_MOSI

GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#/CNV_WFEN

GPP_D10/ISH_SPI_CLK/GSPI2_CLK

GPP_D16/ISH_UART0_CTS#/CNV_WCEN

GPP_D14/ISH_UART0_TXD/I2C2_SCL

GPP_D13/ISH_UART0_RXD/I2C2_SDA

GPP_H20/ISH_I2C0_SCL
GPP_H19/ISH_I2C0_SDA

GPP_H22/ISH_I2C1_SCL
GPP_H21/ISH_I2C1_SDA

GPP_A23/ISH_GP5
GPP_A22/ISH_GP4
GPP_A21/ISH_GP3
GPP_A20/ISH_GP2
GPP_A19/ISH_GP1

GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7

11 OF 13

GPP_A18/ISH_GP0

Function

17"

GPP_A22

1

015"

SKU_ID

GPU_ID2

GPP_B17

0

1 2

RH94 10K_0 201_5%17@

1 2

RH97 10K_0 201_5%15@

GPU_ID1 GPU_ID

GPP_B16

0

0

0

1

N18G3R@

RH98

0

N18G3R@

RH102

N18G3R N18G3R

10K_0201_5%

SCI capability is available on all GPIOs
PCH GPIOs that can be routed to generate SMI# or NMI:

GPP_B14, GPP_B20, GPP_B23

‧

GPP_C[23:22]

‧

GPP_D[4:0]

‧

GPP_E[8:0]

‧

GPP_I[3:0]

‧

GPP_G[7:0] (support SMI# only).

‧

The voltage of all GPIO pads in each GPP group is determined by the voltage supplied to the group (either 3.3V or 1.8V),
except for GPP_I and GPD group, (which are 3.3V only), and GPP_J group (which is 1.8V only).

All GPIOs have programmable internal pull-up/pull-down resistors which are off by default.
The internal pull-up/pull-down for each GPIO can be enabled by BIOS programming.

Deciphered Date

Deciphered Date

Deciphered Date

10K_0201_5%

D

+3VS

1.0

1.0

1.0

A

B

C

D

E

GPIO Group Voltage

LPC: 3.3V

GPPA

GPPG

GPPH
GPPK

GPPI

GPPJ

GPD

1 2

RH188 0_0402_5%@

4.7U_0402_6.3V6M

1

CH35

2

E

eSPI: 1.8V

1.8V for SOC_DMIC

3.3V for IR_DMIC

+1.05VALW

5.95A

1U_0201_6.3V6M

CH28

6.6A

1

2

22U_0603_6.3V6M

CH30

12

1 1

close to VCCPRIM balls

close to VCCPRIM balls

+3VS

1 2

RC50 0_0603_ 5%@

1U_0201_6.3V6M

CH31

1

2

PLACE 3-5MM FROM PACKAGE EDGE

+1.05V_VCCDSW

1U_0201_6.3V6M

CH34

+1.05VALW

1

@

2

RH122 0_0603_5%@

RH125 0_0603_5%@

RH130 0_0603_5%@

RH134 0_0603_5%@

RH139 0_0603_5%

RH141 0_0603_5%

+1.05VALW +1.05V_FUSE

1 2

RH116 0_0603_5%

2 2

3 3

4 4

1 2

RH117 0_0603_5%@

1 2

RH118 0_0603_5%@

1 2

RH124 0_0603_5%

1 2

RH129 0_0603_5%@

1P_0402_50V8

1

CH43

2

@

1 2

RH135 0_0603_5%@

1 2

RH140 0_0603_5%@

A

+1.05V_CNV_HVLDO

+1.05V_VCCUSB

0.1U_0402_10V6K

1

2

+1.05V_VCCCLPL LEBB

1

2

+1.05V_VCCAZPLL

22U_0603_6.3V6M

12

+1.05V_VCCAMPHYPLL

22U_0603_6.3V6M

12

@

+1.05V_XTAL

22U_0603_6.3V6M

12

@

CH36

@

0.1U_0201_10V6K
CH38

22U_0603_6.3V6M

CH44

CH54

12

@

1U_0201_6.3V6M

CH48

1

CH49

2

CH53

1 2

1 2

1 2

1 2

1 2

1 2

+1.8VS_3VS_PGPPA

+1.05V_VCCAZPLL

+1.05V_SRC

+1.05V_OCPLL1

+1.05V_OC

+1.05V_BCLKPL L2

+1.05V_FHV1

+1.05V_FHV0

B

+1.05V_VCCUSB

+1.05V_VCCCLPL LEBB

+1.05V_VCCDSW

+1.05V_VCCAMPHYPLL

+1.05V_XTAL

+1.05V_SRC

+1.05V_OC

+1.05V_BCLKPL L2

1U_0201_6.3V6M

1

CH39

2

0.1U_0402_10V6K

1

CH45

2

@

1U_0201_6.3V6M

1

CH47

2

HSIO for DMIU/USB3.1/PCIE=4162mA

+1.05VALW

+1.05V_CNV_HVLDO

+1.05V_OCPLL1

+3VALW

+1.8VALW

+1.05V_FUSE

+1.05V_VCCDSW

1 2

RH136 0_0805_5%@

+1.05VALW

5.95A

6.6A

0.0012A

0.2A

0.42A

0.109A

0.015A

0.213A

0.00428A

0.169A

0.0198A

0.0085A

0.021A

+VCCRTCEXT

+1.8V_PHVLDO

Internal LDO

+3VALW

Deciphered Date

Deciphered Date

Deciphered Date

+3V_PHVC

+VCCRTCEXT

+3V_USB2

+3V_SPI

+3VALW

+PCH_DSW

RH115

RH120 0_0603_5%@

RH131 0.01_0402_1%

RH133 0_0603_5%

RH137 0_0603_5%@

D

+3VL_RTC

+3V_PHVLDO

+3V_1.8V_PGPPHK

+3V_1.8V_PGPPA

+3VALW

+1.8V_PRIM

+1.8V_PHVLDO

@

1 2

0_0603_5%

+1.05V_FHV1
+1.05V_FHV0

+1.24V_VCCLDOSR AM_IN

+1.24V_PRIM_DPHY

+1.24V_PRIM_MAR

TH11TP@
TH12TP@

Short pins AJ22,AJ23,AK22,AK23 together
at surface layer from PDG Rev0.71

+1.24V_VCCLDOSR AM_IN + 1.24V_PRIM_DPHY

RH119 0_0402_5%@

RH174 for 571391_CFL_H_PDG_Rev0p71.pdf

1 2

@

1 2

1 2

1 2

0.1U_0201_10V6K

1

2

CNP-H

8 OF 13

RH123 0_0603_5%@

RH126 0_0603_5%@

RH127 0_0603_5%@

RH128 0_0603_5%@

CH46

AW9

VCCPRIM_3P32

DCPRTC1
DCPRTC2

VCCPRIM_3P35

VCCSPI

VCCRTC1
VCCRTC2

VCCPGPPG_3P3

VCCPRIM_3P33
VCCPRIM_3P34

VCCPGPPHK1
VCCPGPPHK2

VCCPGPPEF1
VCCPGPPEF2

VCCPGPPD
VCCPGPPBC1
VCCPGPPBC2

VCCPGPPA

VCCPRIM_3P31

VCCDSW_3P31
VCCDSW_3P32

VCCHDA
VCCPRIM_1P83
VCCPRIM_1P84
VCCPRIM_1P85
VCCPRIM_1P86
VCCPRIM_1P87

VCCPRIM_1P81
VCCPRIM_1P82

VCCPRIM_1P0520
VCCPRIM_1P0519

VCCPRIM_1P241
VCCPRIM_1P242

VCCDPHY_1P241
VCCDPHY_1P242
VCCDPHY_1P243

VCCMPHY_SENSE

VSSMPHY_SENSE

1 2

1 2

1 2

1 2

+3VL_RTC +R TCVCC

1

2

2020/7/31 2020/7/31

2020/7/31 2020/7/31

2020/7/31 2020/7/31

BF47
BG47

V23

AN44

BC49
BD49

AN21
AY8
BB7

AC35
AC36
AE35
AE36

AN24
AN26
AP26

AN32

AT44
BE48
BE49

BB14
AG19
AG20
AN15
AR15
BB11

AF19
AF20

AG31
AF31
AK22
AK23

AJ22
AJ23
BG5

K47
K46

Rev1.0

+3V_PHVC

+3V_USB2

+3V_SPI

+3V_PHVLDO

1U_0201_6.3V6M

1

2

1 2

RH138 0_0402_5%@

1U_0201_6.3V6M

CH52

0.182A

0.095A

0.042A

0.195A

0.97A

0.262A

0.174A

0.14A

0.334A

0.101A

0.106A

0.113A

0.00767A

0.766A

0.882A

0.193A

0.0895A

VCCMPHY_SENSE
VSSMPHY_SENSE

0.1U_0402_10V6K

1

CH42

CH41

2

@

W=20mils

Compal Secret Data

Compal Secret Data

Compal Secret Data

UH1H

AA22

VCCPRIM_1P051

AA23

VCCPRIM_1P052

AB20

VCCPRIM_1P053

AB22

VCCPRIM_1P054

AB23

VCCPRIM_1P055

AB27

VCCPRIM_1P056

AB28

VCCPRIM_1P057

AB30

VCCPRIM_1P058

AD20

VCCPRIM_1P059

AD23

VCCPRIM_1P0510

AD27

VCCPRIM_1P0511

AD28

VCCPRIM_1P0512

AD30

VCCPRIM_1P0513

AF23

VCCPRIM_1P0516

AF27

VCCPRIM_1P0517

AF30

VCCPRIM_1P0518

U26

VCCPRIM_1P0523

U29

VCCPRIM_1P0524

V25

VCCPRIM_1P0525

V27

VCCPRIM_1P0526

V28

VCCPRIM_1P0527

V30

VCCPRIM_1P0528

V31

VCCPRIM_1P0529

AD31

VCCPRIM_1P0514

AE17

VCCPRIM_1P0515

W22

VCCDUSB_1P051

W23

VCCDUSB_1P052

BG45

VCCDSW_1P051

BG46

VCCDSW_1P052

W31

VCCPRIM_MPHY_1P05

D1

VCCPRIM_1P0521

E1

VCCPRIM_1P0522

C49

VCCAMPHYPLL_1P051

D49

VCCAMPHYPLL_1P052

E49

VCCAMPHYPLL_1P053

P2

VCCA_XTAL_1P051

P3

VCCA_XTAL_1P052

W19

VCCA_SRC_1P051

W20

VCCA_SRC_1P052

C1

VCCAPLL_1P054

C2

VCCAPLL_1P055

V19

VCCA_BCLK_1P05

B1

VCCAPLL_1P051

B2

VCCAPLL_1P052

B3

VCCAPLL_1P053

CML-H_BGA874

@

+3VALW

+1.8V_PRIM

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

+3VALW

+3V_1.8V_PGPPD

+3V_1.8V_HDA

VCCPHVLDO_1P8
(External VRM mode RH172 unmount)

+1.8V_PRIM

1 2

+3V_1.8V_PGPPHK

RH121 0_0402_5%

0.1U_0402_10V6K

1

CH37

2

@

+3VALW

0.1U_0402_10V6K

1

CH40

2

@

+3V_1.8V_PGPPD

RH132 0_0402_5%@

+3V_1.8V_PGPPA

+3V_1.8V_HDA

1

2

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet

GPPB

+VCCRTCEXT

0.1U_0402_10V6K

1

2

+1.8V_PRIM

4.7U_0402_6.3V6M

1

1

CH32

@

2

2

Close to BB11

@

1 2

1 2

1 2

RH187 0_0603_5%@

1P_0402_50V8

1P_0402_50V8

1

CH51

CH50

2

@

@

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PCH(7/8)Power

PCH(7/8)Power

PCH(7/8)Power

LA-J561P

LA-J561P

LA-J561P

GPPC

GPPD

GPPE

GPPF

CH29

@

+3VALW

1U_0201_6.3V6M

CH33

For DDX03 R02

+1.24V_PRIM_MAR

+1.8V_PRIM

*

3.3V

3.3V

3.3V

3.3V

3.3V Only

1.8V Only

3.3V Only

+PCH_DSW

of

20 100Wednesday, February 26, 2 020

20 100Wednesday, February 26, 2 020

20 100Wednesday, February 26, 2 020

*

1.0

1.0

1.0

A

B

C

D

E

CNP-H

CNP-H

UH1I

A2

VSS

1 1

2 2

3 3

A28

A33
A37

A45
A46
A47
A48

AA19
AA20
AA25
AA27
AA28
AA30
AA31
AA49

AA5
AB19
AB25
AB31
AC12
AC17
AC33
AC38

AC4

AC46

AD1

AD19

AD2
AD22
AD25
AD49
AE12
AE33
AE38

AE4
AE46
AF22
AF25
AF28

AG1
AG22
AG23
AG25
AG27
AG28
AG30
AG49
AH12
AH17
AH33
AH38

AJ19
AJ20
AJ25
AJ27
AJ28
AJ30

AJ31
AK19
AK20
AK25
AK27
AK28
AK30
AK31

AK4

AK46

A3

A4

A5
A8

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

9 OF 13

VSS

CML-H_BG A874

@

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

Rev1.0

AL12
AL17
AL21
AL24
AL26
AL29
AL33
AL38
AM1
AM18
AM32
AM49
AN12
AN16
AN34
AN38
AP4
AP46
AR12
AR16
AR34
AR38
AT1
AT16
AT18
AT21
AT24
AT26
AT29
AT32
AT34
AT45
AV11
AV39
AW10
AW4
AW40
AW46
B47
B48
B49
BA12
BA14
BA44
BA5
BA6
BB41
BB43
BB9
BC10
BC13
BC15
BC19
BC24
BC26
BC31
BC35
BC40
BC45
BC8
BD43
BE44
BF1
BF2
BF3
BF48
BF49
BG17
BG2
BG22
BG25
BG28

BG3
BG33
BG37

BG4
BG48

C12
C25
C30

C48

D12
D16
D17
D30
D33

E10
E13
E15
E17
E19
E22
E24
E26
E31
E33
E35
E40
E42

F41
F43
F47

G44

K11

K39
M16
M18
M21

C4

C5

D8

E8

G6

H8
J10
J26
J29

J4
J40
J46
J47
J48

J9

UH1L

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

12 OF 13

VSS

CML-H_BG A874

@

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

Rev1.0

M24
M32
M34
M49
M5
N12
N16
N34
N35
N37
N38
P26
P29
P4
P46
R12
R16
R26
R29
R3
R34
R38
R4
T17
T18
T32
T4
T49
T5
T7
U12
U15
U17
U21
U24
U33
U38
V20
V22
V4
V46
W25
W27
W28
W30
Y10
Y12
Y17
Y33
Y38
Y9

CNP-H

UH1J

RSVD7
RSVD8
RSVD6
RSVD5

RSVD3
RSVD4

RSVD2
RSVD1

PREQ#
PRDY#

CPU_TRST#

TRIGGER_OUT

TRIGGER_IN

10 OF 13

CML-H_BG A874

@

Rev1.0

Y14
Y15
U37
U35

N32
R32

AH15
AH14

XDP_PRE Q#

AL2

XDP_PRD Y#

AM5
AM4

PCH_TRIGO UT PCH_TRIGOU T_R

AK3

CPU_TRIGO UT_R

AK2

TH13T P@
TH14T P@
TH15T P@
TH16T P@

TH17T P@
TH18T P@

TH19T P@
TH20T P@

1 2

RH142 30_040 2_5%

XDP_PRE Q# <10 >
XDP_PRD Y# < 10>
PCH_XDP _TRST# <10>

PCH_TRIGO UT_R <1 3>
CPU_TRIGO UT_R <1 3>

4 4

Security Classification

Security Classification

Security Classification

2020/7/31 2020/7/31

2020/7/31 2020/7/31

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2020/7/31 2020/7/31

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PCH(8/8)GND/RSVD

PCH(8/8)GND/RSVD

PCH(8/8)GND/RSVD

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Custom

Custom

Custom

LA-J561P

LA-J561P

LA-J561P

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

21 10 0Wednesday, February 26, 2020

21 10 0Wednesday, February 26, 2020

21 10 0Wednesday, February 26, 2020

E

1.0

1.0

1.0

5

4

3

2

1

CHANNEL-A

BOT

Interleaved Memory

TOP: JDIMM1 CONN Non-ECC DIMM

D D

12

RD1

@

0_0402_5%

RD6

@

0_0402_5%

1 2

12

RD2

@

0_0402_5%

RD3

@

0_0402_5%

1 2

PLACE ALL THE B ELOW RESISTORS CLOSE TO SODI MM

SPD ADDRESS FOR CHANNEL A :
WRITE ADDRESS: 0XA0
READ ADDRESS: 0XA1
SA0 = 0; SA1 = 0; SA2 = 0.
DDR4 POR OPERATING SPEED: 1867 MT/S
STRETCH GOAL IS 2133 MT/S

C C

Layout Note:
Place near JDIMM1.257,259

+2.5V +0.6VS

10U_0402_6.3V6M

CD4

1

1

2

2

Layout Note:
PLACE THE CAP near JDIMM1. 164

B B

+0.6V_DDR_VREFCA

2

CD11

0.1U_0201_10V6K

1

10uF*2
1uF*2

1U_0201_6.3V6M

1U_0201_6.3V6M

10U_0402_6.3V6M

CD5

@

1

2

CD6

1

2

@

2

CD12

2.2U_0402_6.3V6M

1

@

CD7

2.2uF*1

0.1uF*1

+3VS+3VS+3VS

12

RD5

@

0_0402_5%

SA2_CHA_DIM1SA1_CHA_DIM1SA0_CHA_DIM1

RD4

@

0_0402_5%

1 2

Layout Note:
Place near JDIMM1.258

10uF*1
1uF*2

1U_0201_6.3V6M

10U_0402_6.3V6M

1

2

1U_0201_6.3V6M

CD9

CD8

CD10

1

1

2

2

+3VS

0.1U_0201_10V6K

2.2U_0402_6.3V6M

+0.6V_DDR_VREFCA

2

2

CD1

CD2

1

1

PLACE NEAR TO P IN

Part Number:SP0 7001FYH0
Part Value:S SO CKET FOX_AS0A826-H4RB-7H 260 P DDR4

+1.2V

DDR_A_D[0..15]<7>

DDR_A_D[16..31]<7>

DDR_A_D[32..47]<7>

DDR_A_D[48..63]<7>

JDIMM1B

REVERSE

111

VDD1

112

VDD2

117

VDD3

118

VDD4

123

VDD5

124

VDD6

129

VDD7

130

VDD8

135

VDD9

136

VDD10

255

VDDSPD

164

VREFCA

1

VSS

2

VSS

5

VSS

6

VSS

9

VSS

10

VSS

14

VSS

15

VSS

18

VSS

19

VSS

22

VSS

23

VSS

26

VSS

27

VSS

30

VSS

31

VSS

35

VSS

36

VSS

39

VSS

40

VSS

43

VSS

44

VSS

47

VSS

48

VSS

51

VSS

52

VSS

56

VSS

57

VSS

60

VSS

61

VSS

64

VSS

65

VSS

68

VSS

69

VSS

72

VSS

73

VSS

77

VSS

78

VSS

81

VSS

82

VSS

85

VSS

86

VSS

89

VSS

90

VSS

93

VSS

94

VSS

98

VSS

262

GND

LOTES_ADDR0206-P001A

ME@

VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19

VPP1
VPP2

GND

VTT

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

REVERSE TYPE

141
142
147
148
153
154
159
160
163

258

257
259

99
102
103
106
107
167
168
171
172
175
176
180
181
184
185
188
189
192
193
196
197
201
202
205
206
209
210
213
214
217
218
222
223
226
227
230
231
234
235
238
239
243
244
247
248
251
252

261

+1.2V

+0.6VS

+2.5V

RD7 240_0402_1%

+1.2V

DDR_DRAMRST#<18,23>

100P_0402_50V8J

Near JDIMM1

ESD@

CD3

DDR_A_CLK0<7>
DDR_A_CLK#0<7>
DDR_A_CLK1<7>
DDR_A_CLK#1<7>

DDR_A_CKE0<7>
DDR_A_CKE1<7>

DDR_A_CS#0<7>
DDR_A_CS#1<7>

DDR_A_ODT0<7>
DDR_A_ODT1<7>

DDR_A_BG0<7>
DDR_A_BG1<7>
DDR_A_BA0<7>
DDR_A_BA1<7>

DDR_A_MA0<7>
DDR_A_MA1<7>
DDR_A_MA2<7>
DDR_A_MA3<7>
DDR_A_MA4<7>
DDR_A_MA5<7>
DDR_A_MA6<7>
DDR_A_MA7<7>
DDR_A_MA8<7>
DDR_A_MA9<7>
DDR_A_MA10<7>
DDR_A_MA11<7>
DDR_A_MA12<7>
DDR_A_MA13<7>
DDR_A_MA14_WE#<7>
DDR_A_MA15_CAS#<7>
DDR_A_MA16_RAS#<7>

DDR_A_ACT#<7>

DDR_A_PAR<7>
DDR_A_ALERT#<7>

12

1

2

For ECC DIMM

+1.2V

+1.2V

(4 mm)

PCH_SMBDATA<18,23>
PCH_SMBCLK<18,23>

DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CLK1
DDR_A_CLK#1

DDR_A_CKE0
DDR_A_CKE1

DDR_A_CS#0
DDR_A_CS#1

DDR_A_ODT0
DDR_A_ODT1

DDR_A_BG0
DDR_A_BG1
DDR_A_BA0
DDR_A_BA1

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14_WE#
DDR_A_MA15_CAS#
DDR_A_MA16_RAS#

DDR_A_ACT#

DDR_A_PAR
DDR_A_ALERT#
DIMM1_CHA_EVENT#

PCH_SMBDATA
PCH_SMBCLK

SA2_CHA_DIM1
SA1_CHA_DIM1
SA0_CHA_DIM1

JDIMM1A

137

CK0(T)

139

CK0#(C)

138

CK1(T)

140

CK1#(C)

109

CKE0

110

CKE1

149

S0#

157

S1#

162

S2#/C0

165

S3#/C1

155

ODT0

161

ODT1

115

BG0

113

BG1

150

BA0

145

BA1

144

A0

133

A1

132

A2

131

A3

128

A4

126

A5

127

A6

122

A7

125

A8

121

A9

146

A10_AP

120

A11

119

A12

158

A13

151

A14_WE#

156

A15_CAS#

152

A16_RAS#

114

ACT#

143

PARITY

116

ALERT#

134

EVENT#

108

RESET#

254

SDA

253

SCL

166

SA2

260

SA1

256

SA0

92

CB0_NC

91

CB1_NC

101

CB2_NC

105

CB3_NC

88

CB4_NC

87

CB5_NC

100

CB6_NC

104

CB7_NC

97

DQS8(T)

95

DQS8#(C)

12

DM0#/DBI0#

33

DM1#/DBI1#

54

DM2#/DBI2#

75

DM3#/DBI3#

178

DM4#/DBI4#

199

DM5#/DBI5#

220

DM6#/DBI6#

241

DM7#/DBI7#

96

DM8#/DBI8#

LOTES_ADDR0206-P001A

ME@

REVERSE

DQS0(T)

DQS0#(C)

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

DQS1(T)

DQS1#(C)

DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23

DQS2(T)

DQS2#(C)

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQS3(T)

DQS3#(C)

DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39

DQS4(T)

DQS4#(C)

DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47

DQS5(T)

DQS5#(C)

DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55

DQS6(T)

DQS6#(C)

DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

DQS7(T)

DQS7#(C)

DDR_A_D5

8

DQ0

DDR_A_D0

7

DQ1

DDR_A_D2

20

DQ2

DDR_A_D3

21

DQ3

DDR_A_D1

4

DQ4

DDR_A_D4

3

DQ5

DDR_A_D6

16

DQ6

DDR_A_D7

17

DQ7

DDR_A_DQS0

13

DDR_A_DQS#0

11

DDR_A_D8

28

DQ8

DDR_A_D12

29

DQ9

DDR_A_D14

41

DDR_A_D11

42

DDR_A_D9

24

DDR_A_D13

25

DDR_A_D10

38

DDR_A_D15

37

DDR_A_DQS1

34

DDR_A_DQS#1

32

DDR_A_D17

50

DDR_A_D20

49

DDR_A_D23

62

DDR_A_D18

63

DDR_A_D16

46

DDR_A_D21

45

DDR_A_D19

58

DDR_A_D22

59

DDR_A_DQS2

55

DDR_A_DQS#2

53

DDR_A_D25

70

DDR_A_D28

71

DDR_A_D30

83

DDR_A_D31

84

DDR_A_D24

66

DDR_A_D29

67

DDR_A_D27

79

DDR_A_D26

80

DDR_A_DQS3

76

DDR_A_DQS#3

74

DDR_A_D32

174

DDR_A_D37

173

DDR_A_D35

187

DDR_A_D39

186

DDR_A_D36

170

DDR_A_D33

169

DDR_A_D34

183

DDR_A_D38

182

DDR_A_DQS4

179

DDR_A_DQS#4

177

DDR_A_D44

195

DDR_A_D45

194

DDR_A_D42

207

DDR_A_D43

208

DDR_A_D41

191

DDR_A_D40

190

DDR_A_D46

203

DDR_A_D47

204

DDR_A_DQS5

200

DDR_A_DQS#5

198

DDR_A_D48

216

DDR_A_D50

215

DDR_A_D53

228

DDR_A_D55

229

DDR_A_D52

211

DDR_A_D49

212

DDR_A_D54

224

DDR_A_D51

225

DDR_A_DQS6

221

DDR_A_DQS#6

219

DDR_A_D60

237

DDR_A_D57

236

DDR_A_D62

249

DDR_A_D58

250

DDR_A_D56

232

DDR_A_D61

233

DDR_A_D59

245

DDR_A_D63

246

DDR_A_DQS7

242

DDR_A_DQS#7

240

DDR_A_DQS0 <7>

DDR_A_DQS#0 <7>

DDR_A_DQS1 <7>

DDR_A_DQS#1 <7>

DDR_A_DQS2 <7>

DDR_A_DQS#2 <7>

DDR_A_DQS3 <7>

DDR_A_DQS#3 <7>

DDR_A_DQS4 <7>

DDR_A_DQS#4 <7>

DDR_A_DQS5 <7>

DDR_A_DQS#5 <7>

DDR_A_DQS6 <7>

DDR_A_DQS#6 <7>

DDR_A_DQS7 <7>

DDR_A_DQS#7 <7>

DIMM Side

+0.6V_DDR_VREFCA

Layout Note:
Place near JDIMM1

10uF*6
1uF*8
330uF*1

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

CD16

CD17

1

1

1

2

2

2

A A

10U_0402_6.3V6M

CD18

CD19

1

1

2

2

5

10U_0402_6.3V6M

10U_0402_6.3V6M

CD20

CD21

1

1

2

2

+1.2V+1.2V

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

10U_0402_6.3V6M

CD22

CD23

1

2

@

@

1U_0201_6.3V6M

1

1

1

1

CD24

CD25

2

2

2

1

CD26

CD27

2

2

4

1U_0201_6.3V6M

1

1

CD28

CD29

CD30

2

2

+1.2V

1U_0201_6.3V6M

1

2

1

+

CD31

CD32
330U_D3_2.5VY_R6M

SGA00006A00

2

@

2

@

CD13

0.1U_0402_10V6K

1

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

3

RD8
1K_0402_1%

1 2

2

RD10
1K_0402_1%

1 2

2020/7/31 2020/7/31

2020/7/31 2020/7/31

2020/7/31 2020/7/31

CD14

0.1U_0201_10V6K

1

Compal Secret Data

Compal Secret Data

Compal Secret Data

1 2

RD9

2_0402_1%

Deciphered Date

Deciphered Date

Deciphered Date

2

CPU Side

+0.6V_VREFCA

VREF traces sho uld be at least 20 mils
wide with 20 mi ls spacing to other

1

signals

CD15

0.022U_0402_25V7K

2

RD11

24.9_0402_1%

1 2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

DDRIV_CHA: DIMM0

DDRIV_CHA: DIMM0

DDRIV_CHA: DIMM0

LA-J561P

LA-J561P

LA-J561P

1

22 100Wednesday, February 26, 2020

22 100Wednesday, February 26, 2020

22 100Wednesday, February 26, 2020

1.0

1.0

1.0

5

4

3

2

1

CHANNEL-B

TOP: JDIMM3 CONN

D D

@

@

12

1 2

RD12

0_0402_5%

RD16
0_0402_5%

Non-ECC DIMM

RD13

@

0_0402_5%

1 2

12

RD17

@

0_0402_5%

+3VS+3 VS+3VS

@

12

@

1 2

RD14

0_0402_5%

SA2_CHB_DIM3SA1_CHB_ DIM3SA0_CHB_DIM3

RD15
0_0402_5%

PLACE ALL THE BELOW RESISTORS CLOSE TO SODIMM

SPD ADDRESS FOR CHANNEL B :
WRITE ADDRESS: 0XA4
READ ADDRESS: 0XA3
SA0 = 0; SA1 = 1; SA2 = 0.
DDR4 POR OPERATING SPEED: 1867 MT/S
STRETCH GOAL IS 2133 MT/S

C C

Layout Note:
Place near JDIMM3.257,259

10uF*2

10U_0402_6.3V6M

1

1

CD36

2

2

Layout Note:
PLACE THE CAP WITHIN 200 MILS
FROM THE JDIMM3

B B

+0.6V_DDRB_VRE FCA

2

CD43

0.1U_0201_ 10V6K

1

Layout Note:
Place near JDIMM3

1

A A

2

1uF*2

10U_0402_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1

1

CD37

CD38

CD39

2

2

@

10U_0402_6.3V6M

CD48

1

2

10U_0402_6.3V6M

CD49

@

2.2uF*1

0.1uF*1

@

2

CD44

2.2U_0402_ 6.3V6M

1

10U_0402_6.3V6M

CD50

1

1

2

2

10uF*6
1uF*8

10U_0402_6.3V6M

10U_0402_6.3V6M

CD51

CD52

1

2

Layout Note:
Place near JDIMM3.258

+0.6VS+2.5V

1

2

10U_0402_6.3V6M

10U_0402_6.3V6M

CD53

CD54

1

1

1

2

2

2

@

10uF*1
1uF*2

10U_0402_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1

1

CD40

CD42

CD41

2

2

+1.2V+1.2V

1U_0201_6.3V6M

10U_0402_6.3V6M

CD55

@

1U_0201_6.3V6M

1

1

CD57

CD58

2

2

Interleaved Memory

+3VS

0.1U_0201_10V6K

2

CD34

1

PLACE NEAR TO PIN

1U_0201_6.3V6M

1U_0201_6.3V6M

1

1

CD59

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

1

1

CD60

CD61

2

2

+1.2V

2.2U_0402_6.3V6M

+0.6V_DDRB_VRE FCA

2

CD33

1

1U_0201_6.3V6M

1

CD62

CD63

2

DDR_B_D[0..15 ]<8>

DDR_B_D[16 ..31]<8>

DDR_B_D[32 ..47]<8>

DDR_B_D[48 ..63]<8>

111
112
117
118
123
124
129
130
135
136

255

164

10
14
15
18
19
22
23
26
27
30
31
35
36
39
40
43
44
47
48
51
52
56
57
60
61
64
65
68
69
72
73
77
78
81
82
85
86
89
90
93
94
98

262

Part Number:SP07001CEA0

art Value:S SOCKET FOX_AS0A826-H4SB-7H 260P DDR4

P

1U_0201_6.3V6M

1

CD64

2

JDIMM2B

STD

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10

VDDSPD

VREFCA

1

VSS

2

VSS

5

VSS

6

VSS

9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

GND

FOX_AS0A826-H4SB-7H

ME@

VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19

VPP1
VPP2

GND

141
142
147
148
153
154
159
160
163

258

VTT

257
259

99

VSS

102

VSS

103

VSS

106

VSS

107

VSS

167

VSS

168

VSS

171

VSS

172

VSS

175

VSS

176

VSS

180

VSS

181

VSS

184

VSS

185

VSS

188

VSS

189

VSS

192

VSS

193

VSS

196

VSS

197

VSS

201

VSS

202

VSS

205

VSS

206

VSS

209

VSS

210

VSS

213

VSS

214

VSS

217

VSS

218

VSS

222

VSS

223

VSS

226

VSS

227

VSS

230

VSS

231

VSS

234

VSS

235

VSS

238

VSS

239

VSS

243

VSS

244

VSS

247

VSS

248

VSS

251

VSS

252

VSS

261

+1.2V

+0.6VS

+2.5V

+1.2V

DDR_DRAMRST #<18 ,22>

Near JDIMM3

RD18 240_0402_1%

CD35

100P_0402_ 50V8J

ESD@

+1.2V

+1.2V

2

CD45

@

1

2

1

0.1U_0402_ 10V6K

CD46

0.1U_0201_ 10V6K

1 2

1 2

RD19
1K_0402_1%

RD21
1K_0402_1%

DDR_B_CLK 0<8>
DDR_B_CLK #0< 8>

DDR_B_CLK #1< 8>

DDR_B_CKE0<8>
DDR_B_CKE1<8>

DDR_B_CS# 0<8>
DDR_B_CS# 1<8>

DDR_B_ODT 0<8>
DDR_B_ODT 1<8>

DDR_B_BG0<8>
DDR_B_BG1<8>
DDR_B_BA0<8>
DDR_B_BA1<8>

DDR_B_MA0<8>
DDR_B_MA1<8>
DDR_B_MA2<8>
DDR_B_MA3<8>
DDR_B_MA4<8>
DDR_B_MA5<8>
DDR_B_MA6<8>
DDR_B_MA7<8>
DDR_B_MA8<8>
DDR_B_MA9<8>
DDR_B_MA10<8>
DDR_B_MA11<8>
DDR_B_MA12<8>
DDR_B_MA13<8>
DDR_B_MA14_ WE#<8>
DDR_B_MA15_ CAS#< 8>
DDR_B_MA16_ RAS#< 8>

DDR_B_ACT#<8>

DDR_B_PAR<8>

DDR_B_ALERT #<8>

12

1

PCH_SMBDATA<18,22>
PCH_SMBCLK<18,22 >

2

DIMM Side

+0.6V_DDRB_VRE FCA

STD

DDR_B_CLK 1<8>

For ECC DIMM

1 2

RD20

2_0402_1%

2

CD47

0.1U_0201_ 10V6K

1

(4 mm)BOT

DDR_B_CLK 0
DDR_B_CLK #0
DDR_B_CLK 1
DDR_B_CLK #1

DDR_B_CKE0
DDR_B_CKE1

DDR_B_CS# 0
DDR_B_CS# 1

DDR_B_ODT 0
DDR_B_ODT 1

DDR_B_BG0
DDR_B_BG1
DDR_B_BA0
DDR_B_BA1

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14_ WE#
DDR_B_MA15_ CAS#
DDR_B_MA16_ RAS#

DDR_B_ACT#

DDR_B_PAR
DDR_B_ALERT #

DIMM3_CHB_EVENT #

PCH_SMBDATA
PCH_SMBCLK

SA2_CHB_DIM3
SA1_CHB_DIM3
SA0_CHB_DIM3

CPU Side

1

CD56

0.022U_040 2_25V7K

2

RD22

24.9_0402_1 %

1 2

JDIMM2A

STD

137

CK0(T)

139

CK0#(C)

138

CK1(T)

140

CK1#(C)

109

CKE0

110

CKE1

149

S0#

157

S1#

162

S2#/C0

165

S3#/C1

155

ODT0

161

ODT1

115

BG0

113

BG1

150

BA0

145

BA1

144

A0

133

A1

132

A2

131

A3

128

A4

126

A5

127

A6

122

A7

125

A8

121

A9

146

A10_AP

120

A11

119

A12

158

A13

151

A14_WE#

156

A15_CAS#

152

A16_RAS#

114

ACT#

143

PARITY

116

ALERT#

134

EVENT#

108

RESET#

254

SDA

253

SCL

166

SA2

260

SA1

256

SA0

92

CB0_NC

91

CB1_NC

101

CB2_NC

105

CB3_NC

88

CB4_NC

87

CB5_NC

100

CB6_NC

104

CB7_NC

97

DQS8(T)

95

DQS8#(C)

12

DM0#/DBI0#

33

DM1#/DBI1#

54

DM2#/DBI2#

75

DM3#/DBI3#

178

DM4#/DBI4#

199

DM5#/DBI5#

220

DM6#/DBI6#

241

DM7#/DBI7#

96

DM8#/DBI8#

FOX_AS0A826-H4SB-7H

ME@

+0.6V_B_VREFDQ

VREF traces should be at least 20 mils
wide with 20 mils spacing to other
signals

DQS0(T)

DQS0#(C)

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

DQS1(T)

DQS1#(C)

DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23

DQS2(T)

DQS2#(C)

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQS3(T)

DQS3#(C)

DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39

DQS4(T)

DQS4#(C)

DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47

DQS5(T)

DQS5#(C)

DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55

DQS6(T)

DQS6#(C)

DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

DQS7(T)

DQS7#(C)

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQ8
DQ9

8
7
20
21
4
3
16
17
13
11

28
29
41
42
24
25
38
37
34
32

50
49
62
63
46
45
58
59
55
53

70
71
83
84
66
67
79
80
76
74

174
173
187
186
170
169
183
182
179
177

195
194
207
208
191
190
203
204
200
198

216
215
228
229
211
212
224
225
221
219

237
236
249
250
232
233
245
246
242
240

DDR_B_D0
DDR_B_D1
DDR_B_D7
DDR_B_D3
DDR_B_D5
DDR_B_D4
DDR_B_D2
DDR_B_D6
DDR_B_DQS0
DDR_B_DQS# 0

DDR_B_D9
DDR_B_D14
DDR_B_D13
DDR_B_D15
DDR_B_D8
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_DQS1
DDR_B_DQS# 1

DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D21
DDR_B_D16
DDR_B_D22
DDR_B_D23
DDR_B_D20
DDR_B_DQS2
DDR_B_DQS# 2

DDR_B_D25
DDR_B_D30
DDR_B_D29
DDR_B_D24
DDR_B_D28
DDR_B_D27
DDR_B_D31
DDR_B_D26
DDR_B_DQS3
DDR_B_DQS# 3

DDR_B_D39
DDR_B_D35
DDR_B_D36
DDR_B_D32
DDR_B_D38
DDR_B_D34
DDR_B_D37
DDR_B_D33
DDR_B_DQS4
DDR_B_DQS# 4

DDR_B_D41
DDR_B_D45
DDR_B_D46
DDR_B_D43
DDR_B_D40
DDR_B_D44
DDR_B_D42
DDR_B_D47
DDR_B_DQS5
DDR_B_DQS# 5

DDR_B_D51
DDR_B_D52
DDR_B_D55
DDR_B_D53
DDR_B_D48
DDR_B_D54
DDR_B_D49
DDR_B_D50
DDR_B_DQS6
DDR_B_DQS# 6

DDR_B_D56
DDR_B_D57
DDR_B_D60
DDR_B_D63
DDR_B_D61
DDR_B_D59
DDR_B_D58
DDR_B_D62
DDR_B_DQS7
DDR_B_DQS# 7

DDR_B_DQS0 <8>

DDR_B_DQS# 0 < 8>

DDR_B_DQS1 <8>

DDR_B_DQS# 1 < 8>

DDR_B_DQS2 <8>

DDR_B_DQS# 2 < 8>

DDR_B_DQS3 <8>

DDR_B_DQS# 3 < 8>

DDR_B_DQS4 <8>

DDR_B_DQS# 4 < 8>

DDR_B_DQS5 <8>

DDR_B_DQS# 5 < 8>

DDR_B_DQS6 <8>

DDR_B_DQS# 6 < 8>

DDR_B_DQS7 <8>

DDR_B_DQS# 7 < 8>

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2020/7/31 2020/7/31

2020/7/31 2020/7/31

2020/7/31 2020/7/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

DDRIV_CHB: DIMM0

DDRIV_CHB: DIMM0

DDRIV_CHB: DIMM0

LA-J561P

LA-J561P

LA-J561P

1

1.0

1.0

23 100Wednesday, February 26, 2 020

23 100Wednesday, February 26, 2 020

23 100Wednesday, February 26, 2 020

1.0

A

B

C

D

E

GC OFF 1.0 GPU Power ON/OFF

1 2

RG1
10K_02 01_5%

DGPU_HOL D_RST#<16>

1 1

2 2

3 3

PCI_RS T#<16,48,4 9,50,57 >

DGPU_HOL D_RST#

NL17SZ0 8DFT2G _SC70 -5

+1V8_AO N

5

1

IN B

VCC

4

1 2

OUT Y

2

IN A

GND

UG1

3

RG2 0_0201 _5%@

12

RG3
100K_0 201_5%

+1V8_MAI N

1 2

GPU_CLK REQ4#<15 >

QG1

MESS138 W-G_SO T323-3

123

D

RG4
10K_02 01_5%

G

S

DGPU_PE X_RST#

+1V8_AO N

RG5
10K_02 01_5%

1 2

PEG_CR X_GTX_ P0<9 >
PEG_CR X_GTX_ N0<9>

PEG_CT X_C_GR X_P0<9>
PEG_CT X_C_GR X_N0<9>

PEG_CR X_GTX_ P1<9 >
PEG_CR X_GTX_ N1<9>

PEG_CT X_C_GR X_P1<9>
PEG_CT X_C_GR X_N1<9>

PEG_CR X_GTX_ P2<9 >
PEG_CR X_GTX_ N2<9>

PEG_CT X_C_GR X_P2<9>
PEG_CT X_C_GR X_N2<9>

PEG_CR X_GTX_ P3<9 >
PEG_CR X_GTX_ N3<9>

PEG_CT X_C_GR X_P3<9>
PEG_CT X_C_GR X_N3<9>

PEG_CR X_GTX_ P4<9 >
PEG_CR X_GTX_ N4<9>

PEG_CT X_C_GR X_P4<9>
PEG_CT X_C_GR X_N4<9>

PEG_CR X_GTX_ P5<9 >
PEG_CR X_GTX_ N5<9>

PEG_CT X_C_GR X_P5<9>
PEG_CT X_C_GR X_N5<9>

PEG_CR X_GTX_ P6<9 >
PEG_CR X_GTX_ N6<9>

PEG_CT X_C_GR X_P6<9>
PEG_CT X_C_GR X_N6<9>

PEG_CR X_GTX_ P7<9 >
PEG_CR X_GTX_ N7<9>

PEG_CT X_C_GR X_P7<9>
PEG_CT X_C_GR X_N7<9>

PEG_CR X_GTX_ P8<9 >
PEG_CR X_GTX_ N8<9>

PEG_CT X_C_GR X_P8<9>
PEG_CT X_C_GR X_N8<9>

PEG_CR X_GTX_ P9<9 >
PEG_CR X_GTX_ N9<9>

PEG_CT X_C_GR X_P9<9>
PEG_CT X_C_GR X_N9<9>

PEG_CR X_GTX_ P10<9>
PEG_CR X_GTX_ N10<9>

PEG_CT X_C_GR X_P10<9>
PEG_CT X_C_GR X_N10< 9>

PEG_CR X_GTX_ P11<9>
PEG_CR X_GTX_ N11<9>

PEG_CT X_C_GR X_P11<9>
PEG_CT X_C_GR X_N11< 9>

PEG_CR X_GTX_ P12<9>
PEG_CR X_GTX_ N12<9>

PEG_CT X_C_GR X_P12<9>
PEG_CT X_C_GR X_N12< 9>

PEG_CR X_GTX_ P13<9>
PEG_CR X_GTX_ N13<9>

PEG_CT X_C_GR X_P13<9>
PEG_CT X_C_GR X_N13< 9>

PEG_CR X_GTX_ P14<9>
PEG_CR X_GTX_ N14<9>

PEG_CT X_C_GR X_P14<9>
PEG_CT X_C_GR X_N14< 9>

PEG_CR X_GTX_ P15<9>
PEG_CR X_GTX_ N15<9>

PEG_CT X_C_GR X_P15<9>
PEG_CT X_C_GR X_N15< 9>

CLK_PE G_P4<15 >
CLK_PE G_N4<15>

DGPU_PE X_RST# <25>

RG6

CLKREQ _PEG#0 _R

T12 P AD~D

1 2

@

@

DGPU_PE X_RST# _R

0_0201 _5%

BK44

BK26

BL26

BM26
BM27

BG26
BH26

BL27

BK27

BF26
BE26

BK29

BL29

BF27
BG27

BM29
BM30

BG29
BH29

BL30

BK30

BF29
BE29

BK32

BL32

BF30
BG30

BM32
BM33

BG32
BH32

BL33

BK33

BF32
BE32

BK35

BL35

BF33
BG33

BM35
BM36

BG35
BH35

BL36

BK36

BF35
BE35

BK38

BL38

BF36
BG36

BM38
BM39

BG38
BH38

BL39

BK39

BF38
BE38

BK41

BL41

BF39
BG39

BM41
BM42

BH41
BG41

BL42
BK42

UV1A

@

1/22 PCI_EXPRESS

PEX_WAKE_N

PEX_RST_N

PEX_CLKREQ_N

PEX_REFCLK
PEX_REFCLK_N

PEX_TX0
PEX_TX0_N

PEX_RX0
PEX_RX0_N

PEX_TX1
PEX_TX1_N

PEX_RX1
PEX_RX1_N

PEX_TX2
PEX_TX2_N

PEX_RX2
PEX_RX2_N

PEX_TX3
PEX_TX3_N

PEX_RX3
PEX_RX3_N

PEX_TX4
PEX_TX4_N

PEX_RX4
PEX_RX4_N

PEX_TX5
PEX_TX5_N

PEX_RX5
PEX_RX5_N

PEX_TX6
PEX_TX6_N

PEX_RX6
PEX_RX6_N

PEX_TX7
PEX_TX7_N

PEX_RX7
PEX_RX7_N

PEX_TX8
PEX_TX8_N

PEX_RX8
PEX_RX8_N

PEX_TX9
PEX_TX9_N

PEX_RX9
PEX_RX9_N

PEX_TX10
PEX_TX10_N

PEX_RX10
PEX_RX10_N

PEX_TX11
PEX_TX11_N

PEX_RX11
PEX_RX11_N

PEX_TX12
PEX_TX12_N

PEX_RX12
PEX_RX12_N

PEX_TX13
PEX_TX13_N

PEX_RX13
PEX_RX13_N

PEX_TX14
PEX_TX14_N

PEX_RX14
PEX_RX14_N

PEX_TX15
PEX_TX15_N

PEX_RX15
PEX_RX15_N

PEX_DVDD_1
PEX_DVDD_2
PEX_DVDD_3
PEX_DVDD_4
PEX_DVDD_5
PEX_DVDD_6

PEX_CVDD_1
PEX_CVDD_2

PEX_HVDD_1
PEX_HVDD_2
PEX_HVDD_3
PEX_HVDD_4
PEX_HVDD_5
PEX_HVDD_6
PEX_HVDD_7
PEX_HVDD_8

PEX_HVDD_9
PEX_HVDD_10
PEX_HVDD_11

PEX_PLL_HVDD

PEX_TERMP

N18E-G3-E S-A1_FC BGA22 28

1

1

CG1

CG2

2

2

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

Under GPU

BB35
BB36
BC35
BC36
BD33
BD36

BB33
BC33

BB26
BB27
BB29
BB32
BC26
BC27
BC29
BC30
BC32
BD27
BD30

BB30

1

2

0.47U_0201_6.3V6K

1

2

0.47U_0201_6.3V6K

Under GPU

1

1

CG43

2

2

0.47U_0201_6.3V6K

1

CG13

CG12

2

0.47U_0201_6.3V6K

1

CG25

CG26

2

0.47U_0201_6.3V6K

CG44

0.47U_0201_6.3V6K

Under GPU

1.0VS_DGPU 0.47U 16 PCS

1.0VS_DGPU 10U 3 PCS

1.0VS_DGPU 4.7U 3 PCS

1.0VS_DGPU 22U 2PCS

PEX_TE RMP

BL44

12

RG7

2.49K_0 402_1%

+1.0VS_D GPU

1

1

1

1

2

1

2

1

2

CG5

0.47U_0201_6.3V6K

CG16

0.47U_0201_6.3V6K

CG29

0.47U_0201_6.3V6K

+1V8_MAI N

1

CG6

CG7

2

2

0.47U_0201_6.3V6K

0.47U_0201_6.3V6K

+1.0VS_D GPU

1

1

CG17

CG18

2

2

0.47U_0201_6.3V6K

0.47U_0201_6.3V6K

+1V8_MAI N

1

1

CG30

CG31

2

2

0.47U_0201_6.3V6K

0.47U_0201_6.3V6K

CG4

CG3

2

2

4.7U_0402_6.3V6M

0.47U_0201_6.3V6K

1

1

CG14

CG15

2

2

0.47U_0201_6.3V6K

0.47U_0201_6.3V6K

1

1

CG28

CG27

2

2

0.47U_0201_6.3V6K

0.47U_0201_6.3V6K

1

1

1

CG8

2

0.47U_0201_6.3V6K

1

CG19

2

0.47U_0201_6.3V6K

1

CG32

2

0.47U_0201_6.3V6K

1V8_MAIN 0.47U 12 PCS

1V8_MAIN 10U 3 PCS

1V8_MAIN 4.7U 3 PCS

1V8_MAIN 22U 2PCS

1

CG9

CG10

CG11

2

2

0.47U_0201_6.3V6K

PEX_DVDD

2

PEX_CVDD

0.47U_0201_6.3V6K

0.47U_0201_6.3V6K

+1.0VS_D GPU

Near GPU

1

2

2

CG21

CG20

1

1

10U_0603_6.3V6M

10U_0603_6.3V6M

2

2

CG33

CG34

1

1

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

CG38

CG39

2

2

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

2

CG22

2

1

10U_0603_6.3V6M

1

2

CG35

2

1

10U_0603_6.3V6M

1

1

CG40

2

2

4.7U_0402_6.3V6M

1

CG23

CG24

2

22U_0603_6.3V6M

22U_0603_6.3V6M

+1V8_MAI N

Near GPU

1

CG36

CG37

2

22U_0603_6.3V6M

22U_0603_6.3V6M

+1V8_MAI N

Under GPU

1

CG41

CG42

2

0.47U_0201_6.3V6K

0.47U_0201_6.3V6K

PEX_HVDD
PEX_PLL_HVDD

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENTEXCEPTASAUTHORIZEDBYCOMPALELECTRONICS,INC.NEITHERTHISSHEETNORTHEINFORMATIONITCONTAINS

DEPARTMENTEXCEPTASAUTHORIZEDBYCOMPALELECTRONICS,INC.NEITHERTHISSHEETNORTHEINFORMATIONITCONTAINS

DEPARTMENTEXCEPTASAUTHORIZEDBYCOMPALELECTRONICS,INC.NEITHERTHISSHEETNORTHEINFORMATIONITCONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

Compal Secret Data

Compal Secret Data

Compal Secret Data

2020/7/31 2020/7/31

2020/7/31 2020/7/31

2020/7/31 2020/7/31

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

N18E(1/9) PCIE

N18E(1/9) PCIE

N18E(1/9) PCIE

Size Doc ument Number Rev

Size Doc ument Number Rev

Size Doc ument Number Rev

LA-J561P

LA-J561P

LA-J561P

Date: Sheet of

Date: Sheet of

Date: Sheet of

E

24 100Wednes day, February 26 , 2020

24 100Wednes day, February 26 , 2020

24 100Wednes day, February 26 , 2020

1.0

1.0

1.0

A

UV1T

@

12/22 MISC 1

BF12

BK24
BL23
BM23
BM24
BL24

BK23

RG26
100K_0201_5%

QG6A
PJT138KA 2N SOT363-6

RG42
100K_0201_5%

QG7A
PJT138KA 2N SOT363-6

BG5

BJ1

BJ2

BJ9

BJ11

2

2

OVERT

TS_VREF

THERMDN

THERMDP

ADC_IN
ADC_IN_N

JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_TRST_N

NVJTAG_SEL

+3VS

12

RG23

2.2K_0201_5%

61

D

G

QG6B

S

PJT138KA 2N SOT363-6

+3VS

12

RG39

2.2K_0201_5%

61

D

G

QG7B

S

PJT138KA 2N SOT363-6

I2CS_SCL
I2CS_SDA

I2CC_SCL

I2CC_SDA

I2CB_SCL
I2CB_SDA

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8

GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
GPIO29
GPIO30

N18E-G3-ES-A1_FCBGA2228

12

RG210
100K_0201_5%

Add Pull down for verndor suggest
20190813

TO eDP PWM MUX

OVERT#

1 1

ADC_IN_P<39>
ADC_IN_N<39>

12

RG16

Default

LLJTAG support

H Test Mode --> Enable

JTAG_TCLK
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_TRST#

12

RG17
10K_0201_5%

FunctionPin Name

Test Mode --> Disable

T13 PAD~D@
T14 PAD~D@
T15 PAD~D@
T16 PAD~D@

10K_0201_5%

2 2

JTAG_TRST

NVJTAG_SEL

+3VS

12

34

D

LCD_BLEN

3 3

G

5

S

+3VS

12

34

D

GPU_INV_PWM

G

5

S

+1V8_AON

12

RG31
10K_0201_5%

4 4

1 2

EDP_HPD_GPU<41>

RG36 0_0201_5%@

EDP_HPD_GPU#

12

RV2
100K_0201_5%

3

5

4

QG5B
L2N7002DW1T1G 2N SC88-6

SB00000PV00 Cha nge to SB00000EO00

A

VGA_SMB_CK2

BJ8

VGA_SMB_DA2

BH8

I2CC_SCL_R

BG9

I2CC_SDA_R

BH9

EDP_I2CB_SCL_R

BG8

EDP_I2CB_SDA_R

BF8

BD6

GPU_GC6_FB_EN

BB5

GC6_EVENT#_D

BD1

DGPU_EDP_MUX_CNTL

BE4

1V8_MAIN_EN

BE1

OD_ON_OFF_R

BG2

NVVDD_PSI#

BD2

GPU_INV_PWM

BD7
BH4

THERM_ALERT#

BJ3

MEM_VREF

BD3

DGPU_ENVDD_R

BH3

GPU_PROHOT_NV

BE6

PCH_ENKBL_MON

BB1

TBTA_HPD_GPU#

BG4

TBTB_HPD_GPU#

BG1

DGPU_PWM_SEL

BE2

EDP_HPD_GPU#

BH1
BE3
BD4

GPU_FGC6_EN

BE5

LCD_BLEN

BA5
BB6
BG3

DONGLE_DET#

BD5

FB_VDD_PSI

BB2

FP_FUSE

BE7
BA4

ADC_MUX_SEL

BB4

IDLE_IN_SW

BA3
BB3

GPU_ENBKL <41>

GPU_BKL_PWM <41>

B

For EC

For NVVDD VR

For eDP DDS

20190808 Change Net Name

T21

@

PAD~D

12

RG19
10K_0402_5%

0190808 add lev el shift for 1.8V and 3.3V

2

DGPU_PWM_SEL

12

RG208
10K_0201_5%

Add Pull down for verndor suggest
20190812

DGPU_EDP_MUX_CNTL

12

RG207
10K_0201_5%

Add Pull down for verndor suggest
20190812

B

C

EDP_I2CB_SCL_R
EDP_I2CB_SDA_R

1 2

RG10 1.8K_0201_1%

1 2

RG11 1.8K_0201_1%

+1V8_AON should be changed to +1V8_MAIN?

Change tounpop for verndor suggest
20190813

DG1

NVVDD_VID <91>
GPU_GC6_FB_EN <34>

1V8_MAIN_EN <34>

NVVDD_PSI# <91>

VRAM_VDD_CTL <95>

MEM_VREF <35,36,37,38>

TBTA_HPD_GPU# <57>
TBTB_HPD_GPU# <57>

TDP_HPD_GPU# <60>

GPU_FGC6_EN <34>

FB_VDD_PSI <95>
FP_FUSE <29>

HDMI_HPD_GPU# <43>

ADC_MUX_SEL <39>

+3VS

12

RG202
100K_0201_5%

34

D

G

5

S

QG18A
PJT138KA 2N SOT363-6

+3VS

12

RG204
100K_0201_5%

34

D

G

5

S

RB751S40T1G_SOD523-2

DG2
RB751S40T1G_SOD523-2

DG7
RB751S40T1G_SOD523-2

2

2

QG19A
PJT138KA 2N SOT363-6

12

@

12
12

GPU_EVENT# <19>

GPU_PROCHOT <48,83>
PCH_ENBKL <17,41>

T17PAD~D @

T18PAD~D @

DGPU_PEX_RST#

1 2

RG20 10K_0201_5%

OVERT#

L2N7002DW1T1G 2N SC88-6

+3VS

12

RG201

2.2K_0201_5%

61

D

G

QG18B

S

PJT138KA 2N SOT363-6

Change GPPIO3 Net Name for verndor suggest
20190812

+3VS

12

RG203

2.2K_0201_5%

61

D

G

QG19B

S

PJT138KA 2N SOT363-6

Change GPPIO3 Net Name for verndor suggest
20190812

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

C

+1V8_AON

2

GPU_OVERT#

61

QG5A

DGPU_PWM_SW_SEL_Q <41>

TO eDP PWM MUX

DGPU_EDP_MUX_CNTL_Q <41>

TO eDP MUX

2020/7/31 2020/7/31

2020/7/31 2020/7/31

2020/7/31 2020/7/31

VGA_SMB_CK2

VGA_SMB_DA2

+1V8_AON

12

RG12

1.8K_0201_1%

I2CC_SCL_R

I2CC_SDA_R

EDP_I2CB_SCL_R

EDP_I2CB_SDA_R

GPU_OVERT# <34>

DGPU_PEX_RST#<24>

DGPU_ENVDD_R

RG211

100K_0201_5%

OVERT#

GC6_EVENT#_D

OD_ON_OFF_R

GPU_PROHOT_NV

VGA_SMB_CK2

VGA_SMB_DA2

1V8_MAIN_EN

NVVDD_PSI#

THERM_ALERT#

ADC_MUX_SEL

PCH_ENKBL_MON

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

1 2

RG8 10K_0201_5%

5

QG2A

34

PJT138KA 2N SOT363-6

SGD

2

QG2B

G

PJT138KA 2N SOT363-6

61

S

D

+1V8_MAIN

Change to +1V8MAIN for verndor suggest
20190812

EC_SMB_CK2 <18,41,48,51,60>

EC_SMB_DA2 <18,41,48,51,60>

+1V8_MAIN

1 2

RG9 10K_0201_5%

12

2

G

QG3B

61

PJT138KA 2N SOT363-6

S

D

5

QG3A

34

PJT138KA 2N SOT363-6

SGD

VGA_I2CC_SDA_R_Q <91>

VGA_I2CC_SCL_R_Q <91>

RG13

1.8K_0201_1%

20190808 add le vel shift for 1.8V and 3.3V

+1V8_MAIN

1 2

RG200 10K_0201_5%

5

QG17A

34

PJT138KA 2N SOT363-6

SGD

2

QG17B

G

PJT138KA 2N SOT363-6

61

S

D

DGPU_PEX_RST#

THERM_ALERT#

+3VS

12

RG206
100K_0201_5%

2

34

D

G

5

S

QG20A
PJT138KA 2N SOT363-6

12

Add Pull down for verndor suggest
20190813

1 2

RG21 10K_0201_5%

1 2

RG22 10K_0201_5%

1 2

RG24 10K_0201_5%@

1 2

RG25 10K_0201_5%

1 2

RG27 1.8K_0201_1%

1 2

RG28 1.8K_0201_1%

1 2

RG29 10K_0201_5%

1 2

RG30 10K_0201_5%

1 2

RG32 10K_0201_5%

1 2

RG33 10K_0201_5%

1 2

RG209 100K_0201_5%

D

1 2

RG18 10K_0201_5%

+3VS

12

RG205

2.2K_0201_5%

61

D

G

QG20B

S

PJT138KA 2N SOT363-6

+1V8_AON

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

EDP_I2CB_SCL <42>

EDP_I2CB_SDA <42>

5

34

SGD

QG4A
PJT138KA 2N SOT363-6

2

G

61

S

D

QG4B
PJT138KA 2N SOT363-6

RG40, RG41, RG43 POP for verndor suggest
20190813

GPU_FGC6_EN

GPU_GC6_FB_EN

VRAM_VDD_CTL

MEM_VREF

GPU_INV_PWM

DGPU_ENVDD

LCD_BLEN

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

N18E(2/9) GPIO

N18E(2/9) GPIO

N18E(2/9) GPIO

LA-J561P

LA-J561P

LA-J561P

E

For EC

For NVVDD VR

For eDP DDS

THERM_ALERT#_EC_R <48>

DGPU_ENVDD <41>

1 2

RG34 10K_0201_5%

1 2

RG35 10K_0201_5%

1 2

RG37 10K_0201_5%

1 2

RG38 100K_0201_5%

1 2

RG40 100K_0201_5%

1 2

RG41 100K_0201_5%

1 2

RG43 100K_0201_5%

25 100Wednesday, February 26, 2020

25 100Wednesday, February 26, 2020

E

25 100Wednesday, February 26, 2020

1.0

1.0

1.0

A

TBT

UV1N

@

7/22 IFPAB

RG44
1K_040 2_1%

IFPAB_ RSET

BD23

12

1 1

2 2

3 3

+IFPX_P LLVDD

+1.0VS_D GPU

1

1

CG48

CG47

2

2

0.47U_0201_6.3V6K

Under GPU

+1.0VS_D GPU

1

1

CG53

CG52

2

2

4.7U_0402_6.3V6M

Near GPU

Under GPU

1

1

1

CG49

CG46

2

2

2

0.47U_0201_6.3V6K

0.47U_0201_6.3V6K

0.47U_0201_6.3V6K

1

1

1

CG54

CG55

2

2

2

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

0.47U_0201_6.3V6K

+IFPX_P LLVDD

IFPAB_RSET

BD21

IFPAB_PLLVDD

1

CG45

2

0.47U_0201_6.3V6K

BB18

IFP_IOVDD_2

BB17

IFP_IOVDD_1

BB20

IFP_IOVDD_3

BB21

IFP_IOVDD_4

CG50

0.47U_0201_6.3V6K

IFPAB

1

1

1

1

CG57

CG56

2

0.47U_0201_6.3V6K

CG59

CG60

CG58

2

2

2

0.47U_0201_6.3V6K

0.47U_0201_6.3V6K

0.47U_0201_6.3V6K

0.47U_0201_6.3V6K

12

@

RG69

10K_04 02_5%

@

CG67

18P_04 02_50V 8J

DL-DVI

SDA
SCL

TXC
TXC

TXD0
TXD0

TXD1
TXD1

TXD2
TXD2

TXD3
TXD3

TXD4
TXD4

TXD5
TXD5

Under GPU

1

2

1

1

CG64

2

2

0.47U_0201_6.3V6K

12

RG70
10K_04 02_5%

1

2

DVI/HDMI DP

SDA

IFPA_AUX_SDA_N

SCL

IFPA_AUX_SCL

TXC

IFPA_L3_N

TXC

IFPA_L3

TXD0

IFPA_L2_N

TXD0

IFPA_L2

TXD1

IFPA_L1_N

TXD1

IFPA_L1

TXD2

IFPA_L0_N

TXD2

IFPA_L0

SDA

IFPB_AUX_SDA_N

SCL

IFPB_AUX_SCL

IFPB_L3_N

TXC
TXC

IFPB_L3

TXD0

IFPB_L2_N

TXD0

IFPB_L2

TXD1

IFPB_L1_N

TXD1

IFPB_L1

TXD2

IFPB_L0_N

TXD2

IFPB_L0

N18E-G3-E S-A1_FC BGA22 28

BD12

1

CG61

2

0.47U_0201_6.3V6K

1

CG65

2

0.47U_0201_6.3V6K

BC12

CG62

0.47U_0201_6.3V6K

U42

AF11

BB24

CG66

0.47U_0201_6.3V6K

BJ6

BL6

XTALIN XTA LOUT

2

CG68
12P_04 02_50V 8J

1

UV1V

BH11
BG11

BF21
BG21

BG23
BH23

BF23
BE23

BF24
BG24

BG12
BH12

BL18
BK18

BK20
BL20

BM20
BM21

BL21
BK21

@

13/22 XTAL/PLL

SP_PLLVDD

VID_PLLVDD

GPCPLL_AVDD0

GPCPLL_AVDD1

XSN_PLLVDD

EXT_REFCLK_FL

XTAL_IN

RG72
10M_040 2_5%

1 2

YG1

113

NC2NC

27MHZ_10 PF_7R2 70000 01

B

GPU_DPA _AUXN <57>
GPU_DPA _AUXP <57>

GPU_DPA _N3 <57>
GPU_DPA _P3 <57>

GPU_DPA _N2 <57>
GPU_DPA _P2 <57>

GPU_DPA _N1 <57>
GPU_DPA _P1 <57>

GPU_DPA _N0 <57>
GPU_DPA _P0 <57>

GPU_DPB _AUXN <57>
GPU_DPB _AUXP <57>

GPU_DPB _N3 <57>
GPU_DPB _P3 <57>

GPU_DPB _N2 <57>
GPU_DPB _P2 <57>

GPU_DPB _N1 <57>
GPU_DPB _P1 <57>

GPU_DPB _N0 <57>
GPU_DPB _P0 <57>

XTAL_OUTBUFF

N18E-G3-E S-A1_FC BGA22 28

3

4

XTAL_OUT

C

Strap1

Strap0GDDR6 VRAMLStrap2

Samsung , K4Z80325BC-HC14

Micron , MT61K256M32JE-14:A

Hynix , H56C8H24MJR-S2C

12

RG71

100K_0 201_5%

RG68

1 2

@

100K_0 201_5%

RG58 X76_S@
100K_0 201_1%

RG58 X76_M@
100K_0 201_1%

Samsung

Micron

XTALOUT BUFF_R

BK6

BM6

2

CG69
12P_04 02_50V 8J

1

+1V8_AO N

RG59 X76_S@
100K_0 201_1%

RG59 X76_M@
100K_0 201_1%

RG60 X76_S@
100K_0 201_1%

RG47 X76_M@
100K_0 201_1%

12

RG45
100K_0 201_1%

@

12

RG58
100K_0 201_1%

@

STRAP2

L

L LH 0X2

12

RG46
100K_0 201_1%

@

STRAP1

12

RG59
100K_0 201_1%

@

L

L

L

H

12

RG47
100K_0 201_1%

@

STRAP0

12

RG60
100K_0 201_1%

@

RAMCFG

0X0

0X1

12

12

RG48

RG49

100K_0 201_1%

100K_0 201_1%

GSYNC@

@

STRAP4

STRAP5

12

12

RG61

RG62

100K_0 201_1%

100K_0 201_1%

NOGSYNC@

SP-08867: Partner must use N18E
GPU Secondary PCI DeviceID for
G-SYNC display enablement.

+1V8_AO N

12

12

RG50
100K_0 201_1%

STRAP3

RG63
100K_0 201_1%

@

D

DGPU_RO M_SCLK

CS#
DO(IO1)
WP#(IO2)
GND

1

@EMI@

CG51
20P_02 01_25V 8J

2

HOLD#(IO3)

DI(IO0)

12

RG51
100K_0 201_1%

@

12

RG55
100K_0 201_1%

8

VCC

7
6

CLK

5

UV1U

@

14/22 MISC 2

BL3

STRAP0

BL4

STRAP1

BM4

STRAP2

BM5

STRAP3

BK5

STRAP4

BJ5

STRAP5

ROM_CS_N

ROM_SO

ROM_SCLK

BUFRST_N

N18E-G3-E S-A1_FC BGA22 28

ROM_CS# ROM_CS# _R
ROM_SO DGPU_ROM_S O_R

ROM_SI

ROM_CS#

BJ4

ROM_SI

BK2

ROM_SO

BK4

ROM_SCL K

10K_02 01_5%

@

GPU_BUFR ST#

RG64

33_020 1_5%

0_0201 _5%

1 2

RG54 33 _0201 _5%

@

T19
PAD~D

GSYNC VBIOS ROM

+1V8_AO N

1 2

UG2

1
2
3
4

W25Q8 0EWSS IG_SO 8

BK3

BF9

1 2

RG65

1 2

RG66

E

+1V8_AO N

12

12

RG53

RG52

100K_0 201_1%

10K_02 01_1%

@

@

12

12

RG56

RG57

10K_02 01_1%

100K_0 201_1%

+1V8_AO N

1

CG63

0.1U_020 1_10V6 K

2

1 2

DGPU_RO M_SCLK

DGPU_RO M_SI ROM_SI

RG67 33_ 0201_ 5%

TXC SJ1000TQ00

Murata SJ10000UI00

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENTEXCEPTASAUTHORIZEDBYCOMPALELECTRONICS,INC.NEITHERTHISSHEETNORTHEINFORMATIONITCONTAINS

DEPARTMENTEXCEPTASAUTHORIZEDBYCOMPALELECTRONICS,INC.NEITHERTHISSHEETNORTHEINFORMATIONITCONTAINS

DEPARTMENTEXCEPTASAUTHORIZEDBYCOMPALELECTRONICS,INC.NEITHERTHISSHEETNORTHEINFORMATIONITCONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

Compal Secret Data

Compal Secret Data

Compal Secret Data

2020/7/31 2020/7/31

2020/7/31 2020/7/31

2020/7/31 2020/7/31

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

N18E(3/9) Strap, XTAL, IFP

N18E(3/9) Strap, XTAL, IFP

N18E(3/9) Strap, XTAL, IFP

Size Doc ument Number Rev

Size Doc ument Number Rev

Size Doc ument Number Rev

LA-J561P

LA-J561P

LA-J561P

Date: Sheet of

Date: Sheet of

Date: Sheet

E

of

26 100Wednes day, February 26 , 2020

26 100Wednes day, February 26 , 2020

26 100Wednes day, February 26 , 2020

1.0

1.0

1.0

A

1 1

HDMI 2.0 eDP

UV1O
RG73
1K_0201_1%

IFPCD_RSET

1 2

+IFPX_PLLVDD

1

CG70

2

0.47U_0201_6.3V6K

2 2

+1.0VS_DGPU

Under GPU

BD20

BD18

BB23
BC17

@

8/22 IFPC

IFPCD_RSET

IFPCD_PLLVDD

IFPC

IFP_IOVDD_5
IFP_IOVDD_6

DVI/HDMI

SDA
SCL

TXC
TXC

TXD0
TXD0

TXD1
TXD1

TXD2
TXD2

N18E-G3-ES-A1_FCBGA2228

B

DP

IFPC_AUX_SDA_N

IFPC_AUX_SCL

IFPC_L3_N

IFPC_L2_N

IFPC_L1_N

IFPC_L0_N

IFPC_L3

IFPC_L2

IFPC_L1

IFPC_L0

BL9
BK9

BF17
BE17

BF18
BG18

BG20
BH20

BF20
BE20

HDMI_CTRLDAT <43>
HDMI_CTRLCLK <43>

TMDS_TXCN <43>
TMDS_TXCP <43>

TMDS_TX0N <43>
TMDS_TX0P <43>

TMDS_TX1N <43>
TMDS_TX1P <43>

TMDS_TX2N <43>
TMDS_TX2P <43>

+1.0VS_DGPU

C

UV1P

@

9/22 IFPD

IFPD

BC18

IFP_IOVDD_7

BC20

IFP_IOVDD_8

D

DVI/HDMI

SDA
SCL

TXC
TXC

TXD0
TXD0

TXD1
TXD1

TXD2
TXD2

N18E-G3-ES-A1_FCBGA2228

DP

IFPD_AUX_SDA_N

IFPD_AUX_SCL

IFPD_L3_N

IFPD_L3

IFPD_L2_N

IFPD_L2

IFPD_L1_N

IFPD_L1

IFPD_L0_N

IFPD_L0

BF11
BE11

BM14
BM15

BL15
BK15

BK17
BL17

BM17
BM18

RV3
100K_0201_1%

RV4
100K_0201_1%

E

12
12

GPU_EDP_AUXN <41>
GPU_EDP_AUXP <41>

GPU_EDP_TXN3 <41>
GPU_EDP_TXP3 <41>

GPU_EDP_TXN2 <41>
GPU_EDP_TXP2 <41>

GPU_EDP_TXN1 <41>
GPU_EDP_TXP1 <41>

GPU_EDP_TXN0 <41>
GPU_EDP_TXP0 <41>

RV77
100K_0201_1%

12
12

Add Pull down for verndor suggest

TYPEC SW

UV1Q

@

3 3

+1V8_MAIN +IFPX_PLLVDD

1 2

LG1
PBY160808T-300Y-N_2P

Near GPU

+1.0VS_DGPU

4 4

12

RG74
1K_0201_1%

1 2

1

CG71

2

22U_0603_6.3V6M

A

IFPEF_RSET

Under GPU

1

CG73

CG72

2

4.7U_0402_6.3V6M

10/22 IFPE

BD17

IFPE_RSET

BD15

IFPE_PLLVDD

IFPE

0.47U_0201_6.3V6K

BC21

IFP_IOVDD_9

BC23

IFP_IOVDD_10

DVI/HDMI

SDA
SCL

TXC
TXC

TXD0
TXD0

TXD1
TXD1

TXD2
TXD2

N18E-G3-ES-A1_FCBGA2228

IFPE_AUX_SDA_N

B

DP

IFPE_AUX_SCL

IFPE_L3_N

IFPE_L3

IFPE_L2_N

IFPE_L2

IFPE_L1_N

IFPE_L1

IFPE_L0_N

IFPE_L0

RV76
100K_0201_1%

BL8
BK8

BG14
BH14

BF14
BE14

BF15
BG15

BG17
BH17

20190813

GPU_TDP_AUXN <60>
GPU_TDP_AUXP <60>

GPU_TDP_N3 <60>
GPU_TDP_P3 <60>

GPU_TDP_N2 <60>
GPU_TDP_P2 <60>

GPU_TDP_N1 <60>
GPU_TDP_P1 <60>

GPU_TDP_N0 <60>
GPU_TDP_P0 <60>

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

C

2020/7/31 2020/7/31

2020/7/31 2020/7/31

2020/7/31 2020/7/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

N18E(4/9) eDP, HDMI, DP

N18E(4/9) eDP, HDMI, DP

N18E(4/9) eDP, HDMI, DP

LA-J561P

LA-J561P

LA-J561P

E

27 100Wednesday, February 26, 2020

27 100Wednesday, February 26, 2020

27 100Wednesday, February 26, 2020

1.0

1.0

1.0

A

UV1R

@

6/22 IFPF/USB-C

1 1

+1V8_AON

12

22U_0603_6.3V6M

CG74

1

0.47U_0201_6.3V6K

2

Under GPUNear GPU

2 2

CG75

USB_DVDD

12

RG7510K_0201_5%

USB_HVDD1

12

RG7610K_0201_5%

1

0.47U_0201_6.3V6K

2

USB_VDDP

12

RG7710K_0201_5%

CG76

BB15
BC15

AW10
AW11

BE12

AW9

BG6

BH6

BA6

USB_DVDD_1
USB_DVDD_2

USB_HVDD_1
USB_HVDD_2

USB_PLL_HVDD

USB_VDDP

USB_TERMP0

USB_TERMP1

USB_RBIAS

B

USB-C Display Interface

USB-C

SBU2
SBU1

RX1
RX1

TX1
TX1

TX2
TX2

RX2
RX2

IFPF/USB-C

DP

IFPF_AUX_SDA_N

IFPF_AUX_SCL

IFPF_L3_N

IFPF_L3

IFPF_L2_N

IFPF_L2

IFPF_L1_N

IFPF_L1

IFPF_L0_N

IFPF_L0

USB_L0_N

USB_L0

USB_L1_N

USB_L1

USB_SCL

USB_SDA

N18E-G3-ES-A1_FCBGA2228

BM9
BM8

BK11
BL11

BM11
BM12

BL12
BK12

BK14
BL14

BA1
BA2

BA7
BA8

BB8
BB7

C

@

+1V8_AON+1V8_AON

@

RG78

RG79

1 2

2.2K_0201_5%

1 2

2.2K_0201_5%

D

E

NVLink Interface

UV1S

@

11/22 NVHS

NVHS0_RX0_N

NVHS0_RX1_N

NVHS0_RX2_N

NVHS0_RX3_N

NVHS0_RX4_N

NVHS0_RX5_N

NVHS0_RX6_N

NVHS0_RX7_N

NVHS_REFCLK

NVHS_REFCLK_N

EXT_REFCLK_SLI

N/A

N18E-G3-ES-A1_FCBGA2228

N18G3@

CG77

0.47U_0201_6.3V6K

NVHS_VDD

1

2

NVHS_HVDD

NVHS_PLL_HVDD

AT10

NVHS_DVDD_1

AT9

NVHS_DVDD_2

AV10

NVHS_DVDD_3

AV11

NVHS_DVDD_4

AR10

NVHS_CVDD_1

AT11

NVHS_CVDD_2

1

CG78

2

N18G3@

0.47U_0201_6.3V6K

AM10

NVHS_HVDD_1

AM11

NVHS_HVDD_2

AN10

NVHS_HVDD_3

AN11

NVHS_HVDD_4

AR11

NVHS_HVDD_5

AN9

NVHS_PLL_HVDD

AM3

NVHS_TERMP

N18E-G3

NVHS RX/TX

B

1 2

RG80 10K_0201_5%

RG82

NVHS_CVDD

0_0201_5%

RG82

N18G1@

N18G0@

+1.0VS_DGPU

1 2

RG82 0_0201_5%N18G2@

1 2

RG83 0_0402_5%N18G3@

3 3

NVHS_CVDD

0_0201_5%

4 4

1 2

RG85 10K_0201_5%

1 2

RG86 10K_0201_5%

A

NVHS0_RX0

NVHS0_RX1

NVHS0_RX2

NVHS0_RX3

NVHS0_RX4

NVHS0_RX5

NVHS0_RX6

NVHS0_RX7

NVHS0_TX0

NVHS0_TX0_N

NVHS0_TX1

NVHS0_TX1_N

NVHS0_TX2

NVHS0_TX2_N

NVHS0_TX3

NVHS0_TX3_N

NVHS0_TX4

NVHS0_TX4_N

NVHS0_TX5

NVHS0_TX5_N

NVHS0_TX6

NVHS0_TX6_N

NVHS0_TX7

NVHS0_TX7_N

AM1
AN1

AN2
AN3

AR3
AR2

AR1
AT1

AT2
AT3

AV3
AV2

AV1
AW1

AW2
AW3

AM7
AM8

AN7
AN6

AR6
AR5

AR7
AR8

AT7
AT6

AV6
AV5

AV7
AV8

AW7
AW6

AM6
AM5

AM2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

C

2020/7/31 2020/7/31

2020/7/31 2020/7/31

2020/7/31 2020/7/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

N18E(5/9) USB-C, NVLink

N18E(5/9) USB-C, NVLink

N18E(5/9) USB-C, NVLink

LA-J561P

LA-J561P

LA-J561P

E

28 100Wednesday, February 26, 2020

28 100Wednesday, February 26, 2020

28 100Wednesday, February 26, 2020

1.0

1.0

1.0

5

4

3

2

1

1V8_AON_1
1V8_AON_2
1V8_AON_3

NC_1
NC_2
NC_3

1

CG83

0.47U_0201_ 6.3V6K

2

1

CG88

1U_0402_6.3 V6K

2

BA10
BB14
BC14

BD24
BM44
BM45

+1V8_AON

1

CG89

1U_0402_6.3 V6K

2

UV1K

@

BD14

12

RG87

2.21K_0402_1%

2.2U_0402_6.3V6M

+1V8_AON

1

CG81

0.47U_0201_ 6.3V6K

2

Under GPU

1

CG86

4.7U_0402_6 .3V6M

2

20/22 NC/1V8

FP_FUSE_SRC

N18E-G3-ES-A1_ FCBGA2228

1

CG82

0.47U_0201_ 6.3V6K

2

1

CG87

1U_0402_6.3 V6K

2

+NVVDD +NVVDD +NVVDD +NVVDD +NVVDD +NVVDD

D D

C C

B B

AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
AA25
AA26
AA27
AA28
AA29
AA30
AA31
AA32
AA33
AA34
AA35
AA36
AA37
AA38
AA39
AA40
AB13
AB40
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC24
AC25
AC26
AC27
AC28
AC29
AC30
AC31
AC32
AC33
AC34
AC35
AC36
AC37
AC38
AC39
AC40
AD13
AD40
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AE26
AE27
AT30
AT31
AT32
AT33
AT34
AT35
AT36
AT37
AT38
AT39
AT40
AT42
AU13
AU40
AU43
AV13
AV14
AV15
AV16
AV17
AV18
AV19
AV20
AV21
AV22
AV23
AV24
AV25
AV26
AV27

@

UV1I

17/22 VDD_1/3

VDD_001
VDD_002
VDD_003
VDD_004
VDD_005
VDD_006
VDD_007
VDD_008
VDD_009
VDD_010
VDD_011
VDD_012
VDD_013
VDD_014
VDD_015
VDD_016
VDD_017
VDD_018
VDD_019
VDD_020
VDD_021
VDD_022
VDD_023
VDD_024
VDD_025
VDD_026
VDD_027
VDD_028
VDD_029
VDD_030
VDD_031
VDD_032
VDD_033
VDD_034
VDD_035
VDD_036
VDD_037
VDD_038
VDD_039
VDD_040
VDD_041
VDD_042
VDD_043
VDD_044
VDD_045
VDD_046
VDD_047
VDD_048
VDD_049
VDD_050
VDD_051
VDD_052
VDD_053
VDD_054
VDD_055
VDD_056
VDD_057
VDD_058
VDD_059
VDD_060
VDD_061
VDD_062
VDD_063
VDD_064
VDD_065
VDD_066
VDD_067
VDD_068
VDD_069
VDD_070
VDD_071
VDD_072
VDD_073
VDD_074
VDD_075
VDD_256
VDD_257
VDD_258
VDD_259
VDD_260
VDD_261
VDD_262
VDD_263
VDD_264
VDD_265
VDD_266
VDD_267
VDD_268
VDD_269
VDD_270
VDD_271
VDD_272
VDD_273
VDD_274
VDD_275
VDD_276
VDD_277
VDD_278
VDD_279
VDD_280
VDD_281
VDD_282
VDD_283
VDD_284
VDD_285

N18E-G3-ES-A1_ FCBGA2228

VDD_076
VDD_077
VDD_078
VDD_079
VDD_080
VDD_081
VDD_082
VDD_083
VDD_084
VDD_085
VDD_086
VDD_087
VDD_088
VDD_089
VDD_090
VDD_091
VDD_092
VDD_093
VDD_094
VDD_095
VDD_096
VDD_097
VDD_098
VDD_099
VDD_100
VDD_101
VDD_102
VDD_103
VDD_104
VDD_105
VDD_106
VDD_107
VDD_108
VDD_109
VDD_110
VDD_111
VDD_112
VDD_113
VDD_114
VDD_115
VDD_116
VDD_117
VDD_118
VDD_119
VDD_120
VDD_121
VDD_122
VDD_123
VDD_124
VDD_125
VDD_126
VDD_127
VDD_128
VDD_129
VDD_130
VDD_131
VDD_132
VDD_133
VDD_134
VDD_135
VDD_136
VDD_137
VDD_138
VDD_139
VDD_140
VDD_141
VDD_142
VDD_143
VDD_144
VDD_286
VDD_287
VDD_288
VDD_289
VDD_290
VDD_291
VDD_292
VDD_293
VDD_294
VDD_295
VDD_296
VDD_297
VDD_298
VDD_299
VDD_300
VDD_301
VDD_302
VDD_303
VDD_304
VDD_305
VDD_306
VDD_307
VDD_308
VDD_309
VDD_310
VDD_311
VDD_312
VDD_313
VDD_314
VDD_315
VDD_316
VDD_317
VDD_318
VDD_319
VDD_320

AE28
AE29
AE30
AE31
AE32
AE33
AE34
AE35
AE36
AE37
AE38
AE39
AE40
AF13
AF14
AF15
AF16
AF17
AF18
AF24
AF25
AF26
AF30
AF31
AF32
AF33
AF34
AF40
AG13
AG19
AG20
AG21
AG22
AG23
AG27
AG28
AG29
AG35
AG36
AG37
AG38
AG39
AG40
AH13
AH14
AH15
AH16
AH17
AH18
AH19
AH20
AH21
AH22
AH23
AH24
AH25
AH26
AH27
AH28
AH29
AH30
AH31
AH32
AH33
AH34
AH35
AH36
AH37
AH38
AV28
AV29
AV30
AV31
AV32
AV33
AV34
AV35
AV36
AV37
AV38
AV39
AV40
AV42
AV43
AV44
AW13
AW40
AW42
AW43
AW44
AW45
AY13
AY14
AY15
AY16
AY17
AY18
AY19
AY20
AY21
AY22
AY23
AY24
AY25

UV1J

AH39
AH40
AJ13
AJ40
AK13
AK14
AK15
AK16
AK17
AK18
AK19
AK20
AK21
AK22
AK23
AK24
AK25
AK26
AK27
AK28
AK29
AK30
AK31
AK32
AK33
AK34
AK35
AK36
AK37
AK38
AK39
AK40
AL13
AL40
AM13
AM14
AM15
AM16
AM17
AM18
AM19
AM20
AM21
AM22
AM23
AM24
AM25
AM26
AM27
AM28
AM29
AM30
AM31
AM32
AM33
AM34
AM35
AM36
AM37
AM38
AM39
AM40
AN13
AN40
AP13
AP14
AP15
AP16
AP17
AP18
AP19
AP20
AP21
AP22
BD41
BD46
BD47
BD48
BD49
BD50
BD51
BE41
BE42
BE43
BE46
BE47

@

18/22 VDD_2/3

VDD_145
VDD_146
VDD_147
VDD_148
VDD_149
VDD_150
VDD_151
VDD_152
VDD_153
VDD_154
VDD_155
VDD_156
VDD_157
VDD_158
VDD_159
VDD_160
VDD_161
VDD_162
VDD_163
VDD_164
VDD_165
VDD_166
VDD_167
VDD_168
VDD_169
VDD_170
VDD_171
VDD_172
VDD_173
VDD_174
VDD_175
VDD_176
VDD_177
VDD_178
VDD_179
VDD_180
VDD_181
VDD_182
VDD_183
VDD_184
VDD_185
VDD_186
VDD_187
VDD_188
VDD_189
VDD_190
VDD_191
VDD_192
VDD_193
VDD_194
VDD_195
VDD_196
VDD_197
VDD_198
VDD_199
VDD_200
VDD_201
VDD_202
VDD_203
VDD_204
VDD_205
VDD_206
VDD_207
VDD_208
VDD_209
VDD_210
VDD_211
VDD_212
VDD_213
VDD_214
VDD_215
VDD_216
VDD_217
VDD_218
VDD_357
VDD_358
VDD_359
VDD_360
VDD_361
VDD_362
VDD_363
VDD_364
VDD_365
VDD_366
VDD_367
VDD_368

N18E-G3-ES-A1_ FCBGA2228

VDD_219
VDD_220
VDD_221
VDD_222
VDD_223
VDD_224
VDD_225
VDD_226
VDD_227
VDD_228
VDD_229
VDD_230
VDD_231
VDD_232
VDD_233
VDD_234
VDD_235
VDD_236
VDD_237
VDD_238
VDD_239
VDD_240
VDD_241
VDD_242
VDD_243
VDD_244
VDD_245
VDD_246
VDD_247
VDD_248
VDD_249
VDD_250
VDD_251
VDD_252
VDD_253
VDD_254
VDD_255
VDD_321
VDD_322
VDD_323
VDD_324
VDD_325
VDD_326
VDD_327
VDD_328
VDD_329
VDD_330
VDD_331
VDD_332
VDD_333
VDD_334
VDD_335
VDD_336
VDD_337
VDD_338
VDD_339
VDD_340
VDD_341
VDD_342
VDD_343
VDD_344
VDD_345
VDD_346
VDD_347
VDD_348
VDD_349
VDD_350
VDD_351
VDD_352
VDD_353
VDD_354
VDD_355
VDD_356
VDD_369
VDD_370
VDD_371
VDD_372
VDD_373
VDD_374
VDD_375
VDD_376
VDD_377
VDD_378
VDD_379
VDD_380
VDD_381

VDD_SENSE

GND_SENSE

AP23
AP24
AP25
AP26
AP27
AP28
AP29
AP30
AP31
AP32
AP33
AP34
AP35
AP36
AP37
AP38
AP39
AP40
AR13
AR40
AT13
AT14
AT15
AT16
AT17
AT18
AT19
AT20
AT21
AT22
AT23
AT24
AT25
AT26
AT27
AT28
AT29
AY26
AY27
AY28
AY29
AY30
AY31
AY32
AY33
AY34
AY35
AY36
AY37
AY38
AY39
AY40
AY43
AY45
BA43
BA44
BA45
BA46
BA47
BB38
BB39
BB45
BB46
BB47
BB48
BC38
BC39
BC40
BC41
BC45
BC47
BC49
BD39
BE48
BE49
BE50
BE51
BE52
BF42
BF44
BF45
BF47
BF49
BF51
BG43
BG44

BK45

NVVDD_VDD_SENSE <91>

BL45

NVVDD_VSS_SENSE <91>

Sense pin connect to Power Mod ule
(VGA NCP81611MNTXGES)

BG45
BG46
BG47
BG48
BG49
BG50
BG51
BG52
BH44
BH45
BH47
BH48
BH49
BH50
BH51
BH52

BJ44
BJ45
BJ46
BJ47
BJ48
BJ49
BJ50
BJ51
BJ52
BK47
BK48
BK49
BK50
BK51
BK52
BL46
BL47
BL48
BL49
BL50
BL51

BL52
BM47
BM48
BM49
BM50
BM51

N13
N14
N15
N16
N17
N18
N19
N20
N21
N22
N23
N24
N25
N26
N27
N28
N29
N30
N31
N32
N33
N34
N35
N36
N37
N38
N39
N40

P13

P40
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22

UV1M

@

22/22 VDD_3/3

VDD_382
VDD_383
VDD_384
VDD_385
VDD_386
VDD_387
VDD_388
VDD_389
VDD_390
VDD_391
VDD_392
VDD_393
VDD_394
VDD_395
VDD_396
VDD_397
VDD_398
VDD_399
VDD_400
VDD_401
VDD_402
VDD_403
VDD_404
VDD_405
VDD_406
VDD_407
VDD_408
VDD_409
VDD_410
VDD_411
VDD_412
VDD_413
VDD_414
VDD_415
VDD_416
VDD_417
VDD_418
VDD_419
VDD_420
VDD_421
VDD_422
VDD_423
VDD_424
VDD_425
VDD_426
VDD_427
VDD_428
VDD_429
VDD_430
VDD_431
VDD_432
VDD_433
VDD_434
VDD_435
VDD_436
VDD_437
VDD_438
VDD_439
VDD_440
VDD_441
VDD_442
VDD_443
VDD_444
VDD_445
VDD_446
VDD_447
VDD_448
VDD_449
VDD_450
VDD_451
VDD_452
VDD_453
VDD_454
VDD_455
VDD_456
VDD_457
VDD_458
VDD_459
VDD_460
VDD_461
VDD_462
VDD_463
VDD_464

N18E-G3-ES-A1_ FCBGA2228

VDD_465
VDD_466
VDD_467
VDD_468
VDD_469
VDD_470
VDD_471
VDD_472
VDD_473
VDD_474
VDD_475
VDD_476
VDD_477
VDD_478
VDD_479
VDD_480
VDD_481
VDD_482
VDD_483
VDD_484
VDD_485
VDD_486
VDD_487
VDD_488
VDD_489
VDD_490
VDD_491
VDD_492
VDD_493
VDD_494
VDD_495
VDD_496
VDD_497
VDD_498
VDD_499
VDD_500
VDD_501
VDD_502
VDD_503
VDD_504
VDD_505
VDD_506
VDD_507
VDD_508
VDD_509
VDD_510
VDD_511
VDD_512
VDD_513
VDD_514
VDD_515
VDD_516
VDD_517
VDD_518
VDD_519
VDD_520
VDD_521
VDD_522
VDD_523
VDD_524
VDD_525
VDD_526
VDD_527
VDD_528
VDD_529
VDD_530
VDD_531
VDD_532
VDD_533
VDD_534
VDD_535
VDD_536
VDD_537
VDD_538
VDD_539
VDD_540
VDD_541
VDD_542
VDD_543
VDD_544

UV1L

@

R23
R24
R25
R26
R27
R28
R29
R30
R31
R32
R33
R34
R35
R36
R37
R38
R39
R40
T13
T40
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
U23
U24
U25
U26
U27
U28
U29
U30
U31
U32
U33
U34
U35
U36
U37
U38
U39
U40
V13
V40
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
W23
W24
W25
W26
W27
W28
W29
W30
W31
W32
W33
W34
W35
W36
W37
W38
W39
W40
Y13
Y40

AA10
AA11
AA42

AA43
AC10
AC11
AC42
AC43
AD10
AD11
AD42
AD43

AF10

AF43
AG10
AG11
AG42
AG43

AJ10

AJ11

AJ42

AJ43

AK10

AK11

AK42

AK43
AM42
AM43
AN43
AR42
AR43

R42
R43
U10
U11
U43

V10
V42
V43
Y10
Y11
Y42
Y43

19/22 FBVDDQ

FBVDDQ_01
FBVDDQ_02
FBVDDQ_03
FBVDDQ_04
FBVDDQ_05
FBVDDQ_06
FBVDDQ_07
FBVDDQ_08
FBVDDQ_09
FBVDDQ_10
FBVDDQ_11
FBVDDQ_12
FBVDDQ_13
FBVDDQ_14
FBVDDQ_15
FBVDDQ_16
FBVDDQ_17
FBVDDQ_18
FBVDDQ_19
FBVDDQ_20
FBVDDQ_21
FBVDDQ_22
FBVDDQ_23
FBVDDQ_24
FBVDDQ_25
FBVDDQ_26
FBVDDQ_27
FBVDDQ_28
FBVDDQ_29
FBVDDQ_30
FBVDDQ_31
FBVDDQ_76
FBVDDQ_77
FBVDDQ_78
FBVDDQ_79
FBVDDQ_80
FBVDDQ_81
FBVDDQ_82
FBVDDQ_83
FBVDDQ_84
FBVDDQ_85
FBVDDQ_86
FBVDDQ_87

FB_CAL_PD_VDD Q

FB_CAL_PU_GN D

FB_CAL_TERM_G ND

N18E-G3-ES-A1_ FCBGA2228

FBVDDQ_32
FBVDDQ_33
FBVDDQ_34
FBVDDQ_35
FBVDDQ_36
FBVDDQ_37
FBVDDQ_38
FBVDDQ_39
FBVDDQ_40
FBVDDQ_41
FBVDDQ_42
FBVDDQ_43
FBVDDQ_44
FBVDDQ_45
FBVDDQ_46
FBVDDQ_47
FBVDDQ_48
FBVDDQ_49
FBVDDQ_50
FBVDDQ_51
FBVDDQ_52
FBVDDQ_53
FBVDDQ_54
FBVDDQ_55
FBVDDQ_56
FBVDDQ_57
FBVDDQ_58
FBVDDQ_59
FBVDDQ_60
FBVDDQ_61
FBVDDQ_62
FBVDDQ_63
FBVDDQ_64
FBVDDQ_65
FBVDDQ_66
FBVDDQ_67
FBVDDQ_68
FBVDDQ_69
FBVDDQ_70
FBVDDQ_71
FBVDDQ_72
FBVDDQ_73
FBVDDQ_74
FBVDDQ_75

FBVDDQ_SENSE

FB_VREF

+1.35VS_VGA+1.35VS_VGA

AT43
K12
K14
K15
K17
K18
K20
K21
K23
K24
K26
K27
K29
K30
K32
K33
K35
K36
K38
K39
K41
L14
L15
L18
L20
L21
L23
L24
L26
L27
L30
L32
L33
L35
L36
L39
M10
M43
P10
P11
P42
P43
R10
R11

FB_VDDQ_SENSE_R

E52

FB_VREF

P45

FBCAL_VDDQ

R44

FBCAL_GND

P44

FBCAL_TERM

R45

FB_VREF

49.9_0402_1%

FP_FUSE<25>

RG89 2_0402_1%

RG90 40.2_0402_1%

RG91 40.2_0402_1%

RG92 40.2_0402_1%

12

RG93

1 2

1 2

1 2

1 2

1

CG90

3.9P_0402_50V8 C

2

+1V8_AON

CG80

1

2

+1.35VS_VGA

2.2U_0402_6.3V6M

12

RG88

10K_0201_5%

FB_VDDQ_SENSE <95>

UG3

6

VIN1

VOUT1

5

VIN2

VOUT2

4

EN

VSS

GS7616SC-R_ SOT363-6

+1V8_AON

Near GPU

1
2

3

1

CG84

4.7U_0402_6 .3V6M

2

FP_FUSE_GPU

1

CG79

2

1

CG85

4.7U_0402_6 .3V6M

2

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENTEXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THEINFORMATION IT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THEINFORMATION IT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THEINFORMATION IT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

5

4

3

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

2020/7/3 1 2020/7/3 1

2020/7/3 1 2020/7/3 1

2020/7/3 1 2020/7/3 1

2

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal El ectronics, Inc.

Compal El ectronics, Inc.

Compal El ectronics, Inc.

Title

Title

Title

N18E(6/9) Powe r

N18E(6/9) Powe r

N18E(6/9) Powe r

Size D ocument Number R ev

Size D ocument Number R ev

Size D ocument Number R ev

LA-J561P

LA-J561P

LA-J561P

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

29 1 00Wednesday, February 26, 202 0

29 1 00Wednesday, February 26, 202 0

29 1 00Wednesday, February 26, 202 0

0.3

0.3

0.3

5

UV1F

15/22 GND_1/3

A2

GND_001

A26

GND_002

A29

GND_003

A3

GND_004

A32

GND_005

A50

GND_006

A51

GND_007

D D

C C

B B

A A

AA49

GND_008

AA8

GND_009

AB10

GND_010

AB14

GND_011

AB15

GND_012

AB16

GND_013

AB17

GND_014

AB18

GND_015

AB19

GND_016

AB2

GND_017

AB20

GND_018

AB21

GND_019

AB22

GND_020

AB23

GND_021

AB24

GND_022

AB25

GND_023

AB26

GND_024

AB27

GND_025

AB28

GND_026

AB29

GND_027

AB30

GND_028

AB31

GND_029

AB32

GND_030

AB33

GND_031

AB34

GND_032

AB35

GND_033

AB36

GND_034

AB37

GND_035

AB38

GND_036

AB39

GND_037

AB4

GND_038

AB43

GND_039

AB45

GND_040

AB47

GND_041

AB49

GND_042

AB51

GND_043

AB6

GND_044

AB8

GND_045

AD14

GND_046

AD15

GND_047

AD16

GND_048

AD17

GND_049

AD18

GND_050

AD19

GND_051

AD20

GND_052

AD21

GND_053

AD22

GND_054

AD23

GND_055

AD24

GND_056

AD25

GND_057

AD26

GND_058

AD27

GND_059

AD28

GND_060

AD29

GND_061

AD30

GND_062

AD31

GND_063

AD32

GND_064

AD33

GND_065

AD34

GND_066

AD35

GND_067

AD36

GND_068

AD37

GND_069

AD38

GND_070

AD39

GND_071

AD44

GND_072

AE10

GND_073

AE2

GND_074

AE4

GND_075

AE43

GND_076

AE45

GND_077

AE47

GND_078

AE49

GND_079

AE51

GND_080

AE6

GND_081

AE8

GND_082

AF1

GND_083

AF19

GND_084

AF20

GND_085

AF21

GND_086

AF22

GND_087

AF23

GND_088

AF27

GND_089

AF28

GND_090

AF29

GND_091

AF35

GND_092

AF36

GND_093

AF37

GND_094

AF38

GND_095

AF39

GND_096

AF45

GND_097

AF5

GND_098

AG14

GND_099

AG15

GND_100

AG16

GND_101

AG17

GND_102

AG18

GND_103

AG24

GND_104

AG25

GND_105

AG26

GND_106

AG3

GND_107

AG30

GND_108

AG31

GND_109

AG32

GND_110

AG33

GND_111

AG34

GND_112

AG44

GND_113

AH10

GND_114

AH2

GND_115

AH4

GND_116

AH43

GND_117

AH45

GND_118

AH47

GND_119

AH49

GND_120

AH51

GND_121

@

GND_122
GND_123
GND_124
GND_125
GND_126
GND_127
GND_128
GND_129
GND_130
GND_131
GND_132
GND_133
GND_134
GND_135
GND_136
GND_137
GND_138
GND_139
GND_140
GND_141
GND_142
GND_143
GND_144
GND_145
GND_146
GND_147
GND_148
GND_149
GND_150
GND_151
GND_152
GND_153
GND_154
GND_155
GND_156
GND_157
GND_158
GND_159
GND_160
GND_161
GND_162
GND_163
GND_164
GND_165
GND_166
GND_167
GND_168
GND_169
GND_170
GND_171
GND_172
GND_173
GND_174
GND_175
GND_176
GND_177
GND_178
GND_179
GND_180
GND_181
GND_182
GND_183
GND_184
GND_185
GND_186
GND_187
GND_188
GND_189
GND_190
GND_191
GND_192
GND_193
GND_194
GND_195
GND_196
GND_197
GND_198
GND_199
GND_200
GND_201
GND_202
GND_203
GND_204
GND_205
GND_206
GND_207
GND_208
GND_209
GND_210
GND_211
GND_212
GND_213
GND_214
GND_215
GND_216
GND_217
GND_218
GND_219
GND_220
GND_221
GND_222
GND_223
GND_224
GND_225
GND_226
GND_227
GND_228
GND_229
GND_230
GND_231
GND_232
GND_233
GND_234
GND_235
GND_236
GND_237
GND_480

GND_F

N18E-G3-ES-A1_ FCBGA2228

4

UV1G

@

AH6
AH8
AJ14
AJ15
AJ16
AJ17
AJ18
AJ19
AJ2
AJ20
AJ21
AJ22
AJ23
AJ24
AJ25
AJ26
AJ27
AJ28
AJ29
AJ30
AJ31
AJ32
AJ33
AJ34
AJ35
AJ36
AJ37
AJ38
AJ39
AJ9
AK1
AK44
AK47
AL10
AL14
AL15
AL16
AL17
AL18
AL19
AL2
AL20
AL21
AL22
AL23
AL24
AL25
AL26
AL27
AL28
AL29
AL30
AL31
AL32
AL33
AL34
AL35
AL36
AL37
AL38
AL39
AL4
AL43
AL45
AL47
AL49
AL51
AL6
AL8
AM4
AM9
AN14
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
AN24
AN25
AN26
AN27
AN28
AN29
AN30
AN31
AN32
AN33
AN34
AN35
AN36
AN37
AN38
AN39
AN4
AN5
AN8
AP10
AP2
AP4
AP43
AP45
AP47
AP49
AP51
AP6
AP8
AR14
AR15
AR16
AR17
AR18
AR19
BL34
BC24

AR20
AR21
AR22
AR23
AR24
AR25
AR26
AR27
AR28
AR29
AR30
AR31
AR32
AR33
AR34
AR35
AR36
AR37
AR38
AR39

AR4

AR52

AR9
AT4

AT5
AT51
AT52

AT8

AU10
AU14
AU15
AU16
AU17
AU18
AU19

AU2

AU20
AU21
AU22
AU23
AU24
AU25
AU26
AU27
AU28
AU29
AU30
AU31
AU32
AU33
AU34
AU35
AU36
AU37
AU38
AU39

AU4

AU45
AU47
AU49
AU51

AU6

AU8

AV4
AV45

AV9

AW14
AW15
AW16
AW17
AW18
AW19
AW20
AW21
AW22
AW23
AW24
AW25
AW26
AW27
AW28
AW29
AW30
AW31
AW32
AW33
AW34
AW35
AW36
AW37
AW38
AW39

AW4

AW46

AW5

AW52

AW8
AY10

AY2

AY4
AY47
AY49
AY51

AY6

AY8

B1
B10
B13
B16
B19

B2
B22
B25
B28
B31
B34
B37
B40
B43
B46
B48

16/22 GND_2/3

GND_238
GND_239
GND_240
GND_241
GND_242
GND_243
GND_244
GND_245
GND_246
GND_247
GND_248
GND_249
GND_250
GND_251
GND_252
GND_253
GND_254
GND_255
GND_256
GND_257
GND_258
GND_259
GND_260
GND_261
GND_262
GND_263
GND_264
GND_265
GND_266
GND_267
GND_268
GND_269
GND_270
GND_271
GND_272
GND_273
GND_274
GND_275
GND_276
GND_277
GND_278
GND_279
GND_280
GND_281
GND_282
GND_283
GND_284
GND_285
GND_286
GND_287
GND_288
GND_289
GND_290
GND_291
GND_292
GND_293
GND_294
GND_295
GND_296
GND_297
GND_298
GND_299
GND_300
GND_301
GND_302
GND_303
GND_304
GND_305
GND_306
GND_307
GND_308
GND_309
GND_310
GND_311
GND_312
GND_313
GND_314
GND_315
GND_316
GND_317
GND_318
GND_319
GND_320
GND_321
GND_322
GND_323
GND_324
GND_325
GND_326
GND_327
GND_328
GND_329
GND_330
GND_331
GND_332
GND_333
GND_334
GND_335
GND_336
GND_337
GND_338
GND_339
GND_340
GND_341
GND_342
GND_343
GND_344
GND_345
GND_346
GND_347
GND_348
GND_349
GND_350
GND_351
GND_352
GND_353
GND_354
GND_355
GND_356
GND_357
GND_358

N18E-G3-ES-A1_ FCBGA2228

GND_361
GND_362
GND_363
GND_364
GND_365
GND_366
GND_367
GND_368
GND_369
GND_370
GND_371
GND_372
GND_373
GND_374
GND_375
GND_376
GND_377
GND_378
GND_379
GND_380
GND_381
GND_382
GND_383
GND_384
GND_385
GND_386
GND_387
GND_388
GND_389
GND_390
GND_391
GND_392
GND_393
GND_394
GND_395
GND_396
GND_397
GND_398
GND_399
GND_400
GND_401
GND_402
GND_403
GND_404
GND_405
GND_406
GND_407
GND_408
GND_409
GND_410
GND_411
GND_412
GND_413
GND_414
GND_415
GND_416
GND_417
GND_418
GND_419
GND_420
GND_421
GND_422
GND_423
GND_424
GND_425
GND_426
GND_427
GND_428
GND_429
GND_430
GND_431
GND_432
GND_433
GND_434
GND_435
GND_436
GND_437
GND_438
GND_439
GND_440
GND_441
GND_442
GND_443
GND_444
GND_445
GND_446
GND_447
GND_448
GND_449
GND_450
GND_451
GND_452
GND_453
GND_454
GND_455
GND_456
GND_457
GND_458
GND_459
GND_460
GND_461
GND_462
GND_463
GND_464
GND_465
GND_466
GND_467
GND_468
GND_469
GND_470
GND_471
GND_472
GND_473
GND_474
GND_475
GND_476
GND_477
GND_478
GND_479
GND_359
GND_360

3

UV1H

@

B52
B7
BA48
BA9
BB49
BC13
BC16
BC19
BC2
BC22
BC25
BC28
BC31
BC34
BC37
BC4
BC51
BC6
BC8
BD26
BD29
BD32
BD35
BD38
BD52
BE10
BE13
BE15
BE16
BE18
BE19
BE21
BE22
BE24
BE25
BE27
BE28
BE30
BE31
BE33
BE34
BE36
BE37
BE39
BE40
BF2
BF4
BF41
BF6
BG10
BG13
BG16
BG19
BG22
BG25
BG28
BG31
BG34
BG37
BG40
BG42
BG7
BH15
BH18
BH2
BH21
BH24
BH27
BH30
BH33
BH36
BH39
BH42
BH5
BJ10
BJ12
BJ13
BJ14
BJ15
BJ16
BJ17
BJ18
BJ19
BJ20
BJ21
BJ22
BJ23
BJ24
BJ25
BJ26
BJ27
BJ28
BJ29
BJ30
BJ31
BJ32
BJ33
BJ34
BJ35
BJ36
BJ37
BJ38
BJ39
BJ40
BJ41
BJ42
BJ43
BJ7
BK1
BL1
BL10
BL13
BL16
BL19
BL2
BL22
BL25
BL28
BL31
B5
B51

BL40
BL43

BL5
BL7
BM2
BM3

C1
C29
C33

C5
C51
C52
D10
D12
D13
D16
D19
D22
D24
D25
D28
D30
D31
D34
D37

D4
D40
D43
D46
D49

D7

E2

E4
E48

E5
E51

E8
F10
F13
F16
F17
F19
F21
F22
F25
F28
F31
F34
F35
F37
F40
F43
F44
F46
F52

F7

G2
G38

G4
G47
G49
G51

G6

H1
H10
H13
H16
H19
H22
H25
H28
H31
H34
H37
H40
H43

J1
J12
J17
J20
J38
J49
J52
K13
K16
K19

K2
K22
K25
K28
K31
K34
K37

K4
K40
K45
K47
K49
K51

K6

K8
M52

M6

N10

N2

N4
N43
N45
N47
N49

BL37

21/22 GND_3/3

GND_482
GND_483
GND_484
GND_485
GND_486
GND_487
GND_488
GND_489
GND_490
GND_491
GND_492
GND_493
GND_494
GND_495
GND_496
GND_497
GND_498
GND_499
GND_500
GND_501
GND_502
GND_503
GND_504
GND_505
GND_506
GND_507
GND_508
GND_509
GND_510
GND_511
GND_512
GND_513
GND_514
GND_515
GND_516
GND_517
GND_518
GND_519
GND_520
GND_521
GND_522
GND_523
GND_524
GND_525
GND_526
GND_527
GND_528
GND_529
GND_530
GND_531
GND_532
GND_533
GND_534
GND_535
GND_536
GND_537
GND_538
GND_539
GND_540
GND_541
GND_542
GND_543
GND_544
GND_545
GND_546
GND_547
GND_548
GND_549
GND_550
GND_551
GND_552
GND_553
GND_554
GND_555
GND_556
GND_557
GND_558
GND_559
GND_560
GND_561
GND_562
GND_563
GND_564
GND_565
GND_566
GND_567
GND_568
GND_569
GND_570
GND_571
GND_572
GND_573
GND_574
GND_575
GND_576
GND_577
GND_578
GND_579
GND_580
GND_581
GND_582
GND_583
GND_584
GND_585
GND_586
GND_587
GND_588
GND_589
GND_590
GND_591
GND_481

N18E-G3-ES-A1_ FCBGA2228

GND_592
GND_593
GND_594
GND_595
GND_596
GND_597
GND_598
GND_599
GND_600
GND_601
GND_602
GND_603
GND_604
GND_605
GND_606
GND_607
GND_608
GND_609
GND_610
GND_611
GND_612
GND_613
GND_614
GND_615
GND_616
GND_617
GND_618
GND_619
GND_620
GND_621
GND_622
GND_623
GND_624
GND_625
GND_626
GND_627
GND_628
GND_629
GND_630
GND_631
GND_632
GND_633
GND_634
GND_635
GND_636
GND_637
GND_638
GND_639
GND_640
GND_641
GND_642
GND_643
GND_644
GND_645
GND_646
GND_647
GND_648
GND_649
GND_650
GND_651
GND_652
GND_653
GND_654
GND_655
GND_656
GND_657
GND_658
GND_659
GND_660
GND_661
GND_662
GND_663
GND_664
GND_665
GND_666
GND_667
GND_668
GND_669
GND_670
GND_671
GND_672
GND_673
GND_674
GND_675
GND_676
GND_677
GND_678
GND_679
GND_680
GND_681
GND_682
GND_683
GND_684
GND_685
GND_686
GND_687
GND_688
GND_689
GND_690
GND_691
GND_692
GND_693
GND_726

2

N51
N6
N8
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P51
R49
R52
T10
T14
T15
T16
T17
T18
T19
T2
T20
T21
T22
T23
T24
T25
T26
T27
T28
T29
T30
T31
T32
T33
T34
T35
T36
T37
T38
T39
T4
T43
T45
T47
T49
T51
T6
T8
U7
U9
V14
V15
V16
V17
V18
V19
V20
V21
V22
V23
V24
V25
V26
V27
V28
V29
V30
V31
V32
V33
V34
V35
V36
V37
V38
V39
V49
V52
W10
W2
W4
W43
Y9

1

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENTEXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THEINFORMATION IT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THEINFORMATION IT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THEINFORMATION IT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

5

4

3

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

2020/7/3 1 2020/7/3 1

2020/7/3 1 2020/7/3 1

2020/7/3 1 2020/7/3 1

2

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal El ectronics, Inc.

Compal El ectronics, Inc.

Compal El ectronics, Inc.

Title

Title

Title

N18E(7/9) GND

N18E(7/9) GND

N18E(7/9) GND

Size D ocument Number R ev

Size D ocument Number R ev

Size D ocument Number R ev

LA-J561P

LA-J561P

LA-J561P

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

30 1 00Wednesday, February 26, 202 0

30 1 00Wednesday, February 26, 202 0

30 1 00Wednesday, February 26, 202 0

1.0

1.0

1.0