Lenovo KIUE0 Schematics

ZZZ1

DAZ

1 1

ZZZ2

12.1W _PCB_LA 5191P

Part Number = DA 80000EF10

ZZZ3

12.1W _PCB_LS 5191P

Part Number = DA 60000C410

ZZZ4

12.1W _PCB_LS 5192P

Part Number = DA 40000K110

ZZZ5

12.1W _PCB_LS 5193P

Part Number = DA 40000K010

ZZZ6

12.1W _PCB_LS 5194P

Part Number = DA 20000GH10

KIUE0

2 2

Schematics Document

Mobile Penryn PGA with Intel

3 3

4 4

Cantiga_GM45+ICH9-M core logic

REV:1.0

Security Class ification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

Deciphered Date

Custom

Date: Sheet of

Compal Electronics,Ltd.

Title

Cover Sheet

Size Document N umber Rev

KIUE0_LA-5191P

1 43Thursday, June 25 , 2009

1.0

Compal confidential

Model Name : KIUE0 File Name : LA-5191P

TP Lock,HDD,Bettery Charging,Power LED on MB CAPS ,NUM Lock,BT,Wlan,NOVO,Power LED on Sub-Brd

1 1

Mobile Penryn

uPGA-478 CPU

page4,5,6

Clock Gen.

SLG8SP556VTR ICS9LPRS387AKLFT

page16

H_A#(3..35) H_D#(0..63)

CRT Conn

page18

LCD Conn

page17

2 2

PCIeMini Card 3G

USB port 3

page 29

PCIeMini Card SSD

SATA port 1,5

page 29

SIM Card

page29

RJ45

page 24

3 3

PCIeMini Card Reserve

PCIeMini Card WLAN

Express Card

USB port 10

Express Card

PCIe port 4

RTL8111DL Giga

PCIe port 6

LVDS I/F

USB port 8

page 29

PCIe port 3

page 29

page 24

1.5V 2.5GHz(250MB/s)

SATA port 1,5

5V 1.5GHz(150MB/s)

1.5V 2.5GHz(250MB/s)

Intel Cantiga GMCH

uFCBGA 1329

page 7,8,9 ,10,11,12, 13

DMI

＊＊＊＊

USB

5V 480MHz

PCIe 1x

USB

5V 480MHz

PCIe 1x

Intel ICH9-M

mBGA-676

FSB 667/800/1066MHz

GM45

page 19,20,21,22

C-Link

USB

5V 480MHz

SATA port 0

5V 1.5GHz(150MB/s)

SATA port 4

5V 1.5GHz(150MB/s)

DDR3-800(1.5V) DDR3-1067(1.5V)

Dual Channel

page 23

Int. Camera

USB port 2

page 17

FP conn

USB port 9

page 33

page 23

USB Left

USB port 4

page 23

USB Right

＊＊＊＊

USB port 0

page 28

CardReader USB Conn

USB port 7 USB port 11

page 25

SATA HDD0

USB port 4

5V 480MHz

eSATA

DDR3-SO-DIMM X2

BANK 0, 1, 2, 3

UP TO 8G

BT conn

USB port 6

page 28

page 14,15

Audio Codec

ALC272-GR

page30

page28

page26

Int MIC Conn

HP Conn

page27

AMP-TPA6017

page27

2-CH SPK 1

.5W X 2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

MB Block Diagram

KIUE0_LA-5191P

2 43Wednesday, June 24, 2009

1.0

Sub-Board List

HD Audio

LPC BUS

3.3V/24.576MHZ/48MHZ

Finger Printer/B

Power/B

4 4

Switch/B

KB Light/B

ENE KB926D3

page31

Int.KBD

page32

SPI BUS

Touch Pad

page32

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/03/24 2008/04/

Compal Secret Data

Deciphered Date

SPI ROM

G-SENSOR

Voltage Rails

1 1

Power Plane Description

VIN

B+

+CPU_CORE

Adapter power supply (19V)

AC or battery power rail for power circuit.

Core voltage for CPU

+0.75VS 0.75V switched power rail for DDR terminator

+1.05VS

+1.5VS

+1.5V

+3VALW

1.05V switched power rail

1.5V switched power rail

1.8V power rail for DDR

3.3V always on power rail

S1 S3 S5

ON ON ON OFF

ON OFF

ON OFF OFF

ON OFF

ON ON

VL 3.3V always on power rail ONON

+3V_SB 3.3V power rail for LAN ON ON

+3V_LAN 3.3V power rail for LAN ON ON

+3V_WLAN 3.3V power rail for LAN ON ON

+3VS

+5VALW

2 2

+5VL 5V always on power rail ON ON

+5VS

+VSB VSB always on power rail ON ON

+RTCVCC RTC power

+GPU_CORE

+1.8VS

3.3V switched power rail

5V always on power rail

5V switched power rail

Core voltage for VGA chip

1.8V power rail for NB

OFF

ON ON

OFF

ONONON

OFF

ON ON

OFF

ON ON

OFF OFF+5V_SB 5V power rail for SB ON ON

OFFON

ONON

OFF

BTO Option Table

Function

description

explain

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

G3 LOWLOWLOWLOW

BTO

SIGNAL

CRT LAN

(Q)

(C)

SLP_S1# SLP_S3#

SLP_S4# SLP_S5#

HIGH HIGH HIGH HIGH

LOW

HIGH

LOWLOWLOW

LOW LOW LOW LOW

Finger printer

(F) (B)

HIGHHIGHHIGH

HIGH

BLUE TOOTH

3G SIM slot

(3)

Mini card

(D2)

External PCI Devices

EC SM Bus1 address

3 3

Device

EC KB926 D3

+3VALW

Smart Battery+3VALW CPU THM Sen

Address Address

EC SM Bus2 address

Device

PowerPower

EC KB926 D3

+3VALW

SMSC SMC1402

ICH9M SM Bus address

Device

Power

ICH9M

+3V_SB

Clock Generator

+3VS

(SLG8SP556V)

DDR DIMM0

+3VS

DDR DIMM1

4 4

+3VS

Express

Address

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/03/24 2008/04/

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

MB Notes List

KIUE0_LA-5191P

3 43Wednesday, June 24, 2009

1.0

ME@

JCPU1A

AA4 AB2 AA3

D22

K5 M3 N2

N3 P5 P2

P4 P1 R1 M1

K3 H2 K2

Y2 U5 R3

U4 Y5 U1 R4 T5

T3 W2 W5

V4 W3

J4 L5 L4

J3 L1

JCPU1A

A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]#

REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]#

A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# ADSTB[1]#

A20M# FERR# IGNNE#

STPCLK# LINT0 LINT1 SMI#

RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09]

Penryn

H_A#[3..16 ]7

D D

H_ADSTB #07

H_REQ#07 H_REQ#17 H_REQ#27 H_REQ#37 H_REQ#47

H_A#[17..3 5]7

C C

H_ADSTB #17

H_A20M#20

H_FERR#20

H_IGNNE#2 0

H_STPCL K#20 H_INTR20

H_NMI20 H_SMI#20

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_ADSTB #0

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 H_ADSTB #1

H_A20M# H_FERR# H_IGNNE#

H_STPCL K# H_INTR H_NMI H_SMI#

RSVD pins on the CPU should be left as NO CONNECT

B B

XDP Reserve for debug , Please close to CPU side

+3VS

XDP_DBR ESET#

XDP_TDI

XDP_TMS

XDP_TDO

A A

XDP_TRS T#

XDP_TCK

R6 1K_0402_5%@R6 1K_0402_5%@

1 2

R8 54.9_0402_1 %R8 54.9_0402_1%

1 2

R9 54.9_0402_1 %R9 54.9_0402_1%

1 2

R10 54.9_040 2_1%@R10 54.9 _0402_1%@

1 2

R11 54.9_040 2_1%R11 54.9_040 2_1%

1 2

R12 54.9_040 2_1%R12 54.9_040 2_1%

1 2

+1.05VS

ADDR GROUP_0

ADDR GROUP_1

THERMAL

ICH

THERMTRIP#

RESERVED

ADS# BNR# BPRI#

DEFER#

DRDY# DBSY#

BR0#

IERR#

INIT#

LOCK#

CONTROL

RESET#

RS[0]# RS[1]# RS[2]#

TRDY#

HIT#

HITM#

BPM[0]# BPM[1]# BPM[2]# BPM[3]#

PRDY# PREQ#

TCK

TDO TMS

TRST#

DBR#

XDP/ITP SIGNALS

PROCHOT#

THERMDA THERMDC

H CLK

BCLK[0] BCLK[1]

H_ADS#

H_BNR#

H_BPRI#

H_DEFER #

H_DRDY#

F21

H_DBSY#

H_BR0#

H_IERR#

D20

H_INIT#

H_LOCK#

H_RESET #

H_RS#0

H_RS#1

H_RS#2

H_TRDY#

H_HIT#

H_HITM#

XDP_BPM #0

AD4

XDP_BPM #1

AD3

XDP_BPM #2

AD1

XDP_BPM #3

AC4

XDP_BPM #4

AC2

XDP_BPM #5

AC1

XDP_TCK

AC5

XDP_TDI

AA6

TDI

XDP_TDO

AB3

XDP_TMS

AB5

XDP_TRS T#

AB6

XDP_DBR ESET#

C20

H_PROCH OT#

D21

H_THERM DA

A24

H_THERM DC

B25

H_THERM TRIP#

CLK_CPU _BCLK

A22

CLK_CPU _BCLK#

A21

H_THERMDA, H_THERMDC routing together, Trace width / Spacing = 10 / 10 mil

H_ADS# 7 H_BNR# 7

H_BPRI# 7

H_DEFER # 7

H_DRDY# 7 H_DBSY# 7

H_BR0# 7

H_INIT# 20

H_LOCK# 7

H_RESET # 7 H_RS#0 7 H_RS#1 7 H_RS#2 7 H_TRDY# 7

H_HIT# 7 H_HITM# 7

XDP_DBR ESET# 21

H_THERM TRIP# 8,20

CLK_CPU _BCLK 16 CLK_CPU _BCLK# 16

H_IERR#

H_PROCH OT#

R1 56_0402_5%R1 56_0402_5%

R2 68_0402_5%R2 68_0402_5%

1 2

Q36

Q36 2N7002_ SOT23

2N7002_ SOT23

EC_PROC HOT

+1.05VS

EC_PROC HOT 3 1

Hardware force mechanism for throttling

+3VS+3VS

R3 10K_040 2_5%

10K_040 2_5%

EC_SMB_ CK2

EC_SMB_ DA2

@R3

EC_SMB_ CK2 31

EC_SMB_ DA2 31

0.1U_040 2_16V4Z

1 2

C2 2200P_0 402_50V7KC2 2200P_0 402_50V7K

1 2

+3VS

R4 10K _0402_5%R4 10K _0402_5%

H_THERM DA

H_THERM DC

THERM#

VDD

THERM#

EMC1402 -1-ACZL-TR_MSOP 8

SMCLK

SMDATA

ALERT#

GND

Address:100_1100

FAN1 Conn

EN_FAN131

FAN +5VS DROOP

EN_FAN1

R5 100_040 2_5%R5 100_040 2_5%

+VCC_FA N1

1 2

FAN_SPE ED131

+5VS

C4 2200P_0 402_50V7K

2200P_0 402_50V7K

C3 10U _0805_10V4ZC3 10U _0805_10V4Z

1 2

VEN

VIN

VSET

G996P11 U_SO8

+3VS

R7 10K_040 2_5%

10K_040 2_5%

C7 1000P_0 402_50V7K

1000P_0 402_50V7K

GND GND GND GND

8 7 6 5

+VCC_FA N1

40mil

+5VS

D1 1SS355T E-17_SOD323-2

1SS355T E-17_SOD323-2

D2 BAS16_SOT2 3-3@D2 BAS16_S OT23-3@

1 2

C5 1U_ 0603_10V4ZC5 1U_ 0603_10V4Z

1 2

C6 0.1U _0402_16V4ZC6 0.1U _0402_16V4Z

1 2

1 2 3

4 5

JFAN1

1 2 3

GND

ME@

GND

E&T_380 1-F03N-01R

Security Class ification

2008/03/ 25 2008/04/

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/03/ 25 2008/04/

Compal Secret Data

Deciphered Date

Compal Electronics,Ltd.

Title

Penryn(1/3)

Size Document N umber Rev

Custom

KIUE0_LA-5191P

Date: Sheet of

4 43Wednesd ay, June 24, 20 09

1.0

ME@

JCPU1B

D D

C C

H_D#[0..15 ]7

H_DSTBN #07 H_DSTBP #07 H_DINV#07

H_D#[16..3 1]7

H_DSTBN #17 H_DSTBP #17 H_DINV#17

R14 1K_0402 _5%@R14 1K_0402 _5%@

1 2

R16 1K_0402 _5%@R16 1K_0402 _5%@

1 2

CPU_BSE L016 CPU_BSE L116 CPU_BSE L216

T1T1 T2T2 T3T3 T4T4 T5T5

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_DSTBN #0 H_DSTBP #0 H_DINV#0

H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_DSTBN #1 H_DSTBP #1 H_DINV#1

+CPU_GT LREF

TEST1 TEST2 TEST3 TEST4 TEST5 TEST6

TEST7 CPU_BSE L0 CPU_BSE L1 CPU_BSE L2

Trace Close CPU < 0.5'

Width=4 mil ,

B B

Spacing: 15mil (55Ohm)

E22 F24 E26

G22

F23

G25

E25 E23 K24

G24

H22 F26 K22 H23

H26 H25

N22 K25 P26 R23 L23

M24

L22

M23

P25 P23 P22 T24

R24

L25 T25

N25

L26 M26 N24

AD26

C23 D25 C24

AF26

AF1

A26

B22

B23 C21

J24 J23

J26

JCPU1B

D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]#

D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]#

GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 BSEL[0] BSEL[1] BSEL[2]

Penryn

layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs

+1.05VS

R19

R19 1K_0402 _1%

1K_0402 _1%

Layout note: Z0=55 ohm

0.5" max for GTLREF.

A A

+CPU_GT LREF

R20

R20 2K_0402 _1%

2K_0402 _1%

H_D#32

Y22

DATA GRP 0

MISC

DATA GRP 1

D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]#

DATA GRP 2DATA GRP 3

D[41]# D[42]# D[43]# D[44]# D[45]# D[46]#

D[47]# DSTBN[2]# DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]# DSTBN[3]# DSTBP[3]#

DINV[3]#

COMP[0] COMP[1] COMP[2] COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

PSI#

AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22

AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20

R26 U26 AA1 Y1

E5 B5 D24 D6 D7 AE6

COMP0 COMP1 COMP2 COMP3

H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_DSTBN #2 H_DSTBP #2 H_DINV#2

H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DSTBN #3 H_DSTBP #3 H_DINV#3

H_DPRST P# H_DPSLP # H_DPW R# H_PW RGOOD H_CPUSL P# H_PSI#

TRACE CLOSELY CPU < 0.5'

COMP0, COMP2 layout : Width 18mils and Space 25mils (27.4Ohms) COMP1, COMP3 layout : Width 5mils and Space 25mils (55Ohms)

FSB

BCLK BSEL2 BSEL1 BSEL0

533

667

800

133

166

200

0 0 1

1067 266 0 0 0

H_D#[32..4 7] 7

H_DSTBN #2 7 H_DSTBP #2 7 H_DINV#2 7

H_D#[48..6 3] 7

H_DSTBN #3 7 H_DSTBP #3 7

R13 27.4_040 2_1%R13 27.4_040 2_1%

1 2

R15 54.9_040 2_1%R15 54.9_040 2_1%

1 2

R17 27.4_040 2_1%R17 27.4_040 2_1%

1 2

R18 54.9_040 2_1%R18 54.9_040 2_1%

1 2

H_DINV#3 7

H_DPRST P# 8,20,40 H_DPSLP # 20 H_DPW R# 7 H_PW RGOOD 20 H_CPUSL P# 7

H_PSI# 40

110

1 00

JCPU1D

VSS[001]

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

A23

VSS[007]

AF2

VSS[008]

VSS[009]

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

VSS[017]

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

VSS[023]

C22

VSS[024]

C25

VSS[025]

VSS[026]

VSS[027]

VSS[028]

D11

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

VSS[035]

VSS[036]

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

VSS[044]

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

VSS[050]

F22

VSS[051]

F25

VSS[052]

VSS[053]

VSS[054]

G23

VSS[055]

G26

VSS[056]

VSS[057]

VSS[058]

H21

VSS[059]

H24

VSS[060]

VSS[061]

VSS[062]

J22

VSS[063]

J25

VSS[064]

VSS[065]

VSS[066]

K23

VSS[067]

K26

VSS[068]

VSS[069]

VSS[070]

L21

VSS[071]

L24

VSS[072]

VSS[073]

VSS[074]

M22

VSS[075]

M25

VSS[076]

VSS[077]

VSS[078]

N23

VSS[079]

N26

VSS[080] VSS[081]P3VSS[162]

Penryn

VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161]

VSS[163]

P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25

Close to CPU pin AD26 within 500mils.

Security Class ification

2007/10/ 15 2008/10/ 15

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/10/ 15 2008/10/ 15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document N umber Rev

Date: Sheet of

Compal Electronics, Inc.

Penryn (2/3)

KIUE0_LA-5191P

5 43Wednesd ay, June 24, 20 09

1.0

+CPU_CO RE +CPU_CO RE

D D

C C

B B

A10 A12 A13 A15 A17 A18 A20

B10 B12 B14 B15 B17 B18 B20

C10 C12 C13 C15 C17 C18

D10 D12 D14 D15 D17 D18

E10 E12 E13 E15 E17 E18 E20

F10 F12 F14 F15 F17 F18 F20 AA7

AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20

AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18

A7 A9

B7 B9

E7 E9

F7 F9

JCPU1C

VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067]

Penryn

VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100]

VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16]

VCCA[01] VCCA[02]

VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]

VCCSENSE

VSSSENSE

AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18

+1.05VS

AF20

G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21

B26 C26

AD6 AF5 AE5 AF4 AE3 AF3 AE2

AF7

AE7

C34

C34 330U_D2 _2VY_R7M

330U_D2 _2VY_R7M

CPU_VID0 40 CPU_VID1 40 CPU_VID2 40 CPU_VID3 40 CPU_VID4 40 CPU_VID5 40 CPU_VID6 40

VCCSENS E

VSSSENS E

NEAR PIN B26

20mils

C51

VCCSENS E 40

VSSSENS E 4 0

The trace width/space/other is 18/7/25.

Layout Note: Route VCCSENSE and VSSSENSE traces at

27.4 Ohms with 50 mil spacing. Place PU and PD within 1 inch of CPU. Length matched to within 25 mils.

+CPU_CO RE

330U_D2 _2VY_R7M

C15

C14

Place these capacitors on L1 (North side,Secondary Layer)

Place these capacitors on L1 (South side,Secondary Layer)

+1.5VS

Place these capacitors on L1

C52

0.01U_0402_16V7K

10U_0805_10V4Z

(South side,Secondary Layer)

Mid Frequence Decoupling

+CPU_CO RE

C15

330U_D2 _2VY_R7M

change highly to H1.9 for thermal type issue.

R21

R21 100_040 2_1%

100_040 2_1%

1 2

R22

R22 100_040 2_1%

100_040 2_1%

1 2

330U_D2 _2VY_R7M

VCCSENS E

VSSSENS E

C16

+CPU_CO RE

C17

330U_D2 _2VY_R7M

3/20 EVT

C18

10U_080 5_6.3V6M

C26

10U_080 5_6.3V6M

C35

10U_080 5_6.3V6M

C43

10U_080 5_6.3V6M

C19

10U_080 5_6.3V6M

C27

10U_080 5_6.3V6M

C36

10U_080 5_6.3V6M

C44

10U_080 5_6.3V6M

+1.05VS

Place these inside socket cavity on L8 (North side Secondary)

0.1U_040 2_10V6K

C20

10U_080 5_6.3V6M

C28

10U_080 5_6.3V6M

C37

10U_080 5_6.3V6M

C45

10U_080 5_6.3V6M

0.1U_040 2_10V6K

C21

10U_080 5_6.3V6M

C29

10U_080 5_6.3V6M

C38

10U_080 5_6.3V6M

C46

10U_080 5_6.3V6M

C10

0.1U_040 2_10V6K

C22

10U_080 5_6.3V6M

C30

10U_080 5_6.3V6M

C39

10U_080 5_6.3V6M

C47

10U_080 5_6.3V6M

C11

0.1U_040 2_10V6K

C40

10U_080 5_6.3V6M

C48

10U_080 5_6.3V6M

C23

10U_080 5_6.3V6M

C31

10U_080 5_6.3V6M

C12

0.1U_040 2_10V6K

C24

10U_080 5_6.3V6M

C32

10U_080 5_6.3V6M

C41

10U_080 5_6.3V6M

C49

10U_080 5_6.3V6M

C13

0.1U_040 2_10V6K

C25

10U_080 5_6.3V6M

C33

10U_080 5_6.3V6M

C42

10U_080 5_6.3V6M

C50

10U_080 5_6.3V6M

Close to CPU pin within 500mils.

A A

Security Class ification

2007/10/ 15 2008/10/ 15

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/10/ 15 2008/10/ 15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document N umber Rev

Custom

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

Penryn (3/3)

KIUE0_LA-5191P

6 43Wednesd ay, June 24, 20 09

1.0

D D

H_D#[0..63 ]5

C C

B B

H_RESET #4 H_CPUSL P#5

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

H_SW NG H_RCOMP

H_RESET # H_CPUSL P#

H_VREF

M11

N12

P13

N10

AD14

Y10 Y12 Y14

AA8

AA13

AA9 AA11 AD11 AD10 AD13 AE12

AE9

AA2

AD8

AA3

AD3

AD7 AE14

AF3

AC1

AE3

AC3 AE11

AE8

AG2 AD6

C12

E11

A11

B11

U3A

F8 E6

H6 H2 F6 D4 H3

J1 J2

J6 P2 L2 R2 N9 L6

J3 N2 R1 N5 N6

N8 L7

C5 E3

H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63

H_SWING H_RCOMP

H_CPURST# H_CPUSLP#

H_AVREF H_DVREF

CANTIGA ES _FCBGA1329

H_ADSTB#_0 H_ADSTB#_1

H_BREQ#

H_DEFER#

HOST

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_LOCK# H_TRDY#

H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3

H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3

H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3

H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4

H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8

H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35

H_ADS#

H_BNR#

H_BPRI#

H_HIT#

H_HITM#

H_RS#_0 H_RS#_1 H_RS#_2

A14 C15 F16 H13 C18 M16 J13 P16 R16 N17 M13 E17 P17 F17 G20 B19 J16 E20 H16 J20 L17 A17 B17 L16 C21 J17 H20 B18 K17 B20 F21 K21 L20

H12 B16 G17 A9 F11 G12 E9 B10 AH7 AH6 J11 F9 H9 E12 H11 C9

J8 L3 Y13 Y1

L10 M7 AA5 AE6

L9 M8 AA6 AE5

B15 K13 F13 B13 B14

B6 F12 C8

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

H_ADS# H_ADSTB #0 H_ADSTB #1 H_BNR# H_BPRI# H_BR0# H_DEFER # H_DBSY# CLK_MCH _BCLK CLK_MCH _BCLK# H_DPW R# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY#

H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3

H_DSTBN #0 H_DSTBN #1 H_DSTBN #2 H_DSTBN #3

H_DSTBP #0 H_DSTBP #1 H_DSTBP #2 H_DSTBP #3

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_RS#0 H_RS#1 H_RS#2

H_A#[3..35 ] 4

H_ADS# 4 H_ADSTB #0 4 H_ADSTB #1 4 H_BNR# 4 H_BPRI# 4 H_BR0# 4 H_DEFER # 4 H_DBSY# 4 CLK_MCH _BCLK 16 CLK_MCH _BCLK# 16 H_DPW R# 5 H_DRDY# 4 H_HIT# 4 H_HITM# 4 H_LOCK# 4 H_TRDY# 4

H_DINV#0 5 H_DINV#1 5 H_DINV#2 5 H_DINV#3 5

H_DSTBN #0 5 H_DSTBN #1 5 H_DSTBN #2 5 H_DSTBN #3 5

H_DSTBP #0 5 H_DSTBP #1 5 H_DSTBP #2 5 H_DSTBP #3 5

H_REQ#0 4 H_REQ#1 4 H_REQ#2 4 H_REQ#3 4 H_REQ#4 4

H_RS#0 4 H_RS#1 4 H_RS#2 4

Layout Note: H_RCOMP / H_VREF / H_SWNG trace width and spacing is 10/20

R23

R23 1K_0402 _1%

1K_0402 _1%

R25

R25 2K_0402 _1%

2K_0402 _1%

C53

0.1U_040 2_16V4Z

within 100 mils from NB

H_RCOMP H_SW NGH_VREF

R26

24.9_040 2_1%

+1.05VS+1.05VS

R24

R24 221_060 3_1%

221_060 3_1%

R27

R27 100_040 2_1%

100_040 2_1%

Near B3 pin

C54

0.1U_040 2_16V4Z

A A

Security Class ification

2007/10/ 15 2008/10/ 15

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/10/ 15 2008/10/ 15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document N umber Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Cantiga GMCH(1/6)-GTL

KIUE0_LA-5191P

7 43Wednesd ay, June 24, 20 09

1.0

Strap Pin Table

011 = FSB667

CFG[2:0]

Internal pull-up

CFG5

Internal pull-up

CFG6

D D

Internal pull-up

CFG7

Internal pull-up

CFG9

Internal pull-up

CFG10

CFG[13:12]

Internal pull-up

CFG16

Internal pull-do wn

CFG19

CFG20

Internal pull-do wn

(PCIE/SDVO select)

C C

B B

+1.05VS

R35

54.9_0402_1%

MCH_TSATN# MCH_TSATN_EC#

ICH_POK21

VGATE21,40

PLT_RST#19,24,29

3 1

Q1 MMBT3904_SOT23-3

MMBT3904_SOT23-3

Layout Note: V_DDR_MCH_REF trace width and spacing is 20/20.

A A

CLOSE TO PIN.AV21

+DDR_MCH_REF

010 = FSB800 000 = FSB1067

0 = DMI x 2 1 = DMI x 4

0 = iTPM Host Interface is enabled

1 = iTPM Host Interface is Disabled

0 = Intel Management Engine Crypto Transport Layer Security (TLS) cipher suite with no confidentiality

1 = Intel Management Engine Crypto TLS cipher suite with confidentiality

0 = Lane Reversal Enable 1 = Normal Operation (Default)

0 = PCIe Loopback Enable 1 = Disable*(Default)

01 = All Z Mode Enabled 00 = Reserved 10 = XOR Mode Enabled 11 = Normal Operation

0 = Dynamic ODT Disabled 1 = Dynamic ODT Enabled

0 = Normal Operation 1 = DMI Lane Reversal Enable

(Default)

can support disble by SW.

(Default)

0 = Only PCIE or [SDVO/DP/HDMI] is operational.

1 = PCIE/[SDVO/DP/HDMI] are operating simu.

+3VS

R33

R33 1K_0402_5%

1K_0402_5%

R47

R47 10K_0402_5%

10K_0402_5%

R51 0_0402_5%R51 0_0402_5%

R53 0_0402_5%@R53 0_0402_5%@

R54 100_0402_5%R54 100_0402_5%

1 2

C61

0.1U_0402_16V4Z

R36

R36 1K_0402_5%

1K_0402_5%

R48

R48 10K_0402_5%

10K_0402_5%

+1.5V

PM_EXTTS#0 PM_EXTTS#1

R58

R58 10K_0402_5%

10K_0402_5%

R64

R64 10K_0402_5%

10K_0402_5%

+3VS

PM_POK_R

PLT_RST#_R

R38 2.21K_0402_1%@R38 2.21K_0402_1 %@ R39 2.21K_0402_1%@R39 2.21K_0402_1 %@ R40 2.21K_0402_1%@R40 2.21K_0402_1 %@

R41 2.21K_0402_1%@R41 2.21K_0402_1 %@ R42 2.21K_0402_1%@R42 2.21K_0402_1 %@

R44 2.21K_0402_1%@R44 2.21K_0402_1 %@ R45 2.21K_0402_1%@R45 2.21K_0402_1 %@

R46 2.21K_0402_1%@R46 2.21K_0402_1 %@

R49 4.02K_0402_1%@R49 4.02K_0402_1 %@ R50 4.02K_0402_1%@R50 4.02K_0402_1 %@

MCH_CLKSEL016 MCH_CLKSEL116 MCH_CLKSEL216

1 2 1 2 1 2

1 2 1 2

1 2

1 2 1 2

PM_BMBUSY#21

H_DPRSTP#5,20,40

PM_EXTTS#014,15

H_THERMTRIP#4,20

DPRSLPVR21,40

(Default)

MCH_CLKSEL0 MCH_CLKSEL1 MCH_CLKSEL2

MCH_CFG_5 MCH_CFG_6 MCH_CFG_7

MCH_CFG_9 MCH_CFG_10

MCH_CFG_12 MCH_CFG_13

MCH_CFG_16

MCH_CFG_19 MCH_CFG_20

PM_BMBUSY# H_DPRSTP# PM_EXTTS#0 PM_EXTTS#1 PM_POK_R PLT_RST#_R H_THERMTRIP# DPRSLPVR

M36 N36 R33

AH9 AH10 AH12 AH13

AL34 AK34 AN35 AM35

AY21

BG23

BF23 BH18

BF18

R25

C25 N24 M24

C23 C24 N21

R20 M20

H21

R28

R29

N33

AT40

AT11

R32

BG48

BF48 BD48 BC48 BH47 BG47 BE47 BH46

BF46 BG45 BH44 BH43

BH6 BH5 BG4 BH3 BF3 BH2 BG2 BE2 BG1 BF1 BD1 BC1

U3B

T33

K12

T24

B31

T25

P25 P20 P24

E21

P21 T21

L21

P29

T28

P32

T20

A47

M_CLK_DDR0

AP24

RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14

RSVD15 RSVD16 RSVD17

RSVD20

RSVD22 RSVD23 RSVD24 RSVD25

CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20

PM_SYNC# PM_DPRSTP# PM_EXT_TS#_0 PM_EXT_TS#_1 PWROK RSTIN# THERMTRIP# DPRSLPVR

NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16 NC_17 NC_18 NC_19 NC_20 NC_21 NC_22 NC_23 NC_24 NC_25 NC_26

CANTIGA ES_FCBGA1329

RSVD CFG PM NC

DDR CLK/ CONTROL/ COMPENSATIONHDA

CLKDMIGRAPHICS VIDMEMISC

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SA_CK_0 SA_CK_1 SB_CK_0 SB_CK_1

SA_CK#_0 SA_CK#_1 SB_CK#_0 SB_CK#_1

SA_CKE_0 SA_CKE_1 SB_CKE_0 SB_CKE_1

SA_CS#_0 SA_CS#_1 SB_CS#_0 SB_CS#_1

SA_ODT_0 SA_ODT_1

SB_ODT_O

SB_ODT_1

SM_RCOMP

SM_RCOMP#

SM_RCOMP_VOH

SM_RCOMP_VOL

SM_VREF

SM_PWROK

SM_REXT

SM_DRAMRST#

DPLL_REF_CLK

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

PEG_CLK

PEG_CLK#

DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3

DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3

DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3

DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3

GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4

GFX_VR_EN

CL_CLK

CL_DATA

CL_PWROK

CL_RST# CL_VREF

DDPC_CTRLCLK

DDPC_CTRLDATA

SDVO_CTRLCLK

SDVO_CTRLDATA

CLKREQ#

ICH_SYNC#

TSATN#

HDA_BCLK HDA_RST#

HDA_SDI

HDA_SDO

HDA_SYNC

2007/10/15 2008/10/15

M_CLK_DDR1

AT21

M_CLK_DDR2

AV24

M_CLK_DDR3

AU20

M_CLK_DDR#0

AR24

M_CLK_DDR#1

AR21

M_CLK_DDR#2

AU24

M_CLK_DDR#3

AV20

DDR_CKE0_DIMMA

BC28

DDR_CKE1_DIMMA

AY28

DDR_CKE2_DIMMB

AY36

DDR_CKE3_DIMMB

BB36

DDR_CS0_DIMMA#

BA17

DDR_CS1_DIMMA#

AY16

DDR_CS2_DIMMB#

AV16

DDR_CS3_DIMMB#

AR13

M_ODT0

BD17

M_ODT1

AY17

M_ODT2

BF15

M_ODT3

AY13

SMRCOMP

BG22

SMRCOMP#

BH21

SMRCOMP_VOH

BF28

SMRCOMP_VOL

BH28

+DDR_MCH_REF

AV42

SM_PWROK

AR36

SM_REXT

BF17

SM_DRAMRST#

BC36

CLK_MCH_DREFCLK

B38

CLK_MCH_DREFCLK#

A38

MCH_CLKDREFSSC

E41

MCH_CLKDREFSSC#

F41

CLK_MCH_3GPLL

F43

CLK_MCH_3GPLL#

E43

DMI_TXN0

AE41

DMI_TXN1

AE37

DMI_TXN2

AE47

DMI_TXN3

AH39

DMI_TXP0

AE40

DMI_TXP1

AE38

DMI_TXP2

AE48

DMI_TXP3

AH40

DMI_RXN0

AE35

DMI_RXN1

AE43

DMI_RXN2

AE46

DMI_RXN3

AH42

DMI_RXP0

AD35

DMI_RXP1

AE44

DMI_RXP2

AF46

DMI_RXP3

AH43

For independent Power Rail : connect to PWM CORE VID For Common Power Rail : left it No Connect

B33 B32 G33 F33 E33

C34

For AMT function

CL_CLK0

AH37

CL_DATA0

AH36

CL_PWROK

AN36

CL_RST#

AJ35

CL_VREF

AH34

N28

DP_DATA

M28

SDVO_SCLK

G36 E36

MCH_CLKREQ#

K36

MCH_ICH_SYNC#

H36

MCH_TSATN#

B12

B28 B30 B29 C29 A28

R57 56_0402_5%R57 56_0402_5%

Notice: Please check HDA power rail to select HDA controller.

Compal Secret Data

Deciphered Date

M_CLK_DDR0 14 M_CLK_DDR1 14 M_CLK_DDR2 15 M_CLK_DDR3 15

M_CLK_DDR#0 14 M_CLK_DDR#1 14 M_CLK_DDR#2 15 M_CLK_DDR#3 15

DDR_CKE0_DIMMA 14 DDR_CKE1_DIMMA 14 DDR_CKE2_DIMMB 15 DDR_CKE3_DIMMB 15

DDR_CS0_DIMMA# 14 DDR_CS1_DIMMA# 14 DDR_CS2_DIMMB# 15 DDR_CS3_DIMMB# 15

M_ODT0 14 M_ODT1 14 M_ODT2 15 M_ODT3 15

1 2

R29 80.6_0402_1%R29 80.6_0402_1%

SM_DRAMRST# 14,15

CL_CLK0 21 CL_DATA0 21

M_PWROK 21 CL_RST# 21

MCH_CLKREQ# 16 MCH_ICH_SYNC# 21

1 2

20mil

R30 0_0402_5%R30 0_0402_5%

1 2

CLK_MCH_DREFCLK 16

CLK_MCH_DREFCLK# 16

MCH_CLKDREFSSC 16

MCH_CLKDREFSSC# 16

CLK_MCH_3GPLL 16 CLK_MCH_3GPLL# 16

DMI_TXN0 21 DMI_TXN1 21 DMI_TXN2 21 DMI_TXN3 21

DMI_TXP0 21 DMI_TXP1 21 DMI_TXP2 21 DMI_TXP3 21

DMI_RXN0 21 DMI_RXN1 21 DMI_RXN2 21 DMI_RXN3 21

DMI_RXP0 21 DMI_RXP1 21 DMI_RXP2 21 DMI_RXP3 21

(Internal pull-down)

+1.05VS

For DDR3 : 1.5V power rail For DDR2 : 1.8V power rail

+1.5V

R28

80.6_0402_1%

For Crestline: 20ohm For Calero: 80.6ohm For Cantiga: 80.6ohm

1.5V_PGOOD 3 9

R31 10K_0402_5%@R31 10K_0402_5%@

1 2

R32 499_0402_1%R32 499_0402_1%

1 2

SM_DRAMRST# is only for DDR3. DDR2 left it No Connect

SMRCOMP_VOH

SMRCOMP_VOL

+1.05VS

R52

R52 1K_0402_1%

1K_0402_1%

R55

C59

0.1U_0402_16V4Z

R55 499_0402_1%

499_0402_1%

Strap Pin Table

SDVO_CTRLDATA

0 = SDVO interface disabled 1 = SDVO interface enabled

0 = Digital display (iHDMI/DP) interface disabled 1 = Digital display (iHDMI/DP) interface enabled

Title

Size Document Number Rev

Custom

KIUE0_LA-5191P

Date: Sheet of

Date: Sheet

KIUE0_LA-5191P

+1.5V

R34

R34 1K_0402_1%

1K_0402_1%

C55

0.01U_0402_25V7K

C57

0.01U_0402_25V7K

Compal Electronics, Inc.

Cantiga(2/7)-DMI/DDR/STRP

SDVO_SCLK

C56

2.2U_0603_6.3V4Z

C58

2.2U_0603_6.3V4Z

(Default)

R56

@R56

2.2K_0402_5%

8 43Wednesday, June 24, 2009

R37

3.01K_0402_1%

R43

R43 1K_0402_1%

1K_0402_1%

(Default)DDPC_CTRLDATA

+3VS

1.0

D D

U3D

DDR_A_D [0..63]14 DDR_A_B S[0..2] 14

C C

B B

DDR_A_D 0 DDR_A_D 1 DDR_A_D 2 DDR_A_D 3 DDR_A_D 4 DDR_A_D 5 DDR_A_D 6 DDR_A_D 7 DDR_A_D 8 DDR_A_D 9 DDR_A_D 10 DDR_A_D 11 DDR_A_D 12 DDR_A_D 13 DDR_A_D 14 DDR_A_D 15 DDR_A_D 16 DDR_A_D 17 DDR_A_D 18 DDR_A_D 19 DDR_A_D 20 DDR_A_D 21 DDR_A_D 22 DDR_A_D 23 DDR_A_D 24 DDR_A_D 25 DDR_A_D 26 DDR_A_D 27 DDR_A_D 28 DDR_A_D 29 DDR_A_D 30 DDR_A_D 31 DDR_A_D 32 DDR_A_D 33 DDR_A_D QS#0 DDR_A_D 34 DDR_A_D 35 DDR_A_D 36 DDR_A_D 37 DDR_A_D 38 DDR_A_D 39 DDR_A_D 40 DDR_A_D 41 DDR_A_D 42 DDR_A_D 43 DDR_A_D 44 DDR_A_D 45 DDR_A_D 46 DDR_A_D 47 DDR_A_D 48 DDR_A_D 49 DDR_A_D 50 DDR_A_D 51 DDR_A_D 52 DDR_A_D 53 DDR_A_D 54 DDR_A_D 55 DDR_A_D 56 DDR_A_D 57 DDR_A_D 58 DDR_A_D 59 DDR_A_D 60 DDR_A_D 61 DDR_A_D 62 DDR_A_D 63

AJ38 AJ41

AN38

AM38

AJ36

AJ40 AM44 AM42

AN43 AN44 AU40 AT38 AN41 AN39 AU44 AU42 AV39 AY44 BA40 BD43 AV41 AY43 BB41 BC40 AY37 BD38 AV37 AT36 AY38 BB38 AV36

AW36

BD13 AU11 BC11 BA12 AU13 AV13 BD12 BC12

BB9 BA9

AU10

AV9

BA11

BD9 AY8 BA6 AV5 AV7 AT9 AN8 AU5 AU6 AT5

AN10

AM11

AM5

AJ9 AJ8

AN12

AM13

AJ11

AJ12

U3D

SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63

CANTIGA ES _FCBGA1329

DDR_A_B S0

BD21

SA_BS_0 SA_BS_1 SA_BS_2

SA_RAS# SA_CAS#

SA_WE#

SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7

SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7

SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7

SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3

DDR SYSTEM MEMORY A

SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8

SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14

BG18 AT25

BB20 BD20 AY20

AM37 AT41 AY41 AU39 BB12 AY6 AT7 AJ5

AJ44 AT44 BA43 BC37 AW12 BC8 AU8 AM7

AJ43 AT43 BA44 BD37 AY12 BD8 AU9 AM8

BA21 BC24 BG24 BH24 BG25 BA24 BD24 BG27 BF25 AW24 BC21 BG26 BH26 BH17 AY25

DDR_A_B S1 DDR_A_B S2

DDR_A_R AS# DDR_A_C AS# DDR_A_W E#

DDR_A_D M0 DDR_A_D M1 DDR_A_D M2 DDR_A_D M3 DDR_A_D M4 DDR_A_D M5 DDR_A_D M6 DDR_A_D M7

DDR_A_D QS0 DDR_A_D QS1 DDR_A_D QS2 DDR_A_D QS3 DDR_A_D QS4 DDR_A_D QS5 DDR_A_D QS6 DDR_A_D QS7

DDR_A_D QS#1

DDR_A_D QS#2 DDR_A_D QS#3 DDR_A_D QS#4 DDR_A_D QS#5 DDR_A_D QS#6 DDR_A_D QS#7

DDR_A_M A0

DDR_A_M A1

DDR_A_M A2

DDR_A_M A3

DDR_A_M A4

DDR_A_M A5

DDR_A_M A6

DDR_A_M A7

DDR_A_M A8

DDR_A_M A9

DDR_A_M A10

DDR_A_M A11

DDR_A_M A12

DDR_A_M A13

DDR_A_M A14

DDR_A_R AS# 14 DDR_A_C AS# 14 DDR_A_W E# 14

DDR_A_D M[0..7] 14

DDR_A_D QS[0..7] 14

DDR_A_D QS#[0..7] 14

DDR_A_M A[0..14] 1 4

DDR_B_D [0..63]15 DDR_B_B S[0..2] 15

DDR_B_D 0 DDR_B_D 1 DDR_B_D 2 DDR_B_D 3 DDR_B_D 4 DDR_B_D 5 DDR_B_D 6 DDR_B_D 7 DDR_B_D 8 DDR_B_D 9 DDR_B_D 10 DDR_B_D 11 DDR_B_D 12 DDR_B_D 13 DDR_B_D 14 DDR_B_D 15 DDR_B_D 16 DDR_B_D 17 DDR_B_D 18 DDR_B_D 19 DDR_B_D 20 DDR_B_D 21 DDR_B_D 22 DDR_B_D 23 DDR_B_D 24 DDR_B_D 25 DDR_B_D 26 DDR_B_D 27 DDR_B_D 28 DDR_B_D 29 DDR_B_D 30 DDR_B_D 31 DDR_B_D 32 DDR_B_D 33 DDR_B_D 34 DDR_B_D 35 DDR_B_D 36 DDR_B_D 37 DDR_B_D 38 DDR_B_D 39 DDR_B_D 40 DDR_B_D 41 DDR_B_D 42 DDR_B_D 43 DDR_B_D 44 DDR_B_D 45 DDR_B_D 46 DDR_B_D 47 DDR_B_D 48 DDR_B_D 49 DDR_B_D 50 DDR_B_D 51 DDR_B_D 52 DDR_B_D 53 DDR_B_D 54 DDR_B_D 55 DDR_B_D 56 DDR_B_D 57 DDR_B_D 58 DDR_B_D 59 DDR_B_D 60 DDR_B_D 61 DDR_B_D 62 DDR_B_D 63

AK47 AH46 AP47 AP46

AJ46

AJ48 AM48 AP48 AU47 AU46 BA48 AY48

AT47 AR47 BA47 BC47 BC46 BC44 BG43

BF43 BE45 BC41

BF40

BF41 BG38

BF38 BH35 BG35 BH40 BG39 BG34 BH34 BH14 BG12 BH11

BG8

BH12

BF11

BF8

BG7

BC5 BC6 AY3 AY1 BF6 BF5 BA1 BD3 AV2 AU3 AR3 AN2 AY2 AV1 AP3 AR1 AL1 AL2 AJ1

AH1 AM2 AM3

AH3

AJ3

U3E

SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63

CANTIGA ES _FCBGA1329

DDR_B_BS0

BC16

SB_BS_0 SB_BS_1 SB_BS_2

SB_RAS# SB_CAS#

SB_WE#

SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7

SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7

SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7

SB_MA_0 SB_MA_1 SB_MA_2

DDR SYSTEM MEMORY B

SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8

SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14

BB17 BB33

AU17 BG16 BF14

AM47 AY47 BD40 BF35 BG11 BA3 AP1 AK2

AL47 AV48 BG41 BG37 BH9 BB2 AU1 AN6

AL46 AV47 BH41 BH37 BG9 BC2 AT2 AN5

AV17 BA25 BC25 AU25 AW25 BB28 AU28 AW28 AT33 BD33 BB16 AW33 AY33 BH15 AU33

DDR_B_B S1 DDR_B_B S2

DDR_B_R AS# DDR_B_C AS# DDR_B_W E#

DDR_B_D M0 DDR_B_D M1 DDR_B_D M2 DDR_B_D M3 DDR_B_D M4 DDR_B_D M5 DDR_B_D M6 DDR_B_D M7

DDR_B_D QS0 DDR_B_D QS1 DDR_B_D QS2 DDR_B_D QS3 DDR_B_D QS4 DDR_B_D QS5 DDR_B_D QS6 DDR_B_D QS7

DDR_B_D QS#0 DDR_B_D QS#1 DDR_B_D QS#2 DDR_B_D QS#3 DDR_B_D QS#4 DDR_B_D QS#5 DDR_B_D QS#6 DDR_B_D QS#7

DDR_B_M A0 DDR_B_M A1 DDR_B_M A2 DDR_B_M A3 DDR_B_M A4 DDR_B_M A5 DDR_B_M A6 DDR_B_M A7 DDR_B_M A8 DDR_B_M A9 DDR_B_M A10 DDR_B_M A11 DDR_B_M A12 DDR_B_M A13 DDR_B_M A14

DDR_B_R AS# 15 DDR_B_C AS# 15 DDR_B_W E# 15

DDR_B_D M[0..7] 15

DDR_B_D QS[0..7] 15

DDR_B_D QS#[0..7] 15

DDR_B_M A[0..14] 1 5

A A

Security Class ification

2007/10/ 15 2008/10/ 15

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/10/ 15 2008/10/ 15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document N umber Rev

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

Cantiga GMCH (2/6)-DDRII

KIUE0_LA-5191P

9 43Wednesd ay, June 24, 20 09

1.0

Place the resistor within 500mils

+3VS

R65 10K_040 2_5%R65 10K_040 2_5%

D D

C C

1 2

R66 10K_040 2_5%R66 10K_040 2_5%

1 2

R69 2.2K_040 2_5%R69 2.2K_04 02_5%

1 2

R70 2.2K_040 2_5%R70 2.2K_04 02_5%

For Cantiga:2.37kohm For Crestline:2.4kohm For Calero: 1.5Kohm

Note: All LVDS data signals/and it's compliments should be routed Differentially

L_CTRL_ CLK

L_CTRL_ DATA

LVDS_SC L

LVDS_SD A

Layout Note: Place 150 Ω termination

B B

resistors close to GMCH

R71 150_040 2_1%R71 150_040 2_1%

1 2

R72 150_040 2_1%R72 150_040 2_1%

1 2

R73 150_040 2_1%R73 150_040 2_1%

1 2

GMCH_CR T_HSYNC18

GMCH_CR T_VSYNC18

change R74,R75 from 33ohm to 30ohm by checklist2.0 & CRB1.0 05/08/08

GMCH_CR T_R GMCH_CR T_G GMCH_CR T_B

EVT 0324 Reverse GMCH DPST

DPST_PW M17 GMCH_EN BKL1 7

LVDS_SC L1 7 LVDS_SD A17 GM_ENVD D17

LVDS_AC LK#17 LVDS_AC LK17

LVDS_A0 #17 LVDS_A1 #17 LVDS_A2 #17

LVDS_A017 LVDS_A117 LVDS_A217

R481 75_04 02_5%R481 75_04 02_5%

1 2

R482 75_04 02_5%R482 75_04 02_5%

1 2

R483 75_04 02_5%R483 75_04 02_5%

1 2

GMCH_CR T_B1 8

GMCH_CR T_G18

GMCH_CR T_R18

GMCH_CR T_CLK18 GMCH_CR T_DATA18

R74 30_0402_1%R74 30_0402_1%

R75 30_0402_1%R75 30_0402_1%

DPST_PW M GMCH_EN BKL L_CTRL_ CLK L_CTRL_ DATA LVDS_SC L LVDS_SD A GM_ENVD D

1 2

R68 2.37K_04 02_1%R68 2.37K _0402_1%

LVDS_AC LK# LVDS_AC LK

LVDS_A0 # LVDS_A1 # LVDS_A2 #

LVDS_A0 LVDS_A1 LVDS_A2

TVA_DAC TVB_DAC TVC_DAC

GMCH_CR T_B

GMCH_CR T_G

GMCH_CR T_R

GMCH_CR T_CLK GMCH_CR T_DATA CRT_HSYNC _R

20mil

CRT_VSYNC _R

L32 G32 M32 M33

K33

J33

M29

C44

B43

E37

E38

C41

C40

B37

A37

H47

E46 G40

A40

H48

D45

F40

B40

A41

H38 G37

J37

B42 G38

F37

K37

F25

H25

K25

H24

C31

E32

E28

G28

J28

G29

H32

J32 J29

E29

L29

R78

1.02K_04 02_1%

U3C

L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK L_CTRL_DATA L_DDC_CLK L_DDC_DATA L_VDD_EN

LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL

LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK

LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2 LVDSA_DATA#_3

LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2 LVDSA_DATA_3

LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2 LVDSB_DATA#_3

LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2 LVDSB_DATA_3

TVA_DAC TVB_DAC TVC_DAC

TV_RTN

TV_DCONSEL_0 TV_DCONSEL_1

CRT_BLUE

CRT_GREEN

CRT_RED

CRT_IRTN

CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF

CRT_VSYNC

CANTIGA ES _FCBGA1329

PEG_COMPI

PEG_COMPO

PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9

LVDS TV VGA

PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15

PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8

PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15

PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8

PCI-EXPRESS GRAPHICS

PEG_TX#_9

PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15

PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8

PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15

(1.27mm)of the (G)MCH

PEGCOMP trace width and spacing is 20/25 mils.

T37 T36

H44 J46 L44 L40 N41 P48 N44 T43 U43 Y43 Y48 Y36 AA43 AD37 AC47 AD39

H43 J44 L43 L41 N40 P47 N43 T42 U42 Y42 W47 Y37 AA42 AD36 AC48 AD40

J41 M46 M47 M40 M42 R48 N38 T40 U37 U40 Y40 AA46 AA37 AA40 AD43 AC46

J42 L46 M48 M39 M43 R47 N37 T39 U36 U39 Y39 Y46 AA36 AA39 AD42 AD46

PEGCOMP

1 2

R67 49 .9_0402_1%R67 49.9_04 02_1%

+VCC_PE G

Please check Power source if want support IAMT

For Cantiga:1.02kohm

A A

Security Class ification

2008/03/ 25 2008/04/

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/03/ 25 2008/04/

Compal Secret Data

For Crestline:1.3kohm For Calero: 255ohm

Deciphered Date

Compal Electronics,Ltd.

Title

Cantiga(3/6)-VGA/LVDS/TV

Size Document N umber Rev

Custom

Date: Sheet of

KIUE0_LA-5191P

10 43W ednesday, June 24, 2009

1.0

0.1U_0402_16V4Z

C62

0.1U_0402_16V4Z

C71

R92

1 2

0_0603_5%

0.022U_0402_16V7K

+3VS_DAC_CRT

0.022U_0402_16V7K

C63

+3VS_DAC_BG

0.022U_0402_16V7K

C72

+3VS_TVDAC

C105

10U_0805_10V4Z

C64

10U_0805_10V4Z

C73

+1.05VS

220U_D2_4VY_R15M

C106

0.1U_0402_16V4Z

+1.5VS_PEG_BG: 0.414mA (0.1UF*1)

220UF_D

1 2

C90

0_0603_5%

VCCA_CRT_DAC: 73mA (0.1UF*1, 0.01UF*1)

CCA_DAC_BG: 2.68mA (0.1UF*1, 0.01UF*1)

+1.5VS_PEG_BG

R85

0_0603_5%

C91

C95

4.7U_0805_10V4Z

4.7U_0805_10V4Z C92

C92

+1.05VS_A_SM_CK

1U_0402_6.3V4Z

10U_0805_10V4Z

C96

+1.5VS

R88

0_0805_5%

10U_0805_10V4Z

R89

+3VS

1 2

R79

R79 0_0603_5%

0_0603_5%

+3VS

D D

1 2

R82

R82 0_0603_5%

0_0603_5%

VCCA_SM:720mA

22UF*2, 4.7UF*1, 1UF*1)

(

C C

VCCA_SM_CK: 220mA (22UF*1, 2.2UF*1, 0.1UF*1)

+3VS

B B

+3VS_DAC_CRT

+3VS_DAC_BG

+1.05VS_DPLLA

+1.05VS_DPLLB

+1.05VS_HPLL

+1.8V_TXLVDS

+1.05VS_MPLL

+1.05VS_PEGPLL

+1.05VS_A_SM

1U_0603_10V4Z

C98

+3VS_TVDAC

+1.05VS_PEGPLL

C76

0.1U_0402_16V4Z

+1.5VS_TVDAC

+1.5VS_QDAC

+1.05VS_HPLL

+1.8V_LVDS

1000P_0402_50V7K

C83

0.1U_0402_16V4Z

C97

+3VS_TVDAC: 40mA (0.1UF*1, 0.01UF*1 for each DAC)

20 mils

C93

U3H

B27

VCCA_CRT_DAC_1

A26

VCCA_CRT_DAC_2

A25

VCCA_DAC_BG

B25

VSSA_DAC_BG

F47

VCCA_DPLLA

L48

VCCA_DPLLB

AD1

VCCA_HPLL

AE1

VCCA_MPLL

J48

VCCA_LVDS

J47

VSSA_LVDS

AD48

VCCA_PEG_BG

AA48

VCCA_PEG_PLL

AR20

VCCA_SM_1

AP20

VCCA_SM_2

AN20

VCCA_SM_3

AR17

VCCA_SM_4

AP17

VCCA_SM_5

AN17

VCCA_SM_6

AT16

VCCA_SM_7

AR16

VCCA_SM_8

AP16

VCCA_SM_9

AP28

VCCA_SM_CK_1

AN28

VCCA_SM_CK_2

AP25

VCCA_SM_CK_3

AN25

VCCA_SM_CK_4

AN24

VCCA_SM_CK_5

AM28

VCCA_SM_CK_NCT F_1

AM26

VCCA_SM_CK_NCT F_2

AM25

VCCA_SM_CK_NCT F_3

AL25

VCCA_SM_CK_NCT F_4

AM24

VCCA_SM_CK_NCT F_5

AL24

VCCA_SM_CK_NCT F_6

AM23

VCCA_SM_CK_NCT F_7

AL23

VCCA_SM_CK_NCT F_8

B24

VCCA_TV_DAC_1

A24

VCCA_TV_DAC_2

A32

VCC_HDA

M25

VCCD_TVDAC

L28

VCCD_QDAC

AF1

VCCD_HPLL

AA47

VCCD_PEG_PLL

M38

VCCD_LVDS_1

L37

VCCD_LVDS_2

CRTPLLA LVDSA PEG

POWER

A SM

HDA

LVDS D TV/CRT

VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8

VTT_9 VTT_10 VTT_11 VTT_12 VTT_13 VTT_14

VTT

VTT_15 VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22 VTT_23 VTT_24 VTT_25

VCC_AXF_1 VCC_AXF_2 VCC_AXF_3

AXF

VCC_SM_CK_1 VCC_SM_CK_2 VCC_SM_CK_3 VCC_SM_CK_4

SM CK

VCC_TX_LVDS

A CK

VCC_HV_1 VCC_HV_2 VCC_HV_3

VCC_PEG_1 VCC_PEG_2 VCC_PEG_3 VCC_PEG_4 VCC_PEG_5

VCC_DMI_1 VCC_DMI_2 VCC_DMI_3 VCC_DMI_4

DMI PEG

VTTLF1 VTTLF2 VTTLF3

VTTLF

CANTIGA ES_FCBGA1329

U13 T13 U12 T12 U11 T11 U10 T10 U9 T9 U8 T8 U7 T7 U6 T6 U5 T5 V3 U3 V2 U2 T2 V1 U1

B22 B21 A21

BF21 BH20 BG20 BF20

K47

C35 B35 A35

V48 U48 V47 U47 U46

AH48 AF48 AH47 AG47

A8 L1 AB2

+1.05VS

+1.8V_TXLVDS

+VCC_DMI

VCC_DMI: 456mA (0.1UF*1)

20mils

C111

220UF_D

220U_D2_4VM

C65

C740.47U_0402_6.3V6K C740.47U_0402_6.3V6K

+V1.05VS_AXF

+1.5V_SM_CK

+VCC_PEG

0.47U_0402_6.3V6K

C112

20 mils

220UF_D

20 mils

+V1.05VS_AXF

10U_0805_10V4Z

+1.5VS_TVDAC

C87

1000P_0402_50V7K

C101

+VCC_PEG+1.05VS_PEGPLL

220U_D2_4VM

C104

+VCC_DMI

1U_0603_10V4Z

C114

C69

0.022U_0402_16V7K

+1.8V_TXLVDS

C102

C109

C115

+1.05VS

+3VS

+1.05VS_DPLLA

+1.05VS_HPLL

0.1U_0402_16V4Z

+1.05VS_MPLL

0.1U_0402_16V4Z

2 1

0.1U_0402_16V4Z

C67

+1.05VS_DPLLB

0.1U_0402_16V4Z

C77

C84

C99

0.1U_0402_16V4Z

C107

+VCCP_D

@D3

CH751H-40PT_SOD323-2

4.7U_0805_10V4Z

C66

4.7U_0805_10V4Z

C75

+3VS_HV

0.1U_0402_16V4Z

C103

0.47U_0402_6.3V6K

C113

R80

1 2

10U_0805_10V4Z

MCK3225151YZF 1210

C68

+1.05VS_DPLLA +1.05VS_DPLLB: 64.8mA (470UF*1, 0.1UF*1)

R83

1 2

10U_0805_10V4Z

MCK3225151YZF 1210

C78

+1.05VS_HPLL: 24mA (4.7UF*1, 0.1UF*1)

L12

MBK2012121YZF_2P

C85

2.2U_0603_6.3V4Z

1.05VS_MPLL: 139.2mA

L13

(22UF*1, 0.1UF*1)

MBK2012121YZF_2P

C100

2.2U_0603_6.3V4Z

BLM18PG121SN1D_0603

C108

2.2U_0603_6.3V4Z

R95

@R95

10_0402_5%

+1.05VS

+1.5VS_PEG_PLL: 50mA (0.1UF*1)

+1.05VS

R96

0_0402_5%

+3VS_HV

1U_0603_10V4Z

+1.5V_SM_CK

C79

0.1U_0402_16V4Z

C88

10U_0805_10V4Z

C70

10U_0805_10V4Z

C89

R91

0_0603_5%

C116

1 2

10U_0805_10V4Z

0_0805_5%

10U_0805_10V4Z

VCC_AXF: 321.35mA (10UF*1, 1UF*1)

+1.05VS

R81

0_0603_5%

VCC_SM_CK: 119.85mA (10UF*1, 0.1UF*1)

0.1U_0402_16V4Z

VCCD_TVDAC: 58.696mA (0.1UF*1, 0.01UF*1)

+1.8V_TXLVDS: 118.8mA (22UF*1, 1000PF*1)

R93

R94

0_0805_5%

R84

1 2

0_0805_5%

C80

R87

0_0603_5%

+1.8VS

+1.5V

+1.5VS

+1.05VS

C117

C118

VCCD_QDAC: 48.363mA (0.1UF*1, 0.01UF*1)

R97

0_0603_5%

0_0603_5% 10U_0805_10V4Z

10U_0805_10V4Z

0.1U_0402_16V4Z

C119

+1.8V_LVDS

+1.5VS

10U_0805_10V4Z

C120

+1.5VS_QDAC

1U_0402_6.3V4Z

A A

1.8V_LVDS: 60.311111mA (1UF*1)

R98

0_0603_5%

0_0603_5% 1U_0603_10V4Z

1U_0603_10V4Z

C121

+1.8VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DR AWING IS THE PR OPRIETARY PROPER TY OF COMPAL ELECT RONICS, INC. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PR OPRIETARY PROPER TY OF COMPAL ELECT RONICS, INC. AND CONTAINS CON FIDENTIAL AND TRAD E SECRET INFOR MATION. THIS SHEET M AY NOT BE TRANSF ERED FROM T HE CUSTODY OF THE COMPETEN T DIVISION OF R&D

AND TRAD E SECRET INFOR MATION. THIS SHEET M AY NOT BE TRANSF ERED FROM T HE CUSTODY OF THE COMPETEN T DIVISION OF R&D

AND TRAD E SECRET INFOR MATION. THIS SHEET M AY NOT BE TRANSF ERED FROM T HE CUSTODY OF THE COMPETEN T DIVISION OF R&D DEPARTMEN T EXCEPT AS AUT HORIZED BY COMPA L ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INF ORMATION IT CONT AINS

DEPARTMEN T EXCEPT AS AUT HORIZED BY COMPA L ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INF ORMATION IT CONT AINS

DEPARTMEN T EXCEPT AS AUT HORIZED BY COMPA L ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INF ORMATION IT CONT AINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, IN C.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, IN C.

2007/10/15 2008/10/15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Crestline GMCH (4/6)-VCC

KIUE0_LA-5191P

1.0

11 43Wednesday, June 24, 2009

1.0

D D

0.22U_0402_10V4Z

10U_0805_10V4Z

C C

B B

A A

C127

C126

+1.05VS

0.1U_0402_16V4Z

C133

C128

AG34 AC34 AB34 AA34

AM33 AK33

AJ33 AG33 AF33

AE33 AC33 AA33

W33

AH28 AF28 AC28 AA28

AJ26 AG26 AE26 AC26 AH25 AG25 AF25 AG24

AJ23 AH23 AF23

U3G

VCC_1 VCC_2 VCC_3 VCC_4

Y34

VCC_5

V34

VCC_6

U34

VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12

VCC_13 VCC_14 VCC_15

Y33

VCC_16 VCC_17

V33

VCC_18

U33

VCC_19 VCC_20 VCC_21 VCC_22 VCC_23 VCC_24 VCC_25 VCC_26 VCC_27 VCC_28 VCC_29 VCC_30 VCC_31 VCC_32 VCC_33 VCC_34

T32

VCC_35

VCC CORE

POWER

VCC NCTF

CANTIGA ES_FCBGA1329

VCC_NCTF_1 VCC_NCTF_2 VCC_NCTF_3 VCC_NCTF_4 VCC_NCTF_5 VCC_NCTF_6 VCC_NCTF_7 VCC_NCTF_8

VCC_NCTF_9 VCC_NCTF_10 VCC_NCTF_11 VCC_NCTF_12 VCC_NCTF_13 VCC_NCTF_14 VCC_NCTF_15 VCC_NCTF_16 VCC_NCTF_17 VCC_NCTF_18 VCC_NCTF_19 VCC_NCTF_20 VCC_NCTF_21 VCC_NCTF_22 VCC_NCTF_23 VCC_NCTF_24 VCC_NCTF_25 VCC_NCTF_26 VCC_NCTF_27 VCC_NCTF_28 VCC_NCTF_29 VCC_NCTF_30 VCC_NCTF_31 VCC_NCTF_32 VCC_NCTF_33 VCC_NCTF_34 VCC_NCTF_35 VCC_NCTF_36 VCC_NCTF_37 VCC_NCTF_38 VCC_NCTF_39 VCC_NCTF_40 VCC_NCTF_41 VCC_NCTF_42 VCC_NCTF_43 VCC_NCTF_44

AM32 AL32 AK32 AJ32 AH32 AG32 AE32 AC32 AA32 Y32 W32 U32 AM30 AL30 AK30 AH30 AG30 AF30 AE30 AC30 AB30 AA30 Y30 W30 V30 U30 AL29 AK29 AJ29 AH29 AG29 AE29 AC29 AA29 Y29 W29 V29 AL28 AK28 AL26 AK26 AK25 AK24 AK23

+1.05VS

1782mA

+1.5V

1U_0603_10V4Z

220UF_D

C132

0.1U_0402_16V4Z

EMI +1.5V decoupling

C134

C135

220U_D2_4VM_R15

220UF_D

220U_D2_4VM_R15

C124

10U_0805_10V4Z

C136

C125

C139

0.1U_0402_16V4Z

C137

10U_0805_10V4Z

+1.05VS

0.1U_0402_16V4Z

C138

U3F

AP33

VCC_SM_1

AN33

VCC_SM_2

BH32

VCC_SM_3

0.01U_0402_16V7K

BG32

VCC_SM_4

BF32

VCC_SM_5

BD32

VCC_SM_6

BC32

C131

T11T11 T12T12

BB32 BA32 AY32

AW32

AV32 AU32 AT32 AR32 AP32 AN32 BH31 BG31 BF31 BG30 BH29 BG29 BF29 BD29 BC29 BB29 BA29 AY29

AW29

AV29 AU29 AT29 AR29 AP29

BA36 BB24 BD16

BB21 AW16 AW13

AT13

AE25

AB25

AA25

AE24

AC24

AA24

AE23

AC23

AB23

AA23

AJ21 AG21 AE21 AC21 AA21

AH20 AF20 AE20 AC20 AB20 AA20

AM15

AL15 AE15

AJ15 AH15 AG15 AF15 AB15 AA15

AN14 AM14

AJ14 AH14

Y26

Y24

Y21

T17 T16

Y15 V15 U15

U14 T14

VCC_SM_7 VCC_SM_8 VCC_SM_9 VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33 VCC_SM_34 VCC_SM_35

VCC_SM_36/NC VCC_SM_37/NC VCC_SM_38/NC VCC_SM_39/NC VCC_SM_40/NC VCC_SM_41/NC VCC_SM_42/NC

VCC_AXG_1 VCC_AXG_2 VCC_AXG_3 VCC_AXG_4 VCC_AXG_5 VCC_AXG_6 VCC_AXG_7 VCC_AXG_8 VCC_AXG_9 VCC_AXG_10 VCC_AXG_11 VCC_AXG_12 VCC_AXG_13 VCC_AXG_14 VCC_AXG_15 VCC_AXG_16 VCC_AXG_17 VCC_AXG_18 VCC_AXG_19 VCC_AXG_20 VCC_AXG_21 VCC_AXG_22 VCC_AXG_23 VCC_AXG_24 VCC_AXG_25 VCC_AXG_26 VCC_AXG_27 VCC_AXG_28 VCC_AXG_29 VCC_AXG_30 VCC_AXG_31 VCC_AXG_32 VCC_AXG_33 VCC_AXG_34 VCC_AXG_35 VCC_AXG_36 VCC_AXG_37 VCC_AXG_38 VCC_AXG_39 VCC_AXG_40 VCC_AXG_41 VCC_AXG_42

VCC_AXG_SENSE VSS_AXG_SENSE

VCC_AXG_NTCF_1 VCC_AXG_NCTF_2 VCC_AXG_NCTF_3 VCC_AXG_NCTF_4 VCC_AXG_NCTF_5 VCC_AXG_NCTF_6 VCC_AXG_NCTF_7 VCC_AXG_NCTF_8

VCC SM

VCC_AXG_NCTF_9 VCC_AXG_NCTF_10 VCC_AXG_NCTF_11 VCC_AXG_NCTF_12 VCC_AXG_NCTF_13 VCC_AXG_NCTF_14 VCC_AXG_NCTF_15 VCC_AXG_NCTF_16 VCC_AXG_NCTF_17 VCC_AXG_NCTF_18 VCC_AXG_NCTF_19 VCC_AXG_NCTF_20 VCC_AXG_NCTF_21 VCC_AXG_NCTF_22 VCC_AXG_NCTF_23 VCC_AXG_NCTF_24 VCC_AXG_NCTF_25 VCC_AXG_NCTF_26 VCC_AXG_NCTF_27 VCC_AXG_NCTF_28 VCC_AXG_NCTF_29 VCC_AXG_NCTF_30 VCC_AXG_NCTF_31 VCC_AXG_NCTF_32 VCC_AXG_NCTF_33 VCC_AXG_NCTF_34 VCC_AXG_NCTF_35 VCC_AXG_NCTF_36 VCC_AXG_NCTF_37 VCC_AXG_NCTF_38 VCC_AXG_NCTF_39 VCC_AXG_NCTF_40 VCC_AXG_NCTF_41 VCC_AXG_NCTF_42 VCC_AXG_NCTF_43

VCC GFX NCTF

VCC_AXG_NCTF_44 VCC_AXG_NCTF_45 VCC_AXG_NCTF_46 VCC_AXG_NCTF_47 VCC_AXG_NCTF_48 VCC_AXG_NCTF_49 VCC_AXG_NCTF_50 VCC_AXG_NCTF_51 VCC_AXG_NCTF_52

POWER

VCC_AXG_NCTF_53 VCC_AXG_NCTF_54 VCC_AXG_NCTF_55 VCC_AXG_NCTF_56 VCC_AXG_NCTF_57 VCC_AXG_NCTF_58 VCC_AXG_NCTF_59 VCC_AXG_NCTF_60

VCC GFX

VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7

VCC SM LF

CANTIGA ES_FCBGA1329

W28 V28 W26 V26 W25 V25 W24 V24 W23 V23 AM21 AL21 AK21 W21 V21 U21 AM20 AK20 W20 U20 AM19 AL19 AK19 AJ19 AH19 AG19 AF19 AE19 AB19 AA19 Y19 W19 V19 U19 AM17 AK17 AH17 AG17 AF17 AE17 AC17 AB17 Y17 W17 V17 AM16 AL16 AK16 AJ16 AH16 AG16 AF16 AE16 AC16 AB16 AA16 Y16 W16 V16 U16

AV44 BA37 AM40 AV21 AY5 AM10 BB13

+1.05VS

VCCSM_LF1 VCCSM_LF2 VCCSM_LF3 VCCSM_LF4 VCCSM_LF5 VCCSM_LF6 VCCSM_LF7

Check : power

C123

0.1U_0402_16V4Z

C141 0.1U_0402_16V4ZC141 0.1U_0402_16V4Z

C140 0.1U_0402_16V4ZC140 0.1U_0402_16V4Z

C129

0.22U_0402_10V4Z

C130

PLACE AS CLOSE PIN AS COULD.

C142 0.22U_0402_10V4 ZC142 0.22U_0402_10V4Z

C143 0.22U_0402_10V4 ZC143 0.22U_0402_10V4Z

C144 0.47U_0402_6.3V6KC144 0.47U_0402_6.3V6K

4.7U_0603_6.3V6K

C145 1U_0402_6.3V4ZC1 45 1U_0402_6.3V4Z

C146 1U_0402_6.3V4ZC1 46 1U_0402_6.3V4Z

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/10/15 2008/10/15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Crestline GMCH (5/6)-VCC

KIUE0_LA-5191P

12 43Wednesday, June 24, 2009

1.0

U3I

AU48

VSS_1

AR48

VSS_2

AL48

VSS_3

BB47

VSS_4

AW47

VSS_5

AN47

VSS_6

AJ47

VSS_7

AF47

VSS_8

AD47

VSS_9

AB47

VSS_10

Y47

VSS_11

T47

BD46 BA46 AY46 AV46 AR46 AM46

BF44 AH44 AD44 AA44

BC43 AV43 AU43 AM43

BG42 AY42 AT42 AN42

AJ42

AE42

BD41 AU41 AM41 AH41 AD41 AA41

BG40 BB40 AV40 AN40

AT39 AM39

AJ39

AE39

BH38 BC38 BA38 AU38 AH38 AD38 AA38

BF37 BB37

AW37

AT37 AN37

AJ37

BG36 BD36 AK15 AU36

G47

V46 R46 P46 H46 F46

Y44 U44 T44 M44 F44

C43

N42

Y41 U41 T41 M41 G41 B41

H40 E40

N39

B39

Y38 U38 T38

F38 C38

H37 C37

N47 L47

J43

L42

L39

J38

VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99

CANTIGA ES_FCBGA1329

VSS

D D

C C

B B

A A

VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 VSS_199

AM36 AE36 P36 L36 J36 F36 B36 AH35 AA35 Y35 U35 T35 BF34 AM34 AJ34 AF34 AE34 W34 B34 A34 BG33 BC33 BA33 AV33 AR33 AL33 AH33 AB33 P33 L33 H33 N32 K32 F32 C32 A31 AN29 T29 N29 K29 H29 F29 A29 BG28 BD28 BA28 AV28 AT28 AR28 AJ28 AG28 AE28 AB28 Y28 P28 K28 H28 F28 C28 BF26 AH26 AF26 AB26 AA26 C26 B26 BH25 BD25 BB25 AV25 AR25 AJ25 AC25 Y25 N25 L25 J25 G25 E25 BF24 AD12 AY24 AT24 AJ24 AH24 AF24 AB24 R24 L24 K24 J24 G24 F24 E24 BH23 AG23 Y23 B23 A23 AJ6

U3J

BG21

VSS_199

L12

VSS_200

AW21

VSS_201

AU21

VSS_202

AP21

VSS_203

AN21

VSS_204

AH21

VSS_205

AF21

VSS_206

AB21

VSS_207

R21

VSS_208

M21

VSS_209

J21

VSS_210

G21

VSS_211

BC20

VSS_212

BA20

VSS_213

AW20

VSS_214

AT20

VSS_215

AJ20

VSS_216

AG20

VSS_217

Y20

VSS_218

N20

VSS_219

K20

VSS_220

F20

VSS_221

C20

VSS_222

A20

VSS_223

BG19

VSS_224

A18

VSS_225

BG17

VSS_226

BC17

VSS_227

AW17

VSS_228

AT17

VSS_229

R17

VSS_230

M17

VSS_231

H17

VSS_232

C17

VSS_233

BA16

VSS_235

AU16

VSS_237

AN16

VSS_238

N16

VSS_239

K16

VSS_240

G16

VSS_241

E16

VSS_242

BG15

VSS_243

AC15

VSS_244

W15

VSS_245

A15

VSS_246

BG14

VSS_247

AA14

VSS_248

C14

VSS_249

BG13

VSS_250

BC13

VSS_251

BA13

VSS_252

AN13

VSS_255

AJ13

VSS_256

AE13

VSS_257

N13

VSS_258

L13

VSS_259

G13

VSS_260

E13

VSS_261

BF12

VSS_262

AV12

VSS_263

AT12

VSS_264

AM12

VSS_265

AA12

VSS_266

J12

VSS_267

A12

VSS_268

BD11

VSS_269

BB11

VSS_270

AY11

VSS_271

AN11

VSS_272

AH11

VSS_273

Y11

VSS_275

N11

VSS_276

G11

VSS_277

C11

VSS_278

BG10

VSS_279

AV10

VSS_280

AT10

VSS_281

AJ10

VSS_282

AE10

VSS_283

AA10

VSS_284

M10

VSS_285

BF9

VSS_286

BC9

VSS_287

AN9

VSS_288

AM9

VSS_289

AD9

VSS_290

VSS_291

VSS_292

BH8

VSS_293

BB8

VSS_294

AV8

VSS_295

AT8

VSS_296

CANTIGA ES_FCBGA1329

VSS

VSS NCTF

VSS SCB

VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325

VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350

VSS_351 VSS_352 VSS_353 VSS_354

VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8

VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16

VSS_SCB_1 VSS_SCB_2 VSS_SCB_3 VSS_SCB_4 VSS_SCB_5

NC_26 NC_27 NC_28 NC_29 NC_30 NC_31 NC_32 NC_33 NC_34 NC_35 NC_36 NC_37 NC_38 NC_39 NC_40 NC_41 NC_42

AH8 Y8 L8 E8 B8 AY7 AU7 AN7 AJ7 AE7 AA7 N7 J7 BG6 BD6 AV6 AT6 AM6 M6 C6 BA5 AH5 AD5 Y5 L5 J5 H5 F5 BE4

BC3 AV3 AL3 R3 P3 F3 BA2 AW2 AU2 AR2 AP2 AJ2 AH2 AF2 AE2 AD2 AC2 Y2 M2 K2 AM1 AA1 P1 H1

U24 U28 U25 U29

AF32 AB32 V32 AJ30 AM29 AF29 AB29 U26 U23 AL20 V20 AC19 AL17 AJ17 AA17 U17

BH48 BH1 A48 C1 A3

E1 D2 C3 B4 A5 A6 A43 A44 B45 C46 D47 B47 A46 F48 E48 C48 B48

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/10/15 2008/10/15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Cantiga GMCH (6/6)-GND

KIUE0_LA-5191P

13 43Wednesday, June 24, 2009

1.0

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