Lenovo LA-3541P, E20, E420G, E42L, K42A Schematic

...
ZZZ1
ZZZ1
PCB
PCB
A
PJP1
PJP1
14W_DCIN
14W_DCIN
14W_45@
14W_45@
PJP1
PJP1
15W_DCIN
15W_DCIN
15W_45@
15W_45@
B
C
D
E
1 1
12/21 Add PJP1 for DCIN Cable on 45 Level One for 14W DCIN , PN: DC301001Y00 Another for 15W DCIN , PN: DC301001V00
Compal Confidential
2 2
IFTxx Schematics Document
Intel Merom Processor with Crestline + DDRII + ICH8M
(With nVIDIA MXM/B)
3 3
2006-1-31
REV: 0.3
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2006/08/18 2007/8/18
2006/08/18 2007/8/18
2006/08/18 2007/8/18
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
Date: Sheet
Date: Sheet
D
Date: Sheet
Compal Electronics, Inc.
Cover Page
Cover Page
Cover Page
IFTXX M/B LA-3541P Schematic
IFTXX M/B LA-3541P Schematic
IFTXX M/B LA-3541P Schematic
153Friday, February 09, 2007
153Friday, February 09, 2007
153Friday, February 09, 2007
E
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Compal Confidential
Model Name : IFTXX
Fan Control
page 4
File Name : LA-3541P
1 1
CRT & TV-out
page 19
LCD Conn.
page 18
Video Processor
page 18
LVDS
LVDS SDVO
Intel Merom Processor
uPGA-478 Package
H_A#(3..35)
FSB
667/800MHz
Intel Crestline
page 4,5,6
H_D#(0..63)
uFCBGA-1299
PCI-Express
MXM II VGA/B
page 17
2 2
PCI-Express
page 7,8,9,10,11,12,13
DMI X4 mode
Intel ICH8-M
3.3V 48MHz
PCI BUS
R5C833
page 28
3.3V 33 MHz
3 in 1 socket
page 29
IDSEL:AD20 (PIRQC#,PIRQD#, GNT#2, REQ#2)
New Card Socket
page 33
3 3
MINI Card x3
WLAN, 3G/TV-Tuner Robson
page 32
LAN(GbE)
BCM5787M/5906
page 30
RJ45
page 31
CardBus
ENE CB1410
page 26
PCMCIA Socket
page 26
IDSEL:AD22 (PIRQG#,PIRQH#, GNT#0, REQ#0)
Card Reader
Conn.
page 28
BGA-676
page 20,21,22,23
LPC BUS
Thermal Sensor
ADM1032
page 4
Memory BUS(DDRII)
Dual Channel
1.8V DDRII 533/667
USB conn x2 TO M/B
page 33
USB conn x2 TO I/O/B
USB
3.3V 24.576MHz/48Mhz
3.3V ATA-100 S-ATA
port 0
IDE
S-ATA HDD Conn.
page 24
page 37 page 33 page 42
Clock Generator
ICS9LPRS365
page 16
200pin DDRII-SO-DIMM X2
BANK 0, 1, 2, 3
Bluetooth
page 14,15
CMOS Camera
Conn
HD Audio
CDROM Conn.
page 24
MDC 1.5 Conn
page 42
HDA Codec
Audio AMP1394
ALC268
page 38
page 39
Finger Print Conn
page 42
RTC CKT.
page 21
Power On/Off CKT.
page 37
Switch/B Conn.
page 35
Touch Pad
page 36
ENE KB925
page 34
Int.KBD
page 35
SUPER I/O
LPC47N217
page 41
TPM
page 29
DC/DC Interface CKT.
page 43
I/O Conn.
G-Sensor
page 25
BIOS
page 36
SCREW
page 40
FRONT LCD /B.
Power Circuit DC/DC
4 4
CHARGER
page 44,45,47,48 49,50,51
page 46
A
LID SW
page 37
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2006/08/18 2007/8/18
2006/08/18 2007/8/18
2006/08/18 2007/8/18
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
Date: Sheet
Date: Sheet
D
Date: Sheet
Compal Electronics, Inc.
Block Diagrams
Block Diagrams
Block Diagrams
IFTXX M/B LA-3541P Schematic
IFTXX M/B LA-3541P Schematic
IFTXX M/B LA-3541P Schematic
253Thursday, February 08, 2007
253Thursday, February 08, 2007
253Thursday, February 08, 2007
E
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E
Voltage Rails
Power Plane
1 1
2 2
VIN B+ +CPU_CORE
+1.05VS +1.25VS +1.5VS +1.8V +1.8VS +2.5VS +3VALW +3VS +5VALW +5VS +VSB +RTCVCC
STATE
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
Description
Adapter power supply (19V) AC or battery power rail for power circuit. Core voltage for CPU
0.9V switched power rail for DDR terminator+0.9VS ( Actual +0.9V )
1.05V switched power rail
1.25V switched power rail
1.5V switched power rail
1.8V power rail for DDR
1.8V switched power rail
2.5V switched power rail
3.3V always on power rail
3.3V switched power rail 5V always on power rail 5V switched power rail VSB always on power rail RTC power
SIGNAL
SLP_S3#SLP_S1#
HIGH HIGH HIGH
LOW
LOW
LOW
LOW LOW LOW
SLP_S4#
HIGH
LOWLOWLOW
SLP_S5#
HIGHHIGHHIGHHIGH
HIGH
HIGH
LOW
S3S1
N/A N/A N/A
OFF
ON ON
ON
ON ON ON
ON
ON
OFF
ON
OFF
ON ON ON
OFF ON
ON
OFF
ON
ONONON
+VALW
+V +VS Clock
ON
ON
ON
ON
ON
ON
ON
OFF
ON
OFF
S5
N/AN/AN/A
OFF OFF OFFOFF OFFOFF OFFOFF OFF OFF OFF ON*ON OFF ON* OFF ON*ON ON
ON
OFF
OFF
OFF
ONON
LOW
OFF
OFF
OFF
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
External PCI Devices
DEVICE
1394+Cardreader G,H
EC SM Bus1 address
Device
Smart Battery EEPROM(24C16/02)
IDSEL #
AD20 AD22
Address
1010 000X b
REQ/GNT #
2
PIRQ
C,DCARD BUS CB1410
0
EC SM Bus2 address
Device
ADI ADM1032 NVIDIA NB8X
Address
1001 100X b0001 011X b
ICH8M SM Bus address
R743
R743
Address
1101 001Xb
1010 000Xb 1010 010Xb
R743
R743
R743
R743
R743
R743
Device
Clock Generator (ICS9LPRS325AKLFT_MLF72)
DDR DIMM0 DDR DIMM1
R743
R743
PROJECT ID Table
3 3
IFT00 ( 00@ ) IFT01 ( 01@ )
IFT91 ( 11@ ) R694 R281
ID1 R284
R694
ID0 R283 R281R284 R283IFL90 ( 10@ )
BOARD ID Table
R
Ra (R743)
4 4
Structure
15W@ 14W@Rb (R740)
MIC ID Table
R
R785 Single MIC R786 Array MIC
A
Structure
INT@ DUAL@
Security Classification
Security Classification
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Vcc 3.3V +/- 5%
Rb~ R740 Ra~ R743
Board ID
1 2 3 4 5 6 7 8 9 10 11 12
Issued Date
Issued Date
Issued Date
C
47K +/- 5%Rb
Rb
NA 4.7K +/- 5% 47K(RB@) 47K(RB@) 47K(RB@) 47K(RB@) 47K(RB@) 47K(RB@) 47K(RB@) 47K(RB@) 47K(RB@) 47K(RB@) 47K(RB@)
2006/08/18 2007/8/18
2006/08/18 2007/8/18
2006/08/18 2007/8/18
4.7K +/- 5% 10K +/- 5% 18K +/- 5% 27K +/- 5% 39K +/- 5% 56K +/- 5% 82K +/- 5% 120K +/- 5% 220K +/- 5% 470K +/- 5% NA
SKU ID Table
4.7K_0402_5%
4.7K_0402_5%
H_14_C@
H_14_C@
R743
R743
56K_0402_5%
56K_0402_5%
L_14_B@
L_14_B@
Ra V min
Deciphered Date
Deciphered Date
Deciphered Date
10K_0402_5%
10K_0402_5%
H_14_MP
H_14_MP
R743
R743
82K_0402_5%
82K_0402_5%
L_14_C@
L_14_C@
AD_BID
0 V
0.274 V 0.300 V 0.328 V
0.553V
0.849V
1.129 V
1.415 V 1.496 V 1.579 V
1.712 V
2.020V
2.303 V
2.670 V
2.972 V
3.135 V
D
18K_0402_5%
18K_0402_5%
H_15_B@
H_15_B@
R743
R743
120K_0402_5%
120K_0402_5%
L_14_MP@
L_14_MP@
V typ
AD_BID
27K_0402_5%
27K_0402_5%
H_15_C@
H_15_C@
R743
R743
220K_0402_5%
220K_0402_5%
L_15_B@
L_15_B@
V
AD_BID
0 V 0 V
0.578 V
0.913V
0.628 V
0.981 V
1.204 V 1.282 V
1.794 V
2.097 V
2.371 V
2.719 V
3.000 V
3.300 V
1.876 V
2.173 V
2.437 V
2.765 V
3.026 V
3.465 V
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
IFTXX M/B LA-3541P Schematic
IFTXX M/B LA-3541P Schematic
IFTXX M/B LA-3541P Schematic
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
39K_0402_5%
39K_0402_5%
H_15_MP@
H_15_MP@
R743
R743
470K_0402_5%
470K_0402_5%
L_15_C@
L_15_C@
Ra BOM Structure
max
H_14_B@ H_14_C@ H_14_MP@ H_15_B@ H_15_C@ H_15_MP@ L_14_B@ L_14_C@ L_14_MP@ L_15_B@ L_15_C@
NA for L_15_MP
Notes List
Notes List
Notes List
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353Thursday, February 15, 2007
353Thursday, February 15, 2007
353Thursday, February 15, 2007
E
5
4
3
2
1
H_A#[3..35]<7>
H_REQ#[0..4]<7>
H_RS#[0..2]<7>
D D
C C
B B
A A
H_A#[3..35] H_REQ#[0..4] H_RS#[0..2]
JP36A
H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15
H_ADSTB#0<7>
H_ADSTB#1<7>
H_A20M#<21>
H_FERR#<21>
H_IGNNE#<21>
H_STPCLK#<21>
H_INTR<21>
H_NMI<21>
H_SMI#<21>
H_A#16
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4
H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35
JP36A
J4
A[3]#
L5
A[4]#
L4
A[5]#
K5
A[6]#
M3
A[7]#
N2
A[8]#
J1
A[9]#
N3
A[10]#
P5
A[11]#
P2
A[12]#
L2
A[13]#
P4
A[14]#
P1
A[15]#
R1
A[16]#
M1
ADSTB[0]#
K3
REQ[0]#
H2
REQ[1]#
K2
REQ[2]#
J3
REQ[3]#
L1
REQ[4]#
Y2
A[17]#
U5
A[18]#
R3
A[19]#
W6
A[20]#
U4
A[21]#
Y5
A[22]#
U1
A[23]#
R4
A[24]#
T5
A[25]#
T3
A[26]#
W2
A[27]#
W5
A[28]#
Y4
A[29]#
U2
A[30]#
V4
A[31]#
W3
A[32]#
AA4
A[33]#
AB2
A[34]#
AA3
A[35]#
V1
ADSTB[1]#
A6
A20M#
A5
FERR#
C4
IGNNE#
D5
STPCLK#
C6
LINT0
B4
LINT1
A3
SMI#
M4
RSVD[01]
N5
RSVD[02]
T2
RSVD[03]
V3
RSVD[04]
B2
RSVD[05]
C3
RSVD[06]
D2
RSVD[07]
D22
RSVD[08]
D3
RSVD[09]
F6
RSVD[10]
Merom Ball-out Rev 1a
Merom Ball-out Rev 1a
ADDR GROUP 0 ADDR GROUP 1
ADDR GROUP 0 ADDR GROUP 1
XDP/ITP SIGNALS
XDP/ITP SIGNALS
THERMAL
THERMAL
PROCHOT#
THERMDA THERMDC
ICH
ICH
THERMTRIP#
H CLK
H CLK
RESERVED
RESERVED
ADS# BNR#
BPRI#
DEFER#
DRDY# DBSY#
BR0#
IERR#
INIT#
LOCK#
CONTROL
CONTROL
RESET#
RS[0]# RS[1]# RS[2]#
TRDY#
HIT#
HITM#
BPM[0]# BPM[1]# BPM[2]# BPM[3]#
PRDY# PREQ#
TCK
TDO TMS
TRST#
DBR#
BCLK[0] BCLK[1]
conn@
conn@
H1 E2 G5
H5 F21 E1
F1
H_IERR#
D20 B3
H4
H_RESET#
C1
H_RS#0
F3
H_RS#1
F4
H_RS#2
G3 G2
G6 E4
AD4 AD3 AD1 AC4 AC2
H_PREQ#
AC1
ITP_TCK
AC5
ITP_TDI
AA6
TDI
AB3
ITP_TMS
AB5
ITP_TRST#
AB6
ITP_DBRESET#
C20
H_PROCHOT#
D21
THERMDA
A24
THERMDC
B25 C7
A22 A21
H_ADS# <7> H_BNR# <7> H_BPRI# <7>
H_DEFER# <7> H_DRDY# <7> H_DBSY# <7>
H_BR0# <7>
H_INIT# <21> H_LOCK# <7> H_RESET# <7>
H_TRDY# <7> H_HIT# <7>
H_HITM# <7>
ITP_DBRESET# <22>
H_PROCHOT# <51>
H_THERMTRIP# <8,21>
CLK_CPU_BCLK <16> CLK_CPU_BCLK# <16>
Checklist recommend 39 Ohm
CRB pull 75 Ohm
Connect SB SYS_RESET# or just left NC
ADM1032
C688
C688
2200P_0402_50V7K
2200P_0402_50V7K
FAN1 Conn
H_THERMDA, H_THERMDC routing together, Trace width / Spacing = 10 / 10 mil
12/27 change C28,C29 to 10U_0805 12/29 change D4 to SC1SS355010 (IEL10)
+5VS
+VCC_FAN1
EN_FAN1<34>
EN_FAN1
FAN_SPEED1<34>
Place close to CPU within 500mil
12/13 NA for Intel recommend
H_PREQ# H_IERR# ITP_TMS ITP_TDI H_PROCHOT# ITP_TCK ITP_TRST#
1
THERMDA
2
THERMDC
C28 10U_0805_10V4Z
C28 10U_0805_10V4Z
U5
U5
1
VEN
2
VIN
3
VO
4
VSET
G993P1UF_SOP8
G993P1UF_SOP8
+3VS
1 2
+3VS
12
1
2
R559 56_0402_5%@R559 56_0402_5%@
1 2
R560 56_0402_5%
R560 56_0402_5%
1 2
R562 56_0402_5%
R562 56_0402_5%
1 2
R563 150_0402_1%
R563 150_0402_1%
1 2
R565 56_0402_5%
R565 56_0402_5%
1 2
R568 27.4_0402_1%
R568 27.4_0402_1%
1 2
R569 680_0402_5%R569 680_0402_5%
1 2
C687
C687
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 2
U38
U38
1
VDD
2
D+
3
D­THERM#4GND
ADM1032ARMZ_MSOP8
ADM1032ARMZ_MSOP8
F75383M_MSOP8
12/21 Change D4,D5 from @ to mount D5 change from 1N4148 to SC100000Y10 0208 Change D5 from SC100000Y10 to
SC1BAS16000
8
GND
7
GND
6
GND
5
GND
R44
R44 10K_0402_5%
10K_0402_5%
C31
C31 1000P_0402_50V7K
1000P_0402_50V7K
40mil
+VCC_FAN1
SCLK
SDATA
ALERT#
8 7 6 5
+5VS
12
D4
D4 1SS355_SOD323
1SS355_SOD323
D5
D5
1 2
BAS16_SOT23-3
BAS16_SOT23-3
<BOM Structure>
<BOM Structure>
C29 10U_0805_10V4Z
C29 10U_0805_10V4Z
1 2
C30
C30
1000P_0402_50V7K
1000P_0402_50V7K
1 2
+1.05VS
EC_SMB_CK2 <17,34> EC_SMB_DA2 <17,34>
JP6
JP6
1
1
2
2
3
3
4
GND
5
GND
ACES_85205-03001
ACES_85205-03001
Security Classification
Security Classification
Security Classification
2006/08/18 2007/8/18
2006/08/18 2007/8/18
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2006/08/18 2007/8/18
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
Date: Sheet
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
Merom (1/3)
Merom (1/3)
Merom (1/3)
IFTXX M/B LA-3541P Schematic
IFTXX M/B LA-3541P Schematic
IFTXX M/B LA-3541P Schematic
453Thursday, February 15, 2007
453Thursday, February 15, 2007
453Thursday, February 15, 2007
of
of
1
of
0
0
0
5
4
3
2
1
H_D#[0..63]
JP36B
H_D#0
PAD
PAD PAD
PAD PAD
PAD
H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15
H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31
GTL_REF
TEST1 TEST2 TEST3 TEST4 TEST5 TEST6
D D
H_DSTBN#0<7> H_DSTBN#2 <7> H_DSTBP#0<7> H_DSTBP#2 <7>
H_DINV#0<7>
Close to CPU pin AD26 within 500mils.
C C
Width=20 mil
B B
layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs
R549
R549 1K_0402_1%
1K_0402_1%
R556
R556 2K_0402_1%
2K_0402_1%
+1.05VS
1 2
1 2
H_DSTBN#1<7> H_DSTBN#3 <7> H_DSTBP#1<7> H_DSTBP#3 <7>
H_DINV#1<7>
R551 1K_0402_5%@R551 1K_0402_5%@ R553 1K_0402_5%@R553 1K_0402_5%@
C684 0.1U_0402_16V4Z@C684 0.1U_0402_16V4Z@
1 2
12 12
T19
T19 T20
T20 T21
T21
CPU_BSEL0<16> CPU_BSEL1<16> CPU_BSEL2<16>
CPU_BSEL CPU_BSEL2 CPU_BSEL1
JP36B
E22
D[0]#
F24
D[1]#
E26
D[2]#
G22
D[3]#
F23
D[4]#
G25
D[5]#
E25
D[6]#
E23
D[7]#
K24
D[8]#
G24
D[9]#
J24
D[10]#
J23
D[11]#
H22
D[12]#
F26
D[13]#
K22
D[14]#
H23
D[15]#
J26
DSTBN[0]#
H26
DSTBP[0]#
H25
DINV[0]#
N22
D[16]#
K25
D[17]#
P26
D[18]#
R23
D[19]#
L23
D[20]#
M24
D[21]#
L22
D[22]#
M23
D[23]#
P25
D[24]#
P23
D[25]#
P22
D[26]#
T24
D[27]#
R24
D[28]#
L25
D[29]#
T25
D[30]#
N25
D[31]#
L26
DSTBN[1]#
M26
DSTBP[1]#
N24
DINV[1]#
AD26
GTLREF
C23
TEST1
D25
TEST2
C24
TEST3
AF26
TEST4
AF1
TEST5
A26
TEST6
B22
BSEL[0]
B23
BSEL[1]
C21
BSEL[2]
Merom Ball-out Rev 1a
Merom Ball-out Rev 1a
conn@
conn@
CPU_BSEL0
DATA GRP 0
DATA GRP 0
DATA GRP 2DATA GRP 3
DATA GRP 2DATA GRP 3
DSTBN[2]# DSTBP[2]#
DINV[2]#
DATA GRP 1
DATA GRP 1
DSTBN[3]# DSTBP[3]#
DINV[3]# COMP[0]
MISC
MISC
COMP[1] COMP[2] COMP[3]
DPRSTP#
DPSLP#
PWRGOOD
D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]#
D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]#
DPWR#
SLP#
PSI#
Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22
AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20
R26 U26 AA1 Y1
E5 B5 D24 D6 D7 AE6
H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47
H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63
COMP0 COMP1 COMP2 COMP3
H_PWRGOOD H_CPUSLP#
H_DINV#2 <7>
R550 27.4_0402_1%
R550 27.4_0402_1% R552 54.9_0402_1%
R552 54.9_0402_1% R554 27.4_0402_1%
R554 27.4_0402_1% R555 54.9_0402_1%
R555 54.9_0402_1%
H_DINV#3 <7>
1 2 1 2 1 2 1 2
H_DPRSTP# <8,21,51> H_DPSLP# <21> H_DPWR# <7> H_PWRGOOD <21> H_CPUSLP# <7> H_PSI# <51>
H_D#[0..63] <7>
Resistor placed within
0.5" of CPU pin.Trace should be at least 25 mils away from any other toggling signal. COMP[0,2] trace width is 18 mils. COMP[1,3] trace width is 4 mils.
+CPU_CORE
JP36C
JP36C
A7
VCC[001]
A9
VCC[002]
A10
VCC[003]
A12
VCC[004]
A13
VCC[005]
A15
VCC[006]
A17
VCC[007]
A18
VCC[008]
A20
VCC[009]
B7
VCC[010]
B9
VCC[011]
B10
VCC[012]
B12
VCC[013]
B14
VCC[014]
B15
VCC[015]
B17
VCC[016]
B18
VCC[017]
B20
VCC[018]
C9
VCC[019]
C10
VCC[020]
C12
VCC[021]
C13
VCC[022]
C15
VCC[023]
C17
VCC[024]
C18
VCC[025]
D9
VCC[026]
D10
VCC[027]
D12
VCC[028]
D14
VCC[029]
D15
VCC[030]
D17
VCC[031]
D18
VCC[032]
E7
VCC[033]
E9
VCC[034]
E10
VCC[035]
E12
VCC[036]
E13
VCC[037]
E15
VCC[038]
E17
VCC[039]
E18
VCC[040]
E20
VCC[041]
F7
VCC[042]
F9
VCC[043]
F10
VCC[044]
F12
VCC[045]
F14
VCC[046]
F15
VCC[047]
F17
VCC[048]
F18
VCC[049]
F20
VCC[050]
AA7
VCC[051]
AA9
VCC[052]
AA10
VCC[053]
AA12
VCC[054]
AA13
VCC[055]
AA15
VCC[056]
AA17
VCC[057]
AA18
VCC[058]
AA20
VCC[059]
AB9
VCC[060]
AC10
VCC[061]
AB10
VCC[062]
AB12
VCC[063]
AB14
VCC[064]
AB15
VCC[065]
AB17
VCC[066]
AB18
VCC[067]
Merom Ball-out Rev 1a
Merom Ball-out Rev 1a
conn@
conn@
VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100]
VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16]
VCCA[01] VCCA[02]
VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]
VCCSENSE
VSSSENSE
AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20
G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21
B26 C26
AD6 AF5 AE5 AF4 AE3 AF3 AE2
AF7
AE7
.
.
+CPU_CORE
VCCSENSE
VSSSENSE
Place this cap more close to B26/C26 rather than 10UF
1
C686
CPU_VID0 <51> CPU_VID1 <51> CPU_VID2 <51> CPU_VID3 <51> CPU_VID4 <51> CPU_VID5 <51> CPU_VID6 <51>
1 2
R557 100_0402_1%
R557 100_0402_1%
R558 100_0402_1% R558 100_0402_1%
1 2
C686
2
0.01U_0402_16V7K
0.01U_0402_16V7K
1
+
+
C677
C677 330U_D2E_2.5VM_R9
330U_D2E_2.5VM_R9
2
20mils
VCCSENSE <51>
VSSSENSE <51>
+1.05VS
1
C685
C685 10U_0805_10V4Z
10U_0805_10V4Z
2
+CPU_CORE
+1.5VS
166
200
01
0
1
1
0
Length match within 25 mils. The trace width/space/other is 20/7/25.
Close to CPU pin
A A
Security Classification
Security Classification
Security Classification
2006/08/18 2007/8/18
2006/08/18 2007/8/18
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2006/08/18 2007/8/18
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
within 500mils.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
IFTXX M/B LA-3541P Schematic
IFTXX M/B LA-3541P Schematic
IFTXX M/B LA-3541P Schematic
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
Merom (2/3)
Merom (2/3)
Merom (2/3)
553Friday, February 09, 2007
553Friday, February 09, 2007
553Friday, February 09, 2007
1
0
0
0
of
of
of
5
4
3
2
1
+CPU_CORE
JP36D
JP36D
A4
VSS[001]
A8
VSS[002]
A11
VSS[003]
A14
VSS[004]
A16
VSS[005]
A19
VSS[006]
D D
C C
B B
A23
VSS[007]
AF2
VSS[008]
B6
VSS[009]
B8
VSS[010]
B11
VSS[011]
B13
VSS[012]
B16
VSS[013]
B19
VSS[014]
B21
VSS[015]
B24
VSS[016]
C5
VSS[017]
C8
VSS[018]
C11
VSS[019]
C14
VSS[020]
C16
VSS[021]
C19
VSS[022]
C2
VSS[023]
C22
VSS[024]
C25
VSS[025]
D1
VSS[026]
D4
VSS[027]
D8
VSS[028]
D11
VSS[029]
D13
VSS[030]
D16
VSS[031]
D19
VSS[032]
D23
VSS[033]
D26
VSS[034]
E3
VSS[035]
E6
VSS[036]
E8
VSS[037]
E11
VSS[038]
E14
VSS[039]
E16
VSS[040]
E19
VSS[041]
E21
VSS[042]
E24
VSS[043]
F5
VSS[044]
F8
VSS[045]
F11
VSS[046]
F13
VSS[047]
F16
VSS[048]
F19
VSS[049]
F2
VSS[050]
F22
VSS[051]
F25
VSS[052]
G4
VSS[053]
G1
VSS[054]
G23
VSS[055]
G26
VSS[056]
H3
VSS[057]
H6
VSS[058]
H21
VSS[059]
H24
VSS[060]
J2
VSS[061]
J5
VSS[062]
J22
VSS[063]
J25
VSS[064]
K1
VSS[065]
K4
VSS[066]
K23
VSS[067]
K26
VSS[068]
L3
VSS[069]
L6
VSS[070]
L21
VSS[071]
L24
VSS[072]
M2
VSS[073]
M5
VSS[074]
M22
VSS[075]
M25
VSS[076]
N1
VSS[077]
N4
VSS[078]
N23
VSS[079]
N26
VSS[080] VSS[081]P3VSS[162]
Merom Ball-out Rev 1a
Merom Ball-out Rev 1a
conn@
conn@
VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161]
VSS[163]
P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25
.
.
1
+
+
C643
C643 330U_D2E_2.5VM_R9
330U_D2E_2.5VM_R9
2
+CPU_CORE
1
C649
C649
2
10U_0805_6.3V6M
10U_0805_6.3V6M
+CPU_CORE
1
C657
C657
2
10U_0805_6.3V6M
10U_0805_6.3V6M
+CPU_CORE
1
C665
C665
2
10U_0805_6.3V6M
10U_0805_6.3V6M
+CPU_CORE
1
C671
C671
2
10U_0805_6.3V6M
10U_0805_6.3V6M
+CPU-CORE Decoupling SPCAP,Polymer
MLCC 0805 X5R
3 x 330uF(9mOhm/3) 3 x 330uF(9mOhm/3)
1
+
+
C644
C644
2
330U_D2E_2.5VM_R9
330U_D2E_2.5VM_R9
South Side Secondary North Side Secondary
1
C650
C650
10U_0805_6.3V6M
10U_0805_6.3V6M
2
10U_0805_6.3V6M
10U_0805_6.3V6M
1
+
+
C645
C645
@
@
330U_D2E_2.5VM_R9
330U_D2E_2.5VM_R9
2
1
C651
C651
10U_0805_6.3V6M
10U_0805_6.3V6M
2
(Place these capacitors on South side,Secondary Layer)
10U_0805_6.3V6M
10U_0805_6.3V6M
1
C658
C658
2
1
C659
C659
2
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
(Place these capacitors on North side,Secondary Layer)
10U_0805_6.3V6M
10U_0805_6.3V6M
1
C666
C666
2
1
C667
C667
2
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
(Place these capacitors on South side,Primary Layer)
1
C673
C673
2
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
1
C672
C672
2
(Place these capacitors on North side,Primary Layer)
C,uF ESR, mohm ESL,nH 6X330uF 9m ohm/6 1.8nH/6
32X22uF 3m ohm/32 0.6nH/32 32X10uF 3m ohm/32 0.6nH/32
+1.05VS
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C678
C678
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C679
C679
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C680
C680
2
1
2
1
2
1
2
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+CPU_CORE
1
+
+
C646
C646
330U_D2E_2.5VM_R9
330U_D2E_2.5VM_R9
2
330U_D2E_2.5VM_R9
330U_D2E_2.5VM_R9
C652
C652
C660
C660
C668
C668
C674
C674
1
C653
C653
2
10U_0805_6.3V6M
10U_0805_6.3V6M
1
C661
C661
2
10U_0805_6.3V6M
10U_0805_6.3V6M
1
C669
C669
2
10U_0805_6.3V6M
10U_0805_6.3V6M
1
C675
C675
2
10U_0805_6.3V6M
10U_0805_6.3V6M
1
C681
C681
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C647
C647
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
1
C682
C682
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
+
+
2
1
C654
C654
2
1
C662
C662
2
1
C670
C670
2
1
C676
C676
2
1
C683
C683
2
1
+
+
C648
C648
@
@
330U_D2E_2.5VM_R9
330U_D2E_2.5VM_R9
2
1
C655
C655
10U_0805_6.3V6M
10U_0805_6.3V6M
2
10U_0805_6.3V6M
10U_0805_6.3V6M
1
C663
C663
10U_0805_6.3V6M
10U_0805_6.3V6M
2
10U_0805_6.3V6M
10U_0805_6.3V6M
1
C700
C700
10U_0805_6.3V6M
10U_0805_6.3V6M
2
10U_0805_6.3V6M
10U_0805_6.3V6M
1
C702
C702
10U_0805_6.3V6M
10U_0805_6.3V6M
2
10U_0805_6.3V6M
10U_0805_6.3V6M
1
CRB no stuff. Reserved!
C656
C656
2
1
C664
C664
2
1
C701
C701
2
1
C703
C703
2
9/25 10U checked. OK for use!
A A
Security Classification
Security Classification
Security Classification
2006/08/18 2007/8/18
2006/08/18 2007/8/18
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2006/08/18 2007/8/18
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
Date: Sheet
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
Merom (3/3)
Merom (3/3)
Merom (3/3)
IFTXX M/B LA-3541P Schematic
IFTXX M/B LA-3541P Schematic
IFTXX M/B LA-3541P Schematic
653Thursday, February 08, 2007
653Thursday, February 08, 2007
653Thursday, February 08, 2007
1
0
0
0
of
of
of
5
4
3
2
1
1/2 change U37 PM part number to SA00001DJ90
U37A
M10 N12
P13
W10
AD12
AE3 AD9 AC9 AC7
AC14 AD11 AC11
AB2 AD7
AB1 AC6
AE2 AC5 AG3
AJ9 AH8
AJ14
AE9
AE11 AH12
AJ5 AH5
AJ6
AE7
AJ7
AJ2
AE5
AJ3 AH2
AH13
E2 G2 G7 M6
H7
H3 G4
F3
N8
H2
N9
H5
K9 M2
Y8
V4 M3
J1
N5
N3 W6 W9
N2
Y7
Y9
P4 W3
N1
Y3
B3
C2 W1
W2
B6
E5
B9
A9
U37A
H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63
H_SWING H_RCOMP
H_SCOMP H_SCOMP#
H_CPURST# H_CPUSLP#
H_AVREF H_DVREF
CRESTLINE_1p0
CRESTLINE_1p0
PM@
PM@
H_ADSTB#_0 H_ADSTB#_1
HOST
HOST
H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3
H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3
H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8
H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35
H_ADS#
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK# H_TRDY#
H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3
H_REQ#_0 H_REQ#_1
H_REQ#_2 H_REQ#_3
H_REQ#_4
H_RS#_0 H_RS#_1 H_RS#_2
J13 B11 C11 M11 C15 F16 L13 G17 C14 K16 B13 L16 J17 B14 K19 P15 R17 B16 H20 L19 D17 M17 N16 J19 B18 E19 B17 B15 E17 C18 A19 B19 N19
G12 H17 G20 C8 E8 F12 D6 C10 AM5 AM7 H8 K7 E4 C6 G10 B7
K5 L2 AD13 AE13
M7 K3 AD2 AH11
L7 K2 AC2 AJ10
M14 E13 A11 H13 B12
E12 D7 D8
H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35
H_ADS# H_ADSTB#0 H_ADSTB#1 H_BNR# H_BPRI# H_BR0# H_DEFER# H_DBSY# CLK_MCH_BCLK CLK_MCH_BCLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY#
H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3
H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3
H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4
H_RS#0 H_RS#1 H_RS#2
H_D#[0..63]<5>
D D
+1.05VS
12
R539
R539 221_0402_1%
221_0402_1%
H_SWNG
1
R540
C C
R540 100_0402_1%
100_0402_1%
1 2
C641
C641
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
Near B3 pin
H_RCOMP
12
R541
R541
24.9_0402_1%
24.9_0402_1%
layout note: Route H_SCOMP and H_SCOMP# with
trace width, spacing and impedance (55 ohm) same as FSB data traces
B B
+1.05VS
R544
R544 1K_0402_1%
1K_0402_1%
1 2 12
R546
R546 2K_0402_1%
2K_0402_1%
54.9_0402_1%
54.9_0402_1%
R542
R542
1
2
+1.05VS
1 2
H_RESET#<4>
H_CPUSLP#<5>
C642
C642
0.1U_0402_16V4Z
0.1U_0402_16V4Z
R543
R543
54.9_0402_1%
54.9_0402_1%
1 2
H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63
H_SWNG H_RCOMP
H_SCOMP H_SCOMP#
H_RESET# H_CPUSLP#
H_VREF
H_A#[3..35] <4>
H_ADS# <4> H_ADSTB#0 <4> H_ADSTB#1 <4> H_BNR# <4> H_BPRI# <4> H_BR0# <4> H_DEFER# <4> H_DBSY# <4> CLK_MCH_BCLK <16> CLK_MCH_BCLK# <16> H_DPWR# <5> H_DRDY# <4> H_HIT# <4> H_HITM# <4> H_LOCK# <4> H_TRDY# <4>
H_DINV#0 <5> H_DINV#1 <5> H_DINV#2 <5> H_DINV#3 <5>
H_DSTBN#0 <5> H_DSTBN#1 <5> H_DSTBN#2 <5> H_DSTBN#3 <5>
H_DSTBP#0 <5> H_DSTBP#1 <5> H_DSTBP#2 <5> H_DSTBP#3 <5>
H_REQ#[0..4] <4>
H_RS#[0..2] <4>
U37
U37
965GM
965GM
GM@
GM@
1/2 change U37 GM part number to SA00000ZW80
within 100mil to Ball A9,B9
A A
Security Classification
Security Classification
Layout Note: H_RCOMP / H_VREF / H_SWNG
trace width and spacing is 10/20
5
Security Classification
2006/08/18 2007/8/18
2006/08/18 2007/8/18
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2006/08/18 2007/8/18
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
Date: Sheet
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
Crestline (1/7)-GTL
Crestline (1/7)-GTL
Crestline (1/7)-GTL
IFTXX M/B LA-3541P Schematic
IFTXX M/B LA-3541P Schematic
IFTXX M/B LA-3541P Schematic
753Friday, February 09, 2007
753Friday, February 09, 2007
753Friday, February 09, 2007
of
of
1
of
0
0
0
5
D D
DDRA_SMA14<14> DDRB_SMA14<14,15>
DDRA_SMA14 DDRB_SMA14
9/20 Modify NB symbol for Pin BJ29/BE24/C48/D47
C C
MCH_CLKSEL0<16> MCH_CLKSEL1<16> MCH_CLKSEL2<16>
B B
PM_BMBUSY#<22>
H_DPRSTP#<5,21,51> PM_EXTTS#0<14>
PLT_RST_BUF#<17,20,29,30,32,41>
H_THERMTRIP#<4,21>
PM_EXTTS#1<15>
PM_DPRSLPVR<22,51>
PM_EXTTS#0 PM_EXTTS#1
R525 100_0402_5%
R525 100_0402_5% R527 0_0402_5%
R527 0_0402_5%
1 2
MCH_CLKSEL0 MCH_CLKSEL1 MCH_CLKSEL2
MCH_CFG_5
MCH_CFG_9
MCH_CFG_12 MCH_CFG_13
MCH_CFG_16
MCH_CFG_19 MCH_CFG_20
GMCH_PWROK MCH_RSTIN#
If THERMTRIP no used, left NC
Use VGATE for GMCH_PWROK
VGATE<22,51> ICH_POK<22,34>
A A
VGATE
ICH_POK
1 2
R533 0_0402_5%@R533 0_0402_5%@
1 2
R535 0_0402_5% R535 0_0402_5%
GMCH_PWROK
AR12 AR13 AM12 AN13
AR37 AM36
AL36
AM37
BJ20
BK22
BF19 BH20 BK18
BJ18
BF23 BG23 BC23 BD24
BJ29 BE24 BH39
AW20
BK20
AW49
AV20
BJ51 BK51 BK50
BL50
BL49
G23
M20 M24
G41
G36
BK1
BK2
4
P36 P37 R35 N35
J12
D20
H10 B51
C48 D47 B44 C44 A35 B37 B36 B34 C34
P27 N27 N24 C21 C23 F23 N23
J20 C20 R24
L23
J23 E23 E20 K23
L32 N33
L35
L39
L36
J36
N20
BL3 BL2
BJ1
E1
A5 C51 B50 A50 A49
U37B
U37B
RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14
RSVD20 RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 RSVD26 RSVD27 RSVD28 RSVD29 RSVD30 RSVD31 SA_MA_14 SB_MA_14 RSVD34 RSVD35 RSVD36 LVDSA_DATA#_3 LVDSA_DATA_3 RSVD39 RSVD40 RSVD41 RSVD42 RSVD43 RSVD44 RSVD45
CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20
PM_BM_BUSY# PM_DPRSTP# PM_EXT_TS#_0 PM_EXT_TS#_1 PWROK RSTIN# THERMTRIP# DPRSLPVR
NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16
CRESTLINE_1p0
CRESTLINE_1p0
PM@
PM@
SM_CK_0 SM_CK_1 SM_CK_3 SM_CK_4
SM_CK#_0 SM_CK#_1 SM_CK#_3 SM_CK#_4
SM_CKE_0 SM_CKE_1 SM_CKE_3 SM_CKE_4
SM_CS#_0 SM_CS#_1 SM_CS#_2 SM_CS#_3
SM_ODT_0 SM_ODT_1 SM_ODT_2 SM_ODT_3
SM_RCOMP
SM_RCOMP#
SM_RCOMP_VOH
SM_RCOMP_VOL
SM_VREF_0 SM_VREF_1
DDR MUXINGCLK
DDR MUXINGCLK
DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
PEG_CLK
PEG_CLK#
DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3
DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3
DMI_TXN_0 DMI_TXN_1 DMI_TXN_2
CFGRSVD
CFGRSVD
PM
PM
NC
NC
DMI_TXN_3 DMI_TXP_0
DMI_TXP_1 DMI_TXP_2
DMI
DMI
DMI_TXP_3
GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3
GFX_VR_EN
GRAPHICS VID
GRAPHICS VID
ME
ME
MISC
MISC
CL_CLK
CL_DATA
CL_PWROK
CL_RST# CL_VREF
SDVO_CTRL_CLK
SDVO_CTRL_DATA
CLK_REQ#
ICH_SYNC#
TEST_1 TEST_2
AV29 BB23 BA25 AV23
AW30 BA23 AW25 AW23
BE29 AY32 BD39 BG37
BG20 BK16 BG16 BE13
BH18 BJ15 BJ14 BE16
BL15 BK14
BK31 BL31
AR49 AW4
B42 C42 H48 H47
K44 K45
AN47 AJ38 AN42 AN46
AM47 AJ39 AN41 AN45
AJ46 AJ41 AM40 AM44
AJ47 AJ42 AM39 AM43
E35 A39 C38 B39 E36
AM49 AK50 AT43 AN49 AM50
H35 K36 G39 G40
A37 R32
3
SMRCOMP SMRCOMP#
SM_RCOMP_VOH SM_RCOMP_VOL
CLK_DREF_96M CLK_DREF_96M# CLK_DREF_SSC CLK_DREF_SSC#
CLK_MCH_3GPLL CLK_MCH_3GPLL#
DMI_ITX_MRX_N0 DMI_ITX_MRX_N1 DMI_ITX_MRX_N2 DMI_ITX_MRX_N3
DMI_ITX_MRX_P0 DMI_ITX_MRX_P1 DMI_ITX_MRX_P2 DMI_ITX_MRX_P3
DMI_MTX_IRX_N0 DMI_MTX_IRX_N1 DMI_MTX_IRX_N2 DMI_MTX_IRX_N3
DMI_MTX_IRX_P0 DMI_MTX_IRX_P1 DMI_MTX_IRX_P2 DMI_MTX_IRX_P3
CL_VREF
SDVO_CTRL_CLK SDVO_CTRL_DATA MCH_CLKREQ#
MCH_TEST_1 MCH_TEST_2
DDRA_CLK0 <14> DDRA_CLK1 <14> DDRB_CLK0 <15> DDRB_CLK1 <15>
DDRA_CLK0# <14> DDRA_CLK1# <14> DDRB_CLK0# <15> DDRB_CLK1# <15>
DDRA_CKE0 <14> DDRA_CKE1 <14> DDRB_CKE0 <15> DDRB_CKE1 <15>
DDRA_SCS0# <14> DDRA_SCS1# <14> DDRB_SCS0# <15> DDRB_SCS1# <15>
DDRA_ODT0 <14> DDRA_ODT1 <14> DDRB_ODT0 <15> DDRB_ODT1 <15>
R516 20_0402_1% R516 20_0402_1%
1 2
R517 20_0402_1% R517 20_0402_1%
1 2
SM_VREF
CLK_DREF_96M <16> CLK_DREF_96M# <16> CLK_DREF_SSC <16> CLK_DREF_SSC# <16>
CLK_MCH_3GPLL <16> CLK_MCH_3GPLL# <16>
DMI_ITX_MRX_N0 <22> DMI_ITX_MRX_N1 <22> DMI_ITX_MRX_N2 <22> DMI_ITX_MRX_N3 <22>
DMI_ITX_MRX_P0 <22> DMI_ITX_MRX_P1 <22> DMI_ITX_MRX_P2 <22> DMI_ITX_MRX_P3 <22>
DMI_MTX_IRX_N0 <22> DMI_MTX_IRX_N1 <22> DMI_MTX_IRX_N2 <22> DMI_MTX_IRX_N3 <22>
DMI_MTX_IRX_P0 <22> DMI_MTX_IRX_P1 <22> DMI_MTX_IRX_P2 <22> DMI_MTX_IRX_P3 <22>
CL_CLK0 <22> CL_DATA0 <22> CL_PWROK <22> CL_RST# <22>
MCH_CLKREQ# <16> MCH_ICH_SYNC# <22>
R537 0_0402_5%
R537 0_0402_5% R538 20K_0402_5%
R538 20K_0402_5%
20mil
+1.8V
1
C639
C639
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C640
C640
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
Layout Note: SM_VREF trace width and spacing is 20/20.
+1.8V
R518
R518 1K_0402_1%
1K_0402_1%
1 2
R520
R520 1K_0402_1%
1K_0402_1%
1 2
+1.25VS
R528
R528
1K_0402_1%
1K_0402_1%
1 2
R531
R531
392_0402_1%
392_0402_1%
1 2
+1.8V
R513
R513 1K_0402_1%
1K_0402_1%
R514
R514
3.01K_0402_1%
3.01K_0402_1%
R515
R515 1K_0402_1%
1K_0402_1%
12/22 Change from 0805 to 0603
C636
C635
C635
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
C637
C637
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
C636
0.01U_0402_16V7K
0.01U_0402_16V7K
C638
C638
0.01U_0402_16V7K
0.01U_0402_16V7K
CLK_DREF_96M# CLK_DREF_SSC# CLK_DREF_96M CLK_DREF_SSC
SM_RCOMP_VOH
SM_RCOMP_VOH
SM_RCOMP_VOL
CFG[17:3] have internal pull up CFG[19:18] have internal pull down
CFG[2:0]
CFG5 CFG9
CFG[13:12]
CFG16 CFG19 CFG20
(PCIE/SDVO select)
SDVO_CTRLDATA
MCH_CFG_5 MCH_CFG_9 MCH_CFG_12 MCH_CFG_13 MCH_CFG_16
MCH_CFG_19 MCH_CFG_20
PM_EXTTS#0 PM_EXTTS#1 MCH_CLKREQ#
SDVO_CTRL_CLK SDVO_CTRL_DATA
011 = 667MT/s FSB 010 = 800MT/s FSB
0 = DMI x 2 1 = DMI x 4
0 = Lane Reversal Enable 1 = Normal Operation
00 = Reserved 01 = XOR Mode Enabled 10 = All Z Mode Enabled 11 = Normal Operation
0 = Dynamic ODT Disabled 1 = Dynamic ODT Enabled
0 = Normal Operation 1 = DMI Lane Reversal Enable
0 = Only PCIE or SDVO is operational.
*
(Default)
1 = PCIE/SDVO are operating simu. 0 = No SDVO Device Present 1 = SDVO Device Present
R521 4.02K_0402_1%@R521 4.02K_0402_1%@ R522 4.02K_0402_1%@R522 4.02K_0402_1%@ R523 4.02K_0402_1%@R523 4.02K_0402_1%@ R524 4.02K_0402_1%@R524 4.02K_0402_1%@ R526 4.02K_0402_1%@R526 4.02K_0402_1%@
R529 4.02K_0402_1%@R529 4.02K_0402_1%@ R530 4.02K_0402_1%@R530 4.02K_0402_1%@
R532 10K_0402_5%
R532 10K_0402_5% R534 10K_0402_5%
R534 10K_0402_5% R536 10K_0402_5%
R536 10K_0402_5%
1 2
R578 0_0402_5%@R578 0_0402_5%@
1 2
R579 0_0402_5%@R579 0_0402_5%@
1
12/13 Modified from +1.05VS to +1.25VS by Intel recommend
1 2
R574 0_0402_5%PM@R574 0_0402_5%PM@
1 2
R575 0_0402_5%PM@R575 0_0402_5%PM@
1 2
R576 0_0402_5%PM@R576 0_0402_5%PM@
1 2
R577 0_0402_5%PM@R577 0_0402_5%PM@
Strap Pin Table
*
(Default)
*
(Default)
(Default)
*
* *
(Default)
(Default)
(Default)
*
+3VS
+3VS
+1.25VS
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2006/08/18 2007/8/18
2006/08/18 2007/8/18
2006/08/18 2007/8/18
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
Crestline (2/7)-DMI/DDR
Crestline (2/7)-DMI/DDR
Crestline (2/7)-DMI/DDR
IFTXX M/B LA-3541P Schematic
IFTXX M/B LA-3541P Schematic
IFTXX M/B LA-3541P Schematic
853Friday, February 09, 2007
853Friday, February 09, 2007
853Friday, February 09, 2007
of
of
1
of
0
0
0
5
4
3
2
1
DDRB_SDQ[0..63] DDRB_SDM[0..7] DDRB_SMA[0..13]
DDRA_SBS0 <14> DDRA_SBS1 <14> DDRA_SBS2 <14>
DDRA_SCAS# <14>
DDRA_SDQS0 <14> DDRA_SDQS1 <14> DDRA_SDQS2 <14>
DDRA_SDQS3 <14> DDRA_SDQS4 <14>
DDRA_SDQS5 <14>
DDRA_SDQS6 <14>
DDRA_SDQS7 <14>
DDRA_SDQS0# <14>
DDRA_SDQS1# <14>
DDRA_SDQS2# <14>
DDRA_SDQS3# <14>
DDRA_SDQS4# <14>
DDRA_SDQS5# <14>
DDRA_SDQS6# <14>
DDRA_SDQS7# <14>
DDRA_SRAS# <14>
PAD
PAD
T18
T18
DDRA_SWE# <14>
DDRB_SDQ0 DDRB_SDQ1 DDRB_SDQ2 DDRB_SDQ3 DDRB_SDQ4 DDRB_SDQ5 DDRB_SDQ6 DDRB_SDQ7 DDRB_SDQ8 DDRB_SDQ9 DDRB_SDQ10 DDRB_SDQ11 DDRB_SDQ12 DDRB_SDQ13 DDRB_SDQ14 DDRB_SDQ15 DDRB_SDQ16 DDRB_SDQ17 DDRB_SDQ18 DDRB_SDQ19 DDRB_SDQ20 DDRB_SDQ21 DDRB_SDQ22 DDRB_SDQ23 DDRB_SDQ24 DDRB_SDQ25 DDRB_SDQ26 DDRB_SDQ27 DDRB_SDQ28 DDRB_SDQ29 DDRB_SDQ30 DDRB_SDQ31 DDRB_SDQ32 DDRB_SDQ33 DDRB_SDQ34 DDRB_SDQ35 DDRB_SDQ36 DDRB_SDQ37 DDRB_SDQ38 DDRB_SDQ39 DDRB_SDQ40 DDRB_SDQ41 DDRB_SDQ42 DDRB_SDQ43 DDRB_SDQ44 DDRB_SDQ45 DDRB_SDQ46 DDRB_SDQ47 DDRB_SDQ48 DDRB_SDQ49 DDRB_SDQ50 DDRB_SDQ51 DDRB_SDQ52 DDRB_SDQ53 DDRB_SDQ54 DDRB_SDQ55 DDRB_SDQ56 DDRB_SDQ57 DDRB_SDQ58 DDRB_SDQ59 DDRB_SDQ60 DDRB_SDQ61 DDRB_SDQ62 DDRB_SDQ63
AP49
AR51 AW50 AW51
AN51
AN50
AV50
AV49
BA50
BB50
BA49
BE50
BA51
AY49
BF50
BF49
BJ50 BJ44
BJ43 BL43 BK47 BK49 BK43 BK42
BJ41 BL41
BJ37
BJ36 BK41
BJ40 BL35 BK37 BK13 BE11 BK11 BC11 BC13 BE12 BC12
BG12
BJ10
BK5 BL5 BK9
BK10
BF4 BH5 BG1 BC2
BK3
BE4 BD3
BA3
BB3 AR1
AT3
AY2
AY3 AU2
AT2
BL9
BJ8 BJ6
BJ2
U37E
U37E
SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63
CRESTLINE_1p0
CRESTLINE_1p0
PM@
PM@
AY17
SB_BS_0
BG18
SB_BS_1
BG36
SB_BS_2
BE17
SB_CAS# SB_DM_0
SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7
SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6
SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7
SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8
SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13
SB_RAS#
SB_RCVEN#
SB_WE#
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY B
AR50 BD49 BK45 BL39 BH12 BJ7 BF3 AW2
AT50 BD50 BK46 BK39 BJ12 BL7 BE2 AV2 AU50 BC50 BL45 BK38 BK12 BK7 BF2 AV3
BC18 BG28 BG25 AW17 BF25 BE25 BA29 BC28 AY28 BD37 BG17 BE37 BA39 BG13
AV16 AY18
BC17
DDRB_SDM0 DDRB_SDM1 DDRB_SDM2 DDRB_SDM3 DDRB_SDM4 DDRB_SDM5 DDRB_SDM6 DDRB_SDM7
DDRB_SDQS0 DDRB_SDQS1 DDRB_SDQS2 DDRB_SDQS3 DDRB_SDQS4 DDRB_SDQS5 DDRB_SDQS6 DDRB_SDQS7 DDRB_SDQS0# DDRB_SDQS1# DDRB_SDQS2# DDRB_SDQS3# DDRB_SDQS4# DDRB_SDQS5# DDRB_SDQS6# DDRB_SDQS7#
DDRB_SMA0 DDRB_SMA1 DDRB_SMA2 DDRB_SMA3 DDRB_SMA4 DDRB_SMA5 DDRB_SMA6 DDRB_SMA7 DDRB_SMA8 DDRB_SMA9 DDRB_SMA10 DDRB_SMA11 DDRB_SMA12 DDRB_SMA13
SB_RCVEN#
DDRB_SBS0 <15> DDRB_SBS1 <15> DDRB_SBS2 <15>
DDRB_SCAS# <15>
DDRB_SDQS0 <15> DDRB_SDQS1 <15> DDRB_SDQS2 <15> DDRB_SDQS3 <15> DDRB_SDQS4 <15> DDRB_SDQS5 <15> DDRB_SDQS6 <15> DDRB_SDQS7 <15> DDRB_SDQS0# <15> DDRB_SDQS1# <15> DDRB_SDQS2# <15> DDRB_SDQS3# <15> DDRB_SDQS4# <15> DDRB_SDQS5# <15> DDRB_SDQS6# <15> DDRB_SDQS7# <15>
DDRB_SRAS# <15>
PAD
PAD
T17
T17
DDRB_SWE# <15>
AR43
AW44
BA45 AY46 AR41 AR45 AT42
AW47
BB45 BF48 BG47
BJ45 BB47 BG50 BH49 BE45
AW43
BE44 BG42 BE40 BF44 BH45 BG40 BF40 AR40
AW40
AT39
AW36 AW41
AY41 AV38 AT38 AV13 AT13
AW11
AV11 AU15 AT11 BA13 BA11 BE10 BD10
BD8
BG10
AW9
BD7
AR5 AR8 AR9 AN3 AM8
AN10
AN9 AM9
AN11
AY9
BB9 BB5 AY7 AT5 AT7 AY6 BB7
AT9
DDRA_SDQ[0..63] DDRA_SDM[0..7] DDRA_SMA[0..13]
U37D
U37D
SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63
CRESTLINE_1p0
CRESTLINE_1p0
PM@
PM@
DDRB_SDQ[0..63]<15>
DDRB_SDM[0..7]<15>
DDRB_SMA[0..13]<15>
BB19
SA_BS_0
BK19
SA_BS_1
BF29
SA_BS_2
BL17
SA_CAS# SA_DM_0
SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7
SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6
SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7
SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8
SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13
SA_RAS#
SA_RCVEN#
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
SA_WE#
AT45 BD44 BD42 AW38 AW13 BG8 AY5 AN6
AT46 BE48 BB43 BC37 BB16 BH6 BB2 AP3 AT47 BD47 BC41 BA37 BA16 BH7 BC1 AP2
BJ19 BD20 BK27 BH28 BL24 BK28 BJ27 BJ25 BL28 BA28 BC19 BE28 BG30 BJ16
BE18 AY20
BA19
DDRA_SDM0 DDRA_SDM1 DDRA_SDM2 DDRA_SDM3 DDRA_SDM4 DDRA_SDM5 DDRA_SDM6 DDRA_SDM7
DDRA_SDQS0 DDRA_SDQS1 DDRA_SDQS2 DDRA_SDQS3 DDRA_SDQS4 DDRA_SDQS5 DDRA_SDQS6 DDRA_SDQS7 DDRA_SDQS0# DDRA_SDQS1# DDRA_SDQS2# DDRA_SDQS3# DDRA_SDQS4# DDRA_SDQS5# DDRA_SDQS6# DDRA_SDQS7#
DDRA_SMA0 DDRA_SMA1 DDRA_SMA2 DDRA_SMA3 DDRA_SMA4 DDRA_SMA5 DDRA_SMA6 DDRA_SMA7 DDRA_SMA8 DDRA_SMA9 DDRA_SMA10 DDRA_SMA11 DDRA_SMA12 DDRA_SMA13
SA_RCVEN#
DDRA_SDQ[0..63]<14>
D D
C C
B B
DDRA_SDM[0..7]<14>
DDRA_SMA[0..13]<14>
DDRA_SDQ0 DDRA_SDQ1 DDRA_SDQ2 DDRA_SDQ3 DDRA_SDQ4 DDRA_SDQ5 DDRA_SDQ6 DDRA_SDQ7 DDRA_SDQ8 DDRA_SDQ9 DDRA_SDQ10 DDRA_SDQ11 DDRA_SDQ12 DDRA_SDQ13 DDRA_SDQ14 DDRA_SDQ15 DDRA_SDQ16 DDRA_SDQ17 DDRA_SDQ18 DDRA_SDQ19 DDRA_SDQ20 DDRA_SDQ21 DDRA_SDQ22 DDRA_SDQ23 DDRA_SDQ24 DDRA_SDQ25 DDRA_SDQ26 DDRA_SDQ27 DDRA_SDQ28 DDRA_SDQ29 DDRA_SDQ30 DDRA_SDQ31 DDRA_SDQ32 DDRA_SDQ33 DDRA_SDQ34 DDRA_SDQ35 DDRA_SDQ36 DDRA_SDQ37 DDRA_SDQ38 DDRA_SDQ39 DDRA_SDQ40 DDRA_SDQ41 DDRA_SDQ42 DDRA_SDQ43 DDRA_SDQ44 DDRA_SDQ45 DDRA_SDQ46 DDRA_SDQ47 DDRA_SDQ48 DDRA_SDQ49 DDRA_SDQ50 DDRA_SDQ51 DDRA_SDQ52 DDRA_SDQ53 DDRA_SDQ54 DDRA_SDQ55 DDRA_SDQ56 DDRA_SDQ57 DDRA_SDQ58 DDRA_SDQ59 DDRA_SDQ60 DDRA_SDQ61 DDRA_SDQ62 DDRA_SDQ63
A A
Security Classification
Security Classification
Security Classification
2006/08/18 2007/8/18
2006/08/18 2007/8/18
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2006/08/18 2007/8/18
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
Date: Sheet
Date: Sheet
2
Date: Sheet of
Compal Electronics, Inc.
Crestline (3/7)-DDRII
Crestline (3/7)-DDRII
Crestline (3/7)-DDRII
IFTXX M/B LA-3541P Schematic
IFTXX M/B LA-3541P Schematic
IFTXX M/B LA-3541P Schematic
953Thursday, February 08, 2007
953Thursday, February 08, 2007
953Thursday, February 08, 2007
1
0
0
0
of
of
5
GMCH_ENBKL<18>
1 2
C792 100P_0402_50V8J
D D
C C
GMCH_ENVDD<18> PCIE_MTX_C_GRX_N[0..15] <17>
C792 100P_0402_50V8J
CRB 2.37K_1% to GND
GMCH_TV_COMPS<19> GMCH_TV_LUMA<19> GMCH_TV_CRMA<19>
R494
R494
GM@
GM@
150_0402_1%
150_0402_1%
GMCH_LCD_CLK<18>
GMCH_LCD_DATA<18>
R493 2.4K_0402_1%GM@R493 2.4K_0402_1%GM@
GMCH_TZCLK-<18> GMCH_TZCLK+<18> GMCH_TXCLK-<18> GMCH_TXCLK+<18>
R495
R495
1 2
1 2
GM@
GM@
150_0402_1%
150_0402_1%
1 2
GMCH_TZOUT0-<18> GMCH_TZOUT1-<18> GMCH_TZOUT2-<18>
GMCH_TZOUT0+<18> GMCH_TZOUT1+<18> GMCH_TZOUT2+<18>
GMCH_TXOUT0-<18> GMCH_TXOUT1-<18> GMCH_TXOUT2-<18>
GMCH_TXOUT0+<18> GMCH_TXOUT1+<18> GMCH_TXOUT2+<18>
R496
R496
GM@
GM@
150_0402_1%
150_0402_1%
1 2
Change to 0Ohm when use PM chip
GMCH_CRT_B<19> GMCH_CRT_G<19> GMCH_CRT_R<19>
B B
CRB 2.2K , Follow!
+3VS
A A
GMCH_CRT_CLK<19>
GMCH_CRT_DATA<19>
GMCH_CRT_HSYNC<19> GMCH_CRT_VSYNC<19>
R503 2.2K_0402_5%GM@ R503 2.2K_0402_5%GM@
1 2
R504 2.2K_0402_5%GM@R504 2.2K_0402_5%GM@
1 2
R505 10K_0402_5%GM@ R505 10K_0402_5%GM@
1 2
R506 10K_0402_5%GM@R506 10K_0402_5%GM@
1 2
R509 2.2K_0402_5%GM@R509 2.2K_0402_5%GM@ R510 2.2K_0402_5%GM@R510 2.2K_0402_5%GM@
1 2
R718 39_0402_1%GM@R718 39_0402_1%GM@
1 2
R719 39_0402_1%GM@R719 39_0402_1%GM@
5
R497 150_0402_1%GM@R497 150_0402_1%GM@ R498 150_0402_1%GM@R498 150_0402_1%GM@ R499 150_0402_1%GM@R499 150_0402_1%GM@
GMCH_LCD_CLK GMCH_LCD_DATA LCTLB_DATA LCTLA_CLK TV_DCONSEL_0 TV_DCONSEL_1
12 12 12
GMCH_CRT_CLK GMCH_CRT_DATA
R500
R500 0_0402_5%
0_0402_5%
PM@
PM@
R501
R501 0_0402_5%
0_0402_5%
PM@
PM@
4
U37C
U37C
J40
LBKLT_EN PEG_COMP LCTLA_CLK LCTLB_DATA GMCH_LCD_CLK GMCH_LCD_DATA GMCH_ENVDD
LVDS_IBG
1 2
R588 0_0402_5%GM@R588 0_0402_5%GM@
GMCH_TZCLK­GMCH_TZCLK+ GMCH_TXCLK­GMCH_TXCLK+
GMCH_TZOUT0­GMCH_TZOUT1­GMCH_TZOUT2-
GMCH_TZOUT0+ GMCH_TZOUT1+ GMCH_TZOUT2+
GMCH_TXOUT0­GMCH_TXOUT1­GMCH_TXOUT2-
GMCH_TXOUT0+ GMCH_TXOUT1+ GMCH_TXOUT2+
GMCH_TV_COMPS GMCH_TV_LUMA GMCH_TV_CRMA
TV_DCONSEL_0 TV_DCONSEL_1
CRT_IREF
R502
1
2
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
C793
C793
C794
C794
R502
1
1.3K_0402_1%
1.3K_0402_1%
1 2
2
R580 0_0402_5%PM@R580 0_0402_5%PM@
1 2
R581 0_0402_5%PM@R581 0_0402_5%PM@
1 2
R582 0_0402_5%PM@R582 0_0402_5%PM@
1 2
R583 0_0402_5%PM@R583 0_0402_5%PM@
1 2
R584 0_0402_5%PM@R584 0_0402_5%PM@
1 2
R585 0_0402_5%PM@R585 0_0402_5%PM@
1 2
R586 0_0402_5%PM@R586 0_0402_5%PM@
1 2
R587 0_0402_5%PM@R587 0_0402_5%PM@
1 2
4
H39
E39
E40 C37 D35
K40
L41
L43 N41 N40 D46 C45 D44
E42 G51
E51
F49
G50
E50
F48
G44
B47
B45
E44
A47
A45
E27 G27
K27
F27
J27
L27 M35
P33
H32 G32
K29
J29
F29
E29
K33 G35
F33 C32
E33
CRESTLINE_1p0
CRESTLINE_1p0
PM@
PM@
L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK L_CTRL_DATA L_DDC_CLK L_DDC_DATA L_VDD_EN
LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK
LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2
LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2
LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2
LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2
TVA_DAC TVB_DAC TVC_DAC
TVA_RTN TVB_RTN TVC_RTN
TV_DCONSEL_0 TV_DCONSEL_1
CRT_BLUE CRT_BLUE# CRT_GREEN CRT_GREEN# CRT_RED CRT_RED#
CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF CRT_VSYNC
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LVDS
LVDS
TV VGA
TV VGA
GMCH_LCD_CLK GMCH_LCD_DATA LCTLB_DATA LCTLA_CLK GMCH_CRT_CLK GMCH_CRT_DATA TV_DCONSEL_0 TV_DCONSEL_1
3
PEG_COMPI
PEG_COMPO
PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8
PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15
PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8
PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15
PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9
PEG_TX#_10
PCI-EXPRESS GRAPHICS
PCI-EXPRESS GRAPHICS
PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15
PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15
2006/08/18 2007/8/18
2006/08/18 2007/8/18
2006/08/18 2007/8/18
3
2
N43 M43
J51 L51 N47 T45 T50 U40 Y44 Y40 AB51 W49 AD44 AD40 AG46 AH49 AG45 AG41
J50 L50 M47 U44 T49 T41 W45 W41 AB50 Y48 AC45 AC41 AH47 AG49 AH45 AG42
N45 U39 U47 N51 R50 T42 Y43 W46 W38 AD39 AC46 AC49 AC42 AH39 AE49 AH44
M45 T38 T46 N50 R51 U43 W42 Y47 Y39 AC38 AD47 AC50 AD43 AG39 AE50 AH43
R589 0_0402_5%PM@R589 0_0402_5%PM@ R590 0_0402_5%PM@R590 0_0402_5%PM@ R591 0_0402_5%PM@R591 0_0402_5%PM@ R592 0_0402_5%PM@R592 0_0402_5%PM@ R593 0_0402_5%PM@R593 0_0402_5%PM@ R594 0_0402_5%PM@R594 0_0402_5%PM@
20/25mils
PCIE_GTX_C_MRX_N0 PCIE_GTX_C_MRX_N1 PCIE_GTX_C_MRX_N2 PCIE_GTX_C_MRX_N3 PCIE_GTX_C_MRX_N4 PCIE_GTX_C_MRX_N5 PCIE_GTX_C_MRX_N6 PCIE_GTX_C_MRX_N7 PCIE_GTX_C_MRX_N8 PCIE_GTX_C_MRX_N9 PCIE_GTX_C_MRX_N10 PCIE_GTX_C_MRX_N11 PCIE_GTX_C_MRX_N12 PCIE_GTX_C_MRX_N13 PCIE_GTX_C_MRX_N14 PCIE_GTX_C_MRX_N15
PCIE_GTX_C_MRX_P0 PCIE_GTX_C_MRX_P1 PCIE_GTX_C_MRX_P2 PCIE_GTX_C_MRX_P3 PCIE_GTX_C_MRX_P4 PCIE_GTX_C_MRX_P5 PCIE_GTX_C_MRX_P6 PCIE_GTX_C_MRX_P7 PCIE_GTX_C_MRX_P8 PCIE_GTX_C_MRX_P9 PCIE_GTX_C_MRX_P10 PCIE_GTX_C_MRX_P11 PCIE_GTX_C_MRX_P12 PCIE_GTX_C_MRX_P13 PCIE_GTX_C_MRX_P14 PCIE_GTX_C_MRX_P15
PCIE_MTX_GRX_N0 PCIE_MTX_GRX_N1 PCIE_MTX_GRX_N2 PCIE_MTX_GRX_N3 PCIE_MTX_GRX_N4 PCIE_MTX_C_GRX_N4 PCIE_MTX_GRX_N5 PCIE_MTX_GRX_N6 PCIE_MTX_GRX_N7 PCIE_MTX_GRX_N8 PCIE_MTX_GRX_N9 PCIE_MTX_GRX_N10 PCIE_MTX_GRX_N11 PCIE_MTX_GRX_N12 PCIE_MTX_GRX_N13 PCIE_MTX_GRX_N14 PCIE_MTX_GRX_N15
PCIE_MTX_GRX_P0 PCIE_MTX_GRX_P1 PCIE_MTX_GRX_P2 PCIE_MTX_GRX_P3 PCIE_MTX_GRX_P4 PCIE_MTX_GRX_P5 PCIE_MTX_GRX_P6 PCIE_MTX_GRX_P7 PCIE_MTX_GRX_P8 PCIE_MTX_GRX_P9 PCIE_MTX_GRX_P10 PCIE_MTX_GRX_P11 PCIE_MTX_GRX_P12 PCIE_MTX_GRX_P13 PCIE_MTX_GRX_P14 PCIE_MTX_GRX_P15
1 2 1 2 1 2 1 2 1 2 1 2
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
1 2
R492 24.9_0402_1%
R492 24.9_0402_1%
C604 0.1U_0402_10V7KPM@C604 0.1U_0402_10V7KPM@
1 2
C606 0.1U_0402_10V7KPM@C606 0.1U_0402_10V7KPM@
1 2
C608 0.1U_0402_10V7KPM@C608 0.1U_0402_10V7KPM@
1 2
C610 0.1U_0402_10V7KPM@C610 0.1U_0402_10V7KPM@
1 2
C612 0.1U_0402_10V7KPM@C612 0.1U_0402_10V7KPM@
1 2
C614 0.1U_0402_10V7KPM@C614 0.1U_0402_10V7KPM@
1 2
C616 0.1U_0402_10V7KPM@C616 0.1U_0402_10V7KPM@
1 2
C618 0.1U_0402_10V7KPM@C618 0.1U_0402_10V7KPM@
1 2
C620 0.1U_0402_10V7KPM@C620 0.1U_0402_10V7KPM@
1 2
C622 0.1U_0402_10V7KPM@C622 0.1U_0402_10V7KPM@
1 2
C624 0.1U_0402_10V7KPM@C624 0.1U_0402_10V7KPM@
1 2
C626 0.1U_0402_10V7KPM@C626 0.1U_0402_10V7KPM@
1 2
C628 0.1U_0402_10V7KPM@C628 0.1U_0402_10V7KPM@
1 2
C630 0.1U_0402_10V7KPM@C630 0.1U_0402_10V7KPM@
1 2
C632 0.1U_0402_10V7KPM@C632 0.1U_0402_10V7KPM@
1 2
C634 0.1U_0402_10V7KPM@C634 0.1U_0402_10V7KPM@
1 2
GMCH_CRT_B GMCH_CRT_G GMCH_CRT_R GMCH_TV_COMPS GMCH_TV_LUMA GMCH_TV_CRMA
+1.05VS
C603 0.1U_0402_10V7KPM@C603 0.1U_0402_10V7KPM@ C605 0.1U_0402_10V7KPM@C605 0.1U_0402_10V7KPM@ C607 0.1U_0402_10V7KPM@C607 0.1U_0402_10V7KPM@ C609 0.1U_0402_10V7KPM@C609 0.1U_0402_10V7KPM@ C611 0.1U_0402_10V7KPM@C611 0.1U_0402_10V7KPM@ C613 0.1U_0402_10V7KPM@C613 0.1U_0402_10V7KPM@ C615 0.1U_0402_10V7KPM@C615 0.1U_0402_10V7KPM@ C617 0.1U_0402_10V7KPM@C617 0.1U_0402_10V7KPM@
C619 0.1U_0402_10V7KPM@C619 0.1U_0402_10V7KPM@ C621 0.1U_0402_10V7KPM@C621 0.1U_0402_10V7KPM@ C623 0.1U_0402_10V7KPM@C623 0.1U_0402_10V7KPM@ C625 0.1U_0402_10V7KPM@C625 0.1U_0402_10V7KPM@ C627 0.1U_0402_10V7KPM@C627 0.1U_0402_10V7KPM@ C629 0.1U_0402_10V7KPM@C629 0.1U_0402_10V7KPM@ C631 0.1U_0402_10V7KPM@C631 0.1U_0402_10V7KPM@ C633 0.1U_0402_10V7KPM@C633 0.1U_0402_10V7KPM@
2
PCIE_MTX_C_GRX_N[0..15] PCIE_MTX_C_GRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15] PCIE_GTX_C_MRX_P[0..15]
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
IFTXX M/B LA-3541P Schematic
IFTXX M/B LA-3541P Schematic
IFTXX M/B LA-3541P Schematic
1
PCIE_MTX_C_GRX_P[0..15] <17>
PCIE_GTX_C_MRX_N[0..15] <17>
PCIE_GTX_C_MRX_P[0..15] <17>
PCIE_MTX_C_GRX_N0 PCIE_MTX_C_GRX_N1 PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_N5 PCIE_MTX_C_GRX_N6 PCIE_MTX_C_GRX_N7 PCIE_MTX_C_GRX_N8 PCIE_MTX_C_GRX_N9 PCIE_MTX_C_GRX_N10 PCIE_MTX_C_GRX_N11 PCIE_MTX_C_GRX_N12 PCIE_MTX_C_GRX_N13 PCIE_MTX_C_GRX_N14 PCIE_MTX_C_GRX_N15
PCIE_MTX_C_GRX_P0 PCIE_MTX_C_GRX_P1 PCIE_MTX_C_GRX_P2 PCIE_MTX_C_GRX_P3 PCIE_MTX_C_GRX_P4 PCIE_MTX_C_GRX_P5 PCIE_MTX_C_GRX_P6 PCIE_MTX_C_GRX_P7 PCIE_MTX_C_GRX_P8 PCIE_MTX_C_GRX_P9 PCIE_MTX_C_GRX_P10 PCIE_MTX_C_GRX_P11 PCIE_MTX_C_GRX_P12 PCIE_MTX_C_GRX_P13 PCIE_MTX_C_GRX_P14 PCIE_MTX_C_GRX_P15
Crestline (4/7)-VGA/LVDS/TV
Crestline (4/7)-VGA/LVDS/TV
Crestline (4/7)-VGA/LVDS/TV
10 53Friday, February 09, 2007
10 53Friday, February 09, 2007
10 53Friday, February 09, 2007
1
0
0
0
of
of
of
5
U37G
U37G
+1.05VS
D D
Replace 0 Ohm by directly connection
C C
B B
A A
+1.8V
+VCC_AXG
AT35 AT34 AH28 AC32 AC31 AK32
AJ31
AJ28 AH32 AH31 AH29 AF32
R30
AU32 AU33 AU35 AV33
AW33 AW35
AY35 BA32 BA33 BA35 BB33 BC32 BC33 BC35 BD32 BD35 BE32 BE33 BE35 BF33 BF34 BG32 BG33 BG35 BH32 BH34 BH35
BJ32
BJ33
BJ34 BK32 BK33 BK34 BK35 BL33 AU30
R20
W13 W14
Y12 AA20 AA23 AA26 AA28 AB21 AB24 AB29 AC20 AC21 AC23 AC24 AC26 AC28 AC29 AD20 AD23 AD24 AD28 AF21 AF26 AA31 AH20 AH21 AH23 AH24 AH26 AD31
AJ20
AN14
T14
VCC_1 VCC_2 VCC_3 VCC_5 VCC_4 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12
VCC_13
VCC_SM_1 VCC_SM_2 VCC_SM_3 VCC_SM_4 VCC_SM_5 VCC_SM_6 VCC_SM_7 VCC_SM_8 VCC_SM_9 VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33 VCC_SM_34 VCC_SM_35 VCC_SM_36
VCC_AXG_1 VCC_AXG_2 VCC_AXG_3 VCC_AXG_4 VCC_AXG_5 VCC_AXG_6 VCC_AXG_7 VCC_AXG_8 VCC_AXG_9 VCC_AXG_10 VCC_AXG_11 VCC_AXG_12 VCC_AXG_13 VCC_AXG_14 VCC_AXG_15 VCC_AXG_16 VCC_AXG_17 VCC_AXG_18 VCC_AXG_19 VCC_AXG_20 VCC_AXG_21 VCC_AXG_22 VCC_AXG_23 VCC_AXG_24 VCC_AXG_25 VCC_AXG_26 VCC_AXG_27 VCC_AXG_28 VCC_AXG_29 VCC_AXG_30 VCC_AXG_31 VCC_AXG_32 VCC_AXG_33 VCC_AXG_34
VCC CORE
VCC CORE
POWER
POWER
VCC SMVCC GFX
VCC SMVCC GFX
VCC_AXG_NCTF_1 VCC_AXG_NCTF_2 VCC_AXG_NCTF_3 VCC_AXG_NCTF_4 VCC_AXG_NCTF_5 VCC_AXG_NCTF_6 VCC_AXG_NCTF_7 VCC_AXG_NCTF_8
VCC_AXG_NCTF_9 VCC_AXG_NCTF_10 VCC_AXG_NCTF_11 VCC_AXG_NCTF_12 VCC_AXG_NCTF_13 VCC_AXG_NCTF_14 VCC_AXG_NCTF_15 VCC_AXG_NCTF_16 VCC_AXG_NCTF_17 VCC_AXG_NCTF_18 VCC_AXG_NCTF_19 VCC_AXG_NCTF_20 VCC_AXG_NCTF_21 VCC_AXG_NCTF_22 VCC_AXG_NCTF_23 VCC_AXG_NCTF_24 VCC_AXG_NCTF_25 VCC_AXG_NCTF_26 VCC_AXG_NCTF_27 VCC_AXG_NCTF_28 VCC_AXG_NCTF_29 VCC_AXG_NCTF_30 VCC_AXG_NCTF_31 VCC_AXG_NCTF_32 VCC_AXG_NCTF_33 VCC_AXG_NCTF_34 VCC_AXG_NCTF_35 VCC_AXG_NCTF_36 VCC_AXG_NCTF_37 VCC_AXG_NCTF_38 VCC_AXG_NCTF_39 VCC_AXG_NCTF_40 VCC_AXG_NCTF_41 VCC_AXG_NCTF_42 VCC_AXG_NCTF_43 VCC_AXG_NCTF_44 VCC_AXG_NCTF_45 VCC_AXG_NCTF_46 VCC_AXG_NCTF_47 VCC_AXG_NCTF_48 VCC_AXG_NCTF_49 VCC_AXG_NCTF_50 VCC_AXG_NCTF_51 VCC_AXG_NCTF_52 VCC_AXG_NCTF_53 VCC_AXG_NCTF_54
VCC GFX NCTF
VCC GFX NCTF
VCC_AXG_NCTF_55 VCC_AXG_NCTF_56 VCC_AXG_NCTF_57 VCC_AXG_NCTF_58 VCC_AXG_NCTF_59 VCC_AXG_NCTF_60 VCC_AXG_NCTF_61 VCC_AXG_NCTF_62 VCC_AXG_NCTF_63 VCC_AXG_NCTF_64 VCC_AXG_NCTF_65 VCC_AXG_NCTF_66 VCC_AXG_NCTF_67 VCC_AXG_NCTF_68 VCC_AXG_NCTF_69 VCC_AXG_NCTF_70 VCC_AXG_NCTF_71 VCC_AXG_NCTF_72 VCC_AXG_NCTF_73 VCC_AXG_NCTF_74 VCC_AXG_NCTF_75 VCC_AXG_NCTF_76 VCC_AXG_NCTF_77 VCC_AXG_NCTF_78 VCC_AXG_NCTF_79 VCC_AXG_NCTF_80 VCC_AXG_NCTF_81 VCC_AXG_NCTF_82 VCC_AXG_NCTF_83
VCC SM LF
VCC SM LF
VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7
4
9/18 modify from +1.05VS to +VCC_AXG
T17 T18 T19 T21 T22 T23 T25 U15 U16 U17 U19 U20 U21 U23 U26 V16 V17 V19 V20 V21 V23 V24 Y15 Y16 Y17 Y19 Y20 Y21 Y23 Y24 Y26 Y28 Y29 AA16 AA17 AB16 AB19 AC16 AC17 AC19 AD15 AD16 AD17 AF16 AF19 AH15 AH16 AH17 AH19 AJ16 AJ17 AJ19 AK16 AK19 AL16 AL17 AL19 AL20 AL21 AL23 AM15 AM16 AM19 AM20 AM21 AM23 AP15 AP16 AP17 AP19 AP20 AP21 AP23 AP24 AR20 AR21 AR23 AR24 AR26 V26 V28 V29 Y31
AW45 BC39 BE39 BD17 BD4 AW8 AT6
+VCC_AXG
VCC: 1573mA
+1.05VS
(220UF*1, 22UF*1, 0.22UF*2, 0.1UF*1)
1
+
+
C573
C573
220U_D2_2VMR15
220U_D2_2VMR15
2
C578
C578
330U_D2E_2.5VM
330U_D2E_2.5VM
22U_0805_6.3V6M
22U_0805_6.3V6M
VCC_SM: 3300mA
+1.8V
(330UF*1, 22UF*2, 0.1UF*1)
1
+
+
2
22U_0805_6.3V6M@
22U_0805_6.3V6M@
9/18 modify from +1.05VS to +VCC_AXG 9/18 Add for 965PM use
VCC_AXG: 7700mA (330UF*2, 22UF*1, 10UF*1, 1U*1, 0.47U*1, 0.1UF*2)
1
C583
C583
+
+
2
GM@
GM@
330U_D2E_2.5VM
330U_D2E_2.5VM
+1.05VS
1
C597
C597
0.22U_0603_16V7K
0.22U_0603_16V7K
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
VCCSM_LF1 VCCSM_LF2 VCCSM_LF3 VCCSM_LF4 VCCSM_LF5 VCCSM_LF6 VCCSM_LF7
C596
C596
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+VCC_AXG
C582
C582
330U_D2E_2.5VM
330U_D2E_2.5VM
GM@
GM@
1
2
3
CRB 270uF , there is no 270u part. 9/19 change to 330u, 9/29 change to 220u 12/19 Modify C573 to correct description ( symbol change )
1
C574
C574
0.22U_0603_16V7K
0.22U_0603_16V7K
2
C575
C575
0.22U_0603_16V7K
0.22U_0603_16V7K
1
C576
C576
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C577
C577
Follow DG 1.1
9/14 add for reservation
C579
C579
22U_0805_6.3V6M
22U_0805_6.3V6M
C584
C584
+
+
22U_0805_6.3V6M
22U_0805_6.3V6M
GM@
GM@
C590
C590 22U_0805_6.3V6M
22U_0805_6.3V6M
1
C580
C580
C692
C692
1U_0603_10V4Z
2
4.7U_0805_10V4Z
4.7U_0805_10V4Z
C585
C585
1
2
GM@
GM@
10U_0805_10V4Z
10U_0805_10V4Z
1
C591
C591
2
0.22U_0603_16V7K
0.22U_0603_16V7K
1U_0603_10V4Z
C586
C586
1
1U_0603_10V4Z
1U_0603_10V4Z
2
GM@
GM@
VCC_AXM: 540mA (22UF*2, 0.22UF*2, 0.1UF*2)
C592
C592
0.22U_0603_16V7K
0.22U_0603_16V7K
1
C581
C581
2
0.1U_0402_16V4Z@
0.1U_0402_16V4Z@
C587
C587
GM@
GM@
0.47U_0603_16V4Z
0.47U_0603_16V4Z
1
C593
C593
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C690
C690
C588
C588
0.1U_0402_16V4Z
0.1U_0402_16V4Z
GM@
GM@
C594
C594
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
1
2
1
2
1
2
9/29 +1.05VS_AXM change to +1.05VS
+1.05VS +VCC_AXG
C598
C598
0.22U_0603_16V7K
0.22U_0603_16V7K
C599
C599
J6
J6
1 2
PAD-OPEN 3x3m
PAD-OPEN 3x3m
@
@
C600
C600
0.47U_0603_16V4Z
0.47U_0603_16V4Z
C601
C601
1U_0603_10V4Z
1U_0603_10V4Z
1005 This is for GM@ Remember open stencil at GM@
C602
C602 1U_0603_10V4Z
1U_0603_10V4Z
C691
C691 1U_0603_10V4Z
1U_0603_10V4Z
@
@
C589
C589
1
2
GM@
GM@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C595
C595
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
U37F
U37F
+1.05VS
R609
R609 0_0805_5%
0_0805_5%
PM@
PM@
+1.05VS
AB33
VCC_NCTF_1
AB36
VCC_NCTF_2
AB37
VCC_NCTF_3
AC33
VCC_NCTF_4
AC35
VCC_NCTF_5
AC36
VCC_NCTF_6
AD35
VCC_NCTF_7
AD36
VCC_NCTF_8
AF33
VCC_NCTF_9
AF36
VCC_NCTF_10
AH33
VCC_NCTF_11
AH35
VCC_NCTF_12
AH36
VCC_NCTF_13
AH37
VCC_NCTF_14
AJ33
VCC_NCTF_15
AJ35
VCC_NCTF_16
AK33
VCC_NCTF_17
AK35
VCC_NCTF_18
AK36
VCC_NCTF_19
AK37
VCC_NCTF_20
AD33
VCC_NCTF_21
AJ36
VCC_NCTF_22
AM35
VCC_NCTF_23
AL33
VCC_NCTF_24
AL35
VCC_NCTF_25
AA33
VCC_NCTF_26
AA35
VCC_NCTF_27
AA36
VCC_NCTF_28
AP35
VCC_NCTF_29
AP36
VCC_NCTF_30
AR35
VCC_NCTF_31
AR36
VCC_NCTF_32
Y32
VCC_NCTF_33
Y33
VCC_NCTF_34
Y35
VCC_NCTF_35
Y36
VCC_NCTF_36
Y37
VCC_NCTF_37
T30
VCC_NCTF_38
T34
VCC_NCTF_39
T35
VCC_NCTF_40
U29
VCC_NCTF_41
U31
VCC_NCTF_42
U32
VCC_NCTF_43
U33
VCC_NCTF_44
U35
VCC_NCTF_45
U36
VCC_NCTF_46
V32
VCC_NCTF_47
V33
VCC_NCTF_48
V36
VCC_NCTF_49
V37
VCC_NCTF_50
AL24
VCC_AXM_NCTF_1
AL26
VCC_AXM_NCTF_2
AL28
VCC_AXM_NCTF_3
AM26
VCC_AXM_NCTF_4
AM28
VCC_AXM_NCTF_5
AM29
VCC_AXM_NCTF_6
AM31
VCC_AXM_NCTF_7
AM32
VCC_AXM_NCTF_8
AM33
VCC_AXM_NCTF_9
AP29
VCC_AXM_NCTF_10
AP31
VCC_AXM_NCTF_11
AP32
VCC_AXM_NCTF_12
AP33
VCC_AXM_NCTF_13
AL29
VCC_AXM_NCTF_14
AL31
VCC_AXM_NCTF_15
AL32
VCC_AXM_NCTF_16
AR31
VCC_AXM_NCTF_17
AR32
VCC_AXM_NCTF_18
AR33
VCC_AXM_NCTF_19
CRESTLINE_1p0
CRESTLINE_1p0
PM@
PM@
VCC NCTF
VCC NCTF
POWER
POWER
VCC AXM NCTF
VCC AXM NCTF
VSS NCTF
VSS NCTF
VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8
VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21
VSS_SCB1 VSS_SCB2 VSS_SCB3 VSS_SCB4 VSS_SCB5 VSS_SCB6
VSS SCBVCC AXM
VSS SCBVCC AXM
VCC_AXM_1 VCC_AXM_2 VCC_AXM_3 VCC_AXM_4 VCC_AXM_5 VCC_AXM_6 VCC_AXM_7
1
T27 T37 U24 U28 V31 V35 AA19 AB17 AB35 AD19 AD37 AF17 AF35 AK17 AM17 AM24 AP26 AP28 AR15 AR19 AR28
A3 B2 C1 BL1 BL51 A51
AT33 AT31 AK29 AK24 AK23 AJ26 AJ23
+1.05VS
9/29 +1.05VS_AXM change to +1.05VS
CRESTLINE_1p0
CRESTLINE_1p0
PM@
PM@
9/18 modify from +1.05VS to +VCC_AXG
5
Security Classification
Security Classification
Security Classification
2006/08/18 2007/8/18
2006/08/18 2007/8/18
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2006/08/18 2007/8/18
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
Date: Sheet
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
Crestline (5/7)-VCC
Crestline (5/7)-VCC
Crestline (5/7)-VCC
IFTXX M/B LA-3541P Schematic
IFTXX M/B LA-3541P Schematic
IFTXX M/B LA-3541P Schematic
11 53Thursday, February 08, 2007
11 53Thursday, February 08, 2007
11 53Thursday, February 08, 2007
of
of
of
1
0
0
0
5
C521
C513
C513
0_0402_5%
0_0402_5%
PM@
PM@
D D
12/13 Modified this block for Intel recommend 12/19 Add C773 and C774 for reservation
+1.25VS
C C
VCC_SYNC: 10mA (0.1UF*1)
+3VS
VCCA_CRT_DAC: 80mA (0.1UF*1, 0.022UF*1)
+3VS
B B
VCCA_DAC_BG: 5mA (0.1UF*1, 0.022UF*1)
+3VS
+3VS
A A
+1.5VS
1/18 Change from PM@ to @
C521
0_0402_5%
0_0402_5%
PM@
PM@
VCCA_HPLL: 50mA (22UF*1, 0.1UF*1)
L39
L39
1 2
MBK1608121YZF_0603
MBK1608121YZF_0603
VCCA_MPLL:150mA (10UF*1, 0.1UF*1)
L41
L41
1 2
MBK1608121YZF_0603
MBK1608121YZF_0603
R476 0_0402_5%
R476 0_0402_5%
GM@
GM@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
L46
L46
1 2
MBK1608121YZF_0603
MBK1608121YZF_0603
GM@
GM@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
L49
L49
1 2
MBK1608121YZF_0603
MBK1608121YZF_0603
GM@
GM@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
L52
L52 MBK1608121YZF_0603
MBK1608121YZF_0603
GM@
GM@
L53
L53 MBK1608121YZF_0603
MBK1608121YZF_0603
VCCA_TV_DAC: 40mA each DAC (0.1UF*1, 0.022UF*1 for each DAC)
1 2
1 2
C689
C689
10U_0805_10V4Z
10U_0805_10V4Z
@
@
+1.25VS_DPLLA
1
C773
C773
@
@
2
10U_0805_6.3V6M
10U_0805_6.3V6M
C511
C511
22U_0805_6.3V6M
22U_0805_6.3V6M
R471
R471
0.5_0603_1%
0.5_0603_1%
C522
C522
22U_0805_6.3V6M
22U_0805_6.3V6M
+3VS_SYNC
1
C536
C536
2
GM@
GM@
1
C546
C546
2
GM@
GM@
1
C552
C552
2
GM@
GM@
1
C564
C564
C563
C563
GM@
GM@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
10U_0805_10V4Z
10U_0805_10V4Z
GM@
GM@
+1.5VS_TVDAC
+1.5VS
1
2
5
VCCA_DPLLA/B: 100mA (470UF*1, 0.1UF*1)
L40
L40
+1.25VS
+1.25VS_HPLL
1
2
1
2
C547
C547
C553
C553
GM@
GM@
1
C512
C512
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
+1.25VS_MPLL
1
C520
C520
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
+1.25VS
R477
R477 0_0402_5%
0_0402_5%
PM@
PM@
GM@
GM@
1
2
+1.25VS
+3VS_CRTDAC
R481
R481 0_0402_5%
0_0402_5%
PM@
PM@
0.022U_0402_16V7K
0.022U_0402_16V7K
+3VS_DACBG
R482
R482 0_0402_5%
0_0402_5%
PM@
PM@
0.022U_0402_16V7K
0.022U_0402_16V7K
0206 Add
C566
C566
C565
C565
GM@
GM@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.022U_0402_16V7K
0.022U_0402_16V7K
GM@
GM@
1/05 Modified L54 to 100 Ohm _0603
L54
L54
1 2
100_0603_5%
100_0603_5%
GM@
GM@
1 2
10U_FLC-453232-100K_0.25A_10%
10U_FLC-453232-100K_0.25A_10%
@
@
L61
L61
1 2
MBK1608121YZF_0603
MBK1608121YZF_0603
GM@
GM@
L62
L62
1 2
MBK1608121YZF_0603
MBK1608121YZF_0603
GM@
GM@
L42
L42
1 2
10U_FLC-453232-100K_0.25A_10%
10U_FLC-453232-100K_0.25A_10%
@
@
VCCA_DPLLA/B: 100mA (470UF*1, 0.1UF*1)
+1.25VS
C529
C529 10U_0805_10V4Z
10U_0805_10V4Z
1 2
R475 0_0805_5%R475 0_0805_5%
R479 0_0603_5%
R479 0_0603_5%
+1.5VS_TVDAC
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C795
C795 10U_0805_10V4Z
10U_0805_10V4Z
2
GM@
GM@
1
C567
C567
C568
C568
GM@
GM@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
0.022U_0402_16V7K
0.022U_0402_16V7K
GM@
GM@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
12
4
+1.25VS_DPLLA
1
1
+
+
C513
C510
C510
GM@
GM@
220U_D2_2VMR15
220U_D2_2VMR15
1
+
+
C519
C519
220U_D2_2VMR15
220U_D2_2VMR15
+1.8V_TX_LVDS
+3VS
0.1U_0402_16V4Z
0.1U_0402_16V4Z
L43
L43
1 2
MBK1608121YZF_0603
MBK1608121YZF_0603
R474 1_0603_5%
R474 1_0603_5%
+1.25VS_A_SM_CK
C540
C540
22U_0805_6.3V6M
22U_0805_6.3V6M
VCCD_TVDAC / CRT: each 60mA (0.1UF*1, 0.022UF*1)
C548
C548
1
C569
C569
2
0.022U_0402_16V7K
0.022U_0402_16V7K
GM@
GM@
VCCD_QDAC: 5mA (0.1UF*1, 0.022UF*1)
1
C571
C571
2
GM@
GM@
1/05 Modified R488 to 1U_0402
2
GM@
GM@
C525
C525
1000P_0402_50V7K
1000P_0402_50V7K
GM@
GM@
1
C526
C526
+1.25VS_A_SM
C532
C532 22U_0805_6.3V6M
22U_0805_6.3V6M
@
@
1
2
1
2
VCCA_PEG_PLL: 100mA (0.1UF*1)
C572
C572
0.022U_0402_16V7K
0.022U_0402_16V7K
GM@
GM@
4
VCCA_PEG_BG: 5mA (0.1UF*1)
2
+1.25VS_A_PEGPLL
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C533
C533
2
22U_0805_6.3V6M
22U_0805_6.3V6M
VCCA_SM_CK: 35mA (22UF*1, 1UF*2, 0.1UF*1)
C541
C541
@
@
1U_0603_10V4Z
1U_0603_10V4Z
R572 0_0402_5%
R572 0_0402_5%
C549
C549
0.022U_0402_16V7K
0.022U_0402_16V7K
VCCD_HPLL: 250mA (0.1UF*1)
+1.25VS
C554
C554
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+3VS_A_TVDAC
R485
R485 0_0402_5%
0_0402_5%
PM@
PM@
C513
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
GM@
GM@
+3VS_SYNC
+1.25VS_DPLLB
C521
C521
GM@
GM@
1
2
C530
C530
VCCA_SM: 640mA (22UF*21, 4.7UF*1, 1UF*1)
1
2
C542
C542
1U_0603_10V4Z
1U_0603_10V4Z
+3VS_A_TVDAC
GM@
GM@
1
2
+1.5VS_QDAC
+3VS_CRTDAC
+3VS_DACBG
1
+1.25VS_DPLLA
2
+1.25VS_DPLLB
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+1.25VS_HPLL +1.25VS_MPLL
VCCA_LVDS: 10mA (0.1UF*1)
1
VCCA_PEG_PLL: 100mA (0.1UF*1)
2
C534
C534
4.7U_0805_10V4Z
4.7U_0805_10V4Z
@
@
R573
R573
+1.8V
R488
R488 1U_0402_6.3V4Z
1U_0402_6.3V4Z
GM@
GM@
C535
C535
1U_0603_10V4Z
1U_0603_10V4Z
C543
C543
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0_0402_5%
0_0402_5%
PM@
PM@
+1.25VS_A_PEGPLL
C555
C555
0.1U_0402_16V4Z
0.1U_0402_16V4Z
R483 0_0402_5%
R483 0_0402_5%
10U_0805_10V4Z
10U_0805_10V4Z
Security Classification
Security Classification
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
2
VCCD_CRT
+1.5VS_TVDAC
+1.5VS_QDAC
1
2
GM@
GM@
VCCD_LVDS: 150mA (10UF*1, 0.1UF*1)
Issued Date
Issued Date
Issued Date
C561
C561
@
@
J32
A33 B33
A30 B32
B49
H49
AL2
AM2
A41 B41
K50 K49
U51
AW18
AV19 AU19 AU18 AU17
AT22 AT21 AT19 AT18 AT17 AR17 AR16
BC29 BB29
C25
B25
C27
B27 B28 A28
M32
L29 N28 AN2 U48
J41
H42
+1.8V_LVDS
1
C562
C562
2
GM@
GM@
1U_0603_10V4Z
1U_0603_10V4Z
3
U37H
U37H
VCCSYNC VCCA_CRT_DAC_1
VCCA_CRT_DAC_2
VCCA_DAC_BG VSSA_DAC_BG
VCCA_DPLLA VCCA_DPLLB VCCA_HPLL VCCA_MPLL
VCCA_LVDS VSSA_LVDS
VCCA_PEG_BG VSSA_PEG_BG
VCCA_PEG_PLL
VCCA_SM_1 VCCA_SM_2 VCCA_SM_3 VCCA_SM_4 VCCA_SM_5
VCCA_SM_7 VCCA_SM_8 VCCA_SM_9 VCCA_SM_10 VCCA_SM_11 VCCA_SM_NCTF_1 VCCA_SM_NCTF_2
VCCA_SM_CK_1 VCCA_SM_CK_2
VCCA_TVA_DAC_1 VCCA_TVA_DAC_2 VCCA_TVB_DAC_1 VCCA_TVB_DAC_2 VCCA_TVC_DAC_1 VCCA_TVC_DAC_2
VCCD_CRT VCCD_TVDAC
VCCD_QDAC VCCD_HPLL VCCD_PEG_PLL VCCD_LVDS_1
VCCD_LVDS_2
CRESTLINE_1p0
CRESTLINE_1p0
PM@
PM@
2006/08/18 2007/8/18
2006/08/18 2007/8/18
2006/08/18 2007/8/18
3
CRTPLLA PEGA SMTV
CRTPLLA PEGA SMTV
AXD
AXD
VCC_AXD_NCTF
POWER
POWER
SM CK
SM CK
A CK A LVDS
A CK A LVDS
VCC_RXR_DMI_1 VCC_RXR_DMI_2
DMI
DMI
D TV/CRTLVDS
D TV/CRTLVDS
R484
R484 0_0402_5%
0_0402_5%
PM@
PM@
R488
R488
0_0402_5%
0_0402_5%
PM@
PM@
1/18 Add 0_0402 for PM use
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
VCC_AXD_1
VCC_AXD_2 VCC_AXD_3
VCC_AXD_4
VCC_AXD_5
VCC_AXD_6
VCC_AXF_1 VCC_AXF_2 VCC_AXF_3
AXF
AXF
VCC_SM_CK_1 VCC_SM_CK_2 VCC_SM_CK_3 VCC_SM_CK_4
VCC_TX_LVDS
HV
HV
VCC_PEG_1 VCC_PEG_2 VCC_PEG_3 VCC_PEG_4
PEG
PEG
VCC_PEG_5
VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8
VTT_9 VTT_10 VTT_11 VTT_12 VTT_13
VTT
VTT
VTT_14 VTT_15 VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22
VCC_DMI
VCC_HV_1 VCC_HV_2
VTTLF1 VTTLF2 VTTLF3
VTTLF
VTTLF
U13 U12 U11 U9 U8 U7 U5 U3 U2 U1 T13 T11 T10 T9 T7 T6 T5 T3 T2 R3 R2 R1
AT23 AU28 AU24 AT29 AT25 AT30
AR29
B23 B21 A21
AJ50
BK24 BK23 BJ24 BJ23
A43
C40 B40
AD51 W50 W51 V49 V50
AH50 AH51
A7 F2 AH1
0.47U_0603_16V4Z
0.47U_0603_16V4Z
2
VTT: 850mA
+1.05VS
(220UF*1, 4.7UF*21, 2.2UF*1, 0.47UF*1)
1
+
+
C514
C514
330U_D2E_2.5VM
330U_D2E_2.5VM
1U_0603_10V4Z
1U_0603_10V4Z
+1.8V_TX_LVDS: 100mA (220UF*1, 1000PF*1)
VCC_HV: 100mA
VTTLF_CAP1 VTTLF_CAP2 VTTLF_CAP3
C556
C556
C557
C557
0.47U_0603_16V4Z
0.47U_0603_16V4Z
+1.05VS +3VS
2
2
+1.25VS_AXD
C524
C524
+1.25VS_AXF
C527
C527 10U_0805_10V4Z
10U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+1.8V_TX_LVDS
+3VS
C544
C544
220U_D2_2VMR15
220U_D2_2VMR15
GM@
GM@
C558
C558
0.47U_0603_16V4Z
0.47U_0603_16V4Z
D41
D41
2 1
RB751V_SOD323
RB751V_SOD323
C515
C515
4.7U_0805_10V4Z
4.7U_0805_10V4Z
VCC_AXD: 515mA (22UF*1, 1UF*1)
1
2
1
2
22U_0805_6.3V6M
22U_0805_6.3V6M
1
+
+
2
GM@
GM@
1000P_0402_50V7K
1000P_0402_50V7K
1
C516
C516
4.7U_0805_10V4Z
4.7U_0805_10V4Z
C517
C517
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
C518
C518
0.47U_0603_16V4Z
0.47U_0603_16V4Z
12/22 Change from 0805 to 0603
R472 0_0603_5%
R472 0_0603_5%
1
C523
C523 22U_0805_6.3V6M
22U_0805_6.3V6M
2
VCC_AXF: 495mA (10UF*1, 1UF*1)
R473 0_0603_5%
R473 0_0603_5%
C528
C528 1U_0603_10V4Z
1U_0603_10V4Z
+1.25VS
C531
C531
+1.8V_SM_CK
1
C537
C537
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C545
C545
2
+1.05VS_PEG
+1.05VS_PEG: 1260mA (220UF*1, 10UF*1)
1
+
+
C551
2
C551
10U_0805_10V4Z
10U_0805_10V4Z
C550
C550 220U_D2_2VMR15
220U_D2_2VMR15
VCC_DMI: 100mA (0.1UF*1)
C538
C538
+1.25VS
+1.25VS
VCC_SM_CK: 200mA (22UF*1, 0.1UF*1)
1
2
L45
L45
1 2
MBK1608121YZF_0603
MBK1608121YZF_0603
GM@
GM@
R480
R480 0_0402_5%
0_0402_5%
PM@
PM@
1
2
1 2
L44
L44 MBK1608121YZF_0603
MBK1608121YZF_0603
1 2
C539
R478
R478 1_0603_5%
1_0603_5%
1 2
R720 0_0805_5%R720 0_0805_5%
C539 10U_0805_10V4Z
10U_0805_10V4Z
+1.8V
+1.05VS
12/19 Modify C550 to correct description ( symbol change )
+1.8V
+1.05VS_DMI: 100mA (220UF*1, 10UF*1)
+1.05VS_PEG
+3VS
1
C570
C570
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
R486
R486
1 2
10_0603_5%
10_0603_5%
1
C560
C560 10U_0805_10V4Z
10U_0805_10V4Z
2
Close to VCC_HV (pin C40/B40)
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
Crestline (6/7)-VCC
Crestline (6/7)-VCC
Crestline (6/7)-VCC
IFTXX M/B LA-3541P Schematic
IFTXX M/B LA-3541P Schematic
IFTXX M/B LA-3541P Schematic
12 53Friday, February 09, 2007
12 53Friday, February 09, 2007
12 53Friday, February 09, 2007
1
0
0
0
of
of
of
5
U37I
U37I
A13
VSS_1
A15
VSS_2
A17
VSS_3
A24
VSS_4
AA21
VSS_5
AA24
VSS_6
AA29
VSS_7
AB20
VSS_8
AB23
VSS_9
AB26
VSS_10
D D
C C
B B
A A
AB28
VSS_11
AB31
VSS_12
AC10
VSS_13
AC13
VSS_14
AC3
VSS_15
AC39
VSS_16
AC43
VSS_17
AC47
VSS_18
AD1
VSS_19
AD21
VSS_20
AD26
VSS_21
AD29
VSS_22
AD3
VSS_23
AD41
VSS_24
AD45
VSS_25
AD49
VSS_26
AD5
VSS_27
AD50
VSS_28
AD8
VSS_29
AE10
VSS_30
AE14
VSS_31
AE6
VSS_32
AF20
VSS_33
AF23
VSS_34
AF24
VSS_35
AF31
VSS_36
AG2
VSS_37
AG38
VSS_38
AG43
VSS_39
AG47
VSS_40
AG50
VSS_41
AH3
VSS_42
AH40
VSS_43
AH41
VSS_44
AH7
VSS_45
AH9
VSS_46
AJ11
VSS_47
AJ13
VSS_48
AJ21
VSS_49
AJ24
VSS_50
AJ29
VSS_51
AJ32
VSS_52
AJ43
VSS_53
AJ45
VSS_54
AJ49
VSS_55
AK20
VSS_56
AK21
VSS_57
AK26
VSS_58
AK28
VSS_59
AK31
VSS_60
AK51
VSS_61
AL1
VSS_62
AM11
VSS_63
AM13
VSS_64
AM3
VSS_65
AM4
VSS_66
AM41
VSS_67
AM45
VSS_68
AN1
VSS_69
AN38
VSS_70
AN39
VSS_71
AN43
VSS_72
AN5
VSS_73
AN7
VSS_74
AP4
VSS_75
AP48
VSS_76
AP50
VSS_77
AR11
VSS_78
AR2
VSS_79
AR39
VSS_80
AR44
VSS_81
AR47
VSS_82
AR7
VSS_83
AT10
VSS_84
AT14
VSS_85
AT41
VSS_86
AT49
VSS_87
AU1
VSS_88
AU23
VSS_89
AU29
VSS_90
AU3
VSS_91
AU36
VSS_92
AU49
VSS_93
AU51
VSS_94
AV39
VSS_95
AV48
VSS_96
AW1
VSS_97
AW12
VSS_98
AW16
VSS_99
CRESTLINE_1p0
CRESTLINE_1p0
PM@
PM@
5
VSS
VSS
VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198
AW24 AW29 AW32 AW5 AW7 AY10 AY24 AY37 AY42 AY43 AY45 AY47 AY50 B10 B20 B24 B29 B30 B35 B38 B43 B46 B5 B8 BA1 BA17 BA18 BA2 BA24 BB12 BB25 BB40 BB44 BB49 BB8 BC16 BC24 BC25 BC36 BC40 BC51 BD13 BD2 BD28 BD45 BD48 BD5 BE1 BE19 BE23 BE30 BE42 BE51 BE8 BF12 BF16 BF36 BG19 BG2 BG24 BG29 BG39 BG48 BG5 BG51 BH17 BH30 BH44 BH46 BH8 BJ11 BJ13 BJ38 BJ4 BJ42 BJ46 BK15 BK17 BK25 BK29 BK36 BK40 BK44 BK6 BK8 BL11 BL13 BL19 BL22 BL37 BL47 C12 C16 C19 C28 C29 C33 C36 C41
4
U37J
U37J
C46
VSS_199
C50
VSS_200
C7
VSS_201
D13
VSS_202
D24
VSS_203
D3
VSS_204
D32
VSS_205
D39
VSS_206
D45
VSS_207
D49
VSS_208
E10
VSS_209
E16
VSS_210
E24
VSS_211
E28
VSS_212
E32
VSS_213
E47
VSS_214
F19
VSS_215
F36
VSS_216
F4
VSS_217
F40
VSS_218
F50
VSS_219
G1
VSS_220
G13
VSS_221
G16
VSS_222
G19
VSS_223
G24
VSS_224
G28
VSS_225
G29
VSS_226
G33
VSS_227
G42
VSS_228
G45
VSS_229
G48
VSS_230
G8
VSS_231
H24
VSS_232
H28
VSS_233
H4
VSS_234
H45
VSS_235
J11
VSS_236
J16
VSS_237
J2
VSS_238
J24
VSS_239
J28
VSS_240
J33
VSS_241
J35
VSS_242
J39
VSS_243
K12
VSS_245
K47
VSS_246
K8
VSS_247
L1
VSS_248
L17
VSS_249
L20
VSS_250
L24
VSS_251
L28
VSS_252
L3
VSS_253
L33
VSS_254
L49
VSS_255
M28
VSS_256
M42
VSS_257
M46
VSS_258
M49
VSS_259
M5
VSS_260
M50
VSS_261
M9
VSS_262
N11
VSS_263
N14
VSS_264
N17
VSS_265
N29
VSS_266
N32
VSS_267
N36
VSS_268
N39
VSS_269
N44
VSS_270
N49
VSS_271
N7
VSS_272
P19
VSS_273
P2
VSS_274
P23
VSS_275
P3
VSS_276
P50
VSS_277
R49
VSS_278
T39
VSS_279
T43
VSS_280
T47
VSS_281
U41
VSS_282
U45
VSS_283
U50
VSS_284
V2
VSS_285
V3
VSS_286
CRESTLINE_1p0
CRESTLINE_1p0
PM@
PM@
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VSS
VSS
3
W11
VSS_287
W39
VSS_288
W43
VSS_289
W47
VSS_290
W5
VSS_291
W7
VSS_292
Y13
VSS_293
Y2
VSS_294
Y41
VSS_295
Y45
VSS_296
Y49
VSS_297
Y5
VSS_298
Y50
VSS_299
Y11
VSS_300
P29
VSS_301
T29
VSS_302
T31
VSS_303
T33
VSS_304
R28
VSS_305
AA32
VSS_306
AB32
VSS_307
AD32
VSS_308
AF28
VSS_309
AF29
VSS_310
AT27
VSS_311
AV25
VSS_312
H50
VSS_313
Compal Secret Data
Compal Secret Data
2006/08/18 2007/8/18
2006/08/18 2007/8/18
2006/08/18 2007/8/18
3
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
Date: Sheet
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
Crestline (7/7)-GND
Crestline (7/7)-GND
Crestline (7/7)-GND
IFTXX M/B LA-3541P Schematic
IFTXX M/B LA-3541P Schematic
IFTXX M/B LA-3541P Schematic
1
0
0
0
13 53Thursday, February 08, 2007
13 53Thursday, February 08, 2007
13 53Thursday, February 08, 2007
of
of
1
of
5
4
3
2
1
+1.8V +1.8V
JP35
JP35
+DIMM_VREF
DDRA_SDQ0 DDRA_SDQ1
DDRA_SDQS0#<9> DDRA_SDQS0<9>
D D
DDRA_SDQS1#<9> DDRA_SDQS1<9>
DDRA_SDQS2#<9> DDRA_SDQS2<9>
EC_TX_P80_DATA<15,34>
C C
EC_RX_P80_CLK<15,34>
B B
EC_RX_P80_CLK
A A
DDRA_CKE0<8>
DDRA_SBS2<9>
DDRA_SBS0<9> DDRA_SWE#<9>
DDRA_SCAS#<9> DDRA_SCS1#<8>
DDRA_ODT1<8>
DDRA_SDQS4#<9> DDRA_SDQS4<9>
R622 0_0402_5%
R622 0_0402_5%
1 2
EC_RX_P80_CLK_R<15>
DDRA_SDQS6#<9> DDRA_SDQS6<9>
D_CK_SDATA<15,16> D_CK_SCLK<15,16>
+3VS
C508
C508
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
DDRA_SDQS0# DDRA_SDQS0
DDRA_SDQ2 DDRA_SDQ3
DDRA_SDQ8 DDRA_SDQ9
DDRA_SDQS1# DDRA_SDQS1
DDRA_SDQ10 DDRA_SDQ11
DDRA_SDQ16 DDRA_SDQ17
DDRA_SDQS2# DDRA_SDQS2
DDRA_SDQ18 DDRA_SDQ19
DDRA_SDQ24 DDRA_SDQ25
DDRA_SDM3 EC_TX_P80_DATA
DDRA_SDQ26 DDRA_SDQ27
DDRA_CKE0 EC_RX_P80_CLK
DDRA_SBS2 DDRA_SMA12
DDRA_SMA9 DDRA_SMA8
DDRA_SMA5 DDRA_SMA3 DDRA_SMA1
DDRA_SMA10 DDRA_SBS0 DDRA_SWE#
DDRA_SCAS# DDRA_SCS1#
DDRA_ODT1 DDRA_SDQ32
DDRA_SDQ33 DDRA_SDQS4#
DDRA_SDQS4 DDRA_SDQ34
DDRA_SDQ35 DDRA_SDQ40
DDRA_SDQ41 DDRA_SDM5 DDRA_SDQ42
DDRA_SDQ43 DDRA_SDQ48
DDRA_SDQ49
EC_RX_P80_CLK_R
DDRA_SDQS6# DDRA_SDQS6
DDRA_SDQ50 DDRA_SDQ51
DDRA_SDQ56 DDRA_SDQ57
DDRA_SDM7 DDRA_SDQ58
DDRA_SDQ59 D_CK_SDATA
D_CK_SCLK
+3VS
1
C509
C509
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
DIMM0 STD H:5.2mm (BOT)
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ40
143
DQ41
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
SCL
199
VDDSPD
P-TWO_A5652C-A0G16
P-TWO_A5652C-A0G16
Change PCB Footprint
DQ12 DQ13
CK0#
DQ14 DQ15
DQ20 DQ21
DQ22 DQ23
DQ28 DQ29
DQS3#
DQS3 DQ30
DQ31
NC/CKE1
NC/A15 NC/A14
RAS#
ODT0
NC/A13
DQ36 DQ37
DQ38 DQ39
DQ44 DQ45
DQS5#
DQS5 DQ46
DQ47 DQ52
DQ53
CK1#
DQ54 DQ55
DQ60 DQ61
DQS7#
DQS7 DQ62
DQ63
VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS
VSS DM1 VSS CK0
VSS
VSS
VSS
VSS DM2
VSS
VSS
VSS
VSS
VSS VDD
VDD
VDD
VDD BA1
VDD
VDD VSS
VSS DM4 VSS
VSS
VSS
VSS
VSS
VSS CK1
VSS DM6 VSS
VSS
VSS
VSS
VSS SAO SA1
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
42 44 46 48 50
NC
52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90
A11
92
A7
94
A6
96 98
A4
100
A2
102
A0
104 106 108 110
S0#
112 114 116 118 120
NC
122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200
12/22 Change from 0805 to 0603
5
4
9/25 Change DIMM0 to SP070004Z00 (HBL50)
DDRA_SDQ4 DDRA_SDQ5
DDRA_SDM0 DDRA_SDQ6
DDRA_SDQ7 DDRA_SDQ12
DDRA_SDQ13 DDRA_SDM1
DDRA_SDQ14 DDRA_SDQ15
DDRA_SDQ20 DDRA_SDQ21
DDRA_SDM2 DDRA_SDQ22
DDRA_SDQ23 DDRA_SDQ28
DDRA_SDQ29 DDRA_SDQS3#
DDRA_SDQS3 DDRA_SDQ30
DDRA_SDQ31 DDRA_CKE1
DDRA_SMA14 DDRA_SMA11
DDRA_SMA7 DDRA_SMA6
DDRA_SMA4 DDRA_SMA2 DDRA_SMA0
DDRA_SBS1 DDRA_SRAS# DDRA_SCS0#
DDRA_ODT0 DDRA_SMA13
DDRA_SDQ36 DDRA_SDQ37
DDRA_SDM4 DDRA_SDQ38
DDRA_SDQ39 DDRA_SDQ44
DDRA_SDQ45 DDRA_SDQS5#
DDRA_SDQS5 DDRA_SDQ46
DDRA_SDQ47 DDRA_SDQ52
DDRA_SDQ53
DDRA_SDM6 DDRA_SDQ54
DDRA_SDQ55 DDRA_SDQ60
DDRA_SDQ61 DDRA_SDQS7#
DDRA_SDQS7 DDRA_SDQ62
DDRA_SDQ63
R469 10K_0402_5% R469 10K_0402_5%
1 2
R470 10K_0402_5% R470 10K_0402_5%
1 2
DDRA_CLK0 <8> DDRA_CLK0# <8>
R468 0_0402_5%
R468 0_0402_5%
1 2
DDRA_SDQS3# <9> DDRA_SDQS3 <9>
DDRA_CKE1 <8>
DDRA_SBS1 <9> DDRA_SRAS# <9> DDRA_SCS0# <8>
DDRA_ODT0 <8>
DDRA_SDQS5# <9> DDRA_SDQS5 <9>
DDRA_CLK1 <8> DDRA_CLK1# <8>
DDRA_SDQS7# <9> DDRA_SDQS7 <9>
PM_EXTTS#0 <8>
DDRA_SMA14<8>
DDRB_SMA14<8,15>
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
+DIMM_VREF
1
2
95.10.5 modify
2006/08/18 2007/8/18
2006/08/18 2007/8/18
2006/08/18 2007/8/18
3
20mils
C483
C483
0.1U_0402_16V4Z
0.1U_0402_16V4Z
DDRA_SMA[0..13]<9> DDRA_SDQ[0..63]<9>
DDRA_SDM[0..7]<9>
DDRA_CKE0 DDRA_SBS2
DDRA_SMA12 DDRA_SMA9
DDRA_SMA8 DDRA_SMA5
DDRA_SMA3 DDRA_SMA1
DDRA_SMA10 DDRA_SBS0
DDRA_SWE# DDRA_SCAS#
DDRA_SCS1# DDRA_ODT1
DDRA_SMA11 DDRA_SMA14
DDRA_SMA6 DDRA_SMA7
DDRA_SMA2 DDRA_SMA4
DDRA_SBS1 DDRA_SMA0
DDRA_SCS0# DDRA_SRAS#
DDRA_SMA13 DDRA_ODT0
DDRB_SMA14 DDRA_CKE1
C484
C484
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
DDRA_SMA[0..13] DDRA_SDQ[0..63] DDRA_SDM[0..7]
1 4 2 3
RP39 56_0404_4P2R_5%
RP39 56_0404_4P2R_5%
1 4 2 3
RP40 56_0404_4P2R_5%
RP40 56_0404_4P2R_5%
RP41 56_0404_4P2R_5%
RP41 56_0404_4P2R_5%
RP42 56_0404_4P2R_5%
RP42 56_0404_4P2R_5%
RP43 56_0404_4P2R_5%
RP43 56_0404_4P2R_5%
RP44 56_0404_4P2R_5%
RP44 56_0404_4P2R_5%
RP45 56_0404_4P2R_5%
RP45 56_0404_4P2R_5%
RP46 56_0404_4P2R_5%
RP46 56_0404_4P2R_5%
RP47 56_0404_4P2R_5%
RP47 56_0404_4P2R_5%
RP48 56_0404_4P2R_5%
RP48 56_0404_4P2R_5%
RP49 56_0404_4P2R_5%
RP49 56_0404_4P2R_5%
RP50 56_0404_4P2R_5%
RP50 56_0404_4P2R_5%
RP51 56_0404_4P2R_5%
RP51 56_0404_4P2R_5%
R748 56_0402_5%
R748 56_0402_5% R749 56_0402_5%
R749 56_0402_5%
Layout Note: Place these resistor closely JP35,all trace length Max=1.5"
1 4 2 3
1 4 2 3
1 4 2 3
1 4 2 3
1 4 2 3
1 4 2 3
1 4 2 3
1 4 2 3
1 4 2 3
1 4 2 3
1 4 2 3
1 2 1 2
Deciphered Date
Deciphered Date
Deciphered Date
+1.8V
12
R465
R465
1K_0402_1%
1K_0402_1%
12
1
C485
R466
R466
1K_0402_1%
1K_0402_1%
C485 220P_0402_50V7K
220P_0402_50V7K
2
@
@
12/22 Change from 0805 to 0603
+1.8V
C486
C486
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
+0.9VS
+1.8V
1
C491
C491
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
+0.9VS
1
C495
C495
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
+0.9VS
1
C500
C500
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
+0.9VS
1
C505
C505
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9VS
2
C487
C487
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
+DIMM_VREF
Layout Note: Place near JP35
C490
1
C494
C494
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C498
C498
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C503
C503
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C490
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
1
2
1
2
14 53Friday, February 09, 2007
14 53Friday, February 09, 2007
14 53Friday, February 09, 2007
C488
C488
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
1
C492
C492
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C496
C496
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C501
C501
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C506
C506
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
Date: Sheet
Date: Sheet
Date: Sheet
C489
C489
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
1
C493
C493
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C497
C497
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C502
C502
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C507
C507
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
DDRII-SODIMM0
DDRII-SODIMM0
DDRII-SODIMM0
IFTXX M/B LA-3541P Schematic
IFTXX M/B LA-3541P Schematic
IFTXX M/B LA-3541P Schematic
C499
C499
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C504
C504
0.1U_0402_16V4Z
0.1U_0402_16V4Z
of
of
of
0
0
0
A
B
C
D
E
9/25 Change DIMM1 to SP070006F00
DQ4 DQ5
DM0 DQ6
DQ7
DQ12 DQ13
DM1
CK0# DQ14
DQ15
DQ20 DQ21
DM2
DQ22 DQ23
DQ28 DQ29
DQS3
DQ30 DQ31
VDD
VDD
VDD
VDD
RAS#
VDD
ODT0
VDD
DQ36 DQ37
DM4
DQ38 DQ39
DQ44 DQ45
DQS5
DQ46 DQ47
DQ52 DQ53
CK1#
DM6
DQ54 DQ55
DQ60 DQ61
DQS7
DQ62 DQ63
SAO
VSS
VSS VSS
VSS
VSS VSS
CK0 VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
BA1
VSS
VSS VSS
VSS
VSS
VSS
VSS
VSS CK1
VSS VSS
VSS
VSS
VSS
VSS SA1
+1.8V+1.8V
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
42 44 46 48 50
NC
52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90
A11
92
A7
94
A6
96 98
A4
100
A2
102
A0
104 106 108 110
S0#
112 114 116 118 120
NC
122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200
B
DDRB_SDQ4 DDRB_SDQ5
DDRB_SDM0 DDRB_SDQ6
DDRB_SDQ7 DDRB_SDQ12
DDRB_SDQ13 DDRB_SDM1
DDRB_SDQ14 DDRB_SDQ15
DDRB_SDQ20 DDRB_SDQ21DDRB_SDQ17
DDRB_SDM2 DDRB_SDQ22
DDRB_SDQ23 DDRB_SDQ28
DDRB_SDQ29 DDRB_SDQS3#
DDRB_SDQS3
DDRB_SDQ31 DDRB_CKE1
DDRB_SMA14 DDRB_SMA11
DDRB_SMA7 DDRB_SMA6
DDRB_SMA4 DDRB_SMA2 DDRB_SMA0
DDRB_SBS1 DDRB_SRAS# DDRB_SCS0#
DDRB_ODT0 DDRB_SMA13
DDRB_SDQ36 DDRB_SDQ37
DDRB_SDM4 DDRB_SDQ38
DDRB_SDQ39 DDRB_SDQ44
DDRB_SDQ45 DDRB_SDQS5#
DDRB_SDQS5 DDRB_SDQ46
DDRB_SDQ47 DDRB_SDQ52
DDRB_SDQ53
DDRB_SDM6 DDRB_SDQ54
DDRB_SDQ55 DDRB_SDQ60
DDRB_SDQ61DDRB_SDQ57 DDRB_SDQS7#
DDRB_SDQS7 DDRB_SDQ62
DDRB_SDQ63
R463 10K_0402_5%
R463 10K_0402_5%
1 2
R464 10K_0402_5%
R464 10K_0402_5%
1 2
R462
R462
0_0402_5%
0_0402_5%
1 2
DDRB_SMA[0..13] DDRB_SDQ[0..63] DDRB_SDM[0..7]
DDRB_CLK0 <8> DDRB_CLK0# <8>
DDRB_SMA[0..13]<9> DDRB_SDQ[0..63]<9>
DDRB_SDM[0..7]<9>
DDRB_CLK0?
12/22 Change from 0805 to 0603
PM_EXTTS#1 <8>
DDRB_SDQS3# <9> DDRB_SDQS3 <9>
DDRB_CKE1 <8>
DDRB_SMA14 <8,14>
DDRB_SBS1 <9> DDRB_SRAS# <9> DDRB_SCS0# <8>
DDRB_ODT0 <8>
DDRB_SDQS5# <9> DDRB_SDQS5 <9>
DDRB_CLK1 <8> DDRB_CLK1# <8>
DDRB_SDQS7# <9> DDRB_SDQS7 <9>
+3VS
Security Classification
Security Classification
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Issued Date
Issued Date
DDRB_CLK1?
C
2006/08/18 2007/8/18
2006/08/18 2007/8/18
2006/08/18 2007/8/18
DDRB_CKE0 DDRB_SBS2
DDRB_SMA12 DDRB_SMA9
DDRB_SMA8 DDRB_SMA5
DDRB_SMA3 DDRB_SMA1
DDRB_SMA10 DDRB_SBS0
DDRB_SWE# DDRB_SCAS#
DDRB_SCS1# DDRB_ODT1
DDRB_SMA11 DDRB_CKE1
DDRB_SMA6 DDRB_SMA7
DDRB_SMA2 DDRB_SMA4
DDRB_SBS1 DDRB_SMA0
DDRB_SCS0# DDRB_SRAS#
DDRB_SMA13 DDRB_ODT0
Layout Note: Place these resistor closely JP35,all trace length Max=1.5"
1 4 2 3
RP25 56_0404_4P2R_5%
RP25 56_0404_4P2R_5%
1 4 2 3
RP26 56_0404_4P2R_5%
RP26 56_0404_4P2R_5%
1 4 2 3
RP27 56_0404_4P2R_5%
RP27 56_0404_4P2R_5%
1 4 2 3
RP28 56_0404_4P2R_5%
RP28 56_0404_4P2R_5%
1 4 2 3
RP29 56_0404_4P2R_5%
RP29 56_0404_4P2R_5%
1 4 2 3
RP30 56_0404_4P2R_5%
RP30 56_0404_4P2R_5%
1 4 2 3
RP31 56_0404_4P2R_5%
RP31 56_0404_4P2R_5%
1 4 2 3
RP32 56_0404_4P2R_5%
RP32 56_0404_4P2R_5%
1 4 2 3
RP33 56_0404_4P2R_5%
RP33 56_0404_4P2R_5%
1 4 2 3
RP34 56_0404_4P2R_5%
RP34 56_0404_4P2R_5%
1 4 2 3
RP35 56_0404_4P2R_5%
RP35 56_0404_4P2R_5%
1 4 2 3
RP36 56_0404_4P2R_5%
RP36 56_0404_4P2R_5%
1 4 2 3
RP37 56_0404_4P2R_5%
RP37 56_0404_4P2R_5%
Deciphered Date
Deciphered Date
Deciphered Date
D
+0.9VS
JP34
JP34
+DIMM_VREF
DDRB_SDQ0 DDRB_SDQ1
1 1
2 2
3 3
4 4
EC_TX_P80_DATA<14,34>
EC_RX_P80_CLK<14,34>
EC_RX_P80_CLK_R<14>
DDRB_SDQS0#<9> DDRB_SDQS0<9>
DDRB_SDQS1#<9> DDRB_SDQS1<9>
DDRB_SDQS2#<9> DDRB_SDQS2<9>
DDRB_CKE0<8>
DDRB_SBS2<9>
DDRB_SBS0<9> DDRB_SWE#<9>
DDRB_SCAS#<9> DDRB_SCS1#<8>
DDRB_ODT1<8>
DDRB_SDQS4#<9> DDRB_SDQS4<9>
DDRB_SDQS6#<9> DDRB_SDQS6<9>
D_CK_SDATA<14,16> D_CK_SCLK<14,16>
DDRB_SDQS0# DDRB_SDQS0
DDRB_SDQ2 DDRB_SDQ3
DDRB_SDQ8 DDRB_SDQ9
DDRB_SDQS1# DDRB_SDQS1
DDRB_SDQ10 DDRB_SDQ11
DDRB_SDQ16
DDRB_SDQS2# DDRB_SDQS2
DDRB_SDQ18 DDRB_SDQ19
DDRB_SDQ24 DDRB_SDQ25
DDRB_SDM3 EC_TX_P80_DATA
DDRB_SDQ26 DDRB_SDQ30 DDRB_SDQ27
DDRB_CKE0 EC_RX_P80_CLK
DDRB_SBS2 DDRB_SMA12
DDRB_SMA9 DDRB_SMA8
DDRB_SMA5 DDRB_SMA3 DDRB_SMA1
DDRB_SMA10 DDRB_SBS0 DDRB_SWE#
DDRB_SCAS# DDRB_SCS1#
DDRB_ODT1 DDRB_SDQ32
DDRB_SDQ33 DDRB_SDQS4#
DDRB_SDQS4 DDRB_SDQ34
DDRB_SDQ35 DDRB_SDQ40
DDRB_SDQ41 DDRB_SDM5 DDRB_SDQ42
DDRB_SDQ43 DDRB_SDQ48
DDRB_SDQ49
EC_RX_P80_CLK_R
DDRB_SDQS6# DDRB_SDQS6
DDRB_SDQ50 DDRB_SDQ51
DDRB_SDQ56
DDRB_SDM7 DDRB_SDQ58
DDRB_SDQ59 D_CK_SDATA
D_CK_SCLK
+3VS
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ40
143
DQ41
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
SCL
199
VDDSPD
P-TWO_A5692A-A0G16-N
P-TWO_A5692A-A0G16-N
DQS3#
NC/CKE1
NC/A15 NC/A14
NC/A13
DQS5#
DQS7#
DIMM1 STD H:9.2mm (BOT)
A
+DIMM_VREF
1
C456
C455
C455
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
+1.8V
C461
C461
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
+1.8V
1
C466
C466
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+0.9VS
1
C470
C470
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+0.9VS
1
C475
C475
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
+0.9VS
1
C480
C480
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9VS
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
Date: Sheet
Date: Sheet
Date: Sheet
C456
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Layout Note: Place near JP34
C464
C462
C462
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
1
C467
C467
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C471
C471
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C476
C476
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C481
C481
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
IFTXX M/B LA-3541P Schematic
IFTXX M/B LA-3541P Schematic
IFTXX M/B LA-3541P Schematic
C464
C463
C463
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
1
C468
C468
C469
C469
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C472
C472
C473
C473
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C477
C477
C478
C478
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C482
C482
2
DDRII-SODIMM1
DDRII-SODIMM1
DDRII-SODIMM1
1
2
1
2
1
2
E
C465
C465
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
1
C474
C474
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C479
C479
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
15 53Friday, February 09, 2007
15 53Friday, February 09, 2007
15 53Friday, February 09, 2007
0
0
0
of
of
of
5
PCI
SRC
CPU
CLKSEL1
1
1
FSLA
CLKSEL0
MHz
200
166
MHz
1000
100
MHz
33.30
33.3
+3VS
KC FBM-L11-201209-221LMAT_0805
KC FBM-L11-201209-221LMAT_0805
12/4 Modified from 0 Ohm to bead ( 3A rated )
FSLC1FSLB
CLKSEL2
0
FSB Frequency Selet:
D D
CPU Driven
(Default)
*
667MHz
800MHz
CPU_BSEL0<5>
C C
CPU_BSEL1<5>
B B
CPU_BSEL2<5>
C451 18P_0402_50V8J C451 18P_0402_50V8J
A A
14.31818MHZ_16PF_DSX840GA
14.31818MHZ_16PF_DSX840GA
C452 18P_0402_50V8J C452 18P_0402_50V8J
12/1 Modified from 27P to 18P
Routing the trace at least 10mil
FSC
1 2
1 2
Stuff
No Stuff
Stuff
No Stuff
Stuff
No Stuff
FSA
R402
R402
2.2K_0402_5%
2.2K_0402_5%
1 2
R406
R406 0_0402_5%
0_0402_5%
FSB
1 2
R427
R427 0_0402_5%
0_0402_5%
R442
R442
2.2K_0402_5%
2.2K_0402_5%
1 2
R444
R444 0_0402_5%
0_0402_5%
Y2
Y2
R401 R408 R417 R430 R447R438
R401 R417 R447
R408 R430 R438
R408 R417 R447
R401 R430 R438
+1.05VS
R401
R401 56_0402_5%
56_0402_5%
@
@
1 2
1 2
12
+1.05VS
+1.05VS
12
R403
R403 1K_0402_5%
1K_0402_5%
12
R408
R408 1K_0402_5%
1K_0402_5%
@
@
R417
R417 1K_0402_5%
1K_0402_5%
@
@
1 2
1 2
R424
R424 1K_0402_5%
1K_0402_5%
12
R430
R430 0_0402_5%
0_0402_5%
@
@
R438
R438 1K_0402_5%
1K_0402_5%
@
@
1 2
1 2
R443
R443 1K_0402_5%
1K_0402_5%
12
R447
R447 0_0402_5%
0_0402_5%
@
@
MCH_CLKSEL0 <8>
MCH_CLKSEL1 <8>
MCH_CLKSEL2 <8>
For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP# For 27_SEL, 0 = Enable DOT96 & SRC1,
For PCI2_EN, 0 = Overclocking of CPU and SRC Allowed
+3VS +3VS +3VS
12
CLK_XTAL_OUT
5
CLK_XTAL_IN
R456
R456 10K_0402_5%
10K_0402_5%
@
@
1 2
ITP_EN 27_SEL
R459
R459 10K_0402_5%
10K_0402_5%
1 2
SATA_CLKREQ#<22> MCH_CLKREQ#<8>
CLK_PCI_PCM<26> CLK_PCI_1394<28>
CLK_PCI_TPM<29>
CLK_PCI_EC<34>
CLK_PCI_SIO<41> CLK_PCI_DB<36>
CLK_PCI_ICH<20>
CLK_ICH_48M<22>
CLK_14M_SIO<36,41> CLK_ICH_14M<22>
1= Enable SRC0 & 27MHz
1 = Overclocking of CPU and SRC NOT allowed
1 2
R457
R457 10K_0402_5%
10K_0402_5%
PM@
PM@
1 2
R460
R460 10K_0402_5%
10K_0402_5%
GM@
GM@
1 2
4
+3VM_CK505
L56
L56
L57
L57
1 2
+1.25VS
KC FBM-L11-201209-221LMAT_0805
KC FBM-L11-201209-221LMAT_0805
+1.25VM_CK505
1 2
PCI2_TME
1 2
4
1
C430
C430 10U_0805_10V4Z
10U_0805_10V4Z
2
+1.25VM_CK505
1 2 1 2 1 2
1 2 1 2 1 2 1 2 1 2 1 2
1 2
1 2 1 2
R458
R458 10K_0402_5%
10K_0402_5%
R461
R461 10K_0402_5%
10K_0402_5%
@
@
+1.25VM_CK505
R412475_0402_1%
R412475_0402_1% R413475_0402_1%
R413475_0402_1% R41622_0402_5%
R41622_0402_5% R41822_0402_5%
R41822_0402_5% R41922_0402_5%
R41922_0402_5% R42022_0402_5%
R42022_0402_5% R42222_0402_5%
R42222_0402_5% R42522_0402_5%
R42522_0402_5% R42633_0402_5%
R42633_0402_5%
CLK_XTAL_IN CLK_XTAL_OUT
R43633_0402_5%
R43633_0402_5%
R59722_0402_5%
R59722_0402_5% R44122_0402_5%
R44122_0402_5%
1
2
1
C431
C431
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C437
C437 10U_0805_10V4Z
10U_0805_10V4Z
2
+3VM_CK505
PCI_CLK0 PCI_CLK1 PCI2_TME PCI_CLK3 27_SEL ITP_EN
FSA
FSB
FSC
C443
C443
0.1U_0402_16V4Z
0.1U_0402_16V4Z
3
1
C432
C432
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C438
C438
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
10/17 : Change P/N from SA0001GT00 to SA00001GT10
1
C433
C433
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C439
C439
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C434
C434
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C440
C440
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C435
C435
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C441
C441
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
1
C436
C436
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C442
C442
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
Need to update Symbol
U35
U35
2
VDD_PCI
9
VDD48
16
VDDPLL3
61
VDDREF
39
VDDSRC
55
VDDCPU
12
VDD96_IO
20
VDDPLL3_IO
26
VDDSRC_IO
36
VDDSRC_IO
49
VDDCPU_IO
1
PCI0/CR#_A
3
PCI1/CR#_B
4
PCI2/TME
5
PCI3
6
PCI4/27_Select
7
PCIF5/ITP_EN
60
X1
59
X2
10
USB_48MHZ/FSLA
57
FSLB/TEST MODE
62
REF0/FSLC/TEST_SEL
45
VDDSRC_IO
42
GNDSRC
8
GNDPCI
11
GND48
15
GND
19
GND
52
GNDCPU
23
GNDSRC
29
GNDSRC
58
GNDREF
* Internal Pull-Up Resistor
* Internal Pull-Up Resistor ** Internal Pull-Down Resistor
** Internal Pull-Down Resistor
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
CPU_STOP#
SRC11/CR#_H
SRC11#/CR#_G
SRC7/CR#_F
SRC7#/CR#_E
SRC3/CR#_C
SRC3#/CR#_D
SRC2#/SATA#
SRC1/SE1/27MHz_NonSS
SRC1#/SE2/27MHz_SS
SRC0/DOT96
SRC0/DOT96#
CK_PWRGD/PD#
ICS9LPRS365
ICS9LPRS365
2006/08/04 2006/10/06
2006/08/04 2006/10/06
2006/08/04 2006/10/06
SCLK
SDATA
PCI_STOP#
CPU0
CPU0#
CPU1_F
CPU1#_F
SRC8/ITP
SRC8#/ITP#
SRC10#
SRC10
SRC9
SRC9#
SRC6
SRC6#
SRC4
SRC4#
SRC2/SATA
48
NC
D_CK_SCLK
64
D_CK_SDATA
63
PM_STP_PCI#
38
PM_STP_CPU#
37
CLK_CPU_BCLK
54
CLK_CPU_BCLK#
53
CLK_MCH_BCLK
51
CLK_MCH_BCLK#
50
CLK_PCIE_EXP
47
CLK_PCIE_EXP#
46
CLK_PCIE_LAN#
35
CLK_PCIE_LAN
34
CLK_PCIE_NAND
33
CLK_PCIE_NAND#
32
CLK_PCIE_3G
30
CLK_PCIE_3G#
31
R_CLKREQ#_F
44
R_CLKREQ#_E
43
CLK_PCIE_WLAN
41
CLK_PCIE_WLAN#
40
CLK_MCH_3GPLL
27
CLK_MCH_3GPLL#
28
CLK_PCIE_ICH
24
CLK_PCIE_ICH#
25
CLK_PCIE_SATA
21
CLK_PCIE_SATA#
22
CLK_PCIE0
17
CLK_PCIE0#
18
R_CLK_DOT
13
R_CLK_DOT#
14
CK_PWRGD
56
R432 475_0402_1%
R432 475_0402_1% R433 475_0402_1%
R433 475_0402_1%
ICS9LPRS365/SA00001GT00
Deciphered Date
Deciphered Date
Deciphered Date
1 2 1 2
R450 0_0402_5%GM@R450 0_0402_5%GM@
1 2
R451 0_0402_5%GM@ R451 0_0402_5%GM@
1 2
R713 0_0402_5%@R713 0_0402_5%@
1 2
R714 0_0402_5%@R714 0_0402_5%@
1 2
R452 0_0402_5%GM@R452 0_0402_5%GM@
1 2
R453 0_0402_5%GM@R453 0_0402_5%GM@
1 2
R454 0_0402_5%PM@R454 0_0402_5%PM@
1 2
R455 0_0402_5%PM@R455 0_0402_5%PM@
1 2
2
R431 10K_0402_5%
R431 10K_0402_5%
1 2
R434 10K_0402_5%
R434 10K_0402_5%
1 2
1
+3VS
R398
R398
2.2K_0402_5%
2.2K_0402_5%
D
S
D
S
+3VS
1 3
2 2
1 3
D
D
Q39
Q39 2N7002_SOT23
2N7002_SOT23
G
G
G
G
S
S
Q40
Q40 2N7002_SOT23
2N7002_SOT23
C444
C444 C445
C445 C446
C446 C447
C447 C448
C448 C449
C449 C450
C450
ICH_SMBDATA<22,32,33>
ICH_SMBCLK<22,32,33>
D_CK_SCLK <14,15>
D_CK_SDATA <14,15> PM_STP_PCI# <22>
PM_STP_CPU# <22>
CLK_CPU_BCLK <4> CLK_CPU_BCLK# <4>
CLK_MCH_BCLK <7> CLK_MCH_BCLK# <7>
CLK_PCIE_EXP <33> CLK_PCIE_EXP# <33>
CLK_PCIE_LAN# <30> CLK_PCIE_LAN <30>
CLK_PCIE_NAND <32> CLK_PCIE_NAND# <32>
CLK_PCIE_3G <32> CLK_PCIE_3G# <32>
EXP_CLKREQ# <33> WLAN_CLKREQ# <32>
CLK_PCIE_WLAN <32> CLK_PCIE_WLAN# <32>
CLK_MCH_3GPLL <8> CLK_MCH_3GPLL# <8>
CLK_PCIE_ICH <22> CLK_PCIE_ICH# <22>
CLK_PCIE_SATA <21> CLK_PCIE_SATA# <21>
CLK_DREF_SSC <8> CLK_DREF_SSC# <8> CLK_27M_VGA <17> CLK_27M_VGA# <17>
CLK_DREF_96M <8> CLK_DREF_96M# <8>
CLK_PCIE_VGA <17> CLK_PCIE_VGA# <17>
CK_PWRGD <22>
+3VS
+3VS
Place close to U35
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
Clock generator
Clock generator
Clock generator
IXXXX LA-3XXXP
IXXXX LA-3XXXP
IXXXX LA-3XXXP
1
R399
R399
2.2K_0402_5%
2.2K_0402_5%
D_CK_SDATA
D_CK_SCLK
CLK_ICH_48M
12
5P_0402_50V8C@
5P_0402_50V8C@
CLK_ICH_14M
12
4.7P_0402_50V8C@
4.7P_0402_50V8C@
CLK_PCI_ICH
12
4.7P_0402_50V8C@
4.7P_0402_50V8C@
CLK_14M_SIO
12
4.7P_0402_50V8C@
4.7P_0402_50V8C@
CLK_PCI_PCM
12
4.7P_0402_50V8C@
4.7P_0402_50V8C@
CLK_PCI_EC
12
4.7P_0402_50V8C@
4.7P_0402_50V8C@
CLK_PCI_SIO
12
4.7P_0402_50V8C@
4.7P_0402_50V8C@
16 53Friday, February 09, 2007
16 53Friday, February 09, 2007
16 53Friday, February 09, 2007
0.1
0.1
0.1
of
of
of
5
4
3
2
1
PCIE_MTX_C_GRX_N[0..15]<10> PCIE_MTX_C_GRX_P[0..15]<10> PCIE_GTX_C_MRX_N[0..15]<10> PCIE_GTX_C_MRX_P[0..15]<10>
D D
B+ +1.8VS
PCIE_GTX_C_MRX_N15 PCIE_GTX_C_MRX_P15
PCIE_GTX_C_MRX_N14 PCIE_GTX_C_MRX_P14
C C
B B
PCIE_GTX_C_MRX_N13 PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_N12 PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_N11 PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_N10 PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_N9 PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_N8 PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_N7 PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_N6 PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_N5 PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_N4 PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_N3 PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_N2 PCIE_GTX_C_MRX_P2
PCIE_MTX_C_GRX_N[0..15] PCIE_MTX_C_GRX_P[0..15] PCIE_GTX_C_MRX_N[0..15] PCIE_GTX_C_MRX_P[0..15]
JP33A
JP33A
1
PWR_SRC
3
PWR_SRC
5
PWR_SRC
7
PWR_SRC
9
PWR_SRC
11
PWR_SRC
13
PWR_SRC
15
PWR_SRC
17
GND
19
GND
21
GND
23
GND
25
PEX_RX15#
27
PEX_RX15
29
GND
31
PEX_RX14#
33
PEX_RX14
35
GND
37
PEX_RX13#
39
PEX_RX13
41
GND
43
PEX_RX12#
45
PEX_RX12
47
GND
49
PEX_RX11#
51
PEX_RX11
53
GND
55
PEX_RX10#
57
PEX_RX10
59
GND
61
PEX_RX9#
63
PEX_RX9
65
GND
67
PEX_RX8#
69
PEX_RX8
71
GND
73
PEX_RX7#
75
PEX_RX7
77
GND
79
PEX_RX6#
81
PEX_RX6
83
GND
85
PEX_RX5#
87
PEX_RX5
89
GND
91
PEX_RX4#
93
PEX_RX4
95
GND
97
PEX_RX3#
99
PEX_RX3
101
GND
103
PEX_RX2#
105
PEX_RX2
107
GND
ACES_88990-2D08
ACES_88990-2D08
1V8RUN 1V8RUN 1V8RUN 1V8RUN 1V8RUN 1V8RUN 1V8RUN
RUNPWROK
5VRUN
GND GND GND
PRSNT2#
PEX_TX15#
PEX_TX15
GND
PEX_TX14#
PEX_TX14
GND
PEX_TX13#
PEX_TX13
GND
PEX_TX12#
PEX_TX12
GND
PEX_TX11#
PEX_TX11
GND
PEX_TX10#
PEX_TX10
GND
PEX_TX9#
PEX_TX9
GND
PEX_TX8#
PEX_TX8
GND
PEX_TX7#
PEX_TX7
GND
PEX_TX6#
PEX_TX6
GND
PEX_TX5#
PEX_TX5
GND
PEX_TX4#
PEX_TX4
GND
PEX_TX3#
PEX_TX3
GND
PEX_TX2#
PEX_TX2
9/13 modify this footprint from ACES_88990-2D08_230P to ACES_88990-2D28_230P 12/19 modify this footprint from ACES_88990-2D28_230P to QUASA_CA0330-230N20_230P
0208 : Modify this footprint from QUASA_CA0330-230N20_230P to QUASA_CA0330-230N20_230P-S
JP33B
JP33B
PCIE_GTX_C_MRX_N1 PCIE_GTX_C_MRX_P1
2 4 6 8 10 12 14 16 18 20 22 24
26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108
SUSP# <28,33,34,41,43,48,49,50>
+5VS
PCIE_MTX_C_GRX_N15 PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_N14 PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_N13 PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_N12 PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_N11 PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N10 PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N9 PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N8 PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N7 PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_N6 PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N5 PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N4 PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N3 PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_N2 PCIE_MTX_C_GRX_P2
CLK_PCIE_VGA#<16>
CLK_PCIE_VGA<16>
PLT_RST_BUF#<8,20,29,30,32,41>
EC_SMB_DA2<4,34> EC_SMB_CK2<4,34>
VGA_CRT_HSYNC<19> VGA_CRT_VSYNC<19>
VGA_DDC_CLK<19>
VGA_DDC_DATA<19>
CLK_27M_VGA#<16>
CLK_27M_VGA<16>
PCIE_GTX_C_MRX_N0 PCIE_GTX_C_MRX_P0
CLK_PCIE_VGA# CLK_PCIE_VGA
VGA_CRT_VSYNC VGA_DDC_CLK VGA_DDC_DATA
CLK_27M_VGA# CLK_27M_VGA
109
PEX_RX1#
111
PEX_RX1
113
GND
115
PEX_RX0#
117
PEX_RX0
119
GND
121
PEX_REFCLK#
123
PEX_REFCLK
125
CLK_REQ#
127
PEX_RST#
129
RSVD
131
RSVD
133
SMB_DAT
135
SMB_CLK
137
THERM#
139
VGA_HSYNC
141
VGA_VSYNC
143
DDCA_CLK
145
DDCA_DAT
147
IGP_UCLK#
149
IGP_UCLK
151
GND
153
RSVD
155
RSVD
157
RSVD
159
IGP_UTX2#
161
IGP_UTX2
163
GND
165
IGP_UTX1#
167
IGP_UTX1
169
GND
171
IGP_UTX0#
173
IGP_UTX0
175
GND
177
IGP_LCLK#/DVI_B_CLK#
179
IGP_LCLK/DVI_B_CLK
181
DVI_B_HPD/GND
183
RSVD
185
RSVD
187
GND
189
IGP_LTX2#/DVI_B_TX2#
191
IGP_LTX2/DVI_B_TX2
193
GND
195
IGP_LTX1#/DVI_B_TX1#
197
IGP_LTX1/DVI_B_TX1
199
GND
201
IGP_LTX0#/DVI_B_TX0#
203
IGP_LTX0/DVI_B_TX0
205
DVI_A_HPD
207
DVI_A_CLK#
209
DVI_A_CLK
211
GND
213
DVI_A_TX2#
215
DVI_A_TX2
217
GND
219
DVI_A_TX1#
221
DVI_A_TX1
223
GND
225
DVI_A_TX0#
227
DVI_A_TX0
229
GND
ACES_88990-2D08
ACES_88990-2D08
GND
PEX_TX1#
PEX_TX1
GND
PEX_TX0#
PEX_TX0 PRSNT1#
TV_C/HDTV_Pr
GND
TV_Y/HDTV_Y
TV_CVBS/HDTV_Pb
GND GND
VGA_RED
GND
VGA_GRN
GND
VGA_BLU
GND
LVDS_UCLK#
LVDS_UCLK
GND
LVDS_UTX3#
LVDS_UTX3
GND
LVDS_UTX2#
LVDS_UTX2
GND
LVDS_UTX1#
LVDS_UTX1
GND
LVDS_UTX0#
LVDS_UTX0
GND
LVDS_LCLK#
LVDS_LCLK
GND
LVDS_LTX3#
LVDS_LTX3
GND
LVDS_LTX2#
LVDS_LTX2
GND
LVDS_LTX1#
LVDS_LTX1
GND
LVDS_LTX0#
LVDS_LTX0
GND DDCC_DAT DDCC_CLK
LVDS_PPEN
LVDS_BL_BRGHT
LVDS_BLEN
DDCB_DAT
DDCB_CLK
2V5RUN
GND
3V3RUN 3V3RUN 3V3RUN
110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230
PCIE_MTX_C_GRX_N1 PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N0 PCIE_MTX_C_GRX_P0
VGA_TV_CRMA VGA_TV_LUMA VGA_TV_COMPS VGA_CRT_R VGA_CRT_GVGA_CRT_HSYNC VGA_CRT_B TXCLK-
TXCLK+
TXOUT2­TXOUT2+
TXOUT1­TXOUT1+
TXOUT0­TXOUT0+
TZCLK­TZCLK+
TZOUT2­TZOUT2+
TZOUT1­TZOUT1+
TZOUT0­TZOUT0+
I2CC_SDA I2CC_SCL ENVDD
VGA_ENBKL
+2.5VS
+3VS
VGA_TV_CRMA <19> VGA_TV_LUMA <19>
VGA_TV_COMPS <19> VGA_CRT_R <19> VGA_CRT_G <19> VGA_CRT_B <19> TXCLK- <18>
TXCLK+ <18>
TXOUT2- <18> TXOUT2+ <18>
TXOUT1- <18> TXOUT1+ <18>
TXOUT0- <18> TXOUT0+ <18>
TZCLK- <18> TZCLK+ <18>
TZOUT2- <18> TZOUT2+ <18>
TZOUT1- <18> TZOUT1+ <18>
TZOUT0- <18> TZOUT0+ <18>
I2CC_SDA <18> I2CC_SCL <18>
ENVDD <18> VGA_ENBKL <18>
+1.8VS +3VS +2.5VS +5VSB+
2
C423
C423
0.1U_0603_25V7K
0.1U_0603_25V7K
PM@
PM@
A A
1
4.7U_0805_10V4Z
4.7U_0805_10V4Z
5
C424
C424
PM@
PM@
1
1
C425
C425
4.7U_0805_10V4Z
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
PM@
PM@
4.7U_0805_10V4Z
C426
C426
PM@
PM@
1
2
4
1
C427
C427
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
PM@
PM@
1
C428
C428
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
PM@
PM@
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
C429
C429
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
PM@
PM@
Compal Secret Data
Compal Secret Data
2006/08/18 2007/8/18
2006/08/18 2007/8/18
2006/08/18 2007/8/18
3
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
MXM Connector
MXM Connector
MXM Connector
IFTXX M/B LA-3541P Schematic
IFTXX M/B LA-3541P Schematic
IFTXX M/B LA-3541P Schematic
17 53Friday, February 09, 2007
17 53Friday, February 09, 2007
17 53Friday, February 09, 2007
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