Lenovo Ideapad 720S Schematic

A

1 1

B

C

D

E

2 2

LCFC Confidential

RAVEN EX85 Rev0.1 Schematic

AMD Raven Ridge FP5 Processor with DDR4

R17M-M1-70 with DDR5 2GB

3 3

2017-3-30 Rev0.1

4 4

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

C

2015/10/5

2015/10/5

2015/10/5

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

2016/12/31

2016/12/31

2016/12/31

Title

COVER PAGE

COVER PAGE

COVER PAGE

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Thursday, May 04, 2017

Thursday, May 04, 2017

Thursday, May 04, 2017

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

JINN/DOOKU

JINN/DOOKU

JINN/DOOKU

E

1 64

1 64

1 64

SDV

SDV

SDV

A

B

C

D

E

AMD Raven Ridge FP5

1 1

R17M-M1 -70
2G GDDR5

VRAM 256M*32 2Pcs

Page 16~23

eDP Conn.

Page 25

HDMI Conn.

Page 28

PCI-Express x4 Gen3

DP0 x2Lane

DDI

AMD

Raven Ridge

Processor

FP5 BGA 1140P
25mm * 35mm

PCIe x1 Gen1

DDR4 Channel A

1.2V 2400 MT/s

DDR4 Channel B

1.2V 2400 MT/s

USB 2.0 x 1

USB2.0 x1

Repeato r
TI

CC

TUSB544

PD

PD Controll er
RTS545 7

SATA_redriver

Parade PS8527C

2 2

Page 44

SATA 10pin CONN

Page 32

JUSB-C Conn.

USB C(DP1.2/USB3.0)

Page 31

SATA Gen3

USB3.0 x1

USB2.0 x1

USB2.0 x1

USB charger

(AOU)

TPS2546R TER

USB 3.0 x 1

PCIE x1 Ge n1(1000M LAN)
PCIE x1 Gen1(Cardreader)

DDR4-SO-DIMM X1

BANK 0, 1

UP TO 16G

Page 14~5

DDR4-SO-DIMM X1

BANK 0, 1

UP TO 16G

NGFF Card WLAN

BT

USB Left Front

USB Left Behind

Page 14~5

Page 40

Page 40

PCIe Port 3

Page 45

USB2.0 x1

SUB/B CONN

3 3

SPI ROM
64M
W25Q64FWSSIQ

Page 9

SPI BUS

1.8 V

Page 5~12

TPM
SLB9670VQ1P2

PWR
Button

Page 53

Sub Board

LPC BUS

3.3V 33MHz

EC
IT8996E-256/DX

RJ45 Conn.

4 4

JCARD Conn.

Realtek
RTL8111GUS

BAYHU B
OZ711LV 1LN

SD/MMC

PCIe

PCIe

G-Sensor
BMA255

Touch Pad
Track Point

Page 54Page 58

Int.KBD

USB2.0 x1

HD Audio

Page 52

Thermal Sensor
F75303M

Codec
CX11852-11Z

MIC_CLK/M IC_DATA

Int. MIC Conn.
(JLCD Conn.)

Page 25

Page ?

HP_R/L_J ACK

SP_OUTR/ L

Ext. HP/MIC
Combo Jack

Page 49Page 57Page 55

Int. camera

SPK Conn .

Page 37

Page 49

JUSB4 Conn.

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

USB2.0

A

B

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. A ND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. A ND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. A ND CONTAINS CONFIDENTIAL
AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CE NTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CE NTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CE NTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

C

2017/01/01

2017/01/01

2017/01/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

2018/06/31

2018/06/31

2018/06/31

Title

BLOCK DIAGRAM

BLOCK DIAGRAM

BLOCK DIAGRAM

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

C

C

C

Thursday, May 04, 2017

Thursday, May 04, 2017

Thursday, May 04, 2017

Date: Sheet of

Date: Sheet of

Date: Sheet of

JINN/DOOKU

JINN/DOOKU

JINN/DOOKU

E

2 64

2 64

2 64

SDV

SDV

SDV

5

4

3

2

1

Voltage Rails

Power Plane

D D

B9+

State

S0

S3

S5 S4/AC Only

C C

S5 S4
Battery only

O

O

O

O

, X --> Means OFF )( O --> Means ON

+3VALW

+5VALW

+1.8VALW

+0.9VALW_VD DP

O O

O

+1.2V

+2.5V

X

XX

+5VS

+3VS

+1.5VS

+0.9VS_ VDDP

+0.6VS

+VDDCR_ SOC

+VDDC_V DD

+VGA_CO RE

+3.3VGS

+1.8VGS

+1.35VG S
+0.95VG S

OOO

X

X

X

USB2 Port

Por t Devic e

0

USB C
1
2

USB3 port2

3

USB2 port1
4
5

USB(WLA N)

Int. Camera

USB3 Port

Por t Devic e

USB Type-C

1USB3 port1

USB3 port1

2

USB3 port2

3

STATE

S0

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SIGNAL

PCIE Port

Por t Devic e

X

X4

LOW LOW

0
1
2
3
4
5

GFX 0

GFX 1
GFX 2

GFX 3

SLP_S3#SLP_A#

LOWLOW

LOWLOW OFF

HIGHHIGHHIGH

HIGH

HIGH

LOW

EC_ONSLP_S5#

ON

ON

SATA Port

Por t Devic e

LAN

CardRea der

WLA N

X

X

X

GPU
GPU

GPU
GPU

1
2

SUSP#

ONON

OFFON

OFF

HDD0

X

S5 S4
AC & Battery
don't exist

XX

X

X

SMBUS Control Table

SOURCE

Main
VGA

Thermal

WLAN

SODIMMBATT

WiMAX

Sensor

APU

CP
Module

Charge

PD

G-Senso r

PMIC

EC_SMB_ CK1 IT8986F

EC_SMB_ DA1

EC_SMB_ CK2

B B

EC_SMB_ CK3

EC_SMB_ DA3

EC_SMB_ CK4

EC_SMB_ DA4

+3VL

IT8986F

+3VALWEC_SMB_ DA2

IT8986F

+3VS

IT8986F

+3VL

X

X

V

+3VS_VG A

V

X

X

X

X X

V

+3VS

X

X

V

+3VL

X X X

X

X

X

X X

X X

X

+3VS

X

X

X X

X

V

+3VL

X

V

+3VALW

XX

X

X

X

X

V

+3VS

X

X

X

X

V

APU I2C

APU Port

I2C3_SCL/SD A

SIC/SID

ZZZ2

A A

PCB@

APPLY PCB PN

NM-A861

DA80000ZP00

5

4

USBC_I2C_SC L

/SDA

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

3

Net

APU_ SMB0CLK /SDAI2C2_SCL/SD A

APU_SMB1 _CLK/SDA

Device

DIMM1/DIMM2

TOUCHPA D

EC_SMB_CK3/ DA3 Conn EC

EC_SMB_CK2/ DA2

2017/01/01

2017/01/01

2017/01/01

PD

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Title

Title

2018/06/31

2018/06/31

2018/06/31

2

Title

BLANK

BLANK

BLANK

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Thursday, May 04, 2017

Thursday, May 04, 2017

Thursday, May 04, 2017

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

JINN/DOOKU

JINN/DOOKU

JINN/DOOKU

1

3 64

3 64

3 64

SDV

SDV

SDV

5

D D

4

3

2

1

BOM Structure Table

BOM Structure

NOT E

HDT @ For HDT AMD debug port

LPC @ For LPC AMD debug port

PX@

C C

X76 @

TPM @

UMA @

CD@

EMC_NS@

ME@

For GPU function

GPU VRAM Setting

Trusted Platform Module(TPM)

UMA SKU ID

COST DOWN

EMC Reserves

ME Connector

For RF functionRF@

For EMI functionEMC@

B B

RF_NS@

RF_PXNS@

14@

15@

reserves RF component

VGA reserves RF component

14 inch

15 inch

A A

Titl e

Titl e

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

2015/10/5

2015/10/5

2015/10/5

3

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2014/12/05

2014/12/05

2014/12/05

2

Titl e

SMBus Block

SMBus Block

SMBus Block

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

B

B

B

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

JINN/DOOKU

JINN/DOOKU

JINN/DOOKU

Thursday, May 04, 2017

Thursday, May 04, 2017

Thursday, May 04, 2017

1

4 64

4 64

4 64

SDV

SDV

SDV

5

D D

PCIE_CRX_GTX_P017
PCIE_CRX_GTX_N017

PCIE_CRX_GTX_P117

GPU

C C

LAN

WLAN

HDD

B B

PCIE_CRX_GTX_N117

PCIE_CRX_GTX_P217
PCIE_CRX_GTX_N217

PCIE_CRX_GTX_P317
PCIE_CRX_GTX_N317

PCIE1_CRX_DTX_P35
PCIE1_CRX_DTX_N35

PCIE2_CRX_DTX_P35
PCIE2_CRX_DTX_N35

PCIE5_CRX_DTX_P37
PCIE5_CRX_DTX_N37

SATA_CRX_DTX_P029
SATA_CRX_DTX_N029

4

SATA_CRX_DTX_N0

PCIE_CRX_GTX_P0
PCIE_CRX_GTX_N0

PCIE_CRX_GTX_P1
PCIE_CRX_GTX_N1

PCIE_CRX_GTX_P2

PCIE_CRX_GTX_P3
PCIE_CRX_GTX_N3

PCIE1_CRX_DTX_P
PCIE1_CRX_DTX_N

PCIE2_CRX_DTX_P
PCIE2_CRX_DTX_N

PCIE5_CRX_DTX_P
PCIE5_CRX_DTX_N

P8

P_GFX_RXP0

P9

P_GFX_RXN0

N6

P_GFX_RXP1

N7

P_GFX_RXN1

M8

P_GFX_RXP2

M9

P_GFX_RXN2

L6

P_GFX_RXP3

L7

P_GFX_RXN3

K11

P_GFX_RXP4

J11

P_GFX_RXN4

H6

P_GFX_RXP5

H7

P_GFX_RXN5

G6

P_GFX_RXP6

F7

P_GFX_RXN6

G8

P_GFX_RXP7

F8

P_GFX_RXN7

N10

P_GPP_RXP0

N9

P_GPP_RXN0

L10

P_GPP_RXP1

L9

P_GPP_RXN1

L12

P_GPP_RXP2

M11

P_GPP_RXN2

P12

P_GPP_RXP3

P11

P_GPP_RXN3

V6

P_GPP_RXP4

V7

P_GPP_RXN4

T8

P_GPP_RXP5

T9

P_GPP_RXN5

R6

P_GPP_RXP6/SATA_RXP0

R7

P_GPP_RXN6/SATA_RXN0

R9

P_GPP_RXP7/SATA_RXP1

R10

P_GPP_RXN7/SATA_RXN1

3

UC1B

PCIE

P_GPP_TXP6/SATA_TXP0
P_GPP_TXN6/SATA_TXN0

P_GPP_TXP7/SATA_TXP1
P_GPP_TXN7/SATA_TXN1

FP5 REV 0.90

PART 2 OF 13

AMD-RAVEN-FP5_BGA1140

P_GFX_TXP0
P_GFX_TXN0

P_GFX_TXP1
P_GFX_TXN1

P_GFX_TXP2
P_GFX_TXN2

P_GFX_TXP3
P_GFX_TXN3

P_GFX_TXP4
P_GFX_TXN4

P_GFX_TXP5
P_GFX_TXN5

P_GFX_TXP6
P_GFX_TXN6

P_GFX_TXP7
P_GFX_TXN7

P_GPP_TXP0
P_GPP_TXN0

P_GPP_TXP1
P_GPP_TXN1

P_GPP_TXP2
P_GPP_TXN2

P_GPP_TXP3
P_GPP_TXN3

P_GPP_TXP4
P_GPP_TXN4

P_GPP_TXP5
P_GPP_TXN5

2

N1
N3

M2
M4

L2
L4

L1
L3

K2
K4

J2
J4

H1
H3

H2
H4

PCIE1_CTX_DRX_P

N2

PCIE1_CTX_DRX_N

P3

PCIE2_CTX_DRX_P PCIE2_CTX_C_DRX_P

P4

PCIE2_CTX_DRX_N

P2

R3
R1

T4
T2

W2

PCIE5_CTX_DRX_N

W4

W3
V2

SATA_CTX_DRX_P0SATA_CRX_DTX_P0

V1

SATA_CTX_DRX_N0

V3

U2
U4

PCIE_CTX_GRX_P0
PCIE_CTX_GRX_N0

PCIE_CTX_GRX_P1
PCIE_CTX_GRX_N1

PCIE_CTX_GRX_P2
PCIE_CTX_GRX_N2PCIE_CRX_GTX_N2

PCIE_CTX_GRX_P3
PCIE_CTX_GRX_N3

PCIE_CTX_GRX_P0 17
PCIE_CTX_GRX_N0 17

PCIE_CTX_GRX_P1 17
PCIE_CTX_GRX_N1 17

PCIE_CTX_GRX_P2 17
PCIE_CTX_GRX_N2 17

PCIE_CTX_GRX_P3 17
PCIE_CTX_GRX_N3 17

AC CAP Close to TX output

1 2

CC1 0.1U_0402_10V7-K

1 2

CC2 0.1U_0402_10V7-K

1 2

CC3 0.1U_0402_10V7-K

1 2

CC4 0.1U_0402_10V7-K

1 2

CC5 0.1U_0402_10V7-K

1 2

CC6 0.1U_0402_10V7-K

SATA_CTX_DRX_P0 29
SATA_CTX_DRX_N0 29

PCIE1_CTX_C_DRX_P
PCIE1_CTX_C_DRX_N

PCIE2_CTX_C_DRX_N

PCIE5_CTX_C_DRX_PPCIE5_CTX_DRX_P
PCIE5_CTX_C_DRX_N

CO-LAY RV1 TV2

HDD

GPU

PCIE1_CTX_C_DRX_P 35
PCIE1_CTX_C_DRX_N 35

PCIE2_CTX_C_DRX_P 35
PCIE2_CTX_C_DRX_N 35

PCIE5_CTX_C_DRX_P 37
PCIE5_CTX_C_DRX_N 37

1

LAN

CardRead erCardRead er

WLAN

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. A ND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. A ND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. A ND CONTAINS CONFIDENTIAL
AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CE NTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CE NTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CE NTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

3

2015/10/5

2015/10/5

2015/10/5

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2014/12/05

2014/12/05

2014/12/05

Title

BLANK page

BLANK page

BLANK page

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

JINN/DOOKU

JINN/DOOKU

JINN/DOOKU

Thursday, May 04, 2017

Thursday, May 04, 2017

Thursday, May 04, 2017

5 64

5 64

1

5 64

SDV

SDV

SDV

5

Vinafix

4

3

2

1

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_WE#
DDR_A_CAS#
DDR_A_RAS#

DDR_A_BA0
DDR_A_BA1

DDR_A_BG0

DDR_A_BG1

DDR_A_ACT_N

DDRA_MA_DM0
DDRA_MA_DM1
DDRA_MA_DM2
DDRA_MA_DM3
DDRA_MA_DM4
DDRA_MA_DM5
DDRA_MA_DM6
DDRA_MA_DM7

DDR_A_DQS0
DDR_A_DQS#0
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS7
DDR_A_DQS#7

SA_CLK_DDR0
SA_CLK_DDR#0
SA_CLK_DDR1
SA_CLK_DDR#1

DDR_A_CS0#
DDR_A_CS1#

DDR_A_CKE0
DDR_A_CKE1

DDR_A_ODT0
DDR_A_ODT1

DDR_A_ALERT_N

DDR_A_EVENT#
DDR4_A_DRAMRST#

DDRA_MA_DM[0..7] 14

DDR_A_DQS#[0..7] 14

DDR_A_DQS[0..7] 14

DDR_A_D[0..63] 14

DDR_A_MA[0..13] 14

AF25

MA_ADD0/MAB_CS0

AE23

MA_ADD1/RSVD

AD27

MA_ADD2/RSVD

AE21

MA_ADD3/RSVD

AC24

MA_ADD4/RSVD

AC26

MA_ADD5/RSVD

AD21

MA_ADD6/RSVD

AC27

MA_ADD7/MAA_CA3

AD22

MA_ADD8/MAA_CA4

AC21

MA_ADD9/MAA_CKE1

AF22

MA_ADD10/MAB_CKE0

AA24

MA_ADD11/MAA_CA5

AC23

MA_ADD12/MAA_CA2

AJ25

MA_ADD13_BANK2/RSVD

AG27

MA_WE_L_ADD14/MAB_CA2

AG23

MA_CAS_L_ADD15/MAB_CA4

AG26

MA_RAS_L_ADD16/MAB_CA3

AF21

MA_BANK0/MAB_CS1

AF27

MA_BANK1/MAB_CA0

AA21

MA_BG0/MAA_CS1

AA27

MA_BG1/MAA_CKE0

AA22

MA_ACT_L/MAA_CS0

F21

MA_DM0/MAA_DM1

G27

MA_DM1/MAA_DM0

N24

MA_DM2/MAA_DM2

N23

MA_DM3/MAA_DM3

AL24

MA_DM4/MAB_DM2

AN27

MA_DM5/MAB_DM3

AW25

MA_DM6/MAB_DM1

AT21

MA_DM7/MAB_DM0

T27

RSVD_36

F22

MA_DQS_H0/MAA_DQS_H1

G22

MA_DQS_L0/MAA_DQS_L1

H27

MA_DQS_H1/MAA_DQS_H0

H26

MA_DQS_L1/MAA_DQS_L0

N27

MA_DQS_H2/MAA_DQS_H2

N26

MA_DQS_L2/MAA_DQS_L2

R21

MA_DQS_H3/MAA_DQS_H3

P21

MA_DQS_L3/MAA_DQS_L3

AM26

MA_DQS_H4/MAB_DQS_H2

AM27

MA_DQS_L4/MAB_DQS_L2

AN24

MA_DQS_H5/MAB_DQS_H3

AN25

MA_DQS_L5/MAB_DQS_L3

AU23

MA_DQS_H6/MAB_DQS_H1

AT23

MA_DQS_L6/MAB_DQS_L1

AV20

MA_DQS_H7/MAB_DQS_H0

AW20

MA_DQS_L7/MAB_DQS_L0

V24

RSVD_41

V23

RSVD_40

AD25

MA_CLK_H0/MAA_CKT

AD24

MA_CLK_L0/MAA_CKC

AE26

MA_CLK_H1/MAB_CKT

AE27

MA_CLK_L1/MAB_CKC

AG21

MA_CS_L0/MAB_CKE1

AJ27

MA_CS_L1/RSVD

Y23

MA_CKE0/MAA_CA0

Y26

MA_CKE1/MAA_CA1

AG24

MA_ODT0/MAB_CA5

AJ22

MA_ODT1/RSVD

AA25

MA_ALERT_L/MA_TEST

AE24

MA_EVENT_L

Y24

MA_RESET_L

FP5 REV 0.90

PART 1 OF 13

UC1A

MEMORY A

MA_DATA16/MAA_DATA17
MA_DATA17/MAA_DATA16
MA_DATA18/MAA_DATA23
MA_DATA19/MAA_DATA20
MA_DATA20/MAA_DATA19
MA_DATA21/MAA_DATA18
MA_DATA22/MAA_DATA21
MA_DATA23/MAA_DATA22

MA_DATA24/MAA_DATA30
MA_DATA25/MAA_DATA31
MA_DATA26/MAA_DATA26
MA_DATA27/MAA_DATA27
MA_DATA28/MAA_DATA28
MA_DATA29/MAA_DATA29
MA_DATA30/MAA_DATA24
MA_DATA31/MAA_DATA25

MA_DATA32/MAB_DATA16
MA_DATA33/MAB_DATA17
MA_DATA34/MAB_DATA22
MA_DATA35/MAB_DATA20
MA_DATA36/MAB_DATA19
MA_DATA37/MAB_DATA18
MA_DATA38/MAB_DATA23
MA_DATA39/MAB_DATA21

MA_DATA40/MAB_DATA30
MA_DATA41/MAB_DATA31
MA_DATA42/MAB_DATA26
MA_DATA43/MAB_DATA27
MA_DATA44/MAB_DATA28
MA_DATA45/MAB_DATA29
MA_DATA46/MAB_DATA24
MA_DATA47/MAB_DATA25

MA_DATA48/MAB_DATA11
MA_DATA49/MAB_DATA10
MA_DATA50/MAB_DATA15
MA_DATA51/MAB_DATA14
MA_DATA52/MAB_DATA12
MA_DATA53/MAB_DATA13

MA_DATA0/MAA_DATA8

MA_DATA1/MAA_DATA9
MA_DATA2/MAA_DATA13
MA_DATA3/MAA_DATA12
MA_DATA4/MAA_DATA11
MA_DATA5/MAA_DATA10
MA_DATA6/MAA_DATA15
MA_DATA7/MAA_DATA14

MA_DATA8/MAA_DATA0

MA_DATA9/MAA_DATA1
MA_DATA10/MAA_DATA5
MA_DATA11/MAA_DATA4
MA_DATA12/MAA_DATA7
MA_DATA13/MAA_DATA6
MA_DATA14/MAA_DATA2
MA_DATA15/MAA_DATA3

MA_DATA54/MAB_DATA9
MA_DATA55/MAB_DATA8

MA_DATA56/MAB_DATA5
MA_DATA57/MAB_DATA6
MA_DATA58/MAB_DATA2
MA_DATA59/MAB_DATA3
MA_DATA60/MAB_DATA7
MA_DATA61/MAB_DATA4
MA_DATA62/MAB_DATA1
MA_DATA63/MAB_DATA0

RSVD_34
RSVD_35
RSVD_51
RSVD_52
RSVD_27
RSVD_28
RSVD_43
RSVD_42

MA_PAROUT/MAB_CA1

J21
H21
F23
H23
G20
F20
J22
J23

G25
F26
L24
L26
L23
F25
K25
K27

M25
M27
P27
R24
L27
M24
P24
P25

M22
N21
T22
V21
L21
M20
R23
T21

AL27
AL25
AP26
AR27
AK26
AK24
AM24
AP27

AM23
AM21
AR25
AU27
AL22
AL21
AP24
AP23

AW26
AV25
AV22
AW22
AU26
AV27
AW23
AT22

AW21
AU21
AP21
AN20
AR22
AN22
AT20
AR20

T24
T25
W25
W27
R26
R27
V27
V26

AF24

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7

DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15

DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23

DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31

DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39

DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47

DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55

DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR_A_PARITY DDR_B_ALERT_N

DDR_A_PARITY 14

DDR_B_WE#15
DDR_B_CAS#15
DDR_B_RAS#15

DDR_B_BA015
DDR_B_BA115

DDR_B_BG015
DDR_B_BG115

DDR_B_ACT_N15

SB_CLK_DDR015
SB_CLK_DDR#015
SB_CLK_DDR115
SB_CLK_DDR#115

DDR_B_CS0#15
DDR_B_CS1#15

DDR_B_CKE015
DDR_B_CKE115

DDR_B_ODT015
DDR_B_ODT115

DDR_B_ALERT_N15

DDR_B_EVENT#15
DDR4_B_DRAMRST#15

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_WE#
DDR_B_CAS#
DDR_B_RAS#

DDR_B_BA0
DDR_B_BA1

DDR_B_BG0
DDR_B_BG1

DDR_B_ACT_N

DDRA_MB_DM0
DDRA_MB_DM1
DDRA_MB_DM2
DDRA_MB_DM3
DDRA_MB_DM4
DDRA_MB_DM5
DDRA_MB_DM6
DDRA_MB_DM7

DDR_B_DQS0
DDR_B_DQS#0
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS7
DDR_B_DQS#7

SB_CLK_DDR0
SB_CLK_DDR#0
SB_CLK_DDR1
SB_CLK_DDR#1

DDR_B_CS0#
DDR_B_CS1#

DDR_B_CKE0
DDR_B_CKE1

DDR_B_ODT0
DDR_B_ODT1

DDR_B_EVENT#
DDR4_B_DRAMRST#

AG30

MB_ADD0/MBB_CS0

AC32

MB_ADD1/RSVD

AC30

MB_ADD2/RSVD

AB29

MB_ADD3/RSVD

AB31

MB_ADD4/RSVD

AA30

MB_ADD5/RSVD

AA29

MB_ADD6/RSVD

Y30

MB_ADD7/MBA_CA3

AA31

MB_ADD8/MBA_CA4

W29

MB_ADD9/MBA_CKE1

AH29

MB_ADD10/MBB_CKE0

Y32

MB_ADD11/MBA_CA5

W31

MB_ADD12/MBA_CA2

AL30

MB_ADD13_BANK2/RSVD

AK30

MB_WE_L_ADD14/MBB_CA2

AK32

MB_CAS_L_ADD15/MBB_CA4

AJ30

MB_RAS_L_ADD16/MBB_CA3

AH31

MB_BANK0/MBB_CS1

AG32

MB_BANK1/MBB_CA0

V31

MB_BG0/MBA_CS1

V29

MB_BG1/MBA_CKE0

V30

MB_ACT_L/MBA_CS0

C21

MB_DM0/MBA_DM1

C25

MB_DM1/MBA_DM0

E32

MB_DM2/MBA_DM2

K30

MB_DM3/MBA_DM3

AP30

MB_DM4/MBB_DM2

AW31

MB_DM5/MBB_DM3

BB26

MB_DM6/MBB_DM1

BD22

MB_DM7/MBB_DM0

N32

RSVD_21

D22

MB_DQS_H0/MBA_DQS_H1

B22

MB_DQS_L0/MBA_DQS_L1

D25

MB_DQS_H1/MBA_DQS_H0

B25

MB_DQS_L1/MBA_DQS_L0

F29

MB_DQS_H2/MBA_DQS_H2

F30

MB_DQS_L2/MBA_DQS_L2

K31

MB_DQS_H3/MBA_DQS_H3

K29

MB_DQS_L3/MBA_DQS_L3

AR29

MB_DQS_H4/MBB_DQS_H2

AR31

MB_DQS_L4/MBB_DQS_L2

AW30

MB_DQS_H5/MBB_DQS_H3

AW29

MB_DQS_L5/MBB_DQS_L3

BC25

MB_DQS_H6/MBB_DQS_H1

BA25

MB_DQS_L6/MBB_DQS_L1

BC22

MB_DQS_H7/MBB_DQS_H0

BA22

MB_DQS_L7/MBB_DQS_L0

N31

RSVD_20

N29

RSVD_18

AC31

MB_CLK_H0/MBA_CKT

AD30

MB_CLK_L0/MBA_CKC

AD29

MB_CLK_H1/MBB_CKT

AD31

MB_CLK_L1/MBB_CKC

AE30

RSVD_89

AE32

RSVD_90

AF29

RSVD_91

AF31

RSVD_92

AJ31

MB_CS_L0/MBB_CKE1

AM31

MB_CS_L1/RSVD

AJ29

RSVD_95

AM29

RSVD_97

U29

MB_CKE0/MBA_CA0

T30

MB_CKE1/MBA_CA1

V32

RSVD_93

U31

RSVD_94

AL31

MB_ODT0/MBB_CA5

AM32

MB_ODT1/RSVD

AL29

RSVD_96

AM30

RSVD_98

W30

MB_ALERT_L/MB_TEST

AG29

MB_EVENT_L

T31

MB_RESET_L

MEMORY B

FP5 REV 0.90

PART 9 OF 13

AMD-RAVEN-FP5_BGA1140

D D

DDR_A_WE#14
DDR_A_CAS#14

C C

B B

DDR_A_RAS#14

DDR_A_BA014
DDR_A_BA114

DDR_A_BG014
DDR_A_BG114

DDR_A_ACT_N14

SA_CLK_DDR014

SA_CLK_DDR#014

SA_CLK_DDR114

SA_CLK_DDR#114

DDR_A_CS0#14
DDR_A_CS1#14

DDR_A_CKE014
DDR_A_CKE114

DDR_A_ODT014
DDR_A_ODT114

DDR_A_ALERT_N14

DDR_A_EVENT#14
DDR4_A_DRAMRST#14

UC1I

MB_DATA0/MBA_DATA8

MB_DATA1/MBA_DATA9
MB_DATA2/MBA_DATA13
MB_DATA3/MBA_DATA12
MB_DATA4/MBA_DATA11
MB_DATA5/MBA_DATA10
MB_DATA6/MBA_DATA15
MB_DATA7/MBA_DATA14

MB_DATA8/MBA_DATA0

MB_DATA9/MBA_DATA1
MB_DATA10/MBA_DATA5
MB_DATA11/MBA_DATA4
MB_DATA12/MBA_DATA7
MB_DATA13/MBA_DATA6
MB_DATA14/MBA_DATA2
MB_DATA15/MBA_DATA3

MB_DATA16/MBA_DATA19
MB_DATA17/MBA_DATA18
MB_DATA18/MBA_DATA22
MB_DATA19/MBA_DATA23
MB_DATA20/MBA_DATA20
MB_DATA21/MBA_DATA21
MB_DATA22/MBA_DATA17
MB_DATA23/MBA_DATA16

MB_DATA24/MBA_DATA30
MB_DATA25/MBA_DATA31
MB_DATA26/MBA_DATA26
MB_DATA27/MBA_DATA27
MB_DATA28/MBA_DATA28
MB_DATA29/MBA_DATA29
MB_DATA30/MBA_DATA25
MB_DATA31/MBA_DATA24

MB_DATA32/MBB_DATA16
MB_DATA33/MBB_DATA17
MB_DATA34/MBB_DATA21
MB_DATA35/MBB_DATA20
MB_DATA36/MBB_DATA19
MB_DATA37/MBB_DATA18
MB_DATA38/MBB_DATA23
MB_DATA39/MBB_DATA22

MB_DATA40/MBB_DATA24
MB_DATA41/MBB_DATA25
MB_DATA42/MBB_DATA29
MB_DATA43/MBB_DATA28
MB_DATA44/MBB_DATA31
MB_DATA45/MBB_DATA30
MB_DATA46/MBB_DATA26
MB_DATA47/MBB_DATA27

MB_DATA48/MBB_DATA11
MB_DATA49/MBB_DATA10
MB_DATA50/MBB_DATA14
MB_DATA51/MBB_DATA15
MB_DATA52/MBB_DATA12
MB_DATA53/MBB_DATA13

MB_DATA54/MBB_DATA9
MB_DATA55/MBB_DATA8

MB_DATA56/MBB_DATA6
MB_DATA57/MBB_DATA7
MB_DATA58/MBB_DATA2
MB_DATA59/MBB_DATA3
MB_DATA60/MBB_DATA4
MB_DATA61/MBB_DATA5
MB_DATA62/MBB_DATA1
MB_DATA63/MBB_DATA0

MB_PAROUT/MBB_CA1

DDRA_MB_DM[0..7] 15

DDR_B_DQS#[0..7] 15

DDR_B_DQS[0..7] 15

DDR_B_D[0..63] 15

DDR_B_MA[0..13] 15

B21
D21
B23
D23
A20
C20
A22
C22

D24
A25
D27
C27
C23
B24
C26
B27

C30
E29
H29
H31
A28
D28
F31
G30

J29
J31
L29
L31
H30
H32
L30
L32

AP29
AP32
AT29
AU32
AN30
AP31
AR30
AT31

AU29
AV30
BB30
BA28
AU30
AU31
AY32
AY29

BA27
BC27
BA24
BC24
BD28
BB27
BB25
BD25

BC23
BB22
BC21
BD20
BB23
BA23
BB21
BA21

M31

RSVD_17

N30

RSVD_19

P31

RSVD_26

R32

RSVD_29

M30

RSVD_16

M29

RSVD_15

P30

RSVD_25

P29

RSVD_24

AG31

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7

DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15

DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23

DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31

DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39

DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47

DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55

DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

DDR_B_PARITY

DDR_B_PARITY 15

A A

Title

Title

Title

Switch

Switch

Switch

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

JINN/DOOKU

JINN/DOOKU

JINN/DOOKU

Thursday, May 04, 2017

Thursday, May 04, 2017

Thursday, May 04, 2017

6 64

6 64

1

6 64

SDV

SDV

SDV

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. A ND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. A ND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. A ND CONTAINS CONFIDENTIAL
AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CE NTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CE NTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CE NTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

2015/10/5

2015/10/5

2015/10/5

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2014/12/05

2014/12/05

2014/12/05

5

+1.8VALW

CC103

12

1

2

APU_AZ_SDIN038

RC28
10K_0402_5%

RSMRST#

PBTN_OUT#42

PWR_GOOD42

EC_WAKE#42

PM_SLP_S3#42
PM_SLP_S5#9,42

AC_PRESENT42

RC129 0_0402_5%

1 2

DC1

RB751V-40_SOD323-2

12

33_0402_5%

AZ_RST#
AZ_SYNC
AZ_SDOUT

1 2

SCS00008K00

@

RC109
100K_0402_5%

AZ_BITCLK

0.1U_0402_10V7-K

EC_RSMRST#42

D D

+3VALW

@

RC133 10K_0402_5%

+3VALW

RPC5

1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

PWR_GOOD

PLT_RST#_R_G

C C

APU_AZ_BITCLK38

APU_AZ_RST#38
APU_AZ_SYNC38
APU_AZ_SDOUT38

CC14

10P_0402_50V8-J

12

Str ap

AC_PRESENT

SYS_RESET#
PBTN_OUT#
EC_WAKE#

BATLOW#

12

100K_0402_5%@

RC134

1 2

EMC@

1

EMC_NS@

2

RPC7

1 8
2 7
3 6
4 5

33_0804_8P4R_5%

EMC@

RC146

4

RC157

1 2

33_0402_5%

Test_Point_20MIL

FN_LED#46

PLT_RST#_R_G

2

CC106
150P_0201_25V9-J

1

1

TPC24

SYS_RESET#

EC_WAKE#

PM_SLP_S3#
PM_SLP_S5#

BOARD_ID1

AC_PRESENT
BATLOW#

PLT_RST#_R_G 17

0.1U_0402_10V7-K

PLT_RST#_R

PCIE_RST1_L/EGPIO27

RSMRST#

PBTN_OUT#
PWR_GOOD

AZ_BITCLK

APU_AZ_SDIN0

APU_AZ_SDIN1
APU_AZ_SDIN2
AZ_RST#
AZ_SYNC
AZ_SDOUT

FN_LED#
BOARD_ID0

3

+3VALW

1

CC105

@

2

5

UC7

1

P

B

4

Y

2

A

G

MC74VHC1G09DFT2G_SC70-5

3

@

RC155 0_0402_5%

1 2

ACPI/AUDIO/I2C/GPI O/MIS C

BD5

PCIE_RST0_L/EGPIO26

BB6

PCIE_RST1_L/EGPIO27

AT16

RSMRST_L

AR15

PWR_BTN_L/AGPIO0

AV6

PWR_GOOD

AP10

SYS_RESET_L/AGPIO1

AV11

WAKE_L/AGPIO2

AV13

SLP_S3_L

AT14

SLP_S5_L

AR8

S0A3_GPIO/AGPIO10

AT10

AC_PRES/AGPIO23

AN6

LLB_L/AGPIO12

AW8

EGPIO42

AR2

AZ_BITCLK/TDM_BCLK_MIC

AP7

AZ_SDIN0/CODEC_GPI

AP1

AZ_SDIN1/SW_DATA1B/TDM_BCLK_PLAYBACK

AP4

AZ_SDIN2/SW_DATA2/TDM_DATA_PLAYBACK

AP3

AZ_RST_L/SW_DATA1A/SW_DATA3/TDM_DATA_MIC

AR4

AZ_SYNC/TDM_FRM_MIC

AR3

AZ_SDOUT/TDM_FRM_PLAYBACK

AT2

SW_MCLK/TDM_BCLK_BT

AT4

SW_DATA0/TDM_DOUT_BT

AR6

AGPIO7/FCH_ACP_I2S_SDIN_BT

AP6

AGPIO8/FCH_ACP_I2S_LRCLK_BT

+3VALW

12

RC154

@

10K_0402_5%

Implement IO connect side

UC1D

PSA_I2C_SCL

PSA_I2C_SDA

AGPIO3

AGPIO9
AGPIO40
AGPIO69
AGPIO86

AW12
AU12

AR13
AT13

AN8
AN9

BC20
BA20

AM9
AM10

L16
M16

AT15
AW10

AP9
AU10
AV15

AU7
AU6
AW13
AW15

AU14
AU16
AV8

AW16
BD15

AR18
AT18

EGPIO41/SFI_S5_EGPIO41
AGPIO39/SFI_S5_AGPIO39

I2C0_SCL/SFI0_I2C_SCL/EGPIO151

I2C0_SDA/SFI0_I2C_SDA/EGPIO152

I2C1_SCL/SFI1_I2C_SCL/EGPIO149

I2C1_SDA/SFI1_I2C_SDA/EGPIO150

I2C2_SCL/EGPIO113/SCL0
I2C2_SDA/EGPIO114/SDA0

I2C3_SCL/AGPIO19/SCL1

I2C3_SDA/AGPIO20/SDA1

AGPIO4/SATAE_IFDET

SATA_ACT_L/AGPIO130

FP5 REV 0.90

PART 4 OF 13

AMD-RAVEN-FP5_BGA1140

AGPIO5/DEVSLP0
AGPIO6/DEVSLP1

INTRUDER_ALERT

SPKR/AGPIO91
BLINK/AGPIO11

GENINT1_L/AGPIO89
GENINT2_L/AGPIO90

FANIN0/AGPIO84

FANOUT0/AGPIO85

TPC19 Test_Point_12MIL

TPC20 Test_Point_12MIL

TPC21 Test_Point_12MIL

TPC22 Test_Point_12MIL

PLT_RST# 35,37,42

EGPIO151
EGPIO152

EGPIO149
EGPIO150

APU_SMB0CLK
APU_SMB0DATA

APU_SMB1CLK
APU_SMB1DATA

PSA_I2C_SCL
PSA_I2C_SDA

HDD_DEVSLP

EC_SMI#

F4_LED#

1

TPC31 Test_Point_20MIL

APU_SPKR

NUMLOCK_LED#
F1_LED#

RF_OFF#
BT_ON

2

1

1

1

1

APU_SMB0CLK

APU_SMB0DATA

HDD_DEVSLP 30

EC_SMI# 42

F4_LED# 46

APU_SPKR 39

NUMLOCK_LED# 46
F1_LED# 46

RF_OFF# 37
BT_ON 37

PM_SLP_S3#

PM_SLP_S5#

RSMRST#

PBTN_OUT#

RC32

RC33

APU_SMB1CLK

APU_SMB1DATA

1 2

1 2

RC149

1 2

RC150

1 2

@

@

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

1 4
2 3

APU_SMB1_CLK
APU_SMB1_DATA
APU_SMB0CLK
APU_SMB0DATA

RPC12

4.7K_0404_4P2R_5%

@

APU_SMB_CK0 9,14,15

APU_SMB_DA0 9,14,15

APU_SMB1_CLK 46

APU_SMB1_DATA 46

PSA_I2C_SDA
PSA_I2C_SCL

APU_SMB_CK0

APU_SMB_DA0

APU_SMB1_CLK

APU_SMB1_DATA

RC9 Implement KB connect side

FN_LED#
NUMLOCK_LED#
F4_LED#
F1_LED#

RF_OFF#

BT_ON

1

+1.8VS

DIMM1, DIMM2

TOUCHPAD

RPC6

1 8
2 7
3 6
4 5

2.2K_0804_8P4R_5%

RPC9

1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

@

@

RC36 10K_0402_5%

RC37 10K_0402_5%

12

@

12

+3VS

+3VS

@

PCIE_RST1_L/EGPIO27

RC11710K_0402_5%

RPC10

1 4
2 3

10K_0404_4P2R_5%

@

BOARD_ID0

BOARD_ID1

12

APU_AZ_SDIN2

APU_AZ_SDIN1

PX@

2K_0402_1%

2K_0402_1%

5

RC41

RC43

UMA@

12

RC42

2K_0402_1%

12

RC44

2K_0402_1%

+3VALW

12

12

SW Can't pull down change to stuff 4/25

12

+3VS

2

G

6 1

D

2N7002KDWH_SOT363-6

15@

APU_SMB1DATA APU_SMB1_DATA

14@

4

QC9A

2N7002KDWH_SOT363-6

APU_SMB1_CLKAPU_SMB1CLK

S

5

G

3 4

D

QC9B

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. A ND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. A ND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. A ND CONTAINS CONFIDENTIAL
AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CE NTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CE NTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CE NTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

3

TP SMB port

Vgs(th) Max >=2.0V

TOUCHPAD

S

2015/10/5

2015/10/5

2015/10/5

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2014/12/05

2014/12/05

2014/12/05

APU_SMB1CLK

APU_SMB1DATA

RC31 10K_0402_5%

RC110 10K_0402_5%

RC111 10K_0402_5%

RC113 10K_0402_5%

2.2K_0402_5%

2.2K_0402_5%

Thursday, May 04, 2017

Thursday, May 04, 2017

Thursday, May 04, 2017

RC153

RC151

RC152

JINN/DOOKU

JINN/DOOKU

JINN/DOOKU

EC_SMI#

2.2K_0402_5%

Title

Title

Title

Switch

Switch

Switch

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

EGPIO149

12

EGPIO150

12

EGPIO151

12

EGPIO152

+3VALW

12

12

12

SDV

SDV

SDV

7 64

7 64

1

7 64

B B

A A

1

DP0-EDP

A A

HDM I

+1.8VS

APU_THERMTRIP#42

APU_SIC
APU_SID

1

APU_PWROKAPU_RESET#

1

CC8
56P_0402_50V8-J

2

APU_PWROK59

H_PROCHOT#42

APU_RESET#

APU_PWROK

APU_PWROK_H

APU_SVC59
APU_SVD59
APU_SVT59

1 2

RC6 300_0402_5%

1 2

RC8 300_0402_5%

B B

1

CC7

@

56P_0402_50V8-J

2

C C

+1.8VALW

RPC1

1 8
2 7
3 6
4 5

1K_0804_8P4R_5%

HDT@

+3VS

1K_0402_5%

1 2

1K_0402_5%

1 2

+3VS

AMD check can change R value to 2.2K

D D

APU_TDI_H
APU_TMS_H
APU_TCK_H
APU_TRST#_H

RC127

RC128

RPC11

1 4
2 3

2.2K_0404_4P2R_5%

RC1261K_0402_1%

1 2

@

APU_PROCHOT#

APU_ALERT#

APU_THERMTRIP#

CPU_EDP_TX0+26
CPU_EDP_TX0-26

CPU_EDP_TX1+26
CPU_EDP_TX1-26

HDT@

APU_THERMTRIP#

H_PROCHOT#

APU_SVC

APU_SVT

1000P_0402_50V7-K

@

H_HDMI_TX2+28
H_HDMI_TX2-28

H_HDMI_TX1+28
H_HDMI_TX1-28

H_HDMI_TX0+28

H_HDMI_TX0-28

H_HDMI_TXC+28
H_HDMI_TXC-28

APU_TDI_H
APU_TDO_H
APU_TCK_H
APU_TMS_H
APU_TRST#_H

APU_PWROK

1 2

RC164

RC14

APU_SVD

1

CC9

2

CPU_EDP_TX0+
CPU_EDP_TX0-

CPU_EDP_TX1+
CPU_EDP_TX1- CPU_EDP_AUX

H_HDMI_TX2+
H_HDMI_TX2-

H_HDMI_TX1+
H_HDMI_TX1-

H_HDMI_TX0+
H_HDMI_TX0-

H_HDMI_TXC+
H_HDMI_TXC-

0_0402_5%

1 2

RC158

HDT@
HDT@

HDT@

1 2

RC15 0_0402_5%
RC16 0_0402_5%
RC17 0_0402_5%

@

HDT@

APU_PWROK_H

APU_RESET#_H

1 2

RC159

1 2

RC160 0_0402_5%HDT@

1 2

RC161 0_0402_5%HDT@

1 2

RC162 0_0402_5%

1 2

RC163

0_0402_5%

APU_PROCHOT#

0_0402_5%

1 2
1 2
1 2

1

CC10

1000P_0402_50V7-K

2

APU_TRST#_H

1

CC11

0.01U_0201_25V7-K

2

0_0402_5%

0_0402_5%

Cap close to JHDT.9

0.1U_0201_6.3V6-K

APU_TDI
APU_TDO
APU_TCK
APU_TMS
APU_TRST#

APU_DBREQ#

APU_RESET#APU_RESET#_H

APU_SIC
APU_SID
APU_ALERT#

UC6

3

2A

2

GND

1

1A

2

AP16

SVC_RA
SVD_RA
SVT_RA

RPC2

1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

HDT@

CC100

2

AW3

AW4
AW2

C8
A8

D8
B8

B6
C7

C6
D6

E6
D5

E1
C1

F3
E4

F4
F2

AU2
AU4
AU1
AU3
AV3

H14

J14
J15

L19

F16
H16

J16

1

2

SN74LVC2G07YZPR_WCSP6HDT@

DP0_TXP0
DP0_TXN0

DP0_TXP1
DP0_TXN1

DP0_TXP2
DP0_TXN2

DP0_TXP3
DP0_TXN3

DP1_TXP0
DP1_TXN0

DP1_TXP1
DP1_TXN1

DP1_TXP2
DP1_TXN2

DP1_TXP3
DP1_TXN3

TDI
TDO
TCK
TMS
TRST_L
DBREQ_L

RESET_L
PWROK

SIC
SID
ALERT_L
THERMTRIP_L
PROCHOT_L

SVC0
SVD0
SVT0

RC21

1 2

HDT@

HDT@

2Y

VCC

1Y

HDT@

4

5

6

UC1C

DISPLAY/ SVI2/J TAG/TE ST

DP_STEREOSYNC

VDDCR_SOC_SENSE

FP5 REV 0.90
PART 3 OF 13

AMD-RAVEN-FP5_BGA1140

33_0402_5%

+1.8VALW+1.8VALW

RC107
300_0402_5%

1 2

DP_BLON

DP_DIGON

DP_VARY_BL

DP0_AUXP
DP0_AUXN

DP0_HPD

DP1_AUXP
DP1_AUXN

DP1_HPD

DP2_AUXP
DP2_AUXN

DP2_HPD

DP3_AUXP
DP3_AUXN

DP3_HPD

RSVD_4
RSVD_3

RSVD_2

TEST4
TEST5

TEST6

TEST14
TEST15
TEST16
TEST17

TEST31/RSVD

TEST41

TEST470
TEST471

SMU_ZVDD

CORETYPE

VDDP_SENSE

VDDCR_SENSE

VSS_SENSE_A
VSS_SENSE_B

+1.8VALW

11

13

15

17

19

RC108
300_0402_5%

HDT@

1 2

APU_PWROK_BUF

APU_RST#_BUF

APU_ENBKL_R

G15

APU_ENVDD

F15

APU_EDP_PWM_R

L14

D9

CPU_EDP_AUX#

B9

CPU_EDP_HPD

C10

HDMI_CLK

G11

HDMI_DAT

F11

HDMI_HPD

G13

J12
H12
K13

APU_DP3_AUXP

J10

APU_DP3_AUXN

H10

DDIP3_HPD

K8

K15

APU_TEST4

F14

APU_TEST3

F12

APU_TEST2

F10

AP14
AN14

F13

APU_TEST14

G18

APU_TEST15

H19

APU_TEST16

F18

APU_TEST17

F19

APU_TEST31

W24

APU_TEST41

AR11

APU_TEST470

AJ21

APU_TEST471

AK21

P_ZVDDP

V4

AW11

TPC14

VDDP_SENSE

AN11

1

VDDCR_SOC_VCC_SENSE

J19

VDDCR_VCC_SENSE

K18

VDDCR_VSS_SENSE

J18

VSS_SENSE_B

AM11

JHDT1

1

1

2

3

3

4

5

5

6

7

7

8

9

9

10

11

12

13

14

15

16

17

18

19

20

ME@

SAMTE_ASP-136446-07-B

Check again 3/30

DP_STEREOSYNC

TEST4

TEST5

TEST6

CORETYPE

Test_Point_20MIL

APU_TCK_H

2

APU_TMS_H

4

1 2

6

RC20

APU_TDO_H

8

APU_PWROK_BUF

10

APU_RST#_BUF

12

14

1 2

16

18

20

3

APU_ENVDD 26

CPU_EDP_AUX 26

CPU_EDP_AUX# 26

CPU_EDP_HPD 26

HDMI_CLK 28
HDMI_DAT 28
HDMI_HPD 28

APU_DP3_AUXP 33
APU_DP3_AUXN 33

DDIP3_HPD 31,33

1

TPC1 Test_Point_20MIL

1

TPC2 Test_Point_20MIL

1

TPC46 Test_Point_20MIL

TPC3

1

Test_Point_20MIL

TPC4

1

Test_Point_20MIL

TPC5

1

Test_Point_20MIL

1

TPC6 Test_Point_20MIL

1

TPC7 Test_Point_20MIL

1

TPC8 Test_Point_20MIL

1

TPC9 Test_Point_20MIL

1

TPC10 Test_Point_20MIL

1

TPC11 Test_Point_20MIL

1

TPC12 Test_Point_20MIL

1

TPC13 Test_Point_20MIL

RC12196_0402_0.5%

1 2

RC13

1

1

Test_Point_20MIL

TPC18

HDT@

0_0402_5%

RC24

33_0402_5%

HDT@

HDT@

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

3

10K_0402_5%@

1 2

Test_Point_20MIL

TPC15

TPC16

1

Test_Point_20MIL

VDDCR_SOC_VCC_SENSE 59
VDDCR_VCC_SENSE 59

TPC17

1

Test_Point_20MIL

VDDCR_VSS_SENSE 59

APU_TDI_H

APU_DBREQ#

1

CC12

0.01U_0201_25V7-K

2

Issued Date

Issued Date

Issued Date

eDP

HDMI

Typec0

+0.9VS_VDDP

+3VALW_APU

+1.8VALW

12

RC22
1K_0402_1%HDT@

Cap close to JHDT.16

2015/10/5

2015/10/5

2015/10/5

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

APU_ENBKL_R

@

APU_EDP_PWM_R

Deciphered Date

Deciphered Date

Deciphered Date

4

12

4

+3VS

RC1

@

2.2K_0402_5%

12

RC136100K_0402_5%

@

RC4

1 2

2.2K_0402_5%

RC5100K_0402_5%

@

RC10

1 2

12

2.2K_0402_5%

RC11

4.7K_0402_5%

For AMD suggest HDMI driver check HDMI port enable ,change DP_STEREOSYNC from
1k pull down to 1K pull high

APU_SIC

APU_SID

2014/12/05

2014/12/05

2014/12/05

C

2

B

E

3 1

12

C

2

QC8

B

MLMBT3904WT1G NPN SOT323-3

E

SB000010U00

3 1

RC26

1 2

0_0402_5%

RC27

1 2

QC2
MLMBT3904WT1G NPN SOT323-3

SB000010U00

RC9
47K_0402_5%

1 2

0_0402_5%

1 2

13

D

QC1

2

G

S

2N7002WT1G_SC-70-3

@

RC3

1 2

0_0402_5%

+3VS

12

RC7

4.7K_0402_5%

13

D

QC3

2

2N7002WT1G_SC-70-3

G

S

RC135

0_0402_5%

@

DP_STEREOSYNC

EC_SMB_CK3

EC_SMB_DA3

Title

Title

Title

Switch

Switch

Switch

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Thursday, May 04, 2017

Thursday, May 04, 2017

Thursday, May 04, 2017

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

5

ENBKL

12

PANEL_BKLT_CTRL 26

APU_TEST14
APU_TEST16

APU_TEST15

APU_TEST17

JINN/DOOKU

JINN/DOOKU

JINN/DOOKU

RPC3

1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

@

EC_SMB_CK3 18,42,49,50

EC_SMB_DA3 18,42,49,50

5

RC148
100K_0402_5%

+1.8VS

@

8 64

8 64

8 64

ENBKL 42

+1.8VS

RC23
1K_0402_1%

1 2

RC25
1K_0402_1%

1 2

SDV

SDV

SDV

5

+3VS

RPC8

CLKREQ_PCIE1_LAN#

1 8

CLKREQ_PCIE2_CR#

2 7

CLKREQ_PCIE3_WLAN#

D D

C C

B B

3 6
4 5

10K_0804_8P4R_5%

+3VS

10K_0402_5%

RC63

@

1 2

RC147

CLK_REQ5

For layout change RPC9

+1.8V_SPI

1 2

RC122

RC123

1 2

RC124

1 2

RC125

1 2

+1.8VALW

@

RC81

1 2

RC82

1 2

CLKREQ_PCIE7_VGA#

1 2

@

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

8MB(64Mb)

SPI_CS3#

SPI_CS1#

SPI_IO2

SPI_IO3

SPI_CS2#

SPI_CS2#_TPM

12

CC19
10P_0402_50V8-J

RC75

1 2

YC2

1

OSC1

NC2

NC12OSC2

48MHZ_10PF_7V48000017

CLK_PCIE_LAN35
CLK_PCIE_LAN#35

CLK_PCIE_CR35
CLK_PCIE_CR#35

CLK_PCIE_WLAN37
CLK_PCIE_WLAN#37

CLK_PCIE_GPU17
CLK_PCIE_GPU#17

1M_0402_5%

4

3

4

CLKREQ_PCIE1_LAN#

CLKREQ_PCIE1_LAN#35
CLKREQ_PCIE2_CR#35

D_J_CTL26
CLKREQ_PCIE3_WLAN#37

CLKREQ_PCIE7_VGA#18

CLKREQ_PCIE2_CR#

D_J_CTL

CLKREQ_PCIE3_WLAN#

CLKREQ_PCIE7_VGA#

RC48 0_0402_5%

CLK_PCIE_LAN#

CLK_PCIE_CR
CLK_PCIE_CR#

CLK_PCIE_WLAN
CLK_PCIE_WLAN#

CLK_PCIE_GPU
CLK_PCIE_GPU# GFX_CLKN_R

1 2

RC46 0_0402_5%

1 2

RC47 0_0402_5%

1 2

RC52 0_0402_5%

1 2

RC54 0_0402_5%

1 2

RC55 0_0402_5%

1 2

RC58 0_0402_5%

1 2

RC59 0_0402_5%

1 2

RTCCLK_R37

Follow 720S

1

CC16
10P_0402_50V8-J

2

change YC2 PN change to SJ10000MQ00,manual modify PN to SJ1000 0MQ00

X48M_X1

X48M_X2

12

CC20
10P_0402_50V8-J

CLK_REQ5

CLK_PCIE_LAN_RCLK_PCIE_LAN

CLK_PCIE_LAN#_R

CLK_PCIE_CR_R
CLK_PCIE_CR_R#

CLK_PCIE_WLAN_R
CLK_PCIE_WLAN#_R

GFX_CLKP_R

X48M_OSC

1

TPC37Test_Point_20MIL

X48M_X1

X48M_X2

RC64

0_0402_5%

1 2

X32K_X1

RC65

X32K_X2

1 2

20M_0402_5%

YC1

1 2

32.768KHZ_12.5PF_202740-PG14

1

2

AV18

CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/AGPIO92

AN19

CLK_REQ1_L/AGPIO115

AP19

CLK_REQ2_L/AGPIO116

AT19

CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/EGPIO131

AU19

CLK_REQ4_L/OSCIN/EGPIO132

AW18

CLK_REQ5_L/EGPIO120

AW19

CLK_REQ6_L/EGPIO121

AK1

GPP_CLK0P

AK3

GPP_CLK0N

AM2

GPP_CLK1P

AM4

GPP_CLK1N

AM1

GPP_CLK2P

AM3

GPP_CLK2N

AL2

GPP_CLK3P

AL4

GPP_CLK3N

AN2

GPP_CLK4P

AN4

GPP_CLK4N

AN3

GPP_CLK5P

AP2

GPP_CLK5N

AJ2

GPP_CLK6P

AJ4

GPP_CLK6N

AJ3

X48M_OSC

BB3

X48M_X1

BA5

X48M_X2

1

AF8

TPC47Test_Point_20MIL

RSVD_76

AF9

1

TPC48Test_Point_20MIL

RSVD_77

AW14

RTCCLK

RTCCLK

AY1

X32K_X1

AY4

X32K_X2

CC17
10P_0402_50V8-J

3

UC1E

CLK/LPC/EMMC/SD/S PI/e SPI/ UART

EGPIO70/SD_CLK

LPC_PD_L/SD_CMD/AGPIO21

LAD0/SD_DATA0/EGPIO104
LAD1/SD_DATA1/EGPIO105
LAD2/SD_DATA2/EGPIO106
LAD3/SD_DATA3/EGPIO107

LPCCLK0/EGPIO74

LPC_CLKRUN_L/AGPIO88

LPCCLK1/EGPIO75

SERIRQ/AGPIO87

LFRAME_L/EGPIO109

LPC_RST_L/SD_WP_L/AGPIO32

AGPIO68/SD_CD

LPC_PME_L/SD_PWR_CTRL/AGPIO22

SPI_ROM_REQ/EGPIO67

SPI_ROM_GNT/AGPIO76

ESPI_RESET_L/KBRST_L/AGPIO129
ESPI_ALERT_L/LDRQ0_L/EGPIO108

SPI_CLK/ESPI_CLK

SPI_DI/ESPI_DAT1

SPI_DO/ESPI_DAT0

SPI_WP_L/ESPI_DAT2

SPI_HOLD_L/ESPI_DAT3

SPI_CS1_L/EGPIO118

SPI_CS2_L/ESPI_CS_L/AGPIO30

SPI_CS3_L/AGPIO31

SPI_TPM_CS_L/AGPIO29

UART0_RXD/EGPIO136

UART0_TXD/EGPIO138
UART0_RTS_L/UART2_RXD/EGPIO137
UART0_CTS_L/UART2_TXD/EGPIO135

UART0_INTR/AGPIO139

EGPIO141/UART1_RXD

EGPIO143/UART1_TXD
EGPIO142/UART1_RTS_L/UART3_RXD
EGPIO140/UART1_CTS_L/UART3_TXD

AGPIO144/UART1_INTR

FP5 REV 0.90
PART 5 OF 13

AMD-RAVEN-FP5_BGA1140

UC8M1

SPI_CS1#

1

SPI_SO

/CS

2

SPI_IO2

DO(IO1)

/HOLDor/RESET(IO3)

3

/WP(IO2)

4

GND

W25Q64FWSSIQ_SO8

Change to SA00008E400 W25Q128FWSIQ

SPI_CS1#
SPI_SI
SPI_SO
SPI_CLK

BD13
BB14

LPCPD#

LPC_AD0_R

BB12
BC11
BB15
BC15
BA15
BC13
BB13
BC12
BA12

LPC_RST#_R LPC_RST#

BD11
BA11
BA13

BC8
BB8

BB11
BC6

BB7
BA9
BB10
BA10
BC10
BC9
BA8
BA6
BD8

BA16
BB18
BC17
BA18
BD18

BC18
BA17
BC16
BB19
BB16

8

VCC

7
6

CLK

5

DI(IO0)

LPC_AD1_R
LPC_AD2_R
LPC_AD3_R

LPC_CLK0

LPC_CLKRUN#

LPC_CLK1

SERIRQ
LPC_FRAME#

RC56 33_0402_5%

EC_SCI#

KBRST#

LDRQ0#

1 2

RC60

SPI_CS1#
SPI_CS2#
SPI_CS3#
SPI_CS2#_TPM

UART0_RXD_C
UART0_TXD_C
UART0_RTS#
UART0_CTS#
UART0_INTR

DGPU_PWROK
DGPU_PWREN_R
DGPU_HOLD_RST#_R

0.085 A

+1.8V_SPI
SPI_IO3
SPI_CLK
SPI_SI

1 2

RC76 0_0402_5%

1 2

RC77 0_0402_5%

1 2

RC78 0_0402_5%

1 2

RC79 0_0402_5%

1 2

RC45
RC49

1 2

RC50 10_0402_5%

1 2

RC51

1 2
1 2

RC53

1 2

10_0402_5%

SPI_SO
SPI_SI

SPI_IO2
SPI_IO3

+1.8V_SPI

10_0402_5%
10_0402_5%

10_0402_5%

22_0402_5%

EMC@

SPI_CLKSPI_CLK_C

SPI_CS2#_TPM 44

DGPU_PWROK 17

RC69 0_0402_5%

1

CC18

0.1U_0201_16V6-K

2

EC_SPI_CS1#
EC_SPI_SI
EC_SPI_SO
EC_SPI_CLK

1K_0402_5%

0_0402_5%

1 2

EC_SPI_CS1# 42
EC_SPI_SI 42
EC_SPI_SO 42
EC_SPI_CLK 42

LPC_AD0

LPC_AD1

LPC_AD2
LPC_AD3

CLK_PCI_EC 42

SERIRQ 42
LPC_FRAME# 42

LPC_RST# 42

EC_SCI# 42

KBRST# 42

SPI_CLK 44
SPI_SO 44
SPI_SI 44

RC141

PX@

1 2

RC144

1 2

PX@

LPC_AD0 42

LPC_AD1 42
LPC_AD2 42
LPC_AD3 42

DGPU_PWREN
DGPU_HOLD_RST#

+1.8VALW

2

DGPU_PWREN 21,58,60,61,62,63
DGPU_HOLD_RST# 17

Close to APU

DGPU_HOLD_RST#_R

LPCPD#

LPC_CLK1

LPC_RST#

DGPU_HOLD_RST#_R

SPI_SO

SPI_CLK_C

CC15 150P_0402_50V8-J

CC104 .01U_0402_25V7-K

DGPU_HOLD_RST#_R

DGPU_PWREN_R

LPC_FRAME#

KBRST#

UART0_RXD_C

UART0_TXD_C

UART0_RTS#

UART0_CTS#

UART0_INTR

For AMD suggestion , pull 10k to S0

1

CLK_PCI_EC

EMC_NS@

1 2

RC142

PX@

RC62

1 2

@

RC115

1 2

@

1 2

1 2

PX@

RC143

1 2

RC140

1 2

RC139

1 2

RC67

1 2

@

RC73 1K_0402_5%

1 2

@

RC74 1K_0402_5%

1 2

@

RC71 1K_0402_5%

1 2

@

RC72 1K_0402_5%

1 2

@

RC116 1K_0402_5%

1 2

RC132

1 2

RC83

1 2

Stra p

@

PX@

@

1

2

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

CC102
10P_0402_50V8-J

+3VS

+1.8VS

LPC ROM EMULATOR HEADER

+3VS_APU

CC21

UNNAMED_16_CAP_I116_B

1 2

1 2

15P_0402_50V8-J

@

CLK_PCI_EC
LPC_FRAME#
LPC_RST#

RC87 0_0402_5%

APU_SMB_CK0

+3VS_APU

RC93

CC24

RC91

RC92

LPC@

1 2

1 2

1 2

1 2

@

RC89 0_0402_5%

LPC@

@

100K_0402_5%

150P_0402_50V8-J

APU_SMB_CK07,14,15

A A

5

4

+3VALW

RC84

33_0402_5%

@

10K_0402_5%

10K_0402_5%

RC85
0_0402_5%

LPC@

1 2

1 2

1 2

LPC_RST#_H

LPC@

LPC@

APU_SMB_CK0_LPC

1

CC22

0.1U_0402_10V7-K

2

LPC@

RC3152 RC3 153 should be put on APU side to reduce stub when MP

LPCPD#

LPC_CLKRUN#

LPC_RST#

RC86
0_0402_5%

LPC@

1 2

LPCRUNPWR

1

CC23

0.1U_0402_10V7-K

2

LPC@

PIN4 should be removed as a Key

IT9@

1

IT10 @

IT11@

1

IT12@

1

IT21 @

IT14@

1

IT22 @

IT16@

1

IT24 @

IT17@

1

3

DAISY CHAIN ROUTI NG FOR LPC SIGNALS

UNNAMED_16_CON20_I130_P6

1

1 2

RC88 0_0402_5%@

APU_SMB1_DATA_LPC

1
1

1

LDRQ0#

SERIRQ

1 2

RC90 0_0402_5%

PM_SLP_S5#

LPC@

PM_SLP_S5# 7,42

APU_SMB_DA0 7,14,15

Security C lassification

Security C lassification

Security C lassification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE I NFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE I NFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE I NFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2

2015/10/5

2015/10/5

2015/10/5

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2014/12/05

2014/12/05

2014/12/05

Title

Title

Title

Switch

Switch

Switch

Size

Size

Size

Document Number Rev

Document Number Rev

Document Number Rev

D

D

D

JINN/DOOKU

JINN/DOOKU

JINN/DOOKU

Thursday, May 04, 2017

Thursday, May 04, 2017

Thursday, May 04, 2017

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

9 64

9 64

9 64

SDV

SDV

SDV

5

4

3

2

1

D D

T11

AC7

Y9

Y10

W11
W12

V9

V10

AA12
AC10

+1.8VALW

C C

B B

USBC_I2C_SCL

1 2

RC94

4.7K_0402_5%

USBC_I2C_SDA USBC0_1_TXN0

1 2

RC95

4.7K_0402_5%

+3VALW

RPC13

USB_OC1#

1 4

USB_OC0#

2 3

10K_0404_4P2R_5%

RC99

AGPIO13

1 2

10K_0402_5%

USB_OC2#

RC118
10K_0402_5%@

1 2

USBC0 For Full typec

USB P0

USB3.0 Port1

USB P1

USB3.0 port2

USB P2

IO BOARD

USB3.0

USB P4

CAMERA

USB P5

USB20_P_WLAN37
USB20_N_WLAN37

USB20_P5_CAMERA26
USB20_N5_CAMERA26

INT#_TYPEC_CPU31
USB_OC0#34
USB_OC1#34
USB_OC2#35

USB20_P0

USB20_P033

USB20_N0

USB20_N033

USB20_P1

USB20_P134

USB20_N1

USB20_N134

USB20_P2

USB20_P234

USB20_N2

USB20_N234

USB20_P3

USB20_P335

USB20_N3

USB20_N335

USB20_P_WLAN

USB20_N_WLAN

USB20_P5_CAMERA
USB20_N5_CAMERA

USBC_I2C_SCL

USBC_I2C_SDA

INT#_TYPEC_CPU
USB_OC0#
USB_OC1#
USB_OC2#

AGPIO13

Vgs(th) max= 1.5V

RSVD_32

RSVD_66

RSVD_55
RSVD_56

RSVD_47
RSVD_48

RSVD_38
RSVD_39

RSVD_64
RSVD_68

AE7
AE6

AG10

AG9

AF12
AF11

AE10

AE9

AJ12
AJ11

AD9
AD8

AM6

AM7

AK10

AK9

AL9
AL8

AW7

AT12

FP5 REV 0.90

PART 12 OF 13

USB_0_DP0
USB_0_DM0

USB_0_DP1
USB_0_DM1

USB_0_DP2
USB_0_DM2

USB_0_DP3
USB_0_DM3

USB_1_DP0
USB_1_DM0

USB_1_DP1
USB_1_DM1

USBC_I2C_SCL

USBC_I2C_SDA

USB_OC0_L/AGPIO16
USB_OC1_L/AGPIO17
USB_OC2_L/AGPIO18
USB_OC3_L/AGPIO24
AGPIO14/USB_OC4_L
AGPIO13/USB_OC5_L

USBC_I2C_SCL

UC1L

RSVD

RSVD_62
RSVD_61
RSVD_65

RSVD_72

RSVD_67
RSVD_63

RSVD_33
RSVD_73

RSVD_53
RSVD_54

RSVD_45
RSVD_46

AMD-RAVEN-FP5_BGA1140

USB

USBC0_A2/USB_0_TXP0/DP3_TXP2
USBC0_A3/USB_0_TXN0/DP3_TXN2

USBC0_B11/USB_0_RXP0/DP3_TXP3
USBC0_B10/USB_0_RXN0/DP3_TXN3

USBC1_A2/USB_0_TXP3/DP2_TXP2
USBC1_A3/USB_0_TXN3/DP2_TXN2

USBC1_B11/USB_0_RXP3/DP2_TXP3
USBC1_B10/USB_0_RXN3/DP2_TXN3

FP5 REV 0.90

PART 10 OF 13

LBSS138LT1G_SOT-23-3

AA9
AA8
AC6

AD11

AC9
AA11

T12
AD12

Y6
Y7

W8
W9

UC1J

USBC0_B2/DP3_TXP1
USBC0_B3/DP3_TXN1

USBC0_A11/DP3_TXP0
USBC0_A10/DP3_TXN0

USB_0_TXP1
USB_0_TXN1

USB_0_RXP1
USB_0_RXN1

USB_0_TXP2
USB_0_TXN2

USB_0_RXP2
USB_0_RXN2

USBC1_B2/DP2_TXP1
USBC1_B3/DP2_TXN1

USBC1_A11/DP2_TXP0
USBC1_A10/DP2_TXN0

USB_1_TXP0
USB_1_TXN0

USB_1_RXP0
USB_1_RXN0

AMD-RAVEN-FP5_BGA1140

+1.8VALW

G

2

13

D

S

QC4

AD2
AD4

AC2
AC4

AF4
AF2

AE3
AE1

AG3
AG1

AJ9
AJ8

AG4
AG2

AG7
AG6

AA2
AA4

Y1
Y3

AC1
AC3

AB2
AB4

AH4
AH2

AK7
AK6

REPETER_SCL

USBC0_0_TXP0
USBC0_0_TXN0

USBC0_0_RXP0
USBC0_0_RXN0

USBC0_1_TXP0

USBC0_1_RXP0
USBC0_1_RXN0

USB3P1_TXP
USB3P1_TXN

USB3P1_RXP
USB3P1_RXN

USB3P2_TXP
USB3P2_TXN

USB3P2_RXP
USB3P2_RXN

PD I2C port

USBC0_0_TXP0 33
USBC0_0_TXN0 33

USBC0_0_RXP0 33

USBC0_0_RXN0 33

USBC0_1_TXP0 33
USBC0_1_TXN0 33

USBC0_1_RXP0 33

USBC0_1_RXN0 33

USB3P1_TXP 34
USB3P1_TXN 34

USB3P1_RXP 34

USB3P1_RXN 34

USB3P2_TXP 34
USB3P2_TXN 34

USB3P2_RXP 34

USB3P2_RXN 34

REPETER_SCL 31,33

USB Typec 0

USB Typec integrated USBC SWITCH with DP

USB3.0 Port1

USB3.0 port2

USBC0_A2/USB_0_ TXP0/DP3_TXP[ 2]1
USBC0_A3/USB_0_TXN0/DP3_TXN[2]1 O-IOVP-D USB Super Speed Port Transmit
USBC0_B11/USB_0 _RXP0/DP3_TXP [3]1
USBC0_B10/USB_0_RXN0/DP3_TXN[3]1 B-IOVP-D USB Super Speed Port Receive
USBC1_A11/DP2 _TXP[0]1
USBC1_A10/DP2_TXN[0]1 B-IOVP-D USB Super Speed Port Receive
USBC1_B2/DP 2_TXP[1]1
USBC1_B3/DP2_TXN[1]1 O-IOVP-D USB Super Speed Port Transmit
USBC1_A2/USB_0_ TXP3/DP2_TXP[ 2]1
USBC1_A3/USB_0_TXN3/DP2_TXN[2]1 O-IOVP-D USB Super Speed Port Transmit
USBC1_B11/USB_0 _RXP3/DP2_TXP [3]1
B-IOVP-D USB Super Speed Port Receive

USBC0_A11/DP3 _TXP[0]1
USBC0_A10/DP3_TXN[0]1 B-IOVP-D USB Super Speed Port Receive
USBC0_B2/DP 3_TXP[1]1
USBC0_B3/DP3_TXN[1]1 O-IOVP-D USB Super Speed Port Transmit

G

2

USBC_I2C_SDA

LBSS138LT1G_SOT-23-3

A A

5

4

REPETER_SDA

13

D

S

QC5

REPETER_SDA 31,33

3

Security C lassification

Security C lassification

Security C lassification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE I NFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE I NFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE I NFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2

2015/10/5

2015/10/5

2015/10/5

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2014/12/05

2014/12/05

2014/12/05

Title

Title

Title

Switch

Switch

Switch

Size

Size

Size

Document Number Rev

Document Number Rev

Document Number Rev

D

D

D

JINN/DOOKU

JINN/DOOKU

JINN/DOOKU

Thursday, May 04, 2017

Thursday, May 04, 2017

Thursday, May 04, 2017

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

1

10 64

10 64

10 64

SDV

SDV

SDV

5

D D

C C

4

UC1M

CAM0_CSI2_CLOCKP
CAM0_CSI2_CLOCKN

CAM0_CSI2_DATAP0
CAM0_CSI2_DATAN0

CAM0_CSI2_DATAP1
CAM0_CSI2_DATAN1

CAM0_CSI2_DATAP2
CAM0_CSI2_DATAN2

CAM0_CSI2_DATAP3
CAM0_CSI2_DATAN3

CAM1_CSI2_CLOCKP
CAM1_CSI2_CLOCKN

CAM1_CSI2_DATAP0
CAM1_CSI2_DATAN0

CAM1_CSI2_DATAP1
CAM1_CSI2_DATAN1

RSVD_6

CAMERAS

FP5 REV 0.90

PART 13 OF 13

AMD-RAVEN-FP5_BGA1140

CAM0_I2C_SCL

CAM0_I2C_SDA

CAM0_SHUTDOWN

CAM1_I2C_SCL

CAM1_I2C_SDA

CAM1_SHUTDOWN

CAM_PRIV_LED

A18
C18

A15
C15

B16
C16

C19
B18

B17
D17

D12
B12

C13
A13

B11
C12

J13

CAM0_CLK

CAM1_CLK

CAM_IR_ILLU

3

B15

D15
C14

B13

B10

A11
C11

D11

D13
D10

2

1

B B

A A

Title

Title

Security C lassification

Security C lassification

Security C lassification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE I NFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE I NFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE I NFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2

2015/10/5

2015/10/5

2015/10/5

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2014/12/05

2014/12/05

2014/12/05

Title

Switch

Switch

Switch

Size

Size

Size

Document Number Rev

Document Number Rev

Document Number Rev

D

D

D

JINN/DOOKU

JINN/DOOKU

JINN/DOOKU

Thursday, May 04, 2017

Thursday, May 04, 2017

Thursday, May 04, 2017

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

11 64

11 64

11 64

SDV

SDV

SDV

5

4

3

2

1

D D

All BU(on bottom side under SOC)

+3VS_APU+3VS

@

2

J2 JUMP_43X39

112

+3VALW_APU+3VALW

@

2

J3 JUMP_43X39

112

+1.8VS

+3VS_APU

1

CC46

BO

2

22U_0603_6.3V6-M

C C

+3VALW_APU

CC72

1

1

BU

CC71

BO

2

2

22U_0603_6.3V6-M

+0.9VALW_VDDP

CC84

1

BU

CC83

1

BO

B B

+0.9VS_VDDP

2

22U_0603_6.3V6-M

1

1

BU

BO BU

BO

CC90

CC89

2

2

22U_0603_6.3V6-M

22U_0603_6.3V6-M

2

1U_0201_6.3V6-M

CC91

1

2

1U_0201_6.3V6-M

+1.8VS

CC39

CC38

1

1

BO

BU

2

2

1U_0201_6.3V6-M

1U_0201_6.3V6-M

CC73

BO

1

2

1U_0201_6.3V6-M

1U_0201_6.3V6-M

CC85

CC86

BO

BU

1

1

2

2

1U_0201_6.3V6-M

CC94

CC92

CC93

1

1

1

BU

BU

2

2

2

1U_0201_6.3V6-M

1U_0201_6.3V6-M

CC41

BO

BU

1

1

1

CC40

BO

2

22U_0603_6.3V6-M

+1.8VALW

CC47

2

2

1U_0402_6.3V7-K

1U_0201_6.3V6-M

CC76

CC75

BO

BU

1

1

1

CC74

BO

2

2

2

22U_0603_6.3V6-M

1U_0201_6.3V6-M

+0.9VALW_VDDP

1A

1U_0201_6.3V6-M

+3VALW_APU

0.25 A

+RTC_LDO

1U_0201_6.3V6-M

BO

CC95

1

2

1U_0201_6.3V6-M

CC97

CC98

CC96

1

1

1

BO

BO

2

2

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1

BU

180P_0402_50V8-J

BO

CC99

2

2

1U_0201_6.3V6-M

1U_0201_6.3V6-M

+1.5VS

+1.8VALW

1 2

+1.8VS

0.5A

+0.9VS_VDDP

1K_0402_5%

Reserves for 1.8V HDA for codec

RC156
0_0603_5%

@

1 2

+VDDIO_AZ

RC100

0_0603_5%

1

CC55

BO

2

22U_0603_6.3V6-M

2A

4A

RC101

1 2

BU

+3VS_APU

+RTC_LDO

1

2

CC56

1U_0402_6.3V7-K

0.25 A

+RTC_LDO

+1.2V

+VDDIO_AZ

+VDDBT_RTC

1

CC87

2

+VDDCR_SOC

10A

M15
M18
M19

N16
N18
N20
P17
P19
R18
R20
T19
U18
U20

V19
W18
W20

Y19

T32

V28
W28
W32

Y22

Y25

Y28

AA20
AA23
AA26
AA28
AA32
AC20
AC22
AC25
AC28
AD23
AD26
AD28
AD32
AE20
AE22
AE25
AE28
AF23
AF26
AF28
AF32
AG20
AG22
AG25
AG28

AJ20
AJ23
AJ26
AJ28
AJ32

AK28
AL28
AL32

AP12

AL18
AM17

AL20
AM19

AL19
AM18

AL17
AM16

AL14
AL15
AM14

AL13
AM12
AM13
AN12
AN13

0.1A

AT11

1

CC88

2

1U_0402_6.3V7-K

0.22U_0402_10V6-K

12

R395

470_0603_5%@

13

D

QC7

S

2N7002KW_SOT323-3

@

VDDCR_SOC_1
VDDCR_SOC_2
VDDCR_SOC_3
VDDCR_SOC_4
VDDCR_SOC_5
VDDCR_SOC_6
VDDCR_SOC_7
VDDCR_SOC_8
VDDCR_SOC_9
VDDCR_SOC_10
VDDCR_SOC_11
VDDCR_SOC_12
VDDCR_SOC_13
VDDCR_SOC_14
VDDCR_SOC_15
VDDCR_SOC_16
VDDCR_SOC_17

VDDIO_MEM_S3_1
VDDIO_MEM_S3_2
VDDIO_MEM_S3_3
VDDIO_MEM_S3_4
VDDIO_MEM_S3_5
VDDIO_MEM_S3_6
VDDIO_MEM_S3_7
VDDIO_MEM_S3_8
VDDIO_MEM_S3_9
VDDIO_MEM_S3_10
VDDIO_MEM_S3_11
VDDIO_MEM_S3_12
VDDIO_MEM_S3_13
VDDIO_MEM_S3_14
VDDIO_MEM_S3_15
VDDIO_MEM_S3_16
VDDIO_MEM_S3_17
VDDIO_MEM_S3_18
VDDIO_MEM_S3_19
VDDIO_MEM_S3_20
VDDIO_MEM_S3_21
VDDIO_MEM_S3_22
VDDIO_MEM_S3_23
VDDIO_MEM_S3_24
VDDIO_MEM_S3_25
VDDIO_MEM_S3_26
VDDIO_MEM_S3_27
VDDIO_MEM_S3_28
VDDIO_MEM_S3_29
VDDIO_MEM_S3_30
VDDIO_MEM_S3_31
VDDIO_MEM_S3_32
VDDIO_MEM_S3_33
VDDIO_MEM_S3_34
VDDIO_MEM_S3_35
VDDIO_MEM_S3_36
VDDIO_MEM_S3_37
VDDIO_MEM_S3_38
VDDIO_MEM_S3_39
VDDIO_MEM_S3_40

VDDIO_AUDIO

VDD_33_1
VDD_33_2

VDD_18_1
VDD_18_2

VDD_18_S5_1
VDD_18_S5_2

VDD_33_S5_1
VDD_33_S5_2

VDDP_S5_1
VDDP_S5_2
VDDP_S5_3

VDDP_1
VDDP_2
VDDP_3
VDDP_4
VDDP_5

VDDBT_RTC_G

EC_RTCRST#_ON

2

G

UC1F

POWER

FP5 REV 0.90
PART 6 OF 13

AMD-RAVEN-FP5_BGA1140

12

RC145
100K_0402_5%

@

VDDCR_1
VDDCR_2
VDDCR_3
VDDCR_4
VDDCR_5
VDDCR_6
VDDCR_7
VDDCR_8

VDDCR_9
VDDCR_10
VDDCR_11
VDDCR_12
VDDCR_13
VDDCR_14
VDDCR_15
VDDCR_16
VDDCR_17
VDDCR_18
VDDCR_19
VDDCR_20
VDDCR_21
VDDCR_22
VDDCR_23
VDDCR_24
VDDCR_25
VDDCR_26
VDDCR_27
VDDCR_28
VDDCR_29
VDDCR_30
VDDCR_31
VDDCR_32
VDDCR_33
VDDCR_34
VDDCR_35
VDDCR_36
VDDCR_37
VDDCR_38
VDDCR_39
VDDCR_40
VDDCR_41
VDDCR_42
VDDCR_43
VDDCR_44
VDDCR_45
VDDCR_46
VDDCR_47
VDDCR_48
VDDCR_49
VDDCR_50
VDDCR_51
VDDCR_52
VDDCR_53
VDDCR_54
VDDCR_55
VDDCR_56
VDDCR_57
VDDCR_58
VDDCR_59
VDDCR_60
VDDCR_61
VDDCR_62
VDDCR_63
VDDCR_64
VDDCR_65
VDDCR_66
VDDCR_67
VDDCR_68
VDDCR_69
VDDCR_70
VDDCR_71
VDDCR_72
VDDCR_73
VDDCR_74
VDDCR_75
VDDCR_76
VDDCR_77
VDDCR_78
VDDCR_79
VDDCR_80
VDDCR_81
VDDCR_82
VDDCR_83

EC_RTCRST#_ON 42

+VDDC_VDD

35A

G7
G10
G12
G14
H8
H11
H15
K7
K12
K14
L8
M7
M10
N14
P7
P10
P13
P15
R8
R14
R16
T7
T10
T13
T15
T17
U14
U16
V13
V15
V17
W7
W10
W14
W16
Y8
Y13
Y15
Y17
AA7
AA10
AA14
AA16
AA18
AB13
AB15
AB17
AB19
AC14
AC16
AC18
AD7
AD10
AD13
AD15
AD17
AD19
AE8
AE14
AE16
AE18
AF7
AF10
AF13
AF15
AF17
AF19
AG14
AG16
AG18
AH13
AH15
AH17
AH19
AJ7
AJ10
AJ14
AJ16
AJ18
AK13
AK15
AK17
AK19

All BU(on bottom side under SOC)

All BU(on bottom side under SOC)

+1.2V

1

1

CC59

CC60

2

2

22U_0603_6.3V6-M

22U_0603_6.3V6-M

@

All BU(on bottom side under SOC)

COST DOWN 4 PIECES

+1.2V

DECOUPLING BETWEEN PROCESSOR AND DIMMs

1

1

CC78

CC77

2

2

0.22U_0402_10V6-K

0.22U_0402_10V6-K

All BU(on bottom side under SOC)

4x0.22UF (0402)+2x180PF(0402)

Delete 22U 0603 and place PWR portion under SOC

Need discuss if space enough ,reserves others component

+VDDC_VDD

1

180P_0402_50V8-J

CC44

2

+VDDCR_SOC

1

1

180P_0402_50V8-J

CC58

CC57

2

2

1U_0402_6.3V7-K

1

1

1

1

CC61

CC62

2

2

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

@

ACROSS VDDIO AND VSS SPLIT

1

1

CC79

CC80

2

2

0.22U_0402_10V6-K

0.22U_0402_10V6-K

1

CC63

2

1

CC64

CC65

CC66

2

2

2

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

@

1

1

180P_0402_50V8-J

180P_0402_50V8-J

CC81

CC82

2

2

1

1

CC67

2

22U_0603_6.3V6-M

1

CC68

CC69

2

2

1U_0402_6.3V7-K

1

180P_0402_50V8-J

CC70

2

1U_0402_6.3V7-K

A A

Title

Title

Security C lassification

Security C lassification

Security C lassification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE I NFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE I NFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE I NFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2

2015/10/5

2015/10/5

2015/10/5

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2014/12/05

2014/12/05

2014/12/05

Title

Switch

Switch

Switch

Size

Size

Size

Document Number Rev

Document Number Rev

Document Number Rev

D

D

D

JINN/DOOKU

JINN/DOOKU

JINN/DOOKU

Thursday, May 04, 2017

Thursday, May 04, 2017

Thursday, May 04, 2017

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

12 64

12 64

12 64

SDV

SDV

SDV

5

D D

4

3

2

1

UC1G

GND

N12

VSS_316

A3

VSS_1

A5

VSS_2

A7

VSS_3

A10

VSS_4

A12

VSS_5

A14

VSS_6

A16

VSS_7

A19

VSS_8

A21

VSS_9

A23

VSS_10

A26

VSS_11

A30

VSS_12

C3

VSS_13

C32

VSS_14

D16

VSS_15

D18

VSS_16

D20

VSS_17

E7

VSS_18

E8

VSS_19

E10

VSS_20

E11

VSS_21

E12

VSS_22

E13

VSS_23

E14

VSS_24

E15

VSS_25

E16

C C

B B

VSS_26

E18

VSS_27

E19

VSS_28

E20

VSS_29

E21

VSS_30

E22

VSS_31

E23

VSS_32

E25

VSS_33

E26

VSS_34

E27

VSS_35

F5

VSS_36

F28

VSS_37

G1

VSS_38

G5

VSS_39

G16

VSS_40

G19

VSS_41

G21

VSS_42

G23

VSS_43

G26

VSS_44

G28

VSS_45

G32

VSS_46

H5

VSS_47

H13

VSS_48

H18

VSS_49

H20

VSS_50

H22

VSS_51

H25

VSS_52

H28

VSS_53

K1

VSS_54

K5

VSS_55

K16

VSS_56

K19

VSS_57

K21

VSS_58

K22

VSS_59

K26

VSS_60

K28

VSS_61

VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98

VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123

FP5 REV 0.90
PART 7 OF 13

AMD-RAVEN-FP5_BGA1140

K32
L5
L13
L15
L18
L20
L25
L28
M1
M5
M12
M21
M23
M26
M28
M32
N4
N5
N8
N11
N13
N15
N17
N19
N22
N25
N28
P1
P5
P14
P16
P18
P20
P23
P26
P28
P32
R5
R11
R12
R13
R15
R17
R19
R22
R25
R28
R30
T1
T5
T14
T16
T18
T20
T23
T26
T28
U13
U15
U17
U19
V5

UC1K

GND/RSVD

AR5

VSS_248

AR7

VSS_249

AR12

VSS_250

AR14

VSS_251

AR16

VSS_252

AR19

VSS_253

AR21

VSS_254

AR26

VSS_255

AR28

VSS_256

AR32

VSS_257

AU5

VSS_258

AU8

VSS_259

AU11

VSS_260

AU13

VSS_261

AU15

VSS_262

AU18

VSS_263

AU20

VSS_264

AU22

VSS_265

AU25

VSS_266

AU28

VSS_267

AV1

VSS_268

AV5

VSS_269

AV7

VSS_270

AV10

VSS_271

AV12

VSS_272

AV14

VSS_273

AV16

VSS_274

AV19

VSS_275

AV21

VSS_276

AV23

VSS_277

AV26

VSS_278

AV28

VSS_279

AV32

VSS_280

AW5

VSS_281

AW28

VSS_282

AY6

VSS_283

AY7

VSS_284

AY8

VSS_285

AY10

VSS_286

AY11

VSS_287

AY12

VSS_288

AY13

VSS_289

AY14

VSS_290

AY15

VSS_291

AY16

VSS_292

AY18

VSS_293

AY19

VSS_294

AY20

VSS_295

AY21

VSS_296

AY22

VSS_297

AY23

VSS_298

AY25

VSS_299

AY26

VSS_300

AY27

VSS_301

BB1

VSS_302

BB20

VSS_303

BB32

VSS_304

BD3

VSS_305

BD7

VSS_306

BD10

VSS_307

BD12

VSS_308

BD14

VSS_309

VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315

RSVD_1
RSVD_5
RSVD_7
RSVD_8

RSVD_9
RSVD_10
RSVD_11
RSVD_12
RSVD_13
RSVD_22
RSVD_23
RSVD_30
RSVD_31
RSVD_37
RSVD_44
RSVD_49
RSVD_50
RSVD_57
RSVD_58
RSVD_59
RSVD_60
RSVD_69
RSVD_70
RSVD_71
RSVD_74
RSVD_75
RSVD_78
RSVD_79
RSVD_80
RSVD_81
RSVD_82
RSVD_83
RSVD_87
RSVD_88

RSVD_14
RSVD_84
RSVD_85
RSVD_86

FP5 REV 0.90

PART 11 OF 13

AMD-RAVEN-FP5_BGA1140

BD16
BD19
BD21
BD23
BD26
BD30

B20
G3
J20
K3
K6
K20
M3
M6
M13
P6
P22
T3
T6
T29
W6
W21
W22
Y21
Y27
AA3
AA6
AC29
AD3
AD6
AF3
AF6
AF30
AJ6
AJ24
AK23
AK27
AL3
AN29
AN31

M14
AL6
AL11
AN16

UC1H

GND

V8

VSS_124

V11

VSS_125

V12

VSS_126

V14

VSS_127

V16

VSS_128

V18

VSS_129

V20

VSS_130

V22

VSS_131

V25

VSS_132

W1

VSS_133

W5

VSS_134

W13

VSS_135

W15

VSS_136

W17

VSS_137

W19

VSS_138

W23

VSS_139

W26

VSS_140

Y5

VSS_141

Y11

VSS_142

Y12

VSS_143

Y14

VSS_144

Y16

VSS_145

Y18

VSS_146

Y20

VSS_147

AA1

VSS_148

AA5

VSS_149

AA13

VSS_150

AA15

VSS_151

AA17

VSS_152

AA19

VSS_153

AB14

VSS_154

AB16

VSS_155

AB18

VSS_156

AB20

VSS_157

AC5

VSS_158

AC8

VSS_159

AC11

VSS_160

AC12

VSS_161

AC13

VSS_162

AC15

VSS_163

AC17

VSS_164

AC19

VSS_165

AD1

VSS_166

AD5

VSS_167

AD14

VSS_168

AD16

VSS_169

AD18

VSS_170

AD20

VSS_171

AE5

VSS_172

AE11

VSS_173

AE12

VSS_174

AE13

VSS_175

AE15

VSS_176

AE17

VSS_177

AE19

VSS_178

AF1

VSS_179

AF5

VSS_180

AF14

VSS_181

AF16

VSS_182

AF18

VSS_183

AF20

VSS_184

AG5

VSS_185

VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247

FP5 REV 0.90
PART 8 OF 13

AMD-RAVEN-FP5_BGA1140

AG8
AG11
AG12
AG13
AG15
AG17
AG19
AH14
AH16
AH18
AH20
AJ1
AJ5
AJ13
AJ15
AJ17
AJ19
AK5
AK8
AK11
AK12
AK14
AK16
AK18
AK20
AK22
AK25
AL1
AL5
AL7
AL10
AL12
AL16
AL23
AL26
AM5
AM8
AM15
AM20
AM22
AM25
AM28
AN1
AN5
AN7
AN10
AN15
AN18
AN21
AN23
AN26
AN28
AN32
AP5
AP8
AP13
AP15
AP18
AP20
AP25
AP28
AR1

A A

Title

Title

Security C lassification

Security C lassification

Security C lassification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE I NFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE I NFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE I NFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2

2015/10/5

2015/10/5

2015/10/5

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2014/12/05

2014/12/05

2014/12/05

Title

Switch

Switch

Switch

Size

Size

Size

Document Number Rev

Document Number Rev

Document Number Rev

D

D

D

JINN/DOOKU

JINN/DOOKU

JINN/DOOKU

Thursday, May 04, 2017

Thursday, May 04, 2017

Thursday, May 04, 2017

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

13 64

13 64

13 64

SDV

SDV

SDV

5

4

3

2

1

+1.2V

12

RD1

1K_0402_1%

D D

+1.2V +1.2V

DDR_A_D5

C C

B B

DDR_A_CKE06

DDR_A_BG16
DDR_A_BG06

DDR_A_D1

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D7

DDR_A_D3

DDR_A_D10

DDR_A_D13

DDRA_MA_DM1

DDR_A_D15

DDR_A_D14

DDR_A_D21

DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D23

DDR_A_D19

DDR_A_D29

DDR_A_D25

DDRA_MA_DM3

DDR_A_D30

DDR_A_D26

DDR_A_BG1
DDR_A_BG0

DDR_A_MA12
DDR_A_MA9

DDR_A_MA8
DDR_A_MA6

12

RD2

1K_0402_1%

JDIMM1A

1

VSS_1

3

DQ5

5

VSS_3

7

DQ1

9

VSS_5

11

DQS0_C

13

DQS0_t

15

VSS_8

17

DQ7

19

VSS_10

21

DQ3

23

VSS_12

25

DQ13

27

VSS_14

29

DQ9

31

VSS_16

33

DM1_n/DBl_n

35

VSS_17

37

DQ15

39

VSS_19

41

DQ10

43

VSS_21

45

DQ21

47

VSS_23

49

DQ17

51

VSS_25

53

DQS2_c

55

DQS2_t

57

VSS_28

59

DQ23

61

VSS_30

63

DQ19

65

VSS_32

67

DQ29

69

VSS_34

71

DQ25

73

VSS_36

75

DM3_n/DBl3_n

77

VSS_37

79

DQ30

81

VSS_39

83

DQ26

85

VSS_41

87

CB5/NC

89

VSS_43

91

CB1/NC

93

VSS_45

95

DQS8_c

97

DQS8_t

99

VSS_48

101

CB2/NC

103

VSS_50

105

CB3/NC

107

VSS_52

109

CKE0

111

VDD_1

113

BG1

115

BG0

117

VDD_3

119

A12

121

A9

123

VDD_5

125

A8

127

A6

129

VDD_7

ARGOS_D4AR0-26005-1P40

ME@

M_VREF_CA_DIMMA

1

CD13

0.1U_0402_10V7-K

2

VSS_2

DQ4

VSS_4

DQ0

VSS_6

DM0_n/DBl0_n

VSS_7

DQ6

VSS_9

DQ2

VSS_11

DQ12

VSS_13

DQ8
VSS_15
DQS1_c

DQS1_t

VSS_18

DQ14

VSS_20

DQ11

VSS_22

DQ20

VSS_24

DQ16

VSS_26

DM2_n/DBl2_n

VSS_27

DQ22

VSS_29

DQ18

VSS_31

DQ28

VSS_33

DQ24
VSS_35
DQS3_c

DQS3_t

VSS_38

DQ31
VSS_40

DQ27
VSS_42
CB4/NC
VSS_44
CB0/NC
VSS_46

DM8_n/DBl_n/NC

VSS_47
CB6/NC
VSS_49
CB7/NC
VSS_51

RESET_n

CKE1

VDD_2
ACT_n

ALERT_n

VDD_4

A11

VDD_6

VDD_8

2

DDR_A_D4

4
6

DDR_A_D0

8
10

DDRA_MA_DM0

12
14

DDR_A_D6

16
18

DDR_A_D2

20
22

DDR_A_D12

24
26

DDR_A_D8

28
30

DDR_A_DQS#1

32

DDR_A_DQS1

34
36

DDR_A_D9

38
40

DDR_A_D11

42
44

DDR_A_D20

46
48

DDR_A_D16

50
52

DDRA_MA_DM2

54
56

DDR_A_D22

58
60

DDR_A_D18

62
64

DDR_A_D28

66
68

DDR_A_D24

70
72

DDR_A_DQS#3

74

DDR_A_DQS3

76
78

DDR_A_D31

80
82

DDR_A_D27

84
86
88
90
92
94
96
98
100
102
104
106
108

DDR_A_CKE1DDR_A_CKE0

110
112

DDR_A_ACT_N

114

DDR_A_ALERT_N

116
118

DDR_A_MA11

120

DDR_A_MA7

122

A7

124

DDR_A_MA5

126

A5
A4

DDR_A_MA4

128
130

+1.2V +2.5V

1

CD1

10U_0402_6.3V6-M

2

+1.2V

CD14

1U_0402_6.3V6-K

+1.2V

12

RD9

@

1K_0402_1%

1

CD30

EMC_NS@

0.1U_0402_10V7-K

2

1

2

CD15

1U_0402_6.3V6-K

DDRA_MA_DM[0..7] 6

DDR_A_D[0..63] 6

DDR_A_MA[0..13] 6

DDR_A_DQS#[0..7] 6

DDR_A_DQS[0..7] 6

+3VS +3VS +3VS

1

CD2

10U_0402_6.3V6-M

12

1 2

CD3

10U_0402_6.3V6-M

2

CD16

1U_0402_6.3V6-K

RD4

@

10K_0402_5%

R1
0_0402_5%

12

RD5

@

SA0_CHA_P SA1_CHA_P SA2_CHA_P

10K_0402_5%

RD7
0_0402_5%

1 2

SPD Address = 0H

DDR4_A_DRAMRST# 6
DDR_A_CKE1 6

DDR_A_ACT_N 6
DDR_A_ALERT_N 6

+3VS

1

CD4

10U_0402_6.3V6-M

2

CD17

1U_0402_6.3V6-K

12

1 2

RD10

12

0_0402_5%

CD18

1U_0402_6.3V6-K

RD6

@

10K_0402_5%

RD8
0_0402_5%

1

2

SA_CLK_DDR06

SA_CLK_DDR#06

DDR_A_PARITY6

DDR_A_BA16

DDR_A_CS0#6

DDR_A_WE#6

DDR_A_ODT06
DDR_A_CS1#6

DDR_A_ODT16

APU_SMB_CK07,9,15

CD5

10U_0402_6.3V6-M

CD19

1U_0402_6.3V6-K

1

CD28

0.1U_0402_10V7-K

2

1

CD6

10U_0402_6.3V6-M

2

DDR_A_MA3
DDR_A_MA1

SA_CLK_DDR0
SA_CLK_DDR#0

DDR_A_PARITY

DDR_A_BA1

DDR_A_CS0#

DDR_A_ODT0
DDR_A_CS1#

DDR_A_ODT1

DDR_A_D37

DDR_A_D33

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D38

DDR_A_D34

DDR_A_D44

DDR_A_D40

DDRA_MA_DM5

DDR_A_D46

DDR_A_D42

DDR_A_D52

DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D55

DDR_A_D51

DDR_A_D61

DDR_A_D60

DDRA_MA_DM7

DDR_A_D56

DDR_A_D57

APU_SMB_CK0

1

2

CD20

1U_0402_6.3V6-K

CD29

2.2U_0402_6.3V6-M

1

CD7

10U_0402_6.3V6-M

2

CD21

1U_0402_6.3V6-K

+1.2V+2.5V

1

CD8

10U_0402_6.3V6-M

2

JDIMM1B

131

A3

133

A1

135

VDD_9

137

CK0_t

139

CK0_c

141

VDD_11

143

Parity

145

BA1

147

VDD_13

149

CS0_n

151

A14/WE_n

153

VDD_15

155

ODT0

157

CS1_n

159

VDD_17

161

ODT1

163

VDD_19

165

C1/CS3_n/NC

167

VSS_53

169

DQ37

171

VSS_55

173

DQ33

175

VSS_57

177

DQS4_c

179

DQS4_t

181

VSS_60

183

DQ38

185

VSS_62

187

DQ34

189

VSS_64

191

DQ44

193

VSS_66

195

DQ40

197

VSS_68

199

DM5_n/DBl5_n

201

VSS_69

203

DQ46

205

VSS_71

207

DQ42

209

VSS_73

211

DQ52

213

VSS_75

215

DQ49

217

VSS_77

219

DQS6_c

221

DQS6_t

223

VSS_80

225

DQS5

227

VSS_82

229

DQ51

231

VSS_84

233

DQ61

235

VSS_86

237

DQ56

239

VSS_88

241

DM7_n/DBl7_n

243

VSS_89

245

DQ62

247

VSS_91

249

DQ58

251

VSS_93

253

SCL

255

VDDSPD

257

VPP_1

259

VPP_2

261

GND_1

ARGOS_D4AR0-26005-1P40

ME@

1

+

CD22

@

330U_D2_2VM_R9M

2

EVENT_n/NF

VDD_10

CK1_t/NF

CK1_c/NF

VDD_12

A10/AP

VDD_14

A16/RAS_n

VDD_16

A15/CAS_n

VDD_18

C0/CS2_n/NC

VREFCA

VSS_54

DQ36

VSS_56

DQ32

VSS_58

DM4_n/DBl4_n

VSS_59

DQ39

VSS_61

DQ35

VSS_63

DQ45

VSS_65

DQ41

VSS_67

DQS5_c

DQS5_t
VSS_70

DQ47

VSS_72

DQ43

VSS_74

DQ53

VSS_76

DQ48

VSS_78

DM6_n/DBl6_n

VSS_79

DQ54

VSS_81

DQ50

VSS_83

DQ60

VSS_85

DQ57

VSS_87

DQS7_c

DQS7_t
VSS_90

DQ63

VSS_92

DQ59

VSS_94

GND_2

132

A2

134
136
138
140
142
144

A0

146
148
150

BA0

152
154
156
158

A13

160
162
164
166

SA2

168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
210
212
214
216
218
220
222
224
226
228
230
232
234
236
238
240
242
244
246
248
250
252
254

SDA

256

SA0

258

VTT

260

SA1

262

1

CD9

10U_0402_6.3V6-M

2

+0.6VS

1

CD23

10U_0402_6.3V6-M

2

+1.2V +0.6VS

1

CD10

10U_0402_6.3V6-M

2

1

CD24

10U_0402_6.3V6-M

2

DDR_A_MA2

SA_CLK_DDR1
SA_CLK_DDR#1

DDR_A_MA0

DDR_A_MA10

DDR_A_BA0
DDR_A_RAS#DDR_A_WE#

DDR_A_CAS#
DDR_A_MA13

M_VREF_CA_DIMMA
SA2_CHA_P

DDR_A_D36

DDR_A_D32

DDRA_MA_DM4

DDR_A_D39

DDR_A_D35

DDR_A_D45

DDR_A_D41

DDR_A_DQS#5
DDR_A_DQS5

DDR_A_D47

DDR_A_D43

DDR_A_D53

DDR_A_D48

DDRA_MA_DM6

DDR_A_D54

DDR_A_D50

DDR_A_D63

DDR_A_D59

DDR_A_DQS#7
DDR_A_DQS7

DDR_A_D62

DDR_A_D58

APU_SMB_DA0
SA0_CHA_P

SA1_CHA_P

CD11

1U_0402_6.3V6-K

CD25

1U_0402_6.3V6-K

+1.2V

12

RD3

1K_0402_1%

DDR_A_EVENT# 6

SA_CLK_DDR1 6
SA_CLK_DDR#1 6

DDR_A_BA0 6
DDR_A_RAS# 6

DDR_A_CAS# 6

1

CD26

1000P_0402_50V7-K

2

APU_SMB_DA0 7,9,15

CD12

1U_0402_6.3V6-K

1

CD27

0.1U_0402_10V7-K

2

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY L C FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY L C FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY L C FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2015/10/5

2015/10/5

2015/10/5

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/12/31

2016/12/31

2016/12/31

Title

DDR4 CH-A PRIMARY

DDR4 CH-A PRIMARY

DDR4 CH-A PRIMARY

Size

Document Number Re v

Size

Document Number Re v

Size

Document Number Re v

JINN/DOOKU

JINN/DOOKU

JINN/DOOKU

Thursday, May 04, 2017

Thursday, May 04, 2017

Thursday, May 04, 2017

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

14 64

14 64

14 64

1

SDVCustom

SDVCustom

SDVCustom

5

4

3

2

1

+1.2V

12

RD11

1K_0402_1%

12

JDIMM2A

1

VSS_1

3

DQ5

5

VSS_3

7

DQ1

9

VSS_5

11

DQS0_C

13

DQS0_t

15

VSS_8

17

DQ7

19

VSS_10

21

DQ3

23

VSS_12

25

DQ13

27

VSS_14

29

DQ9

31

VSS_16

33

DM1_n/DBl_n

35

VSS_17

37

DQ15

39

VSS_19

41

DQ10

43

VSS_21

45

DQ21

47

VSS_23

49

DQ17

51

VSS_25

53

DQS2_c

55

DQS2_t

57

VSS_28

59

DQ23

61

VSS_30

63

DQ19

65

VSS_32

67

DQ29

69

VSS_34

71

DQ25

73

VSS_36

75

DM3_n/DBl3_n

77

VSS_37

79

DQ30

81

VSS_39

83

DQ26

85

VSS_41

87

CB5/NC

89

VSS_43

91

CB1/NC

93

VSS_45

95

DQS8_c

97

DQS8_t

99

VSS_48

101

CB2/NC

103

VSS_50

105

CB3/NC

107

VSS_52

109

CKE0

111

VDD_1

113

BG1

115

BG0

117

VDD_3

119

A12

121

A9

123

VDD_5

125

A8

127

A6

129

VDD_7

ARGOS_D4AR0-26005-1P40

ME@

M_VREF_CA_DIMMB

RD12

1K_0402_1%

DM8_n/DBl_n/NC

1

CD42

0.1U_0402_10V7-K

2

Layout Node:

Place Close DIMMs

2

VSS_2

4

DQ4

6

VSS_4

8

DQ0

10

VSS_6

12

DM0_n/DBl0_n

14

VSS_7

16

DQ6

18

VSS_9

20

DQ2

22

VSS_11

24

DQ12

26

VSS_13

28

DQ8

30

VSS_15

32

DQS1_c

34

DQS1_t

36

VSS_18

38

DQ14

40

VSS_20

42

DQ11

44

VSS_22

46

DQ20

48

VSS_24

50

DQ16

52

VSS_26

54

DM2_n/DBl2_n

56

VSS_27

58

DQ22

60

VSS_29

62

DQ18

64

VSS_31

66

DQ28

68

VSS_33

70

DQ24

72

VSS_35

74

DQS3_c

76

DQS3_t

78

VSS_38

80

DQ31

82

VSS_40

84

DQ27

86

VSS_42

88

CB4/NC

90

VSS_44

92

CB0/NC

94

VSS_46

96
98

VSS_47

100

CB6/NC

102

VSS_49

104

CB7/NC

106

VSS_51

108

RESET_n

110

CKE1

112

VDD_2

114

ACT_n

116

ALERT_n

118

VDD_4

120

A11

122

A7

124

VDD_6

126

A5

128

A4

130

VDD_8

DDR_B_D4

DDR_B_D0

DDRA_MB_DM0

DDR_B_D6

DDR_B_D2

DDR_B_D12

DDR_B_D8

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D14

DDR_B_D11

DDR_B_D20

DDR_B_D16

DDRA_MB_DM2

DDR_B_D22 DDR_B_D34

DDR_B_D18

DDR_B_D28

DDR_B_D24

DDR_B_DQS#3
DDR_B_DQS3

DDR_B_D31

DDR_B_D27

DDR4_B_DRAMRST#
DDR_B_CKE1

DDR_B_ACT_N
DDR_B_ALERT_N

DDR_B_MA11
DDR_B_MA7

DDR_B_MA5
DDR_B_MA4

D D

+1.2V +1.2V

DDR_B_D5

C C

B B

DDR_B_CKE06

DDR_B_BG16
DDR_B_BG06

DDR_B_D1

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D7

DDR_B_D3

DDR_B_D13

DDR_B_D9

DDRA_MB_DM1

DDR_B_D15

DDR_B_D10

DDR_B_D21

DDR_B_D17

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D23

DDR_B_D19

DDR_B_D29

DDR_B_D25

DDRA_MB_DM3

DDR_B_D30

DDR_B_D26

DDR_B_CKE0

DDR_B_BG1
DDR_B_BG0

DDR_B_MA12
DDR_B_MA9

DDR_B_MA8
DDR_B_MA6

+0.6VS

1

CD39

10U_0402_6.3V6-M

2

+2.5V

1

CD43

10U_0402_6.3V6-M

2

DDRA_MB_DM[0..7] 6

+1.2V

12

RD20

@

1K_0402_1%

1

CD59

EMC_NS@

2

0.1U_0402_10V7-K

1

CD40

10U_0402_6.3V6-M

2

1

CD44

10U_0402_6.3V6-M

2

DDR_B_D[0..63] 6

DDR_B_MA[0..13] 6

DDR_B_DQS#[0..7] 6

DDR_B_DQS[0..7] 6

+3VS

12

1 2

+3VS +3VS

RD14

@

10K_0402_5%

SA0_CHB_P SA1_CHB_P SA2_CHB_P

RD17
0_0402_5%

SPD Address = 2H

DDR4_B_DRAMRST# 6
DDR_B_CKE1 6

DDR_B_ACT_N 6
DDR_B_ALERT_N 6

+3VS

CD41

1U_0402_6.3V6-K

CD45

1U_0402_6.3V6-K

12

RD15

10K_0402_5%

RD18
0_0402_5%

1 2

@

RD21

0_0402_5%

12

CD46

1U_0402_6.3V6-K

SB_CLK_DDR06

SB_CLK_DDR#06

DDR_B_PARITY6

DDR_B_BA16

DDR_B_CS0#6

DDR_B_WE#6

DDR_B_ODT06
DDR_B_CS1#6

DDR_B_ODT16

12

RD16

@

10K_0402_5%

RD19
0_0402_5%

1 2

APU_SMB_CK07,9,14

+1.2V

CD32

10U_0402_6.3V6-M

1

CD61

2.2U_0402_6.3V6-M

2

1

2

CD49

1U_0402_6.3V6-K

1

CD33

10U_0402_6.3V6-M

+1.2V+2.5V +1.2V +0.6VS

2

CD50

1U_0402_6.3V6-K

JDIMM2B

131

A3

133

A1

135

VDD_9

137

CK0_t

139

CK0_c

141

VDD_11

143

Parity

145

BA1

147

VDD_13

149

CS0_n

151

A14/WE_n

153

VDD_15

155

ODT0

157

CS1_n

159

VDD_17

161

ODT1

163

VDD_19

165

C1/CS3_n/NC

167

VSS_53

169

DQ37

171

VSS_55

173

DQ33

175

VSS_57

177

DQS4_c

179

DQS4_t

181

VSS_60

183

DQ38

185

VSS_62

187

DQ34

189

VSS_64

191

DQ44

193

VSS_66

195

DQ40

197

VSS_68

199

DM5_n/DBl5_n

201

VSS_69

203

DQ46

205

VSS_71

207

DQ42

209

VSS_73

211

DQ52

213

VSS_75

215

DQ49

217

VSS_77

219

DQS6_c

221

DQS6_t

223

VSS_80

225

DQS5

227

VSS_82

229

DQ51

231

VSS_84

233

DQ61

235

VSS_86

237

DQ56

239

VSS_88

241

DM7_n/DBl7_n

243

VSS_89

245

DQ62

247

VSS_91

249

DQ58

251

VSS_93

253

SCL

255

VDDSPD

257

VPP_1

259

VPP_2

261

GND_1

ARGOS_D4AR0-26005-1P40

ME@

CD34

10U_0402_6.3V6-M

EVENT_n/NF

A16/RAS_n

A15/CAS_n

C0/CS2_n/NC

DM4_n/DBl4_n

DM6_n/DBl6_n

1

2

+1.2V

1

CD31

10U_0402_6.3V6-M

2

CD47

CD48

1U_0402_6.3V6-K

1U_0402_6.3V6-K

DDR_B_MA3
DDR_B_MA1

SB_CLK_DDR0
SB_CLK_DDR#0

DDR_B_PARITY

DDR_B_BA1

DDR_B_CS0#
DDR_B_WE#

DDR_B_ODT0
DDR_B_CS1#

DDR_B_ODT1

DDR_B_D37

DDR_B_D33

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D38

DDR_B_D44

DDR_B_D40

DDRA_MB_DM5

DDR_B_D46

DDR_B_D42

DDR_B_D52

DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D55

DDR_B_D51

DDR_B_D61

DDR_B_D56

DDRA_MB_DM7

DDR_B_D62

DDR_B_D58 DDR_B_D59

APU_SMB_CK0

1

CD60

0.1U_0402_10V7-K

2

CD51

1U_0402_6.3V6-K

A2

VDD_10

CK1_t/NF

CK1_c/NF

VDD_12

A0

A10/AP

VDD_14

BA0

VDD_16

A13

VDD_18

VREFCA

SA2

VSS_54

DQ36

VSS_56

DQ32

VSS_58

VSS_59

DQ39

VSS_61

DQ35

VSS_63

DQ45

VSS_65

DQ41
VSS_67
DQS5_c

DQS5_t

VSS_70

DQ47
VSS_72

DQ43
VSS_74

DQ53
VSS_76

DQ48
VSS_78

VSS_79

DQ54
VSS_81

DQ50
VSS_83

DQ60
VSS_85

DQ57
VSS_87
DQS7_c

DQS7_t

VSS_90

DQ63
VSS_92

DQ59
VSS_94

SDA

SA0
VTT
SA1

GND_2

1

CD35

10U_0402_6.3V6-M

2

132
134
136
138
140
142
144

146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
210
212
214
216
218
220
222
224
226
228
230
232
234
236
238
240
242
244
246
248
250
252
254
256
258
260

262

1

2

CD52

1U_0402_6.3V6-K

DDR_B_MA2

SB_CLK_DDR1
SB_CLK_DDR#1

DDR_B_MA0

DDR_B_MA10

DDR_B_BA0
DDR_B_RAS#

DDR_B_CAS#
DDR_B_MA13

M_VREF_CA_DIMMB
SA2_CHB_P

DDR_B_D36

DDR_B_D32

DDRA_MB_DM4

DDR_B_D39

DDR_B_D35

DDR_B_D45

DDR_B_D41

DDR_B_DQS#5
DDR_B_DQS5

DDR_B_D47

DDR_B_D43

DDR_B_D53

DDR_B_D48

DDRA_MB_DM6

DDR_B_D54

DDR_B_D50

DDR_B_D60

DDR_B_D57

DDR_B_DQS#7
DDR_B_DQS7

DDR_B_D63

APU_SMB_DA0
SA0_CHB_P

SA1_CHB_P

CD36

10U_0402_6.3V6-M

CD53

1U_0402_6.3V6-K

1

CD37

10U_0402_6.3V6-M

2

CD54

CD63 100U_1206_6.3V6M@

1U_0402_6.3V6-K

+1.2V

12

RD13

1K_0402_1%

DDR_B_EVENT# 6

SB_CLK_DDR1 6
SB_CLK_DDR#1 6

DDR_B_BA0 6
DDR_B_RAS# 6

DDR_B_CAS# 6

1

1

CD56

1000P_0402_50V7- K

2

2

@

APU_SMB_DA0 7,9,14

1

CD38

10U_0402_6.3V6-M

2

1

2

CD57

2.2U_0402_6.3V6-M

CD62

100U_1206_6.3V6M

1

CD58

0.1U_0402_10V7-K

2

1

@

2

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY L C FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY L C FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY L C FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2015/10/5

2015/10/5

2015/10/5

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/12/31

2016/12/31

2016/12/31

Title

DDR4 CH-B PRIMARY

DDR4 CH-B PRIMARY

DDR4 CH-B PRIMARY

Size

Document Number Re v

Size

Document Number Re v

Size

Document Number Re v

Custom

Custom

Custom

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

JINN/DOOKU

JINN/DOOKU

JINN/DOOKU

Thursday, May 04, 2017

Thursday, May 04, 2017

Thursday, May 04, 2017

15 64

15 64

15 64

1

SDV

SDV

SDV

5

4

3

2

1

Power-Up/Down Sequence

"Topaz" has the following requirements with regards to power-supply sequencing to

D D

avoid damaging the ASIC:

All the ASIC supplies must reach their respective nominal voltages within 20 ms
of the start of the ramp-up sequence, though a shorter ramp-up duration is
preferred. The maximum slew rate on all rails is 50 mV/µ s.
It is recommended that the 3.3-V rail ramp up first.
The 3.3-V, 1.8-V, and 0.95-V rails must reach their ready state at least 10 µ s
before VDDC, VDDCI, and VMEMIO start to ramp up.
The power rails that are shared with other components on the system should be
gated for the dGPU so that when the dGPU is powered down (for example
AMD PowerXpress idle state), all the power rails are removed from the dGPU.
The gate circuits must meet the slew rate requirement (such as ≤ 50 mV/µ s).
For power down, reversing the ramp-up sequence is recommended.

VRAM ID config

Memory Type

VRAM ID PU resistor PD resistor

PS_3[3: 1]

100

111

RV63 RV7 0

4.53K 4.99K

NC4.75K

110

10K3.4K

0 ~ 20ms

VDDR3(+3VGS)

C C

VDD_CT(+1.8VGS)

0 ~ 20ms

8Gb GDDR5

512M x 32

PCIE_VDDC(+0.95VGS)

Hynix

H5GC8H24MJR-R0C 6.0Gbps@1.35V

Micron

MT51J256M32HF-70:A 6.0Gbps@1.35V

Samsung

K4G80325FB-HC28 6.0Gbps@1.35V

000

010

001

NC 4.75K

4.53K 2K

8.45K 2K

10us min.

VDDR1(+1.35VGS)

VDDC/VDDCI(+VGA_CORE)

PERSTb(GPU_RST#)

100ms min.

100us min.

3HynixH5GC8H24MJR-R0C

SamsungK4G80325FB-HC28
MicronMT51J256M32HF-70:A

REFCLK(CLK_PCIE_VGA)

B B

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

3

2017/01/01

2017/01/01

2017/01/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2018/06/31

2018/06/31

2018/06/31

Title

VGA Notes List

VGA Notes List

VGA Notes List

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Thursday, May 04, 2017

Thursday, May 04, 2017

Thursday, May 04, 2017

JINN/DOOKU

JINN/DOOKU

JINN/DOOKU

1

16 64

16 64

16 64

SDV

SDV

SDV

5

4

UV1A

3

2

1

PCIE_CTX_GRX_P0

PCIE_CTX_GRX_P05

D D

C C

B B

PCIE_CTX_GRX_N05

PCIE_CTX_GRX_P15
PCIE_CTX_GRX_N15

PCIE_CTX_GRX_P25
PCIE_CTX_GRX_N25

PCIE_CTX_GRX_P35
PCIE_CTX_GRX_N35

PCIE_CTX_GRX_N0

PCIE_CTX_GRX_P1
PCIE_CTX_GRX_N1

PCIE_CTX_GRX_P2
PCIE_CTX_GRX_N2

PCIE_CTX_GRX_P3
PCIE_CTX_GRX_N3

0.22U_0402_16V6-K

0.22U_0402_16V6-K

0.22U_0402_16V6-K

0.22U_0402_16V6-K

0.22U_0402_16V6-K

0.22U_0402_16V6-K

0.22U_0402_16V6-K

0.22U_0402_16V6-K

12
12

12

12

12
12

12
12

PX@
PX@

PX@
PX@

PX@
PX@

PX@
PX@

CG1
CG3

CG5
CG7

CG9
CG11

CG13
CG15

PCIE_CTX_C_GRX_P0
PCIE_CTX_C_GRX_N0

PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_N1

PCIE_CTX_C_GRX_P2
PCIE_CTX_C_GRX_N2

PCIE_CTX_C_GRX_P3
PCIE_CTX_C_GRX_N3

AF30
AE31

AE29
AD28

AD30
AC31

AC29
AB28

AB30
AA31

AA29

Y28

Y30

W31

W29

V28

V30
U31

U29
T28

T30
R31

R29
P28

P30
N31

N29
M28

M30

K30

L31

L29

PCIE_RX0P
PCIE_RX0N

PCIE_RX1P
PCIE_RX1N

PCIE_RX2P
PCIE_RX2N

PCIE_RX3P
PCIE_RX3N

PCIE_RX4P
PCIE_RX4N

PCIE_RX5P
PCIE_RX5N

PCIE_RX6P
PCIE_RX6N

PCIE_RX7P
PCIE_RX7N

NC#V30
NC#U31

NC#U29
NC#T28

NC#T30
NC#R31

NC#R29
NC#P28

NC#P30
NC#N31

NC#N29
NC#M28

NC#M30
NC#L31

NC#L29
NC#K30

PCIE_CRX_C_GTX_P0

NC#W24
NC#W23

NC#V27

NC#U26

NC#U24
NC#U23

NC#T26
NC#T27

NC#T24
NC#T23

NC#P27
NC#P26

NC#P24
NC#P23

NC#M27
NC#N26

AH30

PCIE_CRX_C_GTX_N0

AG31

PCIE_CRX_C_GTX_P1

AG29

PCIE_CRX_C_GTX_N1

AF28

PCIE_CRX_C_GTX_P2

AF27

PCIE_CRX_C_GTX_N2

AF26

PCIE_CRX_C_GTX_P3

AD27

PCIE_CRX_C_GTX_N3

AD26

AC25
AB25

Y23
Y24

AB27
AB26

Y27
Y26

W24
W23

V27
U26

U24
U23

T26
T27

T24
T23

P27
P26

P24
P23

M27
N26

PCIE_TX0P

PCIE_TX0N

PCIE_TX1P

PCIE_TX1N

PCIE_TX2P

PCIE_TX2N

PCIE_TX3P

PCIE_TX3N

PCIE_TX4P

PCIE_TX4N

PCIE_TX5P

PCIE_TX5N

PCIE_TX6P

PCIE_TX6N

PCIE_TX7P

PCIE_TX7N

PCI EXPRESS INTERFACE

0.22U_0402_16V6-K

0.22U_0402_16V6-K

0.22U_0402_16V6-K

0.22U_0402_16V6-K

0.22U_0402_16V6-K

0.22U_0402_16V6-K

0.22U_0402_16V6-K

0.22U_0402_16V6-K

with BOM strcture control, CV1--CV8 change to 0.22uf for CZ

change the GPU PN to AMD(EXO-S3 PRO), symbol check ok

11/4 change to PC sample SA000074V10

PX@

12

PX@

12

PX@

12

PX@

12

PX@

12

PX@

12

PX@

12

PX@

12

PCIE_CRX_GTX_P0

CG2

PCIE_CRX_GTX_N0

CG4

PCIE_CRX_GTX_P1

CG6

PCIE_CRX_GTX_N1

CG8

PCIE_CRX_GTX_P2

CG10

PCIE_CRX_GTX_N2

CG12

PCIE_CRX_GTX_P3

CG14

PCIE_CRX_GTX_N3

CG16

PCIE_CRX_GTX_P0 5
PCIE_CRX_GTX_N0 5

PCIE_CRX_GTX_P1 5
PCIE_CRX_GTX_N1 5

PCIE_CRX_GTX_P2 5

PCIE_CRX_GTX_N2 5

PCIE_CRX_GTX_P3 5
PCIE_CRX_GTX_N3 5

CLK_PCIE_GPU9
CLK_PCIE_GPU#9

GPU_RST#18

1 2

RV4 0_0402_5%@

+3VGS

A A

DGPU_HOLD_RST#9

PLT_RST#_R_G7

5

5

1

IN1

VCC

2

OUT

IN2

GND

MC74VHC1G08DFT2G_SC70-5

3

PX@

UV2

GPU_RST#

4

CLK_PCIE_GPU
CLK_PCIE_GPU#

PX@

1 2

GPU_RST#

4

RV21K_0402_1%

12

RV5

100K_0402_5%

PX@

AK30
AK32

N10

AL27

CLOCK

PCIE_REFCLKP
PCIE_REFCLKN

CALIBRATION

PCIE_CALR_TX

TEST_PG

PERSTB

@

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED B Y LC FU TURE CENTER NE ITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED B Y LC FU TURE CENTER NE ITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED B Y LC FU TURE CENTER NE ITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTE N CONSENT OF LC F UTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTE N CONSENT OF LC F UTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTE N CONSENT OF LC F UTURE CENTER.

PCIE_CALR_RX

Y22

AA22

2017/01/01

2017/01/01

2017/01/01

3

PX@

1 2

PX@

1 2

Deciphered Date

Deciphered Date

Deciphered Date

1.69K_0402_1%

RV31K_0402_1%

VR_VGA_PWRGD60

RV1

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

+0.95VGS

GPU_RST#

VR_VGA_PWRGD

VR_VGA_PWRGD

DV1

2

3

LBAT54AWT1G SOT323

PX@

1 2

RV6 0_0402_5%PX@

1

VGA_PWROK

2016/09/29: Add RV1041 to report GPU PWRGD signal to CPU

Titl e

Titl e

Titl e

2018/06/31

2018/06/31

2018/06/31

2

ATI_R17M-M1-70_PCIE

ATI_R17M-M1-70_PCIE

ATI_R17M-M1-70_PCIE

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

Custom

Custom

Custom

Thursday, May 04, 2017

Thursday, May 04, 2017

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

Thursday, May 04, 2017

JINN/DOOKU

JINN/DOOKU

JINN/DOOKU

VGA_PWROK 60

DGPU_PWROK 9

17 64

17 64

17 64

1

SDV

SDV

SDV

5

D D

+3VGS

@

GPU_GPIO5

1 2

@

1 2

@

1 2

@

1 2

@

1 2

@

1 2

@

1 2

@

1 2

@

1 2

@

1 2

@

1 2

@

1 2

@

1 2

@

1 2

@

1 2

RV7

GPU_GPIO0

RV8

GPU_GPIO8

RV9

GPU_GPIO9

RV10

GPU_GPIO10

RV11

GPU_GPIO11

RV12

GPU_GPIO12

RV13

GPU_GPIO13

RV14

GPU_GPIO22

RV15

GPU_VID1

RV16

GPU_GPIO21

RV17

GPU_VID5

RV20

GPU_VID2

RV21

GPU_GPIO17

RV23

RV245.11K_0402_1%

TESTEN

+1.8VGS

PX@

RV18 10K_0402_5%

1 2

PX@

RV22

1 2

10K_0402_5%

10K_0402_5%
10K_0402_5%

10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%

10K_0402_5%

Reserve

+VGA_CORE

RB751V-40_SOD323-2

1 2

GPU_VR_HOT#

+VGA_CORE

GPU_SVD

GPU_SVC

GPU_VR_HOT#

10K_0402_5%
10K_0402_5%

+1.8VGS

(1.8V@20mA TSVDD)

enable MLPS

DV2

1 2

RV26

0_0402_5%

+VGA_CORE

10K_0402_5% PX@

1 2

RV46

1 2

1K_0402_5%

+VGA_CORE

1 2

LV1

BLM15PD121SN1D_2P

VGA_AC_DC#42

C C

+3VGS

layout these component or test point on button layer

10K_0402_5%
10K_0402_5%
10K_0402_5%

10K_0402_5%

1 2

2016/09/02: Pull-down GPU_CLKREQ# at GPU side

1 2

CV5

8P_0402_50V8-C

PX@

YV1

PX@

B B

1 2

CV6

8P_0402_50V8-C

PX@

no symbol for 8pf cap, PLM has PN,change the PN

+3VGS

Need AMD check

@
@
@

@

PX@

2

GND1

OSC23GND2

10K_0402_5%

CLKREQ_PCIE7_VGA#9

RV44

12

RV45

12

RV47

12

RV48

12

RV51470_0402_5%

1

OSC1

4

GPU_VR_HOT#60

JTAG_TRSTB
JTAG_TDI
JTAG_TMS

JTAG_TCK

CLKREQ_PCIE7_VGA#

XTALIN

12

RV53
1M_0402_5%

PX@

27MHZ_10PF_7V27000050

XTALOUT

@

12

RV60

12

RV63

10K_0402_5%

@

TV2

TV3

TV4PAD@

1 2

@

1 2
1 2

1 2
1 2

1 2

RV400_0402_5% @

PX@

1

TV9PAD@

4.7K_0402_5%

1

TV10PAD@

PX@
PX@

TV11PAD@
TV12PAD@

1U_0402_6.3V6-K

4

BP_0
VGA_VDDCI_SEN

1

BP_1

PAD@

PLL_ANALOG_IN

1

PAD@

GPU_GPIO0

VGA_SMB_DATA
VGA_SMB_CLK
GPU_GPIO5

PX@

GPU_VID5

GPU_GPIO8

PX@

GPU_GPIO9
GPU_GPIO10
GPU_GPIO11
GPU_GPIO12

1

GPU_GPIO13

GPU_VID3

RV300_0402_5% @

GPU_GPIO16

RV3210K_0402_5%

GPU_GPIO17

RV310_0402_5% @

GPIO_19_CTF

RV35

GPU_VID4
GPU_GPIO21

RV360_0402_5% @

GPU_GPIO22
GPU_VID2
GPU_VID1

RV380_0402_5% @

CLKREQ_PCIE7_VGA#_R

JTAG_TRSTB
JTAG_TDI
JTAG_TCK
JTAG_TMS

PAD@

JTAG_TDO

1

TV7

TESTEN

PX_EN

1 2

NC_DBG_VREFG

XTALIN
XTALOUT

XO_IN

RV55

12

XO_IN2

RV57

12

GPU_DPLUS

1

GPU_DMINUS

1

GPIO_28_FDO

+TSVDD

PX@

2

CV7

PX@

1

NC#AF2
NC#AF4

NC#AG3
NC#AG5

NC#AH3
NC#AH1

NC#AK3
NC#AK1

NC#AK5

NC#AM3

NC#AK6

NC#AM5

NC#AJ7
NC#AH6

NC#AK8
NC#AL7

NC#V4
NC#U5

NC#W3
NC#V2

NC#Y4
NC#W5

NC#AA3

NC#Y2

NC#J8

NC_R

NC_AVSSN#AK26

NC_G

NC_AVSSN#AJ25

NC_AVSSN#AG25

NC_HSYNC
NC_VSYNC

NC_RSET

NC_AVDD

NC_AVSSQ

NC_VDD1DI
NC_VSS1DI

CEC_1

NC_SVI2#AK12
NC_SVI2#AL11
NC_SVI2#AJ11

NC_GENLK_CLK

NC_SWAPLOCKA
NC_SWAPLOCKB

NC_DDC1CLK

NC_DDC1DATA

NC_AUX1P
NC_AUX1N

NC_DDC2CLK

NC_DDC2DATA

NC_AUX2P
NC_AUX2N

NC#AD20
NC#AC20

NC#AE16
NC#AD16

NC_DDCVGACLK

3

AF2
AF4

AG3
AG5

AH3
AH1

AK3
AK1

AK5
AM3

AK6
AM5

AJ7
AH6

AK8
AL7

V4
U5

VGA_VSSI_SEN

W3
V2

Y4
W5

AA3
Y2

J8

AM26
AK26

AL25
AJ25

AH24

NC_B

AG25

AH26
AJ27

AD22

AG24
AE22

AE23
AD23

AM12

AK12
AL11
AJ11

AL13
AJ13

AG13
AH12

AC19

PS_0

AD19

PS_1

AE17

PS_2

AE20

PS_3

AE19

TS_A

AE6
AE5

AD2
AD4

AC11
AC13

AD13
AD11

AD20
AC20

AE16
AD16

AC1
AC3

1

TV1 PAD @

PLL_ANALOG_OUT

RV19

1 2

16.2K_0402_1%

1 2

PX@

1

RV37 0_0402_5%PX@
RV39 0_0402_5%PX@
RV41 0_0402_5%PX@

1
1

RV67 0_0402_5%@

1 2

4.7K_0402_5%

TV5
PAD @

1 2
1 2
1 2

TV6 PAD@
TV8 PAD@

+VGA_CORE

1 2

RV56 0_0402_5%PX@

1 2

RV58 0_0402_5%PX@

@

PX@

RV2510K_0402_5%

GPU_SVD 60
GPU_SVT 60
GPU_SVC 60

12

RV54

100_0402_5%

PX@

12

RV59

100_0402_5%

PX@

+VGA_CORE

12

WRST# 42

For layout reserves

DIECRACKMON

Debug port for the die.

WAKEB is used as an input for the PCIe? Optimized Buffer Flush/Fill (OBFF)
feature.

RV27

WAKEB

CEC_1

GPU_SVD_R
GPU_SVT_R
GPU_SVC_R

GENLK_CLK
GENLK_VSYNC

PS_0

PS_1

PS_2

PS_3

VGA_VSS_SEN_R
VGA_CORE_SEN_R

Need AMD check

UV1B

N9

DBG_DATA16

L9

DBG_DATA15

AE9

DBG_DATA14

Y11

DBG_DATA13

AE8

DBG_DATA12

AD9

DBG_DATA11

AC10

DBG_DATA10

AD7

DBG_DATA9

AC8

DBG_DATA8

AC7

DBG_DATA7

AB9

DBG_DATA6

AB8

DBG_DATA5

AB7

DBG_DATA4

AB4

DBG_DATA3

AB2

DBG_DATA2

Y8

DBG_DATA1

Y7

DBG_DATA0

W6

NC#W6

V6

NC#V6

AC6

NC#AC6

AC5

NC#AC5

AA5

NC#AA5

AA6

NC#AA6

U1

NC#U1

W1

NC#W1

U3

NC#U3

Y6

NC#Y6

AA1

NC#AA1

I2C

R1

SCL

R3

SDA

U6

GPIO_0

U10

NC_GPIO_1

T10

NC_GPIO_2

U8

SMBDATA

U7

SMBCLK

T9

GPIO_5_AC_BATT

T8

GPIO_6

T7

NC_GPIO_7

P10

GPIO_8_ROMSO

P4

GPIO_9_ROMSI

P2

GPIO_10_ROMSCK

N6

NC_GPIO_11

N5

NC_GPIO_12

N3

NC_GPIO_13

Y9

NC_GPIO_14

N1

GPIO_15_PWRCNTL_0

M4

GPIO_16

R6

GPIO_17_THERMAL_INT

W10

NC_GPIO_18

M2

GPIO_19_CTF

P8

GPIO_20_PWRCNTL_1

P7

GPIO_21

N8

GPIO_22_ROMCSB

AK10

GPIO_29

AM10

GPIO_30

N7

CLKREQB

L6

JTAG_TRSTB

L5

JTAG_TDI

L3

JTAG_TCK

L1

JTAG_TMS

K4

JTAG_TDO

K7

TESTEN

AF24

NC#AF24

AB13

NC_GENERICA

W8

NC_GENERICB

W9

NC_GENERICC

W7

NC_GENERICD

AD10

NC_GENERICE_HPD4

AJ9

NC#AJ9

AL9

DBG_CNTL0

AC14

NC_HPD1

AB16

@

PX_EN

RV52

AC16

NC_DBG_VREFG

PLL/CLOCK

AM28

XTALIN

AK28

XTALOUT

AC22

XO_IN

AB22

XO_IN2

SEYMOUR/FutureASIC

T4

DPLUS

T2

DMINUS

R5

GPIO28_FDO

AD17

TSVDD

AC17

TSVSS

@

DVO

GENERAL PURPOSE I/O

THERMAL

DPA

DPB

DPC

DAC1

FutureASIC/SEYMOUR/ PARK

NC_GENLK_VSYNC

DDC/AUX

NC_DDCVGADATA

2

CONFIGURATION STRAPS

ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE
GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET

MLPS Bit Description

Strap Name

PS_0[1]

ROM_CONFI G[0]
PS_0[2]
PS_0[3]

PS_0[4] N /A Reserved for internal use only. Must be 1 at reset. 1

AUD_PORT_CON N_
PINSTRAP[0 ]

PS_0[5]

PS_1[1]

STRAP_BIF_GEN3_EN_ A

PS_1[2]

STRAP_BIF_CLK_PM_EN

PS_1[3]

STRAP_TX_CFG_DRV_
FULL_SWIN G

PS_1[4]

STRAP_TX_ DEEMPH_ EN

PS_1[5]

PS_2[1]

PS_2[2]

PS_2[3]

STRAP_BIOS_ROM_EN

PS_2[4]

STRAP_BIF_VGA_DIS

PS_2[5] N /A Rese rved 1

PS_3[1]

BOARD_CON FIG[0]

PS_3[2]

BOARD_CON FIG[1]

PS_3[3]

BOARD_CON FIG[2]

AUD_PORT_CON N_
PINSTRAP[1 ]

PS_3[4]

AUD_PORT_CON N_

PS_3[5]

PINSTRAP[2 ]

VGA_VSS_SEN 60
VGA_CORE_SEN 60

Define the R OM type when STRAP_BIOS_ROM_EN = 1,

ROM_CONFI G[1]

Define the primary memory-aperture size when STRAP_BIOS_ROM_EN = 0.

ROM_CONFI G[2]

The LSB (least significant bit) of the strap option that
indicates the number of audio-capable display outputs.

1 = PCIe GEN3 is supported.
0 = PCIe GEN3 is not supported.

0 = The CLKREQB power management capability is disabled
1 = The CLKREQB power management capability is enabled

N/A

Reserved for internal use only. Must be 0 at reset.

0 = The transmitter half-swing is enabled
1 = The transmitter full-swing is enabled

0 = Tx deemphasis disabled.
1 = Tx deemphasis enabled.

Reserve d.

N/A

Reserve d.

N/A

0 = Disable the external BIOS ROM device.
1 = Enable the external BIOS ROM device.

0 = VGA controller capacity enabled.
1 = The device will not be recognized as the system’ s V GA
controller.

Board configuration related strapping, such as for memory ID

Determines the maximum number of digital display audio endpoints
that will be presented to the OS and user.(Combine with PS_0[5])
111 = No usable endpoints.
110 = One usable endpoint.
101 = Two usable endpoints.
100 = Three usable endpoints.
011 = Four usable endpoints.
010 = Five usable endpoints.
001 = Six usable endpoints.
000 = All endpoints are usable.

+1.8VGS +1.8VGS

12

RV28

8.45K_0402_1%

PX@

PS_0

12

1

RV33

2K_0402_1%

PX@

2

+1.8VGS +1.8VGS

RV42

@

10K_0402_5%

1 2

PS_2

12

1

RV49

4.75K_0402_1%

PX@

2

Bit

MLPS

5 4 3 2 1

1 1

PS_0[5 :1]

1 1

PS_1[5 :1]

1 1

PS_2[5 :1]

1 1

PS_3[5 :1]

with BOM strcture control,
RV43,RV50 change to different value to
adjust VRAM config

with BOM strcture control,
when config PEG3
RV29change to 8.45K,
RV34 change to 2K

SVC SVD

00

0

1

1

0

1

1

X X X

Capacitor Value (nF) Bits [5:4]

680

82

10

NC

Output Voltage (V)

1.1

1.0

0.9

0.8

000 = Hynix 8Gb
010 = Micron 8Gb
001 = Samsung 8Gb

CV1
.01U_0402_16V7-K

@

CV3
.01U_0402_16V7-K

@

00 1

00001

GPU_SVD
GPU_SVC
GPU_SVT

1

RECOM MENDED SETTINGS
0= DO NOT INSTALL RESISTOR
1 = INS TALL 10K RESISTOR
X = DES IGN DEPENDANT
NA = NOT APPLICABLE

001 = 256MB

1= GEN3 is supported

1= Enable

0= Disable

111= No usable endpoints.

12

RV29

8.45K_0402_1%

PX@

PS_1

12

RV34

2K_0402_1%

PX@

12

RV43

8.45K_0402_1%

X76@

PS_3

12

RV50

2K_0402_1%

X76@

BOM

R _ p u( )



R _ p d( )

RV28=8.45k RV33=2K CV1=NC

RV29=8.45K RV34=2K CV2=NC

0

RV42=NC RV49=4.75K CV3=NC

RV43=X76 RV50=X76 CV4=NC

R_pu (Ω ) Bits [3:1]

NC

8450

4530

6980

4530

3240

00

3400

01

4750

10

11

Note: 0402 1% resistors are required.

1 2

RV61

+1.8VGS

0_0402_5%

1 2

RV62

0_0402_5%

12

12

RV64

RV65

10K_0402_5%

10K_0402_5%

@

PX@

12

RV68

10K_0402_5%

10K_0402_5%

@

PX@

1 2

@

PX@

RV69

R_pd (Ω )

4750

2000

2000

4990

4990

5620

10000

NC

+VDDIO_GPU+3VGS

RECOMMENDED
SET TINGS

1

CV2
.01U_0402_16V7-K

2

@

1

CV4
.01U_0402_16V7-K

2

@



C(nF)

@

12

@

RV66

10K_0402_5%

12

RV70

10K_0402_5%

@

X

1

X

0

0

1

X

0

0

X

1

X

11

000

001

010

011

100

101

110

111

1

CV198

2

0.1U_0201_6.3V6-K

DV3

@

GPU_RST#

GPIO_19_CTF

1 2

RB751V-40_SOD323-2

@

1 2

47K_0402_5%

4

RV73

GPU_RST#17

A A

5

RV71

1 2

2.2K_0402_5%

@

RV72
100K_0402_5%

@

1 2

C

QV1

2

MMBT3904WH_SOT323-3

B

@

E

3 1

@

1

CV8

0.1U_0201_6.3V6-K

2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIETARY PROPERTY O F LC FUTURE CENTER. AND CONTAINS C ONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIETARY PROPERTY O F LC FUTURE CENTER. AND CONTAINS C ONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIETARY PROPERTY O F LC FUTURE CENTER. AND CONTAINS C ONFIDENTIAL
AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY L C FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY L C FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY L C FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTE N CONSENT OF LC FUTURE CE NTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTE N CONSENT OF LC FUTURE CE NTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTE N CONSENT OF LC FUTURE CE NTER.

3

2017/01/01

2017/01/01

2017/01/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Internal VGA Thermal Sensor

VGA_SMB_CLK

VGA_SMB_DATA

Deciphered Date

Deciphered Date

Deciphered Date

2

RV74

47K_0402_5%

PX@

2018/06/31

2018/06/31

2018/06/31

1 2

+3VGS

RV75

G

2

47K_0402_5%

PX@

1 2

S

61

QV2A

PX@

D

2N7002KDWH_SOT363-6

S

QV2B

2N7002KDWH_SOT363-6

Title

Title

Title

ATI_R17M-M1-70_Main_MSIC

ATI_R17M-M1-70_Main_MSIC

ATI_R17M-M1-70_Main_MSIC

Size

Size

Size

Document Number Rev

Document Number Rev

Document Number Rev

Custom

Custom

Custom

Thursday, May 04, 2017

Thursday, May 04, 2017

Thursday, May 04, 2017

Date: Sheet of

Date: Sheet of

Date: Sheet of

+3VGS

G

5

34

PX@

D

JINN/DOOKU

JINN/DOOKU

JINN/DOOKU

1

EC_SMB_CK3 8,42,49,50

EC_SMB_DA3 8,42,49,50

SDV

SDV

SDV

18 64

18 64

18 64

5

4

3

2

1

UV1F

D D

NC_UPHYAB_TMDPA_TX0N

NC_UPHYAB_TMDPA_TX0P

NC_UPHYAB_TMDPA_TX1N

NC_UPHYAB_TMDPA_TX1P

NC_UPHYAB_TMDPA_TX2N

NC_UPHYAB_TMDPA_TX2P

NC_UPHYAB_TMDPA_TX3N

NC_UPHYAB_TMDPA_TX3P

C C

NC_UPHYAB_TMDPB_TX0N

NC_UPHYAB_TMDPB_TX0P

NC_UPHYAB_TMDPB_TX1N

NC_UPHYAB_TMDPB_TX1P

NC_UPHYAB_TMDPB_TX2N

NC_UPHYAB_TMDPB_TX2P

NC_UPHYAB_TMDPB_TX3N

NC_UPHYAB_TMDPB_TX3P

B B

@

NC_VARY_BL

NC_TXOUT_L3P
NC_TXOUT_L3N

TMDP

NC_TXOUT_U3P
NC_TXOUT_U3N

NC_DIGON

AB11
AB12

AL15
AK14

AH16
AJ15

AL17
AK16

AH18
AJ17

AL19
AK18

AH20
AJ19

AL21
AK20

AH22
AJ21

AL23
AK22

AK24
AJ23

+VGA_CORE

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFO RMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFO RMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFO RMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

2017/01/01

2017/01/01

2017/01/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2018/06/31

2018/06/31

2018/06/31

2

Title

ATI_R17M-M1-70_TMDP

ATI_R17M-M1-70_TMDP

ATI_R17M-M1-70_TMDP

Size Docu ment Number Re v

Size Docu ment Number Re v

Size Docu ment Number Re v

Custom

Custom

Custom

Date : Shee t o f

Date : Shee t o f

Date : Shee t o f

Thursday, May 04, 2017

Thursday, May 04, 2017

Thursday, May 04, 2017

JINN/DOOKU

JINN/DOOKU

JINN/DOOKU

1

19 64

19 64

19 64

SDV

SDV

SDV

5

4

3

2

1

+1.8VGS

1 2

RV76

D D

+0.95VGS

1 2

RV77

C C

B B

(1.8V@425mA DP_VDDR)

PX@

0_0603_5%

10U_0603_6.3V6-M

(0.95V@560mA DP_VDDC)

PX@

0_0603_5%

1U_0402_6.3V6-K

CV11

PX@

PX@

2

1

2

1

2

1U_0402_6.3V6-K

CV10

CV9

PX@

1

PX@

1

CV12

0.1U_0201_6.3V6-K

2

RV78

+DP_VDDR

+DP_VDDC

@

1 2

150_0402_1%

UV1G

AG15

NC_DP_VDDR#AG15

AG16

NC_DP_VDDR#AG16

AF16

NC_DP_VDDR#AF16

AG17

NC_DP_VDDR#AG17

AG18

NC_DP_VDDR#AG18

AG19

NC_DP_VDDR#AG19

AF14

DP_VDDR#AF14

AG20

NC_DP_VDDC#AG20

AG21

NC_DP_VDDC#AG21

AF22

NC_DP_VDDC#AF22

AG22

NC_DP_VDDC#AG22

AD14

DP_VDDC#AD14

AG14

NC_DP_VSSR_1

AH14

NC_DP_VSSR_2

AM14

NC_DP_VSSR_3

AM16

NC_DP_VSSR_4

AM18

NC_DP_VSSR_5

AF23

NC_DP_VSSR_6

AG23

NC_DP_VSSR_7

AM20

NC_DP_VSSR_8

AM22

NC_DP_VSSR_9

AM24

NC_DP_VSSR_10

AF19

NC_DP_VSSR_11

AF20

NC_DP_VSSR_12

AE14

DP_VSSR_13

AF17

NC_UPHYAB_DP_CALR

@

DP POWER

NC/DP POWER

NC#AE11
NC#AF11
NC#AE13
NC#AF13

NC#AG10

NC#AF10

NC#AG11

NC#AE10

NC#AG8

NC#AF6
NC#AF7
NC#AF8
NC#AF9

NC#AE1
NC#AE3
NC#AG1
NC#AG6
NC#AH5

NC#AG9
NC#AH8
NC#AM6
NC#AM8
NC#AG7

AE11
AF11
AE13
AF13
AG8
AG10

AF6
AF7
AF8
AF9

AE1
AE3
AG1
AG6
AH5
AF10
AG9
AH8
AM6
AM8
AG7
AG11

AE10

AA27
AB24

AB32
AC24
AC26
AC27
AD25
AD32

AE27

AF32
AG27
AH32

M32

W25
W26
W27

AA11

M12

K28
K32
L27

N25
N27
P25
P32
R27
T25
T32
U25
U27
V32

Y25
Y32

N13
N16
N18
N21

R12
R15
R17
R20
T13
T16
T18
T21

U15
U17
U20

V13
V16
V18
Y10
Y15
Y17
Y20
R11
T11

N11
V11

UV1E

GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31

M6

GND_32
GND_33
GND_34
GND_35
GND_36

P6

GND_37

P9

GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46

T6

GND_47
GND_48
GND_49
GND_50

U9

GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
GND_60
GND_61
GND_62
GND_63
GND_64

@

GND

VSS_MECH_1
VSS_MECH_2
VSS_MECH_3

GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87
GND_88
GND_89
GND_90
GND_91
GND_92
GND_93
GND_94
GND_95
GND_96
GND_97
GND_98

GND_99
GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_113
GND_114
GND_115
GND_116
GND_117
GND_118
GND_119

A3
A30
AA13
AA16
AB10
AB15
AB6
AC9
AD6
AD8
AE7
AG12
AH10
AH28
B10
B12
B14
B16
B18
B20
B22
B24
B26
B6
B8
C1
C32
E28
F10
F12
F14
F16
F18
F2
F20
F22
F24
F26
F6
F8
G10
G27
G31
G8
H14
H17
H2
H20
H6
J27
J31
K11
K2
K22
K6

A32
AM1
AM32

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFO RMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFO RMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFO RMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

2017/01/01

2017/01/01

2017/01/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2018/06/31

2018/06/31

2018/06/31

2

Title

ATI_R17M-M1-70_DP Power

ATI_R17M-M1-70_DP Power

ATI_R17M-M1-70_DP Power

Size Docu ment Number Re v

Size Docu ment Number Re v

Size Docu ment Number Re v

Custom

Custom

Custom

Date : Shee t o f

Date : Shee t o f

Date : Shee t o f

Thursday, May 04, 2017

Thursday, May 04, 2017

Thursday, May 04, 2017

JINN/DOOKU

JINN/DOOKU

JINN/DOOKU

1

20 64

20 64

20 64

SDV

SDV

SDV