Lenovo ideapad 700-14ISK Schematic

1

A A

2

3

4

5

Compal Confidential

M/B Schematics Document

B B

Intel Skylake-H 4+2 + AMD Tropo XT2

C C

LA-C951P

2015-08-14

REV:1.0

D D

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

For DFT ONLY

1

2

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/08/ 10 2016/12/ 31

2015/08/ 10 2016/12/ 31

2015/08/ 10 2016/12/ 31

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date : Sheet o f

Date : Sheet o f

4

Date : Sheet o f

Compal Electronics, Inc.

Cover Sheet

Cover Sheet

Cover Sheet

LA-C951P

LA-C951P

LA-C951P

1 6 2Friday, August 14, 20 15

1 6 2Friday, August 14, 20 15

1 6 2Friday, August 14, 20 15

5

1.0

1.0

1.0

1

Compal Confidential
Model Name : AIPY6
Project Name : LA-C951P

2

3

4

5

Skylake-H

A A

ATI

Tropo XT2 (R9-M375)

VRAM 256X16, 128X16

gDDR5 x 8

14.0" FHD (1920x1080)

HDMI Conn.

B B

C C

p.32

HDMI level shifter 2.97G

Parade PS8407A

RJ45

p.36

SPI ROM
GD25B64BSIGR
8MB

+VGA_C ORE
+3VS G
+1.8V SG
+1.5V SG

45W DDR4-SO-DIMM X 2

+0.95 VSG

p.22~p .31

IPS/TN

LCD conn

PEG X 8

eDPx1

p.33

DDI x 4 lanes

p.32

NGFF (TYPE E)

2230 Conn.
WLAN/BT4.0

p.34

LAN (10/100/1000GbE)

PCIE x 1

PCIE x 1

Realtek GbE

RTL8111H-CG

Card Reader

p.36

PCIE x 1

Realtek

RTS5249S-GR

p.35

Intel

Processor

Skylake-H
4+2

45W

BGA

42mmX 28mm

DMI x4

Gen3

Intel
Skylake
PCH-H

FCBGA

p.6~p .12

DDR4 2133MHz

1.2V, 2.5V

Dual Channel

USB2.0 x 5

USB3.0 x 2

BT (NGFF)

Camera

USB 3.0 conn x2

USB Charger
TI
TPS2546RTER

p.34

720p HD

p.33

p.43

p.43

p.20~p .21

HM 170

SPI

p.16

23mmX23mm

USB 2.0 conn x1

IO Board
LS-B952P

2.5" SATA HDD

NGFF (TYPE M)
M.2 SATA/PCIE SSD(Gen3)

p.42

p.42

SATA 3.0 x 1

SATA 3.0 x 1

PCIE x 4

p.13~p .19

LPC BUS

Touch Pad CONN.

D D

Thermal Sensor

F75397M

For DFT ONLY

1

2

p.40 p.40

p.40

NPCE388NA0DX

p.38

3

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

HDA

TPM2.0
Z32H320TC

Int. KBDNuvoton

LID switch
Toshiba TCS20DLR

Issued Date

Issued Date

Issued Date

Audio Codec

Realtek ALC3248-CG

p.39

Reser ve

p.41

Compal Secret Data

Compal Secret Data

2015/08/10 2016/12/31

2015/08/10 2016/12/31

2015/08/10 2016/12/31

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

4

p.37

Combo Jack

JBL Speaker

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date : Sheet of

Date: Sheet of

Date: Sheet of

Block Diagram

Block Diagram

Block Diagram

LA-C951P

LA-C951P

LA-C951P

5

1.0

1.0

2 62Friday, August 14, 2015

2 62Friday, August 14, 2015

2 62Friday, August 14, 2015

1.0

A

Funct i on

BOM Structure Table

Un-Stuf f

Stuf f

DGPU SKU DIS@
SPI_IO3(MOW36)
2G VRAM

4G VRAM
NC Components

QS@
V2G@
V4G@

CMC

EMI

ESD
RF
ISCT

MPHY_EXT
CPU

KB ID

Power State

STATE

EMI@

ESD@

RF@

NOISCT@

NOEXTMPHY@ EXTMPHY@
CPU5@/CPU6@

NOKBL@/KBL@

SIGNAL

S0 (Full ON)

S3 (Suspend to RAM)

1 1

S4 (Suspend to Disk)

@DIS@
ES@

@
CMC@
TPM@TPM
@EMI@
@ESD@
@RF@
ISCT@

SLP_S4#

SLP_S3#

HIGH HIGH HIGH

HIGH

LOW

LOWLOW

S5 (Sof t OFF)

Voltage Rails

Power Plane Descript i on

VIN

BATT+
+19VB
+VCC_CO RE
+VCC_GT Sliced graphics power rail

+0.6VS_VTT

+1VALW System +1VALW power rail ON*ONON

+1V_PRIM

+VCCIO +1.0VS IO power rail
+VGA_PCIE

+MEM_GFX +1.5VS power rail for GPU

+1VS_VCCST
+1VS_VCCSTG
+3VALW System +3VALW always on power rail
+3VLP +19VB to +3VLP power rail for suspend power
+3VALW_DSW +3VALW power for PCH DSW rails

+3V_LAN
+3VS
+1.8VGS +1.8VS power rail for GPU

+5VALW

+5VS System +5VS power rail

+3VL_RTC RTC power

+VCC_SA System Agent power rail

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF

Adapter power supply

Bat t ery po wer suppl y
AC or bat t ery po wer r ail f or po wer circ uit

Core voltage for CPU

DDR +0.6VS power rail for DDR terminator

System +1VALW power rail ON*

+1.0VS power rail for GPU

DDR-IV +1.2V power rail+1.2V_VDDQ

+1.0V power rail for CPU
+1.0VS power rail for CPU

+3VALW power for LAN power rails
System +3VS power rail

+3VS power rail for GPU+3VGS

System +5VALW power rail

Load BOM Opt i on Tabl e

BOM Number Load BOM Opt i on

4519YS38L09

4519YS38L12

DIS@/QS@/EMI@/ESD@/RF@/NOEXTMPHY@/HM170@ /NOISCT@

DIS@/QS@/EMI@/ESD@/RF@/NOEXTMPHY@/HM170@ /NOISCT@

For DFT ONLY

HSIO Port Table

HSIO Port Capable

.... .... .... ....

12 PCI E_6

.... .... .... ....

16 PCI E_10 / SATA_1A HDD_SATA

1718PCIE_11

19

20

21

22

.... .... .... ....

+VALW

SLP_S5#

ON ON ON ON

HIGH

ONONON

HIGH

ON

USB3.0_1 / OTG

1

USB3.0_2 / SSIC_1

2

USB3.0_3 / SSIC_2

3

USB3.0_4

4

5 USB3.0_5 / PCIE_1

PCIE_12

PCIE_13 / SATA_0B

PCIE_14 / SATA_1B

PCIE_15 / SATA_2

PCIE_16 / SATA_3

+VS Clock

+V

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFFLOW LOW LOW

S3

S0

N/A

N/A

N/A

N/A

N/A

N/A

OFF

ON

OFF

ON

OFF

ON

ON

ON

OFF

ON

OFF

ON

OFF

ON

ON

ON

ON

ON

OFF

ON

ON

ON

ON

ON

ON

ON

ON

ON

OFF

ON

OFF

ON

OFF

ON

ON

ON

OFF

ON

ON

ON

NA

NA

USB3.0 (MB_UP)

USB3.0 (MB_DOWN)

NA

WLAN(NGFF_KEY E)

Card Reader

LAN

S4/S5

N/A
N/A
N/A

OFF
OFF
OFF

OFF
OFF
OFF
OFF
OFF
OFF
ON*
ON
ON*
ON*
OFF
OFF
OFF
ON*
OFF
ON
OFFOFFON

/CPU5@/KBL@

/CPU6@/KBL@

Device PCIE CLK

SSD_SATA

SSD_PCIe x 4

CPU/PCH part

UC1

S IC CL8066202194632 SR2FP R0 2.3G C38!

SA000096Q30

SKL-H

UC1

S IC CL8066202194635 SR2FQ R0 2.6G C38!

SA000095Z50

UH1

PCH-H

S IC GLHM170 SR2C4 D1 BGA 837P PCH C38 !

SA000096J60

UV1

VGA

HDMI

S IC 216-0866000 A1 TROPO XT2 962P C38!

SA00008B310

HDMI

HDMI_ROYALTY

RO0000003HM
ROYALTY HDMI W/LOGO+HDCP

45@

CPU5@

CPU6@

HM170@

DIS@

CLK3

CLK2

CLK1

CLK4

QS-R3

QS-R3

QS-R3

R3

NOTE

Opt i on SSD ty pe

USB2.0 Port Table

USB2.0 Port Devi ce

USB3.0 (MB_UP)

1

2

USB3.0 (MB_DOWN)

NA

3

4

BT (NGFF)

NA

5

6

USB2.0 (IO_Charge Port)

NA

7

8 Camera

NA

9

NA

10

ZZZ

@

PCB 1F6 LA-C951P REV1 M/B 2

DA80013R010

ZZZ

PCB AIPY6 LA-C951P LS-C951P/C952P 02

DAZ1F600100

ZZZ

V2G@

EDW2032BBBG-6A-F-R

UV3

HYN2@

H5TC2G63FFR-11C

UV7

HYN2@

H5TC2G63FFR-11C

SA00006H410

UV3

MIC2@

EDW2032BBBG-6A-F-R

EDW2032BBBG-6A-F-R

Micron_X7663138L01

Samsung_X7663138L02

A

EDW2032BBBG-6A-F-R

UV7

MIC2@

EDW2032BBBG-6A-F-R

SA00007HS10

UV3

SAM2@

K4G20325FD-FC03

UV7

SAM2@

K4G20325FD-FC03

SA000066I10

2G
X7663138L01

UV4

HYN2@

UV5

H5TC2G63FFR-11C

H5TC2G63FFR-11C

UV4

UV8

K4G20325FD-FC03

K4G20325FD-FC03

H5TC2G63FFR-11C

UV8

UV8

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

UV9

HYN2@

H5TC2G63FFR-11C

MIC2@

UV5

EDW2032BBBG-6A-F-R

MIC2@ UV10

UV9

EDW2032BBBG-6A-F-R

SAM2@

UV5

K4G20325FD-FC03

SAM2@

K4G20325FD-FC03

Issued Date

Issued Date

Issued Date

SOC SMBUS Address Table

SOC_SMBUS Net Name

SMBCLK
SMBD ATA

SML0CLK
SML0DATA

SML1CLK
SML1DATA

EC SMBUS Address Table

EC_SMBUS Port

SMBUS Port 1

SMBUS Port 2

gDDR5 VRAM * 8

RV6

HYN2@ UV6

HYN2@

MIC2@

EDW2032BBBG-6A-F-R

MIC2@

EDW2032BBBG-6A-F-R

SAM2@

UV9

SAM2@

HYN2@

H5TC2G63FFR-11C

UV10

HYN2@

H5TC2G63FFR-11C

UV6

MIC2@

MIC2@

UV6

SAM2@

K4G20325FD-FC03

UV10

SAM2@

K4G20325FD-FC03

2015/08/10 2016/12/31

2015/08/10 2016/12/31

2015/08/10 2016/12/31

HYN2@

10K_0402_5%

RV8

HYN2@

10K_0402_5%

RV10

HYN2@

10K_0402_5%

RV6

MIC2@

10K_0402_5%

RV8

MIC2@

10K_0402_5%

RV9

MIC2@

10K_0402_5%

RV6

SAM2@

10K_0402_5%

RV7

SAM2@

10K_0402_5%

RV10

SAM2@

10K_0402_5%

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Power R ail

+3VS

+3VS

+3VS

Power R ail Device Address (7 bit)

+3VLP

+3VLP TP (reserve) TBC TBCTBC

+3VLP

(TBC)

Device

DIMM1

DIMM2

TP TBC TBC TBC

EC

Thermal sensor

Address (7 bit)

TBC

TBC

TBC TBC

TBC

1001100

(TBC)

BAT

CHGR TBC TBC

Thermal sensor

ZZZ

V4G@

EDW4032BABG-50-F

UV3

HYN4@ UV6

H5GC4H24AJR-T2C

UV7

HYN4@

H5GC4H24AJR-T2C

SA000085V40

1001100

UV4

HYN4@

H5GC4H24AJR-T2C

UV8

HYN4@

H5GC4H24AJR-T2C

TBC

TBC

Hynix_X7663138L04Hynix_X76xxx38Lxx

UV3

MIC4@

UV4

MIC4@

EDW4032BABG-50-F

UV7

MIC4@

EDW4032BABG-50-F

SA00008VF10

EDW4032BABG-50-F

EDW4032BABG-50-F

UV8

EDW4032BABG-50-F

MIC4@

EDW4032BABG-50-F

Micron_X7663138L03

UV4

UV3

SAM4@

K4W4G1646E-BC1A

UV7

SAM4@

K4W4G1646E-BC1A

SA000076P10

SAM4@

K4W4G1646E-BC1A

UV8

SAM4@ UV9

K4W4G1646E-BC1A

K4W4G1646E-BC1A

K4W4G1646E-BC1A

Samsung_X76xxx38Lxx

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Notes List

Notes List

Notes List

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

Custom

Custom

Custom

LA-C951P

LA-C951P

LA-C951P

Date : Sheet of

Date : Sheet of

Date : Sheet of

Address (8bit)
Write Read

TBC

TBC

TBC

TBC TBC

Address (8bit)
Write Read

TBC TBC

TBC

4G
X7663138L03

UV5

HYN4@

H5GC4H24AJR-T2C

UV9

HYN4@

H5GC4H24AJR-T2C

UV5

MIC4@

EDW4032BABG-50-F

UV9

MIC4@

EDW4032BABG-50-F

UV5

SAM4@

K4W4G1646E-BC1A

SAM4@

K4W4G1646E-BC1A

0xA0

0xA4

TBCTBC

TBC

HYN4@

H5GC4H24AJR-T2C

UV10

HYN4@

H5GC4H24AJR-T2C

UV6

MIC4@

UV10

MIC4@

UV6

SAM4@UV4

UV10

SAM4@

RV6

10K_0402_5%

RV7

10K_0402_5%

RV9

10K_0402_5%

RV5

10K_0402_5%

RV8

10K_0402_5%

RV10

10K_0402_5%

RV5

10K_0402_5%

RV7

10K_0402_5%

RV10

10K_0402_5%

3 62Friday, August 14, 2015

3 62Friday, August 14, 2015

3 62Friday, August 14, 2015

SAM4@

SAM4@

SAM4@

HYN4@

HYN4@

HYN4@

MIC4@

MIC4@

MIC4@

1.0

1.0

1.0

5

D D

C C

4

3

2

1

B B

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

For DFT ONLY

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

2015/08/10 2016/12/31

2015/08/10 2016/12/31

2015/08/10 2016/12/31

4

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Document Number Re v

Size

Document Number Re v

Size

Document Number Re v

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

3

Date: Sheet of

2

Power map

Power map

Power map

LA-C951P

LA-C951P

LA-C951P

1.0

1.0

1.0

4 62Friday, August 14, 2015

4 62Friday, August 14, 2015

4 62Friday, August 14, 2015

1

5

[AIPY6-PWR Sequence_SKL-H 4+2_DDR4]

4

3

2

1

G3->S0 S0->S3 ->S0

+3VL_RTC

RTCRST#

D D

+19VB

+3VLP/+5V LP

EC_ON (PIN112)

+5VALW/+ 3VALW
+3VALW_DSW

SUSACK#

+1V_PRIM

DSW_PWROK

EC_RSMRST# (PIN100)

AC_PRESENT (PIN74)

ON/OFF#

PBTN_OUT# (PIN122)

PM_SLP_S5#

C C

PM_SLP_S4#

2.5V_PWR_EN (PIN15) 2.5V_PWR_EN (PIN66)

+2.5V(VPP) +2.5V(VPP)

SYSON (PIN95)

+1.0V_VCCST/+1.0V_VCCSFR

+1.2V_VDDQ/+1.2V_VCCPLL_OC

PM_SLP_S3#

SUSP# (PIN116)

+1VS_VCCSTG

+VCCIO

+5VS/+3V S

B B

H_VCCST_PWRGD (PIN21)

VR_ON (PIN108)

SM_PG_CTRL

+0.6VS_VTT

+VCC_SA

+VCC_C ORE

+VCC_GT

VGATE

(PIN107)

PCH_PWROK (PIN32)

H_CPUPWRGD

SYS_PWROK (PIN98)

A A

SUS_STAT#

PLTRST#

(PIN13)

(PIN123)

(PIN106)

tPCH01_Min : 9 ms

tPCH04_Min : 9 ms

tPCH34_Max : 20 ms

tPCH06_Min : 200 us

tPCH02_Min : 10 ms

tPCH03_Min : 10 ms (VccPrimary stable to RSMRST# high)

tPLT02_Min : 0 ms Max : 90 ms

tPCH43_Min : 95 ms

Minimum duration of PWRBTN# assertion = 16mS. PWRBTN# can assert before or after RSMRST#

T = 30msec

T = 40msec

tCPU04 Min : 100 ns

tCPU10 Min : 1 ms

T <=10msec

T = 20msec

tCPU19 Max : 100 ns

tCPU18 Max : 35 us

tCPU09 Min : 1 ms

T = 100msec

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

For DFT ONLY

5

4

3

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

T = 20msec

T = 100msec

Compal Secret Data

Compal Secret Data

2015/08/10 2016/12/31

2015/08/10 2016/12/31

2015/08/10 2016/12/31

Compal Secret Data

2

Deciphered Date

Deciphered Date

Deciphered Date

S0->S5S3

+3VL_RTC

SOC_RTCRST#

+19VB

+3VLP/+5V LP

EC_ON

+5VALW/+ 3VALW
+3VALW_DSW

SUSACK#

+1.0V_PRIM

DSW_PWROK

EC_RSMRST#

AC_PRESE NT

ON/OFF

PBTN_OUT#

PM_SLP_S5#

PM_SLP_S4#

SYSON (PIN95)

+1V_VCCST/+1V_VCCSFR

+1.2V_VDDQ/+1.2V_VCCPLL_OC

PM_SLP_S3#

SUSP#

+1VS_VCCSTG

+VCCIO

+5VS/+3V S

H_VCCST_PG (PIN107)

VR_ON (PIN70)

SM_PG_CTRL

+0.6VS_VTT

+VCC_SA

+VCC_C ORE

+VCC_GT

VGATE

PCH_PWROK

H_CPUPWRGD

SYS_PWROK (PIN98)

SUS_STAT#

SOC_PLTRST#

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Power Sequence

Power Sequence

Power Sequence

Document Number Re v

Document Number Re v

Document Number Re v

1

5 62Friday, August 14, 2015

5 62Friday, August 14, 2015

5 62Friday, August 14, 2015

1.0

1.0

1.0

tCPU28< 1us

tPLT17< 1us

tPLT16_Min : 30 ms

Title

Title

Title

Size

Size

Size

Date: Sheet of

Date: Sheet of

Date: Sheet of

5

D D

+VCCIO

C C

RC7 24.9_0402_1%

Note :
Trace width=12 mils ,Spacing=15mils
Max length= 400 mils.

1 2

PEG_RCOMP

DMI_CRX_PTX_P[0..3]<13>
DMI_CRX_PTX_N[0..3]<13>

4

PEG_CRX_GTX_P[0..7]<22> PEG_CTX_C_GRX_P [0..7] <22>
PEG_CRX_GTX_N[0..7]<22> PEG_CTX_C_GRX_N[0..7] <22>

UC1C

@

E25

PEG_RXP[0]

D25

PEG_RXN[0]

E24

PEG_RXP[1]

F24

PEG_RXN[1]

E23

PEG_RXP[2]

D23

PEG_RXN[2]

E22

PEG_RXP[3]

F22

PEG_RXN[3]

E21

PEG_RXP[4]

D21

PEG_RXN[4]

E20

PEG_RXP[5]

F20

PEG_RXN[5]

E19

PEG_RXP[6]

D19

PEG_RXN[6]

E18

Reverse

PEG_CRX_GTX_P7
PEG_CRX_GTX_N7

PEG_CRX_GTX_P6
PEG_CRX_GTX_N6

PEG_CRX_GTX_P5
PEG_CRX_GTX_N5

PEG_CRX_GTX_P4
PEG_CRX_GTX_N4

PEG_CRX_GTX_P3
PEG_CRX_GTX_N3

PEG_CRX_GTX_P2
PEG_CRX_GTX_N2

PEG_CRX_GTX_P1
PEG_CRX_GTX_N1

PEG_CRX_GTX_P0
PEG_CRX_GTX_N0

PEG_RCOMP

DMI_CRX_PTX_P0
DMI_CRX_PTX_N0

DMI_CRX_PTX_P1

DMI_CRX_PTX_P2
DMI_CRX_PTX_N2

DMI_CRX_PTX_P3 DM I_CTX_PRX_P3
DMI_CRX_PTX_N3 DMI_CTX_PRX_N3

F18

D17
E17

F16
E16

D15
E15

F14
E14

D13
E13

F12
E12

D11
E11

F10
E10

G2

D8
E8

E6
F6

D5

E5

J8
J9

SKL-H_BGA1440

PEG_RXP[7]
PEG_RXN[7]

PEG_RXP[8]
PEG_RXN[8]

PEG_RXP[9]
PEG_RXN[9]

PEG_RXP[10]
PEG_RXN[10]

PEG_RXP[11]
PEG_RXN[11]

PEG_RXP[12]
PEG_RXN[12]

PEG_RXP[13]
PEG_RXN[13]

PEG_RXP[14]
PEG_RXN[14]

PEG_RXP[15]
PEG_RXN[15]

PEG_RCOMP

DMI_RXP[0]
DMI_RXN[0]

DMI_RXP[1]
DMI_RXN[1]

DMI_RXP[2]
DMI_RXN[2]

DMI_RXP[3]
DMI_RXN[3]

SKYLAKE_HALO

BGA1440

3 OF 14

3

PEG_TXP[10]
PEG_TXN[10]

PEG_TXP[11]
PEG_TXN[11]

PEG_TXP[12]
PEG_TXN[12]

PEG_TXP[13]
PEG_TXN[13]

PEG_TXP[14]
PEG_TXN[14]

PEG_TXP[15]
PEG_TXN[15]

PEG_TXP[0]

PEG_TXN[0]

PEG_TXP[1]
PEG_TXN[1]

PEG_TXP[2]
PEG_TXN[2]

PEG_TXP[3]
PEG_TXN[3]

PEG_TXP[4]
PEG_TXN[4]

PEG_TXP[5]
PEG_TXN[5]

PEG_TXP[6]
PEG_TXN[6]

PEG_TXP[7]
PEG_TXN[7]

PEG_TXP[8]
PEG_TXN[8]

PEG_TXP[9]
PEG_TXN[9]

DMI_TXP[0]
DMI_TXN[0]

DMI_TXP[1]
DMI_TXN[1]

DMI_TXP[2]
DMI_TXN[2]

DMI_TXP[3]
DMI_TXN[3]

B25
A25

B24
C24

B23
A23

B22
C22

B21
A21

B20
C20

B19
A19

B18
C18

PEG_CTX_GRX_P7 PEG_CTX_C_GRX_P 7

A17
B17

C16

PEG_CTX_GRX_N6

B16

PEG_CTX_GRX_P5

A15

PEG_CTX_GRX_N5

B15

PEG_CTX_GRX_P4

C14

PEG_CTX_GRX_N4

B14

PEG_CTX_GRX_P3 PEG_CTX_C_GRX_P 3

A13
B13

C12

PEG_CTX_GRX_N2

B12

PEG_CTX_GRX_P1 PEG_CTX_C_GRX_P 1

A11

PEG_CTX_GRX_N1

B11

PEG_CTX_GRX_P0 PEG_CTX_C_GRX_P 0

C10
B10

DMI_CTX_PRX_P0

B8

DMI_CTX_PRX_N0

A8

DMI_CTX_PRX_P1

C6

DMI_CTX_PRX_N1DMI_CRX_PTX_N1

B6

DMI_CTX_PRX_P2

B5

DMI_CTX_PRX_N2

A5

D4
B4

Reverse

12
12

12
12

12
12

12
12

12
12

12
12

12
12

12
12

CC30.22U_0402 _10V6K DIS@
CC40.22U_0402 _10V6K DIS@

CC50.22U_0402 _10V6K DIS@
CC60.22U_0402 _10V6K DIS@

CC70.22U_0402 _10V6K DIS@
CC80.22U_0402 _10V6K DIS@

CC90.22U_0402 _10V6K DIS@
CC100.22U_0402 _10V6K DIS@

CC120.22U_0402 _10V6K DIS@
CC130.22U_0402 _10V6K DIS@

CC150.22U_0402 _10V6K DIS@
CC140.22U_0402 _10V6K DIS@

CC160.22U_0402 _10V6K DIS@
CC170.22U_0402 _10V6K DIS@

CC180.22U_0402 _10V6K DIS@
CC200.22U_0402 _10V6K DIS@

DMI_CTX_PRX_P[0..3] <13>
DMI_CTX_PRX_N[0..3] <13>

2

PEG_CTX_C_GRX_N 7PEG_CTX_GRX_N7

PEG_CTX_C_GRX_P 6PEG_CTX_GR X_P6
PEG_CTX_C_GRX_N 6

PEG_CTX_C_GRX_P 5
PEG_CTX_C_GRX_N 5

PEG_CTX_C_GRX_P 4
PEG_CTX_C_GRX_N 4

PEG_CTX_C_GRX_N 3PEG_CTX_GRX_N3

PEG_CTX_C_GRX_P 2PEG_CTX_GR X_P2
PEG_CTX_C_GRX_N 2

PEG_CTX_C_GRX_N 1

PEG_CTX_C_GRX_N 0PEG_CTX_GRX_N0

1

B B

TMDS_B_DATA2_ C

12

TMDS_B_DATA2<32>
TMDS_B_DATA2#<32>
TMDS_B_DATA1<32>
TMDS_B_DATA1#<32>
TMDS_B_DATA0<32>

HDMI

A A

TMDS_B_DATA0#<32>
TMDS_B_CL K<32>
TMDS_B_CL K#<32>

12
12
12
12
12
12
12

C2300.1U_0201_ 10V6K
C2310.1U_0201_ 10V6K
C2320.1U_0201_ 10V6K
C2330.1U_0201_ 10V6K
C2340.1U_0201_ 10V6K
C2350.1U_0201_ 10V6K
C2360.1U_0201_ 10V6K
C2370.1U_0201_ 10V6K

TMDS_B_DATA2# _C
TMDS_B_DATA1_ C
TMDS_B_DATA1# _C
TMDS_B_DATA0_ C
TMDS_B_DATA0# _C
TMDS_B_CL K_C
TMDS_B_CL K#_C

K36
K37

J35

J34
H37
H36

J37

J38

D27
E27

H34
H33
F37
G38
F34
F35
E37
E36

F26
E26

C34
D34
B36
B34
F33
E33
C33
B33

A27
B27

For DFT ONLY

5

4

UC1D

@

DDI1_TXP[0]
DDI1_TXN[0]
DDI1_TXP[1]
DDI1_TXN[1]
DDI1_TXP[2]
DDI1_TXN[2]
DDI1_TXP[3]
DDI1_TXN[3]

DDI1_AUXP
DDI1_AUXN

DDI2_TXP[0]
DDI2_TXN[0]
DDI2_TXP[1]
DDI2_TXN[1]
DDI2_TXP[2]
DDI2_TXN[2]
DDI2_TXP[3]
DDI2_TXN[3]

DDI2_AUXP
DDI2_AUXN

DDI3_TXP[0]
DDI3_TXN[0]
DDI3_TXP[1]
DDI3_TXN[1]
DDI3_TXP[2]
DDI3_TXN[2]
DDI3_TXP[3]
DDI3_TXN[3]

DDI3_AUXP
DDI3_AUXN

SKL-H_BGA1440

SKYLAKE_HALO

BGA1440

4 OF 14

D29

EDP_TXP[0]

E29

EDP_TXN[0]

F28

EDP_TXP[1]

E28

EDP_TXN[1]

B29

EDP_TXN[2]

A29

EDP_TXP[2]

B28

EDP_TXN[3]

C28

EDP_TXP[3]

C26

EDP_AUXP

B26

EDP_AUXN

CPU_INV_PWM

EDP_DISP_UTIL

PROC_AUDIO_CLK

PROC_AUDIO_SDI

PROC_AUDIO_SDO

3

A33

EDP_COMP

D37

EDP_RCOMP

G27
G25

CPU_DISPA_SDI

G29

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

EDP_TXP0 <33>
EDP_TXN0 <33>
EDP_TXP1 <33>
EDP_TXN1 <33>

EDP_AUXP < 33>
EDP_AUXN <33>

@

T215

EDP_COMP

Note :
Trace width=20 mils ,Spacing=25mils
Max length= 100 mils.

CPU_DISPA_BCLK_R <15>

RC25 20_0402_1 %

12

2015/08/10 2016/12/31

2015/08/10 2016/12/31

2015/08/10 2016/12/31

CPU_DISPA_SDO_R <15>

CPU_DISPA_SDI_R <15>

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

+VCCIO

12

RC824.9_0402_1%

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document N umber Re v

Size Document N umber R ev

Size Document N umber R ev

Custom

Custom

Custom

Date : Sh eet o f

Date : Sh eet o f

Date : Sh eet o f

Compal Electronics, Inc.
DMI,PEG,DDI,EDP

DMI,PEG,DDI,EDP

DMI,PEG,DDI,EDP

LA-C951P

LA-C951P

LA-C951P

1

6 62Friday, August 14, 2015

6 62Friday, August 14, 2015

6 62Friday, August 14, 2015

1.0

1.0

1.0

5

4

3

2

1

UC1A

DDR_A_D [0..15]<20>

D D

DDR_A_D [16..31]<20>

C C

B B

DDR_A_D [32..47]<20>

DDR_A_D [48..63]<20>

DDR_A_D 0
DDR_A_D 1
DDR_A_D 2
DDR_A_D 3
DDR_A_D 4
DDR_A_D 5
DDR_A_D 6
DDR_A_D 7
DDR_A_D 8
DDR_A_D 9
DDR_A_D 10
DDR_A_D 11
DDR_A_D 12
DDR_A_D 13
DDR_A_D 14
DDR_A_D 15
DDR_A_D 16
DDR_A_D 17
DDR_A_D 18
DDR_A_D 19
DDR_A_D 20
DDR_A_D 21
DDR_A_D 22
DDR_A_D 23
DDR_A_D 24
DDR_A_D 25
DDR_A_D 26
DDR_A_D 27
DDR_A_D 28
DDR_A_D 29
DDR_A_D 30
DDR_A_D 31
DDR_A_D 32
DDR_A_D 33
DDR_A_D 34
DDR_A_D 35
DDR_A_D 36
DDR_A_D 37
DDR_A_D 38
DDR_A_D 39
DDR_A_D 40
DDR_A_D 41
DDR_A_D 42
DDR_A_D 43
DDR_A_D 44
DDR_A_D 45
DDR_A_D 46
DDR_A_D 47
DDR_A_D 48
DDR_A_D 49
DDR_A_D 50
DDR_A_D 51
DDR_A_D 52
DDR_A_D 53
DDR_A_D 54
DDR_A_D 55
DDR_A_D 56
DDR_A_D 57
DDR_A_D 58
DDR_A_D 59
DDR_A_D 60
DDR_A_D 61
DDR_A_D 62
DDR_A_D 63

BR6

BT6
BP3
BR3
BN5
BP6
BP2
BN3
BL4
BL5
BL2

BM1

BK4
BK5
BK1
BK2
BG4

BG5

BF4
BF5
BG2

BG1

BF1

BF2
BD2
BD1
BC4
BC5

BD5
BD4

BC1

BC2

AB1

AB2

AA4

AA5

AB5

AB4

AA2

AA1

BA2

BA1

AY4

AY5

BA5

BA4

AY1

AY2

M4
M1

M5
M2

@

DDR0_DQ[0]
DDR0_DQ[1]
DDR0_DQ[2]
DDR0_DQ[3]
DDR0_DQ[4]
DDR0_DQ[5]
DDR0_DQ[6]
DDR0_DQ[7]
DDR0_DQ[8]
DDR0_DQ[9]
DDR0_DQ[10]
DDR0_DQ[11]
DDR0_DQ[12]
DDR0_DQ[13]
DDR0_DQ[14]
DDR0_DQ[15]
DDR0_DQ[16]/DDR0_DQ[32]
DDR0_DQ[17]/DDR0_DQ[33]
DDR0_DQ[18]/DDR0_DQ[34]
DDR0_DQ[19]/DDR0_DQ[35]
DDR0_DQ[20]/DDR0_DQ[36]
DDR0_DQ[21]/DDR0_DQ[37]
DDR0_DQ[22]/DDR0_DQ[38]
DDR0_DQ[23]/DDR0_DQ[39]
DDR0_DQ[24]/DDR0_DQ[40]
DDR0_DQ[25]/DDR0_DQ[41]
DDR0_DQ[26]/DDR0_DQ[42]
DDR0_DQ[27]/DDR0_DQ[43]
DDR0_DQ[28]/DDR0_DQ[44]
DDR0_DQ[29]/DDR0_DQ[45]
DDR0_DQ[30]/DDR0_DQ[46]
DDR0_DQ[31]/DDR0_DQ[47]
DDR0_DQ[32]/DDR1_DQ[0]
DDR0_DQ[33]/DDR1_DQ[1]
DDR0_DQ[34]/DDR1_DQ[2]
DDR0_DQ[35]/DDR1_DQ[3]
DDR0_DQ[36]/DDR1_DQ[4]
DDR0_DQ[37]/DDR1_DQ[5]
DDR0_DQ[38]/DDR1_DQ[6]
DDR0_DQ[39]/DDR1_DQ[7]

V5

DDR0_DQ[40]/DDR1_DQ[8]

V2

DDR0_DQ[41]/DDR1_DQ[9]

U1

DDR0_DQ[42]/DDR1_DQ[10]

U2

DDR0_DQ[43]/DDR1_DQ[11]

V1

DDR0_DQ[44]/DDR1_DQ[12]

V4

DDR0_DQ[45]/DDR1_DQ[13]

U5

DDR0_DQ[46]/DDR1_DQ[14]

U4

DDR0_DQ[47]/DDR1_DQ[15]

R2

DDR0_DQ[48]/DDR1_DQ[32]

P5

DDR0_DQ[49]/DDR1_DQ[33]

R4

DDR0_DQ[50]/DDR1_DQ[34]

P4

DDR0_DQ[51]/DDR1_DQ[35]

R5

DDR0_DQ[52]/DDR1_DQ[36]

P2

DDR0_DQ[53]/DDR1_DQ[37]

R1

DDR0_DQ[54]/DDR1_DQ[38]

P1

DDR0_DQ[55]/DDR1_DQ[39]
DDR0_DQ[56]/DDR1_DQ[40]
DDR0_DQ[57]/DDR1_DQ[41]

L4

DDR0_DQ[58]/DDR1_DQ[42]

L2

DDR0_DQ[59]/DDR1_DQ[43]
DDR0_DQ[60]/DDR1_DQ[44]
DDR0_DQ[61]/DDR1_DQ[45]

L5

DDR0_DQ[62]/DDR1_DQ[46]

L1

DDR0_DQ[63]/DDR1_DQ[47]

DDR0_ECC[0]
DDR0_ECC[1]
DDR0_ECC[2]
DDR0_ECC[3]
DDR0_ECC[4]
DDR0_ECC[5]
DDR0_ECC[6]
DDR0_ECC[7]

SKYLAKE_HA LO

BGA1440

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]
DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]
DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]
DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]

DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]
DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]
DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#

DDR0_DQSN[2]/DDR0_DQSN[4]
DDR0_DQSN[3]/DDR0_DQSN[5]
DDR0_DQSP[4]/DDR1_DQSP[0]
DDR0_DQSP[5]/DDR1_DQSP[1]
DDR0_DQSP[6]/DDR1_DQSP[4]
DDR0_DQSP[7]/DDR1_DQSP[5]

DDR0_DQSP[2]/DDR0_DQSP[4]
DDR0_DQSP[3]/DDR0_DQSP[5]
DDR0_DQSN[4]/DDR1_DQSN[0]
DDR0_DQSN[5]/DDR1_DQSN[1]
DDR0_DQSN[6]/DDR1_DQSN[4]
DDR0_DQSN[7]/DDR1_DQSN[5]

DDR0_CKP[0]
DDR0_CKN[0]
DDR0_CKN[1]

DDR0_CKP[1]

DDR0_CLKP[2]
DDR0_CLKN[2]
DDR0_CLKP[3]
DDR0_CLKN[3]

DDR0_CKE[0]

DDR0_CKE[1]

DDR0_CKE[2]

DDR0_CKE[3]

DDR0_CS#[0]

DDR0_CS#[1]

DDR0_CS#[2]

DDR0_CS#[3]

DDR0_ODT[0]
DDR0_ODT[1]
DDR0_ODT[2]
DDR0_ODT[3]

DDR0_MA[3]
DDR0_MA[4]

DDR0_PAR

DDR0_ALERT#

DDR0_DQSN[0]
DDR0_DQSN[1]

DDR0_DQSP[0]
DDR0_DQSP[1]

DDR0_DQSP[8]

DDR0_DQSN[8]

AG1
AG2
AK1
AK2
AL3
AK3
AL2
AL1

AT1
AT2
AT3
AT5

AD5
AE2
AD2
AE5

AD3
AE4
AE1
AD4

AH5
AH1
AU1

AH4
AG4
AD1

AH3
AP4
AN4
AP5
AP2
AP1
AP3
AN1
AN3
AT4
AH2
AN2
AU4
AE3
AU2
AU3

AG3
AU5

BR5
BL3
BG3
BD3
AB3
V3
R3
M3

BP5
BK3
BF3
BC3
AA3
U3
P3
L3

AY3
BA3

DDR_A_C LK0
DDR_A_C LK#0
DDR_A_C LK#1
DDR_A_C LK1

DDR_A_C KE0
DDR_A_C KE1

DDR_A_C S#0
DDR_A_C S#1

DDR_A_O DT0
DDR_A_O DT1

DDR_A_B A0
DDR_A_B A1
DDR_A_B G0

DDR_A_R AS#
DDR_A_W E#
DDR_A_C AS#

DDR_A_M A0
DDR_A_M A1
DDR_A_M A2
DDR_A_M A3
DDR_A_M A4
DDR_A_M A5
DDR_A_M A6
DDR_A_M A7
DDR_A_M A8
DDR_A_M A9
DDR_A_M A10
DDR_A_M A11
DDR_A_M A12
DDR_A_M A13
DDR_A_B G1
DDR_A_A CT#

DDR_A_D QS#0
DDR_A_D QS#1
DDR_A_D QS#2
DDR_A_D QS#3
DDR_A_D QS4
DDR_A_D QS5
DDR_A_D QS6
DDR_A_D QS7

DDR_A_D QS0
DDR_A_D QS1
DDR_A_D QS2
DDR_A_D QS3
DDR_A_D QS#4
DDR_A_D QS#5
DDR_A_D QS#6
DDR_A_D QS#7

DDR_A_C LK0 <20>
DDR_A_C LK#0 <20>
DDR_A_C LK#1 <20>
DDR_A_C LK1 <20>

DDR_A_C KE0 <20>
DDR_A_C KE1 <20>

DDR_A_C S#0 <20>
DDR_A_C S#1 <20>

DDR_A_O DT0 <20>
DDR_A_O DT1 <20>

DDR_A_B A0 <20>
DDR_A_B A1 <20>
DDR_A_B G0 <20>

DDR_A_R AS# <20>
DDR_A_W E# <20>
DDR_A_C AS# <20>

DDR_A_M A0 < 20>
DDR_A_M A1 < 20>
DDR_A_M A2 < 20>
DDR_A_M A3 < 20>
DDR_A_M A4 < 20>
DDR_A_M A5 < 20>
DDR_A_M A6 < 20>
DDR_A_M A7 < 20>
DDR_A_M A8 < 20>
DDR_A_M A9 < 20>
DDR_A_M A10 <20>
DDR_A_M A11 <20>
DDR_A_M A12 <20>
DDR_A_M A13 <20>
DDR_A_B G1 <20>
DDR_A_A CT# <20>

DDR_A_P AR <20>
DDR_A_A LERT# <20>

DDR_A_D QS#0 <20 >
DDR_A_D QS#1 <20 >
DDR_A_D QS#2 <20 >
DDR_A_D QS#3 <20 >
DDR_A_D QS4 <20>
DDR_A_D QS5 <20>
DDR_A_D QS6 <20>
DDR_A_D QS7 <20>

DDR_A_D QS0 <20>
DDR_A_D QS1 <20>
DDR_A_D QS2 <20>
DDR_A_D QS3 <20>
DDR_A_D QS#4 <20 >
DDR_A_D QS#5 <20 >
DDR_A_D QS#6 <20 >
DDR_A_D QS#7 <20 >

DDR CHANNEL A

SKL-H_BG A1440

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

For DFT ONLY

5

4

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1 OF 14

Compal Secret Data

Compal Secret Data

2015/08/ 10 2016/12/ 31

2015/08/ 10 2016/12/ 31

2015/08/ 10 2016/12/ 31

3

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date : Sheet o f

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

DDR4_CHA

DDR4_CHA

DDR4_CHA

LA-C951P

LA-C951P

LA-C951P

7 6 2Friday, August 14, 20 15

7 6 2Friday, August 14, 20 15

7 6 2Friday, August 14, 20 15

1

1.0

1.0

1.0

5

4

3

2

1

@

DDR_B_D [0..15]<21>

D D

DDR_B_D [16..31]<21>

DDR_B_D [32..47]<21>

C C

DDR_B_D [48..63]<21>

B B

DDR_B_D 0
DDR_B_D 1
DDR_B_D 2
DDR_B_D 3
DDR_B_D 4
DDR_B_D 5
DDR_B_D 6
DDR_B_D 7
DDR_B_D 8
DDR_B_D 9
DDR_B_D 10
DDR_B_D 11
DDR_B_D 12
DDR_B_D 13
DDR_B_D 14
DDR_B_D 15
DDR_B_D 16
DDR_B_D 17
DDR_B_D 18
DDR_B_D 19
DDR_B_D 20
DDR_B_D 21
DDR_B_D 22
DDR_B_D 23
DDR_B_D 24
DDR_B_D 25
DDR_B_D 26
DDR_B_D 27
DDR_B_D 28
DDR_B_D 29
DDR_B_D 30
DDR_B_D 31
DDR_B_D 32
DDR_B_D 33
DDR_B_D 34
DDR_B_D 35
DDR_B_D 36
DDR_B_D 37
DDR_B_D 38
DDR_B_D 39
DDR_B_D 40
DDR_B_D 41
DDR_B_D 42
DDR_B_D 43
DDR_B_D 44
DDR_B_D 45
DDR_B_D 46
DDR_B_D 47
DDR_B_D 48
DDR_B_D 49
DDR_B_D 50
DDR_B_D 51
DDR_B_D 52
DDR_B_D 53
DDR_B_D 54
DDR_B_D 55
DDR_B_D 56
DDR_B_D 57
DDR_B_D 58
DDR_B_D 59
DDR_B_D 60
DDR_B_D 61
DDR_B_D 62
DDR_B_D 63

DDR_RCO MP0
DDR_RCO MP1
DDR_RCO MP2

UC1B

BT11

DDR1_DQ[0]/DDR0_DQ[16]

BR11

DDR1_DQ[1]/DDR0_DQ[17]

BT8

DDR1_DQ[2]/DDR0_DQ[18]

BR8

DDR1_DQ[3]/DDR0_DQ[19]

BP11

DDR1_DQ[4]/DDR0_DQ[20]

BN11

DDR1_DQ[5]/DDR0_DQ[21]

BP8

DDR1_DQ[6]/DDR0_DQ[22]

BN8

DDR1_DQ[7]/DDR0_DQ[23]

BL12

DDR1_DQ[8]/DDR0_DQ[24]

BL11

DDR1_DQ[9]/DDR0_DQ[25]

BL8

DDR1_DQ[10]/DDR0_DQ[26]

BJ8

DDR1_DQ[11]/DDR0_DQ[27]

BJ11

DDR1_DQ[12]/DDR0_DQ[28]

BJ10

DDR1_DQ[13]/DDR0_DQ[29]

BL7

DDR1_DQ[14]/DDR0_DQ[30]

BJ7

DDR1_DQ[15]/DDR0_DQ[31]

BG11

DDR1_DQ[16]/DDR0_DQ[48]

BG10

DDR1_DQ[17]/DDR0_DQ[49]

BG8

DDR1_DQ[18]/DDR0_DQ[50]

BF8

DDR1_DQ[19]/DDR0_DQ[51]

BF11

DDR1_DQ[20]/DDR0_DQ[52]

BF10

DDR1_DQ[21]/DDR0_DQ[53]

BG7

DDR1_DQ[22]/DDR0_DQ[54]

BF7

DDR1_DQ[23]/DDR0_DQ[55]

BB11

DDR1_DQ[24]/DDR0_DQ[56]

BC11

DDR1_DQ[25]/DDR0_DQ[57]

BB8

DDR1_DQ[26]/DDR0_DQ[58]

BC8

DDR1_DQ[27]/DDR0_DQ[59]

BC10

DDR1_DQ[28]/DDR0_DQ[60]

BB10

DDR1_DQ[29]/DDR0_DQ[61]

BC7

DDR1_DQ[30]/DDR0_DQ[62]

BB7

DDR1_DQ[31]/DDR0_DQ[63]

AA11

DDR1_DQ[32]/DDR1_DQ[16]

AA10

DDR1_DQ[33]/DDR1_DQ[17]

AC11

DDR1_DQ[34]/DDR1_DQ[18]

AC10

DDR1_DQ[35]/DDR1_DQ[19]

AA7

DDR1_DQ[36]/DDR1_DQ[20]

AA8

DDR1_DQ[37]/DDR1_DQ[21]

AC8

DDR1_DQ[38]/DDR1_DQ[22]

AC7

DDR1_DQ[39]/DDR1_DQ[23]

W8

DDR1_DQ[40]/DDR1_DQ[24]

W7

DDR1_DQ[41]/DDR1_DQ[25]

V10

DDR1_DQ[42]/DDR1_DQ[26]

V11

DDR1_DQ[43]/DDR1_DQ[27]

W11

DDR1_DQ[44]/DDR1_DQ[28]

W10

DDR1_DQ[45]/DDR1_DQ[29]

V7

DDR1_DQ[46]/DDR1_DQ[30]

V8

DDR1_DQ[47]/DDR1_DQ[31]

R11

DDR1_DQ[48]

P11

DDR1_DQ[49]

P7

DDR1_DQ[50]

R8

DDR1_DQ[51]

R10

DDR1_DQ[52]

P10

DDR1_DQ[53]

R7

DDR1_DQ[54]

P8

DDR1_DQ[55]

L11

DDR1_DQ[56]

M11

DDR1_DQ[57]

L7

DDR1_DQ[58]

M8

DDR1_DQ[59]

L10

DDR1_DQ[60]

M10

DDR1_DQ[61]

M7

DDR1_DQ[62]

L8

DDR1_DQ[63]

AW11

DDR1_ECC[0]

AY11

DDR1_ECC[1]

AY8

DDR1_ECC[2]

AW8

DDR1_ECC[3]

AY10

DDR1_ECC[4]

AW10

DDR1_ECC[5]

AY7

DDR1_ECC[6]

AW7

DDR1_ECC[7]

G1

DDR_RCOMP[0]

H1

DDR_RCOMP[1]

J2

DDR_RCOMP[2]

SKL-H_BG A1440

DDR CHANNEL B

SKYLAKE_HA LO

BGA1440

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]
DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]
DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]

DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]
DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]

DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]
DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]
DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#

DDR1_DQSN[0]/DDR0_DQSN[2]
DDR1_DQSN[1]/DDR0_DQSN[3]
DDR1_DQSN[2]/DDR0_DQSN[6]
DDR1_DQSN[3]/DDR0_DQSN[7]
DDR1_DQSN[4]/DDR1_DQSN[2]
DDR1_DQSN[5]/DDR1_DQSN[3]

DDR1_DQSP[0]/DDR0_DQSP[2]
DDR1_DQSP[1]/DDR0_DQSP[3]
DDR1_DQSP[2]/DDR0_DQSP[6]
DDR1_DQSP[3]/DDR0_DQSP[7]
DDR1_DQSP[4]/DDR1_DQSP[2]
DDR1_DQSP[5]/DDR1_DQSP[3]

2 OF 14

DDR1_CKP[0]
DDR1_CKN[0]
DDR1_CKN[1]

DDR1_CKP[1]
DDR1_CLKP[2]
DDR1_CLKN[2]
DDR1_CLKP[3]
DDR1_CLKN[3]

DDR1_CKE[0]

DDR1_CKE[1]

DDR1_CKE[2]

DDR1_CKE[3]

DDR1_CS#[0]
DDR1_CS#[1]
DDR1_CS#[2]
DDR1_CS#[3]

DDR1_ODT[0]

DDR1_ODT[1]

DDR1_ODT[2]

DDR1_ODT[3]

DDR1_MA[3]
DDR1_MA[4]

DDR1_PAR

DDR1_ALERT#

DDR1_DQSN[6]
DDR1_DQSN[7]

DDR1_DQSP[6]
DDR1_DQSP[7]

DDR1_DQSP[8]
DDR1_DQSN[8]

DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ

DDR_B_C LK0

AM9

DDR_B_C LK#0

AN9

DDR_B_C LK#1

AM8

DDR_B_C LK1

AM7
AM11
AM10
AJ10
AJ11

DDR_B_C KE0

AT8

DDR_B_C KE1

AT10
AT7
AT11

DDR_B_C S#0

AF11

DDR_B_C S#1

AE7
AF10
AE10

DDR_B_O DT0

AF7

DDR_B_O DT1

AE8
AE9
AE11

DDR_B_R AS#

AH10

DDR_B_W E#

AH11

DDR_B_C AS#

AF8

DDR_B_B A0

AH8

DDR_B_B A1

AH9

DDR_B_B G0

AR9

DDR_B_M A0

AJ9

DDR_B_M A1

AK6

DDR_B_M A2

AK5

DDR_B_M A3

AL5

DDR_B_M A4

AL6

DDR_B_M A5

AM6

DDR_B_M A6

AN7

DDR_B_M A7

AN10

DDR_B_M A8

AN8

DDR_B_M A9

AR11

DDR_B_M A10

AH7

DDR_B_M A11

AN11

DDR_B_M A12

AR10

DDR_B_M A13

AF9

DDR_B_B G1

AR7

DDR_B_A CT#

AT9

AJ7
AR8

DDR_B_D QS#0

BP9

DDR_B_D QS#1

BL9

DDR_B_D QS#2

BG9

DDR_B_D QS#3

BC9

DDR_B_D QS#4

AC9

DDR_B_D QS#5

W9

DDR_B_D QS#6

R9

DDR_B_D QS#7

M9

DDR_B_D QS0

BR9

DDR_B_D QS1

BJ9

DDR_B_D QS2

BF9

DDR_B_D QS3

BB9

DDR_B_D QS4

AA9

DDR_B_D QS5

V9

DDR_B_D QS6

P9

DDR_B_D QS7

L9

AW9
AY9

BN13
BP13
BR13

Trace width/Spacing >= 20mils

+0.6V_VR EFCA
+0.6V_A_ VREFDQ
+0.6V_B_ VREFDQ

DDR_B_C LK0 <21>
DDR_B_C LK#0 <21>
DDR_B_C LK#1 <21>
DDR_B_C LK1 <21>

DDR_B_C KE0 <21>
DDR_B_C KE1 <21>

DDR_B_C S#0 <21>
DDR_B_C S#1 <21>

DDR_B_O DT0 <21>
DDR_B_O DT1 <21>

DDR_B_R AS# <21>
DDR_B_W E# <21>
DDR_B_C AS# <21>

DDR_B_B A0 <21>
DDR_B_B A1 <21>
DDR_B_B G0 <21>

DDR_B_M A0 < 21>
DDR_B_M A1 < 21>
DDR_B_M A2 < 21>
DDR_B_M A3 < 21>
DDR_B_M A4 < 21>
DDR_B_M A5 < 21>
DDR_B_M A6 < 21>
DDR_B_M A7 < 21>
DDR_B_M A8 < 21>
DDR_B_M A9 < 21>
DDR_B_M A10 <21>
DDR_B_M A11 <21>
DDR_B_M A12 <21>
DDR_B_M A13 <21>
DDR_B_B G1 <21>
DDR_B_A CT# <21>

DDR_B_P AR <21>
DDR_B_A LERT# <21>

DDR_B_D QS#0 <21 >
DDR_B_D QS#1 <21 >
DDR_B_D QS#2 <21 >
DDR_B_D QS#3 <21 >
DDR_B_D QS#4 <21 >
DDR_B_D QS#5 <21 >
DDR_B_D QS#6 <21 >
DDR_B_D QS#7 <21 >

DDR_B_D QS0 <21>
DDR_B_D QS1 <21>
DDR_B_D QS2 <21>
DDR_B_D QS3 <21>
DDR_B_D QS4 <21>
DDR_B_D QS5 <21>
DDR_B_D QS6 <21>
DDR_B_D QS7 <21>

+1.2V_VDDQ

@

+0.6V_A_ VREFDQ

@

@

R5

1 2

2_0402_ 1%

1

CC2

0.022U_0 402_25V7K

2

RC6

24.9_040 2_1%

1 2

Refer Doc.546884_SKL_H_PDG_Rev1_2_pub.
Figure 4-25

RC2

1K_0402 _1%

DDR4 COMPENSATION SIGNALS

DDR_RCO MP0

DDR_RCO MP1

DDR_RCO MP2

Note:
Trace width=12~15 mil, Spcing=20 mils
Max trace length= 500 mils

1 2

RC3 121_0402_ 1%

1 2

RC4 75_0402_1 %

1 2

RC5 100_0402_ 1%

RC1
1K_0402 _1%

1 2

@

1 2

@

CC1

0.1U_020 1_10V6K

2

@

1

A A

Security Classification

Security Classification

Security Classification

2015/08/ 10 2016/12/ 31

2015/08/ 10 2016/12/ 31

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

For DFT ONLY

5

4

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/08/ 10 2016/12/ 31

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date : Sheet o f

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

DDR4_CHB

DDR4_CHB

DDR4_CHB

LA-C951P

LA-C951P

LA-C951P

8 6 2Friday, August 14, 20 15

8 6 2Friday, August 14, 20 15

8 6 2Friday, August 14, 20 15

1

1.0

1.0

1.0

5

4

3

2

1

+VCC_CO RE +VCC_ CORE

AA13
AA31
AA32

D D

C C

B B

AA33
AA34
AA35
AA36
AA37
AA38
AB29
AB30
AB31
AB32
AB35
AB36
AB37
AB38
AC13
AC14
AC29
AC30
AC31
AC32
AC33
AC34
AC35
AC36
AD13
AD14
AD31
AD32
AD33
AD34
AD35
AD36
AD37
AD38
AE13
AE14
AE30
AE31
AE32
AE35
AE36
AE37
AE38
AF35
AF36
AF37
AF38

K13
K14
L13
N13
N14
N30
N31
N32
N35
N36
N37
N38
P13

SKYLAKE_HA LO

UC1G

@

BGA1440

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

SKL-H_BG A1440

7 OF 14

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

VCC_SENSE

VSS_SENSE

V32
V33
V34
V35
V36
V37
V38
W13
W14
W29
W30
W31
W32
W35
W36
W37
W38
Y29
Y30
Y31
Y32
Y33
Y34
Y35
Y36
L14
P29
P30
P31
P32
P33
P34
P35
P36
R13
R31
R32
R33
R34
R35
R36
R37
R38
T29
T30
T31
T32
T35
T36
T37
T38
U29
U30
U31
U32
U33
U34
U35
U36
V13
V14
V31
P14

AG37
AG38

+VCC_GT

@

SKYLAKE_HA LO

UC1H

BG34
BG35
BG36

BH33
BH34
BH35
BH36
BH37
BH38
BJ37
BJ38
BL36

BL37
BM36
BM37

BN36

BN37

BN38

BP37

BP38

BR37

BT37

BE38

BF13

BF14

BF29

BF30

BF31

BF32

BF35

BF36

BF37

BF38
BG29
BG30
BG31
BG32
BG33

BC36

BC37

BC38

BD13

BD14

BD29

BD30

BD31

BD32

BD33

BD34

BD35

BD36

BE31

BE32

BE37

VCCCORE _SENSE <54>

VSSCORE _SENSE <54 >

BGA1440

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

SKL-H_BG A1440

8 OF 14

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

AV29
AV30
AV31
AV32
AV33
AV34
AV35
AV36
AW14
AW31
AW32
AW33
AW34
AW35
AW36
AW37
AW38
AY29
AY30
AY31
AY32
AY35
AY36
AY37
AY38
BA13
BA14
BA29
BA30
BA31
BA32
BA33
BA34
BA35
BA36
BB13
BB14
BB31
BB32
BB33
BB34
BB35
BB36
BB37
BB38
BC29
BC30
BC31
BC32
BC35
BE33
BE34
BE35
BE36

+VCC_GT

+VCC_GT

AJ29
AJ30
AJ31
AJ32
AJ33
AJ34
AJ35

AJ36
AK31
AK32
AK33
AK34
AK35
AK36
AK37
AK38
AL13
AL29
AL30
AL31
AL32
AL35
AL36
AL37
AL38

AM13
AM14
AM29
AM30
AM31
AM32
AM33
AM34
AM35
AM36

AN13
AN14
AN31
AN32
AN33
AN34
AN35
AN36
AN37
AN38
AP13
AP14
AP29
AP30
AP31
AP32
AP35
AP36
AP37
AP38
AR29
AR30
AR31
AR32
AR33
AR34
AR35
AR36
AT14
AT31
AT32
AT33
AT34
AT35
AT36
AT37
AT38
AU14
AU29
AU30
AU31
AU32
AU35
AU36
AU37
AU38

@

UC1N

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

SKL-H_BG A1440

REV = 1

?

SKYLAKE_HA LO

BGA1440

14 OF 14

VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX

VCCGT_SENSE

VSSGTX_SENSE

VSSGT_SENSE

VCCGTX_SENSE

AF29
AF30
AF31
AF32
AF33
AF34
AG13
AG14
AG31
AG32
AG33
AG34
AG35
AG36
AH13
AH14
AH29
AH30
AH31
AH32
AJ13
AJ14

AH38
AH35
AH37
AH36

?

VCCGT_S ENSE <54>

VSSGT_S ENSE <54>

A A

Security Classification

Security Classification

Security Classification

2015/08/ 10 2016/12/ 31

2015/08/ 10 2016/12/ 31

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

For DFT ONLY

5

4

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/08/ 10 2016/12/ 31

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date : Sheet o f

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

VCC/VCCGT

VCC/VCCGT

VCC/VCCGT

LA-C951P

LA-C951P

LA-C951P

9 6 2Friday, August 14, 20 15

9 6 2Friday, August 14, 20 15

9 6 2Friday, August 14, 20 15

1

1.0

1.0

1.0

5

4

3

2

1

SKYLAKE_HA LO

UC1I

+VCCSA

D D

+VCCIO

C C

K29
K30
K31
K32
K33
K34
K35

M29
M30
M31
M32
M33
M34
M35
M36

AG12

G15
G17
G19
G21
H15
H16
H17
H19
H20
H21
H26
H27

J30

L31
L32
L35
L36
L37
L38

J15
J16
J17
J19
J20
J21
J26
J27

@

VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA

VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO

SKL-H_BG A1440

BGA1440

9 OF 14

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VDDQC

VCCPLL_OC
VCCPLL_OC

VCCST

VCCSTG

VCCSTG

VCCPLL
VCCPLL

VCCSA_SENSE

VSSSA_SENSE

VCCIO_SENSE

VSSIO_SENSE

AA6
AE12
AF5
AF6
AG5
AG9
AJ12
AL11
AP6
AP7
AR12
AR6
AT12
AW6
AY6
J5
J6
K12
K6
L12
L6
R6
T6
W6

Y12

BH13
G11

H30

H29

G30

H28
J28

M38
M37

H14
J14

+1.2V_CP U_VDDQ

+1.2V_VD DQC

2.8A

+1V_VCC ST

+1.2V_VC CPLL_OC

+1VS_VC CSTG

+1V_VCC ST

VCCSA_S ENSE <54>
VSSSA_S ENSE < 54>

+1.2V +1.2V_ CPU_VDDQ

RC83

@

1 2

0_0805_ 5%

RC189 0_0402_ 5%@

RC81

@

1 2

0_0603_ 5%

PLACE CAP BACKSIDE

1 2

PLACE CAP BACKSIDE

+1.2V_CPU_VDDQ

+1.2V_VD DQC+1.2V_CP U_VDDQ

2.8A

10U_0603_6.3V6M

CC58

2

1

+1.2V_VC CPLL_OC+1.2V_CP U_VDDQ

1U_0402_6.3V6K

1U_0402_6.3V6K

CC21

2

1

CC22

2

1

10U_0603_6.3V6M

2

1

CC23

22uF *4

CC45

+1.2V_CPU_VDDQ

10U_0603_6.3V6M

CC27

2

2

1

1

10U_0603_6.3V6M

CC28

@

10U_0603_6.3V6M

10U_0603_6.3V6M

CC30

CC29

2

2

1

1

10U_0603_6.3V6M

10U_0603_6.3V6M

CC32

CC31

2

2

1

1

10U_0603_6.3V6M

10U_0603_6.3V6M

CC34

CC33

2

2

@

@

1

1

10U_0603_6.3V6M

10U_0603_6.3V6M

CC36

CC35

2

2

@

@

1

1

B B

10U_0603_6.3V6M

10U_0603_6.3V6M

CC41

2

2

1

1

10U_0603_6.3V6M

10U_0603_6.3V6M

CC43

CC42

2

@

1

10U_0603_6.3V6M

CC40

2

1

CC39

2

@

1

10U_0603_6.3V6M

10U_0603_6.3V6M

CC38

2

2

1

1

+1VS_VC CSTG +1V_ VCCST+VCCIO

1U_0402_6.3V6K

1U_0402_6.3V6K

CC37

1U_0402_6.3V6K

2

1

CC47

CC46

2

2

@

1

1

1U_0402_6.3V6K

CC44

2

1

10U_0603_6.3V6M

10U_0603_6.3V6M

CC24

2

1

10U_0603_6.3V6M

CC25

2

1

CC26

2

1

PLACE CAP BACKSIDE

22uF*4/1 0uF*3

PLACE CAP BACKSIDE

A A

For DFT ONLY

5

PLACE CAP BACKSIDE

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/08/ 10 2016/12/ 31

2015/08/ 10 2016/12/ 31

2015/08/ 10 2016/12/ 31

3

10uF*10

PLACE CAP BACKSIDE

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date : Sheet o f

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

VDDQ/VCCSA/VCCIO

VDDQ/VCCSA/VCCIO

VDDQ/VCCSA/VCCIO

LA-C951P

LA-C951P

LA-C951P

10 62F riday, August 14, 2 015

10 62F riday, August 14, 2 015

10 62F riday, August 14, 2 015

1

1.0

1.0

1.0

5

CFG Straps for Processor

PEG Static Lane Reversal - CFG2 is for the 16x

D D

CFG2

Display Port Presence Strap

CFG4

C C

PCIE Port Bifurcation Straps

CFG[6:5 ]

B B

PEG DEFER TRAINING

CFG7

A A

1: Normal Operation; Lane # definition matches
socket pin map definition

0:Lane Reversed

*

CFG2

1 : Disabled; No Physical Display Port
attached to Embedded Display Port

0 : Enabled; An external Display Port device is
connected to the Embedded Display Port

*

1 2

CFG4

RC47 1K_040 2_5%

RC20

1K_0402_1%

1 2

check GPU PEG

11: (Default) x16 - Device 1 functions 1 and 2 disabled

10: x8, x8 - Device 1 function 1 enabled ; function 2
disabled

*

01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)

00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

CFG5

CFG6

RC56

RC58

@

1K_0402_1%

1: (Default) PEG Train immediately following xxRESETB
de assertion

*

1K_0402_1%

1 2

1 2

0: PEG Wait for BIOS for training

CFG7

RC40

@

1K_0402_1%

1 2

4

SM_PG_CTRL< 50>

H_CPUPWR GD<15>

100P_0402_5 0V8J

20141230, ESD require

+3VS

CRB

1 2

VR_SVID_ALERT#_R<54>
VR_SVID_SCLK_R<54>
VR_SVID_SDIO_R<54>

H_PROCHOT#_ EC<38,4 8>

EMI@

+1VS_VCCSTG

+1V_VCCST

RC55
330K_0402_5 %

SM_PG_CTRL

CC271

+1V_VCCST

RC53
100_0402_1 %

1 2

H_PROCHOT#_ EC

H_VCCST_PW RGD<38,45>

PLTRST_CPU #<14>

H_PM_SYNC<14>
H_PM_DOWN<14>

H_PECI<14,38>

THERMTRIP#_R<14>

H_SKTOCC#_R<14>

1

2

@

RC52
100K_0402_5 %

H_PROCHOT#_ EC

1 2

RC38 1K_0 402_5%

1 2

RH25 1K_0402_5 %

1 2

RC46 1K_0402_5 %

PCH_TRIGGER<19>

CPU_TRIGGER<19>

+3VALW

ORB

1 2

3

TC87 TP@

TC91 TP@
TC92 TP@

DDR_PG_CTR L

PCH_CPU_BCL K_P
PCH_CPU_BCL K_N

PCH_CPU_PCIBCL K_P
PCH_CPU_PCIBCL K_N

PCH_CPU_NSS C_P
PCH_CPU_NSS C_N

VR_SVID_ALERT#

VR_SVID_CLK
VR_SVID_DATA
H_PROCHOT#_ R

DDR_PG_CTR L

VCCST_PWRGD _CPUH_VCCST_PW RGD

H_PM_SYNC_R
H_PM_DOWN _R
H_PECI

THERMTRIP#

H_SKTOCC#H_SKT OCC#_R

PCH_CPU_BCLK_P<16>

PCH_CPU_BCL K_N<16>

PCH_CPU_PCIBCLK_P<16>

PCH_CPU_PCIBCL K_N<16>

PCH_CPU_NSSC_P< 16>

PCH_CPU_NSS C_N<16>

RC50
56_0402_5%

1 2

THERMTRIP#_R
H_VCCST_PW RGD

PCH_TRIGGER PCH_TRIGGER_R
CPU_TRIGGER CPU_TRIGGER_R

follow CRB "SKL_H_Mobile_RVP11_Rev0_7"

+1.2V_VDDQ

1 2

RC51 220 _0402_5%

1 2

RC49 0_0402_5%@

1 2

RC54 0_0402_5%@

1 2

RC39 499_0402_1%

1 2

RC48 60.4_04 02_1%

1 2

RH24 30_0402_ 5%

1 2

RC42 20_0402_ 5%

1 2

RC43 0_0402_5 %@

H_PECI 12.1ohm follow CRB RVP11_Rev0_7

1 2

RC57 0_0402_5 %@

1 2

RC44 0_0402_5 %@

1 2

RH14 30_0402_5%

1 2

RC80 30_0402_5%

CC11 0.1U_0201_10V6K@

12

UC2

5

VCC

4

Y

SN74AUP1G07DCK R SC70 5P

GND

1

NC

2

A

3

TC82

BN35

BN33
BL34

AE29
AA14

BR35
BR31
BH30

D1
E1
E3
E2

BR1
BT2

J24

H24

N29
R14

A36
A37

H23

J23

F30
E30

B30
C30

G3

J3

B31
A32

D35
C36

E31
D31

BH31
BH32
BH29
BR30

BT13

H13

BT31
BP35
BM34
BP31

BT34

J31

BR33

BN1

BM30

@

UC1K

RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP

RSVD_TP
RSVD_TP

RSVD

RSVD
RSVD
RSVD
RSVD

RSVD
RSVD
RSVD
RSVD

RSVD
RSVD

PROC_TRIGIN
PROC_TRIGOUT

RSVD
RSVD

RSVD
RSVD

RSVD
RSVD

RSVD
RSVD
RSVD

SKL-H_BGA1440

UC1E

@

BCLKP
BCLKN

PCI_BCLKP
PCI_BCLKN

CLK24P
CLK24N

VIDALERT#
VIDSCK
VIDSOUT
PROCHOT#

DDR_VTT_CNTL

VCCST_PWRGD

PROCPWRGD
RESET#
PM_SYNC
PM_DOWN
PECI
THERMTRIP#

SKTOCC#
PROC_SELECT#

CATERR#

SKL-H_BGA1440

SKYLAKE_HALO

BGA1440

SKYLAKE_HALO

BGA1440

11 OF 14

5 OF 14

2

PROC_TRST#

PROC_PREQ#

PROC_PRDY#

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]

CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]

CFG[17]
CFG[16]
CFG[19]
CFG[18]

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]

PROC_TDO

PROC_TDI

PROC_TMS

PROC_TCK

CFG_RCOMP

RSVD_TP
RSVD_TP

RSVD_TP
RSVD_TP

RSVD
RSVD

RSVD_TP
RSVD_TP

RSVD_TP
RSVD_TP

RSVD
RSVD

RSVD
RSVD

RSVD_TP
RSVD_TP

RSVD
RSVD
RSVD

NCTF
NCTF
NCTF
NCTF
NCTF
NCTF

BN25

CFG0

BN27

CFG1

BN26

CFG2

BN28

CFG3

BR20

CFG4

BM20

CFG5

BT20

CFG6

BP20

CFG7

BR23

CFG8

BR22

CFG9

BT23

CFG10

BT22

CFG11

BM19

CFG12

BR19

CFG13

BP19

CFG14

BT19

CFG15

BN23

CFG17

BP23

CFG16

BP22

CFG19

BN22

CFG18

BR27
BT27
BM31
BT30

BT28
BL32
BP28
BR28

CPU_XDP_TRST #

BP30

XDP_PREQ#

BL30

XDP_PRDY#

BP27

BT25

VSS

VSS

CPU_XDP_TDO
CPU_XDP_TDI
CPU_XDP_TMS
CPU_XDP_TCK0

CFG_RCOMP

BM33
BL33

BJ14
BJ13

BK28
BJ28

BJ18

BJ16
BK16

BK24
BJ24

BK21
BJ21

BT17
BR17

BK18

BJ34
BJ33

G13
AJ8
BL31

B2
B38
BP1
BR2
C1
C38

CFG0 <44 >
CFG1 <44 >
CFG2 <44 >
CFG3 <44 >
CFG4 <44 >
CFG5 <44 >
CFG6 <44 >
CFG7 <44 >
CFG8 <44 >
CFG9 <44 >
CFG10 <4 4>
CFG11 <4 4>
CFG12 <4 4>
CFG13 <4 4>
CFG14 <4 4>
CFG15 <4 4>

CFG17 <4 4>
CFG16 <4 4>
CFG19 <4 4>
CFG18 <4 4>

TC78TP@
TC79TP@
TC80TP@
TC81TP@

TC95TP@
TC96TP@

TC89TP@
TC90TP@

TC93TP@
TC97TP@

TC98TP@
TC99TP@

TC101TP@
TC103TP@

TC255TP@
TC256TP@

TC258TP@
TC259TP@
TC260TP@

CPU_XDP_TDO <15,44>
CPU_XDP_TDI <15,44>
CPU_XDP_TMS <1 5,44>
CPU_XDP_TCK0 <15,44>

CPU_XDP_TRST # <19,44>
XDP_PREQ# <1 9,44>
XDP_PRDY# <19,44>

12

RC45

49.9_0402_1%

1

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

For DFT ONLY

5

4

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2015/08/10 2016/12/31

2015/08/10 2016/12/31

2015/08/10 2016/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document N umber R ev

Size Document N umber R ev

Size Document N umber R ev

Custom

Custom

Custom

Date : Sh eet o f

Date : Sh eet o f

2

Date : Sh eet o f

Compal Electronics, Inc.

RSVD,CFG

RSVD,CFG

RSVD,CFG

LA-C951P

LA-C951P

LA-C951P

1

11 62Friday, August 14, 2015

11 62Friday, August 14, 2015

11 62Friday, August 14, 2015

1.0

1.0

1.0

5

SKYLAKE_HA LO

UC1F

Y38

VSS

Y37

VSS

Y14

VSS

Y13

VSS

D D

C C

B B

Y11
Y10

Y9
Y8

Y7
W34
W33
W12

W5
W4
W3
W2

W1
V30
V29
V12

V6
U38
U37

U6
T34
T33
T14
T13
T12
T11
T10

T9
T8
T7
T5
T4
T3
T2

T1
R30
R29
R12
P38
P37
P12

P6
N34
N33
N12
N11
N10

N9
N8
N7
N6
N5
N4
N3
N2

N1
M14
M13
M12

M6
L34
L33
L30
L29
K38
K11
K10

K9
K8
K7
K5
K4
K3
K2

SKL-H_BG A1440

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

BGA1440

6 OF 14

@

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

NCTFVSS

K1
J36
J33
J32
J25
J22
J18
J10
J7
J4
H35
H32
H25
H22
H18
H12
H11
G28
G26
G24
G23
G22
G20
G18
G16
G14
G12
G10
G9
G8
G6
G5
G4
F36
F31
F29
F27
F25
F23
F21
F19
F17
F15
F13
F11
F9
F8
F5
F4
F3
F2
E38
E35
E34
E9
E4
D33
D30
D28
D26
D24
D22
D20
D18
D16
D14
D12
D10
D9
D6
D3
C37
C31
C29
C27

D38

BT32
BT26
BT24
BT21
BT18
BT14
BT12

BR36
BR34
BR29
BR26
BR24
BR21
BR18
BR14
BR12

BR7
BP34
BP33
BP29
BP26
BP24
BP21
BP18
BP14
BP12

BP7
BN34
BN31
BN30
BN29
BN24
BN21
BN20
BN19
BN18
BN14
BN12

BN9

BN7

BN4

BN2

BM38
BM35
BM28
BM27
BM26
BM23
BM21
BM13
BM12

BM9

BM6

BM2

BL29
BK29
BK15
BK14

BJ32

BJ31

BJ25

BJ22
BH14
BH12

BH9
BH8
BH5
BH4

BH1
BG38
BG13
BG12
BF33
BF12
BE29

BE6

BD9
BC34
BC12
BB12

C17
C13

BT9
BT5

C9

SKYLAKE_HA LO

UC1L

BGA1440

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

SKL-H_BG A1440

4

@

12 OF 14

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

NCTFVSS
NCTFVSS
NCTFVSS
NCTFVSS
NCTFVSS
NCTFVSS

C25
C23
C21
C19
C15
C11
C8
C5
BM29
BM25
BM18
BM11
BM8
BM7
BM5
BM3
BL38
BL35
BL13
BL6
BK25
BK22
BK13
BK6
BJ30
BJ29
BJ15
BJ12
BH11
BH10
BH7
BH6
BH3
BH2
BG37
BG14
BG6
BF34
BF6
BE30
BE5
BE4
BE3
BE2
BE1
BD38
BD37
BD12
BD11
BD10
BD8
BD7
BD6
BC33
BC14
BC13
BC6
BB30
BB29
BB6
BB5

C2
BT36
BT35
BT4
BT3
BR38

3

SKYLAKE_HA LO

UC1M

BB4

VSS

BB3

VSS

BB2

VSS

BB1

VSS

BA38

VSS

BA37

VSS

BA12

VSS

BA11

VSS

BA10

VSS

BA9

VSS

BA8

VSS

BA7

VSS

BA6

VSS

B9

VSS

AY34

VSS

AY33

VSS

AY14

VSS

AY12

VSS

AW30

VSS

AW29

VSS

AW12

VSS

AW5

VSS

AW4

VSS

AW3

VSS

AW2

VSS

AW1

VSS

AV38

VSS

AV37

VSS

AU34

VSS

AU33

VSS

AU12

VSS

AU11

VSS

AU10

VSS

AU9

VSS

AU8

VSS

AU7

VSS

AU6

VSS

AT30

VSS

AT29

VSS

AT6

VSS

AR38

VSS

AR37

VSS

AR14

VSS

AR13

VSS

AR5

VSS

AR4

VSS

AR3

VSS

AR2

VSS

AR1

VSS

AP34

VSS

AP33

VSS

AP12

VSS

AP11

VSS

AP10

VSS

AP9

VSS

AP8

VSS

AN30

VSS

AN29

VSS

AN12

VSS

AN6

VSS

AN5

VSS

AM38

VSS

AM37

VSS

AM12

VSS

AM5

VSS

AM4

VSS

AM3

VSS

AM2

VSS

AM1

TC263TP@

TC264TP@

AL34
AL33
AL14
AL12
AL10

AL9
AL8
AL7
AL4

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

SKL-H_BG A1440

BGA1440

13 OF 14

@

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

NCTFVSS
NCTFVSS
NCTFVSS
NCTFVSS
NCTFVSS

AK30
AK29
AK4
AJ38
AJ37
AJ6
AJ5
AJ4
AJ3
AJ2
AJ1
AH34
AH33
AH12
AH6
AG30
AG29
AG11
AG10
AG8
AG7
AG6
AF14
AF13
AF12
AF4
AF3
AF2
AF1
AE34
AE33
AE6
AD30
AD29
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AC38
AC37
AC12
AC6
AC5
AC4
AC3
AC2
AC1
AB34
AB33
AB6
AA30
AA29
AA12
A30
A28
A26
A24
A22
A20
A18
A16
A14
A12
A10
A9
A6

B37
B3
A34
A4
A3

2

For 4+4e

For 4+4e
EDRAM VR

For 4+4e

For 4+4e EOPIO VR

For EDRAM VR
For EOPIO VR

For OPC

BJ17
BJ19
BJ20
BK17
BK19
BK20
BL16
BL17
BL18
BL19
BL20
BL21

BM17

BN17

BJ23
BJ26
BJ27
BK23
BK26
BK27
BL23
BL24
BL25
BL26
BL27
BL28

BM24

BL15

BM16

BL22

BM22

BP15
BR15
BT15

BP16
BR16
BT16

BN15

BM15

BP17
BN16

BM14

BL14

BJ35
BJ36

AT13

AW13

AU13
AY13

BT29
BR25
BP25

SKL-H_BG A1440@

SKYLAKE_HA LO

UC1J

BGA1440

VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

VCCOPC_SENSE
VSSOPC_SENSE

RSVD
RSVD

VCCEOPIO
VCCEOPIO
VCCEOPIO

RSVD
RSVD
RSVD

VCCEOPIO_SENSE
VSSEOPIO_SENSE

RSVD
RSVD

VCC_OPC_1P8
VCC_OPC_1P8

RSVD
RSVD

ZVM#
MSM#

ZVM2#
MSM2#

OPC_RCOMP
OPCE_RCOMP
OPCE_RCOMP2

1

10 OF 14

A A

Security Classification

Security Classification

Security Classification

2015/08/ 10 2016/12/ 31

2015/08/ 10 2016/12/ 31

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

For DFT ONLY

5

4

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/08/ 10 2016/12/ 31

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date : Sheet o f

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

VSS/VCCOPC

VSS/VCCOPC

VSS/VCCOPC

LA-C951P

LA-C951P

LA-C951P

12 62F riday, August 14, 2 015

12 62F riday, August 14, 2 015

12 62F riday, August 14, 2 015

1

1.0

1.0

1.0

5

4

3

2

1

DMI_CTX_PRX_N0
DMI_CTX_PRX_P0
DMI_CRX_PTX_N0
DMI_CRX_PTX_P0

PCIE_RCOMPN

DMI_CTX_PRX_N1
DMI_CTX_PRX_P1
DMI_CRX_PTX_N1
DMI_CRX_PTX_P1
DMI_CTX_PRX_N2
DMI_CTX_PRX_P2
DMI_CRX_PTX_N2
DMI_CRX_PTX_P2
DMI_CTX_PRX_N3
DMI_CTX_PRX_P3
DMI_CRX_PTX_N3
DMI_CRX_PTX_P3

PCIE_RCOMPP

PCIE_PTX_DRX_N6
PCIE_PTX_DRX_P6

DMI_CRX_PTX_P[0..3]<6>
DMI_CRX_PTX_N[0..3]<6>

D D

PCIE_PRX_DTX_N6< 34>

C C

B B

WLAN(NG FF)

PCIE_PRX_DTX_P6<34>
PCIE_PTX_C_DRX_N6<34>
PCIE_PTX_C_DRX_P6<34 >

DMI_CTX_PRX_P[0..3] <6 >

DMI_CTX_PRX_N[0..3] <6>

CH1 0.1U_0201_10V6K
CH2 0.1U_0201_10V6K

USB2/3 IO (MB)

USB2/3 IO (MB)

1 2
1 2

1 2

RH18

100_0402_1 %

USB3_TX3_P<43>

USB3_TX3_N<43>
USB3_RX3_P<43>
USB3_RX3_N<43>

USB3_TX4_P<43>

USB3_TX4_N<43>
USB3_RX4_P<43>
USB3_RX4_N<43>

UH1B

L27

DMI_RXN0

N27

DMI_RXP0

C27

DMI_TXN0

B27

DMI_TXP0

E24

DMI_RXN1

G24

DMI_RXP1

B28

DMI_TXN1

A28

DMI_TXP1

G27

DMI_RXN2

E26

DMI_RXP2

B29

DMI_TXN2

C29

DMI_TXP2

L29

DMI_RXN3

K29

DMI_RXP3

B30

DMI_TXN3

A30

DMI_TXP3

B18

PCIE_RCOMPN

C17

PCIE_RCOMPP

H15

PCIE1_RXN/USB3_7_RXN

G15

PCIE1_RXP/USB3_7_RXP

A16

PCIE1_TXN/USB3_7_TXN

B16

PCIE1_TXP/USB3_7_TXP

B19

PCIE2_TXN/USB3_8_TXN

C19

PCIE2_TXP/USB3_8_TXP

E17

PCIE2_RXN/USB3_8_RXN

G17

PCIE2_RXP/USB3_8_RXP

L17

PCIE3_RXN/USB3_9_RXN

K17

PCIE3_RXP/USB3_9_RXP

B20

PCIE3_TXN/USB3_9_TXN

C20

PCIE3_TXP/USB3_9_TXP

E20

PCIE4_RXN/USB3_10_RXN

G19

PCIE4_RXP/USB3_10_RXP

B21

PCIE4_TXN/USB3_10_TXN

A21

PCIE4_TXP/USB3_10_TXP

K19

PCIE5_RXN

L19

PCIE5_RXP

D22

PCIE5_TXN

C22

PCIE5_TXP

G22

PCIE6_RXN

E22

PCIE6_RXP

B22

PCIE6_TXN

A23

PCIE6_TXP

L22

PCIE7_RXN

K22

PCIE7_RXP

C23

PCIE7_TXN

B23

PCIE7_TXP

K24

PCIE8_RXN

L24

PCIE8_RXP

C24

PCIE8_TXN

B24

PCIE8_TXP

SKL-H-PCH_BGA837 @

UH1F

C11

USB3_1_TXN

B11

USB3_1_TXP

B7

USB3_1_RXN

A7

USB3_1_RXP

B12

USB3_2_TXN/SSIC_1_TXN

A12

USB3_2_TXP/SSIC_1_TXP

C8

USB3_2_RXN/SSIC_1_RXN

B8

USB3_2_RXP/SSIC_1_RXP

B15

USB3_6_TXN

C15

USB3_6_TXP

K15

USB3_6_RXN

K13

USB3_6_RXP

B14

USB3_5_TXN

C14

USB3_5_TXP

G13

USB3_5_RXN

H13

USB3_5_RXP

D13

USB3_3_TXP/SSIC_2_TXP

C13

USB3_3_TXN/SSIC_2_TXN

A9

USB3_3_RXP/SSIC_2_RXP

B10

USB3_3_RXN/SSIC_2_RXN

B13

USB3_4_TXP

A14

USB3_4_TXN

G11

USB3_4_RXP

E11

USB3_4_RXN

SKL-H-PCH_BGA837 @

SPT-H_PCH

DMI

PCIe/USB 3

2 OF 12 REV = 1.3

SPT-H_PCH

LPC/eSPI

USB

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

SATA

6 OF 12 REV = 1.3

USB2N_1
USB2P_1
USB2N_2
USB2P_2
USB2N_3
USB2P_3
USB2N_4
USB2P_4
USB2N_5
USB2P_5
USB2N_6
USB2P_6

USB 2.0

GPP_A5/LFRAME#/ESPI_CS0#

GPP_A6/SERIRQ/ESPI_CS1#

GPP_A7/PIRQA#/ESPI_ALERT0#

GPP_A0/RCIN#/ESPI_ALERT1#

USB2N_7
USB2P_7
USB2N_8
USB2P_8
USB2N_9

USB2P_9
USB2N_10
USB2P_10
USB2N_11
USB2P_11
USB2N_12
USB2P_12
USB2N_13
USB2P_13
USB2N_14
USB2P_14

GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#

GPP_F15/USB2_OCB_4
GPP_F16/USB2_OCB_5
GPP_F17/USB2_OCB_6
GPP_F18/USB2_OCB_7

USB2_COMP

USB2_VBUSSENSE

RSVD_AB13

USB2_ID

GPD7/RSVD

GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3

GPP_A10/CLKOUT_LPC1

GPP_G19/SMI#
GPP_G18/NMI#

GPP_E6/DEVSLP2
GPP_E5/DEVSLP1
GPP_E4/DEVSLP0

GPP_F9/DEVSLP7
GPP_F8/DEVSLP6
GPP_F7/DEVSLP5
GPP_F6/DEVSLP4
GPP_F5/DEVSLP3

AF5
AG7
AD5
AD7
AG8
AG10
AE1
AE2
AC2
AC3
AF2
AF3
AB3
AB2
AL8
AL7
AA1
AA2
AJ8
AJ7
W2
W3
AD3
AD2
V2
V1
AJ11
AJ13

AD43
AD42
AD39
AC44
Y43
Y41
W44
W43

USB2_COMP

AG3

USB2_VBUSSENSE

AD10
AB13

USB2_ID

AG2

BD14

AT22
AV22
AT19
BD16

BE16
BA17
AW17
AT17
BC18

BC17
AV19

M45

NMI_SMI_DBG#

N43

AE45
AG43
AG42
AB39
AB36
AB43
AB42
AB41

USB_OC0#

GPP_E10
USB_OC2#
GPP_E12

GPO

LPC_FRAME#

PIRQA#
KB_RST#

CK_LPC0
CK_LPC1

USB20_N1 <43>
USB20_P1 <4 3>
USB20_N2 <43>
USB20_P2 <4 3>

USB20_N4 <34>
USB20_P4 <3 4>

USB20_N6 <43>
USB20_P6 <4 3>

USB20_N8 <33>
USB20_P8 <3 3>

USB_OC0# <43>

USB_OC2# <43>

1 2

RH19 113_0402_1%

RH48 1K_0402_5%

TC191TP@

RH53 0_0402_5 %@

TC197TP@

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

SERIRQ

TC221TP@

RH62 22_040 2_5%
RH7 2 2_0402_5%

TC223TP@
TC224TP@

DEVSLP0 < 42>

USB3/2 port3, port4

12

12

LPC_AD0 <38,39>
LPC_AD1 <38,39>
LPC_AD2 <38,39>
LPC_AD3 <38,39>

LPC_FRAME# <38,39>

SERIRQ <38,39>

KB_RST# <17,38>

1 2
1 2

Left USB2/3 IO (MB)

Left USB2/3 IO (MB)

BT (NGFF)

Right USB2.0 (IO/B)

Cam era

Note :
50ohm single-ended and as sho rt as possible,

Spacing=15mils
Max length= 1000 mi ls.

CK_LPC_KBC <38>
CK_LPC_TCM <39>

GPP_E12
GPP_E10
USB_OC0#
USB_OC2#

NMI_SMI_DBG#

PIRQA#

SERIRQ

@RF@

1 8
2 7
3 6
4 5

RP22 10K_0804_8P4 R_5%

1 2

RH63 100K_0402_5%

RH59 10K_0402_5%

10K_0402_5%

12

CK_LPC_TCMCK_LPC_KBC

CH277
22P_0402_50 V8J

Close UH1

SIV RF request (150416)

@RF@

12

RH58

+3V_PCH

+3VALW

+3VS

CH278
22P_0402_50 V8J

USB2.0

Port

1

Left USB3.0

Left USB3.0

32

5

64

7

Right USB2.0BT (NGFF)

8

Came ra

Flexible I/O Capable Ports

16

12

HSIO Port

USB 3.0

A A

3

3

USB3 .0_ 14USB3 .0_ 2

PCIe

SATA

~~~

4

6

WLA N

1

HDD( SSD )

Card Read er LAN

1817

1211

NGFF (SSD )

NGFF (SSD )

NGFF (SSD ) NGFF(SS D)NGFF (SSD )

0

141 3

For DFT ONLY

5

4

212019

22

15

16

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2015/08/10 2016/12/31

2015/08/10 2016/12/31

2015/08/10 2016/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document N umber R ev

Size Document N umber R ev

Size Document N umber R ev

Custom

Custom

Custom

Date : Sh eet o f

Date : Sh eet o f

2

Date : Sh eet o f

Compal Electronics, Inc.

DMI,USB,PCIE,LPC

DMI,USB,PCIE,LPC

DMI,USB,PCIE,LPC

LA-C951P

LA-C951P

LA-C951P

1

13 62Friday, August 14, 2015

13 62Friday, August 14, 2015

13 62Friday, August 14, 2015

1.0

1.0

1.0

5

4

3

2

1

UH1C

AV2

CL_CLK

AV3

CL_DATA

AW2

CL_RST#

R44

GPP_G8/FAN_PWM_0

R43

GPP_G9/FAN_PWM_1

U39

GPP_G10/FAN_PWM_2

12

R74
100K_0402_5 %

N42

GPP_G11/FAN_PWM_3

U43

GPP_G0/FAN_TACH_0

U42

GPP_G1/FAN_TACH_1

U41

GPP_G2/FAN_TACH_2

M44

GPP_G3/FAN_TACH_3

U36

GPP_G4/FAN_TACH_4

P44

GPP_G5/FAN_TACH_5

T45

GPP_G6/FAN_TACH_6

T44

GPP_G7/FAN_TACH_7

B33

PCIE11_TXP

C33

PCIE11_TXN

K31

PCIE11_RXP

L31

PCIE11_RXN

AB33

GPP_F10/SCLOCK

AB35

GPP_F11/SLOAD

AA44

GPP_F13/SDATAOUT0

AA45

GPP_F12/SDATAOUT1

B38

PCIE14_TXN/SATA1B_TXN

C38

PCIE14_TXP/SATA1B_TXP

D39

PCIE14_RXN/SATA1B_RXN

E37

PCIE14_RXP/SATA1B_RXP

C36

PCIE13_TXN/SATA0B_TXN

B36

PCIE13_TXP/SATA0B_TXP

G35

PCIE13_RXN/SATA0B_RXN

E35

PCIE13_RXP/SATA0B_RXP

A35

PCIE12_TXP

B35

PCIE12_TXN

H33

PCIE12_RXP

G33

PCIE12_RXN

J45

PCIE20_TXP/SATA7_TXP

K44

PCIE20_TXN/SATA7_TXN

N38

PCIE20_RXP/SATA7_RXP

N39

PCIE20_RXN/SATA7_RXN

H44

PCIE19_TXP/SATA6_TXP

H43

PCIE19_TXN/SATA6_TXN

L39

PCIE19_RXP/SATA6_RXP

L37

PCIE19_RXN/SATA6_RXN

SKL-H-PCH_BGA837 @

AW4

AY2
AV4
BA4

BD7

SKL-H-PCH_BGA837 @

UH1E

GPP_I0/DDPB_HPD0
GPP_I1/DDPC_HPD1
GPP_I2/DDPD_HPD2
GPP_I3/DDPE_HPD3

GPP_I4/EDP_HPD

D D

EC_SCI#<38>

1 2

PCIE_PTX_C_DRX_P11<35>

Card Reader

SSD

LAN

C C

B B

PCIE_PTX_C_DRX_N11<35>
PCIE_PRX_DTX_P11<35>
PCIE_PRX_DTX_N11<35>

PCIE_PTX_C_DRX_N14<42>
PCIE_PTX_C_DRX_P14<42>
PCIE_PRX_DTX_N14<42>
PCIE_PRX_DTX_P14<42>

SATAB_PTX_C_DRX_N0<42>

SATAB_PTX_C_DRX_P0<42>

SATAB_PRX_DTX_N0<4 2>
SATAB_PRX_DTX_P0< 42>

PCIE_PTX_C_DRX_P12<36>
PCIE_PTX_C_DRX_N12<36>

PCIE_PRX_DTX_P12<36>
PCIE_PRX_DTX_N12<36>

CH4 0.1U_0201_10V6K

1 2

CH3 0.1U_0201_10V6K

1 2

CH9 0.22U_ 0402_10V6K

1 2

CH10 0.22U _0402_10V6K

1 2

CH7 0.22U_ 0402_10V6K

1 2

CH8 0.22U_ 0402_10V6K

1 2

CH6 0.1U_0201_10V6K

1 2

CH5 0.1U_0201_10V6K

TMDS_B_HPD#<32>

EDP_HPD<33>

EC_SCI#

PCIE_PTX_DRX_P11
PCIE_PTX_DRX_N11

PCIE_PTX_DRX_N14
PCIE_PTX_DRX_P14

PCIE_PRX_DTX_N14
PCIE_PRX_DTX_P14

SATAB_PTX_DRX_N0
SATAB_PTX_DRX_P0

SATAB_PRX_DTX_N0
SATAB_PRX_DTX_P0

PCIE_PTX_DRX_P12
PCIE_PTX_DRX_N12

TMDS_B_HPD#

SPT-H_PCH

CLINK

FAN

HOST

3 OF 12 REV = 1.3

SPT-H_PCH

GPP_I10/DDPD_CTRLDATA

5 OF 12 REV = 1.3

PCIE9_RXN/SATA0A_RXN

PCIE9_RXP/SATA0A_RXP
PCIE9_TXN/SATA0A_TXN
PCIE9_TXP/SATA0A_TXP

PCIE10_RXN/SATA1A_RXN
PCIE10_RXP/SATA1A_RXP

PCIE10_TXN/SATA1A_TXN
PCIE10_TXP/SATA1A_TXP

PCIE15_RXN/SATA2_RXN
PCIE15_RXP/SATA2_RXP

PCIE15_TXN/SATA2_TXN
PCIE15_TXP/SATA2_TXP

PCIe/SATA

PCIE16_RXN/SATA3_RXN
PCIE16_RXP/SATA3_RXP

PCIE16_TXN/SATA3_TXN
PCIE16_TXP/SATA3_TXP

PCIE17_RXN/SATA4_RXN
PCIE17_RXP/SATA4_RXP

PCIE17_TXN/SATA4_TXN
PCIE17_TXP/SATA4_TXP

PCIE18_RXN/SATA5_RXN
PCIE18_RXP/SATA5_RXP

PCIE18_TXN/SATA5_TXN
PCIE18_TXP/SATA5_TXP

GPP_E8/SATALED#
GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2
GPP_F0/SATAXPCIE3/SATAGP3
GPP_F1/SATAXPCIE4/SATAGP4
GPP_F2/SATAXPCIE5/SATAGP5
GPP_F3/SATAXPCIE6/SATAGP6
GPP_F4/SATAXPCIE7/SATAGP7

GPP_F21/EDP_BKLTCTL

GPP_F20/EDP_BKLTEN

GPP_F19/EDP_VDDEN

THERMTRIP#

PLTRST_PROC#

PM_DOWN

GPP_I7/DDPC_CTRLCLK

GPP_I8/DDPC_CTRLDATA

GPP_I5/DDPB_CTRLCLK

GPP_I6/DDPB_CTRLDATA

GPP_I9/DDPD_CTRLCLK

GPP_F14
GPP_F23
GPP_F22
GPP_G23
GPP_G22
GPP_G21
GPP_G20
GPP_H23

PECI

PM_SYNC

BB3
BD6
BA5
BC4
BE5
BE6

Y44
V44
W39
L43
L44
U35
R35
BD36

G31
H31
C31
B31

G29
E29
C32
B32

F41
E41

PCIE_PTX_DRX_N15

B39

PCIE_PTX_DRX_P15

A39

D43
E42

PCIE_PTX_DRX_N16

A41

PCIE_PTX_DRX_P16

A40

H42
H40
E45
F45

K37
G37
G45
G44

AD44
AG36
AG35
AG39
AD35
AD31
AD38
AC43
AB44

W36
W35
W42

H_THERMTR IP#

AJ3
AL3
AJ4
AK2
AH2

PCH_SATALED#
SATA_GP0
SATA_GP1
SATA_GP2
SATA_GP3

PCH_PWM

ENBKL
PCH_ENVDD

H_PECI_R

H_PM_SYNC

H_PM_DOWN

SATA_PRX_DTX_N1 <42 >
SATA_PRX_DTX_P1 <42>
SATA_PTX_DRX_N1 <42 >
SATA_PTX_DRX_P1 <42>

12

CH350.22U_0402_1 0V6K

12

CH130.22U_0402_1 0V6K

12

CH120.22U_0402_1 0V6K

12

CH110.22U_0402_1 0V6K

PCH_SATALED# <17,41,42>

SATA_GP0 <42>

PCH_PWM <33>
ENBKL <33,38>
PCH_ENVDD <33 >

1 2

RH23 604_0402_1%

1 2

RC41 12.1_0402_1%

H_PM_SYNC <11>
PLTRST_CPU # <11>

H_PM_DOWN <11>

HDMICLK_NB <32>
HDMIDAT_NB <32>

H_SKTOCC#_R <11>

HDD

PCIE_PRX_DTX_N15 <42>
PCIE_PRX_DTX_P15 <42>
PCIE_PTX_C_DRX_N15 <4 2>
PCIE_PTX_C_DRX_P15 <42>

PCIE_PRX_DTX_N16 <42>
PCIE_PRX_DTX_P16 <42>
PCIE_PTX_C_DRX_N16 <4 2>
PCIE_PTX_C_DRX_P16 <42>

THERMTRIP#_R <11>
H_PECI <11,38>

SATA_GP0
SATA_GP1
SATA_GP2
SATA_GP3

EC_SCI#

SSD

RPH3

4 5
3 6
2 7
1 8

10K_0804_8P 4R_5%

1 2

+3VS

RH1010K_ 0402_5%

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

For DFT ONLY

5

4

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2015/08/10 2016/12/31

2015/08/10 2016/12/31

2015/08/10 2016/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document N umber R ev

Size Document N umber R ev

Size Document N umber R ev

Custom

Custom

Custom

Date : Sh eet o f

Date : Sh eet o f

2

Date : Sh eet o f

Compal Electronics, Inc.

SATA,GPIO

SATA,GPIO

SATA,GPIO

LA-C951P

LA-C951P

LA-C951P

1

14 62Friday, August 14, 2015

14 62Friday, August 14, 2015

14 62Friday, August 14, 2015

1.0

1.0

1.0

5

RPC7

EMI@

HDA_SDOUT_AUDIO<37>

HDA_SYNC_AUDIO<37>
HDA_RST_AUDIO#<37>

HDA_BITCLK_AUDIO<37>

D D

Note: +RTCVCC
Need to check with PWR up date

+RTCVCC

RH37 20K_0402_5%

RH39 20K_0402_5%

C C

13

D

S

ESD@

100P_0402_5 0V8J

B B

20141230, ESD require

ESD@

100P_0402_5 0V8J

20141230, ESD require

ESD@

100P_0402_5 0V8J

20141230, ESD require

@EMI@

68P_0402_50 V8J

ME_EN<38>

12

CH14

1U_0402_6.3V6K

1 2

1 2

1U_0402_6.3V6K

QH3 SSM3K7002BFU_SC7 0-3

2

G

CH274

CH275

CH276

12

CH15

EC_CLEAR_CMOS

SYS_PWROK

1

2

EC_RSMRST#

1

2

PCH_PWROK

1

2

1 8
2 7
3 6
4 5

1

CH27

2

1 2

RC78 0_0402_5 %

Footprint have -NPM

CLRP1

SHORT PADS

OPEN

12

SHORT

mask

PCH_SRTCRS T#

PCH_RTCRST #

CLRP2

SHORT PADS

12

OPEN

SHORT

PCH_RTCRST #

12

RH320_0402_5% @

12

RH3310K_ 0402_5%

1205 add
1217 Q12 RH61 pop

33_0804_8P4 R_5%

CLRP1

SAVE ME RTC REGISTER

CLEAR ME RTC REGIST ER

CLRP2

SAVE CMOS

CLEAR CMOS

need confirm in SIV1

HDA_SDOUT
HDA_SYNC
HDA_RST#
HDA_BIT_CLK

EC_CLEAR_CMOS <38>

+3V_PCH

+3VS

4

HDA_SDIN0<37>

CPU_DISPA_SDO_R< 6>
CPU_DISPA_SDI_R<6>
CPU_DISPA_BCLK_R<6>

EC_RSMRST#

1 2

R243 100K_0402_ 5%

for doc.546765

1 2

RH85 150 K_0402_1%@

RH104 4.7K_0402_5%

1 2

RP25

@

1 8
2 7
3 6
4 5

4.7K_0804_8P4 R_5%

20141217

RP26

1 8
2 7
3 6
4 5

4.7K_0804_8P4 R_5%

RH64 499_0402_1 %

RH65 499_0402_1 %

RH41 8.2K_0402_ 5%

12

12

1 2

PCH_PWROK<38>

EC_RSMRST#<38>

RH36 0_0402_5 %@

PM_CLKRUN#

1 2

PBTN_OUT#

SML1_ALERT#

SMBALERT#

SMBCLK
SMBDATA
SML1CLK
SML1DATA

EC_SMB_DA2
EC_SMB_CK2

PCH_SMB_CLK

PCH_SMB_DATA

SML0CLK

SML0DATA

1 2

RH29

30_0402_1%

1 2

RH30

30_0402_1%

TC210 TP@

TC211 TP@

HDA_BIT_CLK
HDA_RST#
HDA_SDIN0

HDA_SDOUT
HDA_SYNC

CPU_DISPA_SDO
CPU_DISPA_SDI_R
CPU_DISPA_BCLK

PCH_RTCRST #
PCH_SRTCRS T#

PCH_PWROK

EC_RSMRST#

DPWROK_EC_ R

SMBALERT#
SMBCLK
SMBDATA

SML0_ALERT#

SML1_ALERT#

SML0CLK
SML0DATA

SML1CLK
SML1DATA

PCH

PCH

3

UH1D

BA9

HDA_BCLK

BD8

HDA_RST#

BE7

HDA_SDI0

BC8

HDA_SDI1

BB7

HDA_SDO

BD9

HDA_SYNC

BD1

RSVD_BD1

BE2

RSVD_BE2

AM1

DISPA_SDO

AN2

DISPA_SDI

AM2

DISPA_BCLK

AL42

GPP_D8/I2S0_SCLK

AN42

GPP_D7/I2S0_RXD

AM43

GPP_D6/I2S0_TXD

AJ33

GPP_D5/I2S0_SFRM

AH44

GPP_D20/DMIC_DATA0

AJ35

GPP_D19/DMIC_CLK0

AJ38

GPP_D18/DMIC_DATA1

AJ42

GPP_D17/DMIC_CLK1

BC10

RTCRST#

BB10

SRTCRST#

AW11

PCH_PWROK

BA11

RSMRST#

AV11

DSW_PWROK

BB41

GPP_C2/SMBALERT#

AW44

GPP_C0/SMBCLK

BB43

GPP_C1/SMBDATA

BA40

GPP_C5/SML0ALERT#

AY44

GPP_C3/SML0CLK

BB39

GPP_C4/SML0DATA

AT27

GPP_B23/SML1ALERT#/PCHHOT#

AW42

GPP_C6/SML1CLK

AW45

GPP_C7/SML1DATA

SKL-H-PCH_BGA837 @

SMBCLK

ME2N7002D1K W-G 2N SOT363-6
QH1A

@

SMBDATA

SML1CLK

ME2N7002D1K W-G 2N SOT363-6
QH2A

SML1DATA

2

6 1

3 4

ME2N7002D1K W-G 2N SOT363-6
QH1B

@

+3VS

2

6 1

@

3 4

ME2N7002D1K W-G 2N SOT363-6
QH2B

AUDIO

+3VS

SPT-H_PCH

GPP_A12/BMBUSY#/ISH_GP6/SX_EXIT_HOLDOFF#

GPP_A13/SUSWARN#/SUSPWRDNACK

SMBUS

JTAG

4 OF 12 REV = 1.3

GPP_A8/CLKRUN#

GPD11/LANPHYPC

GPD9/SLP_WLAN#

DRAM_RESET#

GPP_B2/VRALERT#

GPP_G17/ADR_COMPLETE

SYS_PWROK

GPD6/SLP_A#

GPP_B12/SLP_S0#

GPD4/SLP_S3#
GPD5/SLP_S4#

GPD10/SLP_S5#

GPD8/SUSCLK

GPD0/BATLOW#

GPP_A15/SUSACK#

GPD2/LAN_WAKE#

GPD1/ACPRESENT

GPD3/PWRBTN#

SYS_RESET#

GPP_B14/SPKR

PROCPWRGD

2

GPP_B1
GPP_B0

GPP_B11

WAKE#

SLP_LAN#

SLP_SUS#

ITP_PMODE

JTAGX
JTAG_TMS
JTAG_TDO

JTAG_TDI

JTAG_TCK

BB17
AW22

AR15

AV13

BC14
BD23
AL27
AR27
N44
AN24
AY1

BC13
BC15
AV15
BC26
AW15
BD15
BA13

AN15
BD13
BB19
BD19

BD11
BB15
BB13
AT13
AW1
BD26
AM3

AT2
AR3
AR2
AP1
AP2
AN3

PM_CLKRUN#

DDR_DRAMRST#
CPU_VRALERT#

SYS_PWROK

WAKE#

PM_SLP_S0#
PM_SLP_S3#
PM_SLP_S4#
PM_SLP_S5#

SUSCLK
BATLOW#
SUSACK#
SUSWARN#

PCH_LAN_WAKE#
AC_PRESENT_R

SLP_SUS#
PBTN_OUT#

XDP_ITP_PMODE
CPU_XDP_TCK0
CPU_XDP_TMS
CPU_XDP_TDO
CPU_XDP_TDI
PCH_JTAG_TCK1

DDR_DRAMRST# < 20>

MPHY_EXT_PWR_ GATE <38,45 >

SYS_PWROK <38>

TC262TP@

TC214TP@

PM_SLP_S3# <38,45,57 >
PM_SLP_S4# <38,45,50 >

TC206TP@

SUSCLK <3 4>

TC207TP@

TC208TP@

TC209TP@

PBTN_OUT# <38>

HDA_SPKR <17,37>
H_CPUPWR GD <11>

20141217

AC_PRESENT_R
CPU_VRALERT#

BATLOW#
PCH_LAN_WAKE#

SYS_RST#
EC_RSMRST#

20141225

12

RH1080_0402_5% @

XDP_ITP_PMODE <44>
CPU_XDP_TCK0 <11,44>
CPU_XDP_TMS <1 1,44>
CPU_XDP_TDO <11,44>
CPU_XDP_TDI <11,44>
PCH_JTAG_TCK1 <44>

4 5
3 6
2 7
1 8

10K_0804_8P 4R_5%

RP36

1

AC_PRESENT <38>

SYS_RST#

1

CH272

ESD@

100P_0402_5 0V8J

20141230, ESD require

2

12

RH5010K_ 0402_5% @

12

RH4410K_ 0402_5% @

+3V_PCH

to DIMM & TP Conn.

5

20141217

to EC & thermal sensor (TP reserve)

5

@

PCH_SMB_CLK <20,21,40>

PCH_SMB_DATA <20,21,40>

EC_SMB_CK2 <38,40>

EC_SMB_DA2 <38,40>

WAKE#
SUSCLK

SMBCLK
SMBDATA
SML1CLK
SML1DATA

RH40 0_0402_5%@
RH42 0_0402_5%@
RH43 0_0402_5%@
RH46 0_0402_5%@

1 2
1 2
1 2
1 2

12
12

20141217

+3V_PCH

RH381K_0 402_5%
RH451K_0 402_5% @

PCH_SMB_CLK
PCH_SMB_DATA
EC_SMB_CK2
EC_SMB_DA2

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

For DFT ONLY

5

4

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2015/08/10 2016/12/31

2015/08/10 2016/12/31

2015/08/10 2016/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document N umber R ev

Size Document N umber R ev

Size Document N umber R ev

Custom

Custom

Custom

Date : Sh eet o f

Date : Sh eet o f

2

Date : Sh eet o f

Compal Electronics, Inc.

SMB,HDA,JTAG

SMB,HDA,JTAG

SMB,HDA,JTAG

LA-C951P

LA-C951P

LA-C951P

1

15 62Friday, August 14, 2015

15 62Friday, August 14, 2015

15 62Friday, August 14, 2015

1.0

1.0

1.0

5

4

3

2

1

UH1G

AR17

GPP_A16/CLKOUT_48

G1

CLKOUT_CPUNSSC_P

F1

CLKOUT_CPUNSSC_N

G2

CLKOUT_CPUBCLK_P

H2

CLKOUT_CPUBCLK_N

A5

XTAL24_OUT

A6

XTAL24_IN

E1

XCLK_BIASREF

BC9

RTCX1

BD10

RTCX2

BC24

GPP_B5/SRCCLKREQ0#

AW24

GPP_B6/SRCCLKREQ1#

AT24

GPP_B7/SRCCLKREQ2#

BD25

GPP_B8/SRCCLKREQ3#

BB24

GPP_B9/SRCCLKREQ4#

BE25

GPP_B10/SRCCLKREQ5#

AT33

GPP_H0/SRCCLKREQ6#

AR31

GPP_H1/SRCCLKREQ7#

BD32

GPP_H2/SRCCLKREQ8#

BC32

GPP_H3/SRCCLKREQ9#

BB31

GPP_H4/SRCCLKREQ10#

BC33

GPP_H5/SRCCLKREQ11#

BA33

GPP_H6/SRCCLKREQ12#

AW33

GPP_H7/SRCCLKREQ13#

BB33

GPP_H8/SRCCLKREQ14#

BD33

GPP_H9/SRCCLKREQ15#

R13

CLKOUT_PCIE_N15

R11

CLKOUT_PCIE_P15

P1

CLKOUT_PCIE_N14

R2

CLKOUT_PCIE_P14

W7

CLKOUT_PCIE_N13

Y5

CLKOUT_PCIE_P13

U2

CLKOUT_PCIE_N12

U3

CLKOUT_PCIE_P12

SKL-H-PCH_BGA837 @

UH1A

BD17

GPP_A11/PME#

AG15

RSVD

AG14

RSVD

AF17

RSVD

AE17

RSVD

AR19

TP2

AN17

TP1

BB29

SPI0_MOSI

BE30

SPI0_MISO

BD31

SPI0_CS0#

BC31

SPI0_CLK

AW31

SPI0_CS1#

BC29

SPI0_IO2

BD30

SPI0_IO3

AT31

SPI0_CS2#

AN36

GPP_D1/SPI1_CLK

AL39

GPP_D0/SPI1_CS#

AN41

GPP_D3/SPI1_MOSI

AN38

GPP_D2/SPI1_MISO

AH43

GPP_D22/SPI1_IO3

AG44

GPP_D21/SPI1_IO2

SKL-H-PCH_BGA837 @

XTAL24_OUT
XTAL24_IN

1 2

LANCLK_REQ#
CRCLK_REQ#
WLANCLK_RE Q#
SSDCLK_REQ#

GPUCLK_REQ#

PCH_CPU_NSS C_P
PCH_CPU_NSS C_N

PCH_CPU_BCL K_P
PCH_CPU_BCL K_N

2.7K_0402_1%

PCH_RTCX1
PCH_RTCX2

PCIECLK_REQ0#

PCIECLK_REQ5#
PCIECLK_REQ6#
PCIECLK_REQ7#
PCIECLK_REQ8#
PCIECLK_REQ9#

PCIECLK_REQ11#
PCIECLK_REQ12#
PCIECLK_REQ13#
PCIECLK_REQ14#
PCIECLK_REQ15#

PCH_SPI_SI

PCH_SPI_SO

PCH_SPI_CS0#

PCH_SPI_CLK

PCH_SPI_IO2
PCH_SPI_IO3

Note :
PCH_RTCX1/PCHRTCX2
Trace length <1000 mils

D D

C C

B B

1 2

RH69 10M_0402_5%

YH1

1 2

SJ10000Q400

1

CH19

8.2P 50V B NPO 0402

2

+3VS

RPH9

4 5
3 6
2 7
1 8

10K_0804_8P 4R_5%

RPH10

4 5
3 6
2 7
1 8

10K_0804_8P 4R_5%

XDP_SPI_SI<44>

XDP_SPI_IO2<44>

RH45/46 place to within 1100 mil of SPIO_MOSI/SPI0_IO2 pin for XDP

+3V_PCH

RH3

1K_0402_5%

RH4

1K_0402_5%

RH5

1K_0402_5%

PCH STRAPS
PESONALITY STRAP IS ENABLED IF LOW
PCH HAS INTERNAL WEAK PU

PCH_RTCX1

PCH_RTCX2

32.768KHZ 9PF 20PP M 9H03280012

1

CH20

8.2P 50V B NPO 0402

2

WLANCLK_RE Q#
LANCLK_REQ#
CRCLK_REQ#
PCIECLK_REQ0#

SSDCLK_REQ#
GPUCLK_REQ#

PCIECLK_REQ6#
PCIECLK_REQ7#

1 2

RH1 1K_0 402_1%

1 2

RH2 1K_0 402_1%CMC@

@

PCH_SPI_IO2

12

QS@

PCH_SPI_IO3

12

ES@

12

CH21

15P_0402_50 V8J

1

2

PCH_SPI_SI

PCH_SPI_IO2

To SPI ROM

12

RH701M_0402_5%

YH2

24MHZ 12PF +-20PP M 7V24000020

1

1

GND

GND

2

+3VS

4 5
3 6
2 7
1 8

10K_0804_8P 4R_5%

4 5
3 6
2 7
1 8

10K_0804_8P 4R_5%

PCH_SPI_SI_R
PCH_SPI_SO_R

PCH_SPI_CS0# EC_SP I_CS0#

PCH_SPI_SI_R
PCH_SPI_SO_R
PCH_SPI_IO2_R PC H_SPI_IO2

PCH_SPI_IO3_R PCH_SPI_IO3

PCH_SPI_CS0#
PCH_SPI_SO_R
PCH_SPI_IO2_R

1
2
3
4

XTAL24_IN

XTAL24_OUT

3

3

1

SJ10000DI00

4

CH22
15P_0402_50 V8J

2

RPH11

<BOM Structure>

PCIECLK_REQ11#
PCIECLK_REQ8#
PCIECLK_REQ9#
PCIECLK_REQ5#

RPH12

<BOM Structure>

PCIECLK_REQ12#
PCIECLK_REQ13#
PCIECLK_REQ14#
PCIECLK_REQ15#

SDV test if unpop

RPH2

EC_SPI_CLKPCH_SPI_CLK_R

1 8

EC_SPI_MOSI

2 7

EC_SPI_MISO

3 6
4 5

33_0804_8P4 R_5%

RPH1

PCH_SPI_CLKPCH_SPI_CLK_R

1 8

PCH_SPI_SI

2 7

PCH_SPI_SO

3 6
4 5

33_0804_8P4 R_5%

1 2

RH49

33_0402_5%

UH2

CS#
SO
WP#
GND

GD25B64CSIGR SOP 8P SPI ROM

SA00007LA10

VCC

HOLD#

SCLK

8
7
6
5

SI

+3V_PCH

1 2

0.1U_0201_10 V6K

PCH_SPI_IO3_R
PCH_SPI_CLK_R
PCH_SPI_SI_R

CH33

PCH_CPU_NSS C_P<11>
PCH_CPU_NSS C_N<11>

PCH_CPU_BCL K_P<11>
PCH_CPU_BCL K_N< 11>

+1VALW

EC_SPI_CLK <38>
EC_SPI_MOSI <38>
EC_SPI_MISO <38>
EC_SPI_CS0# <38>

To PCH

RH68

LANCLK_REQ#<36>
CRCLK_REQ#< 35>
WLANCLK_RE Q#<34>
SSDCLK_REQ#<42>

GPUCLK_REQ#<23>

To EC

SPT-H_PCH

SPT-H_PCH

PLT_RST#<22 ,34,35,36,38,39,42>

CH273

ESD@

100P_0402_5 0V8J

20141230, ESD require

CLKOUT_ITPXDP_N

CLKOUT_ITPXDP_P
CLKOUT_CPUPCIBCLK_N
CLKOUT_CPUPCIBCLK_P

CLKOUT_PCIE_N0
CLKOUT_PCIE_P0

CLKOUT_PCIE_N1
CLKOUT_PCIE_P1

CLKOUT_PCIE_N2
CLKOUT_PCIE_P2

CLKOUT_PCIE_N3
CLKOUT_PCIE_P3

CLKOUT_PCIE_N4
CLKOUT_PCIE_P4

CLKOUT_PCIE_N5
CLKOUT_PCIE_P5

CLKOUT_PCIE_N6
CLKOUT_PCIE_P6

CLKOUT_PCIE_N7
CLKOUT_PCIE_P7

CLKOUT_PCIE_N8
CLKOUT_PCIE_P8

CLKOUT_PCIE_N9
CLKOUT_PCIE_P9

CLKOUT_PCIE_N10
CLKOUT_PCIE_P10

CLKOUT_PCIE_N11
CLKOUT_PCIE_P11

7 OF 12 REV = 1.3

GPP_B13/PLTRST#

GPP_G16/GSXCLK

GPP_G12/GSXDOUT

GPP_G13/GSXSLOAD

GPP_G14/GSXDIN

GPP_G15/GSXSRESET#

GPP_E3/CPU_GP0
GPP_E7/CPU_GP1
GPP_B3/CPU_GP2
GPP_B4/CPU_GP3

GPP_H18/SML4ALERT#

GPP_H17/SML4DATA

GPP_H16/SML4CLK

GPP_H15/SML3ALERT#

GPP_H14/SML3DATA

GPP_H13/SML3CLK

GPP_H12/SML2ALERT#

GPP_H11/SML2DATA

GPP_H10/SML2CLK

INTRUDER#

REV = 1.31 OF 12

1

2

12

RH52
100K_0402_5 %

@

L1
L2
J1
J2

N7
N8

L7
L5

D3
F2

E5
G4

D5
E6

D8
D7

R8
R7

U5
U7

W10
W11

N3
N2

P3
P2

R3
R4

BB27

P43
R39
R36
R42
R41

AF41
AE44
BC23
BD24

BC36
BE34
BD39
BB36
BA35
BC35
BD35
AW35
BD34
BE11

RH8

1 2

0_0402_5%

+3VS

4

O

CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

PCH_PLTRST #

@

5

P

IN1

IN2

G

3

PCH_CPU_PCIBCL K_N <11>

PCH_CPU_PCIBCL K_P <11>

CLK_PCIE_LAN# <36 >

CLK_PCIE_LAN <36>

CLK_PCIE_CR# <35>

CLK_PCIE_WLAN# <34>

CLK_PCIE_WLAN <34>

CLK_PCIE_SSD# < 42>

CLK_PCIE_SSD <4 2>

CLK_PEG_VGA# <22>
CLK_PEG_VGA <22>

DGPU_PWROK

DGPU_PWROK <17,58>

1M_0402_5%

@

1

2

12

PCH_PLTRST #

RH6

UH3

SN74AHC1G08DC KR_SC70-5

CLK_PCIE_CR < 35>

+RTCVCC

TC212TP@
TC213TP@

dGPU

LAN

Card Reader

WLAN(NG FF)

SSD(NGF F)

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

For DFT ONLY

5

4

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2015/08/10 2016/12/31

2015/08/10 2016/12/31

2015/08/10 2016/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document N umber R ev

Size Document N umber R ev

Size Document N umber R ev

Custom

Custom

Custom

Date : Sh eet o f

Date : Sh eet o f

2

Date : Sh eet o f

Compal Electronics, Inc.

CLK,SPI

CLK,SPI

CLK,SPI

LA-C951P

LA-C951P

LA-C951P

1

16 62Friday, August 14, 2015

16 62Friday, August 14, 2015

16 62Friday, August 14, 2015

1.0

1.0

1.0

5

4

3

2

1

+3VS

D D

+3VS

C C

RP33

4 5
3 6
2 7
1 8

10K_080 4_8P4R_5%

RH105 10K_040 2_5%
RH9 10K_040 2_5%

1 2

RH92 49.9 K_0402_1%@

1 2

RH94 49.9 K_0402_1%@

1 2

RH90 49.9 K_0402_1%

1 2

RH91 49.9 K_0402_1%

12
12

GPP_B21

WLB T_OFF#

PCH_SAT ALED#

DGPU_PW R_EN

KB_RST#

DGPU_PW ROK

UART0_C TS#
UART0_R TS#

UART0_T XD

UART0_R XD

PCH_SAT ALED# <14,41,42 >

KB_RST# <13,38>

DGPU_PWROK <16,58>

GSPI1_MOS I
GPP_B21

GSPI0_MOS I

WLB T_OFF#<3 4>

DGPU_HO LD_RST#<22>

DGPU_PW R_EN<24,38,53 ,58,59>

UART0_C TS#<34>
UART0_R TS#<34>
UART0_T XD<34>
UART0_R XD<34>

WLB T_OFF#

DGPU_HO LD_RST#
DGPU_PW R_EN

UART0_C TS#
UART0_R TS#
UART0_T XD
UART0_R XD

UH1K

AT29

GPP_B22/GSPI1_MOSI

AR29

GPP_B21/GSPI1_MISO

AV29

GPP_B20/GSPI1_CLK

BC27

GPP_B19/GSPI1_CS#

BD28

GPP_B18/GSPI0_MOSI

BD27

GPP_B17/GSPI0_MISO

AW27

GPP_B16/GSPI0_CLK

AR24

GPP_B15/GSPI0_CS#

AV44

GPP_C9/UART0_TXD

BA41

GPP_C8/UART0_RXD

AU44

GPP_C11/UART0_CTS#

AV43

GPP_C10/UART0_RTS#

AU41

GPP_C15/UART1_CTS#/ISH_UART1_CTS#

AT44

GPP_C14/UART1_RTS#/ISH_UART1_RTS#

AT43

GPP_C13/UART1_TXD/ISH_UART1_TXD

AU43

GPP_C12/UART1_RXD/ISH_UART1_RXD

AN43

GPP_C23/UART2_CTS#

AN44

GPP_C22/UART2_RTS#

AR39

GPP_C21/UART2_TXD

AR45

GPP_C20/UART2_RXD

AR41

GPP_C19/I2C1_SCL

AR44

GPP_C18/I2C1_SDA

AR38

GPP_C17/I2C0_SCL

AT42

GPP_C16/I2C0_SDA

AM44

GPP_D4/ISH_I2C2_SDA/ISH_I2C3_SDA

AJ44

GPP_D23/ISH_I2C2_SCL/ISH_I2C3_SCL

SKL-H-PCH _BGA837 @

SPT-H_PCH

GPP_D9
GPP_D10
GPP_D11
GPP_D12

GPP_D16/ISH_UART0_CTS#

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C2_SCL

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C2_SDA

11 OF 12 REV = 1.3

GPP_D15/ISH_UART0_RTS#

GPP_H20/ISH_I2C0_SCL
GPP_H19/ISH_I2C0_SDA

GPP_H22/ISH_I2C1_SCL
GPP_H21/ISH_I2C1_SDA

GPP_A23/ISH_GP5
GPP_A22/ISH_GP4
GPP_A21/ISH_GP3
GPP_A20/ISH_GP2
GPP_A19/ISH_GP1
GPP_A18/ISH_GP0
GPP_A17/ISH_GP7

AL44
AL36
AL35
AJ39

AJ43
AL43
AK44
AK45

BC38
BB38

BD38
BE39

BC22
BD18
BE21
BD22
BD21
BB22
BC19

Functional Strap Definitions

SPKR (Internal Pull Down):

TOP Swap Override

0 = Disable TOP Swap mode.---> ORB Use

*

1 = Enable TOP Swap Mode.

GSPI0_MOSI (Internal Pull Down):

No Reboot

0 = Disable No Reboot mode. --> ORB Use

*

1 = Enable No Reboot Mode. (PCH will disable the TCO
Timer system reboot feature). This function is useful
when running ITP/XDP.

GSPI1_MOSI (Internal Pull Down):

Boot BIOS Strap Bit

0 = SPI Mode --> ORB Use

*

1 = LPC Mode

1 2

B B

A A

RH86 100K_04 02_5%@

HDA_SPK R

HDA_SPK R <15,37>

+3VS+3VS

For DFT ONLY

5

4

1 2

RH87 4.7K_0402_5 %@

20141217

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

GSPI0_MOS I

Compal Secret Data

Compal Secret Data

2015/08/ 10 2016/12/ 31

2015/08/ 10 2016/12/ 31

2015/08/ 10 2016/12/ 31

3

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

+3VS

GPP B22 => BBS_BIT0

@

RH88 150K_04 02_1%

12

2

GSPI1_MOS I

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

20141217

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

I2C,UART,GPIO

I2C,UART,GPIO

I2C,UART,GPIO

LA-C951P

LA-C951P

LA-C951P

17 62F riday, August 14, 2 015

17 62F riday, August 14, 2 015

17 62F riday, August 14, 2 015

1

1.0

1.0

1.0

5

+1VALW

3.182mA

D D

+1V_MPH Y_EXT

Imax=3.3A

C C

B B

+1V_PCH

283mA

RH71

@

1 2

0_0603_ 5%

RH72

@

1 2

0_0603_ 5%

RH66

@

1 2

0_0603_ 5%

RH67

@

1 2

0_0603_ 5%

RH78

1 2

0_0603_ 5%

RH80

1 2

0_0603_ 5%

+1V_PRIM

Imax=2.8 99A

1

CH23

@

@

2

22U_0603_6.3V6M

+1V_PCH

283mA

@

+1V_MPH Y

Imax=3.2A

+1V_MPH YPLL

110mA

@

+1V_VCC CLK

232mA

+1V_VCC CLK5

@

6mA

+1V_HDA PLL

45mA

0.1U_0201_10V6K

2

1

1

CH24

2

22U_0603_6.3V6M

1

CH26

2

22U_0603_6.3V6M

1

CH36

2

22U_0603_6.3V6M

1U_0402_6.3V6K

CH279

2

CH31

1

4

+1V_VCC CLK

+1V_VCC CLK5

+1V_MPH Y

+1V_MPH YPLL

+3V_HDA

+3VALW _DSW

+3VS

+3V_PCH

+3VS

+1V_PRIM

+1V_MPH Y

+1V_PRIM

+1V_HDA PLL

994mA

SIV remove(BA29 output pin)

232mA

6mA

Imax=3.2A

110mA

33mA

45mA
60mA

RH79

@

1 2

0_0603_ 5%

20141217

1 2

12

3

UH1H

AA23

VCCPRIM_1P0

AA26

VCCPRIM_1P0

AA28

VCCPRIM_1P0

AC23

VCCPRIM_1P0

AC26

VCCPRIM_1P0

AC28

VCCPRIM_1P0

AE23

VCCPRIM_1P0

AE26

VCCPRIM_1P0

Y23

VCCPRIM_1P0

Y25

VCCPRIM_1P0

BA29

DCPDSW_1P0

N17

VCCCLK1

R19

VCCCLK3

U20

VCCCLK4

V17

VCCCLK2

R17

VCCCLK2

K2

VCCCLK5

K3

VCCCLK5

U21

VCCMPHY_1P0

U23

VCCMPHY_1P0

U25

VCCMPHY_1P0

U26

VCCMPHY_1P0

V26

VCCMPHY_1P0

A43

VCCMPHYPLL_1P0

B43

VCCMPHYPLL_1P0

C44

VCCPCIE3PLL_1P0

C45

VCCPCIE3PLL_1P0

V28

VCCAPLLEBB_1P0

AC17

VCCPRIM_1P0

AJ5

VCCUSB2PLL_1P0

AL5

VCCUSB2PLL_1P0

AN19

VCCHDAPLL_1P0

BA15

VCCHDA

W15

1U_0402_6.3V6K

CH28

2

1

195mA

799mA

7mA7mA

RH1070_0402_5% @

RH1060_0402_5% @

VCCDSW_3P3

SKL-H-PCH _BGA837 @

+3VALW _DSW+3VALW

+3V_PCH

+3VS_PC H

+3V_VCC PGPPBCH

SPT-H_PCH

CORE

MPHY

USB

75mA

VCCGPI O

RH118

1 2

0_0603_ 5%

VCCPRIM_1P0

VCCDSW_3P3

VCCPGPPA
VCCPGPPBCH
VCCPGPPBCH

VCCPGPPEF
VCCPGPPEF

VCCPGPPG

VCCPRIM_3P3

VCCPRIM_1P0

VCCATS

VCCRTCPRIM_3P3

VCCRTC
DCPRTC

VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0

VCCSPI
VCCSPI
VCCSPI

VCCPGPPD
VCCPGPPD
VCCPGPPD
VCCPGPPD

VCCPRIM_3P3
VCCPRIM_3P3
VCCPRIM_3P3

REV = 1.38 OF 12

75mA

4.7U_0603_6.3V6K
CH34

2

@

1 2

1

close BA15

2

+1V_PRIMA L22

+3V_VCC PGPPBCH

+1V_PRIM

+3V_PCH

0.1U_0201_10V6K
CH18

2

1

+3VALW _DSW

4.7U_0603_6.3V6K

Ch29

12

@

AL22

BA24

BA31
BC42
BD40
AJ41
AL41
AD41
AN5

AD15
AD13
BA20
BA22
BA26

CH25

AJ20
AJ21
AJ23
AJ25

BE41
BE43
BE42

BC44
BA45
BC45
BB45

BD3
BE3
BE4

+3V_HDA+3V_PCH

0.1U_0201_10V6K
CH32

0.1U_020 1_10V6K

+3V_PCH

500mA

+1V_PRIMA D15

7mA

+3VS_PC H

<1mA

+3V_PCH

<1mA

+RTCVCC

12

29mA

78mA

117mA

1U_0402_6.3V6K

CC103

2

1

+RTCVCC

2

1

follow SKL-H CRB V1P0

1U_0402_6.3V6K

CH17

1

+1V_PRIMA L22

RH83

@

1 2

0_0603_ 5%

RH84

@

1 2

A A

0_0603_ 5%

For DFT ONLY

5

+1V_PRIMA D15

Security Classification

Security Classification

Security Classification

2015/08/ 10 2016/12/ 31

2015/08/ 10 2016/12/ 31

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

2015/08/ 10 2016/12/ 31

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

DMI x 4
Gen3 x 12 (PEGx8+SSDX4)
USB3.0 x 2
Gen2 x 3 (CR+LAN+WLAN)
Sata x 1
Imax=3.2A

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date : Sheet o f

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

VCC

VCC

VCC

LA-C951P

LA-C951P

LA-C951P

18 62F riday, August 14, 2 015

18 62F riday, August 14, 2 015

18 62F riday, August 14, 2 015

1

1.0

1.0

1.0

5

4

3

2

1

UH1I

SPT-H_PCH

AC18

VSS

AN4

VSS

AN10

VSS

BE14

VSS

BE18

VSS

BE23

VSS

BE28

VSS

D D

C C

B B

BE32

VSS

BE37

VSS

BE40

VSS

BE9

VSS

C10

VSS

C2

VSS

C28

VSS

C37

VSS

J7

VSS

K10

VSS

K27

VSS

K33

VSS

K36

VSS

K4

VSS

K42

VSS

K43

VSS

L12

VSS

L13

VSS

L15

VSS

L4

VSS

L41

VSS

L8

VSS

M35

VSS

M42

VSS

N10

VSS

N15

VSS

N19

VSS

N22

VSS

N24

VSS

N35

VSS

N36

VSS

N4

VSS

N41

VSS

N5

VSS

P17

VSS

P19

VSS

P22

VSS

P45

VSS

R10

VSS

R14

VSS

R22

VSS

R29

VSS

R33

VSS

R38

VSS

R5

VSS

T1

VSS

T2

VSS

T4

VSS

Y18

VSS

Y20

VSS

Y21

VSS

Y26

VSS

Y28

VSS

Y29

VSS

A18

VSS

A25

VSS

A32

VSS

A37

VSS

AA17

VSS

AA18

VSS

AA20

VSS

AA21

VSS

AA25

VSS

AA29

VSS

AA4

VSS

AA42

VSS

AB10

VSS

SKL-H-PCH _BGA837

9 OF 12
REV = 1.3

AR5

VSS

AR7

VSS

U15

VSS

AL4

VSS

AE29

VSS

AE4

VSS

AE42

VSS

AF18

VSS

AF20

VSS

AF21

VSS

AF23

VSS

AF25

VSS

AF26

VSS

AF28

VSS

AF29

VSS

AG11

VSS

AG13

VSS

AG31

VSS

AG32

VSS

AG33

VSS

AG38

VSS

AG4

VSS

AH1

VSS

AH17

VSS

AH18

VSS

AH20

VSS

AH21

VSS

AH23

VSS

AH25

VSS

AH26

VSS

AH28

VSS

AH29

VSS

AH45

VSS

AJ10

VSS

AJ14

VSS

AJ15

VSS

AJ17

VSS

AJ18

VSS

AJ26

VSS

AJ28

VSS

AJ29

VSS

AJ31

VSS

AJ32

VSS

AJ36

VSS

AK4

VSS

AK42

VSS

AU7

VSS

AV17

VSS

AV24

VSS

AV27

VSS

AV31

VSS

AV33

VSS

AV6

VSS

AW13

VSS

AW19

VSS

AW29

VSS

AW37

VSS

AW9

VSS

AY38

VSS

AY45

VSS

B25

VSS

B3

VSS

B37

VSS

B40

VSS

B6

VSS

BA1

VSS

BB11

VSS

BB16

VSS

BB21

VSS

BB25

VSS

BB30

VSS

BB34

VSS

BC2

VSS

BD43

VSS

@

UH1L

C42

VSS

D10

VSS

D12

VSS

D15

VSS

D16

VSS

D17

VSS

D19

VSS

D21

VSS

D24

VSS

D25

VSS

D27

VSS

D29

VSS

D30

VSS

D31

VSS

D33

VSS

D35

VSS

D36

VSS

E13

VSS

E15

VSS

E31

VSS

E33

VSS

F44

VSS

F8

VSS

G42

VSS

G9

VSS

H17

VSS

H19

VSS

H22

VSS

H24

VSS

H27

VSS

H29

VSS

H3

VSS

H35

VSS

J10

VSS

J11

VSS

J3

VSS

J39

VSS

J5

VSS

T42

VSS

U10

VSS

U11

VSS

U14

VSS

U17

VSS

U18

VSS

U28

VSS

U29

VSS

U31

VSS

U32

VSS

U33

VSS

U38

VSS

U4

VSS

U8

VSS

V18

VSS

V20

VSS

V21

VSS

V23

VSS

V25

VSS

V29

VSS

V3

VSS

V45

VSS

W14

VSS

W31

VSS

W32

VSS

W33

VSS

W38

VSS

W4

VSS

W8

VSS

Y17

VSS

SKL-H-PCH _BGA837

12 OF 12
REV = 1.3

SPT-H_PCH

@

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AB11
AB7
AB14
AB31
AB32
AB38
AB4
AB5
AC1
AC20
AC21
AC25
AC29
AC45
AB8
AD11
AD14
AB15
AD32
AD33
AD36
AD4
AD8
AE18
AE20
AE21
AE25
AE28
AL10
AL11
AL13
AL17
AL19
AL24
AL29
AL32
AL33
AL38
AM15
AM17
AM19
AM22
AM24
AM27
AM29
AM45
AN11
AN22
AN27
AN31
AN39
AN7
AN8
AP11
AP4
AR33
AR34
AR42
AR9
AT10
AT15
AT36
AT9
AU1
AU35
AU36
AU39
AU45
C4

UH1J

BD2

VSS

BD45

VSS

BD44

VSS

BE44

VSS

D45

VSS

A42

VSS

B45

VSS

B44

VSS

A4

VSS

A3

VSS

B2

VSS

A2

VSS

B1

VSS

BB1

VSS

BC1

VSS

A44

VSS

C1

RSVD

D1

RSVD

SKL-H-PCH _BGA837 @

10 OF 12
REV = 1.3

SPT-H_PCH

RSVD
RSVD
RSVD

RSVD
RSVD

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

PREQ#

PRDY#

CPU_TRST#

PCH_TRIGOUT

PCH_TRIGIN

AR22
W13
U13

P31
N31

P27
R27
N29
P29
AN29
R24
P24

AT3
AT4
AY5
AL2
AK1

XDP_PRE Q# <11,44>
XDP_PRD Y# < 11,44>
CPU_XDP _TRST# <1 1,44>
PCH_TRIGG ER <11>
CPU_TRIGG ER <11>

A A

Security Classification

Security Classification

Security Classification

2015/08/ 10 2016/12/ 31

2015/08/ 10 2016/12/ 31

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

For DFT ONLY

5

4

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/08/ 10 2016/12/ 31

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date : Sheet o f

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

VSS,RSVD

VSS,RSVD

VSS,RSVD

LA-C951P

LA-C951P

LA-C951P

19 62F riday, August 14, 2 015

19 62F riday, August 14, 2 015

19 62F riday, August 14, 2 015

1

1.0

1.0

1.0