LENOVO IdeaPad 320-17ABR,IdeaPad 320-15ABR Schematics

5

D D

WLAN

LAN

+1.05VS

PCIE_PRX_DTX_P131
PCIE_PRX_DTX_N131

PCIE_PRX_DTX_P228
PCIE_PRX_DTX_N228

1 2

RC1 196_0402_1%

PCIE_PRX_DTX_P1
PCIE_PRX_DTX_N1

PCIE_PRX_DTX_P2
PCIE_PRX_DTX_N2

P_TX_ZVDD

4

UC2B

PCIE

U10

U9

T6
T5

T9
T8

P7
P6

U7

P_GPP_RXP0
P_GPP_RXN0

P_GPP_RXP1
P_GPP_RXN1

P_GPP_RXP2
P_GPP_RXN2

P_GPP_RXP3
P_GPP_RXN3

P_ZVDDP

P_GPP_TXP0
P_GPP_TXN0

P_GPP_TXP1
P_GPP_TXN1

P_GPP_TXP2
P_GPP_TXN2

P_GPP_TXP3
P_GPP_TXN3

P_ZVSS/P_RX_ZVDDP

3

R1
R2

R4
R3

N1
N2

N4
N3

U6

PCIE_PTX_DRX_P1
PCIE_PTX_DRX_N1

PCIE_PTX_DRX_P2
PCIE_PTX_DRX_N2

P_RX_ZVDD

1 2
1 2

1 2
1 2

1 2

2

CC10.1U_0201_6.3V6-K
CC20.1U_0201_6.3V6-K

CC30.1U_0201_6.3V6-K
CC40.1U_0201_6.3V6-K

RC3196_0402_1%

PCIE_PTX_C_DRX_P1
PCIE_PTX_C_DRX_N1

PCIE_PTX_C_DRX_P2
PCIE_PTX_C_DRX_N2

PCIE_PTX_C_DRX_P1 31
PCIE_PTX_C_DRX_N1 31

PCIE_PTX_C_DRX_P2 28
PCIE_PTX_C_DRX_N2 28

1

WLAN

LAN

PCIE_CRX_GTX_P015

C C

B B

A A

PCIE_CRX_GTX_N015

PCIE_CRX_GTX_P115
PCIE_CRX_GTX_N115

PCIE_CRX_GTX_P215
PCIE_CRX_GTX_N215

PCIE_CRX_GTX_P315
PCIE_CRX_GTX_N315

PCIE_CRX_GTX_P415
PCIE_CRX_GTX_N415

PCIE_CRX_GTX_P515
PCIE_CRX_GTX_N515

PCIE_CRX_GTX_P615
PCIE_CRX_GTX_N615

PCIE_CRX_GTX_P715
PCIE_CRX_GTX_N715

5

PCIE_CRX_GTX_P0
PCIE_CRX_GTX_N0

PCIE_CRX_GTX_P1
PCIE_CRX_GTX_N1

PCIE_CRX_GTX_P2
PCIE_CRX_GTX_N2

PCIE_CRX_GTX_P3
PCIE_CRX_GTX_N3

PCIE_CRX_GTX_P4
PCIE_CRX_GTX_N4

PCIE_CRX_GTX_P5
PCIE_CRX_GTX_N5

PCIE_CRX_GTX_P6
PCIE_CRX_GTX_N6

PCIE_CRX_GTX_P7
PCIE_CRX_GTX_N7

P10

P_GFX_RXP0

P9

P_GFX_RXN0

N6

P_GFX_RXP1

N5

P_GFX_RXN1

N9

P_GFX_RXP2

N8

P_GFX_RXN2

L7

P_GFX_RXP3

L6

P_GFX_RXN3

L10

P_GFX_RXP4

L9

P_GFX_RXN4

K6

P_GFX_RXP5

K5

P_GFX_RXN5

K9

P_GFX_RXP6

K8

P_GFX_RXN6

J7

P_GFX_RXP7

J6

P_GFX_RXN7

@

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

FP4 REV 0.93

Issued Date

Issued Date

Issued Date

P_GFX_TXP0
P_GFX_TXN0

P_GFX_TXP1
P_GFX_TXN1

P_GFX_TXP2
P_GFX_TXN2

P_GFX_TXP3
P_GFX_TXN3

P_GFX_TXP4
P_GFX_TXN4

P_GFX_TXP5
P_GFX_TXN5

P_GFX_TXP6
P_GFX_TXN6

P_GFX_TXP7
P_GFX_TXN7

AMD-CARRIZO_FP4-BGA968

M2
M1

L1
L2

L4
L3

J1
J2

J4
J3

H2
H1

G1
G2

G4
G3

2013/08/15

2013/08/15

2013/08/15

3

PCIE_CTX_GRX_P0
PCIE_CTX_GRX_N0

PCIE_CTX_GRX_P1
PCIE_CTX_GRX_N1

PCIE_CTX_GRX_P2
PCIE_CTX_GRX_N2

PCIE_CTX_GRX_P3
PCIE_CTX_GRX_N3

PCIE_CTX_GRX_P4
PCIE_CTX_GRX_N4

PCIE_CTX_GRX_P5
PCIE_CTX_GRX_N5

PCIE_CTX_GRX_P6
PCIE_CTX_GRX_N6

PCIE_CTX_GRX_P7
PCIE_CTX_GRX_N7

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

CC50.22U_0201_6.3V6-K PX@
CC60.22U_0201_6.3V6-K PX@

CC70.22U_0201_6.3V6-K PX@
CC80.22U_0201_6.3V6-K PX@

CC90.22U_0201_6.3V6-K PX@
CC100.22U_0201_6.3V6-K PX@

CC110.22U_0201_6.3V6-K PX@
CC120.22U_0201_6.3V6-K PX@

CC180.22U_0201_6.3V6-K PX@
CC300.22U_0201_6.3V6-K PX@

CC310.22U_0201_6.3V6-K PX@
CC330.22U_0201_6.3V6-K PX@

CC320.22U_0201_6.3V6-K PX@
CC340.22U_0201_6.3V6-K PX@

CC350.22U_0201_6.3V6-K PX@
CC360.22U_0201_6.3V6-K PX@

2013/08/15

2013/08/15

2013/08/15

PCIE_CTX_C_GRX_P0
PCIE_CTX_C_GRX_N0

PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_N1

PCIE_CTX_C_GRX_P2
PCIE_CTX_C_GRX_N2

PCIE_CTX_C_GRX_P3
PCIE_CTX_C_GRX_N3

PCIE_CTX_C_GRX_P4
PCIE_CTX_C_GRX_N4

PCIE_CTX_C_GRX_P5
PCIE_CTX_C_GRX_N5

PCIE_CTX_C_GRX_P6
PCIE_CTX_C_GRX_N6

PCIE_CTX_C_GRX_P7
PCIE_CTX_C_GRX_N7

2

PCIE_CTX_C_GRX_P0 15
PCIE_CTX_C_GRX_N0 15

PCIE_CTX_C_GRX_P1 15
PCIE_CTX_C_GRX_N1 15

PCIE_CTX_C_GRX_P2 15
PCIE_CTX_C_GRX_N2 15

PCIE_CTX_C_GRX_P3 15
PCIE_CTX_C_GRX_N3 15

PCIE_CTX_C_GRX_P4 15
PCIE_CTX_C_GRX_N4 15

PCIE_CTX_C_GRX_P5 15
PCIE_CTX_C_GRX_N5 15

PCIE_CTX_C_GRX_P6 15
PCIE_CTX_C_GRX_N6 15

PCIE_CTX_C_GRX_P7 15
PCIE_CTX_C_GRX_N7 15

Title

Title

Title

FP4 (PCIE I/F)

FP4 (PCIE I/F)

FP4 (PCIE I/F)

Size

Size

Size

Document Nu mber Rev

Document Nu mber Rev

Document Nu mber Rev

Custom

Custom

Custom

Thursday, January 12, 2017

Thursday, January 12, 2017

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Thursday, January 12, 2017

320ABR

320ABR

320ABR

1

GPUGPU

4 50

4 50

4 50

0.1

0.1

0.1

5

UC2A

DDRA_MA[13..0]12

D D

DDRA_BG112
DDRA_ACT#12

DDRA_BA012
DDRA_BA112
DDRA_BG012

DDRA_DM[7..0]12

C C

DDRA_CLK012
DDRA_CLK0#12
DDRA_CLK112
DDRA_CLK1#12

1 2

MEM_MA_RST#12

B B

+1.2V

A A

RC283 10_0402_5%

MEM_MA_EVENT#12

DDRA_CKE012
DDRA_CKE112

DDRA_ODT012
DDRA_ODT112

DDRA_CS0#12
DDRA_CS1#12

DDRA_MA16_RAS#12
DDRA_MA15_CAS#12
DDRA_MA14_WE#12

1 2

RC284 1K_0402_5%

5

TC76@

MEM_MA_EVENT#

1

DDRA_MA0
DDRA_MA1
DDRA_MA2
DDRA_MA3
DDRA_MA4
DDRA_MA5
DDRA_MA6
DDRA_MA7
DDRA_MA8
DDRA_MA9
DDRA_MA10
DDRA_MA11
DDRA_MA12
DDRA_MA13
DDRA_BG1
DDRA_ACT#

DDRA_BA0
DDRA_BA1
DDRA_BG0

DDRA_DM0
DDRA_DM1
DDRA_DM2
DDRA_DM3
DDRA_DM4
DDRA_DM5
DDRA_DM6
DDRA_DM7

DDRA_DQS0
DDRA_DQS#0
DDRA_DQS1
DDRA_DQS#1
DDRA_DQS2
DDRA_DQS#2
DDRA_DQS3
DDRA_DQS#3
DDRA_DQS4
DDRA_DQS#4
DDRA_DQS5
DDRA_DQS#5
DDRA_DQS6
DDRA_DQS#6
DDRA_DQS7
DDRA_DQS#7

DDRA_CLK0
DDRA_CLK0#
DDRA_CLK1
DDRA_CLK1#

MEM_MA_RST#_R
MEM_MA_EVENT#

DDRA_CKE0
DDRA_CKE1

DDRA_ODT0
DDRA_ODT1

DDRA_CS0#
DDRA_CS1#

DDRA_MA16_RAS#
DDRA_MA15_CAS#
DDRA_MA14_WE#

APU_MA_VREFDQ
+MEM_VREF

AG29

AG26
AG27

AW27

AE28

Y27
Y29

Y26
W28
W29
W26

U29
W25

U26

U27

T28

AK26

T26

T25

T29

E19

D21

K21

F29

AP28
AV26
AR22
BC22

K29

H19

G19

B22

A22

F23

E23

G27

F27

AP25
AP26

AV27
AV22
AU22
BA21
AY21

L27

L26

AE25
AE26
AD26
AD27
AB28
AB29
AB25
AB26

N29

AE29

P27

P29

AK27
AL26
AH25
AL25

AH26
AL29
AH29
AL28

AG24
AK29
AH28

B19

T32

MEMORY A

MA_ADD0

MA_ADD1
MA_ADD2
MA_ADD3
MA_ADD4
MA_ADD5
MA_ADD6
MA_ADD7
MA_ADD8
MA_ADD9
MA_ADD10
MA_ADD11
MA_ADD12
MA_ADD13
MA_ADD14/MA_BG1
MA_ADD15/MA_ACT_L

MA_BANK0
MA_BANK1
MA_BANK2/MA_BG0

MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7
MA_DM8

MA_DQS_H0
MA_DQS_L0
MA_DQS_H1
MA_DQS_L1
MA_DQS_H2
MA_DQS_L2
MA_DQS_H3
MA_DQS_L3
MA_DQS_H4
MA_DQS_L4
MA_DQS_H5
MA_DQS_L5
MA_DQS_H6
MA_DQS_L6
MA_DQS_H7
MA_DQS_L7
MA_DQS_H8
MA_DQS_L8

MA_CLK_H0
MA_CLK_L0
MA_CLK_H1
MA_CLK_L1
MA_CLK_H2
MA_CLK_L2
MA_CLK_H3
MA_CLK_L3

MA_RESET_L
MA_EVENT_L

MA_CKE0
MA_CKE1

MA0_ODT0
MA0_ODT1
MA1_ODT0
MA1_ODT1

MA0_CS_L0
MA0_CS_L1
MA1_CS_L0
MA1_CS_L1

MA_RAS_L/MA_RAS_L_ADD16
MA_CAS_L/MA_CAS_L_ADD15
MA_WE_L/MA_WE_L_ADD14

MA_VREFDQ
M_VREF

@

MA_ZVDDIO_MEM_S

FP4 REV 0.93

AMD-CARRIZO_FP4-BGA968

SO-DIMM

MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7

MA_DATA8

MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15

MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23

MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31

MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39

MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47

MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55

MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63

MA_CHECK0
MA_CHECK1
MA_CHECK2
MA_CHECK3
MA_CHECK4
MA_CHECK5
MA_CHECK6
MA_CHECK7

H17
J17
F20
H20
E17
F17
K18
E20

A21
C21
C23
D23
B20
B21
B23
A23

G22
H22
E25
G25
J20
E22
H23
J23

F26
E27
J26
J27
H25
E26
G28
G29

AN26
AP29
AR26
AP24
AN29
AN27
AR29
AR27

AU26
AV29
AU25
AW25
AU29
AU28
AW26
AT25

AV23
AW23
AV20
AW20
AR23
AT23
AR20
AT20

BB23
BB22
BB20
AY19
BA23
BC23
BC21
BB21

K26
K28
N26
N28
J29
K25
L29
N25

AD29

4

DDRA_DQ0
DDRA_DQ1
DDRA_DQ2
DDRA_DQ3
DDRA_DQ4
DDRA_DQ5
DDRA_DQ6
DDRA_DQ7

DDRA_DQ8
DDRA_DQ9
DDRA_DQ10
DDRA_DQ11
DDRA_DQ12
DDRA_DQ13
DDRA_DQ14
DDRA_DQ15

DDRA_DQ16
DDRA_DQ17
DDRA_DQ18
DDRA_DQ19
DDRA_DQ20
DDRA_DQ21
DDRA_DQ22
DDRA_DQ23

DDRA_DQ24
DDRA_DQ25
DDRA_DQ26
DDRA_DQ27
DDRA_DQ28
DDRA_DQ29
DDRA_DQ30
DDRA_DQ31

DDRA_DQ32
DDRA_DQ33
DDRA_DQ34
DDRA_DQ35
DDRA_DQ36
DDRA_DQ37
DDRA_DQ38
DDRA_DQ39

DDRA_DQ40
DDRA_DQ41
DDRA_DQ42
DDRA_DQ43
DDRA_DQ44
DDRA_DQ45
DDRA_DQ46
DDRA_DQ47

DDRA_DQ48
DDRA_DQ49
DDRA_DQ50
DDRA_DQ51
DDRA_DQ52
DDRA_DQ53
DDRA_DQ54
DDRA_DQ55

DDRA_DQ56
DDRA_DQ57
DDRA_DQ58
DDRA_DQ59
DDRA_DQ60
DDRA_DQ61
DDRA_DQ62
DDRA_DQ63

MA_ZVDDIO

1K_0402_1%

1K_0402_1%

4

DDRA_DQS[0..7]12

DDRA_DQS#[0..7]12

DDRA_DQ[63..0] 12

APU

DA32

DA33

DA34

DA35

DA36

DA37

DA38

DA39

DA40

DA41

DA42

DA43

DA44

DA45

DA46

DA47

DA48

DA49

DA50

DA51

DA52

DA53

DA54

DA55

DA56

DA57

DA58

DA59

DA60

DA61

DA62

DA63

1 2

RC33 39.2_0402_1%

+1.2V

12

RC4

@

12

RC5

1

CC13

2

@

@

.047U_0201_6.3V6K

SO-DIMM

DQ39

DQ36

DQ35

DQ34

DQ37

DQ32

DQ38

DQ33

DQ45

DQ44

DQ47

DQ46

DQ40

DQ41

DQ43

DQ42

DQ55

DQ49

DQ54

DQ48

DQ53

DQ52

DQ50

DQ51

DQ61

DQ56

DQ63

DQ58

DQ60

DQ57

DQ59

DQ62

+1.2V

1

CC14

2

@

0.1U_0201_6.3V6-K

DDRA_DQS[0..7]

DDRA_DQS#[0..7]

1

CC15

2

@

1000P_0201_50V7-K

DRAM

UD3.1

UD3.6

UD3.2

UD3.7

UD3.5

UD3.3

UD3.4

UD3.0

UD3.15

UD3.9

UD3.14

UD3.8

UD3.13

UD3.11

UD3.12

UD3.10

UD4.0

UD4.3

UD4.2

UD4.7

UD4.5

UD4.1

UD4.6

UD4.4

UD4.14

UD4.10

UD4.11

UD4.12

UD4.13

UD4.9

UD4.15

UD4.8

+MEM_VREF

3

DDRB_MA[13..0]13

TC77@

DDRB_ACT#13

DDRB_BA013
DDRB_BA113
DDRB_BG013

DDRB_DM[7..0]13

DDRB_CLK013
DDRB_CLK0#13

1 2

MEM_MB_RST#13

3

RC240 10_0402_5%

DDRB_CKE013

DDRB_ODT013

DDRB_CS0#13

DDRB_MA16_RAS#13
DDRB_MA15_CAS#13
DDRB_MA14_WE#13

+1.2V

1 2

RC9 1K_0402_5%

TC70@

DDRB_MA0
DDRB_MA1
DDRB_MA2
DDRB_MA3
DDRB_MA4
DDRB_MA5
DDRB_MA6
DDRB_MA7
DDRB_MA8
DDRB_MA9
DDRB_MA10
DDRB_MA11
DDRB_MA12
DDRB_MA13
DDRB_BG1

1

DDRB_ACT#

DDRB_BA0
DDRB_BA1
DDRB_BG0

DDRB_DM0
DDRB_DM1
DDRB_DM2
DDRB_DM3
DDRB_DM4
DDRB_DM5
DDRB_DM6
DDRB_DM7

DDRB_DQS0
DDRB_DQS#0
DDRB_DQS1
DDRB_DQS#1
DDRB_DQS2
DDRB_DQS#2
DDRB_DQS3
DDRB_DQS#3
DDRB_DQS4
DDRB_DQS#4
DDRB_DQS5
DDRB_DQS#5
DDRB_DQS6
DDRB_DQS#6
DDRB_DQS7
DDRB_DQS#7

DDRB_CLK0
DDRB_CLK0#

MEM_MB_RST#_R
MEM_MB_EVENT#

DDRB_CKE0

DDRB_ODT0

DDRB_CS0#

DDRB_MA16_RAS#
DDRB_MA15_CAS#
DDRB_MA14_WE#

APU_MB_VREFDQ

1

MEM_MB_EVENT#

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2

AG31

MB_ADD0

AC30

MB_ADD1

AC31

MB_ADD2

AB32

MB_ADD3

AA32

MB_ADD4

AA33

MB_ADD5

AA31

MB_ADD6

Y33

MB_ADD7

AA30

MB_ADD8

W32

MB_ADD9

AG32

MB_ADD10

Y32

MB_ADD11

W33

MB_ADD12

AL31

MB_ADD13

W30

MB_ADD14/MB_BG1

V32

MB_ADD15/MB_ACT_L

AH32

MB_BANK0

AG33

MB_BANK1

W31

MB_BANK2/MB_BG0

D25

MB_DM0

D29

MB_DM1

E33

MB_DM2

J33

MB_DM3

AR30

MB_DM4

AW30

MB_DM5

BC30

MB_DM6

BC26

MB_DM7

N33

MB_DM8

B26

MB_DQS_H0

A26

MB_DQS_L0

B30

MB_DQS_H1

A30

MB_DQS_L1

F32

MB_DQS_H2

E32

MB_DQS_L2

K32

MB_DQS_H3

J32

MB_DQS_L3

AR32

MB_DQS_H4

AR33

MB_DQS_L4

AW32

MB_DQS_H5

AW33

MB_DQS_L5

BA29

MB_DQS_H6

AY29

MB_DQS_L6

BA25

MB_DQS_H7

AY25

MB_DQS_L7

P32

MB_DQS_H8

N32

MB_DQS_L8

AE33

MB_CLK_H0

AE32

MB_CLK_L0

AE30

MB_CLK_H1

AE31

MB_CLK_L1

AD32

MB_CLK_H2

AD33

MB_CLK_L2

AC33

MB_CLK_H3

AC32

MB_CLK_L3

T33

MB_RESET_L

AG30

MB_EVENT_L

U32

MB_CKE0

U33

MB_CKE1

AL30

MB0_ODT0

AM32

MB0_ODT1

AJ32

MB1_ODT0

AM33

MB1_ODT1

AJ33

MB0_CS_L0

AL32

MB0_CS_L1

AJ30

MB1_CS_L0

AL33

MB1_CS_L1

AH33

MB_RAS_L/MB_RAS_L_ADD16

AK32

MB_CAS_L/MB_CAS_L_ADD15

AJ31

MB_WE_L/MB_WE_L_ADD14

A19

MB_VREFDQ

@

Memory down

2013/08/15

2013/08/15

2013/08/15

2

UC2I

MEMORY B

MB_ZVDDIO_MEM_S

FP4 REV 0.93

AMD-CARRIZO_FP4-BGA968

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

DQ bi t swapping is allowed in a byte lane.

A25

MB_DATA0

C25

MB_DATA1

C27

MB_DATA2

D27

MB_DATA3

B24

MB_DATA4

B25

MB_DATA5

B27

MB_DATA6

A27

MB_DATA7

A29

MB_DATA8

C29

MB_DATA9

B32

MB_DATA10

D32

MB_DATA11

B28

MB_DATA12

B29

MB_DATA13

A31

MB_DATA14

C31

MB_DATA15

E30

MB_DATA16

E31

MB_DATA17

G33

MB_DATA18

G32

MB_DATA19

C33

MB_DATA20

D33

MB_DATA21

G30

MB_DATA22

G31

MB_DATA23

J30

MB_DATA24

J31

MB_DATA25

L33

MB_DATA26

L32

MB_DATA27

H32

MB_DATA28

H33

MB_DATA29

L30

MB_DATA30

L31

MB_DATA31

AN31

MB_DATA32

AP32

MB_DATA33

AT32

MB_DATA34

AU32

MB_DATA35

AN33

MB_DATA36

AN32

MB_DATA37

AR31

MB_DATA38

AT33

MB_DATA39

AU30

MB_DATA40

AV32

MB_DATA41

BA33

MB_DATA42

AY32

MB_DATA43

AU33

MB_DATA44

AU31

MB_DATA45

AW31

MB_DATA46

AY33

MB_DATA47

BC31

MB_DATA48

BB30

MB_DATA49

BB28

MB_DATA50

AY27

MB_DATA51

BB32

MB_DATA52

BA31

MB_DATA53

BC29

MB_DATA54

BB29

MB_DATA55

BB27

MB_DATA56

BB26

MB_DATA57

BB24

MB_DATA58

AY23

MB_DATA59

BA27

MB_DATA60

BC27

MB_DATA61

BC25

MB_DATA62

BB25

MB_DATA63

N30

MB_CHECK0

N31

MB_CHECK1

R33

MB_CHECK2

R32

MB_CHECK3

M32

MB_CHECK4

M33

MB_CHECK5

R30

MB_CHECK6

R31

MB_CHECK7

AF32

Deciphered Date

Deciphered Date

Deciphered Date

DDRB_DQ0
DDRB_DQ1
DDRB_DQ2
DDRB_DQ3
DDRB_DQ4
DDRB_DQ5
DDRB_DQ6
DDRB_DQ7

DDRB_DQ8
DDRB_DQ9
DDRB_DQ10
DDRB_DQ11
DDRB_DQ12
DDRB_DQ13
DDRB_DQ14
DDRB_DQ15

DDRB_DQ16
DDRB_DQ17
DDRB_DQ18
DDRB_DQ19
DDRB_DQ20
DDRB_DQ21
DDRB_DQ22
DDRB_DQ23

DDRB_DQ24
DDRB_DQ25
DDRB_DQ26
DDRB_DQ27
DDRB_DQ28
DDRB_DQ29
DDRB_DQ30
DDRB_DQ31

DDRB_DQ32
DDRB_DQ33
DDRB_DQ34
DDRB_DQ35
DDRB_DQ36
DDRB_DQ37
DDRB_DQ38
DDRB_DQ39

DDRB_DQ40
DDRB_DQ41
DDRB_DQ42
DDRB_DQ43
DDRB_DQ44
DDRB_DQ45
DDRB_DQ46
DDRB_DQ47

DDRB_DQ48
DDRB_DQ49
DDRB_DQ50
DDRB_DQ51
DDRB_DQ52
DDRB_DQ53
DDRB_DQ54
DDRB_DQ55

DDRB_DQ56
DDRB_DQ57
DDRB_DQ58
DDRB_DQ59
DDRB_DQ60
DDRB_DQ61
DDRB_DQ62
DDRB_DQ63

MB_ZVDDIO

2013/08/15

2013/08/15

2013/08/15

DDRB_DQS[0..7]13

DDRB_DQS#[0..7]13

DDRB_DQ[63..0] 13

APU

DA0

DA1

DA2

DA3

DA4

DA5

DA6

DA7

DA8

DA9

DA10

DA11

DA12

DA13

DA14

DA15

DA16

DA17

DA18

DA19

DA20

DA21

DA22

DA23

DA24

DA25

DA26

DA27

DA28

DA29

DA30

DA31

1 2

RC10 39.2_0402_1%

Size

Size

Size

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

DDRB_DQS[0..7]

DDRB_DQS#[0..7]

SO-DIMM

DQ2 UD1.0

DQ7

DQ6

DQ0

DQ1

DQ5

DQ4

DQ3

DQ12

DQ13

DQ11

DQ10

DQ9

DQ8

DQ15

DQ14

DQ20

DQ16

DQ19

DQ18

DQ17

DQ21

DQ22

DQ23

DQ24

DQ28

DQ30

DQ26

DQ25

DQ29

DQ27

DQ31

+1.2V

Title

Title

Title

FP4 (MEM)

FP4 (MEM)

FP4 (MEM)

Document Number Rev

Document Number Rev

Document Number Rev

Thursday, January 12, 2017

Thursday, January 12, 2017

Thursday, January 12, 2017

1

DRAM

UD1.3

UD1.4

UD1.5

UD1.2

UD1.7

UD1.1

UD1.6

UD1.11

UD1.9

UD1.12

UD1.14

UD1.13

UD1.15

UD1.8

UD1.10

UD2.7

UD2.3

UD2.4

UD2.1

UD2.0

UD2.2

UD2.6

UD2.5

UD2.9

UD2.11

UD2.12

UD2.8

UD2.13

UD2.15

UD2.14

UD2.10

320ABR

320ABR

320ABR

1

5 50

5 50

5 50

0.1

0.1

0.1

5

+1.8VS

12

RC18

D D

C C

B B

300_0402_5%

APU_RST#

PLACE CC16 CAPS CLOSE TO APU,CRB reserve 27pf

1

CC16
220P_0201_25V7-K

2

@

+1.8VS

12

RC19
300_0402_5%

APU_PWROK

PLACE CC17 CAPS CLOSE TO APU,CRB reserve 27pf

1

CC17
220P_0201_25V7-K

2

@

RPC10
1K_0404_4P2R_5%

1 4

APU_SIC

APU_SID

2 3

1

2

@

1

2

@

+1.8VS+1.8VS

G

S

G

2

QC6B
DMN5L06DWK-7 2N SOT363-6

S

61

D

QC6A
DMN5L06DWK-7 2N SOT363-6

APU_SVT

CC214
1000P_0201_50V7-K

APU_GFX_SVT

CC215
1000P_0201_50V7-K

5

34

D

HDMI

eDP

APU_SVT49
APU_SVC49
APU_SVD49

APU_GFX_SVT50
APU_GFX_SVC50
APU_GFX_SVD50

H_PROCHOT#35,46

EC_SMB_CK3 16,30,35

EC_SMB_DA3 16,30,35

APU_HDMI_TX2+24
APU_HDMI_TX2-24

APU_HDMI_TX1+24
APU_HDMI_TX1-24

APU_HDMI_TX0+24
APU_HDMI_TX0-24

APU_HDMI_CLK+24
APU_HDMI_CLK-24

APU_EDP_TX0+23
APU_EDP_TX0-23

APU_EDP_TX1+23
APU_EDP_TX1-23

1 2

RC279 0_0402_5%

1 2

RC213 0_0402_5%

1 2

RC215 0_0402_5%

1 2

RC280 0_0402_5%

1 2

RC217 0_0402_5%

1 2

RC219 0_0402_5%

APU_PWROK49,50

1 2

RC31 0_0402_5%@

APU_SVC

1

CC1281
1000P_0201_50V7-K

2

@

APU_GFX_SVC

1

CC1282
1000P_0201_50V7-K

2

@

With HDT+ Hea der

+1.8VS

RC7
1K_0402_5%

1 2

APU_TRST#

A A

2

CC84

0.01U_0201_10V6K

1

1 2

RC76 33_0402_5%HDT@

5

1 8

2 7

RPC17
10K_0804_8P4R_5%

HDT@

3 6

4 5

APU_TRST#_R

JHDT1

@

1

1

2

3

3

4

5

5

6

7

7

8

9

9

10

11

11

12

13

13

14

15

15

16

17

17

18

19

19

20

SAMTE_ASP-136446-07-B

2

4

6

8

10

12

14

16

RC273 33_0402_5%HDT@

18

20

@

@

APU_TCK

APU_TMS

APU_TDI

APU_TDO

APU_PWROK_BUF

APU_RST#_BUF

APU_DBRDY

1 2

APU_TEST19_PLLTEST0

APU_TEST18_PLLTEST1

4

APU_HDMI_TX2+
APU_HDMI_TX2-

APU_HDMI_TX1+
APU_HDMI_TX1-

APU_HDMI_TX0+
APU_HDMI_TX0-

APU_HDMI_CLK+
APU_HDMI_CLK-

APU_EDP_TX0+
APU_EDP_TX0-

APU_EDP_TX1+
APU_EDP_TX1-

APU_SVT_RA
APU_SVC_RA
APU_SVD_RA

APU_GFX_SVT_RA
APU_GFX_SVC_RA
APU_GFX_SVD_RA

APU_SIC
APU_SID

APU_RST#
APU_PWROK

APU_PROCHOT#_R

ALERT#

APU_TDI
APU_TDO
APU_TCK
APU_TMS
APU_TRST#
APU_DBRDY
APU_DBREQ#

APU_SVD

1

CC1283
1000P_0201_50V7-K

2

APU_GFX_SVD

1

CC1284
1000P_0201_50V7-K

2

4

APU_DBREQ#

B6

DP2_TXP0

A6

DP2_TXN0

D7

DP2_TXP1

C7

DP2_TXN1

A7

DP2_TXP2

B7

DP2_TXN2

D9

DP2_TXP3

C9

DP2_TXN3

A2

DP1_TXP0

A3

DP1_TXN0

B4

DP1_TXP1

A4

DP1_TXN1

D5

DP1_TXP2

C5

DP1_TXN2

A5

DP1_TXP3

B5

DP1_TXN3

E2

DP0_TXP0

E1

DP0_TXN0

E3

DP0_TXP1

E4

DP0_TXN1

D1

DP0_TXP2

D2

DP0_TXN2

C1

DP0_TXP3

B1

DP0_TXN3

C15

SVT0

D17

SVC0

D19

SVD0

B15

SVT1

B16

SVC1

A18

SVD1

B18

SIC

C17

SID

D15

RESET_L

C19

PWROK

A15

PROCHOT_L

B17

ALERT_L

H15

TDI

H14

TDO

D13

TCK

G15

TMS

J14

TRST_L

C13

DBRDY

A11

DBREQ_L

@

RPC5

1K_0804_8P4R_5%

2

CC213

0.01U_0201_10V6K

1

HDT@

DISPLAY/SVI2/JTAG/TEST

DP_STEREOSYNC/TEST36

FP4 REV 0.93

+1.8VS+1.8VS

18
27
36
45

APU_PWROK

APU_RST#

UC2C

DP_ZVSS

DP_AUX_ZVSS

DP_BLON

DP_DIGON

DP_VARY_BL

DP2_AUXP
DP2_AUXN

DP2_HPD

DP1_AUXP
DP1_AUXN

DP1_HPD

DP0_AUXP
DP0_AUXN

DP0_HPD

RSVD_1
TEMPIN0
TEMPIN1
TEMPIN2

TEMPINRETURN

TEST410
TEST411

TEST4
TEST5
TEST6

TEST9
TEST10
TEST14
TEST15
TEST16
TEST17
TEST11
TEST18
TEST19

TEST28_H
TEST28_L

TEST31

TEST37

VDDCR_GFX_SENSE

VDDCR_NB_SENSE

VDDCR_CPU_SENSE

VDDP_SENSE

VSS_SENSE

AMD-CARRIZO_FP4-BGA968

0.1U_0201_6.3V6-K

UC6

3

2A

2

GND

1

1A

APU_TDIAPU_DBREQ#

2

1

DP_2K_ZVSS

A9

DP_150_ZVSS

B9

DP_ENBKL

G5

DP_ENVDD

G6

DP_EDP_PWM

F11

H9
G9
E9

APU_DDC_CLK

F7

APU_DDC_DATA

E7

APU_HDMI_HPD

F5

APU_EDP_AUX

F8

APU_EDP_AUX#

E8

APU_EDP_HPD

G8

Core_type

K24
E15
E14
E12
F14
AK24

TEST410

AL24

TEST411

P24

TEST4

N24

TEST5

AN24
AB8
Y9

APU_TEST14_BP0

B10

APU_TEST15_BP1

D11

APU_TEST16_BP2

A10

APU_TEST17_BP3

C11

APU_TEST11_BP4

B11

APU_TEST18_PLLTEST1

A14

APU_TEST19_PLLTEST0

B14

APU_TEST28_H_PLLCHARZ

A13

APU_TEST28_L_PLLCHARZ

B13

APU_TEST31_MEM_TEST

P26

APU_TEST36_STEREOSYNC

E11

APU_TEST37

A17

APU_VDDGFX_SEN_H

H11

APU_VDDNB_SEN_H

J12

APU_VDDCORE_SEN_H

G12

VDD_095_FB_H

AY18

APU_VSS_SEN_L

H12

1

CC25

2

HDT@

SN74LVC2G07YZPR_WCSP6HDT@

CC212

0.01U_0201_10V6K

@

4

2Y

5

VCC

6

1Y

3

1 2

RC55 2K_0402_1%

1 2

RC12 150_0402_1%

Hot Plug Detect pins is I-IO18-S,but 3.3V tolerant.

DP to VGA

APU_DDC_CLK 24
APU_DDC_DATA 24
APU_HDMI_HPD 24

APU_EDP_AUX 23
APU_EDP_AUX# 23
APU_EDP_HPD 23

1

TC16@

1

TC17@

1

TC13@

1

TC14@

1 2

RC21 1K_0402_5%@

1

TC18@

1 2

RC23 1K_0402_5%@

1 2

RC24 1K_0402_5%@

1 2

RC189 1K_0402_5%@

1

TC21@

1

TC23@

1

TC25@

Test36 pull high for APU read EDID by HDMI DDC signal

APU_VDDGFX_SEN_H 50
APU_VDDNB_SEN_H 49
APU_VDDCORE_SEN_H 49

1

@

TC26

1 2

RC236 0_0402_5%@

1 2

RC237 0_0402_5%@

+1.8VS+1.8VS

12

12

RC36

RC32

300_0402_5%

300_0402_5%

APU_PWROK_BUF

APU_RST#_BUF

3

HDMI

eDP

1 2

RC239 100K_0402_5%@

14
23

1K_0404_4P2R_5%

RPC14

1 2

RC259 1K_0402_5%@

1 2

RC28 1K_0402_5%

1 2

RC27 1K_0402_5%@

1 2

RC29 1K_0402_5%@

1 2

RC30 1K_0402_5%@

APU_VDD_SEN_L 49

APU_VDDGFX_SEN_L 50

APU_VDDNB_SEN_H

APU_VDDCORE_SEN_H

APU_VDD_SEN_L

APU_VDDGFX_SEN_H

APU_VDDGFX_SEN_L

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTU RE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTU RE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTU RE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

+3VALW_APU

+3VS_APU

1

1

1

1

1

2013/08/15

2013/08/15

2013/08/15

2

To EDP pan el

+1.8VS

DP_EDP_PWM

TC27@

TC28@

TC29@

TC30@

TC31@

DP_ENVDD

DP_ENBKL

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

2

APU_DDC_CLK
APU_DDC_DATA

APU_EDP_HPD

ALERT#
APU_PROCHOT#_R

+3VS_APU

+3VALW_APU

RC71
10K_0402_5%

1 2

61

D

2

G

12

RC11
100K_0402_5%

12

RC13
100K_0402_5%

@

S

+3VALW_APU

RC73
10K_0402_5%

@

1 2

61

D

2

G

S

LCD Power IC can change for PCH_ENVDD for cost down

+3VALW_APU

RC75
10K_0402_5%

1 2

61

D

2

G

12

RC14
100K_0402_5%

Deciphered Date

Deciphered Date

Deciphered Date

S

12

RC70

4.7K_0402_5%

34

D

5

QC8B

G

DMN5L06DWK-7 2N SOT363-6

S

QC8A
DMN5L06DWK-7 2N SOT363-6

1 2

RC205 0_0402_5%@

+3VS_APU

12

RC74

4.7K_0402_5%

@

34

D

5

QC9B

G

DMN5L06DWK-7 2N SOT363-6

@

S

QC9A
DMN5L06DWK-7 2N SOT363-6

@

1 2

RC206 0_0402_5%@

+3VS_APU

RC77

2.2K_0402_5%

1 2

34

D

5

QC10B

G

DMN5L06DWK-7 2N SOT363-6

S

QC10A
DMN5L06DWK-7 2N SOT363-6

1 2

RC207 0_0402_5%

@

2013/08/15

2013/08/15

2013/08/15

1

RPC18

1 4
2 3

2.2K_0404_4P2R_5%

1 2

RC35 100K_0402_5%

RPC11

23
14

1K_0404_4P2R_5%

PCH_EDP_PWM 23

PCH_ENVDD 23

PCH_ENBKL 23

Title

Title

Title

FP4 (DISPLAY/CLK/MISC)

FP4 (DISPLAY/CLK/MISC)

FP4 (DISPLAY/CLK/MISC)

Size

Size

Size

Document Number Rev

Document Number Rev

Document Number Rev

Custom

Custom

Custom

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

320ABR

320ABR

320ABR

Thursday, January 12, 2017

Thursday, January 12, 2017

Thursday, January 12, 2017

1

+3VS_APU

+1.8VS

6 50

6 50

6 50

0.1

0.1

0.1

5

1 2

APU_LPC_ RST#30,35

PLT_RST#15,28,31

D D

EC_RSMRST#35

12

RC43
100K_0402_5%@

EC set RSMRST OD output

C C

EC_SYS_P WRGD35

PCIE_W AKE#_RA

AGPIO5

RC84

2.2K_04 02_5%

@

1 2

RC195
15K_0402_5%

SDM10U45 LP-7_DFN1006 -2-2

B B

+3VALW_APU

1 2

+3VS_APU

1 2

RC98 10K_0402_5%PX@

1 2

RC101 100K_0402_5%@

A A

+3VS_APU

1 2

RC100 10K_0402_5%@

1 2

RC104 2K_0402_5%UMA@

RC88

RC92

0_0402_5%

0_0402_5%

2 1

@

RC85
1K_0402_5%

@

1 2

RC196
15K_0402_5%

1 2

12

12

5

RC46 33_0402_5%

1

CC20
150P_04 02_50V8-J

2

1 2

RC38 33_0402_5%

1

CC19
100P_0201_25V8J

2

1 2

1 2

RC95 0_0402_5%@

RC20

2.2K_04 02_5%

@

1 2

TEST0
TEST1
TEST2

RC197
15K_0402_5%

12

DC1

PCIE_W AKE# 28 ,31,35

RC243 0_0402_5%

RB751V-4 0_SOD323-2 @

DC3

1 2

PXS_PW REN_R

VR_VGA_ PWRGD

SYS_RESE T#

LPC_RST#_R

PCIE_RST#_R

+1.8VALW

12

+3VS_APU

Connected to 10-ms RC-delay circuit on VDD_18_S5 powe r rail.

RC53

(CRB PWR Dea ly: 22K/0.1uF)

10K_0402_5%

RSMRST#_R

1

CC21

0.1U_040 2_25V6

2

12

RC72
10K_0402_5%

@

SYS_PW RGD_R

1

CC22

0.1U_020 1_6.3V6-K

2

RB751V-4 0_SOD323-2

1

CC38

0.1U_020 1_6.3V6-K

2

PBTN_OUT#35

PM_SLP_ S3#35
PM_SLP_ S5#35

RPC3

1 4
2 3

10K_040 4_4P2R_5%

DC4

1 2

@

SYS_PW RGD_R

2/22: change to 50K ohm for Crystal vendor suggest

4

BOARD_ID 3

DRAM

APIO15

RC191 0_0402_5%@

SYS_RESE T#11

PM_SLP_ S3#

RC193 0_0402_5%@

PM_SLP_ S5#

RC194 0_0402_5%@

APU_S5_ MUX_CTRL9

KBRST#35
GATEA2035
EC_SCI#35

AC_PRESE NT35

PCH_WL AN_OFF#31

WLAN_CL KREQ#31

LAN_CLKRE Q#28

PCH_BT_OFF#31

GPU_CLKRE Q#16

USB_OC1#25

HDA_SDIN032

Touch pad

RC201 0_0402_5%

TP_I2C0_S CL_R36
TP_I2C0_S DA_R36

Max ESR < 65K ohm !!

1 2

1 2
1 2

1 2

SUSCLK11,31

CC23

Config.
Hynix

Micron

Samsung

LPC_RST#_R
PCIE_RST#_R

RSMRST#_R

PWRBTN#_ RPBTN_OUT#
SYS_PW RGD_R
SYS_RESE T#
PCIE_W AKE#_RA

PM_SLP_ S3#_R
PM_SLP_ S5#_R

BOARD_ID1
APU_S5_ MUX_CTRL

TEST0
TEST1
TEST2

KBRST#

AC_PRESE NT
BOARD_ID4
BOARD_ID5
BOARD_ID3

AGPIO12
PCH_WL AN_OFF#

WLAN_CL KREQ#
LAN_CLKRE Q#
PCH_BT_OFF#
GPU_CLKRE Q#
BOARD_ID2
USB_OC1#
USB_OC2#

HDA_BITCLK
HDA_SDIN0 _R
HDA_SDIN1
HDA_SDIN2
HDA_RST#
HDA_SYNC
HDA_SDOUT

TP_I2C0_S CL_R
TP_I2C0_S DA_R

I2C1SCL
I2C1SDA

RC102

1 2

20M_040 2_5%

YC1

1 2

32.768K HZ_12.5PF_2 02740-PG14

1

2

20P_0402_50V8

0 0

0 1

1

1 1

BB12

LPC_RST_L

AN7

PCIE_RST_L/EGPIO26

AE4

RSMRST_L

AE1

PWR_BTN_L/AGPIO0

BC9

PWR_GOOD

AF2

SYS_RESET_L/AGPIO1

AG2

WAKE_L/AGPIO2

AK7

SLP_S3_L

AH5

SLP_S5_L

AE8

S0A3_GPIO/AGPIO10

AH8

S5_MUX_CTRL/EGPIO42

AH6

TEST0

AK8

TEST1/TMS

AE3

TEST2

AY15

ESPI_RESET_L/KBRST_L/AGPIO129

BC19

GA20IN/AGPIO126

AD7

LPC_PME_L/AGPIO22

BB13

LPC_SMI_L/AGPIO86

AG3

AC_PRES/USB_OC4_L/IR_RX0/AGPIO23

AD5

IR_TX0/USB_OC5_L/AGPIO13

AL8

IR_TX1/USB_OC6_L/AGPIO14

AN8

IR_RX1/AGPIO15

AE2

IR_LED_L/LLB_L/AGPIO12

BC15

CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/AGPIO92

BB17

CLK_REQ1_L/AGPIO115

BC17

CLK_REQ2_L/AGPIO116

BB18

CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/EGPIO131

BB16

CLK_REQG_L/OSCIN/EGPIO132

AH9

USB_OC0_L/TRST_L/AGPIO16

AG1

USB_OC1_L/TDI/AGPIO17

AH2

USB_OC2_L/TCK/AGPIO18

AL9

USB_OC3_L/TDO/AGPIO24

AU6

AZ_BITCLK/I2S_BCLK_MIC

AR8

AZ_SDIN0/I2S_DATA_MIC0

AP6

AZ_SDIN1/I2S_LR_PLAYBACK

AR5

AZ_SDIN2/I2S_DATA_MIC1

AU9

AZ_RST_L/I2S_LR_MIC

AT9

AZ_SYNC/I2S_BCLK_PLAYBACK

AR7

AZ_SDOUT/I2S_DATA_PLAYBACK

BB10

I2C0_SCL/EGPIO145

BB9

I2C0_SDA/EGPIO146

BB7

I2C1_SCL/EGPIO147

BC7

I2C1_SDA/EGPIO148

AG7

32K_X1

32K_X2

1

CC210

2

HDA_RST_AUD IO#32

HDA_SYNC_A UDIO32
HDA_BITCLK_ AUDIO32
HDA_SDOUT_A UDIO32

RTCCLK

AT1

X32K_X1

AT2

X32K_X2

@

change YC1 PN to ESPON S CRYSTAL 32.768KHZ X1A000141000300, footprint no change

20P_0402_50V8

PXS_PWREN_R/PXS_RST#_R/VR_VGA_PWRGD internal pull up 40k

4

BOARD_ID 4
AGPIO13

0

3

BOARD_ID0
BOARD_ID1
BOARD_ID2
BOARD_ID3
BOARD_ID4
BOARD_ID5
BOARD_ID6

ACPI/SD/AZ/GPIO/RTC/I2C/UART/MI SC

UART1_CTS_L/BT_I2S_BCLK/EGPIO140

UART1_INTR/BT_I2S_LRCLK/AGPIO144

FP4 REV 0.93

RPC4

1 8
2 7
3 6
4 5

33_0804 _8P4R_5%

3

2

RC39
10K_0402_5%

BD17@

1 2

RC47
10K_0402_5%

1 2

UC2D

SD0_WP/EGPIO101

SD0_PWR_CTRL/AGPIO102

SD0_CD/AGPIO25

SD0_CLK/EGPIO95

SD0_CMD/EGPIO96

SD0_DATA0/EGPIO97
SD0_DATA1/EGPIO98
SD0_DATA2/EGPIO99

SD0_DATA3/EGPIO100

SD0_LED/EGPIO93

SCL0/I2C2_SCL/EGPIO113
SDA0/I2C2_SDA/EGPIO114

SCL1/I2C3_SCL/AGPIO19

SDA1/I2C3_SDA/AGPIO20

AGPIO6/LDT_RST_L

AGPIO7/LDT_PWROK

VDDGFX_PD/AGPIO39

AGPIO66/SHUTDOWN_L

AGPIO68/SGPIO_CLK

AGPIO69/SGPIO_LOAD

AGPIO71/SGPIO_DATAOUT

AGPIO72/SGPIO_DATAIN

SPKR/AGPIO91

BLINK/USB_OC7_L/AGPIO11

GENINT1_L/AGPIO89
GENINT2_L/AGPIO90

FANIN0/AGPIO84

FANOUT0/AGPIO85

UART0_CTS_L/EGPIO135

UART0_RXD/EGPIO136

UART0_RTS_L/EGPIO137

UART0_TXD/EGPIO138

UART0_INTR/AGPIO139

UART1_RXD/BT_I2S_SDI/EGPIO141

UART1_RTS_L/EGPIO142

UART1_TXD/BT_I2S_SDO/EGPIO143

AMD-CARRIZO_ FP4-BGA968

RC260

RC261

1 2

1 2

1K_0402_5%

1K_0402_5%

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

BD15@

RC262

AGPIO3
AGPIO4
AGPIO5

AGPIO8
AGPIO9

AGPIO40
AGPIO64
AGPIO65

HDA_RST#
HDA_SYNC
HDA_BITCLK

HDA_SDOUT

1 2

1K_0402_5%

RC40
10K_0402_5%

UMA@

1 2

RC269
10K_0402_5%

PX@

1 2

BB2
BB5
BC2
BB4
AY5

BC3
BA3
BC5
BA5
BB6

BA15
AY17

AG5
AG4

AL5
AL6
AJ1
AJ3
AH1
AJ4
AK5
AD8
AG8
AW15
AU15

AT15
AU12
AT14
AR14
BC13

BA17

AN5

BB14
BA19

BC18
BB19

AY9
AW8
AV5
AV8
AW9

AV11
AU7
AT11
AR11
AP9

RC41
10K_0402_5%

NOKBL@

1 2

RC49
2K_0402_5%

1 2

APU_SMB_ CLK
APU_SMB_ DATA

SCL1
SDA1

AGPIO5
LDT_RST_L

LDT_PWRO K
BOARD_ID0
BOARD_ID6
VDDGFX_P D

AGPIO40
AGPIO64

APU_SHUTDOW N#

PCH_TP_INT#

BLINK

HVB_EN
VR_VGA_ PWRGD

PXS_PW REN_R

USB_OC2#

2013/08/15

2013/08/15

2013/08/15

RC257
10K_0402_5%

@

1 2

RC258
2K_0402_5%

KBL@

@

1 2

@

1

TC61

@

1

TC44

@

1

TC71

@

1

TC45

1

@

TC59

1

TC62@

1

TC63@

1

TC64@

1

TC65@

1

TC72@

RPC2

1 4
2 3

@

10K_040 4_4P2R_5%

1

TC67@

1

TC68@

1 2

RC278 0_0402_5%@

1 2

RC109 0_0402_5%@

1 2

RC1654 0_0402_5%

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

RC265
10K_0402_5%

@

1 2

RC264
2K_0402_5%

@

1 2

APU_SMB_ CLK 12,31
APU_SMB_ DATA 12,31

AGPIO3 11

VDDGFX_P D 35

PCH_PW RBT# 3 5

APU_SHUTDOW N# 16

PCH_TP_INT# 36

PCH_BEEP 32

HVB_EN 11,35
VR_VGA_ PWRGD 15,48

+3VALW_APU

RC263
10K_0402_5%

TS@

1 2

RC266
2K_0402_5%

1 2

NOTS@

RC268
2K_0402_5%

@

1 2

ID2--5 internal pull up 40K
ID6 internal pull low 40K

RC267
10K_0402_5%

@

1 2

DIMM1, DIMM2, Mini CARD

VR_GFX_P WRGD 35,50

PXS_PW REN 19,47,4 8

TYPE_C_OCP# 26

2013/08/15

2013/08/15

2013/08/15

1

+1.8VS

TP_I2C0_S CL_R
TP_I2C0_S DA_R

APU_SMB_ CLK
APU_SMB_ DATA

KBRST#
WLAN_CL KREQ#

PCH_BT_OFF#
PCH_WL AN_OFF#

LAN_CLKRE Q#

GATEA20
GPU_CLKRE Q#

APU_SHUTDOW N#
PCH_TP_INT#

PBTN_OUT#
AC_PRESE NT
PCIE_W AKE#_RA

AGPIO5

USB_OC1#
USB_OC2#

AGPIO12
PM_SLP_ S3#

PM_SLP_ S5#

BLINK
VDDGFX_P D

RPC21

23
14

2.2K_04 04_4P2R_5 %

RPC9

23
14

2.2K_04 04_4P2R_5 %
RPC6

18
27
36
45

10K_080 4_8P4R_5%

1 2

RC67 10K_0402_5%

1 2

RC78 10K_0402_5%

1 2

RC64 10K_0402_5%UMA@

1 2

RC96 2K_0402_5%@

1 2

RC1655 10K_0402_5%

RPC15

1 8
2 7
3 6
4 5

10K_080 4_8P4R_5%

RPC16

1 4
2 3

10K_040 4_4P2R_5%

1 2

RC141 10K_0402_5%

1 2

RC203 2.2K_04 02_5%@

1 2

RC208 2.2K_04 02_5%@

1 2

RC158 10K_0402_5%@

1 2

RC247 10K_0402_5%@

+3VS_APU

+3VALW_APU

BLINK isn't strap pin, don't need pull high

AGPIO40

PCH_TP_INT#

VDDGFX_P D

GPU_CLKRE Q#

HDA_BITCLK
HDA_SDIN0 _R
APU_SHUTDOW N#

RSMRST#_R
SYS_PW RGD_R

HDA_SDIN2
HDA_SDIN1

Title

Title

Title

FP4 (GEVENT/GPIO/SD/AZ)

FP4 (GEVENT/GPIO/SD/AZ)

FP4 (GEVENT/GPIO/SD/AZ)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

1 2

RC93 10K_0402_5%

1 2

RC248 10K_0402_5%@

1 2

RC250 10K_0402_5%@

1 2

RC65 2K_0402_5%PX@

1 2

RC90 1K_0402_5%

1 2

RC91 10K_0402_5%@

1 2

RC256 2K_0402_5%@

1 2

RC87 100K_0402_5%

1 2

RC89 100K_0402_5%

1 2

RC241 10K_0402_5%

1 2

RC242 10K_0402_5%

320ABR

320ABR

320ABR

Thursday, January 12, 2017

Thursday, January 12, 2017

Thursday, January 12, 2017

1

7 50

7 50

7 50

0.1

0.1

0.1

5

SATA_PTX_DRX_P034
SATA_PTX_DRX_N034

HDD

CLK_PCI_EC11,35
LPC_CLK111

PXS_RST#

VCC

CLK

DI(IO0)

8M ROM

TPM_CLK30

ODD

+1.05VS

8
7
6
5

D D

1 2

RC270 10K_0402_5%

1 2

RC271 10K_0402_5%

CLK_PCIE_GPU15
CLK_PCIE_GPU#15

CLK_PCIE_W LAN31
CLK_PCIE_W LAN#31

CLK_PCIE_LAN28
CLK_PCIE_LAN#28

C C

+3VS_APU

1 2

RC99 10K_0402_5%@

1 2

RC103 10K_0402_5%

B B

PXS_RST#15

PCH_SPI_CS0#
PCH_SPI_D1
PCH_SPI_D2

A A

UC3

1

/CS

2

DO(IO1)

3

/WP(IO2)

4

GND

W25Q64FW SSIQ_SO8

/HOLDor/RESET(IO3)

SATA_PRX_DTX_N034
SATA_PRX_DTX_P034

SATA_PTX_DRX_P134
SATA_PTX_DRX_N134

SATA_PRX_DTX_N134
SATA_PRX_DTX_P134

1 2

RC113 1K_0402_1%

1 2

RC114 1K_0402_1%

1 2

RC143 10K_0402_5%

CLK_PCIE_GPU CLK_PCIE_GPU_R
CLK_PCIE_GPU# CLK_PCIE_GPU#_R

CLK_PCIE_W LAN CLK_PCIE_W LAN_R

CLK_PCIE_LAN CLK_PCIE_LAN_R
CLK_PCIE_LAN#

PCH_SPI_CLK
PCH_SPI_CS0#

PCH_SPI_D1
PCH_SPI_D0
PCH_SPI_D2
PCH_SPI_D3

50mA

PCH_SPI_D3
PCH_SPI_CLK
PCH_SPI_D0

RC117 0_0402_5%
RC118 0_0402_5%

RC119 0_0402_5%
RC120 0_0402_5%

RC121 0_0402_5%
RC122 0_0402_5%

1 2

RC125 22_0402_5%TPM@

1 2

RC126 3.3_0402_1%

1 2

RC127 0_0402_5%@

LPC_AD030,35
LPC_AD130,35
LPC_AD230,35
LPC_AD330,35

LPC_FRAME#11,30,35

SERIRQ30,35

LPC_CLKRUN#30

RC149

RC209 0_0402_5%
RC202 0_0402_5%
RC144 10K_0402_5%
RC199 0_0402_5%
RC198 0_0402_5%
RC132 0_0402_5%
RC133 0_0402_5%
RC116 0_0402_5%@

CC219 and CC218 should 27pf as EMC suggest

5

1 2
1 2

1 2
1 2

1 2
1 2

TC53 @

1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

PCH_SPI_D2
PCH_SPI_D3
PCH_SPI_CS0#

+1.8VS

1

CC204

0.1U_0201_6.3V6-K

2

4

SATA_PTX_DRX_P0
SATA_PTX_DRX_N0

SATA_PRX_DTX_N0
SATA_PRX_DTX_P0

SATA_PTX_DRX_P1
SATA_PTX_DRX_N1

SATA_PRX_DTX_N1
SATA_PRX_DTX_P1

SATA_CALRN
SATA_CALRP

EGPIO67
EGPIO70
AGPIO130

CLK_PCIE_W LAN#_RCLK_PCIE_W LAN#

CLK_PCIE_LAN#_R

X14M_25M_48M_OSC

1

48M_X1

48M_X2

LPCCLK0
LPCCLK1

1

TC54 @

AGPIO21

10K_0402_5%

SPI_CLK
SPI_CS0#

EGPIO119

SPI_D1
SPI_D0
SPI_D2
SPI_D3

RC254 10K_0402_5%
RC255 10K_0402_5%
RC253 10K_0402_5%

LPCCLK0

4

1 2
1 2
1 2

12

RC282
0_0201_5%

EMC_NS@

1

CC219
22P_0201_25V8

EMC_NS@

2

AU3

SATA_TX0P

AU4

SATA_TX0N

AV1

SATA_RX0N

AV2

SATA_RX0P

AY2

SATA_TX1P

AY1

SATA_TX1N

AW4

SATA_RX1N

AW3

SATA_RX1P

AW1

SATA_ZVSS

AW2

SATA_ZVDDP

AT17

DEVSLP0/EGPIO67

AT12

DEVSLP1/EGPIO70

BB15

SATA_ACT_L/AGPIO130

AU2

SATA_X1

AU1

SATA_X2

U4

GFX_CLKP

U3

GFX_CLKN

U1

GPP_CLK0P

U2

GPP_CLK0N

W4

GPP_CLK1P

W3

GPP_CLK1N

W1

GPP_CLK2P

W2

GPP_CLK2N

Y2

GPP_CLK3P

Y1

GPP_CLK3N

BC10

X25M_48M_OSC

T2

X48M_X1

T1

X48M_X2

AW14

LPCCLK0/EGPIO74

AY13

LPCCLK1/EGPIO75

BB11

LAD0

BA11

LAD1

AY11

LAD2

BA13

LAD3

AV14

LFRAME_L

BA1

ESPI_ALERT_L/LDRQ0_L

BC14

SERIRQ/AGPIO87

BC11

LPC_CLKRUN_L/AGPIO88

AE9

LPC_PD_L/AGPIO21

BC6

SPI_CLK/ESPI_CLK/EGPIO117

BB8

SPI_CS1_L/EGPIO118

AW7

SPI_CS2_L/ESPI_CS_L/EGPIO119

BA9

SPI_DI/ESPI_DATA/EGPIO120

AY7

SPI_DO/EGPIO121

AW11

SPI_WP_L/EGPIO122

BA7

SPI_HOLD_L/EGPIO133

AW12

SPI_TPM_CS_L/AGPIO76

@

+1.8VS

LPCCLK1

EMC

3

UC2E

CLK/SATA/USB/SP I/LPC

FP4 REV 0.93

AMD-CARRIZO_FP4- BGA968

USBCLK/25M_48M_OSC

USB_ZVSS

USB_HSD0P
USB_HSD0N

USB_HSD1P
USB_HSD1N

USB_HSD2P
USB_HSD2N

USB_HSD3P
USB_HSD3N

USB_HSD4P
USB_HSD4N

USB_HSD5P
USB_HSD5N

USB_HSD6P
USB_HSD6N

USB_HSD7P
USB_HSD7N

USB_SS_ZVSS

USB_SS_ZVDDP

USB_SS_0TXP

USB_SS_0TXN

USB_SS_0RXP
USB_SS_0RXN

USB_SS_1TXP

USB_SS_1TXN

USB_SS_1RXP
USB_SS_1RXN

USB_SS_2TXP

USB_SS_2TXN

USB_SS_2RXP
USB_SS_2RXN

USB_SS_3TXP

USB_SS_3TXN

USB_SS_3RXP
USB_SS_3RXN

CLK_USB48M

AP8

USB_RCOMP

AP5

USB20_P0

AR2

USB20_N0

AR1

USB20_P1

AR3

USB20_N1

AR4

USB20_P2

AN2

USB20_N2

AN1

USB20_P3

AN3

USB20_N3

AN4

USB20_P4

AM1

USB20_N4

AM2

USB20_P5

AL2

USB20_N5

AL1

USB20_P6

AL3

USB20_N6

AL4

USB20_P7

AK2

USB20_N7

AJ2

USB3.0 port0 must map to USB2.0 port4,
USB3.0 port1 must map to USB2.0 port5,
USB3.0 port2 must map to USB2.0 port6,
USB3.0 port4 must map to USB2.0 port7

USBSS_CALRN

AD2

USBSS_CALRP

AD1

AA3
AA4

W9
W8

USB30_TX_P1

AA2

USB30_TX_N1

AA1

USB30_RX_P1

W5

USB30_RX_N1

W6

USB30_TX_P2

AC1

USB30_TX_N2

AC2

USB30_RX_P2

Y6

USB30_RX_N2

Y7

USB30_TX_P3

AC4

USB30_TX_N3

AC3

USB30_RX_P3

AB5

USB30_RX_N3

AB6

Connec t the four USB 3.0 ports to onboard devices first
starting from the lower ports and then the remaining
ports can be used for routing to USB 3.0 connectors.
Less than four USB 3.0 ports can be uti lized provided
the unused ports are higher-numbered consecutive
ports.
None of the four USB 3.0 por ts can be configured
as USB 2.0 ext ernal ports.

1

1 2

RC112 11.8K_0402_1%

RC123 1K_0402_1%
RC124 1K_0402_1%

USB30_RX_P1 25
USB30_RX_N1 25

USB30_RX_P2 25
USB30_RX_N2 25

USB30_RX_P3 26
USB30_RX_N3 26

TC69@

USB20_P0 31
USB20_N0 31

USB20_P1 23
USB20_N1 23

USB20_P2 23
USB20_N2 23

USB20_P3 36
USB20_N3 36

USB20_P4 32
USB20_N4 32

USB20_P5 25
USB20_N5 25

USB20_P6 25
USB20_N6 25

USB20_P7 26
USB20_N7 26

1 2
1 2

USB30_TX_P1 25
USB30_TX_N1 25

USB30_TX_P2 25
USB30_TX_N2 25

USB30_TX_P3 26
USB30_TX_N3 26

2

Blue Tooth

Camera

Touch screen

Finger print

Card Reader

LEFT USB (3.0) upper

LEFT USB (3.0) lower

Type C

LEFT USB (3.0) upper

LEFT USB (3.0) lower

Type C

48MHz/10pF Crystal

PCH_SPI_CLK

1 2

RC140 1M _0402_5%

12

RC281
0_0201_5%

EMC_NS@

1

CC218
22P_0201_25V8

EMC_NS@

2

EMC

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2013/08/15

2013/08/15

2013/08/15

RC139
10_0402_5%

EMC_NS@

1 2

1

CC26

10P_0201_25V8G

EMC_NS@

2

EMC

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

1

2

YC2

1

OSC1

NC12OSC2

48MHZ_10PF_7V48000017

CC28
10P_0402_50V8-J

2

NC2

2013/08/15

2013/08/15

2013/08/15

+1.05VALW

4

3

1

48M_X1

48M_X2

change YC2 PN to TXC 48MHZ 10PF X1E000021083400
footprint apply is on going

1

CC29
12P_0402_50V8-J

2

Title

Title

Title

FP4 (SATA/USB/LPC/SPI)

FP4 (SATA/USB/LPC/SPI)

FP4 (SATA/USB/LPC/SPI)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Thursday, January 12, 2017

Thursday, January 12, 2017

Thursday, January 12, 2017

320ABR

320ABR

320ABR

1

8 50

8 50

8 50

0.1

0.1

0.1

5

+1.2V

+1.2V

1

1

22U_0603_6.3V6-M

1

2

10U_0603_6.3V6M

1

2

0.22U_0201_6.3V6-K

CC54

2

+3VS_APU

CC187

1

CC174

2

OK

CC139

CC55

22U_0603_6.3V6-M

1

2

10U_0603_6.3V6M

CC171

10U_0603_6.3V6M

1

CC140

2

0.22U_0201_6.3V6-K

1

2

1

2

1

2

CC56

22U_0603_6.3V6-M

10U_0603_6.3V6M

0.22U_0201_6.3V6-K

+3VS

CC42

2

@

RC214

1 2

0_0402_5%

+1.05VS

CC175

SIT1CD@

+APU_CORE_NB

CC138

D D

C C

OK

VCCRTC

B B

S5_MUX_CTRL: Enable MUX(S0 to S3)-->LOW
Disable MUX(S3 to S0)-->HIGH

A A

1 2

RC231 10K_0402_5%

+1.05VS

1

1

EMC_NS@

EMC_NS@

2

2

CC224

CC225

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

OK EMC

APU_S5_MUX_CTRL7

1

CC37

2

APU_S5_MUX_CTRL

5

1

1

CC57

2

22U_0603_6.3V6-M

Wake-on-Ring not supported:
+VDDIO_AZ_APU Connect to +1.5V S0 rail

+1.8VS

1

CC167

2

10U_0603_6.3V6M

1

CC142

CC141

2

0.22U_0201_6.3V6-K

AP2138N-1.5TRG1_SOT23-3

1U_0402_6.3V6K

1

2

22U_0603_6.3V6-M

CC186

1

2

SIT1CD@

+3VALW_APU

CC58

2

22U_0603_6.3V6-M

SIT1CD@

1

CC173

2

10U_0603_6.3V6M

1

CC178

2

0.22U_0201_6.3V6-K

1

CC143

2

0.22U_0201_6.3V6-K

UC5

1

Vin

2

GND

12

RC230
100K_0402_5%

@

12

RC272

100K_0402_5%

@

1

CC59

2

22U_0603_6.3V6-M

1

2

0.22U_0201_6.3V6-K

1

CC177

2

1

CC144

2

0.22U_0201_6.3V6-K

SIT1CD@

Vout

1

CC60

2

@

22U_0603_6.3V6-M

SIT1CD@

+1.8VALW

CC197

0.22U_0201_6.3V6-K

SIT1CD@

1

CC146

2

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

3

1

CC194

2

1

CC53

2

1

2

0.22U_0201_6.3V6-K

CC145

+RTCBATT

1U_0402_6.3V6K

1

CC61

2

@

22U_0603_6.3V6-M

1

CC188

2

1

CC198

2

0.22U_0201_6.3V6-K

1

2

180P_0402_50V8-J

1

CC62

2

22U_0603_6.3V6-M

22U_0603_6.3V6-M

SIT1CD@

1 2

RC210 0_0805_5%

1

CC189

2

10U_0603_6.3V6M

0.22U_0201_6.3V6-K

1

CC201

CC202

2

0.22U_0201_6.3V6-K

1

CC195

CC196

2

@

@

0.22U_0201_6.3V6-K

follow CRB reserve

12

1

CC157

2

1

CC203

2

0.22U_0201_6.3V6-K

1

2

@

0.22U_0201_6.3V6-K

JCMOS1
SHORT PADS

@

1

2

CC199

4

1

1

CC158

CC159

2

2

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

@

1

2

D

S

0.22U_0201_6.3V6-K

SIT1CD@

OK

1 2

RC212 0_0402_5%

+1.05VS_GFX_APU+1.05VS

1

12

CC180

2

RC229

100_0402_5%

+3VALW_APU

1

1

CC191

CC190

2

2

10U_0603_6.3V6M

1

CC217
47P_0402_50V8J

RF_NS@

2

180P_0402_50V8-J

1

CC200

2

@

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

12

RC8

@

470_0603_5%

13

QC7

EC_RTCRST#_ON

2

G

2N7002KW_SOT323-3

@

4

1

CC160

2

0.22U_0201_6.3V6-K

CC181

10U_0603_6.3V6M

0.22U_0201_6.3V6-K

12

1

CC161

2

0.22U_0201_6.3V6-K

SIT1CD@

+VDDIO_AZ_APUDVDD_IO

SIT1CD@

1

2

0.22U_0201_6.3V6-K

+1.05VALW

RC15
100K_0402_5%

@

1

CC163

2

0.22U_0201_6.3V6-K

1

CC184

CC185

2

1U_0402_6.3V6K

1

CC182

2

+RTCBATT

RC6

EC_RTCRST#_ON 35

1

2

1U_0402_6.3V6K

10U_0603_6.3V6M

1

CC165

2

180P_0402_50V8-J

1

CC193

2

1

CC183

2

0.22U_0201_6.3V6-K

1 2

1K_0402_5%

+1.2V

3A

1U_0402_6.3V6K

0.2A

1.5A

0.2A

1.5A

0.5A

0.2A

0.8A

+VDDCR_FCH_S5

0.2A

+1.05VS

7A

+APU_CORE_NB

12A

+RTCBATT_APU

CC192

P25
P28
T24
T27
U25
U28
V30

V33
W24
W27

Y25

Y28

Y30

AB24
AB27
AB30
AB33
AD25
AD28
AD30
AE24
AE27
AF30
AF33
AG25
AG28
AH24
AH27
AH30
AK25
AK28
AK30
AK33

AL27

AM30

AR19

AE6

AE5

AP19
AP21

AP16
AP18

AP10

AR9

AP15
AR15

AN12
AP12

AP13
AR12

AW19

AU17
AU19
AV17
AV19

AW17

AL12
AL13
AL15
AL18
AL21

AN13
AN16
AN19
AN22

AR17

1

2

0.22U_0201_6.3V6-K

VDDIO_MEM_S3_1
VDDIO_MEM_S3_2
VDDIO_MEM_S3_3
VDDIO_MEM_S3_4
VDDIO_MEM_S3_5
VDDIO_MEM_S3_6
VDDIO_MEM_S3_7
VDDIO_MEM_S3_8
VDDIO_MEM_S3_9
VDDIO_MEM_S3_10
VDDIO_MEM_S3_11
VDDIO_MEM_S3_12
VDDIO_MEM_S3_13
VDDIO_MEM_S3_14
VDDIO_MEM_S3_15
VDDIO_MEM_S3_16
VDDIO_MEM_S3_17
VDDIO_MEM_S3_18
VDDIO_MEM_S3_19
VDDIO_MEM_S3_20
VDDIO_MEM_S3_21
VDDIO_MEM_S3_22
VDDIO_MEM_S3_23
VDDIO_MEM_S3_24
VDDIO_MEM_S3_25
VDDIO_MEM_S3_26
VDDIO_MEM_S3_27
VDDIO_MEM_S3_28
VDDIO_MEM_S3_29
VDDIO_MEM_S3_30
VDDIO_MEM_S3_31
VDDIO_MEM_S3_32
VDDIO_MEM_S3_33
VDDIO_MEM_S3_34
VDDIO_MEM_S3_35

VDDIO_AUDIO

VDDP_GFX_2
VDDP_GFX_1

VDD_33_1
VDD_33_2

VDD_18_1
VDD_18_2

VDD_18_S5_1
VDD_18_S5_2

VDD_33_S5_1
VDD_33_S5_2

VDDP_S5_1
VDDP_S5_2

VDDCR_FCH_S5_1
VDDCR_FCH_S5_2

VDDP_6
VDDP_1
VDDP_2
VDDP_3
VDDP_4
VDDP_5

VDDCR_NB_1
VDDCR_NB_2
VDDCR_NB_3
VDDCR_NB_4
VDDCR_NB_5
VDDCR_NB_6
VDDCR_NB_7
VDDCR_NB_8
VDDCR_NB_9

VDDBT_RTC_G

AMD-CARRIZO_FP4-BGA968@

3

POWER

FP4 REV 0.93

UC2F

VDDCR_CPU_1
VDDCR_CPU_2
VDDCR_CPU_3
VDDCR_CPU_4
VDDCR_CPU_5
VDDCR_CPU_6
VDDCR_CPU_7
VDDCR_CPU_8

VDDCR_CPU_9
VDDCR_CPU_10
VDDCR_CPU_11
VDDCR_CPU_12
VDDCR_CPU_13
VDDCR_CPU_14
VDDCR_CPU_15
VDDCR_CPU_16
VDDCR_CPU_17
VDDCR_CPU_18
VDDCR_CPU_19
VDDCR_CPU_20
VDDCR_CPU_21
VDDCR_CPU_22
VDDCR_CPU_23
VDDCR_CPU_24
VDDCR_CPU_25
VDDCR_CPU_26
VDDCR_CPU_42
VDDCR_CPU_31
VDDCR_CPU_43
VDDCR_CPU_32
VDDCR_CPU_44
VDDCR_CPU_33
VDDCR_CPU_45
VDDCR_CPU_34
VDDCR_CPU_46
VDDCR_CPU_35
VDDCR_CPU_47
VDDCR_CPU_36
VDDCR_CPU_28
VDDCR_CPU_29
VDDCR_CPU_40
VDDCR_CPU_30
VDDCR_CPU_37
VDDCR_CPU_49
VDDCR_CPU_38
VDDCR_CPU_39
VDDCR_CPU_48
VDDCR_CPU_41
VDDCR_CPU_27

VDDCR_GFX_14
VDDCR_GFX_15
VDDCR_GFX_16
VDDCR_GFX_17
VDDCR_GFX_18
VDDCR_GFX_19
VDDCR_GFX_20
VDDCR_GFX_21
VDDCR_GFX_22
VDDCR_GFX_23
VDDCR_GFX_24
VDDCR_GFX_25
VDDCR_GFX_26
VDDCR_GFX_27
VDDCR_GFX_28
VDDCR_GFX_29

VDDCR_GFX_1

VDDCR_GFX_2

VDDCR_GFX_3

VDDCR_GFX_4

VDDCR_GFX_5

VDDCR_GFX_6

VDDCR_GFX_7

VDDCR_GFX_8

VDDCR_GFX_9
VDDCR_GFX_10
VDDCR_GFX_11
VDDCR_GFX_12
VDDCR_GFX_30
VDDCR_GFX_31
VDDCR_GFX_32
VDDCR_GFX_33
VDDCR_GFX_34
VDDCR_GFX_35
VDDCR_GFX_36
VDDCR_GFX_37
VDDCR_GFX_13

U8
W7
W12
W15
W18
W21
Y8
Y10
Y13
Y16
Y19
Y22
AB7
AB9
AB12
AB15
AB18
AB21
AD6
AD10
AD13
AD16
AD19
AD22
AE7
AE12
AK9
AG10
AK10
AG13
AK13
AG16
AK16
AG19
AK19
AG22
AK22
AH7
AE18
AE21
AH21
AG6
AH12
AN6
AH15
AH18
AL7
AK6
AE15

L8
L13
L16
L19
L22
N7
N12
N15
N18
N21
P8
P13
P16
P19
P22
T7
F12
F15
G11
G14
J8
J9
J11
K7
K12
K13
K15
K16
T12
T15
T18
T21
U13
U16
U19
U22
K19

+APU_CORE

+APU_GFX

+APU_CORE

1

CC129

CC130

2

0.22U_0201_6.3V6-K

SIT1CD@

OK

+APU_GFX

1

CC147

CC148

2

0.22U_0201_6.3V6-K

OK

+1.2V

1

CC168

2

SIT1CD@

VDDCR_CPU

VDDCR_NB

VDDCR_GFX

VDDIO_MEM_S3

VDDCR_FCH_S5

VDDP

VDDP_GFX

VDDP_S5

VDD_18

VDD_18_S5

VDD_33

VDD_33_S5

1

2

1

2

0.22U_0201_6.3V6-K

VDDIO_AUDIO

VDDBT_RTC_G

QC1/QC2/QC3/QC4 Rds on should less possible, CRB is 11.8mohm,
there is no load swtich for 0.775V power, so it need mos

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS

THIS

THIS

SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTU RE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTU RE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTU RE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2013/08/15

2013/08/15

2013/08/15

2

1

CC134

2

0.22U_0201_6.3V6-K

1

CC152

2

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

+0.775VALW

1

CC135

2

0.22U_0201_6.3V6-K

CC153

0.22U_0201_6.3V6-K

1

CC179

2

12

CC208

10U_0603_6.3V6M

@

1

2

180P_0402_50V8-J

+VDDCR_FCH_S5

1

1

CC136

2

2

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

1

1

CC154

CC156

2

2

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

1

CC176

2

180P_0402_50V8-J

SIT1CD@

9*22uf 0805
8*0.22uf 0402
1*180pf 0402
4*22uf 0805
8*0.22uf 0402
1*180pf 0402
10*22uf 0805
9*0.22uf 0402
1*180pf 0402
8*22uf 0603
6*0.22uf 0402 split*4
1*180pf 0402 split*2
2*10uf 0603
1*0.22uf 0402

4*10uf 0603
1*0.22uf 0402
1*180pf 0402
1*10uf 0603
1*0.22uf 0402

1*10uf 0603
1*0.22uf 0402

1*22uf 0603
1*10uf 0402

1*10uf 0603
1*0.22uf 0402

1*10uf 0603

1*10uf 0403
1*0.22uf 0402

3*1uf 0402

1*0.22uf 0402

1

CC128

CC126

2

22U_0603_6.3V6-M

+5VALW

1

CC209

2

@

2013/08/15

2013/08/15

2013/08/15

1

1

CC131

CC133

CC132

2

2

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

SIT1CD@

1

1

1

CC151

CC149

CC150

2

2

2

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

SIT1CD@

SIT1CD@

1

1

1

CC172

CC169

CC170

2

2

2

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

DECOUPLING BETWEEN PROCESSOR AND DIMMs
ACROSS VDDIO AND VSS SPLIT

Design Guide CRBG FP4

9*22uf 0603
8*0.22uf 0402
1*180pf 0402
4*22uf 0603
8*0.22uf 0402
1*180pf 0402
9*22uf 0603
9*0.22uf 0402
1*180pf 0402
8*22uf 0603
6*0.22uf 0402 split*4
1*180pf 0402 split*2
2*10uf 0402
1*0.22uf 0402

4*10uf 0402
1*0.22uf 0402
1*180pf 0402
1*10uf 0402
1*0.22uf 0402

1*10uf 0402
1*0.22uf 0402

1*22uf 0603
1*10uf 0402

1*10uf 0402
1*0.22uf 0402

1*10uf 0402

1*10uf 0402
1*0.22uf 0402

3*1uf 0402

1*0.22uf 0402

+APU_CORE_NB

12

CC207

10U_0603_6.3V6M

@

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

ciphered Date

ciphered Date

ciphered Date

De

De

De

2

1

CC137

2

0.22U_0201_6.3V6-K

1

2

4.7U_0402_6.3V6M

1U_0402_6.3V6K

180P_0402_50V8-J

1

CC155

2

180P_0402_50V8-J

13*22uf 0603
8*0.22uf 0402
1*180pf 0402
6*22uf 0603
8*0.22uf 0402 split *5
1*180pf 0402
13*22uf 0603
9*0.22uf 0402
1*180pf 0402
8*22uf 0603
8*0.22uf 0402 split*4
1*180pf 0402 split*2
2*10uf 0603
1*0.22uf 0402

4*10uf 0603
1*0.22uf 0402
1*180pf 0402
1*10uf 0603
1*0.22uf 0402

1*10uf 0603
1*0.22uf 0402

1*22uf 0603
1*10uf 0603

1*10uf 0603
1*0.22uf 0402

1*10uf 0603

1*10uf 0603
1*0.22uf 0402

3*1uf 0402

1*0.22uf 0402

1

1

CC164

CC162

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

SIT1CD@

Decoupling cap
near APU ball

UC7

1

VOUT_1

VIN1_1

2

VIN1_2

VOUT_2

3

SEL

VIN2

VCC4EN

GND

G5018RD1U_TDFN8_3X3

T

T

T

itle

itle

itle

FP4 (POWE

FP4 (POWE

FP4 (POWE

e

e

e

Siz

Siz

Siz

ocument Number Rev

ocument Number Rev

ocument Number Rev

D

D

D

Custom

Custom

Custom

Thurs

Thurs

Thurs

Date: Sheet

Date: Sheet

Date: Sheet

1

1

CC166

2

0.22U_0201_6.3V6-K

8

7

6

5

9

R&DECOUPLING)

R&DECOUPLING)

R&DECOUPLING)

day, January 12, 2017

day, January 12, 2017

day, January 12, 2017

1 2

RC277 0_0603_5%

APU_S5_MUX_CTRL

320ABR

320ABR

320ABR

1

+VDDCR_FCH_S5

f

9 50

f

9 50

f

9 50

o

o

o

0.1

0.1

0.1

5

4

3

2

1

UC2G

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62

GND

FP4 REV 0.93

AMD-CARR IZO_FP4-BGA968@

VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98

VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124

L28
M4
M30
N10
N13
N16
N19
N22
N27
P1
P2
P4
P5
P12
P15
P18
P21
P30
P33
T4
T10
T13
T16
T19
T22
T30
U5
U12
U15
U18
U21
U24
V1
V2
V4
W10
W13
W16
W19
W22
Y4
Y5
Y12
Y15
Y18
Y21
Y24
AB1
AB2
AB4
AB10
AB13
AB16
AB19
AB22
AD4
AD9
AD12
AD15
AD18
AD21
AD24

AE10
AE13
AE16
AE19
AE22

AF1
AF4

AG9
AG12
AG15
AG18
AG21

AH4
AH10
AH13
AH16
AH19
AH22

AK1

AK4
AK12
AK15
AK18

AL16
AL19
AL22

AM4

AN9
AN10
AN15
AN18
AN21
AN25
AN28

AP1
AP2
AP4

AP7
AP22
AP27
AP30
AP33

AR6
AR25
AR28

AT4
AT19
AT22
AT30

AU5

AU8
AU11
AU14
AU20
AU23
AU27

AV4
AV7

AV9
AV12
AV15
AV25

VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186

A8
A12
A16
A20
A24

D D

C C

B B

A28
A32

B12
B33

D10
D12
D14
D16
D18
D20
D22
D24
D26
D28
D30

F19
F22
F25
F30
F33

G17
G20
G23
G26

H30

K10
K22
K27
K30
K33

L12
L15
L18
L21
L25

J15
J19
J22
J25
J28

B2

B8

C3

D4

D6

D8

F1
F2
F4
F9

G7

H4

J5

K1
K2
K4

L5

GND

FP4 REV 0.93

AMD-CARR IZO_FP4-BGA968@

UC2H

VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212

VSS_213
VSS_215
VSS_214

AV30
AV33
AW22
AY4
AY6
AY8
AY10
AY12
AY14
AY16
AY20
AY22
AY24
AY26
AY28
AY30
BB1
BB33
BC4
BC8
BC12
BC16
BC20
BC24
BC28
BC32

L24
AL10
AK21

UC2J

1

TC4@

1

TC6@

1

TC5@

U30
U31

AN30

RSVD_2
RSVD_3
RSVD_4

@

FP4 REV 0.93

AMD-CARR IZO_FP4-BGA968

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

2013/08/15

2013/08/15

2013/08/15

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

3

2013/08/15

2013/08/15

2013/08/15

Title

FP4 (VSS)

FP4 (VSS)

FP4 (VSS)

Size

Size

Size

Document Num ber Rev

Document Num ber Rev

Document Num ber Rev

C

C

C

ustom

ustom

ustom

Thursday

Thursday

Date: Shee t o f

Date: Shee t o f

Date: Shee t o f

2

Thursday

320ABR

320ABR

320ABR

, January 12, 2017

, January 12, 2017

, January 12, 2017

10 50

10 50

10 50

1

0.1

0.1

0.1

5

4

+3VS +3VS +3VS +3VALW_APU +3VALW_APU +3VALW_APU +3VS_APU

3

2

1

12

RC152

D D

LPC_FRAME#8,30,35

LPC_CLK18

CLK_PCI_EC8,35

AGPIO37

SYS_RESET#7

SUSCLK7,31

HVB_EN7,35

C C

10K_0402_5%

12

RC159
2K_0402_5%

@

12

RC153
10K_0402_5%

12

RC160
2K_0402_5%

@

12

RC154
10K_0402_5%

@

12

RC161
2K_0402_5%

12

RC155
10K_0402_5%

12

RC162
2K_0402_5%

@

12

RC156
10K_0402_5%

12

RC163
2K_0402_5%

@

12

RC157
10K_0402_5%

12

RC164
2K_0402_5%

@

RC81
10K_0402_5%

@

1 2

12

RC79

0_0402_5%

@

STRAP PINS

LFRAME_L LPCCLK1 LPCCLK0 AGPIO3SYS_RESET_L

Signal

Type

PULL

HIGH

B B

PULL
LOW

II

SPI ROM

LPC ROM

II II I

Internal
CLK Gen

DefaultDef ault

Reser ved

Boot Fail Timer
Enabled

Boot Fail Timer
Disabled

Default

RTCCLK

I

RTC Coin Battery is
implem ented

Default

RTC Coin Battery is
not implemented

Normal Power Up
&Reset Timing

Default

Reserved

Int pull-upInt pull-upInt pull-up

I

Enhanced reset
logic (for quicker
S5 resume)

Default

traditional
reset logic

HVB_EN

floating

Disable HVB
on FP4 platforms

Default

connected to VSS

Enable HVB
on FP4 platforms

Type I straps become valid immediately after capture with the rising edge of RSMRST_L,they are captured only once when power is first applied to the processor

Type II straps become valid after PWR_GOOD is asserted,straps are captured every time the systems powers up from the S5 state. A transition from S3 to S0 does not trigger capture.
Type II straps should be pulled up to S0 power rail to prevent leakage when the signal is connected to a device in S0 power domain.

If the LPC bus is connected to devices that are on S0 power rail, then a pull-up resistor to VDD_33 is implemented.

All Strap pins must be configured with either external pull-up or pull-down resistors.

Platforms that are designed for AOAC complaint are recommended to use the Alternate Reset by strapping this pin to ‘ 1’ fo r CZ
AGPIO3

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2013/08/15

2013/08/15

2013/08/15

3

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2013/08/15

2013/08/15

2013/08/15

2

Title

FP4 (STRAPS)

FP4 (STRAPS)

FP4 (STRAPS)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Thursday, January 12, 2017

Thursday, January 12, 2017

Thursday, January 12, 2017

320ABR

320ABR

320ABR

11 50

11 50

11 50

1

0.1

0.1

0.1

5

JDDR1A

D D

C C

+1.2V

RD273 240_0402_1%@
RD274 240_0402_1%@

DDRA_CKE05

DDRA_BG15
DDRA_BG05

B B

A A

+1.2V

12

+3VS +3VS

12

RD26

10K_0402_5%

@

12

RD268
0_0402_5%

DDRA_DQ1

DDRA_DQS#0
DDRA_DQS0

DDRA_DQ3

DDRA_DQ2

DDRA_DQ9

DDRA_DQ13

DDRA_DM1

DDRA_DQ14 DDRA_DQ15

DDRA_DQ11 DDRA_DQ10

DDRA_DQ21

DDRA_DQ20

DDRA_DQS#2
DDRA_DQS2

DDRA_DQ23

DDRA_DQ19

DDRA_DQ29

DDRA_DQ25

DDRA_DM3

DDRA_DQ31

DDRA_DQ30

1 2
1 2

DDRA_CKE0

DDRA_BG1
DDRA_BG0

DDRA_MA12
DDRA_MA9

DDRA_MA8
DDRA_MA6 DDRA_MA4

RD258
1K_0402_1%

DDR4_ALERT

+3VS

12

RD269

10K_0402_5%

1 2

@

RD28
0_0402_5%

@

DDRA0_SA0 DDRA0_SA1 DDRA0_SA2

1

VSS_1

3

DQ5

5

VSS_3

7

DQ1

9

VSS_5

11

DQS0_C

DM0_n/DBIO_n/NC

13

DQS0_t

15

VSS_8

17

DQ7

19

VSS_10

21

DQ3

23

VSS_12

25

DQ13

27

VSS_14

29

DQ9

31

VSS_16

33

DM1_n/DBl1_ n/NC

35

VSS_17

37

DQ15

39

VSS_19

41

DQ10

43

VSS_21

45

DQ21

47

VSS_23

49

DQ17

51

VSS_25

53

DQS2_c

DM2_n/DBl2_ n/NC

55

DQS2_t

57

VSS_28

59

DQ23

61

VSS_30

63

DQ19

65

VSS_32

67

DQ29

69

VSS_34

71

DQ25

73

VSS_36

75

DM3_n/DBl3_ n/NC

77

VSS_37

79

DQ30

81

VSS_39

83

DQ26

85

VSS_41

87

CB5/NC

89

+1.2V +1.2V

VSS_43

91

CB1/NC

93

VSS_45

95

DQS8_c

DM8_n/DBI8_n/NC

97

DQS8_t

99

VSS_48

101

CB2/NC

103

VSS_50

105

CB3/NC

107

VSS_52

109

CKE0

111

VDD_1

113

BG1

115

BG0

117

VDD_3

119

A12

121

A9

123

VDD_5

125

A8

127

A6

129

VDD_7

ARGOS_D4AS0-26001-1P60

ME@

+1.2V

12

RD11

1K_0402_1%

1 2

12

RD270

10K_0402_5%

@

RD29
0_0402_5%

@

1 2

VSS_2

VSS_4

VSS_6

VSS_7

VSS_9

VSS_11

VSS_13

VSS_15
DQS1_c

DQS1_t

VSS_18

VSS_20

VSS_22

VSS_24

VSS_26

VSS_27

VSS_29

VSS_31

VSS_33

VSS_35
DQS3_c

DQS3_t

VSS_38

VSS_40

VSS_42
CB4/NC
VSS_44
CB0/NC
VSS_46

VSS_47
CB6/NC
VSS_49
CB7/NC
VSS_51

RESET_n

VDD_2
ACT_n

ALERT_n

VDD_4

VDD_6

VDD_8

RD10
1K_0402_1%

15mil

1

2

CD262

0.1U_0201_6.3V6-K

DQ12

DQ14

DQ11

DQ20

DQ16

DQ22

DQ18

DQ28

DQ24

DQ31

DQ27

CKE1

2

DDRA_DQ4

4

DQ4

6

DDRA_DQ5DDRA_DQ6

8

DQ0

10

DDRA_DM0

12
14

DDRA_DQ0

16

DQ6

18

DDRA_DQ7

20

DQ2

22

DDRA_DQ12

24
26

DDRA_DQ8

28

DQ8

30

DDRA_DQS#1

32

DDRA_DQS1

34
36
38
40
42
44

DDRA_DQ16

46
48

DDRA_DQ17

50
52

DDRA_DM2

54
56

DDRA_DQ22

58
60

DDRA_DQ18

62
64

DDRA_DQ24

66
68

DDRA_DQ28

70
72

DDRA_DQS#3

74

DDRA_DQS3

76
78

DDRA_DQ26

80
82

DDRA_DQ27

84
86
88
90
92
94
96
98
100
102
104
106

MEM_MA_RST#

108

DDRA_CKE1

110
112

DDRA_ACT#

114

DDR4_ALERT

116
118

DDRA_MA11

120

A11

A7

A5
A4

1

2

CD116

122
124
126
128
130

+VREF_CA

0.1U_0201_6.3V6-K

CD117

DDRA_MA7

DDRA_MA5

1

2

1000P_0201_50V7-K

4

for MEM_MB_RST# overshoot issue

DDRA_CKE1 5

DDRA_ACT# 5

+3VS +VDDSPD

RD271 0_0402_5%

+2.5VS

RD272 0_0402_5%@

1 2

1 2

CD120

1

2

@

0.1U_0201_6.3V6-K

Layout Note: Place near JDDR1

+0.6VS

0.1U_0201_6.3V6-K

1

1

CD251

CD249

@

@

+2.5V

CD122

2

2

follow CRB 1pcs 1uf + 2pcs 0.1uf + 1pcs 180pf

1U_0402_6.3V6K

1

1

CD123

2

2

MEM_MA_RST# 5

0.1U_0201_6.3V6-K

CD250

0.1U_0201_6.3V6-K

CD124

1

2

1

2

0.1U_0201_6.3V6-K

CD248

0.1U_0201_6.3V6-K

CC206

+VDDSPD

1U_0402_6.3V6K

4.7U_0402_6.3V6M

1

2

180P_0402_50V8-J

1

2

3

+1.2V

JDDR1B

DDRA_MA3
DDRA_MA1

DDRA_CLK05
DDRA_CLK0#5

RD259 0_0402_5%

DDRA_BA15

DDRA_CS0#5

DDRA_MA14_WE#5

DDRA_ODT05

DDRA_CS1#5

DDRA_ODT15

APU_SMB_CLK7,31 APU_SMB_DATA 7,31

1

1

CD29

CD28

0.1U_0201_6.3V6-K

2

2

+1.2V

0.1U_0201_6.3V6-K

1

CD16

2

+1.2V

1

CD261

@

2

DDRA_CLK0 DDRA_CLK1
DDRA_CLK0#

1 2

DDRA_BA1

DDRA_CS0#
DDRA_MA14_WE#

DDRA_ODT0
DDRA_CS1#

DDRA_ODT1

DDRA_DQ33

DDRA_DQ32

DDRA_DQS#4
DDRA_DQS4

DDRA_DQ35

DDRA_DQ34

DDRA_DQ41

DDRA_DQ45

DDRA_DM5

DDRA_DQ42

DDRA_DQ43

DDRA_DQ48 DDRA_DQ49

DDRA_DQS#6
DDRA_DQS6

DDRA_DQ51

DDRA_DQ55

DDRA_DQ60

DDRA_DQ57

DDRA_DM7

DDRA_DQ63

APU_SMB_CLK APU_SMB_DATA

+2.5V

CD121

22P_0402_50V8-J

RF_NS@

RF

follow CRB 6pcs 0.1uffollow CRB 1pcs 4.7uf + 1pcs 0.1uf

0.1U_0201_6.3V6-K

1

1

CD18

CD17

2

2

1

CD63

CD66

@

@

2

10U_0603_6.3V6M

10U_0603_6.3V6M

131

A3

133

A1

135

VDD_9

137

CK0_t

139

CK0_c

141

VDD_11

143

Parity

145

BA1

147

VDD_13

149

CS0_n

151

WE_n/A14

153

VDD_15

155

ODT0

157

CS1_n

159

VDD_17

161

ODT1

163

VDD_19

165

C1/CS3_n/NC

167

VSS_53

169

DQ37

171

VSS_55

173

DQ33

175

VSS_57

177

DQS4_c

DM4_n/DBl4_ n/NC

179

DQS4_t

181

VSS_60

183

DQ38

185

VSS_62

187

DQ34

189

VSS_64

191

DQ44

193

VSS_66

195

DQ40

197

VSS_68

199

DM5_n/DBl5_ n/NC

201

VSS_69

203

DQ46

205

VSS_71

207

DQ42

209

VSS_73

211

DQ52

213

VSS_75

215

DQ49

217

VSS_77

219

DQS6_c

DM6_n/DBl6_ n/NC

221

DQS6_t

223

VSS_80

225

DQ55

227

VSS_82

229

DQ51

231

VSS_84

233

DQ61

235

VSS_86

237

DQ56

239

VSS_88

241

DM7_n/DBl7_ n/NC

243

VSS_89

245

DQ62

247

VSS_91

249

DQ58

251

VSS_93

253

SCL

255

VDDSPD

257

VPP_1

259

CD20

CD67

@

VPP_2

261

GND_1

ARGOS_D4AS0-26001-1P60

ME@

0.1U_0201_6.3V6-K

1

CD21

2

1

2

22U_0603_6.3V6-M

0.1U_0201_6.3V6-K

1

2

1

CD19
22P_0402_50V8-J

RF@

2

CD22

1

2

0.1U_0201_6.3V6-K

1

2

22U_0603_6.3V6-M

EVENT_n

VDD_10

CK1_t

CK1_c

VDD_12

A10/AP

VDD_14

RAS_n/A16

VDD_16

CAS_n/A15

VDD_18

C0/CS2_n/NC

VREFCA

VSS_54

DQ36

VSS_56

DQ32

VSS_58

VSS_59

DQ39

VSS_61

DQ35

VSS_63

DQ45

VSS_65

DQ41
VSS_67
DQS5_c

DQS5_t

VSS_70

DQ47
VSS_72

DQ43
VSS_74

DQ53
VSS_76

DQ48
VSS_78

VSS_79

DQ54
VSS_81

DQ50
VSS_83

DQ60
VSS_85

DQ57
VSS_87
DQS7_c

DQS7_t

VSS_90

DQ63
VSS_92

DQ59
VSS_94

GND_2

0.1U_0201_6.3V6-K

1

2

A2

A0

BA0

A13

SA2

SDA
SA0

Vtt

SA1

CD23

1

2

132
134
136
138
140
142
144

146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
210
212
214
216
218
220
222
224
226
228
230
232
234
236
238
240
242
244
246
248
250
252
254
256
258
260

262

@

CD260
22P_0402_50V8-J

RF@

+1.2V

DDRA_MA2
MEM_MA_EVENT#

DDRA_CLK1#

DDRA_MA0

DDRA_MA10

DDRA_BA0
DDRA_MA16_RAS#

DDRA_MA15_CAS#
DDRA_MA13

DDRA0_SA2

DDRA_DQ36

DDRA_DQ37

DDRA_DM4

DDRA_DQ39

DDRA_DQ38

DDRA_DQ40

DDRA_DQ44

DDRA_DQS#5
DDRA_DQS5

DDRA_DQ46

DDRA_DQ47

DDRA_DQ52DDRA_DQ53

DDRA_DM6

DDRA_DQ50

DDRA_DQ54

DDRA_DQ56

DDRA_DQ61

DDRA_DQS#7
DDRA_DQS7

DDRA_DQ58

DDRA_DQ59DDRA_DQ62

DDRA0_SA0

DDRA0_SA1

LP2301ALT1G_SOT23-3

SUSP24,37

0.1U_0201_6.3V6-K

1

1

CD58

EMC@

2

2

1

2

2

DDRA_DQ[0..63]

DDRA_DQS[0..7]

DDRA_DQS#[0..7]

DDRA_MA[0..13]

DDRA_DM[0..7]

QD1

27P 25V J NPO 0201

CD59

@

CD12
22P_0402_50V8-J

RF@

S

G

2

@

0.1U_0201_6.3V6-K

1

2

RF

MEM_MA_EVENT# 5

DDRA_CLK1 5
DDRA_CLK1# 5

DDRA_BA0 5

DDRA_MA16_RAS# 5

DDRA_MA15_CAS# 5

+VREF_CA

+0.6VS

D

13

1

CD60

EMC@

2

+2.5VS+2.5V

27P 25V J NPO 0201

DDRA_DQ[0..63] 5

DDRA_DQS[0..7] 5

DDRA_DQS#[0..7] 5

DDRA_MA[0..13] 5

DDRA_DM[0..7] 5

0.1U_0201_6.3V6-K

1

CD61

@

2

CD62

1

Swap Table

Net NamePin Name

DDRB_DQ6

DQ0

DDRB_DQ5

DQ1

DDRB_DQ3

DQ2

DDRB_DQ7

DQ3

DDRB_DQ4

DQ4

DDRB_DQ0

DQ5

DDRB_DQ1

DQ6

DDRB_DQ2

DQ7

DDRB_DQS#0

DQS#0

DDRB_DQS0

DQS0

DDRB_DQ8

DQ8

DDRB_DQ13

DQ9

DDRB_DQ11

DQ10

DDRB_DQ10

DQ11

DDRB_DQ12

DQ12

DDRB_DQ9

DQ13

DDRB_DQ15

DQ14

DDRB_DQ14

DQ15

DDRB_DQS#1

DQS#1

DDRB_DQS1

DQS1

DQ16

DDRB_DQ20

DQ17

DDRB_DQ16

DQ18

DDRB_DQ18

DQ19

DDRB_DQ19

DQ20

DDRB_DQ17

DQ21

DDRB_DQ21

DQ22

DDRB_DQ22

DQ23

DDRB_DQ23

DQS#2

DDRB_DQS#2

DQS2

DDRB_DQS2

DDRB_DQ28

DQ24

DDRB_DQ25

DQ25

DDRB_DQ31

DQ26

DDRB_DQ27

DQ27

DDRB_DQ24

DQ28

DDRB_DQ29

DQ29

DDRB_DQ26

DQ30

DDRB_DQ30

DQ31

DDRB_DQS#3

DQS#3

DDRB_DQS3

DQS3

DDRB_DQ33

DQ32

DDRB_DQ37

DQ33

DDRB_DQ34

DQ34

DDRB_DQ38

DQ35

DDRB_DQ36

DQ36

DDRB_DQ32

DQ37

DDRB_DQ35

DQ38

DDRB_DQ39

DQ39

DDRB_DQS#4

DQS#4

DDRB_DQS4

DQS4

DDRB_DQ45

DQ40

DDRB_DQ44

DQ41

DDRB_DQ46

DQ42

DDRB_DQ42

DQ43

DDRB_DQ41

DQ44

DDRB_DQ40

DQ45

DDRB_DQ47

DQ46

DDRB_DQ43

DQ47

DDRB_DQS#5

DQS#5

DDRB_DQS5

DQS5

DQ48

DDRB_DQ49

DQ49

DDRB_DQ48

DQ50

DDRB_DQ54

DQ51

DDRB_DQ55

DQ52

DDRB_DQ53

DQ53

DDRB_DQ52

DQ54

DDRB_DQ50

DQ55

DDRB_DQ51

DQS#6

DDRB_DQS#6

DQS6

180P_0402_50V8-J

0.1U_0201_6.3V6-K

1

1

CC211

@

2

2

DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQS#7
DQS7

DDRB_DQS6

DDRB_DQ60
DDRB_DQ56
DDRB_DQ63
DDRB_DQ59
DDRB_DQ61
DDRB_DQ57
DDRB_DQ58
DDRB_DQ62
DDRB_DQS#7
DDRB_DQS7

SPD Address = A2H

5

T

T

T

itle

itle

Secu

Secu

Secu

rity Classification

rity Classification

rity Classification

Issued Date

Issued Date

Issued Date

THI

THI

THI

S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2013/08/15

2013/08/15

2013/08/15

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2013/08/15

2013/08/15

2013/08/15

itle

DDRIII SO-DIMM A

DDRIII SO-DIMM A

DDRIII SO-DIMM A

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Cu

Cu

Cu

stom

stom

stom

Thu

Thu

Thu

Date: Sheet

Date: Sheet

Date: Sheet

320ABR

320ABR

320ABR

rsday, January 12, 2017

rsday, January 12, 2017

rsday, January 12, 2017

1

o

o

o

f

12 50

f

12 50

f

12 50

0.

0.

0.

1

1

1

5

P3
P7

R3

N7
N3
P8

P2
R8
R2
R7
M3

T2
M7

T8

L2
M8

L8

K8

K7

K2

F3
G3

A7

B7

E2

E7

N2

N8

L3

L7

P9

M2

K3

T3

N9

P1

F1

H1

A2
D2

E3

A8
D8

E8
C9

H9

F9

12

RD116
240_0402_1%

@

DRAM@

UD3

P3

A0

P7

A1

R3

A2

N7

A3

N3

A4

P8

A5

P2

A6

R8

A7

R2

A8

R7

A9

M3

A10/AP

T2

A11

M7

A12/BC_N

T8

A13

L2

WE_N/A14

M8

CAS_N/A15

L8

RAS_N/A16

K8

CK_C

K7

CK_T

K2

CKE

F3

LDQS_C

G3

LDQS_T

A7

UDQS_C

B7

UDQS_T

E2

NF/UDM_N/UDBI_N

E7

NF/LDM_N/LDBI_N

N2

BA0

N8

BA1

L3

ACT_N

L7

CS_N

P9

ALERT_N

M2

BG0

K3

ODT

T3

PAR

N9

TEN

P1

RESET_N

F1

VSSQ1

H1

VSSQ2

A2

VSSQ3

D2

VSSQ4

E3

VSSQ5

A8

VSSQ6

D8

VSSQ7

E8

VSSQ8

C9

VSSQ9

H9

VSSQ10

F9

ZQ

12

RD118

MT40A51 2M16HA08 3EA_FB GA96

240_0402_1%

@

DRAM@

UD1

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC_N
A13

WE_N/A14
CAS_N/A15
RAS_N/A16

CK_C
CK_T

CKE

LDQS_C
LDQS_T
UDQS_C

VDD10

UDQS_T

VDDQ1

NF/UDM_N/UDBI_N

VDDQ2

NF/LDM_N/LDBI_N

VDDQ3
VDDQ4

BA0

VDDQ5

BA1

VDDQ6
VDDQ7

ACT_N

VDDQ8

CS_N

VDDQ9

ALERT_N

VDDQ10

BG0

ODT

VREFCA

PAR

TEN

RESET_N

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

ZQ

MT40A51 2M16HA08 3EA_FB GA96

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9

VDD10

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VDDQ10

VPP1
VPP2

VREFCA

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9

DDRB_DQ3

G2

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9

VPP1
VPP2

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9

NC

DDRB_DQ2

F7

DDRB_DQ6

H3

DDRB_DQ0

H7

DDRB_DQ1

H2

DDRB_DQ5

H8

DDRB_DQ7

J3

DDRB_DQ4

J7

DDRB_DQ11

A3

DDRB_DQ8

B8

DDRB_DQ15

C3

DDRB_DQ9

C7

DDRB_DQ10

C2

DDRB_DQ13

C8

DDRB_DQ14

D3

DDRB_DQ12

D7

+1.2V

D1

J1

L1

R1

B3

G7

B9

J9

L9

T9

A1

C1

G1

F2

J2

F8

J8

A9

D9

G9

B1

R9

M1

E1

K1

N1

T1

B2

G8

E9

K9

M9

T7

NC

G2
F7
H3
H7
H2
H8
J3
J7
A3
B8
C3
C7
C2
C8
D3
D7

D1
J1
L1
R1
B3
G7
B9
J9
L9
T9

A1
C1
G1
F2
J2
F8
J8
A9
D9
G9

B1
R9

M1

E1
K1
N1
T1
B2
G8
E9
K9
M9

T7

DRAM@

+1.2V

DRAM@

DDRB_DQ38
DDRB_DQ32
DDRB_DQ34
DDRB_DQ37
DDRB_DQ35
DDRB_DQ36
DDRB_DQ39
DDRB_DQ33
DDRB_DQ43

DDRB_DQ40
DDRB_DQ41
DDRB_DQ46
DDRB_DQ45
DDRB_DQ42
DDRB_DQ47

CD234

+VREF_CA

1

1

DRAM@

CD188

CD189

2

2

DRAM@

0.1U_0201_6.3V6-K

1000P_0201_50V7-K

+VREF_CA

1

1

CD235

DRAM@

2

2

DRAM@

0.1U_0201_6.3V6-K

1000P_0201_50V7-K

DDRB_MA 0
DDRB_MA 1
DDRB_MA 2
DDRB_MA 3
DDRB_MA 4
DDRB_MA 5
DDRB_MA 6
DDRB_MA 7
DDRB_MA 8
DDRB_MA 9
DDRB_MA 10
DDRB_MA 11
DDRB_MA 12

D D

RF

C C

B B

A A

DDRB_MA 14_WE #5
DDRB_MA 15_CAS #5
DDRB_MA 16_RAS #5

DDRB_CLK0#5
DDRB_CLK05

DDRB_CKE05

DDRB_BA05
DDRB_BA15

+1.2V

DDRB_ACT#5
DDRB_CS0#5

1 2

DRAM@

DDRB_BG05

DDRB_ODT05

1 2

1 2

MEM_MB_RST #5

+1.2V

1 2

1 2

1 2

DDRB_MA 13

DDRB_MA 14_WE #
DDRB_MA 15_CAS #
DDRB_MA 16_RAS #

DDRB_CLK0#
DDRB_CLK0

DDRB_CKE0

DDRB_DQS#0
DDRB_DQS0
DDRB_DQS#1
DDRB_DQS1

DDRB_D M1
DDRB_D M0

DDRB_BA0
DDRB_BA1

DDRB_ACT#
DDRB_CS0#

RD2601K_0402_1%

DDRB_BG0

DDRB_ODT0

RD2610_0402_5% DRAM@

TEN1 TEN2

RD25110K_0402_5% DRAM@

MEM_MB_RST #

1

CD132

2

@

0.1U_0201_6.3V6-K

DDRB_MA 0
DDRB_MA 1
DDRB_MA 2
DDRB_MA 3
DDRB_MA 4
DDRB_MA 5
DDRB_MA 6
DDRB_MA 7
DDRB_MA 8
DDRB_MA 9
DDRB_MA 10
DDRB_MA 11
DDRB_MA 12
DDRB_MA 13

DDRB_MA 14_WE #
DDRB_MA 15_CAS #
DDRB_MA 16_RAS #

DDRB_CLK0#
DDRB_CLK0

DDRB_CKE0

DDRB_DQS#4
DDRB_DQS4
DDRB_DQS#5
DDRB_DQS5

DDRB_D M5
DDRB_D M4

DDRB_BA0
DDRB_BA1

DDRB_ACT#
DDRB_CS0#

RD2661K_0402_1% DRA M@

DDRB_BG0

DDRB_ODT0

RD2670_0402_5% DRAM@

TEN3

RD25510K_0402_5% DRAM@

MEM_MB_RST #

1

CD161

2

@

0.1U_0201_6.3V6-K

4

P3
P7
R3
N7
N3
P8
P2
R8
R2
R7
M3
T2
M7
T8

L2
M8
L8

K8
K7

K2

F3
G3
A7
B7

E2
E7

N2
N8

L3
L7
P9

M2

K3

T3

N9

P1

F1
H1
A2
D2
E3
A8
D8
E8
C9
H9

F9

12

RD117
240_0402_1%

DRAM@

UD4

P3

A0

P7

A1

R3

A2

N7

A3

N3

A4

P8

A5

P2

A6

R8

A7

R2

A8

R7

A9

M3

A10/AP

T2

A11

M7

A12/BC_N

T8

A13

L2

WE_N/A14

M8

CAS_N/A15

L8

RAS_N/A16

K8

CK_C

K7

CK_T

K2

CKE

F3

LDQS_C

G3

LDQS_T

A7

UDQS_C

B7

UDQS_T

E2

NF/UDM_N/UDBI_N

E7

NF/LDM_N/LDBI_N

N2

BA0

N8

BA1

L3

ACT_N

L7

CS_N

P9

ALERT_N

M2

BG0

K3

ODT

T3

PAR

N9

TEN

P1

RESET_N

F1

VSSQ1

H1

VSSQ2

A2

VSSQ3

D2

VSSQ4

E3

VSSQ5

A8

VSSQ6

D8

VSSQ7

E8

VSSQ8

C9

VSSQ9

H9

VSSQ10

F9

ZQ

12

RD119

MT40A51 2M16HA08 3EA_FB GA96

240_0402_1%

@

DRAM@

UD2

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC_N
A13

WE_N/A14
CAS_N/A15
RAS_N/A16

CK_C
CK_T

CKE

LDQS_C
LDQS_T
UDQS_C
UDQS_T

NF/UDM_N/UDBI_N
NF/LDM_N/LDBI_N

BA0
BA1

ACT_N
CS_N
ALERT_N

BG0

ODT

PAR

TEN

RESET_N

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

ZQ

MT40A51 2M16HA08 3EA_FB GA96

@

DDRB_MA 0
DDRB_MA 1
DDRB_MA 2
DDRB_MA 3
DDRB_MA 4
DDRB_MA 5
DDRB_MA 6
DDRB_MA 7
DDRB_MA 8
DDRB_MA 9
DDRB_MA 10
DDRB_MA 11
DDRB_MA 12
DDRB_MA 13

DDRB_MA 14_WE #
DDRB_MA 15_CAS #
DDRB_MA 16_RAS #

DDRB_CLK0#
DDRB_CLK0

DDRB_CKE0

DDRB_DQS#2
DDRB_DQS2
DDRB_DQS#3
DDRB_DQS3

DDRB_D M3
DDRB_D M2

DDRB_BA0
DDRB_BA1

RD2621K_0402_1% DRA M@

RD2630_0402_5% DRAM@

RD25710K_0402_5% DRAM@

@

0.1U_0201_6.3V6-K

RD2641K_0402_1% DRA M@

RD2650_0402_5% DRAM@

RD25310K_0402_5% DRA M@

@

0.1U_0201_6.3V6-K

DDRB_DQS#6
DDRB_DQS6
DDRB_DQS#7
DDRB_DQS7

DDRB_D M7
DDRB_D M6

1

CD162

2

1

CD160

2

DDRB_ACT#
DDRB_CS0#

DDRB_BG0

DDRB_ODT0

MEM_MB_RST #

DDRB_MA 0
DDRB_MA 1
DDRB_MA 2
DDRB_MA 3
DDRB_MA 4
DDRB_MA 5
DDRB_MA 6
DDRB_MA 7
DDRB_MA 8
DDRB_MA 9
DDRB_MA 10
DDRB_MA 11
DDRB_MA 12
DDRB_MA 13

DDRB_MA 14_WE #
DDRB_MA 15_CAS #
DDRB_MA 16_RAS #

DDRB_CLK0#
DDRB_CLK0

DDRB_CKE0

DDRB_BA0
DDRB_BA1

DDRB_ACT#
DDRB_CS0#

DDRB_BG0

DDRB_ODT0

TEN4

MEM_MB_RST #

+1.2V

+2.5V

1

1

CD202

CD203

2

2

DRAM@

1U_0402_6.3V6K

0.1U_0201_6.3V6-K

+1.2V

+2.5V

1

1

CD237

CD236

2

2

DRAM@

1U_0402_6.3V6K

0.1U_0201_6.3V6-K

1 2

1 2

1 2

1 2

1 2

1 2

VDDQ10

VREFCA

VDD10

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9

VPP1
VPP2

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9

VDDQ10

VREFCA

NC

VDD10

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

3

DDRB_DQ18

G2

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9

VPP1
VPP2

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9

DDRB_DQ19

F7

DDRB_DQ23

H3

DDRB_DQ17

H7

DDRB_DQ22

H2

DDRB_DQ21

H8

DDRB_DQ20

J3

DDRB_DQ16

J7

DDRB_DQ27

A3

DDRB_DQ24

B8

DDRB_DQ31

C3

DDRB_DQ25

C7

DDRB_DQ26

C2

DDRB_DQ28

C8

DDRB_DQ30

D3

DDRB_DQ29

D7

+1.2V

D1

J1

L1

R1

B3

G7

B9

J9

L9

T9

A1

C1

G1

F2

J2

F8

J8

A9

D9

G9

B1

R9

M1

E1

K1

N1

T1

B2

G8

E9

K9

M9

T7

NC

G2
F7
H3
H7
H2
H8
J3
J7
A3
B8
C3
C7
C2
C8
D3
D7

+1.2V

D1
J1
L1
R1
B3
G7
B9
J9
L9
T9

A1
C1
G1
F2
J2
F8
J8
A9
D9
G9

B1
R9

M1

E1
K1
N1
T1
B2
G8
E9

DRAM@

K9
M9

T7

DRAM@

DDRB_DQ51
DDRB_DQ48
DDRB_DQ50
DDRB_DQ53
DDRB_DQ55
DDRB_DQ52
DDRB_DQ54
DDRB_DQ49
DDRB_DQ59DDRB_DQ44
DDRB_DQ56
DDRB_DQ58
DDRB_DQ61
DDRB_DQ63
DDRB_DQ60
DDRB_DQ62
DDRB_DQ57

CD238

1

2

CD230

DRAM@

+VREF_CA

1

1

CD231

2

2

DRAM@

0.1U_0201_6.3V6-K

1000P_0201_50V7-K

+1.2V

CD266

CD267

47P_0201_25V8-J

1

1

EMC_NS@

EMC@

2

2

+VREF_CA

1

DRAM@

CD239

2

0.1U_0201_6.3V6-K

1000P_0201_50V7-K

+2.5V

1

1

CD232

CD233

2

2

DRAM@

DRAM@

1U_0402_6.3V6K

0.1U_0201_6.3V6-K

CD268

CD269

CD270

27P 25V J NPO 0201

27P 25V J NPO 0201

27P 25V J NPO 0201

1

1

EMC@

CD240

1

EMC@

EMC@

2

2

2

+2.5V

1

1

CD241

DRAM@

2

2

1U_0402_6.3V6K

0.1U_0201_6.3V6-K

2/22: change to K back for materil stock risk, and this change
has conf i r m to A MD

CD273

CD274

CD272

CD271

27P 25V J NPO 0201

EMC@

47P_0201_25V8-J

27P 25V J NPO 0201

27P 25V J NPO 0201

1

1

1

EMC_NS@

EMC@

EMC@

2

2

2

2

DDRB_D Q[0..63]

DDRB_D QS[0..7]

DDRB_D QS#[0..7]

DDRB_MA [0..13]

DDRB_D M[0..7]

DDRB_D Q[0..63] 5

DDRB_D QS[0..7] 5

DDRB_D QS#[0..7] 5

DDRB_MA [0..13] 5

DDRB_D M[0..7] 5

CD163 change from K to J

DDRB_CLK0#
DDRB_CLK0

DDRB_MA 0
DDRB_MA 1
DDRB_MA 2
DDRB_MA 3
DDRB_MA 4
DDRB_MA 5
DDRB_MA 6
DDRB_MA 7
DDRB_MA 8
DDRB_MA 9
DDRB_MA 10
DDRB_MA 11
DDRB_MA 12
DDRB_MA 13

DDRB_MA 14_WE #
DDRB_MA 15_CAS #
DDRB_MA 16_RAS #

DDRB_ACT#

DDRB_ODT0
DDRB_CS0#
DDRB_CKE0

DDRB_BA0
DDRB_BA1

DDRB_BG0

CD277

CD276

CD275

47P_0201_25V8-J

27P 25V J NPO 0201

47P_0201_25V8-J

1

1

1

EMC_NS@

EMC_NS@

2

2

2

Layout Note: Place near DRAM

27P 25V J NPO 0201

3A@1.5V

1

EMC@

+1.2V

2

follow SCL 20 pcs 0.22uf

0.22U_0201_6.3V6-K

1

CD155

CD154

2

DRAM@

3A@1.5 V

+1.2V

0.22U_0201_6.3V6-K

1

CD174

CD173

2

DRAM@

+1.2V

0.22U_0201_6.3V6-K

1

CD218

CD215

@

@

2

+0.6VS

follow SCL 10 pcs 0.22uf

0.22U_0201_6.3V6-K

1

CD148

CD146

2

DRAM@

+0.6VS

0.22U_0201_6.3V6-K

1

CD259

CD252

@

@

2

DRAM@

DRAM@

DRAM@

0.22U_0201_6.3V6-K

1

CD142

2

0.22U_0201_6.3V6-K

1

CD169

2

0.22U_0201_6.3V6-K

1

CD212

@

2

0.22U_0201_6.3V6-K

1

CD139

2

0.22U_0201_6.3V6-K

1

2

DRAM@

DRAM@

DRAM@

1 2

RD122 39_0402_5%DRAM@

1 2

RD123 39_0402_5%DRAM@

1 2

RD148 39_0402_5%DRAM@

1 2

RD149 39_0402_5%DRAM@

1 2

RD124 39_0402_5%DRAM@

1 2

RD125 39_0402_5%DRAM@
RD126 39_0402_5%DRAM@

1 2
1 2

RD127 39_0402_5%DRAM@

1 2

RD128 39_0402_5%DRAM@

1 2

RD129 39_0402_5%DRAM@

1 2

RD130 39_0402_5%DRAM@
RD131 39_0402_5%DRAM@

1 2
1 2

RD132 39_0402_5%DRAM@

1 2

RD133 39_0402_5%DRAM@

1 2

RD134 39_0402_5%DRAM@

1 2

RD135 39_0402_5%DRAM@

1 2

RD138 39_0402_5%DRAM@

1 2

RD139 39_0402_5%DRAM@

1 2

RD140 39_0402_5%DRAM@

RD144 39_0402_5%DRAM@

1 2

1 2

RD147 39_0402_5%DRAM@

1 2

RD145 39_0402_5%DRAM@

1 2

RD141 39_0402_5%DRAM@

1 2

RD142 39_0402_5%DRAM@
RD143 39_0402_5%DRAM@

1 2

1 2

RD146 39_0402_5%DRAM@

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

1

1

1

CD127

CD141

2

2

2

DRAM@

DRAM@

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

1

1

1

CD167

CD165

2

2

2

DRAM@

DRAM@

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

1

1

CD211

@

2

2

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

1

1

1

CD201

CD138

2

2

2

DRAM@

DRAM@

+0.6VS

1

CD263
22P_04 02_50V 8-J

RF_NS@

2

0.22U_0201_6.3V6-K

CD152

0.22U_0201_6.3V6-K

CD172

+1.2V

0.22U_0201_6.3V6-K

CD245

1

CD264
22P_04 02_50V 8-J

RF_NS@

2

1

2

DRAM@

1

2

DRAM@

1

CD133
22P_04 02_50V 8-J

RF_NS@

2

1

2

DRAM@

+0.6VS

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

1

CD150

2

DRAM@

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

1

CD171

2

DRAM@

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

1

CD246

2

DRAM@

1

DRAM@

1 2

CD163 0.01 UF_040 2_25V7 -K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

1

1

CD158

CD143

CD137

2

2

DRAM@

DRAM@

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

1

1

CD166

CD168

CD175

2

2

DRAM@

DRAM@

1

CD153
22P_04 02_50V 8-J

RF_NS@

2

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

1

1

CD244

CD242

CD243

2

2

DRAM@

DRAM@

+2.5V

1

1

CD265
22P_04 02_50V 8-J

RF_NS@

CC205

2

2

180P_0402_50V8-J

DRAM@

DRAM@

DRAM@

DRAM@

+1.2V

0.22U_0201_6.3V6-K

1

2

0.22U_0201_6.3V6-K

1

2

0.22U_0201_6.3V6-K

1

2

Swap Table

Pin Name Net Name

DQ0

DDRB_DQ3

DQ1

DDRB_DQ4

DQ2

DDRB_DQ1

DQ3

DDRB_DQ0

DQ4

DDRB_DQ7

DQ5

DDRB_DQ5

DQ6

DDRB_DQ2

DQ7

DDRB_DQ6

DQS#0

DDRB_DQS#0

DQS0

DDRB_DQS0

UD1

DDRB_DQ9

DQ8

DDRB_DQ11

DQ9

DDRB_DQ12

DQ10

DDRB_DQ8

DQ11

DDRB_DQ15

DQ12

DDRB_DQ13

DQ13

DDRB_DQ14

DQ14

DDRB_DQ10

DQ15

DDRB_DQS#1

DQS#1

DDRB_DQS1

DQS1

UD1

DQ16

DDRB_DQ7

DQ17

DDRB_DQ3

DQ18

DDRB_DQ0

DQ19

DDRB_DQ1

DQ20

DDRB_DQ6

DQ21

DDRB_DQ5

DQ22

DDRB_DQ4

DQ23

DDRB_DQ2

DQS#2

DDRB_DQS#2

DQS2

DDRB_DQS2

UD2

DQ24

DDRB_DQ9

DQ25

DDRB_DQ11

DQ26

DDRB_DQ12

DQ27

DDRB_DQ8

DQ28

DDRB_DQ13

DQ29

DDRB_DQ15

DQ30

DDRB_DQ14

DQ31

DDRB_DQ10

DQS#3

DDRB_DQS#3

DQS3

DDRB_DQS3

UD2

DQ32

DDRB_DQ1

DQ33

DDRB_DQ7

DQ34

DDRB_DQ2

DQ35

DDRB_DQ4

DQ36

DDRB_DQ5

DQ37

DDRB_DQ3

DQ38

DDRB_DQ0

DQ39

DDRB_DQ6

DQS#4

DDRB_DQS#4

DQS4

DDRB_DQS4

UD3

DQ40

DDRB_DQ10

DQ41

DDRB_DQ11

DQ42

DDRB_DQ14

DQ43

DDRB_DQ8

DQ44

DDRB_DQ9

DQ45

DDRB_DQ13

DQ46

DDRB_DQ12

DQ47

DDRB_DQ15

DQS#5

DDRB_DQS#5

DQS5

DDRB_DQS5

UD3

DQ48

DDRB_DQ1

DQ49

DDRB_DQ7

DQ50

DDRB_DQ2

DQ51

DDRB_DQ0

DQ52

DDRB_DQ5

DQ53

DDRB_DQ3

DQ54

DDRB_DQ6

DQ55

DDRB_DQ4

DQS#6

DDRB_DQS#6

DQS6

DDRB_DQS6

UD4

DQ56

DDRB_DQ9

DQ57

DDRB_DQ15

DQ58

DDRB_DQ10

DQ59

DDRB_DQ8

DQ60

DDRB_DQ13

DQ61

DDRB_DQ11

DQ62

DDRB_DQ14

DQ63

DDRB_DQ12

DQS#7

DDRB_DQS#7

DQS7

DDRB_DQS7

UD4

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2

2013/08/15

2013/08/15

2013/08/15

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2013/08/15

2013/08/15

2013/08/15

Title

DDRIII SO-DIMM B

DDRIII SO-DIMM B

DDRIII SO-DIMM B

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date : Sheet of

Date : Sheet of

Date : Sheet of

Thursday, January 12, 2017

Thursday, January 12, 2017

Thursday, January 12, 2017

1

320ABR

320ABR

320ABR

13 50

13 50

13 50

0.1

0.1

0.1

5

4

3

2

1

Power-Up/Down Sequence

"Topaz" has the following requirements with regards to power-supply sequencing to

D D

C C

avoid damaging the ASIC:

All the ASIC supplies must reach their respective nominal voltages within 20 ms
of the start of the ramp-up sequence, though a shorter ramp-up duration is
preferred. The maximum slew rate on all rails is 50 mV/μ s.
It is recommended that the 3.3-V rail ramp up first.
The 3.3-V, 1.8-V, and 0.95-V rails must reach their ready state at least 10 μ s
before VDDC, VDDCI, and VMEMIO start to ramp up.
The power rails that are shared with other components on the system should be
gated for the dGPU so that when the dGPU is powered down (for example
AMD PowerXpress idle state), all the power rails are removed from the dGPU.
The gate circuits must meet the slew rate requirement (such as ≤ 50 mV/μ s).
For power down, reversing the ramp-up sequence is recommended.

0 ~ 20ms

VDDR3(+3VGS)

0 ~ 20ms

VDD_CT(+1.8VGS)

PCIE_VDDC(+0.95VGS)

VRAM ID config

Memory Type

Hynix

H5GC4H24AJR-R0C 6.0Gbps@1.35V

4Gb GDDR5

256M x 16

8Gb GDDR5

512M x 16

Micron

EDW4032BABG-70-F 6.0Gbps@1.35V

Samsung

K4G41325FE-HC28 6.0Gbps@1.35V

Hynix

H5GC8H24MJR-R0C 6.0Gbps@1.35V

Micron

MT51J256M32HF-70:A 6.0Gbps@1.35V

Samsung

K4G80325FB-HC28 6.0Gbps@1.35V

VRAM ID PU resistor PD resistor

PS_3[3: 1]

100

111

110

000

010

001

RV63 RV70

4.53K 4.99K

NC4.75K

10K3.4K

NC 4.75K

4.53K 2K

8.45K 2K

10us min.

VDDR1(+1.35VGS)

VDDC/VDDCI(+VGA_CORE)

PERSTb(GPU_RST#)

100ms min.

100us min.

REFCLK(CLK_PCIE_VGA)

B B

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INF ORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND TRADE SECRET INF ORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND TRADE SECRET INF ORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2016/08/16

2016/08/16

2016/08/16

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2017/08/15

2017/08/15

2017/08/15

Title

VGA Notes List

VGA Notes List

VGA Notes List

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

320ABR

320ABR

320ABR

Thursday, January 12, 2017

Thursday, January 12, 2017

Thursday, January 12, 2017

14 50

14 50

1

14 50

0.1

0.1

0.1

5

PCIE_CTX_C_GRX_P[0..7]4

PCIE_CTX_C_GRX_N[0..7]4

PCIE_CTX_C_GRX_P[0..7]

PCIE_CTX_C_GRX_N[0..7]

4

UV1A

3

PCIE_CRX_GTX_P[0..7]

PCIE_CRX_GTX_N[0..7]

2

PCIE_CRX_GTX_P[0..7] 4

PCIE_CRX_GTX_N[0..7] 4

1

AF30

PCIE_CTX_C_GRX_N0

D D

C C

B B

PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_N1

PCIE_CTX_C_GRX_P2
PCIE_CTX_C_GRX_N2

PCIE_CTX_C_GRX_P3
PCIE_CTX_C_GRX_N3

PCIE_CTX_C_GRX_P4
PCIE_CTX_C_GRX_N4

PCIE_CTX_C_GRX_P5
PCIE_CTX_C_GRX_N5

PCIE_CTX_C_GRX_P6
PCIE_CTX_C_GRX_N6

PCIE_CTX_C_GRX_P7
PCIE_CTX_C_GRX_N7

AE31

AE29
AD28

AD30
AC31

AC29
AB28

AB30
AA31

AA29

Y28

Y30

W31

W29

V28

V30
U31

U29

R31

R29
P28

P30
N31

N29
M28

M30

K30

T28

T30

L31

L29

PCIE_RX0P
PCIE_RX0N

PCIE_RX1P
PCIE_RX1N

PCIE_RX2P
PCIE_RX2N

PCIE_RX3P
PCIE_RX3N

PCIE_RX4P
PCIE_RX4N

PCIE_RX5P
PCIE_RX5N

PCIE_RX6P
PCIE_RX6N

PCIE_RX7P
PCIE_RX7N

NC#V30
NC#U31

NC#U29
NC#T28

NC#T30
NC#R31

NC#R29
NC#P28

NC#P30
NC#N31

NC#N29
NC#M28

NC#M30
NC#L31

NC#L29
NC#K30

PCI EXPRESS INTERFACE

PCIE_TX0P

PCIE_TX0N

PCIE_TX1P

PCIE_TX1N

PCIE_TX2P

PCIE_TX2N

PCIE_TX3P

PCIE_TX3N

PCIE_TX4P

PCIE_TX4N

PCIE_TX5P

PCIE_TX5N

PCIE_TX6P

PCIE_TX6N

PCIE_TX7P

PCIE_TX7N

NC#W24
NC#W23

NC#V27
NC#U26

NC#U24
NC#U23

NC#T26
NC#T27

NC#T24
NC#T23

NC#P27
NC#P26

NC#P24
NC#P23

NC#M27

NC#N26

PCIE_CRX_C_GTX_P0PCIE_CTX_C_GRX_P0

AH30

PCIE_CRX_C_GTX_N0

AG31

PCIE_CRX_C_GTX_P1

AG29

PCIE_CRX_C_GTX_N1

AF28

PCIE_CRX_C_GTX_P2

AF27

PCIE_CRX_C_GTX_N2

AF26

PCIE_CRX_C_GTX_P3

AD27

PCIE_CRX_C_GTX_N3

AD26

PCIE_CRX_C_GTX_P4 PCIE_CRX_GTX_P4

AC25

PCIE_CRX_C_GTX_N4

AB25

PCIE_CRX_C_GTX_P5 PCIE_CRX_GTX_P5

Y23

PCIE_CRX_C_GTX_N5

Y24

PCIE_CRX_C_GTX_P6

AB27

PCIE_CRX_C_GTX_N6 PCIE_CRX_GTX_N6

AB26

PCIE_CRX_C_GTX_P7

Y27

PCIE_CRX_C_GTX_N7 PCIE_CRX_GTX_N7

Y26

W24
W23

V27
U26

U24
U23

T26
T27

T24
T23

P27
P26

P24
P23

M27
N26

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

with BOM strcture control, CV1--CV8 change to 0.22uf for CZ

PCIE_CRX_GTX_P0

CV10.22U_0201_6.3V6-K PX@

PCIE_CRX_GTX_N0

CV20.22U_0201_6.3V6-K PX@

PCIE_CRX_GTX_P1

CV30.22U_0201_6.3V6-K PX@

PCIE_CRX_GTX_N1

CV40.22U_0201_6.3V6-K PX@

PCIE_CRX_GTX_P2

CV50.22U_0201_6.3V6-K PX@

PCIE_CRX_GTX_N2

CV60.22U_0201_6.3V6-K PX@

PCIE_CRX_GTX_P3

CV70.22U_0201_6.3V6-K PX@

PCIE_CRX_GTX_N3

CV80.22U_0201_6.3V6-K PX@

CV6360.22U_0201_6.3V6-K PX@

PCIE_CRX_GTX_N4

CV6390.22U_0201_6.3V6-K PX@

CV6330.22U_0201_6.3V6-K PX@

PCIE_CRX_GTX_N5

CV6380.22U_0201_6.3V6-K PX@

PCIE_CRX_GTX_P6

CV6320.22U_0201_6.3V6-K PX@
CV6340.22U_0201_6.3V6-K PX@

PCIE_CRX_GTX_P7

CV6350.22U_0201_6.3V6-K PX@
CV6370.22U_0201_6.3V6-K PX@

CLK_PCIE_GPU8
CLK_PCIE_GPU#8

GPU_RST#16

1 2

RV7 0_0402_5%@

+3VGS

A A

PXS_RST#8

PLT_RST#7,28,31

0.1U_0201_6 .3V6-K

CV640

1

@

2

5

5

1

IN1

VCC

OUT

2

IN2

GND

MC74VHC1G08DFT2 G_SC70-5

3

PX@

UV2

GPU_RST#

4

CLK_PCIE_GPU
CLK_PCIE_GPU#

1 2

GPU_RST#

4

RV41K_0402_1% PX@

12

RV6
100K_0402_ 5%

PX@

AK30
AK32

N10

AL27

CLOCK

PCIE_REFCLKP
PCIE_REFCLKN

CALIBRATION

PCIE_CALR_TX

TEST_PG

PERSTB

@

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

IS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

IS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

IS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

TH

TH

TH
AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R& D

AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R& D

AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R& D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FU TURE CENTER NE ITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FU TURE CENTER NE ITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FU TURE CENTER NE ITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTE N CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTE N CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTE N CONSENT OF LC FUTURE CENTER.

PCIE_CALR_RX

Y22

AA22

2

2

2

016/08/16

016/08/16

016/08/16

3

change the GPU PN to AMD(EXO-S3 PRO), symbol check ok

1 2

RV3 1.69K_0402_ 1%PX@

1 2

RV5 1K_0402_1%PX@

VR_VGA_PWRGD7,48

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

+1.05VGS

11/4 change to PC sample SA000074V10

GPU_RST#

VR_VGA_PWRGD

2017/08/15

2017/08/15

2017/08/15

2

DV3

2

3

LBAT54AWT1G SOT323

PX@

Title

Title

Title

Size

Size

Size

Custom

Custom

Custom

Date: She et

Date: She et

Date: She et

VGA_PWROK

1

ATI_EXO-PRO_PCIE

ATI_EXO-PRO_PCIE

ATI_EXO-PRO_PCIE

Doc

Doc

Doc

ument Number Rev

ument Number Rev

ument Number Rev

Thursday, January 12, 2017

Thursday, January 12, 2017

Thursday, January 12, 2017

320ABR

320ABR

320ABR

VGA_PWROK 48

1

o

o

o

f

15 50

f

15 50

f

15 50

0.1

0.1

0.1