Lenovo Ideapad 300 series Schematic

A

1 1

B

C

D

E

BMWQ1/Q2 UMA M/B Schematics Document

Intel Skylake U22 with DDRIIIL

2 2

2015-07-12

www.rosefix.com

REV:1.0

3 3

4 4

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND C ONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF LC FUTUR E CENTER .

MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF LC FUTUR E CENTER .

A

B

MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF LC FUTUR E CENTER .

C

2014/12/11

LC Future Center Secret Data

Deciphered Date

D

2015/12/11

Title

Cover Page

Size

Document Number Re v

Custom

Date: Sheet

Friday, July 31, 2015

BMWQ1&2_UMA

E

160

0.3

of

A

B

C

D

E

Memory BUS (DDR3L) Dual Channel

1 1

Page25~26

HDMI (DDI0)

DPx2 Lane (DDI1)

Intel MCP

eDP x2 Lane

SKL-U22 15W

USB2.0 1x

VGA Conn.

eDP Conn

Int. Camera

USB2.0 Port6

HDMI Conn.

Page34

DP to VGA

Page35Page36

IT6515FN

1.35V DDR3L 1600 MT/s

USB 3.0 1x USB 2.0 1x

USB2.0 2x

USB3.0 Left CONN1

USB 3.0 Port1 USB 2.0 Port1

USB2.0 Right CONN

USB2.0 Port2, Port3

DDR3L-SO-DIMM X2

Page 14,15

UP TO 8G x 2

Page41

USB Board

BGA-1356

2 2

Int. MIC Conn.

Page33

SATA HDD

Page42

SATA ODD

Page42

SATA Port0

SATA Port1A

SATA Gen3

SATA Gen1

42mm*24mm

USB 2.0 1x

USB2.0 1x

USB 2.0 1x

RJ45 Conn.

Page38

3 3

Codec

Conexant_CX11802_33Z

Page43

LAN Realtek

Page37

RTL8111H_CG

PCIe Port5

SPK Conn.

Page43

PCIe 1x

HD Audio

Page3~13

EC ITE IT8586E-LQFP

Page44

PCIe 1x

SPI BUS

LCP BUS

TPM (reserved)

ST33ZP24AR28PVSP

HP&Mic Combo Conn.

Touch Pad Int.KBD

Page45 Page45

4 4

Thermal Sensor NCT7718W

Page39

Touch Screen (optionanl)

USB2.0 Port5

Page33

Cardreader Realtek RTS5170

USB2.0 Port4

Page30

NGFF slot WLAN&BT

USB2.0 Port7

PCIe Port6

Page40

SPI ROM 8MB

SPI ROM 4MB

for reserve

Page07

SD/MMC Conn.

Sub-board ( for 14")

POWER BOARD

USBBoard

Sub-board ( for 15")

POWER BOARD

USBBoard

ODD Board

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND C ONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF LC FUTUR E CENTER .

MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF LC FUTUR E CENTER .

A

B

MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF LC FUTUR E CENTER .

C

2014/12/11

LC Future Center Secret Data

Deciphered Date

D

2015/12/11

Title

Block Diagram

Size

Document Number Re v

Custom

Monday, July 27, 2015

Date: Sheet

Monday, July 27, 2015

BMWQ1&2_UMA

E

260

0.2

of

A

B

C

D

E

Voltage Rails

Power Plane

1 1

State

S0

S3

2 2

S3 Battery only

S5 S4/AC Only

S5 S4 Battery only

S5 S4 AC & Battery don't exist

SMBUS Control Table

3 3

EC_SMB_DA1

EC_SMB_CK2 EC_SMB_DA2

PCH_SMB_CLK PCH_SMB_DATA

IT8586E

+3VALW_PCH

( O --> Means ON , X --> Means OFF )

+3VALW +5VALW +3VALW_PCH

B+

+1.8VALW +1.0VALW

O

X

XX

SOURCE

IT8586EEC_SMB_CK1

+3VALW

+3VS

PCH

BATT SODIMM

IT8586E

V

+3VALW

X

V

+3VS

XX X

X

VV

+3VS +3VS

WLAN WiMAX

X

V

+1.35V +VCCST

O

X

Thermal Sensor

XXV

V

+3VS

+5VS +3VS +VCCIO +VCCSTG +VCCSA +VCC_GT +CPU_CORE +0.675VS

O

X

PCH

V

+3VALW_PCH

TP Module

XX

X

charger

V

X

DGPU

X

V

+3VGS

X

STATE

Full ON

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SIGNAL

HSIO PORT

1 2

USB3.0

USB2.0

PCIE

SATA

3 4 5 6 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8

X4 PCIE (9-12)

0 1A 1B 2

SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

HIGH HIGH HIGH

LOW

Function

USB3.0 CONN left NC NC NC NC NC USB3.0 CONN Left USB2.0 CONN1 Right USB2.0 CONN2 Right Camera Cardreader Touch Panel BT NC NC NC NC NC NC NC LAN WLAN used as SATA used as SATA

DGPU

HDD ODD used as PCIE used as PCIE

HIGH

LOWLOW

HIGH

LOW

ON

@ 14@ 15@ 14or15@ 14or17@ AOAC@ BCD@ Cannonlake@ CD@ DUALMIC@ EMC@ EMC_15@ EMC_NS@ EMC_PX@ EMC_PXNS@ ES@ EXO@ GCLK@ ME@ NTS@ PCH_SDIO@ PCH_SDIO1@ PCH_SDIO2@ PX@ RANKA@ RANKB@ Realtek_SD@ SINGLEMIC@ SINGLERANK@ DUALRANK@ TS@ TPM@ UMA@

ON ON ON

ON

OFF

OFFLOW LOW LOW

OFF

BTO ItemBOM Structure

Not stuff For 14" part For 15" part For 14" or 15" part For 14" or 17" part AOAC support part For C cost down (BDW) For Cannonlake part For C cost down For Dual MIC part For EMC part For EMC 15" part For EMC nu-stuff part For EMC PX part For EMC PX nu-stuff part For ES CPU For EXO GPU For GreenCLK part For ME part For nu-touch part For PCH SDIO part For PCH SDIO path1 For PCH SDIO path2 For PX part For VRAM rank A part For VRAM rank B part For Realtek SD part For single MIC part For single VRAN rank part For dual VRAN rank part For touch screen part For TPM part For UMA part

EC SM Bus1 address

4 4

Device

Smart Battery Charger

0X16 0001 0010 b

A

EC SM Bus2 address

Device

Thermal Sensor NCT7718W

PCH

DGPU

Address

1001_100xb

need to update need to update

B

PCH SM Bus address

Device Address

DDR DIMMA DDR DIMMB Wlan

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND C ONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF LC FUTUR E CENTER .

MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF LC FUTUR E CENTER .

1010 000Xb 1010 010Xb

Rsvd

C

2014/12/11

LC Future Center Secret Data

Deciphered Date

D

2015/12/11

Title

Notes List

Size

Document Number Re v

Custom

Monday, July 27, 2015

Date: Sheet

Monday, July 27, 2015

BMWQ1&2_UMA

E

360

0.2

of

5

D D

HDMI D2 HDMI D1 HDMI D0

HDMI CLK

DP TO VGA Converter

+VCCIO

C C

check PROCHOT# circuit with PWR

H_PROCHOT#{44}

check H_THRMTRIP# if need to connector to EC

B B

+VCCSTG

+VCCST_CPU

+3VS

HDMI_TX2-{34} HDMI_TX2+{34} HDMI_TX1-{34} HDMI_TX1+{34} HDMI_TX0-{34} HDMI_TX0+{34} HDMI_CLK-{34} HDMI_CLK+{34}

VGA_TX0-{35} VGA_TX0+{35} VGA_TX1-{35} VGA_TX1+{35}

DDPB_CLK{34}

DDPB_DATA{34}

RC4 24.9_0402_1%

12

RC19 1K_0402_5%

RC20 499 +-1% 0402

12

RC143 1K_0402_5%

12

1 2

RC155 49.9_0402_1% RC156 49.9_0402_1% RC157 49.9_0402_1% RC170 49.9_0402_1%

check DDPC_CLK pull high or not?

RPC19

18 27 36

2.2K_0804_8P4R_5%

45

+VCCIO&EDP_COMP : Trace Width: 20mil Isolation Spacing: 25mil Max length: 100mil

1 2 1 2 1 2 1 2

@ @

DDPC_CLK

DDPC_DATA

DDPB_CLK

DDPB_DATA

4

?

AT16

AU16

DDI

D63 A54 C65 C63 A65

C55 D55 B54 C56

A6

A7 BA5 AY5

H66 H65

DISPLAY SIDEBANDS

@

CATERR# PECI PROCHOT# THERMTRIP# SKTOCC#

BPM#[0] BPM#[1] BPM#[2] BPM#[3]

GPP_E3/CPU_GP0 GPP_E7/CPU_GP1 GPP_B3/CPU_GP2 GPP_B4/CPU_GP3

PROC_POPIRCOMP PCH_OPIRCOMP OPCE_RCOMP OPC_RCOMP

SKL_ULT

1 OF 20

SKL_ULT

UC1D

CPU MISC

SKYLAKE-U_BGA1356

REV = 1

EDP

HDMI_TX2HDMI_TX2+ HDMI_TX1HDMI_TX1+ HDMI_TX0HDMI_TX0+ HDMI_CLKHDMI_CLK+

VGA_TX0VGA_TX0+ VGA_TX1VGA_TX1+

DDPB_CLK DDPB_DATA

DDPC_CLK DDPC_DATA

EDP_COMP PCH_ENVDD

+VCCST_CPU

12

@

H_PECI{44}

TC11PAD @ TC12PAD @ TC13PAD @ TC14PAD @

TC162@PAD TC163@PAD TC164@PAD TC165@PAD

UC1A

E55

DDI1_TXN[0]

F55

DDI1_TXP[0]

E58

DDI1_TXN[1]

F58

DDI1_TXP[1]

F53

DDI1_TXN[2]

G53

DDI1_TXP[2]

F56

DDI1_TXN[3]

G56

DDI1_TXP[3]

C50

DDI2_TXN[0]

D50

DDI2_TXP[0]

C52

DDI2_TXN[1]

D52

DDI2_TXP[1]

A50

DDI2_TXN[2]

B50

DDI2_TXP[2]

D51

DDI2_TXN[3]

C51

DDI2_TXP[3]

L13

GPP_E18/DDPB_CTRLCLK

L12

GPP_E19/DDPB_CTRLDATA

N7

GPP_E20/DDPC_CTRLCLK

N8

GPP_E21/DDPC_CTRLDATA

N11

GPP_E22/DDPD_CTRLCLK

N12

GPP_E23/DDPD_CTRLDATA

E52

EDP_RCOMP

SKYLAKE-U_BGA1356

REV = 1 @

RC1625

49.9_0402_1%

CATERR# H_PECI XDP_TDO H_PROCHOT#_R H_THRMTRIP#

XDP_BPM0#

1

XDP_BPM1#

1

XDP_BPM2#

1

XDP_BPM3#

1

GPP_E3

1

GPP_E7

1

GPP_B3

1

GPP_B4

1

PROC_OPI_RCOMP PCH_OPI_RCOMP EDRAM_OPIO_RCOMP EOPIO_RCOMP

GPP_E13/DDPB_HPD0 GPP_E14/DDPC_HPD1 GPP_E15/DDPD_HPD2 GPP_E16/DDPE_HPD3

GPP_E17/EDP_HPD

?

1 OF 20

3

EDP_TXN[0] EDP_TXP[0] EDP_TXN[1] EDP_TXP[1] EDP_TXN[2] EDP_TXP[2] EDP_TXN[3] EDP_TXP[3]

EDP_AUXN EDP_AUXP

EDP_DISP_UTIL

DDI1_AUXN DDI1_AUXP DDI2_AUXN DDI2_AUXP DDI3_AUXN DDI3_AUXP

EDP_BKLTEN

EDP_BKLTCTL

EDP_VDDEN

JTAG

PROC_TCK

PROC_TDI PROC_TDO PROC_TMS

PROC_TRST#

PCH_JTAG_TCK

PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS

PCH_TRST#

?

JTAGX

?

C47 C46 D46 C45 A45 B45 A47 B47

E45 F45

B52 G50

F50 E48 F48 G46 F46

L9 L7 L6 N9 L10

R12 R11 U13

B61 D60 A61 C60 B59

B56 D59 A56 C59 C61 A59

XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST#

PCH_JTAG_TCK PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS PCH_JTAG_TRST# JTAGX

CPU_EDP_TX0CPU_EDP_TX0+ CPU_EDP_TX1CPU_EDP_TX1+

CPU_EDP_AUX# CPU_EDP_AUX

VGA_AUX# VGA_AUX

HDMI_HPD DP_VGA_HPD GPP_E15

CPU_EDP_HPD PCH_ENBKL

PCH_EDP_PWM

1 1 1 1 1

1 1 1 1 1 1

CPU_EDP_TX0- {33} CPU_EDP_TX0+ {33} CPU_EDP_TX1- {33} CPU_EDP_TX1+ {33}

CPU_EDP_AUX# {33}

CPU_EDP_AUX {33}

VGA_AUX# {35}

VGA_AUX {35}

HDMI_HPD {34}

RC181 0_0402_5%

PCH_ENBKL {33}

PCH_EDP_PWM {33} PCH_ENVDD {33}

PAD @

TC15

PAD @

TC16

PAD @

TC17

PAD @

TC18

PAD @

TC27

PAD @

TC29

PAD @

TC31

PAD @

TC35

PAD @

TC36

PAD @

TC42

PAD @

TC43

1 2

2

confirmed with ITE, the HPD pull down resistor should follow ITE recommended resistor 4.7k~10Kohm

RC37

4.7K_0402_5%

1 2

12

RC13 100K_0402_5%

XDP_TCK

1 2

RC1546 0_0402_5%

1 2

RC1547 0_0402_5%

XDP_TDI PCH_JTAG_TDI

1 2

RC1548 0_0402_5%

1 2

RC1549 0_0402_5%

1 2

RC1550 0_0402_5%

check JTAG circuit?

DP_VGA_HPD {35}

EC_SCI# {8,44}

CPU_EDP_HPD {33}

JTAGX PCH_JTAG_TDO

1

GPP_E15

RC1551 51_0402_5% RC1543 51_0402_5%

PCH_JTAG_TMSXDP_TMS PCH_JTAG_TRST#XDP_TRST#

1 2

RC1601 10K_0402_5%

@

1 2

+3VS

+VCCSTG

DDP*_CTRLDATA strapping sampled on the ri sing edge of PWROK

Port

Strap Enable Disable

Port 1

DDPB_CTRLDATA

Port 2

DDPC_CTRLDATA

A A

5

Pull up to 3.3 V with 2.2Kohm

NC

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2014/12/11

LC Future Center Secret Data

Deciphered Date

2

2015/12/11

Title

MCP (DDI,EDP)

Size

Document Number Re v

Custom

Date: Sheet

Monday, July 27, 2015

BMWQ1&2_UMA

1

460

0.2

of

5

DDRA_DQ[0..63]{17}

D D

C C

DDRA_DQ0 DDRA_DQ1 DDRA_DQ2 DDRA_DQ3 DDRA_DQ4 DDRA_DQ5 DDRA_DQ6 DDRA_DQ7 DDRA_DQ8 DDRA_DQ9 DDRA_DQ10 DDRA_DQ11 DDRA_DQ12 DDRA_DQ13 DDRA_DQ14 DDRA_DQ15 DDRA_DQ16 DDRA_DQ17 DDRA_DQ18 DDRA_DQ19 DDRA_DQ20 DDRA_DQ21 DDRA_DQ22 DDRA_DQ23 DDRA_DQ24 DDRA_DQ25 DDRA_DQ26 DDRA_DQ27 DDRA_DQ28 DDRA_DQ29 DDRA_DQ30 DDRA_DQ31 DDRA_DQ32 DDRA_DQ33 DDRA_DQ34 DDRA_DQ35 DDRA_DQ36 DDRA_DQ37 DDRA_DQ38 DDRA_DQ39 DDRA_DQ40 DDRA_DQ41 DDRA_DQ42 DDRA_DQ43 DDRA_DQ44 DDRA_DQ45 DDRA_DQ46 DDRA_DQ47 DDRA_DQ48 DDRA_DQ49 DDRA_DQ50 DDRA_DQ51 DDRA_DQ52 DDRA_DQ53 DDRA_DQ54 DDRA_DQ55 DDRA_DQ56 DDRA_DQ57 DDRA_DQ58 DDRA_DQ59 DDRA_DQ60 DDRA_DQ61 DDRA_DQ62 DDRA_DQ63

4

UC1B

AL71

DDR0_DQ[0]

AL68

DDR0_DQ[1]

AN68

DDR0_DQ[2]

AN69

DDR0_DQ[3]

AL70

DDR0_DQ[4]

AL69

DDR0_DQ[5]

AN70

DDR0_DQ[6]

AN71

DDR0_DQ[7]

AR70

DDR0_DQ[8]

AR68

DDR0_DQ[9]

AU71

DDR0_DQ[10]

AU68

DDR0_DQ[11]

AR71

DDR0_DQ[12]

AR69

DDR0_DQ[13]

AU70

DDR0_DQ[14]

AU69

DDR0_DQ[15]

BB65

DDR0_DQ[16]/DDR0_DQ[32]

AW65

DDR0_DQ[17]/DDR0_DQ[33]

AW63

DDR0_DQ[18]/DDR0_DQ[34]

AY63

DDR0_DQ[19]/DDR0_DQ[35]

BA65

DDR0_DQ[20]/DDR0_DQ[36]

AY65

DDR0_DQ[21]/DDR0_DQ[37]

BA63

DDR0_DQ[22]/DDR0_DQ[38]

BB63

DDR0_DQ[23]/DDR0_DQ[39]

BA61

DDR0_DQ[24]/DDR0_DQ[40]

AW61

DDR0_DQ[25]/DDR0_DQ[41]

BB59

DDR0_DQ[26]/DDR0_DQ[42]

AW59

DDR0_DQ[27]/DDR0_DQ[43]

BB61

DDR0_DQ[28]/DDR0_DQ[44]

AY61

DDR0_DQ[29]/DDR0_DQ[45]

BA59

DDR0_DQ[30]/DDR0_DQ[46]

AY59

DDR0_DQ[31]/DDR0_DQ[47]

AY39

DDR0_DQ[32]/DDR1_DQ[0]

AW39

DDR0_DQ[33]/DDR1_DQ[1]

AY37

DDR0_DQ[34]/DDR1_DQ[2]

AW37

DDR0_DQ[35]/DDR1_DQ[3]

BB39

DDR0_DQ[36]/DDR1_DQ[4]

BA39

DDR0_DQ[37]/DDR1_DQ[5]

BA37

DDR0_DQ[38]/DDR1_DQ[6]

BB37

DDR0_DQ[39]/DDR1_DQ[7]

AY35

DDR0_DQ[40]/DDR1_DQ[8]

AW35

DDR0_DQ[41]/DDR1_DQ[9]

AY33

DDR0_DQ[42]/DDR1_DQ[10]

AW33

DDR0_DQ[43]/DDR1_DQ[11]

BB35

DDR0_DQ[44]/DDR1_DQ[12]

BA35

DDR0_DQ[45]/DDR1_DQ[13]

BA33

DDR0_DQ[46]/DDR1_DQ[14]

BB33

DDR0_DQ[47]/DDR1_DQ[15]

AY31

DDR0_DQ[48]/DDR1_DQ[32]

AW31

DDR0_DQ[49]/DDR1_DQ[33]

AY29

DDR0_DQ[50]/DDR1_DQ[34]

AW29

DDR0_DQ[51]/DDR1_DQ[35]

BB31

DDR0_DQ[52]/DDR1_DQ[36]

BA31

DDR0_DQ[53]/DDR1_DQ[37]

BA29

DDR0_DQ[54]/DDR1_DQ[38]

BB29

DDR0_DQ[55]/DDR1_DQ[39]

AY27

DDR0_DQ[56]/DDR1_DQ[40]

AW27

DDR0_DQ[57]/DDR1_DQ[41]

AY25

DDR0_DQ[58]/DDR1_DQ[42]

AW25

DDR0_DQ[59]/DDR1_DQ[43]

BB27

DDR0_DQ[60]/DDR1_DQ[44]

BA27

DDR0_DQ[61]/DDR1_DQ[45]

BA25

DDR0_DQ[62]/DDR1_DQ[46]

BB25

DDR0_DQ[63]/DDR1_DQ[47]

SKYLAKE-U_BGA1356

REV = 1 @

?

SKL_ULT

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]

DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]

DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]

DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]

DDR0_DQSN[2]/DDR0_DQSN[4] DDR0_DQSP[2]/DDR0_DQSP[4] DDR0_DQSN[3]/DDR0_DQSN[5] DDR0_DQSP[3]/DDR0_DQSP[5] DDR0_DQSN[4]/DDR1_DQSN[0] DDR0_DQSP[4]/DDR1_DQSP[0] DDR0_DQSN[5]/DDR1_DQSN[1] DDR0_DQSP[5]/DDR1_DQSP[1] DDR0_DQSN[6]/DDR1_DQSN[4] DDR0_DQSP[6]/DDR1_DQSP[4] DDR0_DQSN[7]/DDR1_DQSN[5] DDR0_DQSP[7]/DDR1_DQSP[5]

DDR CH - A

1 OF 20

DDR0_CKN[0] DDR0_CKP[0] DDR0_CKN[1] DDR0_CKP[1]

DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3]

DDR0_CS#[0] DDR0_CS#[1] DDR0_ODT[0] DDR0_ODT[1]

DDR0_MA[3] DDR0_MA[4]

DDR0_DQSN[0] DDR0_DQSP[0] DDR0_DQSN[1] DDR0_DQSP[1]

DDR0_ALERT#

DDR0_PAR

DDR_VREF_CA DDR0_VREF_DQ DDR1_VREF_DQ

DDR_VTT_CNTL

3

AU53 AT53 AU55 AT55

BA56 BB56 AW56 AY56

AU45 AU43 AT45 AT43

BA51 BB54 BA52 AY52 AW52 AY55 AW54 BA54 BA55 AY54

AU46 AU48 AT46 AU50 AU52 AY51 AT48 AT50 BB50 AY50 BA50 BB52

DDRA_DQS#0

AM70

DDRA_DQS0

AM69

DDRA_DQS#1

AT69

DDRA_DQS1

AT70

DDRA_DQS#2

BA64

DDRA_DQS2

AY64

DDRA_DQS#3

AY60

DDRA_DQS3

BA60

DDRA_DQS#4

BA38

DDRA_DQS4

AY38

DDRA_DQS#5

AY34

DDRA_DQS5

BA34

DDRA_DQS#6

BA30

DDRA_DQS6

AY30

DDRA_DQS#7

AY26

DDRA_DQS7

BA26 AW50

AT52 AY67

AY68 BA67

DDR_VTT_CNTL

AW67

?

DDRA_CLK0# {17} DDRA_CLK0 {17} DDRA_CLK1# {17} DDRA_CLK1 {17}

DDRA_CKE0 {17} DDRA_CKE1 {17}

DDRA_CS0# {17} DDRA_CS1# {17} DDRA_ODT0 {17} DDRA_ODT1 {17}

DDRA_MA5 {17} DDRA_MA9 {17} DDRA_MA6 {17} DDRA_MA8 {17} DDRA_MA7 {17} DDRA_BS2# {17} DDRA_MA12 {17} DDRA_MA11 {17} DDRA_MA15 {17} DDRA_MA14 {17}

DDRA_MA13 {17}

DDRA_CAS# {17}

DDRA_WE# {17}

DDRA_RAS# {17}

DDRA_BS0# {17} DDRA_MA2 {17} DDRA_BS1# {17} DDRA_MA10 {17} DDRA_MA1 {17} DDRA_MA0 {17} DDRA_MA3 {17} DDRA_MA4 {17}

CHECK

DDR_SM_VREFCA {17} DDR_SA_VREFDQ {17} DDR_SB_VREFDQ {18}

DDRA_DQS#[0..7] DDRA_DQS[0..7]

2

DDRA_DQS#[0..7] {17} DDRA_DQS[0..7] {17}

SMVREF

WIDTH:20MIL SPACING: 20MIL

1

B B

+1.35V

1 2

RC3

1K_0402_5%

DDR_VTT_CNTL

A A

5

4

RC29

10K_0402_5%

+3VALW

12

RC30 100K_0402_5%

C

2

QC18

B

E

3 1

MMBT3904WH_SOT323-3

@

1 2

CPU_DRAMPG_CNTL {55}

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITT EN CONSENT OF LC FUT URE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITT EN CONSENT OF LC FUT URE CENTER.

3

2014/12/11

LC Future Center Secret Data

Deciphered Date

2

2015/12/11

Title

MCP (DDR3LA)

Size

Document Number Re v

Custom

Date: Sheet

Monday, July 27, 2015

BMWQ1&2_UMA

1

560

0.2

of

5

DDRB_DQ[0..63]{18}

D D

C C

B B

DDRB_DQ0 DDRB_DQ1 DDRB_DQ2 DDRB_DQ3 DDRB_DQ4 DDRB_DQ5 DDRB_DQ6 DDRB_DQ7 DDRB_DQ8 DDRB_DQ9 DDRB_DQ10 DDRB_DQ11 DDRB_DQ12 DDRB_DQ13 DDRB_DQ14 DDRB_DQ15 DDRB_DQ16 DDRB_DQ17 DDRB_DQ18 DDRB_DQ19 DDRB_DQ20 DDRB_DQ21 DDRB_DQ22 DDRB_DQ23 DDRB_DQ24 DDRB_DQ25 DDRB_DQ26 DDRB_DQ27 DDRB_DQ28 DDRB_DQ29 DDRB_DQ30 DDRB_DQ31 DDRB_DQ32 DDRB_DQ33 DDRB_DQ34 DDRB_DQ35 DDRB_DQ36 DDRB_DQ37 DDRB_DQ38 DDRB_DQ39 DDRB_DQ40 DDRB_DQ41 DDRB_DQ42 DDRB_DQ43 DDRB_DQ44 DDRB_DQ45 DDRB_DQ46 DDRB_DQ47 DDRB_DQ48 DDRB_DQ49 DDRB_DQ50 DDRB_DQ51 DDRB_DQ52 DDRB_DQ53 DDRB_DQ54 DDRB_DQ55 DDRB_DQ56 DDRB_DQ57 DDRB_DQ58 DDRB_DQ59 DDRB_DQ60 DDRB_DQ61 DDRB_DQ62 DDRB_DQ63

4

AF65 AF64 AK65 AK64 AF66 AF67 AK67 AK66 AF70 AF68 AH71 AH68 AF71 AF69 AH70 AH69 AT66 AU66 AP65 AN65 AN66 AP66 AT65 AU65 AT61 AU61 AP60 AN60 AN61 AP61 AT60 AU60 AU40 AT40 AT37 AU37 AR40 AP40 AP37 AR37 AT33 AU33 AU30 AT30 AR33 AP33 AR30 AP30 AU27 AT27 AT25 AU25 AP27 AN27 AN25 AP25 AT22 AU22 AU21 AT21 AN22 AP22 AP21 AN21

UC1C

DDR1_DQ[0]/DDR0_DQ[16] DDR1_DQ[1]/DDR0_DQ[17] DDR1_DQ[2]/DDR0_DQ[18] DDR1_DQ[3]/DDR0_DQ[19] DDR1_DQ[4]/DDR0_DQ[20] DDR1_DQ[5]/DDR0_DQ[21] DDR1_DQ[6]/DDR0_DQ[22] DDR1_DQ[7]/DDR0_DQ[23] DDR1_DQ[8]/DDR0_DQ[24] DDR1_DQ[9]/DDR0_DQ[25] DDR1_DQ[10]/DDR0_DQ[26] DDR1_DQ[11]/DDR0_DQ[27] DDR1_DQ[12]/DDR0_DQ[28] DDR1_DQ[13]/DDR0_DQ[29] DDR1_DQ[14]/DDR0_DQ[30] DDR1_DQ[15]/DDR0_DQ[31] DDR1_DQ[16]/DDR0_DQ[48] DDR1_DQ[17]/DDR0_DQ[49] DDR1_DQ[18]/DDR0_DQ[50] DDR1_DQ[19]/DDR0_DQ[51] DDR1_DQ[20]/DDR0_DQ[52] DDR1_DQ[21]/DDR0_DQ[53] DDR1_DQ[22]/DDR0_DQ[54] DDR1_DQ[23]/DDR0_DQ[55] DDR1_DQ[24]/DDR0_DQ[56] DDR1_DQ[25]/DDR0_DQ[57] DDR1_DQ[26]/DDR0_DQ[58] DDR1_DQ[27]/DDR0_DQ[59] DDR1_DQ[28]/DDR0_DQ[60] DDR1_DQ[29]/DDR0_DQ[61] DDR1_DQ[30]/DDR0_DQ[62] DDR1_DQ[31]/DDR0_DQ[63] DDR1_DQ[32]/DDR1_DQ[16] DDR1_DQ[33]/DDR1_DQ[17] DDR1_DQ[34]/DDR1_DQ[18] DDR1_DQ[35]/DDR1_DQ[19] DDR1_DQ[36]/DDR1_DQ[20] DDR1_DQ[37]/DDR1_DQ[21] DDR1_DQ[38]/DDR1_DQ[22] DDR1_DQ[39]/DDR1_DQ[23] DDR1_DQ[40]/DDR1_DQ[24] DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQ[44]/DDR1_DQ[28] DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQ[47]/DDR1_DQ[31] DDR1_DQ[48] DDR1_DQ[49] DDR1_DQ[50] DDR1_DQ[51] DDR1_DQ[52] DDR1_DQ[53] DDR1_DQ[54] DDR1_DQ[55] DDR1_DQ[56] DDR1_DQ[57] DDR1_DQ[58] DDR1_DQ[59] DDR1_DQ[60] DDR1_DQ[61] DDR1_DQ[62] DDR1_DQ[63]

SKYLAKE-U_BGA1356

REV = 1

@

3

?

SKL_ULT

DDR1_CKN[0] DDR1_CKN[1] DDR1_CKP[0] DDR1_CKP[1]

DDR1_CKE[0] DDR1_CKE[1] DDR1_CKE[2] DDR1_CKE[3]

DDR1_CS#[0] DDR1_CS#[1] DDR1_ODT[0]

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]

DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]

DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]

DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]

DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]

DDR1_DQSN[0]/DDR0_DQSN[2]

DDR1_DQSP[0]/DDR0_DQSP[2]

DDR1_DQSN[1]/DDR0_DQSN[3]

DDR1_DQSP[1]/DDR0_DQSP[3]

DDR1_DQSN[2]/DDR0_DQSN[6]

DDR1_DQSP[2]/DDR0_DQSP[6]

DDR1_DQSN[3]/DDR0_DQSN[7]

DDR1_DQSP[3]/DDR0_DQSP[7]

DDR1_DQSN[4]/DDR1_DQSN[2]

DDR1_DQSP[4]/DDR1_DQSP[2]

DDR1_DQSN[5]/DDR1_DQSN[3]

DDR1_DQSP[5]/DDR1_DQSP[3]

DDR CH - B

1 OF 20

DDR1_ODT[1]

DDR1_DQSN[6] DDR1_DQSP[6] DDR1_DQSN[7] DDR1_DQSP[7]

DDR1_ALERT#

DRAM_RESET# DDR_RCOMP[0] DDR_RCOMP[1] DDR_RCOMP[2]

DDR1_MA[3] DDR1_MA[4]

DDR1_PAR

AN45 AN46 AP45 AP46

AN56 AP55 AN55 AP53

BB42 AY42 BA42 AW42

AY48 AP50 BA48 BB48 AP48 AP52 AN50 AN48 AN53 AN52

BA43 AY43 AY44 AW44 BB44 AY47 BA44 AW46 AY46 BA46 BB46 BA47

AH66 AH65 AG69 AG70 AR66 AR65 AR61 AR60 AT38 AR38 AT32 AR32 AR25 AR27 AR22 AR21

AN43 AP43 AT13 AR18 AT18 AU18

?

DDRB_DQS#0 DDRB_DQS0 DDRB_DQS#1 DDRB_DQS1 DDRB_DQS#2 DDRB_DQS2 DDRB_DQS#3 DDRB_DQS3 DDRB_DQS#4 DDRB_DQS4 DDRB_DQS#5 DDRB_DQS5 DDRB_DQS#6 DDRB_DQS6 DDRB_DQS#7 DDRB_DQS7

CPU_DRAMRST#_R SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2

2

DDRB_CLK0# {18} DDRB_CLK1# {18} DDRB_CLK0 {18} DDRB_CLK1 {18}

DDRB_CKE0 {18} DDRB_CKE1 {18}

DDRB_CS0# {18} DDRB_CS1# {18} DDRB_ODT0 {18} DDRB_ODT1 {18}

DDRB_MA5 {18} DDRB_MA9 {18} DDRB_MA6 {18} DDRB_MA8 {18} DDRB_MA7 {18} DDRB_BS2# {18} DDRB_MA12 {18} DDRB_MA11 {18} DDRB_MA15 {18} DDRB_MA14 {18}

DDRB_MA13 {18}

DDRB_CAS# {18}

DDRB_WE# {18}

DDRB_RAS# {18}

DDRB_BS0# {18} DDRB_MA2 {18} DDRB_BS1# {18} DDRB_MA10 {18} DDRB_MA1 {18} DDRB_MA0 {18} DDRB_MA3 {18} DDRB_MA4 {18}

DDRB_DQS#[0..7] DDRB_DQS[0..7]

1 2

RC24 121_0402_1%

1 2

RC25 80.6_0402_1%

1 2

RC26 100_0402_1%

1

DDRB_DQS#[0..7] {18} DDRB_DQS[0..7] {18}

Need to check the resistor value

+1.35V

12

RC22 470_0402_5%

RC23 0_0402_5%@

CPU_DRAMRST#{17,18}

1

EMC_NS@

CC1

0.01U_0402_25V7K

2

1 2

CPU_DRAMRST#_R

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND C ONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF LC FUTUR E CENTER .

MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF LC FUTUR E CENTER .

5

4

MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF LC FUTUR E CENTER .

3

2014/12/11

LC Future Center Secret Data

Deciphered Date

2

2015/12/11

Title

MCP (DDR3LB)

Size

Document Number Re v

Custom

Monday, July 27, 2015

Date: Sheet

Monday, July 27, 2015

BMWQ1&2_UMA

1

660

0.2

of

5

1 2

SPI_CLK{44}

SPI_SO{44}

D D

SPI_SI{44}

SPI_CS0#{44}

Check with BIOS, SPI is Dual mode or quad mode

SPI_WP#_R

C C

B B

A A

RC54 15_0402_5%

SPI_HOLD#_R

RC55 15_0402_5%

SPI_WP#_R SPI_WP#_1

SPI_HOLD#_R

+3VALW_PCH

RC1568 20K_0402_5% RC1565 20K_0402_5% RC1578 20K_0402_5% RC1580 20K_0402_5%

Follow CRB, need to check the strap ?

RC1567 4.7K_0402_5% RC1566 4.7K_0402_5% RC1581 4.7K_0402_5% RC64 1K_0402_5%

Based on WW36 SKL U&Y WOM, RC64 populated, and RC61 de-populated for SKL U ES sample. In this case, customers must ensure that the SPI flash device on the platform has HOLD functionality disabled by default.

RC1539 15_0402_5%

SPI_CLK_1

SPI_SO SPI_SO_1

SPI_SI SPI_SI_1

1 2

RC176 33_0402_5%@

RC178 33_0402_5%@

Follow CRB, need to check the strap ?

1 2

RC1538 33_0402_5%@

1 2

RC53 15_0402_5%

1 2

RC177 33_0402_5%@

1 2

RC52 15_0402_5%

1 2

RC175 33_0402_5%@

SPI_CS0# SPI_CS0#_R

@

1 2

@ @ @ @

@ @ @

@

1 2

RC51 0_0402_5%

1 2

RC174 0_0402_5%@

1K_0402_5%

12 12 12 12

12 12 12

@

RC60

RC179

+3V_SPI

12

+3V_SPI

12

@

SPI_SO_R SPI_SI_R SPI_WP#_R SPI_HOLD#_R

SPI_SO_R SPI_SI_R SPI_WP#_R

SPI_HOLD#_R

12

RC61 1K_0402_5%

SPI_WP#

SPI_HOLD#

RC180 1K_0402_5%

@

SPI_SO_R

SPI_SI_R

SPI_CS1#_RSPI_CS1#

SPI_HOLD#_1

BOARD_ID4{8}

KBRST#{44} SERIRQ{32,44}

+3VS

+3VALW_PCH

+3V_SPI

*

1. If support DS3, connect to +3VS and don't support EC mirror code;

2. If don't support DS3, connect to +3VALW_PCH and support EC mirror code.

SPI_CS0# SPI_SO SPI_WP#

SPI_CS1# SPI_SO_1 SPI_WP#_1

1 2 3

1 2 3 4

W25Q32FVSSIQ_SO8

SPI_CLK_RSPI_CLK SPI_CLK_R SPI_SO_R SPI_SI_R SPI_WP#_R SPI_HOLD#_R SPI_CS0#_R SPI_CS1#_R

BOARD_ID4

KBRST# SERIRQ

1 2

RC171 0_0402_5%@

1 2

RC172

0_0402_5%

UC3

VCC

CS# DO

HOLD#

CLK

WP# GND4DI

W25Q64FVSSIQ_SO8

UC6

CS#

VCC

DO

HOLD#

WP#

CLK

GND

DI

@

4

?

1

CC8 .1U_0402_10V6-K

2

CC97 .1U_0402_10V6-K

@

SKL_ULT

SMBUS, SMLINK

GPP_B23/SML1ALERT#/PCHHOT#

LPC

GPP_A5/LFRAME#/ESPI_CS#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

1 OF 20

check CLKRUN# / SUS_STAT# signal if need to connect

PM_CLKRUN#

SERIRQ

KBRST#

GPP_C2/SMBALERT#

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

GPP_C7/SML1DATA

GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3

GPP_A10/CLKOUT_LPC1

RC11 8.2K_0402_5%

RC12 10K_0402_5%

RC10 10K_0402_5%

CC1255 1000P_0402_50V7KEMC_NS@

PCH_SML1_CLK

PCH_SML1_DAT

UC1E

SPI - FLASH

AV2

SPI0_CLK

AW3

SPI0_MISO

AV3

SPI0_MOSI

AW2

SPI0_IO2

AU4

SPI0_IO3

AU3

SPI0_CS0#

AU2

SPI0_CS1#

AU1

SPI0_CS2#

SPI - TOUCH

M2

GPP_D1/SPI1_CLK

M3

GPP_D2/SPI1_MISO

J4

GPP_D3/SPI1_MOSI

V1

GPP_D21/SPI1_IO2

V2

GPP_D22/SPI1_IO3

M1

GPP_D0/SPI1_CS#

C LINK

G3

CL_CLK

G2

CL_DATA

G1

CL_RST#

AW13

GPP_A0/RCIN#

AY11

GPP_A6/SERIRQ

SKYLAKE-U_BGA1356

REV = 1 @

+3V_SPI

@

+3V_SPI

8

SPI_HOLD#

7

SPI_CLK

6

SPI_SI

5

+3V_SPI

8

SPI_HOLD#_1

7

SPI_CLK_1

6

SPI_SI_1

5

1

2

3

R7

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C3/SML0CLK

GPP_C6/SML1CLK

GPP_A8/CLKRUN#

R8 R10

R9 W2 W1

W3 V3 AM7

AY13 BA13 BB13 AY12 BA12 BA11

AW9 AY9 AW11

?

1 2

+3VALW_PCH +3VS

RPC25

2.2K_0404_4P2R_5%

1 4

2 3

PCH_SMB_CLK PCH_SMB_DATA SMB_ALERT#

SML0_CLK SML0_DATA SML0_ALERT#

PCH_SML1_CLK PCH_SML1_DAT SML1_ALERT#

SUS_STAT#

CLK_PCI_EC_R CLK_PCI_TPM_R PM_CLKRUN#

6 1

QC10A

D

2N7002KDWH_SOT363-6

@

DIMM1, DIMM2, NGFF

GPU, EC, Thermal Sensor

LPC_AD0 {32,44} LPC_AD1 {32,44} LPC_AD2 {32,44} LPC_AD3 {32,44}

LPC_FRAME# {32,44}

RC173 22_0402_5% RC1541 22_0402_5%

+3VS

2

G

S

5

G

3 4

QC10B

S

D

2N7002KDWH_SOT363-6

@

TPM@

2

+3VALW_PCH +3VS +3VS

RPC20

2.2K_0404_4P2R_5%

1

12 12

TC81@

CLK_PCI_EC {44} CLK_PCI_TPM {32}

EC_SMB_CK2 {39,44}

EC_SMB_DA2 {39,44}

2 3

PCH_SMB_CLK

PCH_SMB_DATA

To enable Direct Connect Interface (DCI), a 150K pull up resistor will need to be added to PCHHOT# pin. This pin must be low during the rising edge of RSMRST#. (Refer to WW52_MOW)

2

1 4

SMB_ALERT#

SML0_ALERT#

SML1_ALERT#

G

6 1

QC2A

S

D

2N7002KDWH_SOT363-6

SML0_CLK SML0_DATA

This signal has a weak internal pull-down. 0 = LPC Is selected for EC. (Default) 1 = eSPI Is selected for EC. Notes:

1. The internal pull-down is disabled after RSMRST# de-asserts.

2. This signal is in the primary wel Rising edge of RSMRST#

5

G

3 4

QC2B

S

D

2N7002KDWH_SOT363-6

12

RC15622.2K_0402_5%

RPC23

14 23

2.2K_0404_4P2R_5%

@

12

RC1564 2.2K_0402_5%

1 2

RC1569 150K_0402_5%

1 4

2 3

RPC24

2.2K_0404_4P2R_5%

+3VALW_PCH

1

SMB_CLK_S3 {17,18,40}

SMB_DATA_S3 {17,18,40}

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2014/12/11

LC Future Center Secret Data

2

Deciphered Date

2015/12/11

Title

MPC (MISC,JTAG,SPI,LPC,SMB)

Size Document Number Re v

Custom

Date: Sheet

Monday, July 27, 2015

1

BMWQ1&2_UMA

760

of

0.2

5

@

1 2

+3VS

D D

1 2

RC1558 10K_0402_5%UMA@

+3VALW_PCH

@

+3VS

12

@

12 12 12

1 2

RC1600 1K_0402_5%@

1 2

RC47 1K_0402_5%@

RC1593 10K_0402_5%

+3VS

C C

RC1595 10K_0402_5% RC1596 10K_0402_5% RC1597 10K_0402_5%

double check if need the pull up resisor

+3VALW_PCH

*

HDA_SDO This signal has a weak internal pull-down. 0 = Enable security measures defined in the Flash Descriptor. 1 = Disable Flash Descriptor Security(override). This strap should only be asserted high during external pull-up in manufacturing/debug environments ONLY.

For EMI

1

B B

EMC_NS@

CC7 10P_0402_50V8J

2

VGA_PWRGD

ODD_EN

CMOS_ON# PCH_WLAN_OFF# PCH_BT_OFF#

HDA_SDIN0

HDA_SDOUT

RC1561 2.2K_0402_5%

1 2

RC1602 10K_0402_5%

@ @

1 2

RC1563 2.2K_0402_5%

CMOS_ON#{33}

EC_SCI#{4,44}

UART_RX_DEBUG{40} UART_TX_DEBUG{40}

UART2_RXD{40} UART2_TXD{40}

PCH_WLAN_OFF#{40} PCH_BT_OFF#{40}

HDA_SYNC_AUDIO{43} HDA_BITCLK_AUDIO{43}

HDA_SDIN0{43} HDA_RST_AUDIO#{43}

RC183 0_0402_5%

PCH_BEEP{43}

4

GPP_B18

EC_SCI#_R

GPP_B22

1 2

@

RC43 33_0402_5% RC42 33_0402_5%

RC44 33_0402_5%

1 2 1 2

1 2

GPP_B18

CMOS_ON# EC_SCI#_R GPP_B22

VGA_PWRGD

ODD_EN

PCH_WLAN_OFF# PCH_BT_OFF#

AN8 AP7 AP8 AR7

AM5 AN7 AP5 AN5

AB1 AB2

AB3 AD1

AD2 AD3 AD4

AH9

AH10 AH11

AH12 AF11

AF12

HDA_SYNC HDA_BCLK HDA_SDOUT HDA_SDIN0

HDA_RST#

PCH_BEEP

UC1F

GPP_B15/GSPI0_CS# GPP_B16/GSPI0_CLK GPP_B17/GSPI0_MISO GPP_B18/GSPI0_MOSI

GPP_B19/GSPI1_CS# GPP_B20/GSPI1_CLK GPP_B21/GSPI1_MISO GPP_B22/GSPI1_MOSI

GPP_C8/UART0_RXD GPP_C9/UART0_TXD

W4

GPP_C10/UART0_RTS# GPP_C11/UART0_CTS#

GPP_C20/UART2_RXD GPP_C21/UART2_TXD GPP_C22/UART2_RTS# GPP_C23/UART2_CTS#

U7

GPP_C16/I2C0_SDA

U6

GPP_C17/I2C0_SCL

U8

GPP_C18/I2C1_SDA

U9

GPP_C19/I2C1_SCL GPP_F4/I2C2_SDA

GPP_F5/I2C2_SCL GPP_F6/I2C3_SDA

GPP_F7/I2C3_SCL GPP_F8/I2C4_SDA

GPP_F9/I2C4_SCL

SKYLAKE-U_BGA1356

REV = 1

@

BA22 AY22 BB22 BA21 AY21

AW22

J5

AY20

AW20

AK7 AK6 AK9

AK10

H5 D7

D8 C8

AW5

3

?

REV = 1

SKL_ULT

GPP_F10/I2C5_SDA/ISH_I2C2_SDA

GPP_F11/I2C5_SCL/ISH_I2C2_SCL

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_C15/UART1_CTS#/ISH_UART1_CTS#

GPP_A12/BM_BUSY#/ISH_GP6

1 OF 20

?

SKL_ULT

SDIO/SDXC

GPP_A17/SD_PWR_EN#/ISH_GP7

1 OF 20

LPSS ISH

UC1G

AUDIO

HDA_SYNC/I2S0_SFRM HDA_BLK/I2S0_SCLK HDA_SDO/I2S0_TXD HDA_SDI0/I2S0_RXD HDA_SDI1/I2S1_RXD HDA_RST#/I2S1_SCLK GPP_D23/I2S_MCLK I2S1_SFRM I2S1_TXD

GPP_F1/I2S2_SFRM GPP_F0/I2S2_SCLK GPP_F2/I2S2_TXD GPP_F3/I2S2_RXD

GPP_D19/DMIC_CLK0 GPP_D20/DMIC_DATA0

GPP_D17/DMIC_CLK1 GPP_D18/DMIC_DATA1

GPP_B14/SPKR

SKYLAKE-U_BGA1356

@

GPP_D9 GPP_D10 GPP_D11 GPP_D12

GPP_D5/ISH_I2C0_SDA GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA GPP_D8/ISH_I2C1_SCL

GPP_D15/ISH_UART0_RTS#

GPP_A18/ISH_GP0 GPP_A19/ISH_GP1 GPP_A20/ISH_GP2 GPP_A21/ISH_GP3 GPP_A22/ISH_GP4 GPP_A23/ISH_GP5

GPP_G0/SD_CMD GPP_G1/SD_DATA0 GPP_G2/SD_DATA1 GPP_G3/SD_DATA2 GPP_G4/SD_DATA3

GPP_G5/SD_CD# GPP_G6/SD_CLK

GPP_G7/SD_WP

GPP_A16/SD_1P8_SEL

SD_RCOMP

GPP_F23

?

AB11 AB13 AB12 W12 W11 W10 W8 W7

BA9 BB9

AB7

AF13

BOARD_ID0

P2

BOARD_ID1

P3 P4

BOARD_ID3

P1 M4

BOARD_ID5

N3 N1

N2 AD11

AD12

U1 U2 U3 U4

AC1 AC2 AC3 AB4

AY8 BA8 BB7 BA7 AY7 AW7

GPP_A12

AP13

check GPP_A12

SD_CMD_PCH SD_D0_PCH SD_D1_PCH SD_D2_PCH SD_D3_PCH SD_CD#_PCH SD_CLK_PCH SD_WP_PCH

SD_PWR_EN# SD_1P8_SEL

SD_RCOMP

2

BOARD_ID2{9} BOARD_ID4{7}

1

TC82 @

SD_CMD_PCH {30}

SD_D0_PCH {30} SD_D1_PCH {30} SD_D2_PCH {30} SD_D3_PCH {30}

SD_CD#_PCH {30}

SD_CLK_PCH {30}

SD_WP_PCH {30}

SD_PWR_EN# {44}

1 2

RC49 200_0402_1%

SD_1P8_SEL {30}

BOARD_ID0 BOARD_ID1 BOARD_ID2 BOARD_ID3 BOARD_ID4 BOARD_ID5

17@

15@

RC1615

1 2

10K_0402_5%

14or15@

14or17@

RC1616

1 2

10K_0402_5%

Board ID Description

Board_ID[0:1]

Board_ID2 Non-touch

Board_ID3 UMA

Board_ID4

Board_ID5 SingleMIC

RC1613

1 2

10K_0402_5%

RC1614

1 2

10K_0402_5%

TS@

NTS@

RC1611

1 2

RC1612

1 2

00 01 10 11 0 1 0 1 0 1 0 1

1

DUALRANK@

PX@

RC1609

1 2

10K_0402_5%

SINGLERANK@

UMA@

RC1610

1 2

10K_0402_5%

14" 15" 17" Reserved

Touch

DIS SingleRankRC1607 DualRank

DualMIC

+3VS

DUALMIC@

RC1608

1 2

10K_0402_5%

SINGLEMIC@

RC1607

1 2

10K_0402_5%

Stuff R RC1616

RC1614 RC1616 RC1613 RC1615

RC1614

RC1612 RC1611 RC1610 RC1609

RC1608 RC123 RC1606

RC1606

1 2

10K_0402_5%

RC123

10K_0402_5%

1 2

HDA_SDOUT_AUDIO{43} ME_FLASH{44}

RC45 33_0402_5%

1 2

RC46 0_0402_5%

@

Pin Name Strap Description Configuration

Internal PD

SPKR /

Top Swap

GPP_B14

Override

GSPI0_MOSI

A A

/GPP_B18

GSPI1_MOSI /GPP_B22

No Reboot

Boot BIOS Strap Bit BBS

5

0 = Disable “ Top Swap” mode. (Default) 1 = Enable “ Top Swap” mode.

Internal PD

0 = Disable “ No Reboot” mode. (Default) 1 = Enable “ No Reboot” mode

Internal PD 0 = SPI (Default) 1 = LPC

HDA_SDOUT

*

Default

When

Value

Sampled

0*Rising edge

of PCH_PWROK

0*Rising edge

of PCH_PWROK

Rising edge

0

of PCH_PWROK

4

+3VS

@

1 2

RC14 2.2K_0402_5%

PCH_BEEP

SD_PWR_EN#

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2014/12/11

LC Future Center Secret Data

PCH_SDIO@

1 2

RC1603 49.9K_0402_1%

Deciphered Date

2

+3VALW_PCH

2015/12/11

Title

MCP (LPSS,ISH,AUDIO,SDIO)

Size

Document Number Re v

Custom

Monday, July 27, 2015

Date: Sheet

BMWQ1&2_UMA

1

860

0.2

of

5

4

3

2

1

USB30_RX_N1

H8

USB30_RX_P1

G8

USB30_TX_N1

C13

USB30_TX_P1

D13 J6

H6 B13 A13

J10 H10 B15 A15

E10 F10 C15 D15

USB20_N1

AB9

USB20_P1

AB10

USB20_N2

AD6

USB20_P2

AD7

USB20_N3

AH3

USB20_P3

AJ3

USB20_N4

AD9

USB20_P4

AD10

USB20_N5

AJ1

USB20_P5

AJ2

USB20_N6

AF6

USB20_P6

AF7

USB20_N7

AH1

USB20_P7

AH2 AF8

AF9 AG1

AG2 AH7

AH8

USB2_COMP

AB6

USB2_ID

AG3

USB2_VBUSSENSE

AG4

USB_OC0#

A9

USB_OC1#

C9

USB_OC2#

D9

USB_OC3#

B9

GPP_E4

J1

GPP_E5

J2 J3

H2

SATA0GP ODD_DETECT#

H3 G4

SATA2GP BOARD_ID2

H1

PCIE1

USB30_RX_N1 {41} USB30_RX_P1 {41} USB30_TX_N1 {41}

USB30_TX_P1 {41}

USB20_N1 {41} USB20_P1 {41}

USB20_N2 {45} USB20_P2 {45}

USB20_N3 {45} USB20_P3 {45}

USB20_N4 {33} USB20_P4 {33}

USB20_N5 {30} USB20_P5 {30}

USB20_N6 {33} USB20_P6 {33}

USB20_N7 {40} USB20_P7 {40}

RC118 113_0402_1%

1 2

RC1635 0_0402_5%

1 2

RC1634 1K_0402_5%

1 2

RC1636 0_0402_5%

@

GPP_E4

@

RC1617 10K_0402_5%

LEFT USB (3.0)

LEFT USB (3.0) RIGHT USB (2.0)

RIGHT USB (2.0) Camera Card reader

Touch panel

BT

12

USB_OC1# {41} USB_OC2# {45}

EC_SMI# {44}

1

TC202PAD@

ODD_DETECT#

BOARD_ID2 {8}

+3VS

12

USBRBIAS

Width 20Mil Space 15Mil Length 500Mil

D D

PCIE_PRX_DTX_N5{37}

C C

LAN PCIE5

WLAN PCIE6

B B

PCIE_PRX_DTX_P5{37} PCIE_PTX_C_DRX_N5{37} PCIE_PTX_C_DRX_P5{37}

PCIE_PRX_DTX_N6{40} PCIE_PRX_DTX_P6{40} PCIE_PTX_C_DRX_N6{40} PCIE_PTX_C_DRX_P6{40}

RC119 100_0402_1%

+3VS

1 2

CC22 .1U_0402_10V6-K

1 2

CC23 .1U_0402_10V6-K

1 2

CC24 .1U_0402_10V6-K

1 2

CC25 .1U_0402_10V6-K

SATA_PRX_DTX_N0{42} SATA_PRX_DTX_P0{42} SATA_PTX_DRX_N0{42} SATA_PTX_DRX_P0{42}

SATA_PRX_DTX_N1{42} SATA_PRX_DTX_P1{42} SATA_PTX_DRX_N1{42} SATA_PTX_DRX_P1{42}

1 2

TC20PAD @ TC19PAD @

RPC2

1 8 2 7 3 6 4 5

10K_0804_8P4R_5%

ODD_DETECT# SATA0GP SATA2GP PIRQA#

PCIE_PRX_DTX_N5 PCIE_PRX_DTX_P5 PCIE_PTX_DRX_N5 PCIE_PTX_DRX_P5

PCIE_PRX_DTX_N6 PCIE_PRX_DTX_P6 PCIE_PTX_DRX_N6 PCIE_PTX_DRX_P6

SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 SATA_PTX_DRX_N0 SATA_PTX_DRX_P0

SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 SATA_PTX_DRX_N1 SATA_PTX_DRX_P1

PCIE_RCOMPN PCIE_RCOMPP

XDP_PRDY#

1

XDP_PREQ#

1

PIRQA#

UC1H

PCIE/USB3/SATA

H13

PCIE1_RXN/USB3_5_RXN

G13

PCIE1_RXP/USB3_5_RXP

B17

PCIE1_TXN/USB3_5_TXN

A17

PCIE1_TXP/USB3_5_TXP

G11

PCIE2_RXN/USB3_6_RXN

F11

PCIE2_RXP/USB3_6_RXP

D16

PCIE2_TXN/USB3_6_TXN

C16

PCIE2_TXP/USB3_6_TXP

H16

PCIE3_RXN

G16

PCIE3_RXP

D17

PCIE3_TXN

C17

PCIE3_TXP

G15

PCIE4_RXN

F15

PCIE4_RXP

B19

PCIE4_TXN

A19

PCIE4_TXP

F16

PCIE5_RXN

E16

PCIE5_RXP

C19

PCIE5_TXN

D19

PCIE5_TXP

G18

PCIE6_RXN

F18

PCIE6_RXP

D20

PCIE6_TXN

C20

PCIE6_TXP

F20

PCIE7_RXN/SATA0_RXN

E20

PCIE7_RXP/SATA0_RXP

B21

PCIE7_TXN/SATA0_TXN

A21

PCIE7_TXP/SATA0_TXP

G21

PCIE8_RXN/SATA1A_RXN

F21

PCIE8_RXP/SATA1A_RXP

D21

PCIE8_TXN/SATA1A_TXN

C21

PCIE8_TXP/SATA1A_TXP

E22

PCIE9_RXN

E23

PCIE9_RXP

B23

PCIE9_TXN

A23

PCIE9_TXP

F25

PCIE10_RXN

E25

PCIE10_RXP

D23

PCIE10_TXN

C23

PCIE10_TXP

F5

PCIE_RCOMPN

E5

PCIE_RCOMPP

D56

PROC_PRDY#

D61

PROC_PREQ#

BB11

GPP_A7/PIRQA#

E28

PCIE11_RXN/SATA1B_RXN

E27

PCIE11_RXP/SATA1B_RXP

D24

PCIE11_TXN/SATA1B_TXN

C24

PCIE11_TXP/SATA1B_TXP

E30

PCIE12_RXN/SATA2_RXN

F30

PCIE12_RXP/SATA2_RXP

A25

PCIE12_TXN/SATA2_TXN

B25

PCIE12_TXP/SATA2_TXP

SKYLAKE-U_BGA1356

REV = 1

@

USB_OC0# USB_OC1# USB_OC3# USB_OC2#

SKL_ULT

10K_0804_8P4R_5%

?

USB2

1 OF 20

RPC17

SSIC / USB3

GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2

18 27 36 45

USB3_1_RXN USB3_1_RXP USB3_1_TXN

USB3_1_TXP

USB3_2_RXN/SSIC_1_RXN

USB3_2_RXP/SSIC_1_RXP USB3_2_TXN/SSIC_1_TXN

USB3_2_TXP/SSIC_1_TXP

USB3_3_RXN/SSIC_2_RXN

USB3_3_RXP/SSIC_2_RXP USB3_3_TXN/SSIC_2_TXN

USB3_3_TXP/SSIC_2_TXP

USB3_4_RXN USB3_4_RXP USB3_4_TXN

USB3_4_TXP

USB2N_1 USB2P_1

USB2N_2 USB2P_2

USB2N_3 USB2P_3

USB2N_4 USB2P_4

USB2N_5 USB2P_5

USB2N_6 USB2P_6

USB2N_7 USB2P_7

USB2N_8 USB2P_8

USB2N_9 USB2P_9

USB2N_10 USB2P_10

USB2_COMP

USB2_ID

USB2_VBUSSENSE

GPP_E9/USB2_OC0# GPP_E10/USB2_OC1# GPP_E11/USB2_OC2# GPP_E12/USB2_OC3#

GPP_E4/DEVSLP0 GPP_E5/DEVSLP1 GPP_E6/DEVSLP2

GPP_E8/SATALED#

?

+3VALW_PCH

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND C ONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF LC FUTUR E CENTER .

MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF LC FUTUR E CENTER .

5

4

MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF LC FUTUR E CENTER .

3

2014/12/11

LC Future Center Secret Data

Deciphered Date

2

2015/12/11

Title

MCP (PCIE,SATA,USB3,USB2)

Size

Document Number Re v

Custom

Monday, July 27, 2015

Date: Sheet

Monday, July 27, 2015

BMWQ1&2_UMA

1

960

0.2

of

5

D D

check the Pull up resistor

+3VS

C C

B B

check if need to change to 1M_0402_1% follow PDG, CRB is 1M_0402_5%

RPC3

@ 1 8 2 7 3 6 4 5

10K_0804_8P4R_5%

RPC4

1 8 2 7 3 6 4 5

10K_0804_8P4R_5%

PCIE CLK5

PCIE CLK6

PCIE_CLKREQ2# PCIE_CLKREQ3# PCIE_CLKREQ1#

GPU_CLKREQ# LAN_CLKREQ#

WLAN_CLKREQ#

LAN

WLAN

CLK_PCIE_LAN#{37} CLK_PCIE_LAN{37}

LAN_CLKREQ#{37}

CLK_PCIE_WLAN#{40} CLK_PCIE_WLAN{40}

WLAN_CLKREQ#{40}

4

XTAL24_IN

CC12

2.7P_0402_50V9-B

GPU_CLKREQ#

PCIE_CLKREQ1#

PCIE_CLKREQ2#

PCIE_CLKREQ3# CLK_PCIE_LAN#

CLK_PCIE_LAN LAN_CLKREQ#

CLK_PCIE_WLAN# CLK_PCIE_WLAN WLAN_CLKREQ#

1

2

AR10

AT10

RC71 1M_0402_5%

GND12OSC2

1

OSC1

YC2

24MHZ_6PF_X1E000021088000

UC1I

CSI-2

A36

CSI2_DN0

B36

CSI2_DP0

C38

CSI2_DN1

D38

CSI2_DP1

C36

CSI2_DN2

D36

CSI2_DP2

A38

CSI2_DN3

B38

CSI2_DP3

C31

CSI2_DN4

D31

CSI2_DP4

C33

CSI2_DN5

D33

CSI2_DP5

A31

CSI2_DN6

B31

CSI2_DP6

A33

CSI2_DN7

B33

CSI2_DP7

A29

CSI2_DN8

B29

CSI2_DP8

C28

CSI2_DN9

D28

CSI2_DP9

A27

CSI2_DN10

B27

CSI2_DP10

C27

CSI2_DN11

D27

CSI2_DP11

SKYLAKE-U_BGA1356

@

UC1J

D42

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0 GPP_B5/SRCCLKREQ0#

B42

CLKOUT_PCIE_N1

A42

CLKOUT_PCIE_P1

AT7

GPP_B6/SRCCLKREQ1#

D41

CLKOUT_PCIE_N2

C41

CLKOUT_PCIE_P2

AT8

GPP_B7/SRCCLKREQ2#

D40

CLKOUT_PCIE_N3

C40

CLKOUT_PCIE_P3 GPP_B8/SRCCLKREQ3#

B40

CLKOUT_PCIE_N4

A40

CLKOUT_PCIE_P4

AU8

GPP_B9/SRCCLKREQ4#

E40

CLKOUT_PCIE_N5

E38

CLKOUT_PCIE_P5

AU7

GPP_B10/SRCCLKREQ5#

SKYLAKE-U_BGA1356

REV = 1

@

12

3 4

GND2

REV = 1

1

2

SKL_ULT

CLOCK SIGNALS

XTAL24_OUT

CC11

2.7P_0402_50V9-B

?

EMMC

GPP_F13/EMMC_DATA0 GPP_F14/EMMC_DATA1 GPP_F15/EMMC_DATA2 GPP_F16/EMMC_DATA3 GPP_F17/EMMC_DATA4 GPP_F18/EMMC_DATA5 GPP_F19/EMMC_DATA6 GPP_F20/EMMC_DATA7

GPP_F21/EMMC_RCLK

GPP_F12/EMMC_CMD

1 OF 20

?

1 OF 20

3

CSI2_CLKN0

CSI2_CLKP0

CSI2_CLKN1

CSI2_CLKP1

CSI2_CLKN2

CSI2_CLKP2

CSI2_CLKN3

CSI2_CLKP3 CSI2_COMP

GPP_D4/FLASHTRIG

GPP_F22/EMMC_CLK

EMMC_RCOMP

?

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

GPD8/SUSCLK

XCLK_BIASREF

C37 D37 C32 D32 C29 D29 B26 A26

CSI2_COMP

E13 B7

AP2 AP1 AP3 AN3 AN1 AN2 AM4 AM1

AM2 AM3 AP4

EMMC_RCOMP

AT1

F43 E43

BA17

SUSCLK XTAL24_IN

E37

XTAL24_IN

XTAL24_OUT

RTCX1 RTCX2

SRTCRST#

RTCRST#

?

E35 E42 AM18

AM20 AN18

AM16

XTAL24_OUT DIFFCLK_BIASREF RTC_X1

RTC_X2 SRTC_RST#

RTC_RST#

change to SJ10000LM00

RC32 10M_0402_5%

2

CC4 7P_0402_50V8J

1

12

YC1

1 2

X1A000141000200

2

1 2

RC73 100_0402_1%

1 2

RC50 200_0402_1%

1 2

RC72 2.7K_0402_1%

VCCRTC

1 2

RC33 20K_0402_1%

1 2

RC34 20K_0402_1%

RTC_X1

RTC_X2

2

CC5 7P_0402_50V8J

1

RC95 1K_0402_5%@

DIFFCLK_BIASREF

RC1624

1 2

1 2 Cannonlake@

1 2

@

RC1555

60.4_0402_1%

0_0402_5%

SUSCLK

SUSCLK {40}

+VCCCLK5

1

CC3

1U_0402_10V6K

when single end external clock generator used, this pin should be grounded

CC6

2

1

2

SRTC_RST# RTC_RST#

12

JCMOS1 SHORT PADS

@

EC_RTC_RST# {44}

need to use 38.4MHz (30ohm) for Cannonlake-u

GCLK@

1 2

A A

24M_CLK{31}

RC122

GCLK@

1 2

0_0402_5%

XTAL24_IN

RTC_CLK{31}

RC121

0_0402_5%

RTC_X1

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND C ONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF LC FUTUR E CENTER .

MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF LC FUTUR E CENTER .

5

4

MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF LC FUTUR E CENTER .

3

2014/12/11

LC Future Center Secret Data

Deciphered Date

2

2015/12/11

Title

MCP (CSI2,EMMC,CLOCK)

Size

Document Number Re v

Custom

Monday, July 27, 2015

Date: Sheet

Monday, July 27, 2015

BMWQ1&2_UMA

1

10 60

0.2

of

5

check if need one buffer

12

CC1254

1 2

1000P_0402_50V7K

CC104

1 2

1000P_0402_50V7K

CC103

1 2

1000P_0402_50V7K

EMC_NS@

1 2

1000P_0402_50V7K

RPC21

PLT_RST#{32,37,40,44}

EC_RSMRST#{44}

SYS_PWROK{44} PCH_PWROK{44}

SUSWARN#{44}

EMC_NS@

SUSACK#{44}

PCIE_WAKE#{37,40,44}

AC_PRESENT_R BATLOW# WAKE#

PCH_LAN_WAKE#

SUSWARN#_R

PCH_RSMRST#_R

PCH_PWROK

PCH_DPWROK_R

SYS_PWROK

PCH_RSMRST#_R PCH_PWROK SYS_PWROK

TC21PAD@

VCCST_PWRGD_R

Reserve for DS3

TC203PAD @

Follow CRB change to 1kohm

EC_VCCST_PWRGD{44}

1

D D

+3VALW

1 2

RC74 10K_0402_5%

1 2

RC75 8.2K_0402_5% RC76 1K_0402_5%

1 2

C C

B B

RC90 10K_0402_5%

+3VALW_PCH

1 2

RC78 10K_0402_5%@

CC101

1 8 2 7 3 6 4 5

10K_0804_8P4R_5%

4

@

1 2

RC84 0_0402_5%

@

1 2

RC85 0_0402_5%

1 2

RC93 60.4_0402_1%

1 2

RC139 0_0402_5%@

1 2

RC126 0_0402_5%@

1 2

RC86 0_0402_5%@

1 2

RC79 0_0402_5%@

1 2

RC91 0_0402_5%@

+3VS

1 2

RC80 10K_0402_5%

PLT_RST#_R SYS_RESET# PCH_RSMRST#_R

CPU_PROCPWRGD VCCST_PWRGD

SYS_PWROK_R PCH_PWROK_R PCH_DPWROK_R

SUSWARN#_R SUSACK#_R

WAKE# PCH_LAN_WAKE#

GPD11

SYS_RESET#

UC1K

SYSTEM POWER MANAGEMENT

AN10

GPP_B13/PLTRST#

B5

SYS_RESET#

AY17

RSMRST#

A68

PROCPWRGD

B65

VCCST_PWRGD

B6

SYS_PWROK

BA20

PCH_PWROK

BB20

DSW_PWROK

AR13

GPP_A13/SUSWARN#/SUSPWRDNACK

AP11

GPP_A15/SUSACK#

BB15

WAKE#

AM15

GPD2/LAN_WAKE#

AW17

GPD11/LANPHYPC

AT15

GPD7/RSVD

SKYLAKE-U_BGA1356

REV = 1

@

1 2

RC138 0_0402_5%

@

1

CC46

0.01U_0402_16V7K

EMC_NS@

2

3

?

SKL_ULT

1 OF 20

2

G

@

1 2

RC1599 0_0402_5%@

GPP_B11/EXT_PWR_GATE#

+3VALW

RC136 10K_0402_5%

1 2

@

61

D

QC6A 2N7002KDWH_SOT363-6

S

GPP_B12/SLP_S0#

GPD4/SLP_S3# GPD5/SLP_S4#

GPD10/SLP_S5#

SLP_SUS# SLP_LAN#

GPD9/SLP_WLAN#

GPD6/SLP_A#

GPD3/PWRBTN#

GPD1/ACPRESENT

GPD0/BATLOW#

GPP_A11/PME#

INTRUDER#

GPP_B2/VRALERT#

PM_SLP_S0#_R

AT11

PM_SLP_S3#_R

AP15

PM_SLP_S4#_R

BA16

PM_SLP_S5#

AY16

PM_SLP_SUS#_R

AN15 AW15 BB17 AN16

PBTN_OUT#_R

BA15

AC_PRESENT_R

AY15 AU13

BATLOW#

AU11

PME#

AP16

INTVRMEN

AM10 AM11

?

+VCCST_CPU +VCCSTG

RC137 1K_0402_5%

1 2

34

D

5

G

@

QC6B 2N7002KDWH_SOT363-6

S

2

1 1

TC40 PAD@

1

TC41 PAD@ TC44 PAD@

1

TC89 @

1

TC93 @

1

TC96 @

AC_PRESENT{44}

@

RC1554 1K_0402_5%

1 2

VCCST_PWRGD_R

1

TC204 PAD @

1 2

RC96 0_0402_5%@

1 2

RC97 0_0402_5%@

1 2

RC89 0_0402_5%@

Reserve for DS3

1 2

RC87 0_0402_5%@

1 2

RC88 0_0402_5%@

ACIN#{44}

2

CC140 1000P_0402_50V7K

1

EMC_NS@

12

RC41 330K_0402_5%

PM_SLP_S3# {11,13,44} PM_SLP_S4# {44} PM_SLP_S5# {44}

PM_SLP_SUS# {44}

PBTN_OUT# {44}

VCCRTC

13

D

2

G

S

AC_PRESENT_R

@

QC8 2N7002KW_SOT323-3

1

1 2

PM_SLP_S3#{11,13,44}

PLT_RST#_R

12

RC92100K_0402_5%

PCH_DPWROK_R

12

RC94100K_0402_1% @

A A

5

DC4

RB751V-40_SOD323-2

4

@

1 2

RC182 0_0402_5%@

PCH_DPWROK_R

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND C ONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF LC FUTUR E CENTER .

MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF LC FUTUR E CENTER .

3

2014/12/11

1 2

RC81 0_0402_5%@

LC Future Center Secret Data

Deciphered Date

EC_RSMRST#

Reserve for DS3

DPWROK_EC {44}

2015/12/11

2

Title

MCP (SYSTEM PWR MANAGEMENT)

Size

Document Number Re v

Custom

Monday, July 27, 2015

Date: Sheet

Monday, July 27, 2015

BMWQ1&2_UMA

1

11 60

0.2

of

5

+CPU_CORE +CPU_CORE

D D

@

1

TC90

1

TC91

@

U23E@

1

2

U23E@

+V1.8S_EDRAM

VCCOPC_SENSE VSSOPC_SENSE

2.0A

VCCEOPIO_SENSE VSSEOPIO_SENSE

1

CC1264

2

1U_0201_6.3V6-M

U23E@

2.5A

0.05A

CC1259

1U_0201_6.3V6-M

U23E@

1

CC1260

2

1U_0201_6.3V6-M

U23E@

+VCCOPC_1.0V

+1.8VALW

C C

1 2

RC1626 0_0402_5%

VCCOPC_SENSE{57} VSSOPC_SENSE{57}

+VCCEOPIO

+VCCOPC_1.0V

1

CC1265

2

10U_0402_6.3V6-M

U23E@

1

2

A30 A34 A39

A44 AK33 AK35 AK37 AK38 AK40

AL33 AL37

AL40 AM32 AM33 AM35 AM37 AM38

G30

K32 AK32 AB62

P62

V62

H63 G61

AC63 AE63

AE62 AG62

AL63 AJ62

CC1261

1U_0201_6.3V6-M

U23E@

UC1L

VCC_A30 VCC_A34 VCC_A39 VCC_A44 VCC_AK33 VCC_AK35 VCC_AK37 VCC_AK38 VCC_AK40 VCC_AL33 VCC_AL37 VCC_AL40 VCC_AM32 VCC_AM33 VCC_AM35 VCC_AM37 VCC_AM38 VCC_G30

RSVD_K32 RSVD_AK32 VCCOPC_AB62

VCCOPC_P62 VCCOPC_V62

VCC_OPC_1P8_H63 VCC_OPC_1P8_G61 VCCOPC_SENSE

VSSOPC_SENSE VCCEOPIO_AE62

VCCEOPIO_AG62 VCCEOPIO_SENSE

VSSEOPIO_SENSE

SKYLAKE-U_BGA1356

@

1

CC1262

2

1U_0201_6.3V6-M

U23E@

CC1263

1U_0201_6.3V6-M

?

SKL_ULT

CPU POWER 1 OF 4

+VCCEOPIO

1

2

U23E@

1 OF 20 REV = 1

CC1266

VCC_G32 VCC_G33 VCC_G35 VCC_G37 VCC_G38 VCC_G40 VCC_G42

VCC_J30 VCC_J33 VCC_J37

VCC_J40 VCC_K33 VCC_K35 VCC_K37 VCC_K38 VCC_K40 VCC_K42 VCC_K43

VCC_SENSE

VSS_SENSE

VIDALERT#

VIDSCK

VIDSOUT

VCCSTG_G20

1

CC1267

2

10U_0402_6.3V6-M

U23E@

?

G32 G33 G35 G37 G38 G40 G42 J30 J33 J37 J40 K33 K35 K37 K38 K40 K42 K43

VCORE_VCC_SEN

E32

VCORE_VSS_SEN

E33

CPU_SVID_ALERT#_R

B63

CPU_SVID_CLK_R

A63

CPU_SVID_DAT_R

D64 G20

+V1.8S_EDRAM

4

VCORE_VCC_SEN

VCORE_VSS_SEN VCCGT_VSS_SEN

VCORE_VCC_SEN {59} VCORE_VSS_SEN {59}

+VCCSTG

VCCOPC_SENSE

VSSOPC_SENSE

1

@

CC1268

2

1U_0402_10V6K

1 2

RC1627 100_0402_1%

U23E@

1 2

RC1628 100_0402_1%

U23E@

VCCOPC_SENSE

VSSOPC_SENSE

1 2

RC77 100_0402_1%

1 2

RC82 100_0402_1%

+VCCOPC_1.0V

1 2

RC1632 0_0402_5%

@

1 2

RC1633 0_0402_5%

@

RC1631

1 2

0_0805_5%

U23E@

3

+CPU_CORE +VCC_GT

+VCCEOPIO

VCCEOPIO_SENSE

VSSEOPIO_SENSE

VCCEOPIO_SENSE

VSSEOPIO_SENSE

VCCGT_VCC_SEN

1 2

RC1629 100_0402_1%

U23E@

1 2

RC1630 100_0402_1%

U23E@

1 2

RC83 100_0402_1%

1 2

RC98 100_0402_1%

+VCCEOPIO

VCCGT_VCC_SEN{59} VCCGT_VSS_SEN{59}

2

VCCGT_VCC_SEN VCCGT_VSS_SEN

+VCC_GT

?

SKL_ULT

UC1M

AA63 AA64 AA66 AA67 AA69 AA70 AA71 AC64 AC65 AC66 AC67 AC68 AC69 AC70 AC71

A48 A53 A58 A62 A66

J43 J45 J46 J48 J50 J52 J53 J55 J56 J58

J60 K48 K50 K52 K53 K55 K56 K58 K60

L62 L63 L64 L65 L66 L67 L68 L69 L70

L71 M62 N63 N64 N66 N67 N69

J70

J69

VCCGT_A48 VCCGT_A53 VCCGT_A58 VCCGT_A62 VCCGT_A66 VCCGT_AA63 VCCGT_AA64 VCCGT_AA66 VCCGT_AA67 VCCGT_AA69 VCCGT_AA70 VCCGT_AA71 VCCGT_AC64 VCCGT_AC65 VCCGT_AC66 VCCGT_AC67 VCCGT_AC68 VCCGT_AC69 VCCGT_AC70 VCCGT_AC71 VCCGT_J43 VCCGT_J45 VCCGT_J46 VCCGT_J48 VCCGT_J50 VCCGT_J52 VCCGT_J53 VCCGT_J55 VCCGT_J56 VCCGT_J58 VCCGT_J60 VCCGT_K48 VCCGT_K50 VCCGT_K52 VCCGT_K53 VCCGT_K55 VCCGT_K56 VCCGT_K58 VCCGT_K60 VCCGT_L62 VCCGT_L63 VCCGT_L64 VCCGT_L65 VCCGT_L66 VCCGT_L67 VCCGT_L68 VCCGT_L69 VCCGT_L70 VCCGT_L71 VCCGT_M62 VCCGT_N63 VCCGT_N64 VCCGT_N66 VCCGT_N67 VCCGT_N69

VCCGT_SENSE VSSGT_SENSE

REV = 1

@

CPU POWER 2 OF 4

SKYLAKE-U_BGA1356

VCCGTX_SENSE VSSGTX_SENSE

1 OF 20

VCCGT_N70 VCCGT_N71 VCCGT_R63 VCCGT_R64 VCCGT_R65 VCCGT_R66 VCCGT_R67 VCCGT_R68 VCCGT_R69 VCCGT_R70 VCCGT_R71

VCCGT_T62 VCCGT_U65 VCCGT_U68 VCCGT_U71 VCCGT_W63 VCCGT_W64 VCCGT_W65 VCCGT_W66 VCCGT_W67 VCCGT_W68 VCCGT_W69 VCCGT_W70 VCCGT_W71

VCCGT_Y62

VCCGTX_AK42 VCCGTX_AK43 VCCGTX_AK45 VCCGTX_AK46 VCCGTX_AK48 VCCGTX_AK50 VCCGTX_AK52 VCCGTX_AK53 VCCGTX_AK55 VCCGTX_AK56 VCCGTX_AK58 VCCGTX_AK60 VCCGTX_AK70 VCCGTX_AL43 VCCGTX_AL46 VCCGTX_AL50 VCCGTX_AL53 VCCGTX_AL56

VCCGTX_AL60 VCCGTX_AM48 VCCGTX_AM50 VCCGTX_AM52 VCCGTX_AM53 VCCGTX_AM56 VCCGTX_AM58 VCCGTX_AU58 VCCGTX_AU63

VCCGTX_BB57

VCCGTX_BB66

?

Backside Cap 8x10uF 0402, SIT update

N70 N71 R63 R64 R65 R66 R67 R68 R69 R70 R71 T62 U65 U68 U71 W63 W64 W65 W66 W67 W68 W69 W70 W71 Y62

AK42 AK43 AK45 AK46 AK48 AK50 AK52 AK53 AK55 AK56 AK58 AK60 AK70 AL43 AL46 AL50 AL53 AL56 AL60 AM48 AM50 AM52 AM53 AM56 AM58 AU58 AU63 BB57 BB66

AK62 AL61

+VCC_GT

1

+VCC_GT

VCCGTX_SENSE VSSGTX_SENSE

TC133 TC134

1 1

@ @

1

CC1122

+VCC_GT

Deciphered Date

@

2

1U_0402_6.3V6K

10U_0402_6.3V6-M

@

CC1111

+VCCST_CPU

+CPU_CORE

B B

A A

13x10uF 0402, SIT update to 0603 package

10U_0402_6.3V6-M

1

2

1

CC1098

2

1U_0402_6.3V6K

5

1

CC1080

2

1

CC1099

2

1U_0402_6.3V6K

1

CC1085

CC1086

2

10U_0402_6.3V6-M

@

+CPU_CORE

15x1uF 0201, SIT update to 0402 package

1

CC1096

2

1U_0402_6.3V6K

2

1U_0402_6.3V6K

CC1097

CC1095

1U_0402_6.3V6K

10U_0603_6.3V6M

1

CC1100

2

1U_0402_6.3V6K

1

2

1

CC1101

2

1U_0402_6.3V6K

CC1236

10U_0603_6.3V6M

1

CC1102

2

1U_0402_6.3V6K

1

2

CC1237

10U_0603_6.3V6M

1U_0402_6.3V6K

1

2

CC1104

CC1093

10U_0603_6.3V6M

1

2

1U_0402_6.3V6K

12

1

CC1092

CC1091

2

10U_0603_6.3V6M

1

CC1105

2

1

2

@

1

CC1238

CC1089

2

10U_0603_6.3V6M

VR_SVID_ALRT#{59}

VR_SVID_CLK{59}

VR_SVID_DAT{59}

1

CC1109

CC1108

2

1U_0201_6.3V6-K

@

4

12

RC131

RC1544

1 2

56_0402_5%

100_0402_1%

@

1, Alert# Route Between CLK and Data

3

SVID

@

12

RC132

100_0402_1%

RC134 0_0402_5%@

RC1545 0_0402_5%@

CC42

.1U_0402_10V6-K

1 2

RC133 220_0402_1%

1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PART Y WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PART Y WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

CPU_SVID_ALERT#_R

CPU_SVID_CLK_R

CPU_SVID_DAT_R

2014/12/11

LC Future Center Secret Data

2

1

CC1124

CC1123

2

10U_0402_6.3V6-M

@

Backside Cap 12x1uF 0201, SIT update

1

2

+VCC_GT

1

CC1269

2

10U_0402_6.3V6-M

U23E@

2015/12/11

1

CC1125

2

10U_0402_6.3V6-M

@

1

CC1114

2

1U_0402_6.3V6K

CC1126

2

10U_0402_6.3V6-M

1

CC1115

2

1U_0402_6.3V6K

1

CC1127

2

10U_0402_6.3V6-M

1

CC1116

2

1U_0402_6.3V6K

Backside Cap 8x10uF 0402

1

CC1270

2

10U_0402_6.3V6-M

U23E@

1

CC1272

CC1271

2

10U_0402_6.3V6-M

U23E@

Title

MCP (CPU PWR1)

Size Do cument Number Re v

Custom

Date: Sheet

1

CC1128

2

10U_0402_6.3V6-M

1

CC1273

2

10U_0402_6.3V6-M

U23E@

Monday, July 27, 2015

CC1129

10U_0402_6.3V6-M

1

CC1118

2

1U_0402_6.3V6K

1

CC1274

2

10U_0402_6.3V6-M

U23E@

1

CC1240

CC1119

CC1241

2

1U_0402_6.3V6K

1

CC1275

CC1276

2

10U_0402_6.3V6-M

U23E@

BMWQ1&2_UMA

1

2

12 60

0.2

of

5

+1.35V +1.35V_CPU

Need short

JC1

@

2

@

1

2

+1.35V_CPU

1

D D

+1.35V_CPU

C C

1

CC1256

CC1257

2

22U_0603_6.3V6-M

RC1497 0_0402_5%

RC104 0_0402_5%

112

JUMP_43X79

CC1170

0.1u_0201_10V6K

2A , 3x22uF, 6x10uF, 4x1uF, SIT update

1

CC1258

2

22U_0603_6.3V6-M

1 2

22U_0603_6.3V6-M

CC1168

2

1

CC1169

2

10U_0603_6.3V6M

+VDDQ_CPU_CLK

+VCCSFR_OC

1

2

10U_0402_6.3V6-M

@

1

2

1

2

1

@

CC1223

CC1222

CC1171

2

10U_0603_6.3V6M

10U_0402_6.3V6-M

+VCCIO

1

+VCCST_CPU

CC1229

CC1228

2

1U_0201_6.3V6-K

10U_0402_6.3V6-M

Reserved for VCCST/VCCSTG/VCCPLL power optimized

CC85

1U_0201_6.3V6-M

+VCCST_CPU

1

2

1

@

CC1243

CC1244

2

10U_0402_6.3V6-M

RC103 0_0402_5% RC1604 0_0402_5%

1

CC1226

CC1225

CC1224

2

1U_0201_6.3V6-K

@

+VCCSTG

1 2 1 2

@

1 2

RC105 0_0402_5%

4

+1.35V_CPU

1

CC1227

2

1U_0201_6.3V6-K

1U_0201_6.3V6-M

@

+VCCST_CPU

+VDDQ_CPU_CLK

+VCCST_CPU

+VCCSFR_OC

+VCCPLL_CPU

+VCCSTG

AU23 AU28 AU35 AU42 BB23 BB32 BB41 BB47 BB51

AM40

AL23

A18 A22

K20 K21

UC1N

VDDQ_AU23 VDDQ_AU28 VDDQ_AU35 VDDQ_AU42 VDDQ_BB23 VDDQ_BB32 VDDQ_BB41 VDDQ_BB47 VDDQ_BB51

VDDQC VCCST VCCSTG_A22 VCCPLL_OC VCCPLL_K20

VCCPLL_K21

SKL_ULT

CPU POWER 3 OF 4

?

120mA

1

2

CC87

1U_0402_10V6K

+VCCPLL_CPU

2

CC86

1U_0402_10V6K

SKYLAKE-U_BGA1356

REV = 1 @

1 OF 20

120mA

1

CC84

CC1249

2

1U_0402_10V6K

0.1U_0402_10V7K

VCCIO_AK28 VCCIO_AK30 VCCIO_AL30 VCCIO_AL42 VCCIO_AM28 VCCIO_AM30 VCCIO_AM42

VCCSA_AK23 VCCSA_AK25

VCCSA_G23 VCCSA_G25 VCCSA_G27 VCCSA_G28

VCCSA_J22 VCCSA_J23

VCCSA_J27 VCCSA_K23 VCCSA_K25 VCCSA_K27 VCCSA_K28 VCCSA_K30

VCCIO_SENSE VSSIO_SENSE

VSSSA_SENSE VCCSA_SENSE

3

AK28 AK30 AL30 AL42 AM28 AM30 AM42

AK23 AK25 G23 G25 G27 G28 J22 J23 J27 K23 K25 K27 K28 K30

AM23 AM22

H21 H20

?

VCCSA_VCC_SEN

VCCSA_VSS_SEN

+VCCIO

+VCCSA

VCCIO_SENSE VSSIO_SENSE

VCCSA_VSS_SEN VCCSA_VCC_SEN

1

TC136

1

1 2

RC101 100_0402_1%

1 2

RC102 100_0402_1%

@ @

TC137

VCCSA_VSS_SEN {59} VCCSA_VCC_SEN {59}

+VCCSA

2

+VCCIO

3.1A 2x10uF, 4x1uF

1

2

+VCCSA

1

CC1152

2

10U_0402_6.3V6-M

1

CC1158

CC1159

CC1153

2

1U_0201_6.3V6-K

10U_0402_6.3V6-M

@

1U_0201_6.3V6-K

@

4.5A 10x10uF, 7x1uF, SIT update

1

2

CC1132

10U_0603_6.3V6M

1

CC1133

2

10U_0603_6.3V6M

@

1

CC1134

CC1135

2

10U_0402_6.3V6-M

@

1

2

1

2

1

2

1

CC1160

2

1U_0201_6.3V6-K

@

1

CC1136

2

10U_0603_6.3V6M

1

CC1218

CC1161

2

1U_0402_10V6K

1U_0201_6.3V6-K

1

CC1137

2

10U_0603_6.3V6M

+1.0VALW +VCCST_CPU

RC1605 0_0402_5%

1

CC1230

2

1U_0402_10V6K

1

CC1251

2

10U_0603_6.3V6M

@

1 2

1

CC1231

2

1U_0402_10V6K

1

CC1252

2

10U_0402_6.3V6-M

@

CC1232

@

1U_0402_10V6K

CC1253

10U_0402_6.3V6-M

1

2

CC1139

1U_0402_6.3V6K

Reserved for VCCST/VCCSTG/VCCPLL power optimized

1

2

1

CC1140

2

1U_0402_6.3V6K

1

CC1142

2

1U_0402_6.3V6K

1

CC1145

2

1U_0402_6.3V6K

1

CC1144

CC1143

CC1141

2

1U_0201_6.3V6-M

+1.0VALW +VCCST_CPU

DC3

2 1

@

2 1 5

2

CC1245

0.01U_0402_25V7K

1

@

UC7

VIN EN GATE

M5938CTB1U_SOT23-6

@

RC1591

1 2

40.2K_0402_1%

VCCIO_EN

DC2

2 1

SDM10U45LP-7_DFN1006-2-2

@

+1.0VALW +VCCIO_R

UC8

VOUT

VIN

VBIAS

EN

GND

GATE

M5938CTB1U_SOT23-6

@

6 3 4

2 1 5

2

CC1247

0.01U_0402_25V7K

1

@

need to open

JC2

@

2

112

JUMP_43X79

1

2

@

+VCCIO

CC1248

1U_0402_10V6K

+5VALW

RC1590

1 2

40.2K_0402_1%

EC_VCCST_EN

SDM10U45LP-7_DFN1006-2-2

@

Reserved for +VCCIO switch

B B

@

+3VALW

RC128 47K_0402_5%

@

RC1575

47K_0402_5%

1 2

EC_VCCIO_EN{44}

A A

PM_SLP_S3#{11,44}

RC1577 0_0402_5%@

1 2

DC1

RB751V-40_SOD323-2

5

@

VCCIO_EN

+20VSB

RC1621 100K_0402_5%

VCCIO_EN#

1 2

5

G

34

D

S

CC72

1

CC71

2

22U_0603_6.3V6-M

12

61

D

2

G

2N7002KDWH_SOT363-6

S

QC12B 2N7002KDWH_SOT363-6

4

10U_0603_6.3V6M

QC12A

AON7408L_DFN8-5 QC11

5

D

4

1

2

S1 S2 S3

G

1 2 3

CC77

0.01U_0402_25V7K

+VCCIO+1.0VALW

12

RC125 470K_0402_5%

CC1250

1

2

1

C1102

2

10U_0603_6.3V6M

@

22U_0603_6.3V6-M

VCCIO_EN#

CC79

1

RC142

61

D

S

2015/12/11

2

10U_0603_6.3V6M

QC16A

2N7002KDWH_SOT363-6

12

RC124 470_0603_5%

@

13

D

2

QC13

G

2N7002KW_SOT323-3

S

@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PART Y WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PART Y WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PART Y WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

EC_VCCST_EN{44}

+3VALW

2014/12/11

RC141

+20VSB

1 2

100K_0402_5%

VCCST_EN#

1 2

47K_0402_5%

34

5

G

Deciphered Date

2

D

QC16B 2N7002KDWH_SOT363-6

S

EC_VCCST_EN

LC Future Center Secret Data

2

G

+VCCST_CPU_R

VOUT

VBIAS

6 3 4

GND

@

1 2

RC1592 0_0402_5%

+5VALW

1

CC1246

2

1U_0402_10V6K

@

Reserved for +VCCST_CPU switch

1

2

G

CC81

0.01U_0402_25V7K

3

+VCCST_CPU+1.0VALW

10U_0603_6.3V6M

RC1584

1 2

1

@

CC80

2

VCCST_EN#

100K_0402_5%

12

13

D

2

G

S

QC19 AO3402_SOT-23-3

D1S

2

+VCCST_CPU switch

Title

MCP (CPU PWR2)

Size Do cument Number Re v

Custom

Monday, July 27, 2015

Date: Sheet

1

BMWQ1

RC135 470_0603_5%

@

QC14 2N7002KW_SOT323-3

@

of

13 60

0.2

5

1 2

RC1503 0_0603_5%@

+1.0VALW +VCCAMPHY

D D

+1.0VALW +VCCAPLL_1P0

1 2

EMC@

RC1504BLM15GG471SN1D

+3VS

+3VALW_PCH

4

@

1 2

RC1585 0_0402_5%

1 2

RC1586 BLM15GG471SN1D

EMC@

+VCCHDA

3

1 2

RC1622 0_0402_5%@

+3VALW_PCH

+VCCPGPPG_SDIO

1 2

RC1623 0_0402_5%

@

+VCCPGPPG

2

1

+VCCHDA

1

2

VCCMPHYON_1P0_L1

+VCCDSW_1P0

PCH Internal VRM

1

2

CC171

1U_0402_10V6K

+1.0VALW

CC165

.1U_0402_10V6-K

75mA

+1.0VALW

1

2

1

2

CC145

1U_0402_10V6K

+3VALW

68mA

+3VALW_PCH

CC144

1U_0402_10V6K

+1.0VALW

2.574A22mA

22U_0603_6.3V6-M

@

0.118A

1

CC158

2

Near AF18

11mA

+1.0VALW

0.696A

Near AB19

1

2

CC153

1U_0402_10V6K

VCCMPHYON_1P0_L1

33mA

@

1

CC141

2

1U_0402_10V6K

1

CC169

2

Near A18

AB19

VCCPRIM_1P0_AB19

AB20

VCCPRIM_1P0_AB20

P18

VCCPRIM_1P0_P18

AF18

VCCPRIM_CORE_AF18

AF19

VCCPRIM_CORE_AF19

V20

VCCPRIM_CORE_V20

V21

VCCPRIM_CORE_V21

AL1

DCPDSW_1P0

K17

VCCMPHYAON_1P0_K17

L1

VCCMPHYAON_1P0_L1

N15

VCCMPHYGT_1P0_N15

N16

VCCMPHYGT_1P0_N16

N17

VCCMPHYGT_1P0_N17

P15

VCCMPHYGT_1P0_P15

P16

VCCMPHYGT_1P0_P16

K15

VCCAMPHYPLL_1P0_K15

L15

VCCAMPHYPLL_1P0_L15

V15

VCCAPLL_1P0

AB17

VCCPRIM_1P0_AB17

Y18

VCCPRIM_1P0_Y18

AD17

VCCDSW_3P3_AD17

AD18

VCCDSW_3P3_AD18

AJ17

VCCDSW_3P3_AJ17

AJ19

VCCHDA

AJ16

VCCSPI

AF20

VCCSRAM_1P0_AF20

AF21

VCCSRAM_1P0_AF21

T19

VCCSRAM_1P0_T19

T20

VCCSRAM_1P0_T20

AJ21

VCCPRIM_3P3_AJ21

AK20

VCCPRIM_1P0_AK20

N18

VCCAPLLEBB

REV = 1

@

1U_0402_10V6K

SKL_ULT

UC1O

CPU POWER 4 OF 4

SKYLAKE-U_BGA1356

?

1 OF 20

VCCPGPPA VCCPGPPB VCCPGPPC VCCPGPPD VCCPGPPE VCCPGPPF

VCCPGPPG

VCCPRIM_3P3_V19

VCCPRIM_1P0_T1

VCCATS_1P8

VCCRTCPRIM_3P3

VCCRTC_AK19 VCCRTC_BB14

DCPRTC VCCCLK1 VCCCLK2 VCCCLK3 VCCCLK4 VCCCLK5 VCCCLK6

GPP_B0/CORE_VID0 GPP_B1/CORE_VID1

+3VALW_PCH

@

1

CC164

CC156

2

1U_0402_10V6K

20mA

AK15

4mA

AG15

6mA

Y16

8mA

Y15

6mA

T16

161mA

AF16

61mA

AD15 V19 T1

6mA

AA1

1mA

AK17 AK19

BB14 BB10

VCCRTCEXT

35mA

A14

29mA

K19

24mA

L21

33mA

N20

4mA

L19

10mA

A10 AN11

AN13

?

1U_0402_10V6K

+1.8VALW

+1.0VALW

1mA

+1.0VALW

+1.0VALW +VCCCLK4 +VCCCLK5

1

TC179 PAD@

1

TC180 PAD@

1

CC172

2

1U_0402_10V6K

Near Y15

@

1

CC173

2

1U_0402_10V6K

CC174

1U_0402_10V6K

@

+VCCPGPPG

+1.0VALW

1

CC57

2

1U_0402_10V6K

1

C1099

2

1

C1100

2

@

1

CC175

2

1U_0402_10V6K

1 2

22U_0603_6.3V6-M

1 2

22U_0603_6.3V6-M

1

CC56

2

RC15880_0603_5%

RC15890_0603_5%

@

1

CC176

2

1U_0402_10V6K

1 2

@

1

1U_0402_10V6K

2

+1.0VALW+VCCCLK4

+1.0VALW+VCCCLK5

+3VALW_PCH

C1098

22U_0603_6.3V6-M

RC15870_0603_5%

1

CC142

2

+1.8VALW

1U_0402_10V6K

+1.0VALW

1

CC149

2

.1U_0402_10V6-K

1

CC55

2

0.1U_0402_10V7K

1

2

1

CC146

2

.1U_0402_10V6-K

+3VALW_PCH

CC143

1U_0402_10V6K

1

CC1242

2

1U_0402_10V6K

VCCRTC

1 2

+1.0VALW

1

@

2

CC159

1U_0402_10V6K

1.5A

CC148

Near AF20

RC1620 0_0402_5%

@

1

CC147

2

47U_0805_4V6-M

1U_0201_6.3V6-M

0.642A

+3VALW_PCH

+1.0VALW

C C

+1.0VALW

Near N15

+VCCAMPHY

+VCCAPLL_1P0

+1.0VALW

B B

@

1

2

1

C1096

2

22U_0603_6.3V6-M

C1097

.1U_0402_10V6-K

88mA

1

CC151

2

1

CC154

2

Near K15

1U_0402_10V6K

22mA

+1.0VALW

1U_0402_10V6K

1

2

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2014/12/11

LC Future Center Secret Data

Deciphered Date

2

2015/12/11

Title

MCP (PCH PWR)

Size

Document Number Rev

Custom

Monday, July 27, 2015

Date: Sheet

BMWQ1&2_UMA

1

14 60

0.2

of

5

?

SKL_ULT

UC1P

GND 1 OF 3

A5

VSS_A5

A67

VSS_A67

A70

D D

C C

B B

AA65 AA68 AB15 AB16 AB18 AB21

AD13 AD16 AD19 AD20 AD21 AD62

AE64 AE65 AE66 AE67 AE68 AE69

AF10 AF15 AF17

AF63 AG16 AG17 AG18 AG19 AG20 AG21 AG71 AH13

AH63 AH64 AH67

AJ15 AJ18 AJ20

AK11 AK16 AK18 AK21 AK22 AK27 AK63 AK68 AK69

AL28 AL32 AL35 AL38

AL45 AL48 AL52 AL55 AL58 AL64

VSS_A70

AA2

VSS_AA2

AA4

VSS_AA4 VSS_AA65 VSS_AA68 VSS_AB15 VSS_AB16 VSS_AB18 VSS_AB21

AB8

VSS_AB8 VSS_AD13 VSS_AD16 VSS_AD19 VSS_AD20 VSS_AD21 VSS_AD62

AD8

VSS_AD8 VSS_AE64 VSS_AE65 VSS_AE66 VSS_AE67 VSS_AE68 VSS_AE69

AF1

VSS_AF1 VSS_AF10 VSS_AF15 VSS_AF17

AF2

VSS_AF2

AF4

VSS_AF4 VSS_AF63 VSS_AG16 VSS_AG17 VSS_AG18 VSS_AG19 VSS_AG20 VSS_AG21 VSS_AG71 VSS_AH13

AH6

VSS_AH6 VSS_AH63 VSS_AH64 VSS_AH67 VSS_AJ15 VSS_AJ18 VSS_AJ20

AJ4

VSS_AJ4 VSS_AK11 VSS_AK16 VSS_AK18 VSS_AK21 VSS_AK22 VSS_AK27 VSS_AK63 VSS_AK68 VSS_AK69

AK8

VSS_AK8

AL2

VSS_AL2 VSS_AL28 VSS_AL32 VSS_AL35 VSS_AL38

AL4

VSS_AL4 VSS_AL45 VSS_AL48 VSS_AL52 VSS_AL55 VSS_AL58 VSS_AL64

REV = 1

@

1 OF 20

SKYLAKE-U_BGA1356

VSS_AL65

VSS_AL66 VSS_AM13 VSS_AM21 VSS_AM25 VSS_AM27 VSS_AM43 VSS_AM45 VSS_AM46 VSS_AM55 VSS_AM60 VSS_AM61 VSS_AM68 VSS_AM71

VSS_AM8 VSS_AN20 VSS_AN23 VSS_AN28 VSS_AN30 VSS_AN32 VSS_AN33 VSS_AN35 VSS_AN37 VSS_AN38 VSS_AN40 VSS_AN42 VSS_AN58 VSS_AN63 VSS_AP10 VSS_AP18 VSS_AP20 VSS_AP23 VSS_AP28 VSS_AP32 VSS_AP35 VSS_AP38 VSS_AP42 VSS_AP58 VSS_AP63 VSS_AP68 VSS_AP70 VSS_AR11 VSS_AR15 VSS_AR16 VSS_AR20 VSS_AR23 VSS_AR28 VSS_AR35 VSS_AR42 VSS_AR43 VSS_AR45 VSS_AR46 VSS_AR48

VSS_AR5 VSS_AR50 VSS_AR52 VSS_AR53 VSS_AR55 VSS_AR58 VSS_AR63

VSS_AR8

VSS_AT2 VSS_AT20 VSS_AT23 VSS_AT28 VSS_AT35

VSS_AT4 VSS_AT42 VSS_AT56 VSS_AT58

4

AL65 AL66 AM13 AM21 AM25 AM27 AM43 AM45 AM46 AM55 AM60 AM61 AM68 AM71 AM8 AN20 AN23 AN28 AN30 AN32 AN33 AN35 AN37 AN38 AN40 AN42 AN58 AN63 AP10 AP18 AP20 AP23 AP28 AP32 AP35 AP38 AP42 AP58 AP63 AP68 AP70 AR11 AR15 AR16 AR20 AR23 AR28 AR35 AR42 AR43 AR45 AR46 AR48 AR5 AR50 AR52 AR53 AR55 AR58 AR63 AR8 AT2 AT20 AT23 AT28 AT35 AT4 AT42 AT56 AT58

?

AT63 AT68 AT71 AU10 AU15 AU20 AU32 AU38

AV68 AV69 AV70

AV71 AW10 AW12 AW14 AW16 AW18 AW21 AW23 AW26 AW28 AW30 AW32 AW34 AW36 AW38 AW41 AW43 AW45 AW47 AW49 AW51 AW53 AW55 AW57

AW6 AW60 AW62 AW64 AW66

AW8

AY66

BA10 BA14 BA18

BA23 BA28 BA32 BA36

BA45

AV1

B10 B14 B18 B22 B30 B34 B39 B44 B48 B53 B58 B62 B66 B71

BA1

BA2

F68

@

3

?

SKL_ULT

UC1Q

GND 2 OF 3

VSS_AT63 VSS_AT68 VSS_AT71 VSS_AU10 VSS_AU15 VSS_AU20 VSS_AU32 VSS_AU38 VSS_AV1 VSS_AV68 VSS_AV69 VSS_AV70 VSS_AV71 VSS_AW10 VSS_AW12 VSS_AW14 VSS_AW16 VSS_AW18 VSS_AW21 VSS_AW23 VSS_AW26 VSS_AW28 VSS_AW30 VSS_AW32 VSS_AW34 VSS_AW36 VSS_AW38 VSS_AW41 VSS_AW43 VSS_AW45 VSS_AW47 VSS_AW49 VSS_AW51 VSS_AW53 VSS_AW55 VSS_AW57 VSS_AW6 VSS_AW60 VSS_AW62 VSS_AW64 VSS_AW66 VSS_AW8 VSS_AY66 VSS_B10 VSS_B14 VSS_B18 VSS_B22 VSS_B30 VSS_B34 VSS_B39 VSS_B44 VSS_B48 VSS_B53 VSS_B58 VSS_B62 VSS_B66 VSS_B71 VSS_BA1 VSS_BA10 VSS_BA14 VSS_BA18 VSS_BA2 VSS_BA23 VSS_BA28 VSS_BA32 VSS_BA36 VSS_F68 VSS_BA45

1 OF 20

SKYLAKE-U_BGA1356

REV = 1

VSS_BA49 VSS_BA53 VSS_BA57

VSS_BA6 VSS_BA62 VSS_BA66 VSS_BA71 VSS_BB18 VSS_BB26 VSS_BB30 VSS_BB34 VSS_BB38 VSS_BB43 VSS_BB55

VSS_BB6 VSS_BB60 VSS_BB64 VSS_BB67 VSS_BB70

VSS_C1

VSS_C25

VSS_C5 VSS_D10 VSS_D11 VSS_D14 VSS_D18 VSS_D22 VSS_D25 VSS_D26 VSS_D30 VSS_D34 VSS_D39 VSS_D44 VSS_D45 VSS_D47 VSS_D48 VSS_D53 VSS_D58

VSS_D6 VSS_D62 VSS_D66 VSS_D69

VSS_E11 VSS_E15 VSS_E18 VSS_E21 VSS_E46 VSS_E50 VSS_E53 VSS_E56

VSS_E6

VSS_E65 VSS_E71

VSS_F1

VSS_F13

VSS_F2

VSS_F22 VSS_F23 VSS_F27 VSS_F28 VSS_F32 VSS_F33 VSS_F35 VSS_F37 VSS_F38

VSS_F4

VSS_F40 VSS_F42

VSS_BA41

2

?

SKL_ULT

BA49 BA53 BA57 BA6 BA62 BA66 BA71 BB18 BB26 BB30 BB34 BB38 BB43 BB55 BB6 BB60 BB64 BB67 BB70 C1 C25 C5 D10 D11 D14 D18 D22 D25 D26 D30 D34 D39 D44 D45 D47 D48 D53 D58 D6 D62 D66 D69 E11 E15 E18 E21 E46 E50 E53 E56 E6 E65 E71 F1 F13 F2 F22 F23 F27 F28 F32 F33 F35 F37 F38 F4 F40 F42 BA41

?

UC1R

F8

VSS_F8

G10

VSS_G10

G22

VSS_G22

G43

VSS_G43

G45

VSS_G45

G48

VSS_G48

G5

VSS_G5

G52

VSS_G52

G55

VSS_G55

G58

VSS_G58

G6

VSS_G6

G60

VSS_G60

G63

VSS_G63

G66

VSS_G66

H15

VSS_H15

H18

VSS_H18

H71

VSS_H71

J11

VSS_J11

J13

VSS_J13

J25

VSS_J25

J28

VSS_J28

J32

VSS_J32

J35

VSS_J35

J38

VSS_J38

J42

VSS_J42

J8

VSS_J8

K16

VSS_K16

K18

VSS_K18

K22

VSS_K22

K61

VSS_K61

K63

VSS_K63

K64

VSS_K64

K65

VSS_K65

K66

VSS_K66

K67

VSS_K67

K68

VSS_K68

K70

VSS_K70

K71

VSS_K71

L11

VSS_L11

L16

VSS_L16

L17

VSS_L17

SKYLAKE-U_BGA1356

REV = 1

@

GND 3 OF 3

1 OF 20

VSS_L18

VSS_L2

VSS_L20

VSS_L4

VSS_L8 VSS_N10 VSS_N13 VSS_N19 VSS_N21

VSS_N6 VSS_N65 VSS_N68 VSS_P17 VSS_P19 VSS_P20 VSS_P21 VSS_R13

VSS_R6 VSS_T15 VSS_T17 VSS_T18

VSS_T2 VSS_T21

VSS_T4 VSS_U10 VSS_U63 VSS_U64 VSS_U66 VSS_U67 VSS_U69 VSS_U70 VSS_V16 VSS_V17 VSS_V18

VSS_W13

VSS_W6

VSS_W9 VSS_Y17 VSS_Y19 VSS_Y20 VSS_Y21

L18 L2 L20 L4 L8 N10 N13 N19 N21 N6 N65 N68 P17 P19 P20 P21 R13 R6 T15 T17 T18 T2 T21 T4 U10 U63 U64 U66 U67 U69 U70 V16 V17 V18 W13 W6 W9 Y17 Y19 Y20 Y21

?

1

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND C ONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF LC FUTUR E CENTER .

MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF LC FUTUR E CENTER .

5

4

MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF LC FUTUR E CENTER .

3

2014/12/11

LC Future Center Secret Data

Deciphered Date

2

2015/12/11

Title

MCP (VSS)

Size

Document Number Re v

Custom

Monday, July 27, 2015

Date: Sheet

Monday, July 27, 2015

BMWQ1&2_UMA

1

15 60

0.2

of

5

D D

RC1618 1K_0402_5%

1 2

@

C C

B B

Pin Name Strap Description Configuration

A A

CFG[4] Display Port

Presence strap

5

CPU_CFG0

CPU_CFG4

RC106 1K_0402_5%

1 2

CFG_RCOMP

RC162

49.9_0402_1%

1 2

— 1 = eDP Disabled — 0 = eDP Enabled

*

TC142PAD@ TC143PAD@ TC144PAD@

TC146PAD@ TC147PAD@ TC148PAD@ TC153PAD@

TC151PAD@ TC152PAD@

TC154PAD@ TC156PAD@ TC159PAD@

TC158PAD@ TC161PAD@

TC160PAD@

TC166PAD@ TC201PAD@

TC195PAD@ TC186PAD@

TC189PAD@ TC191PAD@

TC171PAD@ TC172PAD@

TC169PAD@ TC170PAD@

Default Value

1

CPU_CFG1

1

CPU_CFG2

1

XDP_CPU_CFG3

1

CPU_CFG5

1

CPU_CFG6

1

CPU_CFG7

1

CPU_CFG8

1

CPU_CFG9 CPU_CFG10

1

CPU_CFG11

1

CPU_CFG12 CPU_CFG13

1

CPU_CFG14 CPU_CFG15

1

CPU_CFG16

1

CPU_CFG17

1

CPU_CFG18

1

CPU_CFG19

1

XDP_ITP_PMODE

1 1

4

E68

B67 D65 D67

E70 C68 D68 C67

F71 G69

F70 G68 H70 G71 H69 G70

E63

F63

E66

F66

E60

E8

AY2 AY1

D1 D3

K46

K45

AL25 AL27

C71

B70

F60

A52

BA70 BA68

J71 J68

F65 G65

F61

E61

4

UC1S

RESERVED SIGNALS-1

CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15]

CFG[16] CFG[17]

CFG[18] CFG[19]

CFG_RCOMP ITP_PMODE RSVD_AY2

RSVD_AY1 RSVD_D1

RSVD_D3 RSVD_K46

RSVD_K45 RSVD_AL25

RSVD_AL27 RSVD_C71

RSVD_B70 RSVD_F60 RSVD_A52 RSVD_TP_BA70

RSVD_TP_BA68 RSVD_J71

RSVD_J68 VSS_F65

VSS_G65 RSVD_F61

RSVD_E61

SKYLAKE-U_BGA1356

REV = 1

@

SKL_ULT

?

1 OF 20

3

RSVD_TP_BB68 RSVD_TP_BB69

RSVD_TP_AK13 RSVD_TP_AK12

RSVD_TP_AW71 RSVD_TP_AW70

PROC_SELECT#

BB68 BB69

AK13 AK12

BB2

RSVD_BB2

BA3

RSVD_BA3

AU5

TP5

AT5

TP6

D5

RSVD_D5

D4

RSVD_D4

B2

RSVD_B2

C2

RSVD_C2

B3

RSVD_B3

A3

RSVD_A3

AW1

RSVD_AW1

E1

RSVD_E1

E2

RSVD_E2

BA4

RSVD_BA4

BB4

RSVD_BB4

A4

RSVD_A4

C4

RSVD_C4

BB5

TP4

A69

RSVD_A69

B69

RSVD_B69

AY3

RSVD_AY3

D71

RSVD_D71

C70

RSVD_C70

C54

RSVD_C54

D54

RSVD_D54

AY4

TP1

BB3

TP2

AY71

VSS_AY71

AR56

ZVM#

AW71 AW70

AP56

MSM#

C64

?

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF T HE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF T HE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF T HE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC F UTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC F UTURE CENTER.

3

RSVD_AY3

VSS_AY71 ZVM#

PROC_SELECT#

2014/12/11

1

TC173 PAD@

1

TC174 PAD@

1

TC175 PAD@

1

TC176 PAD@

1

TC196 PAD@

1

TC200 PAD@

1

TC183 PAD@

1

TC185 PAD@

1

TC184 PAD@

1

TC181 PAD@

1

TC194 PAD@

1

TC187 PAD@

1

TC198 PAD@

1

TC182 PAD@

1

TC199 PAD@

1

TC188 PAD@

1

TC193 PAD@

need to check with Intel

1

TC190 PAD@

1

TC192 PAD@

1

TC197 PAD@

need to check with Intel

ZVM# {57}

1

TC177 PAD@

1

TC178 PAD@

1

TC168 PAD@

1 2

R22 100K_0402_5%

Cannonlake@

LC Future Center Secret Data

Deciphered Date

+1.8VALW

2

Cannonlake@

RC1582 0_0402_5% RC1583 0_0402_5%

Cannonlake@

+VCCST_CPU

2

12 12

2015/12/11

1 2

RSVD_U12 RSVD_U11

RC107 0_0402_5%

RC108 0_0402_5%

1

?

SKL_ULT

UC1T

AW69 AW68

AU56

AW48

C7 U12 U11 H11

Title

Size

Custom

Date: Sheet

SPARE

RSVD_AW69 RSVD_AW68 RSVD_AU56 RSVD_AW48 RSVD_C7 RSVD_U12 RSVD_U11 RSVD_H11

SKYLAKE-U_BGA1356

REV = 1 @

MCP (CFG,RESERVED)

Document Number Re v

1 OF 20

Monday, July 27, 2015

F6

RSVD_F6

E3

RSVD_E3

C11

RSVD_C11

B11

RSVD_B11

A11

RSVD_A11

D12

RSVD_D12

C12

RSVD_C12

RSVD_F52

BMWQ1&2_UMA

RSVD_F52

F52

?

1

+VCCST_CPU

12

RC1619 150_0402_5%

@

of

16 60

0.2

5

DDR_SA_VREFDQ {5}

+1.35V

12

RD5

RD6

1 2

D D

C C

B B

A A

2_0402_5%

0.022U_0402_16V7-K

CD3

1

2

12

RD8

24.9_0402_1%

1.82K_0402_1%

+VREF_DQ_DIMMA

1.82K_0402_1%

12

RD7

CD4

CD@

DDRA_CKE0{5}

DDRA_BS2#{5}

DDRA_CLK0{5} DDRA_CLK0#{5}

DDRA_BS0#{5} DDRA_WE#{5}

DDRA_CAS#{5}

DDRA_CS1#{5}

+3VS

CD28

2.2U_0603_6.3V6K

@

.1U_0402_10V6-K

2.2U_0603_6.3V6K

1

CD2

2

1

CD29 .1U_0402_10V6-K

2

5

DDRA_DQ5

1

2

DDRA_DQ7 DDRA_DQ12 DDRA_DQ13

DDRA_DQ9 DDRA_DQS#1

DDRA_DQS1 DDRA_DQ14 DDRA_DQ11

DDRA_DQ10 DDRA_DQ20

DDRA_DQ21 DDRA_DQS#2

DDRA_DQS2 DDRA_DQ18

DDRA_DQ23 DDRA_DQ29

DDRA_DQ25

DDRA_DQ26 DDRA_DQ30

DDRA_CKE0

DDRA_BS2# DDRA_MA12

DDRA_MA9 DDRA_MA8

DDRA_MA5 DDRA_MA3

DDRA_MA1 DDRA_CLK0

DDRA_CLK0# DDRA_MA10

DDRA_BS0# DDRA_WE#

DDRA_CAS# DDRA_MA13

DDRA_CS1#

DDRA_DQ33 DDRA_DQ37 DDRA_DQ36 DDRA_DQ32

DDRA_DQS#4 DDRA_DQS4

DDRA_DQ39 DDRA_DQ38

DDRA_DQ44 DDRA_DQ41

DDRA_DQ47 DDRA_DQ42 DDRA_DQ48

DDRA_DQ53 DDRA_DQS#6

DDRA_DQS6 DDRA_DQ55

DDRA_DQ54 DDRA_DQ61 DDRA_DQ57

DDRA_DQ60

DDRA_DQ59 DDRA_DQ63 DDRA_DQ58

1 2

RD13

12

@

0_0402_5% RD14

DDR3 SO-DIMM A

3A@1.5V

JDDR1

1

VREF_DQ

3

VSS_1

5

DQ0

7

DQ1

9

VSS_3

11

DM0

13

VSS_5

15

DQ2

17

DQ3

19

VSS_7

21

DQ8

23

DQ9

25

VSS_9

27

DQS1#

29

DQS1

31

VSS_11

33

DQ10

35

DQ11

37

VSS_13

39

DQ16

41

DQ17

43

VSS_15

45

DQS2#

47

DQS2

49

VSS_17

51

DQ18

53

DQ19

55

VSS_19

57

DQ24

59

DQ25

61

VSS_21

63

DM3

65

VSS_23

67

DQ26

69

DQ27

71

VSS_25

73

CKE0

75

VDD_1

77

NC_1

79

BA2

81

VDD_3

83

A12/BC#

85

A9

87

VDD_5

89

A8

91

A5

93

VDD_7

95

A3

97

A1

99

VDD_9

101

CK0

103

CK0#

105

VDD_11

107

A10/AP

109

BA0

111

VDD_13

113

WE#

115

CAS#

117

VDD_15

119

A13

121

S1#

123

VDD_17

125

TEST

127

VSS_27

129

DQ32

131

DQ33

133

VSS_29

135

DQS4#

137

DQS4

139

VSS_31

141

DQ34

143

DQ35

145

VSS_33

147

DQ40

149

DQ41

151

VSS_36

153

DM5

155

VSS_37

157

DQ42

159

DQ43

161

VSS_39

163

DQ48

165

DQ49

167

VSS_41

169

DQS6#

171

DQS6

173

VSS_43

175

DQ50

177

DQ51

179

VSS_45

181

DQ56

183

DQ57

185

VSS_47

187

DM7

189

VSS_49

191

DQ58

193

DQ59

195

VSS_51

197

0_0402_5%@

SA0

199

VDDSPD

201

SA1

203

VTT_1

205

GND1

207

BOSS1

LCN_DAN06-K4406-0103

ME@

4

VSS_2

DQ4 DQ5

VSS_4

DQS0#

DQS0

VSS_6

DQ6 DQ7

VSS_8

DQ12 DQ13

VSS_10

DM1

RESET#

VSS_12

DQ14 DQ15

VSS_14

DQ20 DQ21

VSS_16

DM2

VSS_18

DQ22 DQ23

VSS_20

DQ28 DQ29

VSS_22

DQS3#

DQS3

VSS_24

DQ30 DQ31

VSS_26

CKE1

VDD_2

VDD_4

VDD_6

VDD_8

VDD_10

CK1#

VDD_12

RAS#

VDD_14

ODT0

VDD_16

ODT1

NC_2

VDD_18

VREF_CA

VSS_28

DQ36 DQ37

VSS_30

DM4

VSS_32

DQ38 DQ39

VSS_34

DQ44 DQ45

VSS_35

DQS5#

DQS5

VSS_38

DQ46 DQ47

VSS_40

DQ52 DQ53

VSS_42

DM6

VSS_44

DQ54 DQ55

VSS_46

DQ60 DQ61

VSS_48

DQS7#

DQS7

VSS_50

DQ62 DQ63

VSS_52

EVENT#

SDA

VTT_2

GND2

BOSS2

4

3

DDRA_DQ[0..63] {5} DDRA_DQS[0..7] {5}

+1.35V+1.35V

For RF

+0.675VS

0.65A@0.75V

For RF

1

CD5

2

47P_0402_50V8J

.1U_0402_10V6-K

@

CD70

DDRA_CKE1 {5}

DDRA_CLK1 {5} DDRA_CLK1# {5}

DDRA_BS1# {5} DDRA_RAS# {5}

DDRA_CS0# {5} DDRA_ODT0 {5}

DDRA_ODT1 {5}

.1U_0402_10V6-K

CD22

1

2

SMB_DATA_S3 {7,18,40} SMB_CLK_S3 {7,18,40}

2

DDRA_DQ0

4

DDRA_DQ4DDRA_DQ1

6 8

DDRA_DQS#0

10

DDRA_DQS0

12 14

DDRA_DQ2DDRA_DQ6

16

DDRA_DQ3

18 20 22

DDRA_DQ8

24 26 28

CPU_DRAMRST#

30 32 34

DDRA_DQ15

36 38

DDRA_DQ17

40

DDRA_DQ16

42 44 46 48

DDRA_DQ22

50

DDRA_DQ19

52 54

DDRA_DQ24

56

DDRA_DQ28

58 60

DDRA_DQS#3

62

DDRA_DQS3

64 66

DDRA_DQ31

68

DDRA_DQ27

70 72

DDRA_CKE1

74 76

DDRA_MA15

78

A15 A14

A11

A7 A6

A4 A2

A0

CK1

BA1

S0#

SCL

80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206 208

DDRA_MA14 DDRA_MA11

DDRA_MA7 DDRA_MA6

DDRA_MA4 DDRA_MA2

DDRA_MA0 DDRA_CLK1

DDRA_CLK1# DDRA_BS1#

DDRA_RAS# DDRA_CS0#

DDRA_ODT0 DDRA_ODT1

+VREF_CA_DIMMA

DDRA_DQ34 DDRA_DQ35

DDRA_DQ45 DDRA_DQ40

DDRA_DQS#5 DDRA_DQS5

DDRA_DQ43DDRA_DQ46

DDRA_DQ52 DDRA_DQ49

DDRA_DQ51 DDRA_DQ50

DDRA_DQ56

DDRA_DQS#7 DDRA_DQS7

DDRA_DQ62

SMB_DATA_S3 SMB_CLK_S3

1

CD68

2

47P_0402_50V8J

DDRA_DQS#[0..7] {5} DDRA_MA[0..15] {5}

1

2

1

2

RD22 0_0402_5%@

CD23

2.2U_0603_6.3V6K

Layout Note: Place near DIMM

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND C ONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF LC FUTUR E CENTER .

MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF LC FUTUR E CENTER .

CD7

CD6

2

47P_0402_50V8J

Layout Note: Place near DIMM

+1.35V

CD8

10U_0603_6.3V6M

1

2

CD@

CD16

1U_0402_6.3V6K

1

2

1 2

+0.675VS

CD25

CD24

.1U_0402_10V6-K

Issued Date

1

2

CD@

3

CPU_DRAMRST# {6,18}

CD9

10U_0603_6.3V6M

1

2

CD17

1

2

CD10

1

2

CD18

1U_0402_6.3V6K

1

2

+VREF_CA

CD11

10U_0603_6.3V6M

1

2

1U_0402_6.3V6K

CD@

(10U_0603_6.3V)*2 (.1U_0402_10V)*4

CD26

1

2

CD27

.1U_0402_10V6-K

1

2

CD@

2014/12/11

.1U_0402_10V6-K

(10uF_0603_6.3V)*8 (1U_0402_6.3V)*8

CD12

CD13

10U_0603_6.3V6M

1

2

CD57

1U_0402_6.3V6K

1

2

CD65

1

2

CD@

Deciphered Date

10U_0603_6.3V6M

1

2

CD19

CD56

1U_0402_6.3V6K

1

2

CD@

CD64

10U_0603_6.3V6M

1

2

LC Future Center Secret Data

2

Swap Table

Pin Number

CD14

CD15

10U_0603_6.3V6M

1

2

CD59

CD58

1U_0402_6.3V6K

CD@

1

2

1

2

CD@

Trac e wi dth:20 mils Space:20mils

2015/12/11

2

5 7 15 17 4 6 16 18 10 12

21 23 33 35 22 24 34 36 27 29

39 41 51 53 40 42 50 52 45 47

57 59 67 69 56 58 68 70 62 64

+VREF_CA

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS#0 DQS0

DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS#1 DQS1

DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS#2 DQS2

DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS#3 DQS3

Net NamePin Name DDRA_DQ1

DDRA_DQ5 DDRA_DQ6 DDRA_DQ7 DDRA_DQ0 DDRA_DQ4 DDRA_DQ2 DDRA_DQ3 DDRA_DQS#0 DDRA_DQS0

DDRA_DQ12 DDRA_DQ9 DDRA_DQ14 DDRA_DQ10 DDRA_DQ13 DDRA_DQ8 DDRA_DQ11 DDRA_DQ15 DDRA_DQS#1 DDRA_DQS1

DDRA_DQ20 DDRA_DQ21 DDRA_DQ18 DDRA_DQ23 DDRA_DQ17 DDRA_DQ16 DDRA_DQ22 DDRA_DQ19 DDRA_DQS#2 DDRA_DQS2

DDRA_DQ29 DDRA_DQ25 DDRA_DQ26 DDRA_DQ30 DDRA_DQ24 DDRA_DQ28 DDRA_DQ31 DDRA_DQ27 DDRA_DQS#3 DDRA_DQS3

+1.35V

12

RD9

1.82K_0402_1%

1 2

RD10 2_0402_5%

12

RD11

1.82K_0402_1%

Title

DDRIII SO-DIMM A

Size

Custom

Date: Sheet

Note: VREFtracewidth:20 milsatleast Spacing:20milstoothersign al/planes

PlacenearDIMMscoket

Document Number Re v

Friday, July 31, 2015

1

Pin Number

5 7 15 17 4 6 16 18 10 12

21 23 33 35 22 24 34 36 27 29

39 41 51 53 40 42 50 52 45 47

57 59 67 69 56 58 68 70 62 64

1

CD21

0.022U_0402_16V7-K

2

12

RD12

24.9_0402_1%

BMWQ1&2_UMA

1

DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS#4 DQS4

DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS#5 DQS5

DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS#6 DQS6

DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQS#7 DQS7

Net NamePin Name DDRA_DQ33

DDRA_DQ36 DDRA_DQ39 DDRA_DQ38 DDRA_DQ37 DDRA_DQ32 DDRA_DQ34 DDRA_DQ35 DDRA_DQS#4 DDRA_DQS4

DDRA_DQ44 DDRA_DQ41 DDRA_DQ46 DDRA_DQ47 DDRA_DQ45 DDRA_DQ40 DDRA_DQ43 DDRA_DQ42 DDRA_DQS#5 DDRA_DQS5

DDRA_DQ48 DDRA_DQ53 DDRA_DQ55 DDRA_DQ54 DDRA_DQ52 DDRA_DQ49 DDRA_DQ51 DDRA_DQ50 DDRA_DQS#6 DDRA_DQS6

DDRA_DQ61 DDRA_DQ60 DDRA_DQ59 DDRA_DQ63 DDRA_DQ56 DDRA_DQ57 DDRA_DQ62 DDRA_DQ58 DDRA_DQS#7 DDRA_DQS7

DDR_SM_VREFCA {5}+VREF_CA{18}

of

17 60

0.2

5

DDR_SB_VREFDQ {5}

+1.35V

12

RD15

RD16

1 2

2_0402_5%

D D

C C

B B

A A

0.022U_0402_16V7-K

CD32

1

2

12

RD18

24.9_0402_1%

1.82K_0402_1%

+VREF_DQ_DIMMB

1.82K_0402_1%

12

RD17

+3VS

CD54

2.2U_0603_6.3V6K

@

5

CD30

2.2U_0603_6.3V6K

CD31

.1U_0402_10V6-K

DDRB_DQ12 DDRB_DQ13

1

2

CD@

DDRB_CKE0{6}

DDRB_BS2#{6}

DDRB_CLK0{6} DDRB_CLK0#{6}

DDRB_BS0#{6} DDRB_WE#{6}

DDRB_CAS#{6}

DDRB_CS1#{6}

1

2

DDRB_DQ8

1

2

DDRB_DQ10 DDRB_DQ11

DDRB_DQ4 DDRB_DQ5

DDRB_DQS#0 DDRB_DQS0

DDRB_DQ7

DDRB_DQ16

DDRB_DQS#2 DDRB_DQS2

DDRB_DQ19 DDRB_DQ23

DDRB_DQ24

DDRB_DQ31 DDRB_DQ30

DDRB_CKE0

DDRB_BS2# DDRB_MA12

DDRB_MA9 DDRB_MA8

DDRB_MA5 DDRB_MA3

DDRB_MA1 DDRB_CLK0

DDRB_CLK0# DDRB_MA10

DDRB_BS0# DDRB_WE#

DDRB_CAS# DDRB_MA13

DDRB_CS1#

DDRB_DQ36 DDRB_DQ37

DDRB_DQS#4 DDRB_DQS4

DDRB_DQ38 DDRB_DQ39

DDRB_DQ45

DDRB_DQ47 DDRB_DQ46

DDRB_DQ52 DDRB_DQ49 DDRB_DQ53 DDRB_DQ48

DDRB_DQS#6 DDRB_DQS6

DDRB_DQ54 DDRB_DQ51

DDRB_DQ57 DDRB_DQ60

DDRB_DQ58 DDRB_DQ59 DDRB_DQ63

1 2

RD20

0_0402_5%

1 2

RD21 10K_0402_5%

1

CD55 .1U_0402_10V6-K

2

DDR3 SO-DIMM B

+1.35V +1.35V

3A@1.5V

3 5 7

9 11 13 15 17 19 21 23 25 27

33 35

39 41

45 47 49 51 53 55 57 59

63 67

69

73 75 77 79 81 83 85 87 89 91 93 95 97 99

101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197

@

199 201 203

205

4

JDDR2

VREF_DQ1VSS1 VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS129RESET# VSS1131VSS12 DQ10 DQ11 VSS1337VSS14 DQ16 DQ17 VSS1543VSS16 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS2261DQS#3 DM3 VSS2365VSS24 DQ26 DQ27 VSS2571VSS26

CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1

G1

LCN_DAN06-K4406-0102 ME@

DQ4 DQ5

VSS3

DQS#0

DQS0

VSS6

DQ6 DQ7

VSS8 DQ12 DQ13

VSS10

DM1

DQ14 DQ15

DQ20 DQ21

DM2

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3 DQ30

DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

DM4

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35 DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

DM6

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47 DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

SDA

VTT2

4

3

2

DDRB_DQ9

4 6 8

DDRB_DQS#1

10

DDRB_DQS1

12 14

DDRB_DQ14

16

DDRB_DQ15

18 20

DDRB_DQ1

22

DDRB_DQ0

24 26 28

CPU_DRAMRST#

30 32

DDRB_DQ6

34

DDRB_DQ2DDRB_DQ3

36 38

DDRB_DQ20

40

DDRB_DQ21DDRB_DQ18

42 44 46 48

DDRB_DQ17

50

DDRB_DQ22

52 54

DDRB_DQ27

56

DDRB_DQ28DDRB_DQ29

58 60

DDRB_DQS#3

62

DDRB_DQS3

64 66

DDRB_DQ25

68

DDRB_DQ26

70 72

DDRB_CKE1

74 76

DDRB_MA15

78

A15 A14

A11

A7 A6

A4 A2

A0

CK1

BA1

S0#

SCL

G2

80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

DDRB_MA14 DDRB_MA11

DDRB_MA7 DDRB_MA6

DDRB_MA4 DDRB_MA2

DDRB_MA0 DDRB_CLK1

DDRB_CLK1# DDRB_BS1#

DDRB_RAS# DDRB_CS0#

DDRB_ODT0 DDRB_ODT1

+VREF_CA_DIMMB DDRB_DQ33

DDRB_DQ32

DDRB_DQ35 DDRB_DQ34

DDRB_DQ41 DDRB_DQ40DDRB_DQ44

DDRB_DQS#5 DDRB_DQS5

DDRB_DQ42 DDRB_DQ43

DDRB_DQ50 DDRB_DQ55

DDRB_DQ56 DDRB_DQ61

DDRB_DQS#7 DDRB_DQS7

DDRB_DQ62

SMB_DATA_S3 SMB_CLK_S3

1

CD69

2

47P_0402_50V8J

For RF

DDRB_CKE1 {6}

DDRB_CLK1 {6} DDRB_CLK1# {6}

DDRB_BS1# {6} DDRB_RAS# {6}

DDRB_CS0# {6} DDRB_ODT0 {6}

DDRB_ODT1 {6}

.1U_0402_10V6-K

1

CD48

2

SMB_DATA_S3 {7,17,40} SMB_CLK_S3 {7,17,40}

+0.675VS

1

2

1

2

CD34

47P_0402_50V8J

RD19 0_0402_5%@

1

CD35

2

47P_0402_50V8J

Layout Note: Place near DIMM

+1.35V

10U_0603_6.3V6M

CD@

1U_0402_6.3V6K

1 2

Layout Note: Place near DIMM

+0.675VS

CD50

.1U_0402_10V6-K

1

2

CD@

CPU_DRAMRST# {6,17}

CD37

CD36

10U_0603_6.3V6M

1

2

CD@

CD45

CD44

1U_0402_6.3V6K

1

2

CD@

CD51

.1U_0402_10V6-K

1

2

CD@

(10uF_0603_6.3V)*8 (1U_0402_6.3V)*8

CD38

10U_0603_6.3V6M

1

2

CD46

1U_0402_6.3V6K

1

2

+VREF_CA {17}

CD39

10U_0603_6.3V6M

1

2

CD47

1U_0402_6.3V6K

1

2

CD@

10U_0603_6.3V6M

1U_0402_6.3V6K

(10U_0603_6.3V)*2 (.1U_0402_10V)*4

CD53

CD52

.1U_0402_10V6-K

10U_0603_6.3V6M

1

2

1

2

CD33

47P_0402_50V8J

@

.1U_0402_10V6-K

CD71

1

2

CD49

2.2U_0603_6.3V6K

0.65A@0.75V

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND C ONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF LC FUTUR E CENTER .

MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF LC FUTUR E CENTER .

3

2014/12/11

LC Future Center Secret Data

Deciphered Date

1

2

CD66

CD40

1

2

CD60

1

2

Swap Table

Pin Name Net Name

DDRB_DQ[0..63] {6} DDRB_DQS[0..7] {6} DDRB_DQS#[0..7] {6} DDRB_MA[0..15] {6}

CD43

CD42

CD41

10U_0603_6.3V6M

1

2

CD61

1U_0402_6.3V6K

1

2

CD67

10U_0603_6.3V6M

1

2

CD@

2

10U_0603_6.3V6M

1

2

CD62

1U_0402_6.3V6K

1

2

CD@

2015/12/11

10U_0603_6.3V6M

1

2

CD63

1U_0402_6.3V6K

1

2

CD@

Number

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

10

DQS#0

12

DQS0

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

27

DQS#1

29

DQS1

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

45

DQS#2

47

DQS2

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

62

DQS#3

64

DQS3

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

135

DQS#4

137

DQS4

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

152

DQS#5

154

DQS5

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

169

DQS#6

171

DQS6

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

186

DQS#7

188

DQS7

Title

DDRIII SO-DIMM B

Size

Document Number Re v

Custom

Monday, July 27, 2015

Date: Sheet

Monday, July 27, 2015

1

DDRB_DQ12 DDRB_DQ8 DDRB_DQ10 DDRB_DQ11 DDRB_DQ9 DDRB_DQ13 DDRB_DQ14 DDRB_DQ15 DDRB_DQS#1 DDRB_DQS1

DDRB_DQ4 DDRB_DQ5 DDRB_DQ7 DDRB_DQ3 DDRB_DQ1 DDRB_DQ0 DDRB_DQ6 DDRB_DQ2 DDRB_DQS#0 DDRB_DQS0

DDRB_DQ16 DDRB_DQ18 DDRB_DQ19 DDRB_DQ23 DDRB_DQ20 DDRB_DQ21 DDRB_DQ17 DDRB_DQ22 DDRB_DQS#2 DDRB_DQS2

DDRB_DQ29 DDRB_DQ24 DDRB_DQ31 DDRB_DQ30 DDRB_DQ27 DDRB_DQ28 DDRB_DQ25 DDRB_DQ26 DDRB_DQS#3 DDRB_DQS3

DDRB_DQ36 DDRB_DQ37 DDRB_DQ38 DDRB_DQ39 DDRB_DQ33 DDRB_DQ32 DDRB_DQ35 DDRB_DQ34 DDRB_DQS#4 DDRB_DQS4

DDRB_DQ44 DDRB_DQ45 DDRB_DQ47 DDRB_DQ46 DDRB_DQ41 DDRB_DQ40 DDRB_DQ42 DDRB_DQ43 DDRB_DQS#5 DDRB_DQS5

DDRB_DQ52 DDRB_DQ53 DDRB_DQ54 DDRB_DQ51 DDRB_DQ49 DDRB_DQ48 DDRB_DQ50 DDRB_DQ55 DDRB_DQS#6 DDRB_DQS6

DDRB_DQ57 DDRB_DQ60 DDRB_DQ58 DDRB_DQ59 DDRB_DQ56 DDRB_DQ61 DDRB_DQ62 DDRB_DQ63 DDRB_DQS#7 DDRB_DQS7

BMWQ1&2_UMA

1

18 60

0.2

of

Lenovo Ideapad 300 series Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual