Lenovo Ideapad 300S-14 Schematic

5
D D
4
3
2
1
Tesla Schematics
Skylake-U
C C
B B
A A
5
4
3
2
BOM1
BOM1
BOM1
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3
Tuesday, July 21, 2015
Tuesday, July 21, 2015
Tuesday, July 21, 2015
Date: Sheet of
Date: Sheet of
Date: Sheet of
Cover Page
Cover Page
Cover Page
Tesla SKL-U
Tesla SKL-U
Tesla SKL-U
1102
1102
1102
1
-1
-1
-1
Project code:
5
PCB P/N: 14292-1 Revision: -1
IO Board:
D D
GPU
VRAM(DDR3L) *4
2GB (Single Rank)
81,82,83,84
DDR3L
27MHz
HDMI V1.4a
C C
HDMI
57
14.0"/15.6" (FHD)
Touch Screen
Camera (HD)
D-MIC
HDA
Left side
CODEC
Realtek ALC3240
2CH SPEAKER (2CH 2W/4ohm)
B B
MIC_IN/GND
Universal Jack
IO Board (14874-SX)
SD Card Slot SDR104 SSD/MMC
29
HP_R/L
USB2(USB2.0)
CardReader
GL3213L
USB1&2
A A
(USB3.0)
5
N16S-GT N16V-GM
76,77,78,79,80
52
27
USB3.0 x 1,USB2.0 x 1
USB3.0 x 1,USB2.0 x 1
4
3
Tesla SKL-U Block Diagram
DDR3L 1333/1600MHz Channel B
34
Intel CPU
Skylake U
28W (UMA only) 15W (UMA&DIS)
SKL PCH-LP
10 USB 2.0/1.1 ports
6 USB 3.0 port s
High Definition A udio
3 SATA ports
6 PCIE ports
LPC I/F
ACPI 5.0
PCIe x 1
PCIe x 1
USB2.0 x 1
LPC BUS
SPI
I2C
SATA(Gen3) x 1
32.768KHz
24MHz
3
SPI
Flash ROM
16MB
LAN 10/100/1000
RealTek RTL8111H
NGFF WLAN
W/ Bluetooth COMBO
LPC debug port
KBC
NPCE285
25
Clickpad
HDD
PCIe x 4
eDP
USB2.0 x 1
USB2.0 x 1
HDA
USB2.0 x 1
USB3.0 x 1
USB Charger TPS2544
4
PS2
25MHz
Int. KB
60
2
DDR3L 1600
SODIMM B
13
RJ45
30
Conn.
PCB LAYER
L1:Top L2:VCC L3:Signal L4:Signal L5:GND
SMBUS
PWM
70
L6:Signal
Thermal
NUVOTON NCT7718W
FAN
INPUTS
1D0V_S5
INPUTS
1D0V_S5
26
26
VCCSTG
M5938ARD1U
OUTPUTS
+V1.00DX
VCCST
M5938ARD1U
OUTPUTS
+V1.00U_CPU
BOM1
BOM1
BOM1
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev C
C
C
Tuesday, July 21, 2015
Tuesday, July 21, 2015
Tuesday, July 21, 2015 Date: Sheet of
Date: Sheet of
Date: Sheet of
61
65
24
G-Sensor LIS3DETR
62
2
1
CHARGER
BQ24780RUYR
INPUTS
AD+
BT+
SYSTEM DC/DC
TPS51275CRUKR
INPUTS
DCBATOUT
CPU Core Power
NCP81208MNTXG NCP81382MNTXG x 2 NCP81382MNTXG(23e) NCP81253MNTBG
INPUTS
DCBATOUT
DCBATOUT +VCCGT
DCBATOUT
DDR3L SUS
TPS51716RUKR
INPUTS OUTPUTS
DCBATOUT 1D35V_S3
CPU VCCIO 0.975V
RT8068AZQWID
3D3V_S5
+V_VCCGTUS_VR (23e only)
+VCCSA_VRDCBATOUT
CPU VCCPRIM_CORE
0.95V
TPS22961DNYT
3D3V_S5
CPU DCDC-V1D00A
AOZ1268QI
INPUTS OUTPUTS
DCBATOUT
LDO-V1D5V
TLV70215DBVR
3D3V_S5
LDO-V1D8V
RT9025-25ZSP
INPUTS OUTPUTS
3D3V_S5
5V/3V S0
40
G5016KD1U
INPUTS
5V_S5
EOPIO/EDRAM (23e)
40
TPS22961DNYT
INPUTS
1D0V_S5 1D0V_S5
3D3V VGA
G5016KD1U
INPUTS
3D3V_S0 3D3V_S0
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, H sin Tai Wu Rd., Hsic hih,
21F, 88, Sec.1, H sin Tai Wu Rd., Hsic hih,
21F, 88, Sec.1, H sin Tai Wu Rd., Hsic hih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Block Diagram
Block Diagram
Block Diagram
Tesla SKL-U
Tesla SKL-U
Tesla SKL-U
2102
2102
2102
1
OUTPUTS
44
DCBATOUT
45
OUTPUTS
3D3V_AUX_S5 5V_PWR_2 5V_S5 3D3V_S5
46~50
33
OUTPUTS
VCC_CORE
51
0D65V_S0
52
OUTPUTSINPUTS
+VCCIO_VR
52
OUTPUTSINPUTS
VCCPRIM_CORE
53
1D0V_S5
54
OUTPUTSINPUTS
1D5V_S0
54
1D8V_S5
40
OUTPUTS
5V_S0 3D3V_S03D3V_S5
52
OUTPUTS
+V_EDRAM_VR +V_EOPIO_VR
86
OUTPUTS
+V_EDRAM_VR +V_EOPIO_VR
-1
-1
-1
5
4
3
2
1
Main Func = CPU
D D
C C
(Blanking)
B B
A A
5
4
3
2
BOM1
BOM1
BOM1
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3
Tuesday, July 21, 2015
Tuesday, July 21, 2015
Tuesday, July 21, 2015
Date: Sheet of
Date: Sheet of
Date: Sheet of
Reserved
Reserved
Reserved
Tesla SKL-U
Tesla SKL-U
Tesla SKL-U
3102
3102
3102
1
-1
-1
-1
5
Vinafix
4
3
2
1
Main Func = CPU
+VCCST_CPU
12
R419
R419 1KR2J-1-GP
SKYLAKE_ULT
SKYLAKE_ULT
1KR2J-1-GP
R420
R420
1 2
DY
DY
0R2J-2-GP
0R2J-2-GP
JTAG
JTAG
PROC_TCK
PROC_TDI PROC_TDO PROC_TMS
PROC_TRST#
PCH_JTAG_TCK
PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS
PCH_TRST#
4 OF 20
4 OF 20
JTAGX
B61 D60 A61 C60 B59
B56 D59 A56 C59 C61 A59
H_THERMTRIP# 40
PROC_TCK 99 PROC_TDI 99
PROC_TMS 99 PROC_TRST# 99
PCH_JTAG_TCK 99
PCH_JTAG_TDO 99
PCH_JTAG_TDO
1 2
R406 51R2J-2-GP
R406 51R2J-2-GP
1 2
DY
DY
DY
DY
R40751R2J-2-GP
R40751R2J-2-GP
+VCCSTG
+VCCSTG
D D
[PECI] and [PROCHOT#] Impedance control: 50 ohm
H_PECI24
H_PROCHOT#24,44,46
#543016 Rev0.7: Ra = 500 ohm / Rb = 1k ohm #544669 Rev0.52: Ra = 56 ohm (TO BE CHANGED TO 100 OHMS) / Rb = 62 ohm and 150 ohm
C C
Rb
TPAD14-OP-GP
TPAD14-OP-GP
+VCCSTG = 1.0 V +VCCSTG = 1.0 V
12
TP404
TP404
R401
R401 1KR2J-1-GP
1KR2J-1-GP
R403499R2F-2-GP R403499R2F-2-GP
1 2
Ra
TPAD14-OP-GP
TPAD14-OP-GP
TPAD14-OP-GP
TPAD14-OP-GP
GPP_B4/CPU_GP3 PROC_TCK
1
TP403
TP403
TP401
TP401
TPAD14-OP-GP
TPAD14-OP-GP
TP402
TP402
GPP_E3/CPU_GP0
1
12
R41249D9R2F-GP R41249D9R2F-GP
12
R41349D9R2F-GP R41349D9R2F-GP
12
R41449D9R2F-GP R41449D9R2F-GP
12
R41549D9R2F-GP R41549D9R2F-GP
H_CATERR#
1
H_PROCHOT#_R PCH_THERMTRIP SKTOCC#
1
CPU_POPIRCOMP PCH_POPIRCOMP
EDRAM_OPIO_RCOMP
EOPIO_RCOMP
PCH_THERMTRIP
CPU1D
CPU1D
D63
CATERR#
A54
PECI
C65
PROCHOT#
C63
THERMTRIP#
A65
SKTOCC#
C55
BPM#[0]
D55
BPM#[1]
B54
BPM#[2]
C56
BPM#[3]
A6
GPP_E3/CPU_GP0
A7
GPP_E7/CPU_GP1
BA5
GPP_B3/CPU_GP2
AY5
GPP_B4/CPU_GP3
AT16
PROC_POPIRCOMP
AU16
PCH_OPIRCOMP
H66
OPCE_RCOMP
H65
OPC_RCOMP
SKYLAKE-U-GP
SKYLAKE-U-GP
071.SKYLA.000U
071.SKYLA.000U
CPU MISC
CPU MISC
(#543016) PROCHOT# Routing Guidelines
B B
M1,2,3,4,5: <3 inches M6: 1-11 inches MCPU: 0.3-1.5 inches Mt <0.3 mils Main route(M1+M2+M3+M4+M5+M6+MCPU): 1-12 inches
A A
5
4
3
2
BOM1
BOM1
BOM1
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CPU_(JTAG/CPU SIDE BAND)
CPU_(JTAG/CPU SIDE BAND)
CPU_(JTAG/CPU SIDE BAND)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3
Tuesday, July 21, 2015
Tuesday, July 21, 2015
Tuesday, July 21, 2015
Date: Sheet of
Date: Sheet of
Date: Sheet of
Tesla SKL-U
Tesla SKL-U
Tesla SKL-U
4102
4102
4102
1
-1
-1
-1
Main Func = CPU
5
4
3
2
1
DDR3L ball type: Interleaved Type
M_B_DQ[63:0]13
D D
2 OF 20
CPU1B
CPU1B
AL71
DDR0_DQ[0]
AL68
DDR0_DQ[1]
AN68
DDR0_DQ[2]
AN69
DDR0_DQ[3]
AL70
DDR0_DQ[4]
AL69
DDR0_DQ[5]
AN70
DDR0_DQ[6]
AN71
DDR0_DQ[7]
AR70
DDR0_DQ[8]
AR68
DDR0_DQ[9]
AU71
DDR0_DQ[10]
AU68
DDR0_DQ[11]
AR71
DDR0_DQ[12]
AR69
DDR0_DQ[13]
AU70
DDR0_DQ[14]
AU69
M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3
M_B_DQ[0:7]
M_B_DQ[8:15]
C C
M_B_DQ[16:23]
M_B_DQ[24:31]
DQ Bit Swapping is allowed within the same byte, and Byte Swapping is allowed within the same channel.
B B
Clock (CLK and CLK#) and Strobe (DQS and DQS#) differential signal swapping within a pair is not allowed. Also differential clock pair to clock pair swapping within a channel is not allowed.
M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15
M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31
DDR0_DQ[15]
AF65
DDR1_DQ[0]/DDR0_DQ[16]
AF64
DDR1_DQ[1]/DDR0_DQ[17]
AK65
DDR1_DQ[2]/DDR0_DQ[18]
AK64
DDR1_DQ[3]/DDR0_DQ[19]
AF66
DDR1_DQ[4]/DDR0_DQ[20]
AF67
DDR1_DQ[5]/DDR0_DQ[21]
AK67
DDR1_DQ[6]/DDR0_DQ[22]
AK66
DDR1_DQ[7]/DDR0_DQ[23]
AF70
DDR1_DQ[8]/DDR0_DQ[24]
AF68
DDR1_DQ[9]/DDR0_DQ[25]
AH71
DDR1_DQ[10]/DDR0_DQ[26]
AH68
DDR1_DQ[11]/DDR0_DQ[27]
AF71
DDR1_DQ[12]/DDR0_DQ[28]
AF69
DDR1_DQ[13]/DDR0_DQ[29]
AH70
DDR1_DQ[14]/DDR0_DQ[30]
AH69
DDR1_DQ[15]/DDR0_DQ[31]
BB65
DDR0_DQ[16]/DDR0_DQ[32]
AW65
DDR0_DQ[17]/DDR0_DQ[33]
AW63
DDR0_DQ[18]/DDR0_DQ[34]
AY63
DDR0_DQ[19]/DDR0_DQ[35]
BA65
DDR0_DQ[20]/DDR0_DQ[36]
AY65
DDR0_DQ[21]/DDR0_DQ[37]
BA63
DDR0_DQ[22]/DDR0_DQ[38]
BB63
DDR0_DQ[23]/DDR0_DQ[39]
BA61
DDR0_DQ[24]/DDR0_DQ[40]
AW61
DDR0_DQ[25]/DDR0_DQ[41]
BB59
DDR0_DQ[26]/DDR0_DQ[42]
AW59
DDR0_DQ[27]/DDR0_DQ[43]
BB61
DDR0_DQ[28]/DDR0_DQ[44]
AY61
DDR0_DQ[29]/DDR0_DQ[45]
BA59
DDR0_DQ[30]/DDR0_DQ[46]
AY59
DDR0_DQ[31]/DDR0_DQ[47]
AT66
DDR1_DQ[16]/DDR0_DQ[48]
AU66
DDR1_DQ[17]/DDR0_DQ[49]
AP65
DDR1_DQ[18]/DDR0_DQ[50]
AN65
DDR1_DQ[19]/DDR0_DQ[51]
AN66
DDR1_DQ[20]/DDR0_DQ[52]
AP66
DDR1_DQ[21]/DDR0_DQ[53]
AT65
DDR1_DQ[22]/DDR0_DQ[54]
AU65
DDR1_DQ[23]/DDR0_DQ[55]
AT61
DDR1_DQ[24]/DDR0_DQ[56]
AU61
DDR1_DQ[25]/DDR0_DQ[57]
AP60
DDR1_DQ[26]/DDR0_DQ[58]
AN60
DDR1_DQ[27]/DDR0_DQ[59]
AN61
DDR1_DQ[28]/DDR0_DQ[60]
AP61
DDR1_DQ[29]/DDR0_DQ[61]
AT60
DDR1_DQ[30]/DDR0_DQ[62]
AU60
DDR1_DQ[31]/DDR0_DQ[63]
SKYLAKE-U-GP
SKYLAKE-U-GP
071.SKYLA.000U
071.SKYLA.000U
SKYLAKE_ULT
SKYLAKE_ULT
DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR0_DQ[16]
DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
DDR0_DQ[17]
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0_DQ[18]
DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]
DDR0_DQ[19]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]
DDR0_DQ[20]
DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
DDR0_DQ[21]
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DDR0_DQ[22]
DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]
DDR0_DQ[23]
DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]
DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]
DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]
DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]
DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]
DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]
DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]
DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]
DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]
DDR1_DQSN[0]/DDR0_DQSN[2] DDR1_DQSP[0]/DDR0_DQSP[2] DDR1_DQSN[1]/DDR0_DQSN[3] DDR1_DQSP[1]/DDR0_DQSP[3] DDR0_DQSN[2]/DDR0_DQSN[4] DDR0_DQSP[2]/DDR0_DQSP[4] DDR0_DQSN[3]/DDR0_DQSN[5] DDR0_DQSP[3]/DDR0_DQSP[5] DDR1_DQSN[2]/DDR0_DQSN[6] DDR1_DQSP[2]/DDR0_DQSP[6] DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQSP[3]/DDR0_DQSP[7]
DDR CH - A
DDR CH - A
PDG: DDR/ODT
A A
2 OF 20
DDR0_CKN[0] DDR0_CKP[0] DDR0_CKN[1] DDR0_CKP[1]
DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3]
DDR0_CS#[0]
DDR0_CS#[1] DDR0_ODT[0] DDR0_ODT[1]
DDR0_MA[3] DDR0_MA[4]
DDR0_DQSN[0] DDR0_DQSP[0] DDR0_DQSN[1] DDR0_DQSP[1]
DDR0_ALERT#
DDR0_PAR
DDR_VREF_CA DDR0_VREF_DQ DDR1_VREF_DQ
DDR_VTT_CNTL
AU53 AT53 AU55 AT55
BA56 BB56 AW56 AY56
AU45 AU43 AT45 AT43
BA51 BB54 BA52 AY52 AW52 AY55 AW54 BA54 BA55 AY54
AU46 AU48 AT46 AU50 AU52 AY51 AT48 AT50 BB50 AY50 BA50 BB52
AM70 AM69 AT69 AT70 AH66 AH65 AG69 AG70 BA64 AY64 AY60 BA60 AR66 AR65 AR61 AR60
AW50 AT52
AY67 AY68 BA67
AW67
M_B_DQS_DN0 M_B_DQS_DP0 M_B_DQS_DN1 M_B_DQS_DP1
M_B_DQS_DN2 M_B_DQS_DP2 M_B_DQS_DN3 M_B_DQS_DP3
DDR0_PAR
M_VREF_DQ_DIMM0
SM_PGCNTL
SM_PGCNTL
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
TP501 TPAD14-OP-GPTP501 TPAD14-OP-GP
1
V_SM_VREF_CNT 42
TP503 TPAD14-OP-GPTP503 TPAD14-OP-GP
1
M_VREF_DQ_DIM1 42
2nd = 084.00138.0A31
2nd = 084.00138.0A31
G
Q501
Q501 DMN5L06K-7-GP
DMN5L06K-7-GP
84.05067.031
84.05067.031
DS
M_B_DQ[32:39]
M_B_DQ[40:47]
M_B_DQ[48:55]
M_B_DQ[56:63]
3D3V_S01D35V_S3
12
R506
R506 220KR2F-GP
220KR2F-GP
M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47
M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63
DDR_PG_OUT 51
CPU1C
CPU1C
AY39
DDR0_DQ[32]/DDR1_DQ[0]
AW39
DDR0_DQ[33]/DDR1_DQ[1]
AY37
DDR0_DQ[34]/DDR1_DQ[2]
AW37
DDR0_DQ[35]/DDR1_DQ[3]
BB39
DDR0_DQ[36]/DDR1_DQ[4]
BA39
DDR0_DQ[37]/DDR1_DQ[5]
BA37
DDR0_DQ[38]/DDR1_DQ[6]
BB37
DDR0_DQ[39]/DDR1_DQ[7]
AY35
DDR0_DQ[40]/DDR1_DQ[8]
AW35
DDR0_DQ[41]/DDR1_DQ[9]
AY33
DDR0_DQ[42]/DDR1_DQ[10]
AW33
DDR0_DQ[43]/DDR1_DQ[11]
BB35
DDR0_DQ[44]/DDR1_DQ[12]
BA35
DDR0_DQ[45]/DDR1_DQ[13]
BA33
DDR0_DQ[46]/DDR1_DQ[14]
BB33
DDR0_DQ[47]/DDR1_DQ[15]
AU40
DDR1_DQ[32]/DDR1_DQ[16]
AT40
DDR1_DQ[33]/DDR1_DQ[17]
AT37
DDR1_DQ[34]/DDR1_DQ[18]
AU37
DDR1_DQ[35]/DDR1_DQ[19]
AR40
DDR1_DQ[36]/DDR1_DQ[20]
AP40
DDR1_DQ[37]/DDR1_DQ[21]
AP37
DDR1_DQ[38]/DDR1_DQ[22]
AR37
DDR1_DQ[39]/DDR1_DQ[23]
AT33
DDR1_DQ[40]/DDR1_DQ[24]
AU33
DDR1_DQ[41]/DDR1_DQ[25]
AU30
DDR1_DQ[42]/DDR1_DQ[26]
AT30
DDR1_DQ[43]/DDR1_DQ[27]
AR33
DDR1_DQ[44]/DDR1_DQ[28]
AP33
DDR1_DQ[45]/DDR1_DQ[29]
AR30
DDR1_DQ[46]/DDR1_DQ[30]
AP30
DDR1_DQ[47]/DDR1_DQ[31]
AY31
DDR0_DQ[48]/DDR1_DQ[32]
AW31
DDR0_DQ[49]/DDR1_DQ[33]
AY29
DDR0_DQ[50]/DDR1_DQ[34]
AW29
DDR0_DQ[51]/DDR1_DQ[35]
BB31
DDR0_DQ[52]/DDR1_DQ[36]
BA31
DDR0_DQ[53]/DDR1_DQ[37]
BA29
DDR0_DQ[54]/DDR1_DQ[38]
BB29
DDR0_DQ[55]/DDR1_DQ[39]
AY27
DDR0_DQ[56]/DDR1_DQ[40]
AW27
DDR0_DQ[57]/DDR1_DQ[41]
AY25
DDR0_DQ[58]/DDR1_DQ[42]
AW25
DDR0_DQ[59]/DDR1_DQ[43]
BB27
DDR0_DQ[60]/DDR1_DQ[44]
BA27
DDR0_DQ[61]/DDR1_DQ[45]
BA25
DDR0_DQ[62]/DDR1_DQ[46]
BB25
DDR0_DQ[63]/DDR1_DQ[47]
AU27
DDR1_DQ[48]
AT27
DDR1_DQ[49]
AT25
DDR1_DQ[50]
AU25
DDR1_DQ[51]
AP27
DDR1_DQ[52]
AN27
DDR1_DQ[53]
AN25
DDR1_DQ[54]
AP25
DDR1_DQ[55]
AT22
DDR1_DQ[56]
AU22
DDR1_DQ[57]
AU21
DDR1_DQ[58]
AT21
DDR1_DQ[59]
AN22
DDR1_DQ[60]
AP22
DDR1_DQ[61]
AP21
DDR1_DQ[62]
AN21
DDR1_DQ[63]
SKYLAKE-U-GP
SKYLAKE-U-GP
071.SKYLA.000U
071.SKYLA.000U
SKYLAKE_ULT
SKYLAKE_ULT
DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]
DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]
DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]
DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]
DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]
DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]
DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]
DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]
DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]
DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
DDR0_DQSN[4]/DDR1_DQSN[0] DDR0_DQSP[4]/DDR1_DQSP[0] DDR0_DQSN[5]/DDR1_DQSN[1] DDR0_DQSP[5]/DDR1_DQSP[1] DDR1_DQSN[4]/DDR1_DQSN[2] DDR1_DQSP[4]/DDR1_DQSP[2] DDR1_DQSN[5]/DDR1_DQSN[3] DDR1_DQSP[5]/DDR1_DQSP[3] DDR0_DQSN[6]/DDR1_DQSN[4] DDR0_DQSP[6]/DDR1_DQSP[4] DDR0_DQSN[7]/DDR1_DQSN[5] DDR0_DQSP[7]/DDR1_DQSP[5]
DDR CH - B
DDR CH - B
3 OF 20
3 OF 20
DDR1_CKN[0] DDR1_CKN[1] DDR1_CKP[0] DDR1_CKP[1]
DDR1_CKE[0] DDR1_CKE[1] DDR1_CKE[2] DDR1_CKE[3]
DDR1_CS#[0] DDR1_CS#[1] DDR1_ODT[0] DDR1_ODT[1]
DDR1_MA[3] DDR1_MA[4]
DDR1_DQSN[6] DDR1_DQSP[6] DDR1_DQSN[7] DDR1_DQSP[7]
DDR1_ALERT#
DDR1_PAR
DRAM_RESET# DDR_RCOMP[0] DDR_RCOMP[1] DDR_RCOMP[2]
AN45 AN46 AP45 AP46
AN56 AP55 AN55 AP53
BB42 AY42 BA42 AW42
AY48 AP50 BA48 BB48 AP48 AP52 AN50 AN48 AN53 AN52
BA43 AY43 AY44 AW44 BB44 AY47 BA44 AW46 AY46 BA46 BB46 BA47
BA38 AY38 AY34 BA34 AT38 AR38 AT32 AR32 BA30 AY30 AY26 BA26 AR25 AR27 AR22 AR21
AN43 AP43 AT13 AR18 AT18 AU18
M_B_A5 M_B_A9 M_B_A6 M_B_A8 M_B_A7
M_B_A12 M_B_A11 M_B_A15 M_B_A14
M_B_A13
M_B_A2
M_B_A10 M_B_A1 M_B_A0 M_B_A3 M_B_A4
M_B_DQS_DN4 M_B_DQS_DP4 M_B_DQS_DN5 M_B_DQS_DP5
M_B_DQS_DN6 M_B_DQS_DP6 M_B_DQS_DN7 M_B_DQS_DP7
DDR1_PAR SM_DRAMRST# SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2
M_B_CLK#0 13 M_B_CLK#1 13 M_B_CLK0 13 M_B_CLK1 13
M_B_CKE0 13 M_B_CKE1 13
M_B_CS#0 13 M_B_CS#1 13 M_B_DIMB_ODT0 13 M_B_DIMB_ODT1 13
M_B_BS2 13
M_B_CAS# 13
M_B_WE# 13
M_B_RAS# 13
M_B_BS0 13
M_B_BS1 13
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
1
R501 121R2F-GPR501 121R2F-GP
1 2
R502 80D6R2F-L-GPR502 80D6R2F-L-GP
1 2
R503 100R2F-L1-GP-UR503 100R2F-L1-GP-U
1 2
#543016
Design Guideline: SM_RCOMP keep routing length less than 500 mils.
M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15
M_B_DQS_DN0 M_B_DQS_DN1 M_B_DQS_DN2 M_B_DQS_DN3 M_B_DQS_DN4 M_B_DQS_DN5 M_B_DQS_DN6 M_B_DQS_DN7
M_B_DQS_DP0 M_B_DQS_DP1 M_B_DQS_DP2 M_B_DQS_DP3 M_B_DQS_DP4 M_B_DQS_DP5 M_B_DQS_DP6 M_B_DQS_DP7
Layout Note:
M_B_A[15:0] 13
TP502 TPAD14-OP-GPTP502 TPAD14-OP-GP
M_B_DQS_DN[7:0] 13
M_B_DQS_DP[7:0] 13
1D35V_S3
12
R505
R505 470R2F-GP
470R2F-GP
R504
R504
1 2
0R0402-PAD
0R0402-PAD
12
ED501
ED501
PESD5V0U1BL-GP-U1
PESD5V0U1BL-GP-U1
PESD5V0U1BL-GP-U1
PESD5V0U1BL-GP-U1
12
ED502
ED502
DDR3_DRAMRST# 13
BOM1
BOM1
BOM1
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Numb er Rev
Size Document Numb er Rev
Size Document Numb er Rev A2
A2
A2
Tuesday, July 21, 2015
Tuesday, July 21, 2015
Tuesday, July 21, 2015 Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
CPU_(DDR)
CPU_(DDR)
CPU_(DDR)
Tesla SKL-U
Tesla SKL-U
Tesla SKL-U
1
-1
-1
5102
5102
5102
-1
Main Func = CPU
D D
C C
PCH strap pin:
CFG3
CFG4
5
CPU1S
CPU1S
RESERVED SIGNALS-1
RESERVED SIGNALS-1
SKYLAKE_ULT
E68
CFG[0]
B67
CFG[1]
D65
CFG3
CFG399
CFG4
CFG_RCOMP
R60149D9R2F-GP R60149D9R2F-GP
ITP_P MODE99
12
R604
R604 1KR2J-1-GP
1KR2J-1-GP
DY
DY
12
RSVD_TP_BA70
1
TP601TPAD14-OP-GP TP601TPAD14-OP-GP TP602TPAD14-OP-GP TP602TPAD14-OP-GP
TP612TPAD14-OP-GP TP612TPAD14-OP-GP TP613TPAD14-OP-GP TP613TPAD14-OP-GP
[BDW Only]PHYSICAL_DEBUG_ENABLED (DFX PRIVACY)
CFG[3]
RSVD_TP_BA68
1
RSVD_F65
1
RSVD_G65
1
0 : ENABLED SET DFX ENABLED BIT IN DEBUG INTERFACE MSR
1 : DISABLED
CFG[2]
D67
CFG[3]
E70
CFG[4]
C68
CFG[5]
D68
CFG[6]
C67
CFG[7]
F71
CFG[8]
G69
CFG[9]
F70
CFG[10]
G68
CFG[11]
H70
CFG[12]
G71
CFG[13]
H69
CFG[14]
G70
CFG[15]
E63
CFG[16]
F63
CFG[17]
E66
CFG[18]
F66
CFG[19]
E60
CFG_RCOMP
E8
ITP_PMODE
AY2
RSVD#AY2
AY1
RSVD#AY1
D1
RSVD#D1
D3
RSVD#D3
K46
RSVD#K46
K45
RSVD#K45
AL25
RSVD#AL25
AL27
RSVD#AL27
C71
RSVD#C71
B70
RSVD#B70
F60
RSVD#F60
A52
RSVD#A52
BA70
RSVD_TP#BA70
BA68
RSVD_TP#BA68
J71
RSVD#J71
J68
RSVD#J68
F65
VSS
G65
VSS
F61
RSVD#F61
E61
RSVD#E61
SKYLAKE-U-GP
SKYLAKE-U-GP
071.SKYLA.000U
071.SKYLA.000U
SKYLAKE_ULT
(#543016)
12
DISPLAY PORT PRESENCE STRAP
R605
R605 1KR2J-1-GP
1KR2J-1-GP
CFG[4]
0 : ENABLED An external Display Port device is connected to the Embedded Display Port.
1 : DISABLED (Default)
No Physical Display Port attached to Embedded DisplayPort*. No connect for disable.
4
RSVD_TP_AW71 RSVD_TP_AW70
19 OF 20
19 OF 20
RSVD_TP#BB68 RSVD_TP#BB69
RSVD_TP#AK13 RSVD_TP#AK12
RSVD#BB2 RSVD#BA3
RSVD#D5 RSVD#D4 RSVD#B2 RSVD#C2
RSVD#B3 RSVD#A3
RSVD#AW1
RSVD#E1 RSVD#E2
RSVD#BA4 RSVD#BB4
RSVD#A4 RSVD#C4
RSVD#A69 RSVD#B69
RSVD#AY3
RSVD#D71 RSVD#C70
RSVD#C54 RSVD#D54
ZVM#
RSVD_TP#AW71 RSVD_TP#AW70
MSM#
PROC_SELECT#
3
RSVD_TP_BB68
BB68
RSVD_TP_BB69
BB69
RSVD_TP_AK13
AK13
RSVD_TP_AK12
AK12
BB2 BA3
TP5_AU5
AU5
TP5
TP6_AT5
AT5
TP6
D5 D4 B2 C2
B3 A3
AW1
E1 E2
BA4 BB4
A4 C4
TP4_BB5
BB5
TP4
A69 B69
RSVD_AY3
AY3
D71 C70
C54 D54
TP1_AY4
AY4
TP1
TP2_BB3
BB3
TP2
VSS_AY71
AY71
VSS
ZVM#
AR56
RSVD_TP_AW71
AW71
RSVD_TP_AW70
AW70
MSM#
AP56 C64
PROC_SELECT#
R606
R606
1 2
0R2J-2-GP
0R2J-2-GP
DY
DY
R602
R602
1 2
0R0402-PAD
0R0402-PAD
1 1
1 1
1 1
1
1 1
1
1 1
1
1 2
R603
R603
100KR2J-1-GP
100KR2J-1-GP
TP603 TPAD14-OP-GPTP603 TPAD14-OP-GP TP604 TPAD14-OP-GPTP604 TPAD14-OP-GP
TP605 TPAD14-OP-GPTP605 TPAD14-OP-GP TP606 TPAD14-OP-GPTP606 TPAD14-OP-GP
TP607 TPAD14-OP-GPTP607 TPAD14-OP-GP TP608 TPAD14-OP-GPTP608 TPAD14-OP-GP
TP609 TPAD14-OP-GPTP609 TPAD14-OP-GP
TP610 TPAD14-OP-GPTP610 TPAD14-OP-GP TP611 TPAD14-OP-GPTP611 TPAD14-OP-GP
TP616 TPAD14-OP-GPTP616 TPAD14-OP-GP
TP614 TPAD14-OP-GPTP614 TPAD14-OP-GP TP615 TPAD14-OP-GPTP615 TPAD14-OP-GP
TP617 TPAD14-OP-GPTP617 TPAD14-OP-GP
[#543016 Rev0.9]
#54469 CRB.
+VCCST_CPU
2
1
SKL(#543016): Processor strap CFG[4] should be pulled low to enable embedded DisplayPort*
B B
A A
BOM1
BOM1
BOM1
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Numb er Rev
Size Document Numb er Rev
Size Document Numb er Rev A2
A2
A2
Tuesday, July 21, 2015
Tuesday, July 21, 2015
Tuesday, July 21, 2015 Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
CPU_(RESERVED)
CPU_(RESERVED)
CPU_(RESERVED)
Tesla SKL-U
Tesla SKL-U
Tesla SKL-U
1
6102
6102
6102
-1
-1
-1
3A
TP701TPAD14-OP-GP TP701TPAD14-OP-GP
TP702TPAD14-OP-GP TP702TPAD14-OP-GP
1 2
0R0603-PAD
0R0603-PAD
3A
R702
R702
23e
23e
+V_EDRAM_VR
23e
23e
23e
23e
+V_EOPIO_VR
23e
23e
23e
23e
5
+VCCCOREG0
1
+VCCCOREG1
1
+V_EDRAM_VR
VCC_EDR AM_FU SEPR G
VCCSENS E_ED RAM_VR VSSSENS E_ED RAM_VR
+V_EOPIO_VR
VCCSENS E_EO PIO_VR VSSSENS E_EO PIO_VR
12
R724
R724
100R2J-2-GP
100R2J-2-GP
VCCSENS E_ED RAM_VR VSSSENS E_ED RAM_VR
12
R725
R725
100R2J-2-GP
100R2J-2-GP
12
R729
R729
100R2J-2-GP
100R2J-2-GP
VCCSENS E_EO PIO_VR VSSSENS E_EO PIO_VR
12
R731
R731
100R2J-2-GP
100R2J-2-GP
VCC_COR E
CPU1L
CPU1L
A30
VCC
A34
VCC
A39
VCC
A44
VCC
AK33
VCC
AK35
VCC
AK37
VCC
AK38
VCC
AK40
VCC
AL33
VCC
AL37
VCC
AL40
VCC
AM32
VCC
AM33
VCC
AM35
VCC
AM37
VCC
AM38
VCC
G30
VCC
K32
RSVD#K32
AK32
RSVD#AK32
AB62
VCCOPC
P62
VCCOPC
V62
VCCOPC
H63
VCC_OPC_1P8
G61
VCC_OPC_1P8
AC63
VCCOPC_SENSE
AE63
VSSOPC_SENSE
AE62
VCCEOPIO
AG62
VCCEOPIO
AL63
VCCEOPIO_SENSE
AJ62
VSSEOPIO_SENSE
SKYLAKE-U-GP
SKYLAKE-U-GP
071.SKYLA.000U
071.SKYLA.000U
RSVD_K32
RSVD_AK32
CPU POWER 1 OF 4
CPU POWER 1 OF 4
SKYLAKE_ULT
SKYLAKE_ULT
12 OF 20
12 OF 20
G32
VCC
G33
VCC
G35
VCC
G37
VCC
G38
VCC
G40
VCC
G42
VCC
J30
VCC
J33
VCC
J37
VCC
J40
VCC
K33
VCC
K35
VCC
K37
VCC
K38
VCC
K40
VCC
K42
VCC
K43
VCC
E32
VCC_SENSE
E33
VSS_SENSE
B63
VIDALERT#
A63
VIDSCK
D64
VIDSOUT
G20
VCCSTG
SVID DATA
VCC_COR E
H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT
+VCCFUSEPRG
VCC_SEN SE 46 VSS_SEN SE 46
Main Func = CPU
D D
+V1.8S_EDRAM
140mA
+V_EDRAM_VR
12
12
C702SC10U6D3V3MX-GP
C702SC10U6D3V3MX-GP
C701SC10U6D3V3MX-GP
C701SC10U6D3V3MX-GP
23e
23e
23e
23e
+V_EOPIO_VR
12
12
C704SC10U6D3V3MX-GP
C704SC10U6D3V3MX-GP
C703SC10U6D3V3MX-GP
C703SC10U6D3V3MX-GP
23e
23e
23e
23e
C C
CLOSE TO CPU
H_CPU_SVIDDAT
R703
R703
1 2
0R0603-PAD
0R0603-PAD
+VCCST_CPU
12
R726
R726 100R2F-L1-GP-U
100R2F-L1-GP-U
4
CPU1M
CPU1M
+VCCGT
+VCCSTG
VCCGT_ SENS E46 VSSGT_ SENS E46
Layout Note: The total Length of Data and Clock (from CPU to each VR) must be equal (±0.1 inch). Route the Alert signal between the Clock and the Data signals.
#544669
R709
R709
1 2
0R0402-PAD
0R0402-PAD
A48 A53 A58 A62
A66 AA63 AA64 AA66 AA67 AA69 AA70 AA71 AC64 AC65 AC66 AC67 AC68 AC69 AC70 AC71
J43
J45
J46
J48
J50
J52
J53
J55
J56
J58
J60
K48
K50
K52
K53
K55
K56
K58
K60
L62
L63
L64
L65
L66
L67
L68
L69
L70
L71
M62
N63
N64
N66
N67
N69
J70
J69
SKYLAKE-U-GP
SKYLAKE-U-GP
071.SKYLA.000U
071.SKYLA.000U
VR_SVID_D ATA 46
CPU POWER 2 OF 4
CPU POWER 2 OF 4
VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT
VCCGT_SENSE VSSGT_SENSE
SKYLAKE_ULT
SKYLAKE_ULT
VCCGTX_SENSE VSSGTX_SENSE
13 OF 20
13 OF 20
VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT
VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX
3
+VCCGT
N70 N71 R63 R64 R65 R66 R67 R68 R69 R70 R71 T62 U65 U68 U71 W63 W64 W65 W66 W67 W68 W69 W70 W71 Y62
+VCCGT
AK42 AK43 AK45 AK46 AK48 AK50 AK52 AK53 AK55 AK56 AK58 AK60 AK70 AL43 AL46 AL50 AL53 AL56 AL60 AM48 AM50 AM52 AM53 AM56 AM58 AU58 AU63 BB57 BB66
AK62 AL61
#544669 CRB.
+VDDQ_CPU_CLK1D35V_S3
R705
R705
1 2
0R0603-PAD
0R0603-PAD
R710
R710
1 2
0R0402-PAD
0R0402-PAD
+VCCSTG(ICCMAX.=0.16A)
DY
DY
+VCCSTG+VCCIO
12
C722
C722 SC1U10V2KX-1GP
SC1U10V2KX-1GP
VCC_COR E
+VCCGT
1D35V_S3+VDDQ_CPU_CLK
DY
RN701
RN701
2 3 1
SRN100F-1-GP
SRN100F-1-GP
RN702
RN702
R1
R1
1
R2
R2
2 3
SRN100F-1-GP
SRN100F-1-GP
12
+VDDQ_CPU_CLK
C715SC10U6D3V3MX-GP C715SC10U6D3V3MX-GP
12
+VCCST_CPU
C716SC1U10V2KX-1GP C716SC1U10V2KX-1GP
12
C717SC1U10V2KX-1GPDYC717SC1U10V2KX-1GP
12
C718SCD1U16V2KX-3GP C718SCD1U16V2KX-3GP
12
R2
R2
4
R1
R1
4
C719
C719 SC1U10V2KX-1GP
SC1U10V2KX-1GP
+VCCSTG
1D35V_S3
+V1.00U_CPU
12
C720
C720
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
AU23 AU28 AU35 AU42 BB23 BB32 BB41 BB47 BB51
AM40
0.04 A
A18
A22
AL23
K20 K21
0.12 A
12
C721
C721
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
VCC_SEN SE 46
VSS_SEN SE 46
Layout Note:
1. Place close to CPU
2. VCC_SENSE/ VSS_SENSE impedance=50 ohm
3. Length match<25mil
VCCGT_ SENS E 46
VSSGT_ SENS E 4 6
CPU1N
CPU1N
CPU POWER 3 OF 4
CPU POWER 3 OF 4
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VDDQC
VCCST
VCCSTG
VCCPLL_OC
VCCPLL VCCPLL
SKYLAKE-U-GP
SKYLAKE-U-GP
071.SKYLA.000U
071.SKYLA.000U
SKYLAKE_ULT
SKYLAKE_ULT
2
VCCIO_SENSE VSSIO_SENSE
VSSSA_SENSE VCCSA_SENSE
14 OF 20
14 OF 20
VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO
VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA
AK28 AK30 AL30 AL42 AM28 AM30 AM42
AK23 AK25 G23 G25 G27 G28 J22 J23 J27 K23 K25 K27 K28 K30
AM23 AM22
H21 H20
VCCIO_VR_ FB
VSSIO_VR_ FB
VCCSA_SE NSE VSSSA_SE NSE
VCCIO_VR_ FB VSSIO_VR_ FB
+VCCIO
+VCCIO(ICCMAX.=2.73A
+VCCSA
+VCCIO
12
R733
R733 100R2J-2-GP
100R2J-2-GP
12
R730
R730 100R2J-2-GP
100R2J-2-GP
+VCCSA
12
R735
R735 100R2J-2-GP
100R2J-2-GP
12
R734
R734 100R2J-2-GP
100R2J-2-GP
VSSSA_SE NSE 46 VCCSA_SE NSE 46
(#543016 SKL U/Y PDG rev1.0)
1
12
R732
R732
1 2
0R0402-PAD
0R0402-PAD
+VCCST_CPU
4
+VCCST_CPU
12
R727
R727 56R2J-4-GP
56R2J-4-GP
12
R723
R723 54D9R2F-L1-GP
54D9R2F-L1-GP
DY
DY
#544669 CLOSE TO CPU
#544669 CLOSE TO VR
VR_SVID_AL ERT # 46
VR_SVID_C LK 46
SVID_543016:
BOM1
BOM1
BOM1
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A1
A1
A1
Tuesday, July 21, 2015
Tuesday, July 21, 2015
Tuesday, July 21, 2015
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
1
Wist ron C orpor ation
Wist ron C orpor ation
Wist ron C orpor ation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
CPU(VCC_CORE)
CPU(VCC_CORE)
CPU(VCC_CORE)
Tesla SKL-U
Tesla SKL-U
Tesla SKL-U
-1
-1
-1
7102
7102
7102
SVID CLOCK
B B
A A
5
H_CPU_SVIDCLK
H_CPU_SVIDALRT#
R728
R728
220R2J-L2-GP
220R2J-L2-GP
5
4
3
2
1
Main Func = CPU
D D
1 OF 20
CPU1A
CPU1A
HDMI_CRT_N057
HDMI_CRT_P057
HDMI_CRT_N157
HDMI_CRT_P157
CPU_DP1_CTRL_CLK57
CPU_DP1_CTRL_DATA57
HDMI_DATA0#57
HDMI_DATA057
HDMI_CLK#57
HDMI_CLK57
TPAD14-OP-GP
TPAD14-OP-GP
TP802
TP802
DDPD_CTRLDATA
1
EDP_COMP
HDMI/CRT
3D3V_S0
RN801
C C
RN801
2 3 1
SRN2K2J-1-GP
SRN2K2J-1-GP
CPU_DP1_CTRL_CLK CPU_DP1_CTRL_DATA
4
HDMI
Check
+VCCIO
R801
R801
1 2
24D9R2F-L-GP
24D9R2F-L-GP
E55
DDI1_TXN[0]
F55
DDI1_TXP[0]
E58
DDI1_TXN[1]
F58
DDI1_TXP[1]
F53
DDI1_TXN[2]
G53
DDI1_TXP[2]
F56
DDI1_TXN[3]
G56
DDI1_TXP[3]
C50
DDI2_TXN[0]
D50
DDI2_TXP[0]
C52
DDI2_TXN[1]
D52
DDI2_TXP[1]
A50
DDI2_TXN[2]
B50
DDI2_TXP[2]
D51
DDI2_TXN[3]
C51
DDI2_TXP[3]
L13
GPP_E18/DDPB_CTRLCLK
L12
GPP_E19/DDPB_CTRLDATA
N7
GPP_E20/DDPC_CTRLCLK
N8
GPP_E21/DDPC_CTRLDATA
N11
GPP_E22
N12
GPP_E23
E52
EDP_RCOMP
SKYLAKE-U-GP
SKYLAKE-U-GP
071.SKYLA.000U
071.SKYLA.000U
SKYLAKE_ULT
SKYLAKE_ULT
DDI
DDI
DISPLAY SIDEBANDS
DISPLAY SIDEBANDS
Strap
Strap
Strap
EDP
EDP
GPP_E13/DDPB_HPD0 GPP_E14/DDPC_HPD1 GPP_E15/DDPD_HPD2 GPP_E16/DDPE_HPD3
(#543016) The Skylake U/Y processor supports only two DDI ports - Port 1 and Port 2.
1 OF 20
EDP_TXN[0]
EDP_TXP[0]
EDP_TXN[1]
EDP_TXP[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]
EDP_AUXN EDP_AUXP
EDP_DISP_UTIL
DDI1_AUXN DDI1_AUXP DDI2_AUXN DDI2_AUXP
RSVD#G46
RSVD#F46
GPP_E17/EDP_HPD
EDP_BKLTEN
EDP_BKLTCTL
EDP_VDDEN
C47 C46 D46 C45 A45 B45 A47 B47
E45 F45
B52
G50 F50 E48 F48 G46 F46
L9 L7 L6 N9 L10
R12 R11 U13
EDP_DISP_UTIL
EC_SMI#
eDP_TX_ CPU_N0 55 eDP_TX_ CPU_P0 55 eDP_TX_ CPU_N1 55 eDP_TX_ CPU_P1 55
eDP_AUX _CPU_N 55 eDP_AUX _CPU_P 55
1
TP801 TPAD14-OP-GPTP801 TPAD14-OP-GP
CPU_DP1_HPD 57
EC_SMI# 24 EC_SCI# 24 EDP_HPD 55
L_BKLT_EN 55 L_BKLT_CTRL 55 EDP_VDD_EN 55
(#543016) eDP_RCOMP Guideline
Signal Trace
Width
eDP_RCOMP 20 mils 25 mils 24.9 ±1%
B B
(#543016) DDI Disabling and Termination Guidelines
Port Strap Enable Port Disable Port
Port 1
DDPB_CTRLDATA
Port 2
DDPC_CTRLDATA
A A
Design Guideline: Skylake processor signal eDP_RCOMP should be connected to the VCCIO rail via a single 24.9 ±1% resistor.
5
Isolation Spacing
PU to 3.3 V with 2.2-k ±5% resistor
PU to 3.3 V with 2.2-k ±5% resistor
Resistor Value
Length
Max = 100 mils
NC
NC
4
EC_SMI#
EC_SCI#
3
2
R804
R804
1 2
1 2
1 2
100KR2J-4-GP
100KR2J-4-GP
3D3V_S0
R802 10KR2J-3-GPR802 10KR2J-3-GP
R803 10KR2J-3-GP
R803 10KR2J-3-GP
DY
DY
L_BKLT_EN
BOM1
BOM1
BOM1
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3
Tuesday, July 21, 2015
Tuesday, July 21, 2015
Tuesday, July 21, 2015
Date: Sheet of
Date: Sheet of
Date: Sheet of
CPU_(DISPLAY)
CPU_(DISPLAY)
CPU_(DISPLAY)
Tesla SKL-U
Tesla SKL-U
Tesla SKL-U
8102
8102
8102
1
-1
-1
-1
5
4
3
2
1
Main Func = CPU
D D
C C
(Blanking)
B B
A A
5
4
3
2
BOM1
BOM1
BOM1
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3
Tuesday, July 21, 2015
Tuesday, July 21, 2015
Tuesday, July 21, 2015
Date: Sheet of
Date: Sheet of
Date: Sheet of
(Reserved)CPU
(Reserved)CPU
(Reserved)CPU
Tesla SKL-U
Tesla SKL-U
Tesla SKL-U
9102
9102
9102
1
-1
-1
-1
5
4
3
2
1
Main Func = CPU
(#543016 PDG)
CORE
U-line 23e 28W IccMax current-10ms max = 34 A
D D
VCC_CORE
PC1001
PC1001
12
PC1002
PC1002
PC1003
PC1003
12
12
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
PC1004
PC1004
12
PC1006
PC1006
PC1007
PC1007
PC1008
PC1005
PC1005
12
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
PC1008
PC1009
12
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
PC1009
12
12
12
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
1D35V_S3
PC1055SC10U6D3V3MX-GP PC1055SC10U6D3V3MX-GP
12
12
12
12
12
PC1056SC10U6D3V3MX-GP PC1056SC10U6D3V3MX-GP
PC1057SC10U6D3V3MX-GP PC1057SC10U6D3V3MX-GP
PC1058SC10U6D3V3MX-GP PC1058SC10U6D3V3MX-GP
12
PC1059SC10U6D3V3MX-GP PC1059SC10U6D3V3MX-GP
PC1060SC10U6D3V3MX-GP PC1060SC10U6D3V3MX-GP
12
PC1061
PC1061
SC1U10V2KX-L1-GP
PC1052
PC1052
12
SC1U10V2KX-L1-GP
PC1027
PC1027
12
PC1053
PC1053
12
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
PC1017
PC1011
PC1011
PC1010
PC1010
12
12
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
PC1022
PC1022
PC1021
PC1021
12
+VCCIO
12
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
C C
PC1012
PC1012
12
12
PC1023
PC1023
PC1014
PC1014
PC1013
PC1013
12
12
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
12
12
PC1028
PC1028
PC1024
PC1024
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC18P50V2JN-1-GP
SC18P50V2JN-1-GP
SC18P50V2JN-1-GP
SC18P50V2JN-1-GP
1D0V_S5
+VCCIO(ICCMAX.=2.73A)
PC1036
PC1036
12
12
12
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
PC1035SC22U6D3V3MX-1-GP PC1035SC22U6D3V3MX-1-GP
PC1037
PC1037
DY
DY
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
B B
SLICED GT
U-line 23e 28W IccMax current-10ms max[A] = 67 A
+VCCGT
PC1031
PC1031
12
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
PC1032
PC1032
12
PC1033
PC1033
12
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
12
12
PC1039SC22U6D3V3MX-1-GP PC1039SC22U6D3V3MX-1-GP
PC1038SC22U6D3V3MX-1-GP PC1038SC22U6D3V3MX-1-GP
PC1034
PC1034
PC1041
PC1041
PC1042
PC1042
12
12
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
12
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
PC1015
PC1015
12
DY
DY
12
PC1029
PC1029
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
PC1043
PC1043
12
PC1016
PC1016
12
DY
DY
12
PC1030
PC1030
PC1017
12
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
VCCSA
+VCCSA
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
PC1018
PC1018
12
PC1045
PC1045
12
PC1019
PC1019
PC1020
PC1020
12
12
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
PC1047
PC1047
PC1048
PC1046
PC1046
12
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
PC1048
12
12
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
PC1050
PC1050
PC1051
PC1049
PC1049
12
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
PC1051
12
12
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
12
12
12
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC1U10V2KX-L1-GP
SC1U10V2KX-L1-GP
SC1U10V2KX-L1-GP
SC1U10V2KX-L1-GP
SC1U10V2KX-L1-GP
SC1U10V2KX-L1-GP
PC1064
PC1064
PC1063
PC1063
PC1062
PC1062
PC1025
PC1025
PC1026
PC1026
12
12
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
PC1072
PC1072
PC1073
PC1073
PC1074
PC1074
PC1075
PC1075
PC1076
PC1076
PC1077
PC1077
PC1078
PC1078
PC1079
PC1044
PC1044
PC1069
PC1069
PC1070
PC1070
PC1071
PC1071
12
12
12
12
12
12
12
12
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
A A
PC1083
PC1083
PC1082
PC1082
PC1084
PC1084
PC1085
PC1085
12
12
12
12
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
DY
DY
5
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
PC1087
PC1087
PC1086
PC1086
12
12
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
DY
DY
12
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
PC1089
PC1089
PC1090
PC1090
12
12
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
PC1079
PC1080
PC1080
PC1081
12
12
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
DY
DY
PC1081
12
12
12
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
BOM1
BOM1
BOM1
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Numb er Rev
Size Document Numb er Rev
Size Document Numb er Rev A2
A2
A2
Tuesday, July 21, 2015
Tuesday, July 21, 2015
Tuesday, July 21, 2015 Date: Sheet of
Date: Sheet of
4
3
2
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
CPU_(Power CAP1)
CPU_(Power CAP1)
CPU_(Power CAP1)
Tesla SKL-U
Tesla SKL-U
Tesla SKL-U
1
10 102
10 102
10 102
-1
-1
-1
5
4
3
2
1
Main Func = CPU
+VCCGT
12
12
12
C1136
C1136
D D
C1138
C1138
SC18P50V2JN-1-GP
SC18P50V2JN-1-GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
12
C1147
C1147
12
12
C1148
C1148
C1149
C1149
C1150
C1150
SC1U10V2KX-1GP
SC1U10V2KX-1GP
1U 0402 x 6
SC18P50V2JN-1-GP
SC18P50V2JN-1-GP
SC18P50V2JN-1-GP
SC18P50V2JN-1-GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
UNSLICED GT
+VCCIO
+VCCIO(ICCMAX.=2.73A)
12
12
C1151
C1151
C1152
C1152
SC1U10V2KX-1GP
SC1U10V2KX-1GP
VCCIO
12
12
C1153
C1153
C1154
C1154
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
PCH DERIVED RAILS
1D0V_S5
R1114
R1114
1 2
0R0603-PAD
0R0603-PAD
C C
B B
+VCCCLK
+VCCPGPPA(ICCMAX.=0.05A)
+V1.8A +VCCPGPPA
R1111
R1111
1 2
DY
DY
0R3J-0-U-GP
3D3V_S5
0R3J-0-U-GP
R1109
R1109
1 2
0R0603-PAD
0R0603-PAD
R1116
R1116
1 2
0R0603-PAD
0R0603-PAD
+VCCPGPP
GTUS
+VCCGT
1D0V_S5
SC1U10V2KX-1GP
SC1U10V2KX-1GP
C1174
C1174
12
+V_VCCGTUS_VR can merge to +VCCGT
PC1104
PC1104
PC1105
PC1105
12
PC1107
PC1107
12
23e
23e
12
C1104
C1104
12
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
23e
23e
23e
23e
12
C1105
C1105
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
DY
DY
PC1106
PC1106
12
23e
23e
12
C1182
C1182
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC18P50V2JN-1-GP
SC18P50V2JN-1-GP
DY
DY
20141114 Alden
R1102
R1102
1 2
0R0603-PAD
0R0603-PAD
+VCCAMPHYPLL_1P01D0V_S5
C1172
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
C1181
C1181
12
C1172
SC1U10V2KX-1GP
SC1U10V2KX-1GP
12
VCC_CORE
12
12
12
C1102
C1102
C1101
C1101
C1103
C1103
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
A A
U-line 23e 28W IccMax current-10ms max = 34 A
SC1U10V2KX-1GP
5
12
12
C1116
C1116
C1117
C1117
SC1U10V2KX-1GP
SC1U10V2KX-1GP
1U 0402 x 5
SC1U10V2KX-1GP
SC1U10V2KX-1GP
4
3D3V_S5
+V1.8A
R1108
R1108
1 2
0R0603-PAD
0R0603-PAD
R1129
R1129
1 2
DY
DY
0R3J-0-U-GP
0R3J-0-U-GP
3
+VCCPGPPD_TCH
+VCCPGPPD_TCH
C1183
C1183
12
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
BOM1
BOM1
BOM1
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Numb er Rev
Size Document Numb er Rev
Size Document Numb er Rev A2
A2
A2
Tuesday, July 21, 2015
Tuesday, July 21, 2015
Tuesday, July 21, 2015 Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
CPU_(Power CAP2)
CPU_(Power CAP2)
CPU_(Power CAP2)
Tesla SKL-U
Tesla SKL-U
Tesla SKL-U
1
11 102
11 102
11 102
-1
-1
-1
5
4
3
2
1
Main Func = DDR SODIMM
D D
(Blanking)
C C
B B
A A
BOM1
BOM1
BOM1
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Numb er Rev
Size Document Numb er Rev
Size Document Numb er Rev A2
A2
A2
Tuesday, July 21, 2015
Tuesday, July 21, 2015
Tuesday, July 21, 2015 Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
DDR3-SODIMM1
DDR3-SODIMM1
DDR3-SODIMM1
Tesla SKL-U
Tesla SKL-U
Tesla SKL-U
1
12 102
12 102
12 102
-1
-1
-1
5
4
3
2
1
Main Func = DDR SODIMM
DIMM1
M_B_A[15:0]5
D D
M_B_BS25
M_B_BS05 M_B_BS15
M_B_DQ[63:0]5
M_B_DQ[8:15]
M_B_DQ[0:7]
M_B_DQ[16:23]
M_B_DQ[24:31]
M_B_DQ[32:39]
M_B_DQ[40:47]
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SC2D2U10V3KX-1GP
SC2D2U10V3KX-1GP
12
C1309
C1309
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
12
C1310
C1310
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
Layout Note:
Place these caps close to VREF_CA
Layout Note:
Place these caps close to VREF_DQ
M_VREF_CA_DIMMB
12
12
C1306
C1306
C1308
C1308
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
M_VREF_DQ_DIMMB
C C
12
12
C1302
C1302
C1305
C1305
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
M_B_DQ[48:55]
M_B_DQ[56:63]
M_B_DQS_DN[7:0]5
B B
Layout Note:
All VREF traces should have width=20mil; spacing=20 mil
M_B_DQS_DP[7:0]5
M_B_DIMB_ODT05 M_B_DIMB_ODT15
M_VREF_CA_DIMMB M_VREF_DQ_DIMMB
DDR3_DRAMRST#5
12
C1301
C1301 SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
DY
DY
M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15
0D675V_S0
M_B_DQ8 M_B_DQ12 M_B_DQ10 M_B_DQ11 M_B_DQ9 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ4 M_B_DQ0 M_B_DQ6 M_B_DQ3 M_B_DQ5 M_B_DQ1 M_B_DQ7 M_B_DQ2 M_B_DQ20 M_B_DQ19 M_B_DQ17 M_B_DQ22 M_B_DQ18 M_B_DQ21 M_B_DQ23 M_B_DQ16 M_B_DQ29 M_B_DQ24 M_B_DQ30 M_B_DQ31 M_B_DQ28 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ37 M_B_DQ36 M_B_DQ35 M_B_DQ39 M_B_DQ33 M_B_DQ32 M_B_DQ34 M_B_DQ38 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ45 M_B_DQ44 M_B_DQ47 M_B_DQ46 M_B_DQ49 M_B_DQ51 M_B_DQ50 M_B_DQ55 M_B_DQ52 M_B_DQ53 M_B_DQ48 M_B_DQ54 M_B_DQ56 M_B_DQ58 M_B_DQ60 M_B_DQ59 M_B_DQ57 M_B_DQ61 M_B_DQ62 M_B_DQ63
M_B_DQS_DN1 M_B_DQS_DN0 M_B_DQS_DN2 M_B_DQS_DN3 M_B_DQS_DN4 M_B_DQS_DN5 M_B_DQS_DN6 M_B_DQS_DN7
M_B_DQS_DP1 M_B_DQS_DP0 M_B_DQS_DP2 M_B_DQS_DP3 M_B_DQS_DP4 M_B_DQS_DP5 M_B_DQS_DP6 M_B_DQS_DP7
close to dimm
DIMM1
98
A0
97
A1
96
A2
95
A3
92
A4
91
A5
90
A6
86
A7
89
A8
85
A9
107
A10/AP
84
A11
83
A12
119
A13
80
A14
78
A15
79
A16/BA2
109
BA0
108
BA1
5
DQ0
7
DQ1
15
DQ2
17
DQ3
4
DQ4
6
DQ5
16
DQ6
18
DQ7
21
DQ8
23
DQ9
33
DQ10
35
DQ11
22
DQ12
24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68
70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194
10
27
45
62 135 152 169 186
12
29
47
64 137 154 171 188
116 120
126
1
30
203 204
VDDSPD DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19
NC#/TEST DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7#
DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7
ODT0 ODT1
VREF_CA VREF_DQ
RESET#
VTT1 VTT2
SKT_DDR 204P SMD
SKT_DDR 204P SMD
DDR3-204P-263-GP-U
DDR3-204P-263-GP-U
62.10024.S61
62.10024.S61
1ST = 62.10024.S61
1ST = 62.10024.S61
RAS#
CAS#
CS0# CS1#
CKE0 CKE1
CK0#
CK1#
EVENT#
NC#1 NC#2
VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8
VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18
NP1
NP1
NP2
NP2
110 113
WE#
115
114 121
73 74
101
CK0
103
102
CK1
104
11
DM0
28
DM1
46
DM2
63
DM3
136
DM4
153
DM5
170
DM6
187
DM7
200
SDA
202
SCL
198
199
SA0_DIMB
197
SA0
SA1_DIMB
201
SA1
77 122 125
75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124
2
VSS
3
VSS
8
VSS
9
VSS
13
VSS
14
VSS
19
VSS
20
VSS
25
VSS
26
VSS
31
VSS
32
VSS
37
VSS
38
VSS
43
VSS
44
VSS
48
VSS
49
VSS
54
VSS
55
VSS
60
VSS
61
VSS
65
VSS
66
VSS
71
VSS
72
VSS
127
VSS
128
VSS
133
VSS
134
VSS
138
VSS
139
VSS
144
VSS
145
VSS
150
VSS
151
VSS
155
VSS
156
VSS
161
VSS
162
VSS
167
VSS
168
VSS
172
VSS
173
VSS
178
VSS
179
VSS
184
VSS
185
VSS
189
VSS
190
VSS
195
VSS
196
VSS
205
VSS
206
VSS
1D35V_S3
M_B_RAS# 5 M_B_WE# 5 M_B_CAS# 5
M_B_CS#0 5 M_B_CS#1 5
M_B_CKE0 5 M_B_CKE1 5
M_B_CLK0 5 M_B_CLK#0 5
M_B_CLK1 5 M_B_CLK#1 5
PCH_SMBDATA 18,65 PCH_SMBCLK 18,65
3D3V_S0
12
C1311
C1311 SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
Layout Note:
Place these Caps near DIMM2.
0D675V_S0
12
C1307
C1307
1D35V_S3
SC1U10V2KX-1GP
SC1U10V2KX-1GP
12
SA1_DIMB
SA0_DIMB
C1304
C1304
SC1U10V2KX-1GP
SC1U10V2KX-1GP
12
3D3V_S0
12
C1303
C1303
12
R1302
R1302 10KR2J-3-GP
10KR2J-3-GP
12
R1301
R1301
Note: SO-DIMM B SPD Address is 0xA4
0R0402-PAD
0R0402-PAD
SO-DIMM B TS Address is 0x34
12
12
C1317
C1317
C1318
C1318
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
12
C1321
C1321
C1322
C1322
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
12
12
C1315
C1315
C1314
C1314
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
1U 0402 x 3
SC1U10V2KX-1GP
SC1U10V2KX-1GP
10U 0603 x 3
12
C1323
C1323
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
12
C1316
C1316
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
1U 0402 x 2
0.1U 0402 x 5
12
12
C1312
C1312
C1313
C1313
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
Place these Caps near DIMM2.
A A
5
4
3
AFTP1301AFTE14P-GP AFTP1301AFTE14P-GP
0D675V_S0
1
BOM1
BOM1
BOM1
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Numb er Rev
Size Document Numb er Rev
Size Document Numb er Rev A2
A2
A2
Tuesday, July 21, 2015
Tuesday, July 21, 2015
Tuesday, July 21, 2015 Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
DDR3-SODIMM2
DDR3-SODIMM2
DDR3-SODIMM2
Tesla SKL-U
Tesla SKL-U
Tesla SKL-U
1
13 102
13 102
13 102
-1
-1
-1
5
D D
4
3
2
1
C C
(Blanking)
B B
BOM1
BOM1
BOM1
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A4
A4
A4
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
(Reserved)SODIMM3_SODIMM4
(Reserved)SODIMM3_SODIMM4
(Reserved)SODIMM3_SODIMM4
Tesla SKL-U
Tesla SKL-U
Tuesday, July 21, 2015
Tuesday, July 21, 2015
Tuesday, July 21, 2015
2
Tesla SKL-U
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
-1
-1
14 102
14 102
14 102
1
-1
5
4
3
2
1
Main Func = PCH
9 OF 20
CPU1I
CPU1I
CSI-2
CSI-2
A36
CSI2_DN0
B36
CSI2_DP0
D D
C C
C38
CSI2_DN1
D38
CSI2_DP1
C36
CSI2_DN2
D36
CSI2_DP2
A38
CSI2_DN3
B38
CSI2_DP3
C31
CSI2_DN4
D31
CSI2_DP4
C33
CSI2_DN5
D33
CSI2_DP5
A31
CSI2_DN6
B31
CSI2_DP6
A33
CSI2_DN7
B33
CSI2_DP7
A29
CSI2_DN8
B29
CSI2_DP8
C28
CSI2_DN9
D28
CSI2_DP9
A27
CSI2_DN10
B27
CSI2_DP10
C27
CSI2_DN11
D27
CSI2_DP11
SKYLAKE-U-GP
SKYLAKE-U-GP
071.SKYLA.000U
071.SKYLA.000U
SKYLAKE_ULT
SKYLAKE_ULT
GPP_F13/EMMC_DATA0 GPP_F14/EMMC_DATA1 GPP_F15/EMMC_DATA2 GPP_F16/EMMC_DATA3 GPP_F17/EMMC_DATA4 GPP_F18/EMMC_DATA5 GPP_F19/EMMC_DATA6 GPP_F20/EMMC_DATA7
GPP_F21/EMMC_RCLK
9 OF 20
CSI2_CLKN0
CSI2_CLKP0
CSI2_CLKN1
CSI2_CLKP1
CSI2_CLKN2
CSI2_CLKP2
CSI2_CLKN3
CSI2_CLKP3
CSI2_COMP
GPP_D4/FLASHTRIG
EMMC
EMMC
GPP_F22/EMMC_CLK
GPP_F12/EMMC_CMD
EMMC_RCOMP
C37 D37 C32 D32 C29
DC resistance < 0.5ohm.
D29 B26 A26
CSI2_COMP
E13 B7
AP2 AP1 AP3
GPP_F: VCCPGPPF = 1.8V Only
AN3 AN1 AN2 AM4 AM1
AM2 AM3 AP4
EMMC_RCOMP
AT1
1 2
R1501
R1501
1 2
100R2F-L1-GP-U
100R2F-L1-GP-U
R1502
R1502
200R2F-L-GP
200R2F-L-GP
[#545659 Rev0.7]
B B
A A
5
4
3
2
BOM1
BOM1
BOM1
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CPU_(CS-2/EMMC)
CPU_(CS-2/EMMC)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3
Tuesday, July 21, 2015
Tuesday, July 21, 2015
Tuesday, July 21, 2015
Date: Sheet of
Date: Sheet of
Date: Sheet of
CPU_(CS-2/EMMC)
Tesla SKL-U
Tesla SKL-U
Tesla SKL-U
15 102
15 102
15 102
1
-1
-1
-1
Main Func = PCH
#543016: 220 nF nominal capacitors are recommended for Gen 3. 100 nF nominal capacitors are recommended for Gen 2.
GPU
D D
WLAN
LAN
HDD
Layout Note:
XDP_PRE Q#99
12
PESD5V0U1BL-GP-U1
PESD5V0U1BL-GP-U1
C C
PCIE Table
Port
1
2
3
4
5(L0~L3)
6(L3)
6(L2)
6(L0~L1)
5
PEG_RX_CPU_N076 PEG_RX_CPU_P076 PEG_TX_GPU_N076 PEG_TX_GPU_P076
PEG_RX_CPU_N176 PEG_RX_CPU_P176 PEG_TX_GPU_N176 PEG_TX_GPU_P176
PEG_RX_CPU_N276 PEG_RX_CPU_P276 PEG_TX_GPU_N276 PEG_TX_GPU_P276
PEG_RX_CPU_N376 PEG_RX_CPU_P376 PEG_TX_GPU_N376 PEG_TX_GPU_P376
PCIE_RX_CPU_N561 PCIE_RX_CPU_P561 PCIE_TX_CON_N561 PCIE_TX_CON_P561
PCIE_RX_CPU_N631 PCIE_RX_CPU_P631 PCIE_TX_CON_N631 PCIE_TX_CON_P631
SATA_RX_CPU_N060 SATA_RX_CPU_P060 SATA_TX_CPU_N060 SATA_TX_CPU_P060
1. Trace Width: 4 mils min (breakout) 12-15 mils (trace) Note: Must maintain low DC resistance routing (<0.1 ohm).
2. Isolation Spacing: At least 12 mils to any adjacent high speed I/O.
XDP_PRD Y#99
DY
DY
ED1602
ED1602
Device
N/A
N/A
WLAN
LAN
GPU
HDD
N/A SATA1
N/A
3D3V_S0
R1604
R1604
C1606
C1606 C1605
C1605
C1608
C1608 C1607
C1607
C1610
C1610 C1609
C1609
C1612
C1612 C1611
C1611
C1601
C1601 C1602
C1602
C1603
C1603 C1604
C1604
1 2
100R2F-L1-GP-U
100R2F-L1-GP-U
Share BUS
USB3.0_3
USB3.0_4
SATA0
1 2 1 2
1 2 1 2
1 2 1 2
1 2 1 2
1 2 1 2
1 2 1 2
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
OPS
OPS OPS
OPS
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
OPS
OPS OPS
OPS
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
OPS
OPS OPS
OPS
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
OPS
OPS OPS
OPS
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
PEG_TX_CPU_N0 PEG_TX_CPU_P0
PEG_TX_CPU_N1 PEG_TX_CPU_P1
PEG_TX_CPU_N2 PEG_TX_CPU_P2
PEG_TX_CPU_N3 PEG_TX_CPU_P3
PCIE_TX_CPU_N5 PCIE_TX_CPU_P5
PCIE_TX_CPU_N6 PCIE_TX_CPU_P6
PCIE_RCOMPN PCIE_RCOMPP
R160710KR2J-3-GP R160710KR2J-3-GP
12
USB 2.0 Table
Pair
0
1
2
3
4
5
6
7
CPU1H
CPU1H
PCIE/USB3/SATA
PCIE/USB3/SATA
H13
PCIE1_RXN/USB3_5_RXN
G13
PCIE1_RXP/USB3_5_RXP
B17
PCIE1_TXN/USB3_5_TXN
A17
PCIE1_TXP/USB3_5_TXP
G11
PCIE2_RXN/USB3_6_RXN
F11
PCIE2_RXP/USB3_6_RXP
D16
PCIE2_TXN/USB3_6_TXN
C16
PCIE2_TXP/USB3_6_TXP
H16
PCIE3_RXN
G16
PCIE3_RXP
D17
PCIE3_TXN
C17
PCIE3_TXP
G15
PCIE4_RXN
F15
PCIE4_RXP
B19
PCIE4_TXN
A19
PCIE4_TXP
F16
PCIE5_RXN
E16
PCIE5_RXP
C19
PCIE5_TXN
D19
PCIE5_TXP
G18
PCIE6_RXN
F18
PCIE6_RXP
D20
PCIE6_TXN
C20
PCIE6_TXP
F20
PCIE7_RXN/SATA0_RXN
E20
PCIE7_RXP/SATA0_RXP
B21
PCIE7_TXN/SATA0_TXN
A21
PCIE7_TXP/SATA0_TXP
G21
PCIE8_RXN/SATA1A_RXN
F21
PCIE8_RXP/SATA1A_RXP
D21
PCIE8_TXN/SATA1A_TXN
C21
PCIE8_TXP/SATA1A_TXP
E22
PCIE9_RXN
E23
PCIE9_RXP
B23
PCIE9_TXN
A23
PCIE9_TXP
F25
PCIE10_RXN
E25
PCIE10_RXP
D23
PCIE10_TXN
C23
PCIE10_TXP
F5
PCIE_RCOMPN
E5
PCIE_RCOMPP
D56
PROC_PRDY#
D61
PROC_PREQ#
PIRQA#
BB11
GPP_A7/PIRQA#
E28
PCIE11_RXN/SATA1B_RXN
E27
PCIE11_RXP/SATA1B_RXP
D24
PCIE11_TXN/SATA1B_TXN
C24
PCIE11_TXP/SATA1B_TXP
E30
PCIE12_RXN/SATA2_RXN
F30
PCIE12_RXP/SATA2_RXP
A25
PCIE12_TXN/SATA2_TXN
B25
PCIE12_TXP/SATA2_TXP
SKYLAKE-U-GP
SKYLAKE-U-GP
071.SKYLA.000U
071.SKYLA.000U
Device
USB3.0 port1 (Debug Port)
USB2.0 Port2
USB2.0 Port3 (IOBD)
X
CAMERA
Card Reader
Touch Panel
Bluetooth
SKYLAKE_ULT
SKYLAKE_ULT
4
SSIC / USB3
SSIC / USB3
USB3_2_ RXN/SSI C_RXN USB3_2_ RXP/SS IC_RX P USB3_2_ TXN/SSI C_TXN USB3_2_ TXP/SS IC_TX P
USB2
USB2
USB2_VB USSENSE
GPP_E9/USB2_OC0# GPP_E10/USB2_OC1# GPP_E11/USB2_OC2# GPP_E12/USB2_OC3#
GPP_E4/DEVSLP0 GPP_E5/DEVSLP1 GPP_E6/DEVSLP2
GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2
GPP_E8/SATALED#
8 OF 20
8 OF 20
H8
USB3_1_ RXN
G8
USB3_1_ RXP
C13
USB3_1_ TXN
D13
USB3_1_ TXP
J6 H6 B13 A13
J10
USB3_3_ RXN
H10
USB3_3_ RXP
B15
USB3_3_ TXN
A15
USB3_3_ TXP
E10
USB3_4_ RXN
F10
USB3_4_ RXP
C15
USB3_4_ TXN
D15
USB3_4_ TXP
AB9
USB2N_1
AB10
USB2P_1
AD6
USB2N_2
AD7
USB2P_2
AH3
USB2N_3
AJ3
USB2P_3
USB_CPU_PN3
AD9
USB2N_4
USB_CPU_PP3
AD10
USB2P_4
AJ1
USB2N_5
AJ2
USB2P_5
AF6
USB2N_6
AF7
USB2P_6
AH1
USB2N_7
AH2
USB2P_7
AF8
USB2N_8
AF9
USB2P_8
AG1
USB2N_9
AG2
USB2P_9
DC resistance < 0.5ohm.
AH7
USB2N_10
AH8
USB2P_1 0
USBCOMP
AB6
USB2_CO MP
AG3
USB2_ID
AG4
A9
USB_OC1#
C9
USB_OC2#
D9 B9
J1 J2
SATA_ODD_DA#
J3
GPP_E0/SATAXPCIE0/SATAGP0
H2
SATA_ODD_PRSNT#
H3
GPP_E2/SATAXPCIE2/SATAGP2
G4
SATA_LED# USB_OC2#
H1
(#543016) Unused SATAGP[2:0]/GPP_E[2:0] pins must be terminated to either 3.3 V rail or GND using 8.2 K to 10 K on the motherboard. Do not use both pull-up and pull-down. Either pull-up or pull-down is acceptable.
USB30_RX_CPU_N1 34 USB30_RX_CPU_P1 34 USB30_TX_CPU_N1 34 USB30_TX_CPU_P1 34
USB30_RX_CPU_N2 36 USB30_RX_CPU_P2 36 USB30_TX_CPU_N2 36 USB30_TX_CPU_P2 36
USB30_RX_CPU_N4 66 USB30_RX_CPU_P4 66 USB30_TX_CPU_N4 66 USB30_TX_CPU_P4 66
USB_CPU_PN0 34 USB_CPU_PP0 34
USB_CPU_PN1 36 USB_CPU_PP1 36
USB_CPU_PN2 66 USB_CPU_PP2 66
1
TP1601 TPAD14-OP-GPTP1601 TPAD14-OP-GP
1
TP1602 TPAD14-OP-GPTP1602 TPAD14-OP-GP
USB_CPU_PN4 55 USB_CPU_PP4 55
USB_CPU_PN6 55 USB_CPU_PP6 55
USB_CPU_PN7 61 USB_CPU_PP7 61
R1603 113R2F-GPR1603 113R2F-GP
1 2
USB_OC0# 34 USB_OC1# 36 USB_OC2# 66
NFC_IRQ 90
NFC_RST 90 DEVSLP1_HDD_CON 60
GPP_E2/SATAXPCIE2/SATAGP2 SATA_ODD_PRSNT# SATA_LED# GPP_E0/SATAXPCIE0/SATAGP0
USB1 (USB3.0 Port1)
USB2 (USB3.0 Port2)
Card Reader (USB3.0 Port3)
USB1 (USB2.0 port1)
USB2 (USB2.0 Port2)
USB3 (IO BD/USB2.0 Port3)
CAMERA (USB2.0 Port5)
Touch Panel (USB2.0 Port7)
Bluetooth (USB2.0 Port8)
Unused SATA[3:0]GP pins must be terminated to either
3.3V rail or GND using 8.2K to 10K on the motherboard. Either pull-up or pull-down is acceptable.
(#543016) When used as DEVSLP, no external pull-up or pull-down termination required from SATA Host DEVSLP.
3D3V_S0
RN803
RN803
1
8
2
7
3456
SRN10KJ-6-GP
SRN10KJ-6-GP
3
(#545659) The xHCI controller supports USB Debug port on all USB3.0 capable ports.
3D3V_S0
R1608
R1608
SATA_ODD_DA#
USB_OC0# USB_OC1#
10KR2J-3-GP
10KR2J-3-GP
8 7
12
RN802
RN802
SRN10KJ-6-GP
SRN10KJ-6-GP
1 2 3456
3D3V_S5_PCH
DEVSLP1_HDD_CON
R1610
R1610
DY
DY
10KR2J-3-GP
10KR2J-3-GP
12
3D3V_S0
2
1
#545659 (SKL_PCH_U_Y_EDS Rev0.7)
B B
A A
BOM1
BOM1
BOM1
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A1
A1
A1
Tuesday, July 21, 2015
Tuesday, July 21, 2015
Tuesday, July 21, 2015
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
1
Wist ron C orpor ation
Wist ron C orpor ation
Wist ron C orpor ation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
CPU_(PCIE/SATA/USB)
CPU_(PCIE/SATA/USB)
CPU_(PCIE/SATA/USB)
Tesla SKL-U
Tesla SKL-U
Tesla SKL-U
16 102
16 102
16 102
-1
-1
-1
5
4
3
2
1
Main Func = PCH
3D3V_S5
R1709
R1709
1 2
10KR2J-3-GP
10KR2J-3-GP
RN1701
RN1701
2 3 1
SRN10KJ-5-GP
SRN10KJ-5-GP
R1723
R1723
D D
C C
1 2
10KR2J-3-GP
10KR2J-3-GP
RTC_AUX_S5
1 2
R1730 1MR2J-1-GPR1730 1MR2J-1-GP
R1733 10KR2J-3-GPR1733 10KR2J-3-GP
1 2
PESD5V0U1BL-GP-U1
PESD5V0U1BL-GP-U1
1 2
R1732 8K2R2F-1-GPR1732 8K2R2F-1-GP
R1717 10KR2J-3-GP
R1717 10KR2J-3-GP
ED1701
ED1701
DY
DY
AC_PRESENT
SIO_PWRBTN#
PCH_WAKE#
4
R1713
R1713
PCH_PLTRST#
1 2
0R0402-PAD
0R0402-PAD
12
12
C1701
C1701 SC220P50V2KX-3GP
SC220P50V2KX-3GP
DY
DY
CPU1K
CPU1K
SYSTEM POWER MANAGEMENT
SYSTEM POWER MANAGEMENT
AN10
GPP_B13/PLTRST#
B5
SYS_RESET#
AY17
RSMRST#
A68
PROCPWRGD
B65
VCCST_PWRGD
B6
SYS_PWROK
BA20
PCH_PWROK
BB20
DSW_PWROK
AR13
GPP_A13/SUSWARN#/SUSPWRDN ACK
AP11
GPP_A15/SUSACK#
BB15
WAKE#
AM15
GPD2/LAN_WAKE#
AW17
GPD11/LANPHYPC
AT15
GPD7/RSVD#AT15
SKYLAKE-U-GP
SKYLAKE-U-GP
071.SKYLA.000U
071.SKYLA.000U
3D3V_S5
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
C1702
C1702
+VCCST_CPU
12
5
VCC
4
12
R1719
R1719 47KR2F-GP
47KR2F-GP
DY
DY
11 OF 20
11 OF 20
GPP_B11/EXT_PWR_GATE#
H_VCCST_PWRGD_R
GPP_B12/SLP_S0#
GPD4/SLP_S3# GPD5/SLP_S4#
GPD10/SLP_S5#
SLP_SUS#
SLP_LAN#
GPD9/SLP_WLAN#
GPD6/SLP_A#
GPD3/PWRBTN#
GPD1/ACPRESENT
GPD0/BATLOW#
GPP_A11/PME#
INTRUDER#
GPP_B2/VRALERT#
SKYLAKE_ULT
SKYLAKE_ULT
Dis-wire with XDP_PM_RSMRST_PWRGD_XDP
12
R1722
R1722 1KR2J-1-GP
1KR2J-1-GP
EC1708
EC1708
12
DY
DY
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
AT11 AP15 BA16
SIO_SLP_S5#
AY16
AN15
SLP_LAN#
AW15
GPD9/SLP_WLAN#
BB17
SIO_SLP_A#
AN16
BA15
AC_PRESENT
AY15
PCH_BATLOW#
AU13
PME#
AU11
SM_INTRUDER#
AP16
EXT_PWR_GATE#
AM10
GPP_B2/VRALERT#
AM11
VCCST_PWRGD / HWM201:
12
12
DY
DY
PCH_BATLOW#
SM_INTRUDER#
PM_PCH_PWROK
PM_PCH_PWROK
SYS_PWROK
PM_RSMRST#
#544669 Rev0.52 CRB: No PL resistor on THERMTRIP#.
H_CPUPWRGD
1
AFTP1702
AFTP1702 AFTE14P-GP
AFTE14P-GP
12
12
ED1703
ED1703
DY
DY
PESD5V0U1BL-GP-U1
PESD5V0U1BL-GP-U1
R405
R405 10KR2J-3-GP
10KR2J-3-GP
ME_SUS_PWR_ACK_R20,24
PCH_WAKE#24,31
PESD5V0U1BL-GP-U1
PESD5V0U1BL-GP-U1
H_THERMTRIP_EN40
SYS_PWROK24 PCH_PWROK40
3D3V_S5
3D3V_S5
3D3V_S0
12
R1711
R1711
10KR2J-3-GP
10KR2J-3-GP
ED1704
ED1704
12
H_VCCST_PWRGD_R
(PDG#543016) WAKE#: Ensure that WAKE# signal Trise (Maximum) is <100 ns.
12
R1701
R1701 3KR2J-2-GP
3KR2J-2-GP
DY
DY
DY
R4110R2J- 2-GPDYR4110R2J- 2-GP
1 2
1 2
R1706 0R0402-PADR1706 0R0402-PAD
1 2
R1704 0R0402-PADR1704 0R0402-PAD
1 2
R1707 10KR2J-3-GPR1707 10KR2J-3-GP
1 2
ALL_SYS_PWRGD24,40
60D4R2F-GP
60D4R2F-GP R1734
R1734
DY
DY
PLT_RST#24,31,40,61,68,79
PCH_PLTRST# XDP_DBRESET# PM_RSMRST#
H_CPUPWRGD H_VCCST_PWRGD
SYS_PWROK PM_PCH_PWROK PCH_DPWROKPM_RSMRST#
ME_SUS_PWR_ ACK_R SUSACK#_R
PCH_WAKE# GPD2/LAN_WAKE#
12
EC1709
EC1709 SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
R1715
R1715
47KR2J-2-GP
47KR2J-2-GP
U1701
U1701
1
NC#1
2
A
GND3Y
74LVC1G07GW-G P
74LVC1G07GW-G P
73.01G07.0HG
73.01G07.0HG
1 2
DY
DY
R1716
R1716 100KR2F-L1-GP
100KR2F-L1-GP
SIO_SLP_S3#
[#543016 Rev0.7] EXT_PWR_GATE#: Due to a bug on A0, a temporary pull-up resistor will be required to overcome the internal 20k pull-down that is active during the early portion of the power up sequence
1
1 1 1
1
1
AFTP1701
AFTP1701
1
TPAD14-OP-GP
TPAD14-OP-GP
SIO_SLP_S0# 40 SIO_SLP_S3# 24,40,51,52,54
SIO_SLP_S4# 24,40,51
TP1703 TPAD14-OP-GPTP1703 TPAD14-OP-GP
SIO_SLP_SUS# 40,41,53,54
TP1704 TPAD14-OP-GPTP1704 TPAD14-OP-GP TP1705 TPAD14-OP-GPTP1705 TPAD14-OP-GP TP1706 TPAD14-OP-GPTP1706 TPAD14-OP-GP
SIO_PWRBTN# 24
AC_PRESENT 24
TP1707 TPAD14-OP-GPTP1707 TPAD14-OP-GP
TP1708 TPAD14-OP-GPTP1708 TPAD14-OP-GP
3D3V_S5
R1731
EXT_PWR_GATE#
BATLOW#: Pull-up required even if not implemented.
R1731
20KR2J-L2-GP
20KR2J-L2-GP
12
#543016 Rev0.7
1. VCCST_PWRGD is only 1.0 V tolerant.
B B
XDP_DBRESET#
SYS_PWROK PLT_RST# PCH_PWROK
SUSACK#_RME_SUS_PWR_ACK_R
PM_RSMRST#
3V_5V_POK_C
2345
1
DS3 BOM Option
PCH_DPWROK
R1718 0R2J-2-GP
R1718 0R2J-2-GP
1KR2J-1-GP
1KR2J-1-GP R1702
R1702
1 2
R1728
R1728
1 2
0R0402-PAD
0R0402-PAD
DS3
DS3
1 2
SIO_SLP_SUS#
R1729
R1729 0R2J-2-GP
0R2J-2-GP
1 2
DS3
DS3
EC1711
EC1711
DS3
DS3
R1725
R1725 100KR2F-L1-GP
100KR2F-L1-GP
1 2
12
DY
DY
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
3V_5V_POK 45,54
EC1712
EC1712
12
DY
DY
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
4
KBC_DPWROK 24
PCH_RSMRST# 24
12
12
DY
DY
DY
DY
EC1702
EC1702
EC1703
EC1706
EC1706
3
EC1703
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
12
12
DY
DY
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
EC1704
EC1704
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
DY
DY
12
ED1702
ED1702 PESD5V0U1BL-GP-U1
PESD5V0U1BL-GP-U1
DY
DY
DY
DY
R1708
R1708
1 2
0R2J-2-GP
0R2J-2-GP
3D3V_AUX_S5
A A
1 2
R1726
R1726 10KR2J-3-GP
10KR2J-3-GP
3V_5V_POK#
R1727
R1727
100KR2J-1-GP
100KR2J-1-GP
1 2
NON DS3
NON DS3
6
84.2N702.A3F
84.2N702.A3F
2nd = 84.2N702.E3F
2nd = 84.2N702.E3F
3rd = 75.00601.07C
3rd = 75.00601.07C
4th = 84.DMN66.03F
4th = 84.DMN66.03F
5
Q1701
Q1701
2N7002KDW-G P
2N7002KDW-G P
2. VCCST_PWRGD must go low during Sx pwr states, regardless of the voltage level of VCCST
BOM1
BOM1
BOM1
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CPU_(POWER MANAGEMENT)
CPU_(POWER MANAGEMENT)
CPU_(POWER MANAGEMENT)
Size Document Numb er Rev
Size Document Numb er Rev
Size Document Numb er Rev A2
A2
A2
Monday, July 27, 2015
Monday, July 27, 2015
Monday, July 27, 2015 Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
Tesla SKL-U
Tesla SKL-U
Tesla SKL-U
1
17 102
17 102
17 102
-1
-1
-1
3D3V_S5
SIO_RCIN#
INT_S ERIRQ
5
12
DY
DY
12
PCH strap pin:
eSPI or LPC
SML0ALERT# / GPP_C5
This signal h as a weak internal pull- down.
R1835
R1835 1KR2J-1-GP
1KR2J-1-GP
SPI_HOLD_CPU
R1836
R1836 1KR2J-1-GP
1KR2J-1-GP
SPI_CS0#_R24,25
CL_CLK61 CL_DATA61
Sampled at rising edge of RSMRST#
This signal h as a weak internal pull- down. 0 = LPC Is selected for EC. 1 = eSPI Is selected for EC.
Resister value will check later
SPI_CLK_R24,25
SPI_SO_R24,25
SPI_SI0_R24,25 SPI0_WP#25 SPI_HOLD_0#25
CL_RST#61
SIO_RCIN#24
INT_S ERIRQ24
PLACE WITHIN 1.1 INCH OF PCH
R18060R0402-PAD R18060R0402-P AD
1 2
R18070R0402-PAD R18070R0402-P AD
1 2
R18080R0402-PAD R18080R0402-P AD
1 2
R18090R0402-PAD R18090R0402-P AD
1 2
R18110R0402-PAD R18110R0402-P AD
1 2
R18120R0402-PAD R18120R0402-P AD
1 2
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
12
EC1805
EC1805
DY
DY
Main Func = PCH
D D
3D3V_S5
12
R1834
R1834 1KR2J-1-GP
1KR2J-1-GP
DY
DY
SPI_WP_CPU
3D3V_S0
R2021
R2021
1 2
10KR2J-3-GP
10KR2J-3-GP
R2032
R2032
1 2
10KR2J-3-GP
10KR2J-3-GP
SERIRQ PH: PDG: 8.2k CRB: 10k
C C
RCIN#: Frequency to Avoid: 33 MHz
4
PCH Prim
3D3V_S5_PCH
12
R1822
R1822
DY
DY
1KR2J-1-GP
1KR2J-1-GP
GPP_C5/SML0ALERT#
DY
DY
12
R1823
R1823 1KR2J-1-GP
1KR2J-1-GP
(#543016)Optional, can be left as OPEN/No-Connect.
CPU1E
CPU1E
SPI - FLASH
SPI_CLK_CPU SPI_SO_CPU SPI_SI_CPU SPI_WP_CPU SPI_HOLD_CPU SPI_CS_CPU_N0
TP1801TPAD14-OP-GP TP1801TPAD14-OP-GP TP1802TPAD14-OP-GP TP1802TPAD14-OP-GP TP1803TPAD14-OP-GP TP1803TPAD14-OP-GP TP1804TPAD14-OP-GP TP1804TPAD14-OP-GP TP1805TPAD14-OP-GP TP1805TPAD14-OP-GP TP1806TPAD14-OP-GP TP1806TPAD14-OP-GP
1 1 1 1 1 1
CPU_D1_TP CPU_D2_TP CPU_D3_TP CPU_D4_TP CPU_D5_TP CPU_D6_TP
AV2
SPI0_CLK
AW3
SPI0_MISO
AV3
SPI0_MOSI
AW2
SPI0_IO2
AU4
SPI0_IO3
AU3
SPI0_CS0#
AU2
SPI0_CS1#
AU1
SPI0_CS2#
M2
GPP_D1/SPI1_CLK
M3
GPP_D2/SPI1_MISO
J4
GPP_D3/SPI1_MOSI
V1
GPP_D21/SPI1_IO2
V2
GPP_D22/SPI1_IO3
M1
GPP_D0/SPI1_CS#
G3
CL_CLK
G2
CL_DATA
G1
CL_RST#
AW13
GPP_A0/RCIN#
AY11
GPP_A6/SERIRQ
SKYLAKE-U-GP
SKYLAKE-U-GP
071.SKYLA.000U
071.SKYLA.000U
SPI - FLASH
SPI - TOUCH
SPI - TOUCH
C LINK
C LINK
Strap
PCH strap pin:
BOOT HAL T
SPI0_MOSI
This signal h as a weak internal pull- up.
0 = ENABLED 1 = DISABLED WEAK INTERNAL PU
SKYLAKE_ULT
SKYLAKE_ULT
LPC
LPC
SMBUS, SMLINK
SMBUS, SMLINK
GPP_A14/SUS_STAT#/ESPI_RESET#
3
5 OF 20
5 OF 20
GPP_C0/SMBCLK
GPP_C1/SMBDATA
GPP_C2/SMBALERT#
GPP_C3/SML0CLK
GPP_C4/SML0DATA
Strap
GPP_C5/SML0ALERT#
GPP_C6/SML1CLK
GPP_C7/SML1DATA
GPP_B23/SML1ALERT#/PCHHOT#
GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3
GPP_A5/LFRAME#/ESPI_CS#
GPP_A9/CLKOUT_LPC0/ESPI_CLK
GPP_A10/CLKOUT_LPC1
GPP_A8/CLKRUN#
SPI_SI_CPU
R7 R8 R10
R9 W2 W1
W3 V3 AM7
AY13 BA13 BB13 AY12 BA12 BA11
AW9 AY9 AW11
PCH Prim
LPC_AD024,68 LPC_AD224,68 LPC_AD124,68 LPC_AD324,68
MEM_SMBCLK MEM_SMBDATA GPP_C2/SMBALERT#
SML0_CLK SML0_DATA GPP_C5/SML0ALERT#
SML1_SMBCLK SML1_SMBDATA SENSOR_HUB_INT#
LPC_LAD0_R LPC_LAD1_R LPC_LAD2_R LPC_LAD3_R LPC_LFRAME#_R SUS_STAT#/LPCPD#
PCI_CLK_LPC0 PCI_CLK_LPC1 CLKRUN#_R
3D3V_S5
12
R1824
R1824
DY
DY
1KR2J-1-GP
1KR2J-1-GP
12
R1825
R1825
DY
DY
1KR2J-1-GP
1KR2J-1-GP
LPC_AD0
LPC_AD1 LPC_AD3
SML1_SMBCLK 24,26,66,79,90 SML1_SMBDATA 24,26,66,79,90
SENSOR_HUB_INT# 24
R1801
R1801
0R0402-PAD
0R0402-PAD
R1819
R1819
1 2
0R0402-PAD
0R0402-PAD
8 7 6
20140820 DAIVD
12
RN1806
RN1806
SRN0J-7-GP-U
SRN0J-7-GP-U
LPC_LAD0_R
1
LPC_LAD2_RLPC_AD2
2
LPC_LAD1_R
3
LPC_LAD3_R
45
SUS_STAT#/LPCPD#
CLKRUN#_R
LPC_FRAME# 24,68
PM_CLKRUN#_EC_R 24
2
R1814
R1814
DY
DY
10KR2J-3-GP
10KR2J-3-GP
R1818
R1818
8K2R2F-1-GP
8K2R2F-1-GP
1 2
3D3V_S5_PCH
12
3D3V_S0
R1820 22R2J-2-GPR1820 22R2J-2-GP R1804 22R2J-2-GPR1804 22R2J-2-GP
1 2 1 2
TP1810
TP1810
TPAD14-OP-GP
TPAD14-OP-GP
TP1809
TP1809
TPAD14-OP-GP
TPAD14-OP-GP
SML1_SMBDATA SML1_SMBCLK SML0_DATA SML0_CLK
SENSOR_HUB_INT#
GPP_C2/SMBALERT#
MEM_SMBCLK MEM_SMBDATA
add Circuit for NFC
3D3V_S0
SML0_DATA
1
SML0_CLK
1
RN1807
RN1807
8 7 6
SRN2K2J-4-GP
SRN2K2J-4-GP
1 2
10KR2J-3-GP
10KR2J-3-GP
1 2
10KR2J-3-GP
10KR2J-3-GP
DY
DY
RN1811
RN1811
4
SRN2K2J-1-GP
SRN2K2J-1-GP
RN1812
RN1812
2 3 1
4
NFC
NFC
SRN1KJ-7-GP
SRN1KJ-7-GP
Q1802
Q1802
1
6
2345
2N7002KDW-G P
2N7002KDW-G P
84.2N702.A3F
84.2N702.A3F
2nd = 84.DM601.03F
2nd = 84.DM601.03F
NFC
NFC
CLK_PCI_KBC 24 CLK_PCI_DB 68
R1826
R1826
R1827
R1827
1
3D3V_S5_PCH
1 2 3 45
1 23
PCH_SML0_DATA 90
PCH_SML0_CLK 90
3D3V_S0
RN1810
RN1810
23
3D3V_S0
1
4
SRN10KJ-5-GP
CLOCK SIGNALS
CLOCK SIGNALS
SKYLAKE_ULT
SKYLAKE_ULT
SRN10KJ-5-GP
PCH_SMBDATA 13,65
PCH_SMBCLK 13,65
10 OF 20
10 OF 20
CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P
GPD8/SUSCLK
XTAL24_IN
XTAL24_OUT
XCLK_BIASREF
RTCX1 RTCX2
SRTCRST#
RTCRST#
F43 E43
BA17
E37 E35
E42
AM18 AM20
AN18 AM16
3
C1804
C1804
SC4P50V2CN-GP
SC4P50V2CN-GP
SUSCLK_R
XTAL24_IN XTAL24_OUT
XCLK_BIASREF
RTC_X1 RTC_X2
SRTC_RST#
RTC_RST#
DY
DY
12
ED1802
ED1802
PESD5V0U1BL-GP-U1
PESD5V0U1BL-GP-U1
1 2
R1815 10MR2J-L-GPR1815 10MR2J-L-GP
X1802
X1802
2 3
1 2
XTAL-32D768KHZ-67-GP
XTAL-32D768KHZ-67-GP
82.30001.G11
82.30001.G11
R1813
R1813
1 2
0R0402-PAD
0R0402-PAD
R1803
R1803
1 2
2K7R2F-GP
2K7R2F-GP
Intel recommend: 2.71k ohm 5%
RTCRST_ON24
41
1D0V_S5
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
EC1808
EC1808
DY
DY
10KR2J-3-GP
10KR2J-3-GP
DY
DY
12
RTC_X1
RTC_X2
C1803
C1803
SC4P50V2CN-GP
SC4P50V2CN-GP
1 2
PCH_SUSCLK_KBC 61
+V1.05S_AXCK_LCPLL
R1810
R1810
1 2
0R0402-PAD
0R0402-PAD
Q1803
Q1803
G
12
R1821
R1821
S
DY
DY
2N7002K-2-GP
2N7002K-2-GP
84.2N702.J31
84.2N702.J31
2ND = 84.2N702.031
2ND = 84.2N702.031
3rd = 84.07002.I31
3rd = 84.07002.I31
D
(#514849)
Layout: Place at the open door area.
C1801
XTAL24_IN
R1802
R1802 1MR2J-1-GP
1MR2J-1-GP
SUSCLK_R
23
12
EC1806
EC1806
DY
DY
12
XTAL24_OUT
RTC_AUX_S5
1
23
RN1813
RN1813 SRN20KJ-1-GP
SRN20KJ-1-GP
4
21
12
G1801
G1801
12
C1805
C1805
GAP-OPEN
GAP-OPEN
C1806
C1806
SC1U10V2KX-1GP
SC1U10V2KX-1GP
2
SC1U10V2KX-1GP
SC1U10V2KX-1GP
C1801
12
SC15P50V2JN-2-GP
SC15P50V2JN-2-GP
X1801
X1801 XTAL-24MHZ-81-GP
XTAL-24MHZ-81-GP
82.30004.841
82.30004.841
4 1
C1802
C1802
12
SC15P50V2JN-2-GP
SC15P50V2JN-2-GP
EC1803
EC1803
DY
DY
1 2
SC4D7P50V2BN-GP
SC4D7P50V2BN-GP
SRTC_RST# RTC_RST#
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
12
EC1807
EC1807
DY
DY
Title
Title
Title
CPU_(LPC/SPI/SMBUS/CL/CLK)
CPU_(LPC/SPI/SMBUS/CL/CLK)
CPU_(LPC/SPI/SMBUS/CL/CLK)
Size Document Numb er Rev
Size Document Numb er Rev
Size Document Numb er Rev A2
A2
A2
Tuesday, July 21, 2015
Tuesday, July 21, 2015
Tuesday, July 21, 2015 Date: Sheet of
Date: Sheet of
Date: Sheet of
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Tesla SKL-U
Tesla SKL-U
Tesla SKL-U
1
XTAL24_OUT
DY
DY
12
ED1803
ED1803
PESD5V0U1BL-GP-U1
PESD5V0U1BL-GP-U1
18 102
18 102
18 102
-1
-1
-1
2N7002KDW-G P
MEM_SMBDATA
84.2N702.A3F
84.2N702.A3F
2nd = 84.2N702.E3F
2nd = 84.2N702.E3F
3rd = 75.00601.07C
3rd = 75.00601.07C
4th = 84.DMN66.03F
B B
3D3V_S0
CLKREQ_PEG#0
R1817
R1817
1 2
10KR2J-3-GP
10KR2J-3-GP
CLKREQ_PCIE#1
R1829
R1829
1 2
10KR2J-3-GP
10KR2J-3-GP
RN1801
RN1801
CLKREQ_PCIE#5
1
8
CLKREQ_PCIE#2
2
7
CLKREQ_PCIE#4
3
6
CLKREQ_PCIE#3
45
SRN10KJ-6-GP
SRN10KJ-6-GP
PEG_CLK_CPU#76
GPU
WLAN
LAN
A A
5
PEG_CLK_CPU76
CLKREQ_PEG#076
PEG_CLK1_CPU#61 PEG_CLK1_CPU61
CLKREQ_PCIE#161
PEG_CLK2_CPU#31 PEG_CLK2_CPU31
CLKREQ_PCIE#231
4th = 84.DMN66.03F
MEM_SMBCLK
CLKREQ_PEG#0
CLKREQ_PCIE#1
CLKREQ_PCIE#3
CLKREQ_PCIE#4
CLKREQ_PCIE#5
4
2N7002KDW-G P
6
Q1801
Q1801
CPU1J
CPU1J
D42
CLKOUT_PCIE_N0
C42
CLKOUT_PCIE_P0
AR10
GPP_B5/SRCCLKREQ0#
B42
CLKOUT_PCIE_N1
A42
CLKOUT_PCIE_P1
AT7
GPP_B6/SRCCLKREQ1#
D41
CLKOUT_PCIE_N2
C41
CLKOUT_PCIE_P2
AT8
GPP_B7/SRCCLKREQ2#
D40
CLKOUT_PCIE_N3
C40
CLKOUT_PCIE_P3
AT10
GPP_B8/SRCCLKREQ3#
B40
CLKOUT_PCIE_N4
A40
CLKOUT_PCIE_P4
AU8
GPP_B9/SRCCLKREQ4#
E40
CLKOUT_PCIE_N5
E38
CLKOUT_PCIE_P5
AU7
GPP_B10/SRCCLKREQ5#
SKYLAKE-U-GP
SKYLAKE-U-GP
071.SKYLA.000U
071.SKYLA.000U
1
2345
5
Main Func = PCH
Strap pin:
Port B / Port C Detected
DDPB_CTRLDATA
4
Sampled at rising edge of PCH_PWROK
0 = Port B is not detected. 1 = Port B is detected.
*
3
2
1
D D
DDPC_CTRLDATA
These two signals h ave weak internal pu ll-down.
C C
PCH strap pin:
Flash Descriptor Security Overide/ Intel ME De bug Mode
HDA_SDO UT
The internal pull-do wn is disabled aft er PLTRST# deasserts
B B
Low = Default High = Enable
EC1901
EC1901
SC10P50V2JN-4GP
SC10P50V2JN-4GP
1 2
DY
DY
HDA_CODEC_BITCLK
HDA_CODEC_RST#
*
PCH strap pin:
HDA_SPK R
The internal pull-do wn is disabled aft er PLTRST# deasserts
*
HDA_SDIN027
DGPU_PWROK24,76,86
NO REB OOT
Low = Enable (Default)
*
High = Disable
0 = Port C is not detected. 1 = Port C is detected.
SPKR27
HDA_SYNC HDA_BITCLK HDA_SDOUT
HDA_RST#
DGPU_PWROK
SPKR
3D3V_S0
BA22 AY22 BB22 BA21 AY21
AW22
AY20
AW20
AK10
AW5
1KR2J-1-GP
1KR2J-1-GP R2006
R2006
1 2
DY
DY
HDA_CODEC_SYNC27 HDA_CODEC_SDOUT27
HDA_CODEC_BITCLK27 HDA_CODEC_RST#27
CPU1G
CPU1G
HDA_SYNC/I2S0_SFRM HDA_BLK/I2S0_SCLK HDA_SDO/I2S0_TXD HDA_SDI0/I2S0_RX D HDA_SDI1/I2S1_RX D HDA_RST#/I2S1_SCLK
J5
GPP_D23/I2S_MCLK I2S1_SFRM I2S1_TXD
AK7
GPP_F1/I2S2_SFRM
AK6
GPP_F0/I2S2_SCLK
AK9
GPP_F2/I2S2_TXD GPP_F3/I2S2_RXD
H5
GPP_D19/DMIC_CLK0
D7
GPP_D20/DMIC_DATA0
D8
GPP_D17/DMIC_CLK1
C8
GPP_D18/DMIC_DATA1
GPP_B14/SPKR
SKYLAKE-U-GP
SKYLAKE-U-GP
SPKR
ME_FWP_EC24
AUDIO
AUDIO
RN1901
RN1901
1 2 3
SRN0J-6-GP
SRN0J-6-GP
R1909 1KR2J-1-GPR1909 1KR2J-1-GP
1 2
RN1902
RN1902
1 2 3
SRN0J-6-GP
SRN0J-6-GP
SKYLAKE_ULT
SKYLAKE_ULT
4
4
7 OF 20
7 OF 20
SDIO/SDXC
SDIO/SDXC
GPP_G0/SD_CMD GPP_G1/SD_DATA0 GPP_G2/SD_DATA1 GPP_G3/SD_DATA2 GPP_G4/SD_DATA3
GPP_G5/SD_CD# GPP_G6/SD_CLK
GPP_G7/SD_WP
GPP_A17/SD_PWR_EN#/ISH_GP7
GPP_A16/SD_1P8_SEL
SD_RCOMP
GPP_F23
HDA_SYNC
HDA_SDOUTHDA_SDOUTHDA_SDOUT
HDA_BITCLK
HDA_RST#
AB11 AB13 AB12 W12 W11 W10 W8 W7
BA9 BB9
AB7
AF13
CPU_A16_TP
SD_RCOMP
1
1 2
TP1902
TP1902
R1901
R1901
200R2F-L-GP
200R2F-L-GP
BT_DISABLE#
BT_DISABLE# 61
GPU_EVENT# 79
TPAD14-OP-GP
TPAD14-OP-GP
R1915
R1915
12
10KR2J-3-GP
10KR2J-3-GP
12
EC1902
EC1902
DY
DY
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
A A
5
4
3
2
BOM1
BOM1
BOM1
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CPU_(AUDIO/SDIO/SDXC)
CPU_(AUDIO/SDIO/SDXC)
CPU_(AUDIO/SDIO/SDXC)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3
Tuesday, July 21, 2015
Tuesday, July 21, 2015
Tuesday, July 21, 2015
Date: Sheet of
Date: Sheet of
Date: Sheet of
Tesla SKL-U
Tesla SKL-U
Tesla SKL-U
19 102
19 102
19 102
1
-1
-1
-1
DGPU_HOLD_RST#
12
DGPU_PWR_EN#
12
CAMERA_EN
10KR2J-3-GP
10KR2J-3-GP
Low = SPI (Default) High = LPC
5
CAMERA_EN
TOUCH_RST
GPP_B22/GSPI1_MOSI
DGPU_HOLD_RST#79
G-sensor
12
DY
DY
EC2002
EC2002
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
SENSOR_HUB_SDA24
SENSOR_HUB_SCL24
NFC_REQ90
RTC_DET_R25
VIDEO_THERM_ALERT#79
TOUCH_RST55
Main Func = PCH
R1922
R1922
10KR2J-3-GP
10KR2J-3-GP
R192310KR 2J-3-GP R192310KR2J-3-GP
R1916
R1916
1 2
PCH strap pin:
D D
Boot BIOS Strap Bi t BBS
Boot BIOS
*
Destination
The internal pu ll-down is disabled after PLTRST# deasserts
Need double confirm, GPIO table set to GPI if that's needed PH or PL
3D3V_S0
R1914 10KR2J-3-GP
R1914 10KR2J-3-GP
1 2
DY
DY
R1917 10KR2J-3-GPR1917 10KR2J-3-GP
1 2
R1918
R1918
1 2
1KR2J-L2-GP
1KR2J-L2-GP
DY
DY
PCH Prim
PCH strap pin:
C C
No Reboot
GSPI0_MOSI / GPP_B18
The signal has a weak internal pull-down .
3D3V_S5_PCH
R2039 10KR2J-3-GPR2039 10KR2J-3-GP
B B
Sampled at rising edge of PCH_PWR OK
0 = Disable “No Reboot” mode. 1 = Enable “No Reboot” mode (PCH will disable the TCO Timer system r eboot feature). This function is u seful when running ITP/XDP.
3D3V_S0 3D3V_S0
12
R2022
R2022
10KR2J-3-GP
10KR2J-3-GP
DY
R2020
R2020
10KR2J-3-GP
10KR2J-3-GP
DY
12
DY
DY
NFC_REQ VIDEO_THERM_ALERT#
1 2
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
12
R2028
R2028
DY
DY
12
R2027
R2027
DY
DY
ME_SUS_PWR_ACK_R 17,24
3D3V_S0
12
R2007
R2007
DY
DY
1KR2J-1-GP
1KR2J-1-GP
GPP_B18/GSPI0_MOSI
12
R2019
R2019
DY
DY
1KR2J-1-GP
1KR2J-1-GP
RTC_DET_R
RN2010
RN2010
2 3 1
SRN0J-14-GP
SRN0J-14-GP
4
VRAM_ID1 GPP_B18/GSPI0_MOSI
GPP_B22/GSPI1_MOSI
DGPU_PRSNT#
SENSOR_HUB_SDA0 SENSOR_HUB_SCL0
4
CPU1F
CPU1F
AN8
GPP_B15/GSPI0_CS#
AP7
GPP_B16/GSPI0_CLK
AP8
GPP_B17/GSPI0_MISO
AR7
GPP_B18/GSPI0_MOSI
AM5
GPP_B19/GSPI1_CS#
AN7
GPP_B20/GSPI1_CLK
AP5
GPP_B21/GSPI1_MISO
AN5
GPP_B22/GSPI1_MOSI
AB1
GPP_C8/UART0_RXD
AB2
GPP_C9/UART0_TXD
W4
GPP_C10/UART0_RTS#
AB3
GPP_C11/UART0_CTS#
AD1
GPP_C20/UART2_RXD
AD2
GPP_C21/UART2_TXD
AD3
GPP_C22/UART2_RTS#
AD4
GPP_C23/UART2_CTS#
U7
GPP_C16/I2C0_SDA
U6
GPP_C17/I2C0_SCL
U8
GPP_C18/I2C1_SDA
U9
GPP_C19/I2C1_SCL
AH9
GPP_F4/I2C2_SDA
AH10
GPP_F5/I2C2_SCL
AH11
GPP_F6/I2C3_SDA
AH12
GPP_F7/I2C3_SCL
AF11
GPP_F8/I2C4_SDA
AF12
GPP_F9/I2C4_SCL
SKYLAKE-U-GP
SKYLAKE-U-GP
071.SKYLA.000U
071.SKYLA.000U
3
LPSS ISH
LPSS ISH
SKYLAKE_ULT
SKYLAKE_ULT
Strap
GPP_F10/I2C5_SDA/ISH_I2C 2_SDA
GPP_F11/I2C5_SCL/ISH_I2C 2_SCL
GPP_D13/ISH_UART0_RXD/SM L0BDATA/I2C4B_SDA
GPP_D14/ISH_UART0_TXD/SM L0BCLK/I2C4B_SCL
GPP_D16/ISH_UART0_CTS#/S ML0BALERT#
GPP_C12/UART1_RXD/ISH_U ART1_RXD
GPP_C13/UART1_TXD/ISH_U ART1_TXD GPP_C14/UART1_RTS#/ISH_U ART1_RTS# GPP_C15/UART1_CTS#/ISH_U ART1_CTS#
SX_EXIT_HOLDOFF#/GPP_A12/BM_BUSY#/ ISH_GP6
TPM_DETECT_1 TPM_DETECT_2
TPM/TCM Strap pin
TPM
TCM
Non-TPM& Non-TCM
3D3V_S0 3D3V_S0
12
R2010
R2010 10KR2J-3-GP
10KR2J-3-GP
DY
DY
12
R2009
R2009
DY
DY
10KR2J-3-GP
10KR2J-3-GP
TPM_DETECT_1
0
12
DY
DY
12
DY
DY
TPM_DETECT_2
GPP_D5/ISH_I2C0_SDA GPP_D6/ISH_I2C0_SCL
GPP_D7/ISH_I2C1_SDA GPP_D8/ISH_I2C1_SCL
GPP_D15/ISH_UART0_RTS#
GPP_A18/ISH_GP0 GPP_A19/ISH_GP1 GPP_A20/ISH_GP2 GPP_A21/ISH_GP3 GPP_A22/ISH_GP4 GPP_A23/ISH_GP5
R2029
R2029 10KR2J-3-GP
10KR2J-3-GP
R2013
R2013 10KR2J-3-GP
10KR2J-3-GP
0
10
01
6 OF 20
6 OF 20
GPP_D9 GPP_D10 GPP_D11 GPP_D12
P2 P3 P4 P1
M4 N3
N1 N2
AD11 AD12
U1 U2 U3 U4
AC1 AC2 AC3 AB4
AY8 BA8 BB7 BA7 AY7 AW7 AP13
USB_UART_SEL_D9
DGPU_HOLD_RST#
I2C1_S DA I2C1_S CL
1.8V Only
TPM_DETECT_1 TPM_DETECT_2 UART0_CTS#
UART1_RXD UART1_TXD UART1_RTS# UART1_CTS#
ISH_G P_0_R ISH_G P_1_R
TOUCH_DET
NFC_DETECT
UC_DETECT
ThermalIC_DET
1
1
1 1 1 1
DGPU_PRSNT#
NCT7718
NCT7718
ThermalIC_DET
TP2006 TPAD14-OP-GPTP2006 TPAD14-OP-GP
GC6_FB_EN_PCH 79
CAMERA_EN 55
TP2011 TPAD14-OP-GPTP2011 TPAD14-OP-GP
TP2012 TPAD14-OP-GPTP2012 TPAD14-OP-GP TP2013 TPAD14-OP-GPTP2013 TPAD14-OP-GP TP2014 TPAD14-OP-GPTP2014 TPAD14-OP-GP TP2015 TPAD14-OP-GPTP2015 TPAD14-OP-GP
ISH_G P_0_R 70 ISH_G P_1_R 66
3D3V_S0
12
R2005
R2005
UMA
UMA
10KR2J-3-GP
10KR2J-3-GP
12
R2008
R2008 10KR2J-3-GP
10KR2J-3-GP
OPS
OPS
12
R2053
R2053 10KR2J-3-GP
10KR2J-3-GP
12
R2054
R2054 10KR2J-3-GP
10KR2J-3-GP
TV
TV
2
DGPU_PWR_EN# 86
VRAM_ID1
10KR2J-3-GP
10KR2J-3-GP
TOUCH_DET
10KR2J-3-GP
10KR2J-3-GP
1
3D3V_S0
SRN2K2J-1-GP
SRN2K2J-1-GP
RN2007
SENSOR_HUB_SCL SENSOR_HUB_SDA
I2C1_S CL I2C1_S DA
ISH_G P_0_R ISH_G P_1_R
GC6_FB_EN_PCH
10KR2J-3-GP
10KR2J-3-GP
(PDG#543016) Ensure that all I2C interface on-board terminations are pulled up to the same voltage rail as the device/end point.
3D3V_S0
R2017
R2017
R2018
R2018
12
TOUCH
TOUCH
12
NON TOUCH
NON TOUCH
3D3V_S03D3V_S0
12
R2023
R2023 10KR2J-3-GP
10KR2J-3-GP
DY
DY
12
R2024
R2024
DY
DY
10KR2J-3-GP
10KR2J-3-GP
(PDG#543016) If the UART/GPIO functionality is also not used, the signals can be left as no-connect.
1 2 3
1 2 3
NFC_DETECT
RN2007
RN2008
RN2008
DY
DY
SRN2K2J-1-GP
SRN2K2J-1-GP
RN2009
RN2009
1 2 3
SRN10KJ-5-GP
SRN10KJ-5-GP
R1921
R1921
12
NFC
NFC
4
4
4
3D3V_S0
12
R2026
R2026 10KR2J-3-GP
10KR2J-3-GP
RN2011
RN2011
1 2 3
SRN10KJ-5-GP
SRN10KJ-5-GP
4
UC_DETECT
10KR2J-3-GP
10KR2J-3-GP
NFC_DETECT
UC_DETECT
R2016
R2016
NUC
NUC
12
A A
BOM1
BOM1
BOM1
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Numb er Rev
Size Document Numb er Rev
Size Document Numb er Rev A2
A2
A2
Tuesday, July 21, 2015
Tuesday, July 21, 2015
Tuesday, July 21, 2015 Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
CPU_(LPSS/ISH)
CPU_(LPSS/ISH)
CPU_(LPSS/ISH)
Tesla SKL-U
Tesla SKL-U
Tesla SKL-U
1
20 102
20 102
20 102
-1
-1
-1
5
4
3
2
1
Main Func = PCH
RTC_AUX_S5
C2118
C2118
C2119
C2119
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
1D0V_S5
D D
C C
3D3V_S5
12
C2120
C2120
12
SC1U10V2KX-1GP
SC1U10V2KX-1GP
C2105
C2105
SC1U10V2KX-1GP
SC1U10V2KX-1GP
+VCCDSW_1P0
1D0V_S5
+VCCAMPHYPLL_1P0
1D0V_S5
3D3V_S5
1D0V_S5
1D0V_S5
2.57A
CPU1O
CPU1O
AB19
VCCPRIM_1P0
AB20
VCCPRIM_1P0
P18
VCCPRIM_1P0
AF18
VCCPRIM_CORE
AF19
VCCPRIM_CORE
V20
VCCPRIM_CORE
V21
VCCPRIM_CORE
AL1
DCPDSW_1P0
K17
VCCMPHYAON_1P0
L1
VCCMPHYAON_1P0
N15
VCCMPHYGT_1P0
N16
VCCMPHYGT_1P0
N17
VCCMPHYGT_1P0
P15
VCCMPHYGT_1P0
P16
VCCMPHYGT_1P0
K15
VCCAMPHYPLL_1P0
L15
VCCAMPHYPLL_1P0
V15
VCCAPLL_1P0
AB17
VCCPRIM_1P0
Y18
VCCPRIM_1P0
AD17
VCCDSW_3P3
AD18
VCCDSW_3P3
AJ17
VCCDSW_3P3
AJ19
VCCHDA
AJ16
VCCSPI
AF20
VCCSRAM_1P0
AF21
VCCSRAM_1P0
T19
VCCSRAM_1P0
T20
VCCSRAM_1P0
AJ21
VCCPRIM_3P3
AK20
VCCPRIM_1P0
N18
VCCAPLLEBB_1P0
SKYLAKE-U-GP
SKYLAKE-U-GP
071.SKYLA.000U
071.SKYLA.000U
CPU POWER 4 OF 4
CPU POWER 4 OF 4
SKYLAKE_ULT
SKYLAKE_ULT
1.8V Only
15 OF 20
15 OF 20
VCCPGPPA VCCPGPPB VCCPGPPC VCCPGPPD VCCPGPPE
VCCPGPPF
VCCPGPPG
VCCPRIM_3P3
VCCPRIM_1P0
VCCATS_1P8
VCCRTCPRIM_3P3
VCCRTC VCCRTC
DCPRTC
VCCCLK1
VCCCLK2
VCCCLK3
VCCCLK4
VCCCLK5
VCCCLK6
GPP_B0/CORE_VID0 GPP_B1/CORE_VID1
AK15 AG15 Y16 Y15 T16 AF16 AD15
V19
T1
AA1
AK17
AK19 BB14
BB10
A14
K19
L21
N20
L19
A10
AN11 AN13
VCCRTCEXT
V0.85A_VID0 V0.85A_VID1
+VCCPGPPA
+V1.8A
3D3V_S5
1D0V_S5
+V1.8A
+VCCCLK
+VCCCLK
+VCCCLK
+VCCCLK
+VCCCLK
+VCCCLK
C2112 SCD1U16V2KX-3GPC2112 SCD1U16V2KX-3GP
1 2
TP2101 TPAD14-OP-GPTP2101 TPAD14-OP-GP
1
TP2102 TPAD14-OP-GPTP2102 TPAD14-OP-GP
1
RTC_AUX_S5
+VCCPGPP
C2107
C2107
C2106
C2106
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
12
12
C2109
C2109
SC1U10V2KX-1GP
SC1U10V2KX-1GP
12
12
C2110
C2110
12
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
12
DY
DY
CAP need close to VCCRTC
3D3V_S5
C2111
C2111
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
C2117
C2117
12
12
SC1U10V2KX-1GP
SC1U10V2KX-1GP
1D0V_S5
C2101
C2101
12
12
SC18P50V2JN-1-GP
SC18P50V2JN-1-GP
+VCCCLK
B B
A A
12
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
C2113
C2113
5
+VCCDSW_1P0
+V1.8A
C2102
C2102
C2104
C2104
C2103
C2103
C2108
SC1U10V2KX-1GP
SC1U10V2KX-1GP
12
SC18P50V2JN-1-GP
SC18P50V2JN-1-GP
12
12
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
C2114
C2114
C2115
C2115
C2108
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
12
12
SC1U10V2KX-1GP
12
C2116
C2116
C2121
C2121
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC2D2U10V2KX-GP
SC2D2U10V2KX-GP
12
BOM1
BOM1
BOM1
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Numb er Rev
Size Document Numb er Rev
Size Document Numb er Rev A2
A2
A2
Tuesday, July 21, 2015
Tuesday, July 21, 2015
Tuesday, July 21, 2015 Date: Sheet of
Date: Sheet of
4
3
2
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
CPU_(POWER1)
CPU_(POWER1)
CPU_(POWER1)
Tesla SKL-U
Tesla SKL-U
Tesla SKL-U
1
21 102
21 102
21 102
-1
-1
-1
5
4
3
2
1
Main Func = PCH
D D
20 OF 20
CPU1T
CPU1T
AW69
RSVD#AW69
AW68
RSVD#AW68
AU56
RSVD#AU56
AW48
RSVD#AW48
C7
RSVD#C7
U12
RSVD#U12
U11
RSVD#U11
H11
RSVD#H11
SKYLAKE-U-GP
SKYLAKE-U-GP
071.SKYLA.000U
C C
071.SKYLA.000U
SKYLAKE_ULT
SKYLAKE_ULT
SPARE
SPARE
20 OF 20
RSVD#F6
RSVD#E3 RSVD#C11 RSVD#B11 RSVD#A11 RSVD#D12 RSVD#C12
RSVD#F52
F6 E3 C11 B11 A11 D12 C12 F52
B B
BOM1
BOM1
BOM1
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
CPU_(RSVD)
CPU_(RSVD)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A4
A4
A4
Tuesday, July 21, 2015
Tuesday, July 21, 2015
Tuesday, July 21, 2015
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
2
CPU_(RSVD)
Tesla SKL-U
Tesla SKL-U
Tesla SKL-U
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
-1
-1
22 102
22 102
22 102
1
-1
5
4
3
2
1
Main Func = PCH
16 OF 20
CPU1P
CPU1P
GND 1 OF 3
GND 1 OF 3
SKYLAKE_ULT
SKYLAKE_ULT
A5
VSS
D D
C C
B B
A67
VSS
A70
VSS
AA2
VSS
AA4
VSS
AA65
VSS
AA68
VSS
AB15
VSS
AB16
VSS
AB18
VSS
AB21
VSS
AB8
VSS
AD13
VSS
AD16
VSS
AD19
VSS
AD20
VSS
AD21
VSS
AD62
VSS
AD8
VSS
AE64
VSS
AE65
VSS
AE66
VSS
AE67
VSS
AE68
VSS
AE69
VSS
AF1
VSS
AF10
VSS
AF15
VSS
AF17
VSS
AF2
VSS
AF4
VSS
AF63
VSS
AG16
VSS
AG17
VSS
AG18
VSS
AG19
VSS
AG20
VSS
AG21
VSS
AG71
VSS
AH13
VSS
AH6
VSS
AH63
VSS
AH64
VSS
AH67
VSS
AJ15
VSS
AJ18
VSS
AJ20
VSS
AJ4
VSS
AK11
VSS
AK16
VSS
AK18
VSS
AK21
VSS
AK22
VSS
AK27
VSS
AK63
VSS
AK68
VSS
AK69
VSS
AK8
VSS
AL2
VSS
AL28
VSS
AL32
VSS
AL35
VSS
AL38
VSS
AL4
VSS
AL45
VSS
AL48
VSS
AL52
VSS
AL55
VSS
AL58
VSS
AL64
VSS
SKYLAKE-U-GP
SKYLAKE-U-GP
071.SKYLA.000U
071.SKYLA.000U
16 OF 20
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
AL65 AL66 AM13 AM21 AM25 AM27 AM43 AM45 AM46 AM55 AM60 AM61 AM68 AM71 AM8 AN20 AN23 AN28 AN30 AN32 AN33 AN35 AN37 AN38 AN40 AN42 AN58 AN63 AP10 AP18 AP20 AP23 AP28 AP32 AP35 AP38 AP42 AP58 AP63 AP68 AP70 AR11 AR15 AR16 AR20 AR23 AR28 AR35 AR42 AR43 AR45 AR46 AR48 AR5 AR50 AR52 AR53 AR55 AR58 AR63 AR8 AT2 AT20 AT23 AT28 AT35 AT4 AT42 AT56 AT58
CPU1Q
CPU1Q
AT63
VSS
AT68
VSS
AT71
VSS
AU10
VSS
AU15
VSS
AU20
VSS
AU32
VSS
AU38
VSS
AV1
VSS
AV68
VSS
AV69
VSS
AV70
VSS
AV71
VSS
AW10
VSS
AW12
VSS
AW14
VSS
AW16
VSS
AW18
VSS
AW21
VSS
AW23
VSS
AW26
VSS
AW28
VSS
AW30
VSS
AW32
VSS
AW34
VSS
AW36
VSS
AW38
VSS
AW41
VSS
AW43
VSS
AW45
VSS
AW47
VSS
AW49
VSS
AW51
VSS
AW53
VSS
AW55
VSS
AW57
VSS
AW6
VSS
AW60
VSS
AW62
VSS
AW64
VSS
AW66
VSS
AW8
VSS
AY66
VSS
B10
VSS
B14
VSS
B18
VSS
B22
VSS
B30
VSS
B34
VSS
B39
VSS
B44
VSS
B48
VSS
B53
VSS
B58
VSS
B62
VSS
B66
VSS
B71
VSS
BA1
VSS
BA10
VSS
BA14
VSS
BA18
VSS
BA2
VSS
BA23
VSS
BA28
VSS
BA32
VSS
BA36
VSS
F68
VSS
BA45
VSS
SKYLAKE-U-GP
SKYLAKE-U-GP
071.SKYLA.000U
071.SKYLA.000U
GND 2 OF 3
GND 2 OF 3
SKYLAKE_ULT
SKYLAKE_ULT
17 OF 20
17 OF 20
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
BA49 BA53 BA57 BA6 BA62 BA66 BA71 BB18 BB26 BB30 BB34 BB38 BB43 BB55 BB6 BB60 BB64 BB67 BB70 C1 C25 C5 D10 D11 D14 D18 D22 D25 D26 D30 D34 D39 D44 D45 D47 D48 D53 D58 D6 D62 D66 D69 E11 E15 E18 E21 E46 E50 E53 E56 E6 E65 E71 F1 F13 F2 F22 F23 F27 F28 F32 F33 F35 F37 F38 F4 F40 F42 BA41
CPU1R
CPU1R
GND 3 OF 3
GND 3 OF 3
F8
VSS
G10
VSS
G22
VSS
G43
VSS
G45
VSS
G48
VSS
G5
VSS
G52
VSS
G55
VSS
G58
VSS
G6
VSS
G60
VSS
G63
VSS
G66
VSS
H15
VSS
H18
VSS
H71
VSS
J11
VSS
J13
VSS
J25
VSS
J28
VSS
J32
VSS
J35
VSS
J38
VSS
J42
VSS
J8
VSS
K16
VSS
K18
VSS
K22
VSS
K61
VSS
K63
VSS
K64
VSS
K65
VSS
K66
VSS
K67
VSS
K68
VSS
K70
VSS
K71
VSS
L11
VSS
L16
VSS
L17
VSS
SKYLAKE-U-GP
SKYLAKE-U-GP
071.SKYLA.000U
071.SKYLA.000U
SKYLAKE_ULT
SKYLAKE_ULT
18 OF 20
18 OF 20
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
L18 L2 L20 L4 L8 N10 N13 N19 N21 N6 N65 N68 P17 P19 P20 P21 R13 R6 T15 T17 T18 T2 T21 T4 U10 U63 U64 U66 U67 U69 U70 V16 V17 V18 W13 W6 W9 Y17 Y19 Y20 Y21
A A
5
4
3
2
BOM1
BOM1
BOM1
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3
Tuesday, July 21, 2015
Tuesday, July 21, 2015
Tuesday, July 21, 2015
Date: Sheet of
Date: Sheet of
Date: Sheet of
CPU_(VSS)
CPU_(VSS)
CPU_(VSS)
Tesla SKL-U
Tesla SKL-U
Tesla SKL-U
23 102
23 102
23 102
1
-1
-1
-1
SSID = KBC
5
D D
3D3V_S0
12
12
C2428
C2428
C2402
C2402
SC2D2U10V3KX-L-GP
SC2D2U10V3KX-L-GP
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
1D0V_S5
1
AFTP24 04AFTE1 4P-G P AFTP2404AFTE14 P-GP
C C
3D3V_AUX_KBC
12
12
C2401
C2401
SC2D2U10V3KX-L-GP
SC2D2U10V3KX-L-GP
R2481
R2481
1 2
1D0V_S5
0R0402-PAD
0R0402-PAD
12
C2425
C2425 SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
PCH / GPU N15S / Gsensor /NCT7718
BATTERY / CHARGER ---->
VOL_UP_ BTN #66
06/24 NOVO Button---->
R2462
R2462
R2404 0R2J-2-GP
R2404 0R2J-2-GP
D2401
D2401
3
075.00054.0B7D
075.00054.0B7D
1 2
󴅐󴅐󴅐󴅐
12
R1736
R1736 1KR2J-L2-GP
1KR2J-L2-GP
DY
DY
R2403
R2403
1 2
0R0402-PAD
0R0402-PAD
1 2
AOAC
AOAC
Power button
E51_TXD 61
E51_RXD 61
1 2
DY
DY
KBC_NOVO_BTN#
VIDEO_PO WER_ LIMIT #79
KBC_DPWROK17
06/16 MAX R1717 DY
PM_CLKRUN#_EC_R18
WLAN_PWRON61
Reserved AOAC
B B
KBC_PWRBTN_EC#
LBAT54CLT1G-1-GP
LBAT54CLT1G-1-GP
KBC_NOVO_BTN#_EC
06/24 add D2401.
󱭐󱭐󱭐󱭐
󲆉󲆉󲆉󲆉󰸮󰸮󰸮󰸮󴣊󴣊󴣊󴣊󴫜󴫜󴫜󴫜
0R0402-PAD
0R0402-PAD
R2458
R2458
R2451
R2451
1 2
Novo button
1 Pin
󳲯󳲯󳲯󳲯
AOU_IFLG#
E51_TXD
12
E51_RXD
DY
DY
,
E51_TXD_KBC
USB_PWR_EN
0R2J-2-GP
0R2J-2-GP
A A
R2469
R2469 2D2R3-1-U-GP
2D2R3-1-U-GP
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
VOL_UP_ BTN #
0R2J-2-GP
0R2J-2-GP
ME_SUS_PWR_ACK_R17,20
󲋮󲋮󲋮󲋮󰵉󰵉󰵉󰵉󴳀󴳀󴳀󴳀,󱘩󱘩󱘩󱘩
R2479
R2479
1 2
0R0805-PAD
0R0805-PAD
1 2
0R0603-PAD
0R0603-PAD
12
C2404
C2404
EC_VTT
Thermal VD
R2493
R2493
3D3V_AUX_KBC_VCC
12
C2405
C2405
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
DY
DY
SENSOR_HUB_INT#18
WLAN_PCIE_WAKE#61
DGPUHOTVIDEO_PO WER_ LIMIT #
Thermal VD
AC_PRES ENT17
PM_CLKRUN#_EC
KBC_NOVO_BTN# 66
KBC PSL
3D3V_AUX_S5
12
C2430
C2430
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
SCREEN_ROTATE_LOCK#66
DGPU_PWROK19,76,86
TP---->
KBC_NOVO_BTN#_EC
LAN_PWR_ON31
1 2
DS3
DS3
󱌳󱌳󱌳󱌳󲙒󲙒󲙒󲙒
4Pin
VBAT
12
12
C2426
C2426
C2420
C2420
SC2D2U10V3KX-L-GP
SC2D2U10V3KX-L-GP
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
EC_AGND
12
12
C2429
C2429
C2421
C2421
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
C2427 SCD1U10V2KX-5GP
C2427 SCD1U10V2KX-5GP
1 2
EC_AGND
DY
DY
AD_IA44
PCB_VER
LID_CLOSE2#66
PCH_WAKE#17,31
VD_IN226
USB_PWR_EN134 USB_AO_SEL134 USB_AO_SEL234
ALL_SYS _PWR GD17,40
SML1_SMBCLK18,26,66,79,90
SML1_SMBDATA18,26,66,79,90 SENSOR_HUB_SCL20 SENSOR_HUB_SDA20
DGPUHOT
FAN_TACH126
KB_BKLT_PWM65
CHARGE_LED64,66
VOL_DOW N_BT N#66
1 2
R2463 0R0402-PADR2463 0R0402-PAD
VD_IN126
VD_OUT 1#26 VD_OUT 2#26
WIRELESS_EN61
R2402 0R2J-2-GP
R2402 0R2J-2-GP
AMP_MUT E#27
ADT_T YPE
MODEL_ID
VD_IN2
USB_PWR_EN1 USB_AO_SEL1 USB_AO_SEL2
BAT_SCL43,44,70 BAT_SDA43,44,70
PROCHOT_EC
DGPU_PWROK_EC
R2445
R2445
12
0R0402-PAD
0R0402-PAD
TPCLK65
TPDATA65
BLON_OUT55
SIO_PWRBTN#17 CAP_LED65 SIO_SLP_S3#17,40,51,52,54
DC_BATFULL64,66
PWRLED64,66
FAN1_PWM26
PANEL_BLEN55
KBC_BEEP
KBC_BEEP27
KB_BKLT_PWM
VOL_DOW N_BT N# PWRLED
VD1_EN#
VD_IN1
VD_OUT 1# VD_OUT 2#
SYS_PWROK17
WIRELESS_EN
5V_EN
5V_EN40,45
PM_SUSWARN#_KBC
E51_TXD_KBC
6/18 U2403 Change Part Number to 71.00285.0A0G (285P)
EC GPIO PH
3D3V_AUX_KBC
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
2 3 1
SRN4K7J-8-GP
SRN4K7J-8-GP
1 2 3
SRN100KJ-6-GP
SRN100KJ-6-GP
RN2403
RN2403
4
R2435
R2435
12
R2434
R2434
12
RN2406
RN2406
4
NPCE285G
U2403
U2403
19
VCC
46
VCC
76
VCC
88
VCC
115
VCC
102
AVCC
4
VDD
12
VTT
97
GPIO90/AD0
98
GPIO91/AD1
99
GPIO92/AD2
100
GPIO93/AD3
108
GPIO05/AD4
96
GPIO04/AD5
95
GPIO03/EXT_PURST#/AD6
94
GPIO07/AD7/VD_IN2
101
GPIO94/DA0
105
GPIO95/DA1
106
GPIO96/DA2
107
GPIO97/DA3
70
GPIO17/SCL1/N2TCK
69
GPIO22/SDA1/N2TMS
67
GPIO73/SCL2/N2TCK
68
GPIO74/SDA2/N2TMS
119
GPIO23/SCL3/N2TCK
120
GPIO31/SDA3/N2TMS
24
GPIO47/SCL4A/N2TCK
28
GPIO53/SDA4A/N2TMS
26
GPIO51/TA3/N2TCK
123
GPIO67/SOUT1/N2TMS
72
GPIO37/PSCLK1
71
GPIO35/PSDAT1
10
GPIO26/PSCLK2
11
GPIO27/PSDAT2
25
GPIO50/PSCLK3
27
GPIO52/PSDAT3
31
GPIO56/TA1
117
GPIO20/TA2/IOX_DIN_DIO
63
GPIO14/TB1
64
GPIO01/TB2
32
GPIO15/A_PWM
118
GPIO21/B_PWM
62
GPIO13/C_PWM
65
GPIO32/D_PWM
22
GPIO45/E_PWM/DTR1#_BOUT1
16
GPIO40/F_PWM/1_WIRE/RI1#
81
GPIO66/G_PWM/PSL_GPIO66
66
GPO33/H_PWM/VD1_EN#
104
GPIO80/VD_IN1
110
GPIO82/IOX_LDSH/VD_OUT1
112
GPIO84/IOX_SCLK/VD_OUT2
84
GPIO77/SPI_MISO
83
GPIO76/SPI_MOSI
82
GPIO75/SPI_SCK
79
GPIO02/SPI_CS#
124
GPIO10/LPCPD#
121
GPIO85/GA20
111
GPIO83/SOUT_CR
9
GPIO65/SMI#
8
GPIO11/CLKRUN#
30
GPIO55/CLKOUT/IOX_DIN_DIO
NPCE285PA0DX-1-GP
NPCE285PA0DX-1-GP
071.00285.0A0G
071.00285.0A0G
BAT_SCL BAT_SDA
S5_ENABLE
ECRST#
BAT_IN#
5V_EN
4
KBSIN0/GPIOA0/N2TCK KBSIN1/GPIOA1/N2TMS
KBSIN2/GPIOA2 KBSIN3/GPIOA3 KBSIN4/GPIOA4 KBSIN5/GPIOA5 KBSIN6/GPIOA6 KBSIN7/GPIOA7
KBSOUT0/GPOB0/SOUT_CR/JENK#
KBSOUT1/GPIOB1/TCK KBSOUT2/GPIOB2/TMS
KBSOUT3/GPIOB3/TDI
KBSOUT4/GPOB4
KBSOUT5/GPIOB5/TDO
KBSOUT6/GPIOB6/RDY#
KBSOUT7/GPIOB7 KBSOUT8/GPIOC0
KBSOUT9/GPOC1/SDP_VIS# KBSOUT10/P80_CLK/GPIOC2 KBSOUT11/P80_DAT/GPIOC3
KBSOUT12/GPO64/TEST#
KBSOUT13/GP(I)O63/TRIST# KBSOUT14/GP(I)O62/XORTR#
KBSOUT15/GPIO61/XOR_OUT
GPIO60/KBSOUT16/DSR1# GPIO57/KBSOUT17/DCD1#
LFRAME#/GPIOF6 LRESET#/GPIOF7
GPIOC6/F_CS0#
GPIOC7/F_SCK
GPIO30/F_WP#/RTS1#
GPIO41/F_WP#/PSL_GPIO41
GPIOC5/F_SDIO/F_SDIO0
GPIOC4/F_SDI/F_SDIO1
GPIO81/F_WP#/F_SDIO2
GPIO00/32KCLKIN/F_SDIO3
PSL_IN1#/GPI70
PSL_IN2#/GPI06/EXT_PURST#
PSL_OUT#/GPIO71
ECSCI#/GPIO54
KBRST#/GPIO86
SERIRQ/GPIOF0
GPIO36/TB3/CTS1#
GPIO44/SCL4B PSL_IN4#/GPI43 PSL_IN3#/GPI42
GPIO46/SDA4B/CIRRXM
GPIO87/CIRRXM/SIN_CR
GPIO34/SIN1/CIRRXL
3D3V_S5
R2448
R2448
1 2
100KR2J-1-GP
100KR2J-1-GP
R2452
R2452
1 2
3D3V_S0
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
KROW0
54
KROW1
55
KROW2
56
KROW3
57
KROW4
58
KROW5
59
KROW6
60
KROW7
61
KCOL0
53
KCOL1
52
KCOL2
51
KCOL3
50
KCOL4
49
KCOL5
48
KCOL6
47
KCOL7
43
KCOL8
42
KCOL9
41
KCOL10
40
KCOL11
39
KCOL12
38
KCOL13
37
KCOL14
36
KCOL15
35
KCOL16
34
KCOL17
33
LPC_AD0_C1
126
LAD0/GPIOF1
LPC_AD1_C1
127
LAD1/GPIOF2
LPC_AD2_C1
128
LAD2/GPIOF3
LPC_AD3_C1
1
LAD3/GPIOF4
CLK_PCI_KBC_R
2
LCLK/GPIOF5
LPC_FRAME#_C1
3
PLT_RST#_EC
7
EC_SPI_CS#_C
90
EC_SPI_CLK_C
92
RTCRST_ON
109 80
EC_SPI_DO_C
87
EC_SPI_DI_C
86
NUM_LED
91 77
AC_IN_KB C#
73
KBC_PWRBTN_EC#
93
EC_ENABLE#
74
ECSCI#_KBC
29
ECRST#
85
EXT_RST#
122
KBC_VSBY
75
VSBY
KBC_VBKUP
114
VBKUP
KBC_VCORF
44
VCORF
PECI
13
PECI
125 6
GPIO24
15
21 20
LID_CLOSE#
17 23
113 14
1
5
GND
18
GND
45
GND
78
GND
89
GND
116
GND
R2472
R2472
1 2
103
AGND
0R0402-PAD
0R0402-PAD
EC_AGND
NOTE: Connect GND and AGND planes via either 0R resistor or one point layout connection.
3D3V_AUX_S5
USB_PWR_EN
WLAN_PCIE_WAKE#
10KR2J-3-GP
10KR2J-3-GP
R2439
R2439
VOL_UP_ BTN #
12
R2443
R2443
VOL_DOW N_BT N#
12
R2447
R2447
SCREEN_ROTATE_LOCK#
12
3
KROW[0..7] 65
KCOL[0..17] 65
LPC_AD0_C1
33R2J-2-GP R244933R2J-2-GP R2449
LPC_AD1_C1
33R2J-2-GP R245433R2J-2-GP R2454
LPC_AD2_C1 LPC_AD3_C1
LPC_FRAME#_C1
33R2J-2-GP R249833R2J-2-GP R2498
EMI
R2457
R2457
12
CLK_PCI_KBC 18
0R0402-PAD
0R0402-PAD
33R2J-2-GPR2485 33R2J-2-GPR2485
12
33R2J-2-GPR2497 33R2J-2-GPR2497
12
33R2J-2-GPR2491 33R2J-2-GPR2491
12
33R2J-2-GPR2482 33R2J-2-GPR2482
1 2
USB_CHAR_SEL 34
R2416 100KR2J-1-GPR2416 100KR2J-1-GP
PSL
1
TP2418
TP2418
TPAD14-OP-GP
TPAD14-OP-GP
SIO_RCIN# 18
R24940R0402-PAD R24940R0402-PAD
1 2
R24880R0402-PAD R24880R0402-PAD
1 2
C2422
C2422
1 2
R2474
R2474
SC1U10V2KX-L1-GP
SC1U10V2KX-L1-GP
1 2
43R2J-GP
43R2J-GP
AD_OFF 43,4 4
PCH_RSMRST# 17
SIO_SLP_S4# 17,40,51
LID_CLOSE# 55,66
ME_FWP_EC 19
S5_ENABLE 40
AFTP24 03 AFTE14P-GPAFT P240 3 AFTE14 P-GP
R2472 close to Pin103
2013/9/12 GPIO83/SOUT_CR & GPIO87/SIN_CR Need reserved TP for Debug
NOTE: PWM Signal :
1. If unused, select altrnative GPIO function and enable internal pull-down.
2. Please measure and make sure that the rise time of VCC_P OR is less than 10 us.
R2470
R2470
12
10KR2J-3-GP
10KR2J-3-GP
3D3V_AUX_KBC
1 2
10KR2J-3-GP
10KR2J-3-GP
06/24 R2464 KBC_NOVO_BTN# Change Net Name to KBC_NOVO_BTN#_EC
06/25 KBC_NOVO_BTN#_EC
3D3V_AUX_S5
RN2404
RN2404
1 2 3
SRN10KJ-5-GP
SRN10KJ-5-GP
C2431
C2431
1 2
0R0402-PAD
0R0402-PAD
SPI_CS0#_R 18,25 SPI_CLK_R 18,25
RTCRST_ON 18
BAT_IN# 43,44
SPI_SI0_R 18,25
SPI_SO_R 18,25
1 2
R2433
R2433
1 2
0R0402-PAD
0R0402-PAD
KBC PWR supply at PSL mode.
3D3V_AUX_S5 RTC_AUX_S5
H_PECI 4
INT_SE RIRQ 18
< ---08/06 AD_OFF
AOU_IFLG # 34
USB_PWR_EN 34,36,66
PECI
12
C2403
C2403
DY
DY
SC100P50V2JN-3GP
SC100P50V2JN-3GP
LID_CLOSE#
R2464
R2464
KBC_NOVO_BTN#_EC
󲋮󲋮󲋮󲋮
3D3V_AUX_S5,
LID_CLOSE2#
4
KBC_NOVO_BTN#
LPC_AD0
1 2
LPC_AD1
1 2
RN2405
RN2405
LPC_AD2
2 3
LPC_AD3
1
4
SRN33J-5-GP-U
SRN33J-5-GP-U
1 2
NOTE: Please be aware that the SPI interface trace length between PCH and EC should not exceed 6500mils,. The mismatch of SPI interface signals between EC and SPI flash should not exceed 500mils.
1 2
DY
DY
SC220P50V2KX-3GP
SC220P50V2KX-3GP
R2473
R2473
PLT_RST# 17,31,40,61,68,79
NOTE: Locate re sistors R24 15 and R 2417 c lose to the U2401.
NUM_LED 65
< ----06/26 LT41 USB_CHAR_SEL
3D3V_AUX_S5
AC_IN# 44
PSL
< ---- Viber Del TPM
< ---06/24 AOU_IFLG#
EC GPIO PL
AMP_MUT E#
USB_PWR_EN1
AD_OFF
󴣊󴣊󴣊󴣊󲒂󲒂󲒂󲒂󲅙󲅙󲅙󲅙
3D3V_AUX_KBC
06/05 Delete R2460(DG)
LPC_AD0 18,68 LPC_AD1 18,68
LPC_AD2 18,68 LPC_AD3 18,68
LPC_FRAME# 18,68
EC_SMI#8
EC_SCI#8
NOVO button Fun define: one key to recover OS.
NOVO button wake KBC at PSL mode.
KBC_PWRBTN_EC#KBC_NOVO_BTN#
Low
Low
KBC_PWRBTN_EC#:Low (1) 4sec: PWR Button shut down (2) 8sec: KBC reset
R2450
R2450
1 2
DY
DY
10KR2J-3-GP
10KR2J-3-GP
R2440
R2440
12
10KR2J-3-GP
10KR2J-3-GP
R2476
R2476
1 2
1KR2J-1-GP
1KR2J-1-GP
2
SPEC: ADT PWR Detection Function V1 3
DELTA Model:ADP65FD BB-PD03 ADP
R2489
R2489
1 2
0R0402-PAD
0R0402-PAD
R2486
R2486
ECSCI#_KBC
1 2
DY
DY
0R2J-2-GP
0R2J-2-GP
Nuvoton KBC PSL Power Logic
1.Enter PSL mode (Entry S5 after 10sec) : 3D3V_AUX_KBC : OFF (KBC PWR supply)
2.At PSL mode (SPEC: S5<10mW)
PSL mode(AC or DC):
S5_ENABLE 3D3V_AUX_KBCEC_ENABLE#_G
PSL Wake(AC or DC):
S5_ENABLE 3D3V_AUX_KBCEC_ENABLE#_G
OFFHi
Low
ONLow
Hi
MODEL ID
3D3V_AUX_KBC
12
R2441
R2441
33KR2F-2-GP
33KR2F-2-GP
BOM Ctrl_Model
BOM Ctrl_Model
MODEL_ID
12
R2442
R2442 100KR2F-L1-GP
100KR2F-L1-GP
3D3V_AUX_KBC
12
R2437
R2437 10KR2F-2-GP
10KR2F-2-GP
BOM Ctr l_VER
BOM Ctr l_VER
PCB_VER
12
R2436
R2436 100KR2F-L1-GP
100KR2F-L1-GP
3D3V_AUX_KBC
12
R2407
R2407
750R2F-L-GP
750R2F-L-GP
ADT_T YPE
12
R2408
R2408 100KR2F-L1-GP
100KR2F-L1-GP
DY
DY
Prevent BIOS data loss solution
PURE_HW_SHUTDOWN#26,40,79
R2409
R2409
EC_ENABLE#
1 2
1KR2F-3-GP
1KR2F-3-GP
PSL
PSL
EC_GPIO47 High Active
PROCHOT_EC
12
R2480
R2480 100KR2J-1-GP
100KR2J-1-GP
2nd = 84.2N702.031
2nd = 84.2N702.031
KBC_PWRBTN#64
Model_ID_BOM Ctrl
PCB VERSION A/D(PIN98) PULL-LOW RESISTOR PULL-HIGH RESISTOR VO LTAGE
LT51 Intel skylake
LC41 Inte l skylake
LC51 Inte l skylake
LC51P Int el skylake 1 00.0K 2.0V
M51
NA 100.0K 1.048V215.0K 64.21535.6DL
PCB VERSION
PCB VERSION A/D(PIN98) PULL-LOW RESISTOR PULL-HIGH RESISTOR VO LTAGE
ADP internal Resis 287ohm
3.3*287/1037=0.91V (65W)
R2499
R2499
1 2
0R0402-PAD
0R0402-PAD
3D3V_AUX_KBC
PURE_HW_SHUTDOWN#
3D3V_AUX_S5
12
R2410
R2410 330KR2J-L-GP
330KR2J-L-GP
EC_ENABLE#_G_1
Q2405
Q2405
G
H_PROCHOT#_EC
D
S
2N7002K-2-GP
2N7002K-2-GP
84.2N702.J31
84.2N702.J31
3D3V_AUX_S5
12
R2477
R2477 10KR2J-3-GP
10KR2J-3-GP
R2484
R2484
1 2
12
R2492
R2492 100KR2J-1-GP
100KR2J-1-GP
100.0KLT41 Intel skylake
100.0K
100.0K
100.0K
100.0K 1.87V
AD_ID 43
100.0KSA
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
SB
SC
-1
SE
SA
12
R2471
R2471 10KR2J-3-GP
10KR2J-3-GP
R2495
R2495
PURE_HW_SHUTDOWN#_B
1 2
10KR2J-3-GP
10KR2J-3-GP
2nd = 84.T3906.E11
2nd = 84.T3906.E11
PSL
PSL
R2411
R2411
EC_ENABLE#_G
1 2
20KR2J-L3-GP
20KR2J-L3-GP
PSL
PSL
R2478
R2478
1 2
0R0402-PAD
0R0402-PAD
KBC_PWRBTN_EC#
470R2J-2-GP
470R2J-2-GP
12
C2423
C2423 SC220P50V2KX-3GP
SC220P50V2KX-3GP
DY
DY
1
10.0K
64.10025.6DL
20.0K
64.20025.L0L
33.0K
64.33025.L0L
47.0K
64.47025.6DL
64.9K
64.64925.6DL
76.8K
64.76825.6DL
10.0K
20.0K
33.0K
47.0K
64.9K
76.8K
100.0K
45W_65W# High: 45W / Low 65W DISCRETE# High: UMA / Low: Discrete
ECRST#
12
E
Q2401
Q2401
B
MMBT3906-4-GP
MMBT3906-4-GP
C
84.T3906.A11
84.T3906.A11
3D3V_AUX_KBC
DY
DY
U2402
U2402
1
GND
3
VDD
2
RESET#
TPS3809K33-2-GP
TPS3809K33-2-GP
3D3V_AUX_S5 3D3V_AUX_KBC
C2406
C2406
1 2
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
PSL
PSL
S
PSL
PSL
G
G
G
Q2402
Q2402
DMP2130L-7-GP
DMP2130L-7-GP
D
D
D
84.02130.031
84.02130.031
2nd = 084.03413.0031
2nd = 084.03413.0031
Q2403
Q2403
G
S5_ENABLE
D
S
2N7002K-2-GP
2N7002K-2-GP
PSL
PSL
84.2N702.J31
84.2N702.J31
H_PROCHOT# 4,44,46
3.0V
2.75V
2.48V
2.24V
3.0V
2.75V
2.48V
2.24VSD
2.0V
1.87V
1.65VReserved
C2424
C2424 SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
DY
DY
Nuvoton KBC PSL Logic
BOM1
BOM1
BOM1
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A1
A1
A1
Tuesday, July 21, 2015
Tuesday, July 21, 2015
Tuesday, July 21, 2015
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
1
Wist ron C orpor ation
Wist ron C orpor ation
Wist ron C orpor ation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
NPCE285
NPCE285
NPCE285
Tesla SKL-U
Tesla SKL-U
Tesla SKL-U
24 102
24 102
24 102
-1
-1
-1
5
SSID = Flash.ROM
U2502
Main
SC
D D
SD
72.25128.0E1Winbond
SPI ROM Equal length need to less than 500mil
3D3V_SPI
12
R2505
R2505
4K7R2J-2-GP
4K7R2J-2-GP
12
DY
DY
R2506
R2506 10KR2J-3-GP
10KR2J-3-GP
4
3
3D3V_SPI
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
2
3D3V_S5
R2501
R2501
0R0402-PAD
0R0402-PAD
12
C2501
C2501
DY
DY
1 2
12
C2502
C2502
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
Test point
3D3V_S5
TP2503
TP2503
1
TPAD14-OP-GP
TPAD14-OP-GP
1
U2502
R2502
R2502
SPI_CS0#
SPI_CS0#_R18,24
SPI_SO_R18,24
SPI0_WP#18
C C
B B
1 2 1 2
33R2J-2-GPR2503 33R2J-2-GPR2503 33R2J-2-GPR2550 33R2J-2-GPR2550
12
0R0402-PAD
0R0402-PAD
C2503
C2503 SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
DY
DY
12
SPI_SO SPI0_WP#_1
U2502
1
CS#
2
SO/SIO1
3
SIO2 GND4SI/SIO0
MX25L12873FM2I-10G-GP
MX25L12873FM2I-10G-GP
72.12873.001
72.12873.001
SCLK
VCC
SIO3
3D3V_SPI
8
SPI_HOLD_0#_1
7
SPI_CLK_R_1
6
SPI_SI0_R_1
5
12
12
C2504
C2504
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
DY
DY
C2505
C2505
DY
DY
1 2 1 2 1 2
33R2J-2-GPR2551 33R2J-2-GPR2551 33R2J-2-GPR2552 33R2J-2-GPR2552 33R2J-2-GPR2553 33R2J-2-GPR2553
SPI_HOLD_0# 18
SPI_CLK_R 18,24 SPI_SI0_R 18,24
SSID = RBATT
SSID = RBATT
RTC_AUX_S5
3
12
C2506
C2506
SC1U10V2KX-L1-GP
A A
5
SC1U10V2KX-L1-GP
83.00040.E81
83.00040.E81
3D3V_AUX_S5
Q2501
Q2501
2
R2504
R2504
RTC_PWR
1 2
1
BAS40CW-GP
BAS40CW-GP
Width=20mils
Test point
AFTP2501AFTE14P-GP AFTP2501AFTE14P-GP
AFTP2502AFTE14P-GP AFTP2502AFTE14P-GP
4
1KR2J-1-GP
1KR2J-1-GP
+RTC_VCC
1
1
+RTC_VCC
RTCCN1
RTCCN1
1
PWR
2
GND
NP1
NP1
NP2
NP2
BAT-AAA-BAT-054-P06-GP-U
BAT-AAA-BAT-054-P06-GP-U
62.70001.061
62.70001.061
1ST = 62.70014.001
1ST = 62.70014.001
2nd = 20.F2316.002
2nd = 20.F2316.002
3rd = 62.70001.061
3rd = 62.70001.061
High Detect Need to Check whether to PD in PCH Side
Q2503
Q2503 DMN5L06K-7-GP
5V_S0
DMN5L06K-7-GP
D S
84.05067.031
84.05067.031
2nd = 084.00138.0A31
2nd = 084.00138.0A31
G
RTC_DET
12
1 2
0R0402-PAD
0R0402-PAD
R2508
R2508 6D2MR2J-GP
6D2MR2J-GP
RTC_PWR
3
R2514
R2514
RTC_DET_R 20
BOM1
BOM1
BOM1
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Numb er Rev
Size Document Numb er Rev
Size Document Numb er Rev A2
A2
A2
Tuesday, July 21, 2015
Tuesday, July 21, 2015
Tuesday, July 21, 2015 Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
Flash(KBC+PCH)/RTC
Flash(KBC+PCH)/RTC
Flash(KBC+PCH)/RTC
Tesla SKL-U
Tesla SKL-U
Tesla SKL-U
1
25 102
25 102
25 102
-1
-1
-1
Main Func = Thermal Sensor
5
3D3V_S0
NCT7718
NCT7718
12
R2605
R2605
3D3V_S0
12
R2601
R2601
NCT7718
NCT7718
10R2F-L-GP
12
C2603
C2603
10R2F-L-GP
12
C2601
C2601 SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
THERM_VDD
THERM_SYS_SHDN#
NCT7718
NCT7718
D D
Layout notice : Both DXN and DXP routing 10 mil trace width and 10 mil spacing.
NCT7718
12
R2602
R2602 NTC-100K-8-GP
NTC-100K-8-GP
METR3904-G-GP
METR3904-G-GP
DY
DY
NCT7718
Q2601
Q2601
C
B
E
84.03904.E11
84.03904.E11
NCT7718
NCT7718
SC470P50V3JN-2GP
SC470P50V3JN-2GP
12
C2602
C2602
P2800_DXN
P2800_DXP
NCT7718
NCT7718
SC2K2P50V2KX-L-GP
SC2K2P50V2KX-L-GP
2.System Sensor, Put on palm rest
2.System Sensor, Put on palm rest
Close to Thermal sensor
3D3V_AUX_KBC
06/11 Delete R2611 & R2621 Connect to 3D3V_AUX_S5
C C
B B
12
TV
TV
12
TV
TV
3D3V_AUX_KBC
TV
TV
TV
TV
R2615
R2615 16KR2F-GP
16KR2F-GP
R2610
R2610 NTC-100K-11-GP-U
NTC-100K-11-GP-U
69.60013.201
69.60013.201
12
12
TBD
TBD
R2616
R2616 16KR2F-GP
16KR2F-GP
R2619
R2619 NTC-100K-11-GP-U
NTC-100K-11-GP-U
69.60013.201
69.60013.201
PU 3D3V_AUX_KBC
12
C2615
C2615 SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
VD_IN1_C
TV
TV
PU 3D3V_AUX_KBC
12
C2617
C2617 SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
VD_IN2_C
TV
TV
R5
18K7R2F-GP
18K7R2F-GP
ALERT#
U2601
U2601
1
VDD
2
D+
3
D­T_CRIT#4GND
NCT7718W-GP
NCT7718W-GP
NCT7718
NCT7718
74.07718.0B9
74.07718.0B9
2ND = 074.00788.00B9
2ND = 074.00788.00B9
Note: Need R1717 PD: Enable Thermal VD Fun. Note: (1) VD_IN1 for System sensor (2) VD_IN2 for CPU sensor
ALERT#
THM_SML1_CLK
8
SCL
THM_SML1_DATA
7
SDA
ALERT#
6 5
Close to CPU chips
VD_IN1 24
12
C2616
C2616 SC100P50V2JN-3GP
SC100P50V2JN-3GP
R2612
R2612
1 2
TV
TV
0R0402-PAD
0R0402-PAD
Close to KBC chips
12
TV
TV
C2618
C2618 SC100P50V2JN-3GP
SC100P50V2JN-3GP
R2620
R2620
1 2
0R0402-PAD
0R0402-PAD
VD_IN2 24
4
THM_SML1_CLK
THM_SML1_DATA
T8=85 degree
3D3V_S0
NCT7718
NCT7718
PURE_HW_SHUTD OWN#24,40,79
1
23
4
RN2601
RN2601 SRN2K2J-5-GP
SRN2K2J-5-GP
84.2N702.A3F
84.2N702.A3F
2nd = 75.00601.07C
2nd = 75.00601.07C
1
2
3 4
R2603
R2603
1 2
DY
DY
R2604
R2604
1 2
DY
DY
NCT7718
NCT7718
Q2602
Q2602 2N7002KDW-G P
2N7002KDW-G P
6
5
0R2J-L-GP
0R2J-L-GP
0R2J-L-GP
0R2J-L-GP
12
R2606
R2606 10KR2J-L-GP
10KR2J-L-GP
DY
DY
3
2
1
*Layout* 15 mil
5V_FAN_S0
KA
D2601
D2601 RB551V30-GP
SML1_SMBCLK 18,24,66,79,90
SML1_SMBDATA 18,24,66,79,90
3D3V_S0
12
R2614
R2614 10KR2J-L-GP
10KR2J-L-GP
FAN_TACH124
THERM_SYS_SHDN#
S
G
12
C2607
C2607
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
DY
DY
Q2603
Q2603
D
2N7002K-2-GP
2N7002K-2-GP
84.2N702.J31
84.2N702.J31
2ND = 84.2N702.031
2ND = 84.2N702.031
3rd = 84.2N702.W31
3rd = 84.2N702.W31
RB551V30-GP
83.R5003.H8H
83.R5003.H8H
2nd = 83.R5003.T8F
2nd = 83.R5003.T8F
FAN1_PWM24
D2602
D2602
FAN_TACH1_C
KA
RB551V30-GP
RB551V30-GP
83.R5003.H8H
83.R5003.H8H
2nd = 83.R5003.T8F
2nd = 83.R5003.T8F
07/31 C2604 Change part number 78.47523.5BL to 78.47522.L4L,
󰾅󰾅󰾅󰾅󳀃󳀃󳀃󳀃
4.uF, 0805,
FAN_TACH1_C
5V_FAN_S0
12
R2613
R2613 10KR2J-L-GP
10KR2J-L-GP
DY
DY
3D3V_S0
12
R2607
R2607 2KR2F-3-GP
2KR2F-3-GP
12
C2604
C2604
SC4D7U25V5KX-L2-GP
SC4D7U25V5KX-L2-GP
󰵖󰵖󰵖󰵖󱍕󱍕󱍕󱍕󳗍󳗍󳗍󳗍󲕸󲕸󲕸󲕸
DY
DY
R2618
R2618
1 2
0R2J-L-GP
0R2J-L-GP
R2617
R2617
1 2
0R0402-PAD
0R0402-PAD
D2603
D2603 BAW56-5-GP
BAW56-5-GP
3
VR_RDY 40,46
12
C2605
C2605 SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
25V
FAN1
FAN1
5
1
2 3 4
6
ACES-CON4-17-GP-U1
ACES-CON4-17-GP-U1
20.F1621.004
20.F1621.004
2nd = 20.F1937.004
2nd = 20.F1937.004
3rd = 020.F0243.0004
3rd = 020.F0243.0004
12
DY
DY
2
83.00056.Q11
83.00056.Q11
2nd = 75.00056.07DDY
2nd = 75.00056.07DDY
1
R2624
R2624 2KR2F-3-GP
2KR2F-3-GP
FAN1_PWM
1
AFTP2601AFTE14P-GP AFTP2601AFTE14P-GP AFTP2602AFTE14P-GP AFTP2602AFTE14P-GP AFTP2603AFTE14P-GP AFTP2603AFTE14P-GP AFTP2604AFTE14P-GP AFTP2604AFTE14P-GP
3D3V_S03D3V_S0
12
R2625
R2625 2KR2F-3-GP
2KR2F-3-GP
DY
DY
VD_OUT1# 24
VD_OUT2# 24
1
1
1
FAN_TACH1_C 5V_FAN_S0
5V_S0 5V_FAN_S05V_FAN_S0
R2630
R2630
1 2
0R0603-PAD
0R0603-PAD
Thermal config
Function LOCATION
Thermal VD NCT7718W
U2601 Q2601 Q2602 RN2601 R2601 R2605 C2601 C2602 C2603
DY DY DY DY
DY DY DY ASM DY
ASM ASM ASM ASM ASMDY ASM ASM
ASM
R2610 R2619 R2615 R2616
A A
R2612 R2620 R2624 R2625 C2615 C2617 C2616 C2618 D2603
R1717
ASM ASM ASM ASM ASM ASM ASM ASM ASM ASM ASM ASM ASM
5
DY DY DY DY DY DY DY DY DY DY DY DY DY
DYASM
4
3
2
BOM1
BOM1
BOM1
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
THERMAL NCT7718W/Fan
THERMAL NCT7718W/Fan
THERMAL NCT7718W/Fan
Size Document Numb er Rev
Size Document Numb er Rev
Size Document Numb er Rev A2
A2
A2
Tuesday, July 21, 2015
Tuesday, July 21, 2015
Tuesday, July 21, 2015 Date: Sheet of
Date: Sheet of
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
Tesla SKL-U
Tesla SKL-U
Tesla SKL-U
1
26 102
26 102
26 102
-1
-1
-1
5
4
3
2
1
R2719
R2719
1 2
0R0603-PAD
0R0603-PAD
1 2
1 2
DY
DY
1 2
DY
DY
1 2
AUD_5VD5V_S0
12
C2706
C2706
AUD_5VA5V_S0
12
C2727
C2727
SC10U6D3V3MX-L-GP
SC10U6D3V3MX-L-GP
ALC_AGND
AUD_3V3_S53D3V_S5
12
C2712
C2712
SC10U6D3V3MX-L-GP
SC10U6D3V3MX-L-GP
ALC_AGND
AUD_3VD3D3V_S0
12
C2703
C2703
SC10U6D3V3MX-L-GP
SC10U6D3V3MX-L-GP
AUD_1D8VD
12
C2710
C2710
SC10U6D3V3MX-L-GP
SC10U6D3V3MX-L-GP
ALC_AGND
12
C2716
C2716
DY
SC10U6D3V3MX-L-GP
SC10U6D3V3MX-L-GP
DY
SC10U6D3V3MX-L-GP
SC10U6D3V3MX-L-GP
Tied at one point only under Codec or near the Codec
Near AVDD1 and AVDD2 power source input
SA_ESD
ALC_AGND
3D3V_S5
12
SCD1U25V2KX-L-GP
SCD1U25V2KX-L-GP
C2707
C2707
12
SCD1U25V2KX-L-GP
SCD1U25V2KX-L-GP
C2708
C2708
C2713
C2713
SC4D7U6D3V3KX-L-GP
SC4D7U6D3V3KX-L-GP
AUD_1D8VD
12
HDA_CODEC_BITCLK19
HDA_CODEC_SYNC19
ALC_AGND
ALC_AGND
HP_DET#29,66
AUD_3VD
C2701
C2701
12
SC1U10V2KX-L1-GP
SC1U10V2KX-L1-GP
12
SCD1U25V2KX-L-GP
SCD1U25V2KX-L-GP
C2702
C2702
Place close to pin1
AUD_5VA
12
C2709
C2709 SC2D2U10V3KX-L-GP
SC2D2U10V3KX-L-GP
Place close to pin26
ALC_AGND
AUD_1D8VD
12
C2711
C2711 SC4D7U6D3V3KX-L-GP
SC4D7U6D3V3KX-L-GP
ALC_AGND
AUD_3V3_S5
AUD_5VD
AUD_3VD
12
SCD1U25V2KX-L-GP
SCD1U25V2KX-L-GP
C2714
C2714
ER2723
ER2723
1 2
DMIC_DATA55 DMIC_CLK55
R2713 0R0402-PADR2713 0R0402-PAD
1 2
1 2
C2722 SC22P50V2JN-L-GPC2722 SC22P50V2JN-L-GP
R2708 100KR2J-L-GPR2708 100KR2J-L-GP
1 2
R2721 200KR2F-L-3-GPR2721 200KR2F-L-3-GP
1 2
R2708 power shoul d follow DVDD (pin1) power rail. If DVDD=3.3V, R7 power source should be change to 3.3V
100R2J-2-GP
100R2J-2-GP
1 2
ER2720 100R2J-2-GPER2720 100R2J- 2-GP
HDA_CODEC_SDOUT19
HDA_SDIN019
R2702 0R0402-PADR2702 0R0402-PAD
1 2
C2704 SCD1U25V2KX-L-GPC2704 SCD1U25V2KX-L-GP
1 2
Place close to pin8
C2715 SC1U10V2KX-L1-GPC2715 SC1U10V2KX-L1-GP
1 2
C2717 SC1U10V2KX-L1-GPC2717 SC1U10V2KX-L1-GP
1 2
C2718 SC4D7U6D3V3KX-L-GPC2718 SC4D7U6D3V3KX-L-GP
1 2
C2719 SC4D7U6D3V3KX-L-GPC2719 SC4D7U6D3V3KX-L-GP
1 2
C2720 SC4D7U6D3V3KX-L-GPC2720 SC4D7U6D3V3KX-L-GP
1 2
1 2
C2721 SC22P50V2JN-L-GP
C2721 SC22P50V2JN-L-GP
DY
DY
R2710
R2710
1 2
0R0402-PAD
0R0402-PAD
HDA_CODEC_BITCLK_C
AUD_SD#
ALC233_SENSE_A
DVDD_IO
VREF CPVEE
LDO1_CAP LDO2_CAP LDO3_CAP
DMIC_DATA_C
DMIC_CLK_C
AC97_DATIN
U2701
U2701
1
DVDD
8
DVDD-IO
20
AVDD1
33
AVDD2
16
VD33STB
34
PVDD1
39
PVDD2
29
CPVDD
22
VREF
27
CPVEE
21
LDO1-CAP
32
LDO2-CAP
6
LDO3-CAP
2
GPIO0/DMIC-DATA12
3
GPIO1/DMIC-CLK
4
SDATA-OUT
7
SDATA-IN
5
BCLK
9
SYNC
10
DC_DET
40
PDB
12
HP/LINE1-JD(JD1)
ALC3240-CG-GP
ALC3240-CG-GP
071.03240.0003
071.03240.0003
PCBEEP
MIC2-L(PORT-F-L)/RING2
MIC2-R(PORT-F-R)/SLEEVE
MIC2-CAP
LINE1-R(PORT-C-R)
LINE1-L(PORT-C-L)
SPK-OUT-LP
SPK-OUT-LN
SPK-OUT-RP SPK-OUT-RN
HPOUT-L(PORT-I-L)
HPOUT-R(PORT-I-R)
MIC2-VREFO
LINE1-VREFO-L
AVSS1 AVSS2
RN2701
12
ALC_AGND
R2709
R2709 10KR2J-3-GP
10KR2J-3-GP
RN2701
1 2 3
SRN1KJ-7-GP
SRN1KJ-7-GP
4
SPKR 19
KBC_BEEP 24
AUDIO_PC_BEEP
11
13 14 15
17 18
35 36
38 37
HP_OUT_L_AUD
25
HP_OUT_R_AUD
26
AUD_CBN
28
CBN
AUD_CBP
30
CBP
23 24
19 31
41
GND
C2723
C2723
MIC2
C2725 SC1U10V2KX-L1-GPC2725 SC1U10V2KX-L1-GP
1 2
1 2
RN2702
RN2702
2 3 1
SRN47J-7-GP
SRN47J-7-GP
AUDIO_BEEP
SCD1U25V2KX-L-GP
SCD1U25V2KX-L-GP
4
ALC_AGNDALC_AGND
C2724 SC4D7U6D3V3KX-L-GPC2724 SC4D7U6D3V3KX-L-GP
1 2
AUD_SPK_L+ 29
AUD_SPK_L- 29
SPK 4 40mils
AUD_SPK_R+ 29 AUD_SPK_R- 29
HP_OUT_L 29,66
HP_OUT_R 29,66
R2716 2K2R2F-GPR2716 2K2R2F-GP
1 2
R2717 2K2R2F-GPR2717 2K2R2F-GP
1 2
ALC_AGND
RING2 29,66 SLEEVE 29,66
SLEEVE RING2MIC2V
R2703
R2703
1 2
12
0R0603-PAD
0R0603-PAD
C2705
C2705
SC1U10V2KX-L1-GP
SC1U10V2KX-L1-GP
D D
MOAT
R2726
R2726
1 2
0R0603-PAD
0R0603-PAD
MOAT
R2705
R2705
1 2
0R0603-PAD
0R0603-PAD
R2701
R2701
1 2
0R0603-PAD
0R0603-PAD
MOAT
C C
1D8V_S0
R2704
R2704
1 2
0R0603-PAD
0R0603-PAD
G2701 GAP-CLOSEG2701 GAP-CLOSE
G2702 GAP-CLOSEG2702 GAP-CLOSE
B B
0R3J-0-U-GP
0R3J-0-U-GP
ER2722
ER2722
0R3J-0-U-GP
0R3J-0-U-GP
ER2721
ER2721
Q9002
Q9002
G
DY
DY
DS
T2N7002BK-GP
T2N7002BK-GP
R2724 0R2J-2-GP
R2724 0R2J-2-GP
AMP_MUTE#24
HDA_CODEC_RST#19
FAE HDA_RST#_CODEC: High=1.8V
A A
Low=0V this signal might cause AUD_SD# always low when R2710=0ohm You should add level shift on HDA_RST#_CODEC signal when Codec PIN9 DVDDI O= 1.5V.
1 2
DY
DY
R2723 0R2J-2-GP
R2723 0R2J-2-GP
1 2
DY
DY
R2725 0R0402-PADR2725 0R0402-PAD
1 2
AUD_PD#_2
AUD_PD#_1
5
D2701
D2701
BAW56-5-GP
BAW56-5-GP
2
DY
DY
1
AUD_3VD
12
R2722
R2722 1KR2J-1-GP
1KR2J-1-GP
DY
DY
3
AUD_SD#
12
R2718
R2718 10KR2J-L-GP
10KR2J-L-GP
BOM1
BOM1
BOM1
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Numb er Rev
Size Document Numb er Rev
Size Document Numb er Rev A2
A2
A2
Tuesday, July 21, 2015
Tuesday, July 21, 2015
Tuesday, July 21, 2015 Date: Sheet of
Date: Sheet of
4
3
2
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
Audio Codec ALC3234
Audio Codec ALC3234
Audio Codec ALC3234
Tesla SKL-U
Tesla SKL-U
Tesla SKL-U
1
27 102
27 102
27 102
-1
-1
-1
5
D D
C C
4
3
2
1
B B
A A
BOM1
BOM1
BOM1
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A1
A1
A1
Tuesday, July 21, 2015
Tuesday, July 21, 2015
Tuesday, July 21, 2015
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
1
Wist ron C orpor ation
Wist ron C orpor ation
Wist ron C orpor ation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Reserved
Reserved
Reserved
Tesla SKL-U
Tesla SKL-U
Tesla SKL-U
28 102
28 102
28 102
-1
-1
-1
5
4
3
2
1
INTERNAL STEREO SPEAKERS
D D
R2903 0R0603-PADR2903 0R0603-PAD
AUD_SPK_R+27
AUD_SPK_R-27
Place these EMI components close to speaker connecto r.
Only needed if speaker connector is physically far f rom audio codec. When in doubt, it's always a good idea to have population option.
AUD_SPK_L+27
C C
AUD_SPK_L-27
1 2
R2904
R2904
1 2
0R0603-PAD
0R0603-PAD
R2905 0R0603-PADR2905 0R0603-PAD
1 2
R2906
R2906
1 2
0R0603-PAD
0R0603-PAD
RIGHT SIDE
12
12
C2902
C2902
C2903
C2903
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
LEFT SIDE
12
12
C2904
C2904
C2905
C2905
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
AUD_SPK_R+_C
AUD_SPK_R-_C
ACES-CON4-17-GP-U1
ACES-CON4-17-GP-U1
AUD_SPK_L+_C
AUD_SPK_L-_C
2nd = 20.F1937.004
2nd = 20.F1937.004
3rd = 020.F0243.0004
3rd = 020.F0243.0004
08/12 SPK1 20.F2348.007 Change to 20.F1621.004
06/12 SPK1
󱋨󱋨󱋨󱋨󲙵󲙵󲙵󲙵󳀃󳀃󳀃󳀃
4Pin,
󲌤󲌤󲌤󲌤
7 pin
SPK1
SPK1
5
1
2 3 4
6
20.F1621.004
20.F1621.004
󲋮󲋮󲋮󲋮
Hall Sensor
󴥓󴥓󴥓󴥓󴖨󴖨󴖨󴖨
HP_OUT_R
1
AFTP2913AFTE14P-GP AFTP2913AFTE14P-GP AFTP2914AFTE14P-GP AFTP2914AFTE14P-GP
AFTP2915AFTE14P-GP AFTP2915AFTE14P-GP AFTP2916AFTE14P-GP AFTP2916AFTE14P-GP AFTP2917AFTE14P-GP AFTP2917AFTE14P-GP
AFTP2918AFTE14P-GP AFTP2918AFTE14P-GP
R2907
R2907
1 2
0R0402-PAD
0R0402-PAD
R2908
R2908
1 2
0R0402-PAD
0R0402-PAD
R2909 0R2J-2-GP
R2909 0R2J-2-GP
1 2
DY
DY
R2910 0R2J-2-GP
R2910 0R2J-2-GP
1 2
DY
DY
HP_OUT_L
1
SLEEVE
1
RING2
1
HP_DET#
1
1
ALC_AGND
HP_OUT_R 27,66 HP_OUT_L 27,66
SLEEVE 27,66 RING2 27,66 HP_DET# 27,66
ALC_AGND
AUD_SPK_L+_C
1
AFTP2910AFTE14P-GP AFTP2910AFTE14P-GP AFTP2911AFTE14P-GP AFTP2911AFTE14P-GP
AFTP2912AFTE14P-GP AFTP2912AFTE14P-GP
Place these EMI components close to speaker connecto r.
B B
A A
5
AUD_SPK_L-_C
1
1
Only needed if speaker connector is physically far f rom audio codec. When in doubt, it's always a good idea to have population option.
DY
DY
12
ED2901
ED2901
ESD5B5D0ST1G-GP-U
ESD5B5D0ST1G-GP-U
DY
DY
12
ED2902
ED2902
ESD5B5D0ST1G-GP-U
ESD5B5D0ST1G-GP-U
4
AFTP2908AFTE14P-GP AFTP2908AFTE14P-GP AFTP2909AFTE14P-GP AFTP2909AFTE14P-GP
AUD_SPK_R+_C
1
AUD_SPK_R-_C
1
12
12
ED2904
ED2904
ED2903
ED2903
DY
DY
DY
DY
ESD5B5D0ST1G-GP-U
ESD5B5D0ST1G-GP-U
ESD5B5D0ST1G-GP-U
ESD5B5D0ST1G-GP-U
BOM1
BOM1
BOM1
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3
Tuesday, July 21, 2015
Tuesday, July 21, 2015
Tuesday, July 21, 2015
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
Audio IO
Audio IO
Audio IO
Tesla SKL-U
Tesla SKL-U
Tesla SKL-U
29 102
29 102
29 102
1
-1
-1
-1
5
4
3
2
1
Main Func = Audio
D D
C C
(Blanking)
B B
BOM1
BOM1
BOM1
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
Reserved
Reserved
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A4
A4
A4
Tuesday, July 21, 2015
Tuesday, July 21, 2015
Tuesday, July 21, 2015
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
2
Reserved
Tesla SKL-U
Tesla SKL-U
Tesla SKL-U
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
-1
-1
30 102
30 102
30 102
1
-1
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