Lenovo IdeaPad 110-15xxx Schematic

A

1 1

B

C

D

E

LCFC Confidential

NANO G ACL CG521 M/B Schematics Document

2 2

AMD FP4 Carrizo L SOC with DDRIIIL

AMD R16M-M1-30

2016-02-24

3 3

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

A

B

REV:1.0

2013/08/15

2013/08/15

2013/08/15

C

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2013/08/15

2013/08/15

2013/08/15

D

Title

Title

Title

Cover Page

Cover Page

Cover Page

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Tuesday, March 08, 2016

Tuesday, March 08, 2016

Tuesday, March 08, 2016

CG521

CG521

CG521

E

of

of

of

150

150

150

1.0

1.0

1.0

A

B

C

D

E

LCFC confidential

File Name : CG521

AMD R16M-M1-30
S3 Package: 23mmX23mm

Page18~24

1 1

VRAM 256*16
DDR3L*4 2GB

Page14~22

PCI-Express

4x Gen2

PEG 0~3

Memory BUS (DDR3L)
Single Channel B

1.35V DDR3L 1600 MT/s
1333MT/s

DDR3L-SO-DIMM X1

Page 12

UP TO 8G

HDMI Conn.

Page25

Int. Camera

USB2.0 Port5

eDP Conn

Page23

2 2

SATA HDD

Page33

HDMI x4 Lane Port1

eDP x2 Lane
USB2.0 1x

SATA Port0

SATA Gen3

AMD FP4 APU
Carrizo L 15W

(Integrated FCH)

BGA-968

USB 3.0 1x

USB 2.0 2x

USB2.0 1x

37mm*29mm

SATA ODD

Page33

RJ45 Conn.

Page29

3 3

LAN Realtek

RTL8106E

Page28

SATA Port1

PCIe Port2

SATA Gen1

PCIe 1x

HD Audio

USB 2.0 1x
PCIe 1x

SPI BUS

Page4~11

USB Left

USB 2.0 Port0

USB 2.0 Port7
USB 3.0 Port3

JUSB1

JUSB2

Page32

Cardreader Realtek
RTS5170

NGFF Card
WLAN&BT
Key E

Page31

USB2.0 Port2

PCIe Port1
USB2.0 Port4

SPI ROM
8MB

Page08

SD/MMC Conn.

USB Board

TPM

Codec

Realtek ALC3248

Page34

Int. MIC HP&Mic Combo Conn.

SPK Conn.

Page34

Page34Page34

EC
ITE IT8586E-LQFP

Page35

Thermistor

reserve

Page30

Page30

Sub-board ( for 15")

Touch Pad Int.KBD

4 4

A

B

Page36 Page36

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

C

Thermal Sensor
NCT7718W

Page30

2013/08/15

2013/08/15

2013/08/15

reserve

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

2013/08/15

2013/08/15

2013/08/15

ODDBoard

Title

Title

Title

Block Diagram

Block Diagram

Block Diagram

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Tuesday, March 08, 2016

Tuesday, March 08, 2016

Date: Sheet

Date: Sheet

Date: Sheet

Tuesday, March 08, 2016

CG521

CG521

CG521

E

of

of

of

250

250

250

1.0

1.0

1.0

A

B

C

D

E

Voltage Rails

power
plane

1 1

State

S0

S3

2 2

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery
don't exist

SMBUS Control Table

EC_SMB_CK1
EC_SMB_DA1

3 3

EC_SMB_CK2
EC_SMB_DA2

APU_SCLK0
APU_SDATA0

IT8586E

+3VALW

IT8586E

EC SM Bus1 address

Device

Battery
Charger

APU SM Bus address

4 4

Device Address

DDR DIMMA
DDR DIMMB
WLAN

( O --> Means ON , X --> Means OFF )

SOURCE

+3VS

APU

+3VS

B+
(+20VSB)

+3VL

+5VLP

O

O

O

O

X

GPU BATT SODIMM WLAN Thermal

X

V

+3VS_VGA

XXX X

+5VALW

+3VALW
(+3VALW_APU)

+1.8VALW

+0.95VALW

+0.775VALW

+1.35V
(+VSYSMEM_APU)

O

O

O

X

O

XX

X

XX X

X

X

X

VV

EC SM Bus2 address

Address

0X16 1001_100xb(reserve)

0001 0010 b

0xA0h

0xA2h

RSVD

A

Device

Thermal Sensor
GPU
APU SB-TSI

HDMI Convert

Address

0x41(default)

releate to F3x1E4[SbiAddr] or Address Select Pins setting

RSVD

+5VS
+3VS
+1.8VS
+1.5VS
+0.95VS
+0.675VS
+APU_CORE
+APU_CORE_NB
+APU_GFX
+VGA_CORE
+3VGS
+1.8VGS
+1.35VGS
+0.95VGS

OO

X

STATE

S0 (Full ON)

S1 (Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SIGNAL

SLP_S3# SLP_S5# +VALW +V +VS Clock

HIGH HIGH

LOW

LOW LOW

HIGHHIGH

HIGHLOW

LOW

ON

ON

ON

ON

ON

USB Port Table for CarrizoL

USB 3.0USB 2.0 Port Port device

0

RIGHT USB (2.0)

1

EHCI0

EHCI1

xHCI

0
1

2
3
4
5
6
7

N/A
Card Reader
Touch screen
Blue Tooth
Camera
LEFT USB (3.0)
LEFT USB (3.0)

ONONON ON

ON

OFF

ON

OFF

OFF

OFF

OFF

LOW

OFF

OFF

OFF

USB Port Table for Carrizo

X

USB 3.0USB 2.0 Port

EHCI0

APUIT8586E

Sensor

X

X

XV

APU_SIC
APU_SID

V

1.8VS for CZ
3VS for CZL

Charger

X

V

HDMI
Convert
reserve

V

X

X

V

X

X

xHCI 2

PCIE PORT LIST

GPP

3

Port Device

0
1
2
3
0

GFX

1
2
3
4
5
6
7

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

C

2013/08/15

2013/08/15

2013/08/15

Port device

0

RIGHT USB (2.0)

1

N/A

2

Card Reader

3

Touch screen

4

Blue Tooth

5

Camera

6

LEFT USB (3.0)

7

LEFT USB (3.0)

N/A
WLAN
LAN
N/A

CZL
GPU

N/A

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

CZ
GPU

Deciphered Date

Deciphered Date

Deciphered Date

VRAM

D

BOARD
Config.

BOARD_ID0 Function
0: 14''
1: 15'' 1: UMA

BOM Structure Table

@

ME@
14@
15@

EMC@

EMC_NS@

EMC_PX@

EMC_CZ@

EMC_15@

RF_NS@

RF_PXNS@

UMA@

PX@

EXO@

TOPAZ@

2013/08/15

2013/08/15

2013/08/15

TPM@

AOAC@

HDT@

TS@

CZ@

CZL@

CZPX@

CZLPX@

S4GX4@

M4GX4@

H4GX4@

S2GX4@

M2GX4@

H2GX4@

S2G@

M2G@

H2G@

S1G@

M1G@

H1G@

CZLUMA@

CZUMA@

SIVCD@

HDMI@

AOAC support part

Title

Title

Title

Notes List

Notes List

Notes List

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

BOARD_ID1
0: Dis

BOARD_ID2

BTO ItemBOM Structure

Not stuff
Connector
For 14" part
For 15" part
EMC Part
EMC reserve Part
EMC GPU part
EMC Carrizo APU part
EMC 15 part
RF reserve Part
RF GPU reserve part
UMA SKU ID part
Discrete GPU SKU part
EXO GPU Part
TOPAZ GPU Part
TPM part

HDT Debug part
Touch screen part
Carrizo Part
CarrizoL part
Carrizo Discrete Part
CarrizoL Discrete Part
X76 SAMSUNG 2G
X76 MICRON 2G
X76 HYNIX 2G
X76 SAMSUNG 1G
X76 MICRON 1G
X76 HYNIX 1G
SAMSUNG 2G
MICRON 2G
HYNIX 2G
SAMSUNG 1G
MICRON 1G
HYNIX 1G
CarrizoL UMA Part
Carrizo UMA Part
SIV COST down material

HDMI Logo

CG521

CG521

Wednesday, February 24, 2016

Wednesday, February 24, 2016

Wednesday, February 24, 2016

CG521

E

1.0

1.0

1.0

of

of

of

350

350

350

5

D D

PCIE_PRX_DTX_P1{31}

WLAN
LAN

C C

PCIE_PRX_DTX_N1{31}
PCIE_PRX_DTX_P2{28}

PCIE_PRX_DTX_N2{28}

+0.95VS +0.95VS

1 2

RC1 1.69K_0402_1%CZL@

with BOM strcture control, RC1 change to 196_0402_1% for Stoney and Carrizo

PCIE_CRX_GTX_P0{15}
PCIE_CRX_GTX_N0{15}

PCIE_CRX_GTX_P1{15}
PCIE_CRX_GTX_N1{15}

PCIE_CRX_GTX_P2{15}
PCIE_CRX_GTX_N2{15}

PCIE_CRX_GTX_P3{15}
PCIE_CRX_GTX_N3{15}

CarrizoL not support GFX4-GFX7

B B

4

PCIE_PRX_DTX_P1
PCIE_PRX_DTX_N1

PCIE_PRX_DTX_P2
PCIE_PRX_DTX_N2

P_TX_ZVDD

PCIE_CRX_GTX_P0
PCIE_CRX_GTX_N0

PCIE_CRX_GTX_P1
PCIE_CRX_GTX_N1

PCIE_CRX_GTX_P2
PCIE_CRX_GTX_N2

PCIE_CRX_GTX_P3
PCIE_CRX_GTX_N3

U10

P10

L10

U9
T6

T5
T9

T8
P7

P6
U7

P9
N6

N5
N9

N8
L7

L6

L9
K6

K5
K9

K8

J7
J6

P_GPP_RXP0
P_GPP_RXN0

P_GPP_RXP1
P_GPP_RXN1

P_GPP_RXP2
P_GPP_RXN2

P_GPP_RXP3
P_GPP_RXN3

P_ZVDDP

P_GFX_RXP0
P_GFX_RXN0

P_GFX_RXP1
P_GFX_RXN1

P_GFX_RXP2
P_GFX_RXN2

P_GFX_RXP3
P_GFX_RXN3

P_GFX_RXP4
P_GFX_RXN4

P_GFX_RXP5
P_GFX_RXN5

P_GFX_RXP6
P_GFX_RXN6

P_GFX_RXP7
P_GFX_RXN7

@

UC2B

PCIE

P_GPP_TXP0
P_GPP_TXN0

P_GPP_TXP1
P_GPP_TXN1

P_GPP_TXP2
P_GPP_TXN2

P_GPP_TXP3
P_GPP_TXN3

P_ZVSS/P_RX_ZVDDP

P_GFX_TXP0
P_GFX_TXN0

P_GFX_TXP1
P_GFX_TXN1

P_GFX_TXP2
P_GFX_TXN2

P_GFX_TXP3
P_GFX_TXN3

P_GFX_TXP4
P_GFX_TXN4

P_GFX_TXP5
P_GFX_TXN5

P_GFX_TXP6
P_GFX_TXN6

P_GFX_TXP7
P_GFX_TXN7

FP4 REV 0.93

AMD-CARRIZO_FP4-BGA968

3

R1
R2

PCIE_PTX_DRX_P1

R4

PCIE_PTX_DRX_N1

R3

PCIE_PTX_DRX_P2

N1

PCIE_PTX_DRX_N2

N2
N4

N3

P_RX_ZVDD

U6

PCIE_CTX_GRX_P0

M2

PCIE_CTX_GRX_N0

M1

PCIE_CTX_GRX_P1

L1

PCIE_CTX_GRX_N1

L2

PCIE_CTX_GRX_P2

L4

PCIE_CTX_GRX_N2

L3

PCIE_CTX_GRX_P3

J1

PCIE_CTX_GRX_N3

J2
J4

J3

with BOM strcture control, CC5--CC12 change to 0.22uf for STN

H2
H1

G1
G2

G4
G3

1 2

CC1 0.1U_0201_6.3V6-K

1 2

CC2 0.1U_0201_6.3V6-K

1 2

CC3 0.1U_0201_6.3V6-K

1 2

CC4 0.1U_0201_6.3V6-K

1 2
1 2

CC5 0.1U_0201_6.3V6-KCZLPX@
CC6 0.1U_0201_6.3V6-KCZLPX@

CC7 0.1U_0201_6.3V6-KCZLPX@
CC8 0.1U_0201_6.3V6-KCZLPX@

CC9 0.1U_0201_6.3V6-KCZLPX@
CC10 0.1U_0201_6.3V6-KCZLPX@

CC11 0.1U_0201_6.3V6-KCZLPX@
CC12 0.1U_0201_6.3V6-KCZLPX@

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

2

RC21K_0402_1% CZL@
RC3196_0402_1% STN@

PCIE_PTX_C_DRX_P1

PCIE_PTX_C_DRX_N1

PCIE_PTX_C_DRX_P2
PCIE_PTX_C_DRX_N2

PCIE_CTX_C_GRX_P0
PCIE_CTX_C_GRX_N0

PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_N1

PCIE_CTX_C_GRX_P2
PCIE_CTX_C_GRX_N2

PCIE_CTX_C_GRX_P3
PCIE_CTX_C_GRX_N3

PCIE_PTX_C_DRX_P1 {31}
PCIE_PTX_C_DRX_N1 {31}

PCIE_PTX_C_DRX_P2 {28}
PCIE_PTX_C_DRX_N2 {28}

PCIE_CTX_C_GRX_P0 {15}
PCIE_CTX_C_GRX_N0 {15}

PCIE_CTX_C_GRX_P1 {15}
PCIE_CTX_C_GRX_N1 {15}

PCIE_CTX_C_GRX_P2 {15}
PCIE_CTX_C_GRX_N2 {15}

PCIE_CTX_C_GRX_P3 {15}
PCIE_CTX_C_GRX_N3 {15}

1

WLAN
LAN

GPUGPU

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2013/08/15

2013/08/15

2013/08/15

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2013/08/15

2013/08/15

2013/08/15

2

Title

FP4 (PCIE I/F)

FP4 (PCIE I/F)

FP4 (PCIE I/F)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Wednesday, February 24, 2016

Wednesday, February 24, 2016

Wednesday, February 24, 2016

CG521

CG521

CG521

450

450

450

1

1.0

1.0

1.0

5

CarrizoL not support ChannelA

4

3

DDRB_DQS[0..7]{12}
DDRB_DQS#[0..7]{12}

2

DDRB_DQS[0..7]
DDRB_DQS#[0..7]

1

UC2A

AE28

MA_ADD0

Y27

MA_ADD1

Y29

MA_ADD2

Y26

MA_ADD3

D D

C C

B B

+MEM_VREF

+1.35V

RC4

1K_0402_1%

A A

RC5

1K_0402_1%

W28

MA_ADD4

W29

MA_ADD5

W26

MA_ADD6

U29

MA_ADD7

W25

MA_ADD8

U26

MA_ADD9

AG29

MA_ADD10

U27

MA_ADD11

T28

MA_ADD12

AK26

MA_ADD13

T26

MA_ADD14/MA_BG1

T25

MA_ADD15/MA_ACT_L

AG26

MA_BANK0

AG27

MA_BANK1

T29

MA_BANK2/MA_BG0

E19

MA_DM0

D21

MA_DM1

K21

MA_DM2

F29

MA_DM3

AP28

MA_DM4

AV26

MA_DM5

AR22

MA_DM6

BC22

MA_DM7

K29

MA_DM8

H19

MA_DQS_H0

G19

MA_DQS_L0

B22

MA_DQS_H1

A22

MA_DQS_L1

F23

MA_DQS_H2

E23

MA_DQS_L2

G27

MA_DQS_H3

F27

MA_DQS_L3

AP25

MA_DQS_H4

AP26

MA_DQS_L4

AW27

MA_DQS_H5

AV27

MA_DQS_L5

AV22

MA_DQS_H6

AU22

MA_DQS_L6

BA21

MA_DQS_H7

AY21

MA_DQS_L7

L27

MA_DQS_H8

L26

MA_DQS_L8

AE25

MA_CLK_H0

AE26

MA_CLK_L0

AD26

MA_CLK_H1

AD27

MA_CLK_L1

AB28

MA_CLK_H2

AB29

MA_CLK_L2

AB25

MA_CLK_H3

AB26

MA_CLK_L3

N29

MA_RESET_L

AE29

MA_EVENT_L

P27

MA_CKE0

P29

MA_CKE1

AK27

MA0_ODT0

AL26

MA0_ODT1

AH25

MA1_ODT0

AL25

MA1_ODT1

AH26

MA0_CS_L0

AL29

MA0_CS_L1

AH29

MA1_CS_L0

AL28

MA1_CS_L1

AG24

MA_RAS_L/MA_RAS_L_ADD16

AK29

MA_CAS_L/MA_CAS_L_ADD15

AH28

MA_WE_L/MA_WE_L_ADD14

B19

MA_VREFDQ

T32

M_VREF

@

12

@

12

1

2

.47U_0402_6.3V6K

CC13

5

MEMORY A

MA_ZVDDIO_MEM_S

FP4 REV 0.93

AMD-CARRIZO_FP4-BGA968

+MEM_VREF

CC14 0.1U_0201_6.3V6-K

1

1

CC15
1000P_0201_50V7-K

2

2

MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7

MA_DATA8

MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15

MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23

MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31

MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39

MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47

MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55

MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63

MA_CHECK0
MA_CHECK1
MA_CHECK2
MA_CHECK3
MA_CHECK4
MA_CHECK5
MA_CHECK6
MA_CHECK7

H17
J17
F20
H20
E17
F17
K18
E20

A21
C21
C23
D23
B20
B21
B23
A23

G22
H22
E25
G25
J20
E22
H23
J23

F26
E27
J26
J27
H25
E26
G28
G29

AN26
AP29
AR26
AP24
AN29
AN27
AR29
AR27

AU26
AV29
AU25
AW25
AU29
AU28
AW26
AT25

AV23
AW23
AV20
AW20
AR23
AT23
AR20
AT20

BB23
BB22
BB20
AY19
BA23
BC23
BC21
BB21

K26
K28
N26
N28
J29
K25
L29
N25

AD29

MEM_MB_RST#{12}

+1.35V

1 2

RC9 1K_0402_5%

4

DDRB_MA[15..0]{12}

DDRB_BS0#{12}
DDRB_BS1#{12}
DDRB_BS2#{12}

DDRB_DM[7..0]{12}

1

TC20@

1

TC8@

1

TC9@

DDRB_CLK0{12}
DDRB_CLK0#{12}
DDRB_CLK1{12}
DDRB_CLK1#{12}

1 2

RC240 10_0402_5%

MEM_MB_EVENT#{12}

DDRB_CKE0{12}
DDRB_CKE1{12}

DDRB_ODT0{12}
DDRB_ODT1{12}

DDRB_CS0#{12}
DDRB_CS1#{12}

DDRB_RAS#{12}
DDRB_CAS#{12}
DDRB_WE#{12}

APU_M_VREFDQ{12}

MEM_MB_EVENT#

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Issued Date

Issued Date

Issued Date

3

DDRB_MA0
DDRB_MA1
DDRB_MA2
DDRB_MA3
DDRB_MA4
DDRB_MA5
DDRB_MA6
DDRB_MA7
DDRB_MA8
DDRB_MA9
DDRB_MA10
DDRB_MA11
DDRB_MA12
DDRB_MA13
DDRB_MA14
DDRB_MA15

DDRB_BS0#
DDRB_BS1#
DDRB_BS2#

DDRB_DM0
DDRB_DM1
DDRB_DM2
DDRB_DM3
DDRB_DM4
DDRB_DM5
DDRB_DM6
DDRB_DM7
DDRB_DM8

DDRB_DQS0
DDRB_DQS#0
DDRB_DQS1
DDRB_DQS#1
DDRB_DQS2
DDRB_DQS#2
DDRB_DQS3
DDRB_DQS#3
DDRB_DQS4
DDRB_DQS#4
DDRB_DQS5
DDRB_DQS#5
DDRB_DQS6
DDRB_DQS#6
DDRB_DQS7
DDRB_DQS#7
DDRB_DQS8
DDRB_DQS#8

DDRB_CLK0
DDRB_CLK0#
DDRB_CLK1
DDRB_CLK1#

MEM_MB_RST#_R
MEM_MB_EVENT#

DDRB_CKE0
DDRB_CKE1

DDRB_ODT0
DDRB_ODT1

DDRB_CS0#
DDRB_CS1#

DDRB_RAS#
DDRB_CAS#
DDRB_WE#

APU_M_VREFDQ

AG31

MB_ADD0

AC30

MB_ADD1

AC31

MB_ADD2

AB32

MB_ADD3

AA32

MB_ADD4

AA33

MB_ADD5

AA31

MB_ADD6

Y33

MB_ADD7

AA30

MB_ADD8

W32

MB_ADD9

AG32

MB_ADD10

Y32

MB_ADD11

W33

MB_ADD12

AL31

MB_ADD13

W30

MB_ADD14/MB_BG1

V32

MB_ADD15/MB_ACT_L

AH32

MB_BANK0

AG33

MB_BANK1

W31

MB_BANK2/MB_BG0

D25

MB_DM0

D29

MB_DM1

E33

MB_DM2

J33

MB_DM3

AR30

MB_DM4

AW30

MB_DM5

BC30

MB_DM6

BC26

MB_DM7

N33

MB_DM8

B26

MB_DQS_H0

A26

MB_DQS_L0

B30

MB_DQS_H1

A30

MB_DQS_L1

F32

MB_DQS_H2

E32

MB_DQS_L2

K32

MB_DQS_H3

J32

MB_DQS_L3

AR32

MB_DQS_H4

AR33

MB_DQS_L4

AW32

MB_DQS_H5

AW33

MB_DQS_L5

BA29

MB_DQS_H6

AY29

MB_DQS_L6

BA25

MB_DQS_H7

AY25

MB_DQS_L7

P32

MB_DQS_H8

N32

MB_DQS_L8

AE33

MB_CLK_H0

AE32

MB_CLK_L0

AE30

MB_CLK_H1

AE31

MB_CLK_L1

AD32

MB_CLK_H2

AD33

MB_CLK_L2

AC33

MB_CLK_H3

AC32

MB_CLK_L3

T33

MB_RESET_L

AG30

MB_EVENT_L

U32

MB_CKE0

U33

MB_CKE1

AL30

MB0_ODT0

AM32

MB0_ODT1

AJ32

MB1_ODT0

AM33

MB1_ODT1

AJ33

MB0_CS_L0

AL32

MB0_CS_L1

AJ30

MB1_CS_L0

AL33

MB1_CS_L1

AH33

MB_RAS_L/MB_RAS_L_ADD16

AK32

MB_CAS_L/MB_CAS_L_ADD15

AJ31

MB_WE_L/MB_WE_L_ADD14

A19

MB_VREFDQ

@

2013/08/15

2013/08/15

2013/08/15

UC2I

MEMORY B

MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7

MB_DATA8

MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15

MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23

MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31

MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39

MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47

MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55

MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63

MB_CHECK0
MB_CHECK1
MB_CHECK2
MB_CHECK3
MB_CHECK4
MB_CHECK5
MB_CHECK6
MB_CHECK7

MB_ZVDDIO_MEM_S

FP4 REV 0.93

AMD-CARRIZO_FP4-BGA968

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

A25
C25
C27
D27
B24
B25
B27
A27

A29
C29
B32
D32
B28
B29
A31
C31

E30
E31
G33
G32
C33
D33
G30
G31

J30
J31
L33
L32
H32
H33
L30
L31

AN31
AP32
AT32
AU32
AN33
AN32
AR31
AT33

AU30
AV32
BA33
AY32
AU33
AU31
AW31
AY33

BC31
BB30
BB28
AY27
BB32
BA31
BC29
BB29

BB27
BB26
BB24
AY23
BA27
BC27
BC25
BB25

N30
N31
R33
R32
M32
M33
R30
R31

AF32

MB_ZVDDIO

2

DDRB_DQ0
DDRB_DQ1
DDRB_DQ2
DDRB_DQ3
DDRB_DQ4
DDRB_DQ5
DDRB_DQ6
DDRB_DQ7

DDRB_DQ8
DDRB_DQ9
DDRB_DQ10
DDRB_DQ11
DDRB_DQ12
DDRB_DQ13
DDRB_DQ14
DDRB_DQ15

DDRB_DQ16
DDRB_DQ17
DDRB_DQ22
DDRB_DQ23
DDRB_DQ20
DDRB_DQ21
DDRB_DQ19
DDRB_DQ18

DDRB_DQ24
DDRB_DQ25
DDRB_DQ26
DDRB_DQ27
DDRB_DQ29
DDRB_DQ28
DDRB_DQ30
DDRB_DQ31

DDRB_DQ36
DDRB_DQ32
DDRB_DQ39
DDRB_DQ35
DDRB_DQ33
DDRB_DQ37
DDRB_DQ34
DDRB_DQ38

DDRB_DQ41
DDRB_DQ44
DDRB_DQ43
DDRB_DQ47
DDRB_DQ45
DDRB_DQ40
DDRB_DQ46
DDRB_DQ42

DDRB_DQ54
DDRB_DQ53
DDRB_DQ50
DDRB_DQ52
DDRB_DQ49
DDRB_DQ48
DDRB_DQ51
DDRB_DQ55

DDRB_DQ60
DDRB_DQ57
DDRB_DQ58
DDRB_DQ59
DDRB_DQ61
DDRB_DQ56
DDRB_DQ63
DDRB_DQ62

RC10 39.2_0402_1%

2013/08/15

2013/08/15

2013/08/15

DDRB_DQ[63..0] {12}

DATA16--DATA23 Byte internal swap

DATA24--DATA31 Byte internal swap

DATA32--DATA39 Byte internal swap

DATA40--DATA47 Byte internal swap

DATA48--DATA55 Byte internal swap

DATA56--DATA63 Byte internal swap

+1.35V

1 2

Title

Title

Title

FP4 (MEM)

FP4 (MEM)

FP4 (MEM)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

CG521

CG521

CG521

Wednesday, February 24, 2016

Wednesday, February 24, 2016

Wednesday, February 24, 2016

1

1.0

1.0

1.0

of

of

of

550

550

550

5

+1.8VS

12

RC18

D D

C C

B B

300_0402_5%

APU_RST#

PLACE CC16 CAPS CLOSE TO APU,CRB reserve 27pf

1

CC16
150P_0402_50V8-J

@

2

+1.8VS

12

RC19
300_0402_5%

APU_PWROK

PLACE CC17 CAPS CLOSE TO APU,CRB reserve 27pf

1

CC17
150P_0402_50V8-J

@

2

+1.8VS+1.8VS

RPC10
1K_0404_4P2R_5%

STN@

1 4

APU_SIC
APU_SID

2 3

1 4
2 3

APU_SIC EC_SMB_CK2

G

5

S

G

2

QC6B
DMN5L06DWK-7 2N SOT363-6

S

61

D

STN@

QC6A
DMN5L06DWK-7 2N SOT363-6

RPC7

CZL@

0_0404_4P2R_5%

D

STN@

34

EC_SMB_CK2
EC_SMB_DA2

CarrizoL not support DP2

CarrizoL:HDMI

eDP

APU_SVT{49}
APU_SVC{49}
APU_SVD{49}

APU_SVT_R

12

CC210

1000P_0402_25V7-K

@

H_PROCHOT#{35}

EC_SMB_DA2APU_SID

EC_SMB_CK2 {16,30,35}
EC_SMB_DA2 {16,30,35}

APU_HDMI_TX2+{25}
APU_HDMI_TX2-{25}

APU_HDMI_TX1+{25}
APU_HDMI_TX1-{25}

APU_HDMI_TX0+{25}
APU_HDMI_TX0-{25}

APU_HDMI_CLK+{25}
APU_HDMI_CLK-{25}

APU_EDP_TX0+{23}
APU_EDP_TX0-{23}

APU_EDP_TX1+{23}
APU_EDP_TX1-{23}

1 2

RC249 0_0402_5%

1 2

RC213 0_0402_5%

1 2

RC215 0_0402_5%

APU_PWROK{49}

1 2

RC31 0_0402_5%@

With HDT+ Header

+1.8VS

RC7
1K_0402_5%

1 2

APU_TRST#

A A

RC76 33_0402_5%HDT@

2

CC84

0.01U_0201_6.3V7-K

1

1 2

1 8

2 7

RPC17
10K_0804_8P4R_5%

HDT@

3 6

4 5

APU_TRST#_R

JHDT1

@

1

1

2

3

3

4

5

5

6

7

7

8

9

9

10

11

11

12

13

13

14

15

15

16

17

17

18

19

19

20

SAMTE_ASP-136446-07-B

2
4
6
8
10
12
14
16
18
20

4

APU_TCK
APU_TMS
APU_TDI
APU_TDO
APU_PWROK_BUF
APU_RST#_BUF
APU_DBRDY
APU_DBREQ#
APU_TEST19_PLLTEST0
APU_TEST18_PLLTEST1

APU_HDMI_TX2+
APU_HDMI_TX2-

APU_HDMI_TX1+
APU_HDMI_TX1-

APU_HDMI_TX0+
APU_HDMI_TX0-

APU_HDMI_CLK+
APU_HDMI_CLK-

APU_EDP_TX0+
APU_EDP_TX0-

APU_EDP_TX1+
APU_EDP_TX1-

APU_SVT_R
APU_SVC_R
APU_SVD_R

APU_SIC
APU_SID

APU_RST#
APU_PWROK

APU_PROCHOT#_R
ALERT#

APU_TDI
APU_TDO
APU_TCK
APU_TMS
APU_TRST#
APU_DBRDY
APU_DBREQ#

1K_0804_8P4R_5%

RPC5

B6
A6

D7
C7

A7
B7

D9
C9

A2
A3

B4
A4

D5
C5

A5
B5

E2
E1

E3
E4

D1
D2

C1
B1

C15
D17
D19

B15
B16
A18

B18
C17

D15
C19

A15
B17

H15
H14
D13
G15
J14
C13
A11

18
27
36
45

APU_PWROK

APU_RST#

DP2_TXP0
DP2_TXN0

DP2_TXP1
DP2_TXN1

DP2_TXP2
DP2_TXN2

DP2_TXP3
DP2_TXN3

DP1_TXP0
DP1_TXN0

DP1_TXP1
DP1_TXN1

DP1_TXP2
DP1_TXN2

DP1_TXP3
DP1_TXN3

DP0_TXP0
DP0_TXN0

DP0_TXP1
DP0_TXN1

DP0_TXP2
DP0_TXN2

DP0_TXP3
DP0_TXN3

SVT0
SVC0
SVD0

SVT1
SVC1
SVD1

SIC
SID

RESET_L
PWROK

PROCHOT_L
ALERT_L

TDI
TDO
TCK
TMS
TRST_L
DBRDY
DBREQ_L

@

+1.8VS+1.8VS

UC2C

DISPLAY/SVI2/JTAG/TEST

DP_AUX_ZVSS

TEMPINRETURN

DP_STEREOSYNC/TEST36

VDDCR_GFX_SENSE

VDDCR_NB_SENSE

VDDCR_CPU_SENSE

FP4 REV 0.93

AMD-CARRIZO_FP4-BGA968

UC6

3

2A

2

GND

1

1A

DP_ZVSS

DP_BLON

DP_DIGON

DP_VARY_BL

DP2_AUXP
DP2_AUXN

DP2_HPD

DP1_AUXP
DP1_AUXN

DP1_HPD

DP0_AUXP
DP0_AUXN

DP0_HPD

RSVD_1
TEMPIN0
TEMPIN1
TEMPIN2

TEST410
TEST411

TEST4
TEST5
TEST6

TEST9
TEST10
TEST14
TEST15
TEST16
TEST17
TEST11
TEST18
TEST19

TEST28_H

TEST28_L

TEST31
TEST37

VDDP_SENSE

VSS_SENSE

A9
B9
G5
G6
F11

H9
G9
E9

F7
E7
F5

F8
E8
G8

K24
E15
E14
E12
F14
AK24
AL24
P24
N24
AN24
AB8
Y9
B10
D11
A10
C11
B11
A14
B14

A13
B13
P26
E11
A17

H11
J12
G12
AY18

H12

1

CC25

0.1U_0201_6.3V6-K

2

HDT@

2Y

VCC

1Y

SN74LVC2G07YZPR_WCSP6HDT@

3

DP_2K_ZVSS
DP_150_ZVSS
DP_ENBKL
DP_ENVDD
DP_EDP_PWM

APU_DDC_CLK
APU_DDC_DATA
APU_HDMI_HPD

APU_EDP_AUX
APU_EDP_AUX#
APU_EDP_HPD

Core_type

TEST410
TEST411
TEST4
TEST5

APU_TEST14_BP0
APU_TEST15_BP1
APU_TEST16_BP2
APU_TEST17_BP3
APU_TEST11_BP4
APU_TEST18_PLLTEST1
APU_TEST19_PLLTEST0

APU_TEST28_H_PLLCHARZ
APU_TEST28_L_PLLCHARZ
APU_TEST31_MEM_TEST
APU_TEST36_STEREOSYNC
APU_TEST37

APU_VDDNB_SEN_H
APU_VDDCORE_SEN_H
VDD_095_FB_H

APU_VSS_SEN_L

+1.8VS+1.8VS

12

RC32
300_0402_5%

4
5
6

2

For Carrizo
DisplayPort Auxiliary Channel pins are dual-mode pins and are 3.3V tolerant.
In I2C mode AUXP pins change to SCL, and AUXN pins change to SDA.
During this operation the pin type is B-IO33-OD. FDS

1 2

RC55 2K_0402_1%

1 2

RC12 150_0402_1%

For STN,
Hot Plug Detect pins is I-IO18-S,but 3.3V tolerant.

APU_DDC_CLK {25}
APU_DDC_DATA {25}
APU_HDMI_HPD {25}

APU_EDP_AUX {23}
APU_EDP_AUX# {23}
APU_EDP_HPD {23}

1

TC16@

1

TC17@

1

TC13@

1

TC14@

1 2

RC21 1K_0402_5%@

1

TC18@

1 2

RC23 1K_0402_5%@

1 2

RC24 1K_0402_5%@

1 2

RC189 1K_0402_5%@

1

TC21@

1

TC23@

1

TC25@

APU_VDDNB_SEN_H {49}
APU_VDDCORE_SEN_H {49}

1

@

TC26

1 2

RC236 0_0402_5%@

HDMI Convert Carrizo

eDP

1 2

RC239 100K_0402_5%@

RPC14

1 2

RC34 1K_0402_5%CZL@

1 2

RC28 1K_0402_5%STN@

1 2

RC27 1K_0402_5%@

1 2

RC29 1K_0402_5%@

1 2

RC30 1K_0402_5%@

APU_VDD_SEN_L {49}

APU_VDDNB_SEN_H
APU_VDDCORE_SEN_H
APU_VDD_SEN_L

+3VALW_APU

14
23

1K_0404_4P2R_5%

+3VS_APU

1
1
1

TC27@
TC28@
TC29@

To EDP panel

+1.8VS

LCD Power IC can change for PCH_ENVDD for CZ cost down

12

RC36
300_0402_5%

APU_PWROK_BUF

APU_RST#_BUF

DP_EDP_PWM

12

RC11
100K_0402_5%

STN@

DP_ENVDD

DP_ENBKL

STN@

2

G

STN@

12

RC246
100K_0402_5%

APU_DDC_CLK
APU_DDC_DATA

APU_EDP_HPD

APU_PROCHOT#_R
ALERT#

APU_PROCHOT#_R
ALERT#

+3VALW_APU

RC71
10K_0402_5%

1 2

STN@

5

G

61

D

STN@

QC8A
DMN5L06DWK-7 2N SOT363-6

S

1 2

RC205 0_0402_5%CZL@

RC206 0_0402_5%@

+3VALW_APU

1 2

STN@

61

D

2

G

S

STN@

+3VS_APU

12

RC70

4.7K_0402_5%

STN@

34

D

QC8B
DMN5L06DWK-7 2N SOT363-6

S

1 2

+3VS_APU

12

RC245

4.7K_0402_5%

RC244

STN@

10K_0402_5%

34

D

5

G

S

STN@

QC9A
DMN5L06DWK-7 2N SOT363-6

1 2

RC207 0_0402_5%CZL@

1

RPC18

1 4
2 3

2.2K_0404_4P2R_5%

1 2

RC35 100K_0402_5%

RPC11

STN@

23
14

1K_0404_4P2R_5%

RPC12

CZL@

23
14

1K_0404_4P2R_5%

PCH_EDP_PWM {23}

QC9B
DMN5L06DWK-7 2N SOT363-6

+3VS_APU

+1.8VS

+3VS_APU

PCH_ENVDD {23}

PCH_ENBKL {23}

PCH_ENBKL can to con EC ADC pin for CZ cost down because 1.8V level

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2013/08/15

2013/08/15

2013/08/15

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2013/08/15

2013/08/15

2013/08/15

Title

FP4 (DISPLAY/CLK/MISC)

FP4 (DISPLAY/CLK/MISC)

FP4 (DISPLAY/CLK/MISC)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

CG521

CG521

CG521

Wednesday, February 24, 2016

Wednesday, February 24, 2016

Wednesday, February 24, 2016

1

650

650

650

of

of

of

1.0

1.0

1.0

5

1 2

APU_LPC_RST#{30,35}

PLT_RST#{15,28,31}

D D

EC_RSMRST#{35}

12

RC43
100K_0402_5%@

12

RC66
100K_0402_5%@

RC46 33_0402_5%

1

CC20
150P_0402_50V8-J

2

1 2

RC38 33_0402_5%

1

CC19
150P_0402_50V8-J

2

RC247

0_0402_5%

DC1

1 2

LRB751V-40T1G_SOD323-2

12

@

with QC16,QC17, EC must set EC_RSMRST# and EC_SYS_PWRGD reversed compare to DC1 and DC2

C C

12

RC95 0_0402_5%

@

DC2

1 2

RC20

2.2K_0402_5%

@

TEST0
TEST1
TEST2

RC197
15K_0402_5%

@

PCIE_WAKE# {28,31,35}

SYS_RESET#

EC_SYS_PWRGD{35}

PCIE_WAKE#_RA

AGPIO5

B B

+3VALW_APU

RC84

2.2K_0402_5%

@

1 2

RC195
15K_0402_5%

1 2

+3VS_APU

RC98 10K_0402_5%PX@
RC99 10K_0402_5%@
RC100 10K_0402_5%@

A A

RC101 100K_0402_5%@
RC103 2K_0402_5%PX@
RC104 2K_0402_5%UMA@

12

LRB751V-40T1G_SOD323-2

RC82
100K_0402_5%@

12

RC88 0_0402_5%

@

12

RC92

@

0_0402_5%

2 1

RC85
1K_0402_5%

@

1 2

RC196
15K_0402_5%

1 2

DC3

@

SDM10U45LP-7_DFN1006-2-2

1 2
1 2
1 2

1 2
1 2
1 2

1 2

1 2

PXS_PWREN_R
PXS_RST#
VR_VGA_PWRGD

PXS_PWREN_R
PXS_RST#
VR_VGA_PWRGD

LPC_RST#_R

PCIE_RST#_R

+1.8VALW

12

RC53
10K_0402_5%

RSMRST#_R

1

CC21

0.1U_0201_6.3V6-K

2

+1.8VS

12

RC72
10K_0402_5%

CZL@

Type2 1.8V, Type1 3 3.3V

SYS_PWRGD_R

1

CC22

0.1U_0201_6.3V6-K

2

LRB751V-40T1G_SOD323-2

1

CC38

0.1U_0201_6.3V6-K

2

VGA_GATE#{35}

Connected to 10-ms RC-delay circuit on VDD_18_S5 power rail.
(CRB PWR Dealy: 22K/0.1uF)

PBTN_OUT#{35}

PM_SLP_S3#{35}
PM_SLP_S5#{35}

Delete Zero ODD circuit ODD_DA# 10/20

RPC3

STN@
1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

DC4

@

1 2

@

0_0402_5%

SYS_PWRGD_R

1 2

RC170

PXS_PWREN_R/PXS_RST#_R/VR_VGA_PWRGD internal pull up 40k

5

4

Type1 2 3 all 1.8V

1 2

RC191 0_0402_5%

@

SYS_RESET#{11}

PM_SLP_S3#
PM_SLP_S5#

APU_S5_MUX_CTRL{9}

1 2

RC193 0_0402_5%

1 2

RC194 0_0402_5%

@
@

KBRST#{35}
GATEA20{35}
EC_SCI#{35}

AC_PRESENT{35}

Delete Zero ODD circuit ODD_EN 10/20

PCH_WLAN_OFF#{31}

WLAN_CLKREQ#{31}

LAN_CLKREQ#{28}

PCH_BT_OFF#{31}

GPU_CLKREQ#{16}

USB_OC1#{32}

RC201 0_0402_5%

SUSCLK{11,31}

I2C1SDA
I2C1SCL
I2C0SCl
I2C0SDA

HDA_SDIN0{34}

Max ESR < 65K ohm !!

PXS_PWREN

13

D

QC15

2

G

1

CC96

0.1U_0201_6.3V6-K

2

@

S

L2N7002KWT1G_SOT323-3

@

4

BOARD_ID0
BOARD_ID1
BOARD_ID2

@

1

CC23

2

APU_S5_MUX_CTRL

12

RC102

1 2

20M_0402_5%

YC1

1 2

202983-PG14

20P_0402_50V8

3

+3VALW_APU

RC39
10K_0402_5%

15@

1 2

RC47
2K_0402_5%

17@

1 2

LPC_RST#_R
PCIE_RST#_R

RSMRST#_R
PWRBTN#_RPBTN_OUT#

SYS_PWRGD_R
SYS_RESET#
PCIE_WAKE#_RA

PM_SLP_S3#_R
PM_SLP_S5#_R

AGPIO10

TEST0
TEST1
TEST2

KBRST#

ODD_DA#
AC_PRESENT

BOARD_ID0
BOARD_ID1

ODD_EN
PCH_WLAN_OFF#
WLAN_CLKREQ#
LAN_CLKREQ#
PCH_BT_OFF#
GPU_CLKREQ#
BOARD_ID2
USB_OC1#
USB_OC2#

HDA_BITCLK
HDA_SDIN0_R
HDA_SDIN1
HDA_SDIN2
HDA_RST#
HDA_SYNC
HDA_SDOUT

I2C0SCl
I2C0SDA
I2C1SCL
I2C1SDA

RC40
10K_0402_5%

UMA@

1 2

1 2

BB12

AN7
AE4
AE1

BC9
AF2
AG2

AK7
AH5

AE8
AH8

AH6
AK8
AE3

AY15
BC19

AD7

BB13

AG3
AD5

AN8

AE2
BC15
BB17
BC17
BB18
BB16

AH9

AG1

AH2

AU6

AR8

AP6

AR5

AU9

AT9

AR7
BB10

BB9

BB7

BC7

AG7

32K_X1

32K_X2

1

change YC1 from SIWARD SJ10000M500 to Micro crystalSJ10000M900, SIWARD as 2nd source

CC24

2

20P_0402_50V8

HDA_RST_AUDIO#{34}

HDA_SYNC_AUDIO{34}
HDA_BITCLK_AUDIO{34}
HDA_SDOUT_AUDIO{34}

RC41
10K_0402_5%

@

1 2

RC48

RC49

2K_0402_5%

2K_0402_5%

PX@

AL8

AL9

AT1

AT2

@

1 2

LPC_RST_L
PCIE_RST_L/EGPIO26

RSMRST_L
PWR_BTN_L/AGPIO0

PWR_GOOD
SYS_RESET_L/AGPIO1
WAKE_L/AGPIO2

SLP_S3_L
SLP_S5_L

S0A3_GPIO/AGPIO10
S5_MUX_CTRL/EGPIO42

TEST0
TEST1/TMS
TEST2

ESPI_RESET_L/KBRST_L/AGPIO129
GA20IN/AGPIO126
LPC_PME_L/AGPIO22
LPC_SMI_L/AGPIO86

AC_PRES/USB_OC4_L/IR_RX0/AGPIO23
IR_TX0/USB_OC5_L/AGPIO13
IR_TX1/USB_OC6_L/AGPIO14
IR_RX1/AGPIO15
IR_LED_L/LLB_L/AGPIO12
CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/AGPIO92
CLK_REQ1_L/AGPIO115
CLK_REQ2_L/AGPIO116
CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/EGPIO131
CLK_REQG_L/OSCIN/EGPIO132
USB_OC0_L/TRST_L/AGPIO16
USB_OC1_L/TDI/AGPIO17
USB_OC2_L/TCK/AGPIO18
USB_OC3_L/TDO/AGPIO24

AZ_BITCLK/I2S_BCLK_MIC
AZ_SDIN0/I2S_DATA_MIC0
AZ_SDIN1/I2S_LR_PLAYBACK
AZ_SDIN2/I2S_DATA_MIC1
AZ_RST_L/I2S_LR_MIC
AZ_SYNC/I2S_BCLK_PLAYBACK
AZ_SDOUT/I2S_DATA_PLAYBACK

I2C0_SCL/EGPIO145
I2C0_SDA/EGPIO146
I2C1_SCL/EGPIO147
I2C1_SDA/EGPIO148

RTCCLK

X32K_X1

X32K_X2

@

ACPI/SD/AZ/GPIO/RTC/I2C/UART/MISC

RPC4

1 8
2 7
3 6
4 5

33_0804_8P4R_5%

3

UC2D

SD0_WP/EGPIO101

SD0_PWR_CTRL/AGPIO102

SD0_CD/AGPIO25

SD0_CLK/EGPIO95

SD0_CMD/EGPIO96

SD0_DATA0/EGPIO97
SD0_DATA1/EGPIO98
SD0_DATA2/EGPIO99

SD0_DATA3/EGPIO100

SD0_LED/EGPIO93

SCL0/I2C2_SCL/EGPIO113

SDA0/I2C2_SDA/EGPIO114

SCL1/I2C3_SCL/AGPIO19
SDA1/I2C3_SDA/AGPIO20

AGPIO6/LDT_RST_L

AGPIO7/LDT_PWROK

VDDGFX_PD/AGPIO39

AGPIO66/SHUTDOWN_L

AGPIO68/SGPIO_CLK

AGPIO69/SGPIO_LOAD

AGPIO71/SGPIO_DATAOUT

AGPIO72/SGPIO_DATAIN

BLINK/USB_OC7_L/AGPIO11

GENINT1_L/AGPIO89
GENINT2_L/AGPIO90

FANIN0/AGPIO84

FANOUT0/AGPIO85

UART0_CTS_L/EGPIO135

UART0_RXD/EGPIO136

UART0_RTS_L/EGPIO137

UART0_TXD/EGPIO138

UART0_INTR/AGPIO139

UART1_CTS_L/BT_I2S_BCLK/EGPIO140

UART1_RXD/BT_I2S_SDI/EGPIO141

UART1_RTS_L/EGPIO142

UART1_TXD/BT_I2S_SDO/EGPIO143

UART1_INTR/BT_I2S_LRCLK/AGPIO144

FP4 REV 0.93

AMD-CARRIZO_FP4-BGA968

HDA_RST#
HDA_SYNC
HDA_BITCLK
HDA_SDOUT

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

AGPIO3
AGPIO4
AGPIO5

AGPIO8
AGPIO9

AGPIO40
AGPIO64
AGPIO65

SPKR/AGPIO91

BB2

SD_PWR_CNTL

BB5

ODD_DETECT#

BC2
BB4
AY5

SD_DATA0_R

BC3

SD_DATA1_R

BA3

SD_DATA2_R

BC5

SD_DATA3_R

BA5

SD_LED

BB6

APU_SMB_CLK

BA15

APU_SMB_DATA

AY17
AG5

SCL1

AG4

SDA1

AL5
AL6

AGPIO4

AJ1

AGPIO5
LDT_RST_L

AJ3

LDT_PWROK

AH1
AJ4

AGPIO8

AK5
AD8
AG8

AGPIO40

AW15

AGPIO64

AU15

APU_SHUTDOWN#

AT15
AU12
AT14

AGPIO69

AR14
BC13

BA17
AN5

HVB_EN

BB14

VR_VGA_PWRGD

BA19

PXS_PWREN_R

BC18
BB19

AY9
AW8
AV5
AV8
AW9

AV11
AU7
AT11
AR11
AP9

CRB: CARRIZO NEED 10K PD ON UNUSED SDIN
DG: 10K PD

2013/08/15

2013/08/15

2013/08/15

2

@

1

TC61

@

1

TC44

@

1

TC75

@

1

TC45

1

@

TC59

1

TC62@

1

TC63@

1

TC64@

1

TC65@

RPC2

1 4
2 3

CZL@

10K_0404_4P2R_5%

1
1

1 2

RC116 0_0402_5%CZLPX@

1 2

RC109 1K_0402_5%PX@

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

2

APU_SMB_CLK {12,31}
APU_SMB_DATA {12,31}

AGPIO3 {11}

TC67@
TC68@

APU_SHUTDOWN# {16}

PCH_BEEP {34}

BLINK {11}
HVB_EN {11,35}

VR_VGA_PWRGD {15,48}

Deciphered Date

Deciphered Date

Deciphered Date

DIMM1, DIMM2, Mini CARD,HDMI Convert

APU_SMB_CLK
APU_SMB_DATA

KBRST#
PCH_BT_OFF#

PXS_RST# {8,15}

PXS_PWREN {19,48}

2013/08/15

2013/08/15

2013/08/15

PCH_WLAN_OFF#

ODD_DA#
ODD_DETECT#

LAN_CLKREQ#
WLAN_CLKREQ#
GPU_CLKREQ#
APU_SHUTDOWN#

APU_SHUTDOWN#
inter pull down for Cz,pull high for Czl

PCIE_WAKE#_RA
AC_PRESENT
AGPIO5
PBTN_OUT#

USB_OC1#
USB_OC2#

ODD_EN
PM_SLP_S3#
PM_SLP_S5#
AGPIO40
AGPIO4
APU_S5_MUX_CTRL

AGPIO4
AGPIO64

AGPIO8

SD_LED
AGPIO10
APU_SHUTDOWN#

GPU_CLKREQ#
HDA_BITCLK

HDA_SDIN0_R

RSMRST#_R
SYS_PWRGD_R

HDA_SDIN2
HDA_SDIN1

Title

Title

Title

FP4 (GEVENT/GPIO/SD/AZ)

FP4 (GEVENT/GPIO/SD/AZ)

FP4 (GEVENT/GPIO/SD/AZ)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Wednesday, February 24, 2016

Wednesday, February 24, 2016

Wednesday, February 24, 2016

Date: Sheet

Date: Sheet

Date: Sheet

1

RPC9

23
14

2.2K_0404_4P2R_5%
RPC6

18
27
36
45

10K_0804_8P4R_5%

RPC21

1 4

@

2 3

10K_0404_4P2R_5%

1 2

RC67 10K_0402_5%

1 2

RC78 10K_0402_5%

1 2

RC64 10K_0402_5%UMA@

1 2

RC96 10K_0402_5%

CZL@

RPC15

1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

RPC16

1 4
2 3

10K_0404_4P2R_5%

1 2

RC141 10K_0402_5%

1 2

RC203 2.2K_0402_5%@

1 2

RC208 2.2K_0402_5%@

1 2

RC145 10K_0402_5%STN@

1 2

RC94 10K_0402_5%@

1 2

RC248 100K_0402_5%

STN@

1 2

RC86 10K_0402_5%CZL@

1 2

RC93 10K_0402_5%CZL@

1 2

RC83 10K_0402_5%STN@

1 2

RC97 10K_0402_5%CZL@

1 2

RC80 10K_0402_5%

1 2

RC68 10K_0402_5%@

1 2

RC65 2K_0402_5%PX@

1 2

RC90 10K_0402_5%@

1 2

RC91 10K_0402_5%@

1 2

RC87 100K_0402_5%

1 2

RC89 100K_0402_5%

1 2

RC241 10K_0402_5%@

1 2

RC242 10K_0402_5%@

CG521

CG521

CG521

1

750

750

750

+3VS_APU

+3VALW_APU

of

of

of

1.0

1.0

1.0

5

SATA_PTX_DRX_P0{33}
SATA_PTX_DRX_N0{33}

HDD

SATA_PRX_DTX_N0{33}
SATA_PRX_DTX_P0{33}

SATA_PTX_DRX_P1{33}

+3VS_APU

D D

RPC13

23
14

10K_0404_4P2R_5%

STN@

1 2

RC147 10K_0402_5%

C C

B B

48MHz/10pF Crystal

1 2

RC140 1M_0402_5%

YC2

1

OSC1

1

2

NC12OSC2

48MHZ 10PF X1E000021083400
CC28
12P_0402_50V8-J

EGPIO70
SATA0_DEVSLP_R

APU_TS_ON#

4

NC2

3

CLK_PCIE_GPU{15}
CLK_PCIE_GPU#{15}

CLK_PCIE_WLAN{31}
CLK_PCIE_WLAN#{31}

CLK_PCIE_LAN{28}
CLK_PCIE_LAN#{28}

TPM_CLK{30}
CLK_PCI_EC{11,35}
LPC_CLK1{11}

SPI_CLK{35}
SPI_CS0#{35}

SPI_SO{35}
SPI_SI{35}

PXS_RST#{7,15}

48M_X1
48M_X2

1

CC29
12P_0402_50V8-J

2

SATA_PTX_DRX_N1{33}

ODD

SATA_PRX_DTX_N1{33}
SATA_PRX_DTX_P1{33}

+0.95VS

Nano not support Touch 10/20
AGPIO130 CZ STN OD output, CZL output

CLK_PCIE_GPU CLK_PCIE_GPU_R
CLK_PCIE_GPU# CLK_PCIE_GPU#_R

CLK_PCIE_WLAN CLK_PCIE_WLAN_R

CLK_PCIE_LAN CLK_PCIE_LAN_R
CLK_PCIE_LAN#

SPI_CS0#

SPI_WP#

SPI_HOLD#

1 2

RC113 1K_0402_1%

1 2

RC114 1K_0402_1%

RC117 0_0402_5%
RC118 0_0402_5%

RC119 0_0402_5%
RC120 0_0402_5%

RC121 0_0402_5%
RC122 0_0402_5%

1 2

RC125 22_0402_5%TPM@

1 2

RC126 3.3_0402_1%

1 2

RC127 0_0402_5%

@

LPC_AD0{30,35}
LPC_AD1{30,35}
LPC_AD2{30,35}
LPC_AD3{30,35}

LPC_FRAME#{11,30,35}

SERIRQ{30,35}

RC149 10K_0402_5%

SPI_CLK

SPI_SO

SPI_SI

RC209 0_0402_5%@
RC202 0_0402_5%@
RC144 10K_0402_5%STN@
RC199 0_0402_5%@
RC198 0_0402_5%@
RC132 0_0402_5%@
RC133 0_0402_5%@
RC143 10K_0402_5%@

Reference CG412, only reserved for Stoney

SPI_CS0#
SPI_SO
SPI_WP# SPI_CLK

with BOM strcture control, UC3 change to 1.8V SPI ROM for CZ

1 2
1 2

@
@

1 2
1 2

@

@
1 2
1 2

@

@

TC53 @

1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

RC243 0_0402_5%STNPX@

8M ROM

4

SATA_PTX_DRX_P0
SATA_PTX_DRX_N0

SATA_PRX_DTX_N0
SATA_PRX_DTX_P0

SATA_PTX_DRX_P1
SATA_PTX_DRX_N1

SATA_PRX_DTX_N1
SATA_PRX_DTX_P1

SATA_CALRN
SATA_CALRP

SATA0_DEVSLP_R

EGPIO70

APU_TS_ON#

CLK_PCIE_WLAN#_RCLK_PCIE_WLAN#

CLK_PCIE_LAN#_R

X14M_25M_48M_OSC

1

48M_X1

48M_X2

LPCCLK0
LPCCLK1

TC54 @

1 2

UC3

1

CS#

2

DO

3

WP#

4

GND

W25Q64FVSSIQ_SO8

CZL@

1

AGPIO21

SPI_CLK_R

SPI_CS0#_R
EGPIO119
SPI_SO_R
SPI_SI_R
SPI_WP#_R

SPI_HOLD#_R

AGPIO76

VCC

HOLD#

CLK

DI

AU3

SATA_TX0P

AU4

SATA_TX0N

AV1

SATA_RX0N

AV2

SATA_RX0P

AY2

SATA_TX1P

AY1

SATA_TX1N

AW4

SATA_RX1N

AW3

SATA_RX1P

AW1

SATA_ZVSS

AW2

SATA_ZVDDP

AT17

DEVSLP0/EGPIO67

AT12

DEVSLP1/EGPIO70

BB15

SATA_ACT_L/AGPIO130

AU2

SATA_X1

AU1

SATA_X2

U4

GFX_CLKP

U3

GFX_CLKN

U1

GPP_CLK0P

U2

GPP_CLK0N

W4

GPP_CLK1P

W3

GPP_CLK1N

W1

GPP_CLK2P

W2

GPP_CLK2N

Y2

GPP_CLK3P

Y1

GPP_CLK3N

BC10

X25M_48M_OSC

T2

X48M_X1

T1

X48M_X2

AW14

LPCCLK0/EGPIO74

AY13

LPCCLK1/EGPIO75

BB11

LAD0

BA11

LAD1

AY11

LAD2

BA13

LAD3

AV14

LFRAME_L

BA1

ESPI_ALERT_L/LDRQ0_L

BC14

SERIRQ/AGPIO87

BC11

LPC_CLKRUN_L/AGPIO88

AE9

LPC_PD_L/AGPIO21

BC6

SPI_CLK/ESPI_CLK/EGPIO117

BB8

SPI_CS1_L/EGPIO118

AW7

SPI_CS2_L/ESPI_CS_L/EGPIO119

BA9

SPI_DI/ESPI_DATA/EGPIO120

AY7

SPI_DO/EGPIO121

AW11

SPI_WP_L/EGPIO122

BA7

SPI_HOLD_L/EGPIO133

AW12

SPI_TPM_CS_L/AGPIO76

@

+VCC_SPI

1

2

8

SPI_HOLD#

7
6

SPI_SI

5

CC27

0.1U_0201_6.3V6-K

UC2E

CLK/SATA/USB/SPI/LPC

FP4 REV 0.93

AMD-CARRIZO_FP4-BGA968

+VCC_SPI

SPI_WP#
SPI_HOLD#

SPI_CS0#

3

USB_ZVSS

USB_HSD0P

USB_HSD1P

USB_HSD2P

USB_HSD3P

USB_HSD4P

USB_HSD5P

USB_HSD6P

USB_HSD7P

1 4
2 3

1 2

AP8
AP5
AR2

AR1
AR3

AR4
AN2

AN1
AN3

AN4
AM1

AM2
AL2

AL1
AL3

AL4
AK2

AJ2

AD2
AD1

AA3
AA4

W9
W8

AA2
AA1

W5
W6

AC1
AC2

Y6
Y7

AC4
AC3

AB5
AB6

RPC8

10K_0404_4P2R_5%

USBCLK/25M_48M_OSC

USB_HSD0N

USB_HSD1N

USB_HSD2N

USB_HSD3N

USB_HSD4N

USB_HSD5N

USB_HSD6N

USB_HSD7N

USB_SS_ZVSS

USB_SS_ZVDDP

USB_SS_0TXP

USB_SS_0TXN
USB_SS_0RXP

USB_SS_0RXN

USB_SS_1TXP

USB_SS_1TXN
USB_SS_1RXP

USB_SS_1RXN

USB_SS_2TXP

USB_SS_2TXN
USB_SS_2RXP

USB_SS_2RXN

USB_SS_3TXP

USB_SS_3TXN
USB_SS_3RXP

USB_SS_3RXN

+VCC_SPI

RC138 10K_0402_5%

2

USB_RCOMP
USB20_P0

USB20_N0

1 2

RC112 11.8K_0402_1%

USB20_P0 {32}
USB20_N0 {32}

Left USB2.0

RIGHT USB (2.0)

USB20_P3
USB20_N3

USB20_P4
USB20_N4

USB20_P5
USB20_N5

USB20_P6
USB20_N6

CarrizoL don't support USB_SS_[1:0]
Note: Route USB 3.0 ports starting from the lowest numbered port,
for example, Port0, Port1, Port2.
All unused ports should be the highest numbered ports.
For CZ and CZL Co-lay, can start from Port2

USBSS_CALRN
USBSS_CALRP

USB3.0 port0 must map to USB2.0 port4,
USB3.0 port1 must map to USB2.0 port5,
USB3.0 port2 must map to USB2.0 port6,
USB3.0 port0 must map to USB2.0 port7

USB30_TX_P2
USB30_TX_N2

USB30_RX_P2
USB30_RX_N2

1 2

RC135 0_0402_5%CZL@

1 2

RC192 0_0402_5%STN@

+VCC_SPI

USB20_P3 {24}
USB20_N3 {24}

USB20_P4 {31}
USB20_N4 {31}

USB20_P5 {23}
USB20_N5 {23}

USB20_P6 {32}
USB20_N6 {32}

1 2

RC123 1K_0402_1%

1 2

RC124 1K_0402_1%

Less than two USB 3.0 ports can be utilized provided
the unused ports are higher-numbered consecutive

USB30_TX_P2 {32}
USB30_TX_N2 {32}

USB30_RX_P2 {32}
USB30_RX_N2 {32}

ports. 10.15

+3VALW_APU

Card Reader

Blue Tooth

Camera

LEFT USB (3.0) upper

+0.95VALW

LEFT USB (3.0) upper

+1.8VS

SPI_CLK

RC139
10_0402_5%

EMC_NS@

1 2

2

CC26
10P_0402_50V8J

EMC_NS@

1

EMC

1

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2013/08/15

2013/08/15

2013/08/15

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2013/08/15

2013/08/15

2013/08/15

Title

FP4 (SATA/USB/LPC/SPI)

FP4 (SATA/USB/LPC/SPI)

FP4 (SATA/USB/LPC/SPI)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Wednesday, February 24, 2016

Wednesday, February 24, 2016

Wednesday, February 24, 2016

CG521

CG521

CG521

of

of

of

850

850

1

850

1.0

1.0

1.0

5

+1.35V

+1.35V

1

1

D D

C C

CC42

2

@

FP4 Type 3 (Stoney) processors do not use the VDDP_GFX
power rail so leave VDDP_GFX unconnected.

+3VS

RC214

1 2

0_0402_5%

+0.95VS

CC175

+APU_CORE_NB

CC54

2

22U_0603_6.3V6-M

+3VS_APU

@

CC187

1

1

CC174

2

2

10U_0603_6.3V6M

SIVCD@

OK

0.22U_0201_6.3V6-K

1

CC138

2

1

1

CC57

CC55

CC56

2

2

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

SIVCD@

If P_GFX[7:0] are not used,
VDDP_GFX power balls can be connected to VSS.

1

2

10U_0603_6.3V6M

0.22U_0201_6.3V6-K

1

2

10U_0603_6.3V6M

1

CC171

2

10U_0402_6.3V6M

0.22U_0201_6.3V6-K

1

CC139

CC140

2

+1.8VS

1

CC167

2

10U_0402_6.3V6M

0.22U_0201_6.3V6-K

1

CC141

2

SIVCD@

OK

+VCCRTC

B B

1 2

RC231 10K_0402_5%

1

CC37

2

AP2138N-1.5TRG1_SOT23-3

1U_0402_6.3V6K

1

1

1

CC59

CC58

2

2

2

22U_0603_6.3V6-M

22U_0603_6.3V6-M

Wake-on-Ring not supported:
+VDDIO_AZ_APU Connect to +1.5V S0 rail

0.22U_0201_6.3V6-K

1

1

CC186

2

2

10U_0603_6.3V6M

SIVCD@

0.22U_0201_6.3V6-K

1

CC178

CC177

2

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

1

1

CC142

CC143

2

2

UC5

1

Vin

Vout

2

GND

1

CC60

2

22U_0603_6.3V6-M

22U_0603_6.3V6-M

SIVCD@

+1.8VALW

CC173

1

2

180P_0402_50V8-J

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

1

1

CC144

2

2

SIVCD@

3

1

CC194

2

1

CC53

CC61

2

@

@

22U_0603_6.3V6-M

CC188

0.22U_0201_6.3V6-K

1

CC197

2

1

CC146

CC145

2

180P_0402_50V8-J

+RTCBATT

1U_0402_6.3V6K

1

1

CC62

2

2

22U_0603_6.3V6-M

22U_0603_6.3V6-M

1 2

RC210 0_0805_5%CZLPX@

0.22U_0201_6.3V6-K

1

1

2

2

10U_0603_6.3V6M

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

1

1

CC198

CC201

2

2

0.22U_0201_6.3V6-K

1

CC195

2

@

follow CRB reserve

12

L2N7002KWT1G_SOT323-3

1

2

CZLUMA@

CC189

0.22U_0201_6.3V6-K

1

CC202

2

0.22U_0201_6.3V6-K

1

CC196

2

@

JCMOS1
SHORT PADS

@

4

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

1

1

CC157

CC158

2

2

OK

1 2

RC212 0_0402_5%

+0.95VS_GFX_APU+0.95VS

12

CC180

CZLPX@

RC229

100_0402_5%

+3VALW_APU

1

CC190

2

10U_0603_6.3V6M

0.22U_0201_6.3V6-K

1

CC203

2

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

1

1

CC199

CC200

2

2

@

@

12

RC8

@

470_0603_5%

13

D

QC7

EC_RTCRST#_ON

2

G

S

@

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

1

CC159

CC160

2

SIVCD@

@

0.22U_0201_6.3V6-K

1

1

2

2

10U_0603_6.3V6M

0.22U_0201_6.3V6-K

1

CC191

2

12

RC15

100K_0402_5%

@

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

1

1

CC161

2

2

SIVCD@

+VDDIO_AZ_APU+VAUDIO

1

CC184

2

1U_0402_6.3V6K

CC181

CZLPX@

+0.95VALW

CC182

+RTCBATT

EC_RTCRST#_ON {35}

CC163

1

CC185

2

1

2

10U_0603_6.3V6M

RC6

+1.35V

1

CC165

2

180P_0402_50V8-J

SIVCD@

1

CC193

2

1U_0402_6.3V6K

1U_0402_6.3V6K

SIVCD@

+VDDCR_FCH_S5

0.22U_0201_6.3V6-K

1

CC183

2

+APU_CORE_NB

+RTCBATT_APU

1 2

1K_0402_5%

+0.95VS

3A

0.2A

1.5A

0.2A

1.5A

0.5A

0.2A

0.8A

0.2A

7A

12A

0.22U_0201_6.3V6-K

1

2

AM30

AW19

AW17

AB24
AB27
AB30
AB33
AD25
AD28
AD30
AE24
AE27
AF30
AF33
AG25
AG28
AH24
AH27
AH30
AK25
AK28
AK30
AK33
AL27

AR19

AP19
AP21

AP16
AP18

AP10

AP15
AR15

AN12
AP12

AP13
AR12

AU17
AU19
AV17
AV19

AL12
AL13
AL15
AL18
AL21
AN13
AN16
AN19
AN22

AR17

P25
P28

T24

T27
U25
U28
V30
V33
W24
W27
Y25
Y28
Y30

AE6
AE5

AR9

CC192

VDDIO_MEM_S3_1
VDDIO_MEM_S3_2
VDDIO_MEM_S3_3
VDDIO_MEM_S3_4
VDDIO_MEM_S3_5
VDDIO_MEM_S3_6
VDDIO_MEM_S3_7
VDDIO_MEM_S3_8
VDDIO_MEM_S3_9
VDDIO_MEM_S3_10
VDDIO_MEM_S3_11
VDDIO_MEM_S3_12
VDDIO_MEM_S3_13
VDDIO_MEM_S3_14
VDDIO_MEM_S3_15
VDDIO_MEM_S3_16
VDDIO_MEM_S3_17
VDDIO_MEM_S3_18
VDDIO_MEM_S3_19
VDDIO_MEM_S3_20
VDDIO_MEM_S3_21
VDDIO_MEM_S3_22
VDDIO_MEM_S3_23
VDDIO_MEM_S3_24
VDDIO_MEM_S3_25
VDDIO_MEM_S3_26
VDDIO_MEM_S3_27
VDDIO_MEM_S3_28
VDDIO_MEM_S3_29
VDDIO_MEM_S3_30
VDDIO_MEM_S3_31
VDDIO_MEM_S3_32
VDDIO_MEM_S3_33
VDDIO_MEM_S3_34
VDDIO_MEM_S3_35

VDDIO_AUDIO
VDDP_GFX_2

VDDP_GFX_1
VDD_33_1

VDD_33_2
VDD_18_1

VDD_18_2
VDD_18_S5_1

VDD_18_S5_2
VDD_33_S5_1

VDD_33_S5_2
VDDP_S5_1

VDDP_S5_2
VDDCR_FCH_S5_1

VDDCR_FCH_S5_2
VDDP_6

VDDP_1
VDDP_2
VDDP_3
VDDP_4
VDDP_5

VDDCR_NB_1
VDDCR_NB_2
VDDCR_NB_3
VDDCR_NB_4
VDDCR_NB_5
VDDCR_NB_6
VDDCR_NB_7
VDDCR_NB_8
VDDCR_NB_9

VDDBT_RTC_G

AMD-CARRIZO_FP4-BGA968@

3

POWER

FP4 REV 0.93

UC2F

VDDCR_CPU_1
VDDCR_CPU_2
VDDCR_CPU_3
VDDCR_CPU_4
VDDCR_CPU_5
VDDCR_CPU_6
VDDCR_CPU_7
VDDCR_CPU_8

VDDCR_CPU_9
VDDCR_CPU_10
VDDCR_CPU_11
VDDCR_CPU_12
VDDCR_CPU_13
VDDCR_CPU_14
VDDCR_CPU_15
VDDCR_CPU_16
VDDCR_CPU_17
VDDCR_CPU_18
VDDCR_CPU_19
VDDCR_CPU_20
VDDCR_CPU_21
VDDCR_CPU_22
VDDCR_CPU_23
VDDCR_CPU_24
VDDCR_CPU_25
VDDCR_CPU_26
VDDCR_CPU_42
VDDCR_CPU_31
VDDCR_CPU_43
VDDCR_CPU_32
VDDCR_CPU_44
VDDCR_CPU_33
VDDCR_CPU_45
VDDCR_CPU_34
VDDCR_CPU_46
VDDCR_CPU_35
VDDCR_CPU_47
VDDCR_CPU_36
VDDCR_CPU_28
VDDCR_CPU_29
VDDCR_CPU_40
VDDCR_CPU_30
VDDCR_CPU_37
VDDCR_CPU_49
VDDCR_CPU_38
VDDCR_CPU_39
VDDCR_CPU_48
VDDCR_CPU_41
VDDCR_CPU_27

VDDCR_GFX_14
VDDCR_GFX_15
VDDCR_GFX_16
VDDCR_GFX_17
VDDCR_GFX_18
VDDCR_GFX_19
VDDCR_GFX_20
VDDCR_GFX_21
VDDCR_GFX_22
VDDCR_GFX_23
VDDCR_GFX_24
VDDCR_GFX_25
VDDCR_GFX_26
VDDCR_GFX_27
VDDCR_GFX_28
VDDCR_GFX_29

VDDCR_GFX_1

VDDCR_GFX_2

VDDCR_GFX_3

VDDCR_GFX_4

VDDCR_GFX_5

VDDCR_GFX_6

VDDCR_GFX_7

VDDCR_GFX_8

VDDCR_GFX_9
VDDCR_GFX_10
VDDCR_GFX_11
VDDCR_GFX_12
VDDCR_GFX_30
VDDCR_GFX_31
VDDCR_GFX_32
VDDCR_GFX_33
VDDCR_GFX_34
VDDCR_GFX_35
VDDCR_GFX_36
VDDCR_GFX_37
VDDCR_GFX_13

U8
W7
W12
W15
W18
W21
Y8
Y10
Y13
Y16
Y19
Y22
AB7
AB9
AB12
AB15
AB18
AB21
AD6
AD10
AD13
AD16
AD19
AD22
AE7
AE12
AK9
AG10
AK10
AG13
AK13
AG16
AK16
AG19
AK19
AG22
AK22
AH7
AE18
AE21
AH21
AG6
AH12
AN6
AH15
AH18
AL7
AK6
AE15

L8
L13
L16
L19
L22
N7
N12
N15
N18
N21
P8
P13
P16
P19
P22
T7
F12
F15
G11
G14
J8
J9
J11
K7
K12
K13
K15
K16
T12
T15
T18
T21
U13
U16
U19
U22
K19

+APU_CORE

+APU_CORE

0.22U_0201_6.3V6-K

1

CC129

2

OK

+1.35V

0.22U_0201_6.3V6-K

1

2

QC1/QC2/QC3/QC4 Rds on should less possible, CRB is 11.8mohm,
there is no load swtich for 0.775V power, so it need mos

2

0.22U_0201_6.3V6-K

CC179

CC134

1

2

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

1

1

CC135

2

2

SIVCD@

1

CC176

2

180P_0402_50V8-J

CC136

CC137

180P_0402_50V8-J

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

1

1

CC130

CC131

2

2

DECOUPLING BETWEEN PROCESSOR AND DIMMs
ACROSS VDDIO AND VSS SPLIT

0.22U_0201_6.3V6-K

1

1

CC168

CC169

2

2

VDDCR_CPU

VDDCR_NB

VDDCR_GFX

VDDIO_MEM_S3

VDDCR_FCH_S5

VDDP

VDDP_GFX

VDDP_S5

VDD_18

VDD_18_S5

VDD_33

VDD_33_S5

VDDIO_AUDIO

VDDBT_RTC_G

1

1

1

CC133

CC132

2

2

2

SIVCD@

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

1

CC172

CC170

2

SIVCD@

Design Guide CRBG FP4

9*22uf 0603
8*0.22uf 0402
1*180pf 0402
4*22uf 0603
8*0.22uf 0402
1*180pf 0402
9*22uf 0603
9*0.22uf 0402
1*180pf 0402
8*22uf 0603
6*0.22uf 0402 split*4
1*180pf 0402 split*2
2*10uf 0402
1*0.22uf 0402

4*10uf 0402
1*0.22uf 0402
1*180pf 0402
1*10uf 0402
1*0.22uf 0402

1*10uf 0402
1*0.22uf 0402

1*22uf 0603
1*10uf 0402

1*10uf 0402
1*0.22uf 0402

1*10uf 0402
1*10uf 0402

1*0.22uf 0402

3*1uf 0402

1*0.22uf 0402

1

2

180P_0402_50V8-J

place near SVC/SVD/SVT Bus

9*22uf 0805
8*0.22uf 0402
1*180pf 0402
4*22uf 0805
8*0.22uf 0402
1*180pf 0402
10*22uf 0805
9*0.22uf 0402
1*180pf 0402
8*22uf 0603
6*0.22uf 0402 split*4
1*180pf 0402 split*2
2*10uf 0603
1*0.22uf 0402

4*10uf 0603
1*0.22uf 0402
1*180pf 0402
1*10uf 0603
1*0.22uf 0402

1*10uf 0603
1*0.22uf 0402

1*22uf 0603
1*10uf 0402

1*10uf 0603
1*0.22uf 0402

1*10uf 0603
1*10uf 0403

1*0.22uf 0402

3*1uf 0402

1*0.22uf 0402

1

13*22uf 0603
8*0.22uf 0402
1*180pf 0402
6*22uf 0603
8*0.22uf 0402 split *5
1*180pf 0402
13*22uf 0603
9*0.22uf 0402
1*180pf 0402
8*22uf 0603
8*0.22uf 0402 split*4
1*180pf 0402 split*2
2*10uf 0603
1*0.22uf 0402

4*10uf 0603
1*0.22uf 0402
1*180pf 0402
1*10uf 0603
1*0.22uf 0402

1*10uf 0603
1*0.22uf 0402

1*22uf 0603
1*10uf 0603

1*10uf 0603
1*0.22uf 0402

1*10uf 0603
1*10uf 0603

1*0.22uf 0402

3*1uf 0402

1*0.22uf 0402

+APU_CORE_NB

12

+0.775VALW

CC207

STN@

A A

5

4

12

10U_0603_6.3V6M

CC208

STN@

10U_0603_6.3V6M

+5VALW

CC209

STN@

1

2

1U_0402_6.3V6K

3

UC7

1

VIN1_1

2

VIN1_2

3

VIN2
VCC4EN

G5018RD1U_TDFN8_3X3

STN@

8

VOUT_1

7

VOUT_2

6

SEL

5
9

GND

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

+VDDCR_FCH_S5

APU_S5_MUX_CTRL

APU_S5_MUX_CTRL {7}

2013/08/15

2013/08/15

2013/08/15

1

CC162

CC164

2

10U_0603_6.3V6M

STN@

STN@

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

1

2

10U_0603_6.3V6M

1

CC166

2

0.22U_0201_6.3V6-K

STN@

2013/08/15

2013/08/15

2013/08/15

Title

Title

Title

FP4 (POWER&DECOUPLING)

FP4 (POWER&DECOUPLING)

FP4 (POWER&DECOUPLING)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

CG521

CG521

CG521

Wednesday, February 24, 2016

Wednesday, February 24, 2016

Wednesday, February 24, 2016

1

950

950

950

of

of

of

1.0

1.0

1.0

5

4

3

2

1

GND

FP4 REV 0.93

AMD-CARRIZO_FP4-BGA968@

UC2H

VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212

VSS_213
VSS_215
VSS_214

AV30
AV33
AW22
AY4
AY6
AY8
AY10
AY12
AY14
AY16
AY20
AY22
AY24
AY26
AY28
AY30
BB1
BB33
BC4
BC8
BC12
BC16
BC20
BC24
BC28
BC32

L24
AL10
AK21

UC2J

1

TC4@

1

TC6@

1

TC5@

U30
U31

AN30

RSVD_2
RSVD_3
RSVD_4

@

FP4 REV 0.93

AMD-CARRIZO_FP4-BGA968

UC2G

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62

GND

FP4 REV 0.93

AMD-CARRIZO_FP4-BGA968@

VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98

VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124

L28
M4
M30
N10
N13
N16
N19
N22
N27
P1
P2
P4
P5
P12
P15
P18
P21
P30
P33
T4
T10
T13
T16
T19
T22
T30
U5
U12
U15
U18
U21
U24
V1
V2
V4
W10
W13
W16
W19
W22
Y4
Y5
Y12
Y15
Y18
Y21
Y24
AB1
AB2
AB4
AB10
AB13
AB16
AB19
AB22
AD4
AD9
AD12
AD15
AD18
AD21
AD24

A8
A12
A16
A20
A24

D D

C C

B B

A28
A32

B12
B33

D10
D12
D14
D16
D18
D20
D22
D24
D26
D28
D30

F19
F22
F25
F30
F33

G17
G20
G23
G26

H30

J15
J19
J22
J25
J28

K10
K22
K27
K30
K33

L12
L15
L18
L21
L25

B2

B8

C3

D4

D6

D8

F1

F2

F4

F9

G7

H4

J5

K1

K2

K4

L5

AE10
AE13
AE16
AE19
AE22

AF1
AF4

AG9
AG12
AG15
AG18
AG21

AH4
AH10
AH13
AH16
AH19
AH22

AK1

AK4
AK12
AK15
AK18
AL16
AL19
AL22

AM4

AN9
AN10
AN15
AN18
AN21
AN25
AN28

AP1
AP2
AP4

AP7
AP22
AP27
AP30
AP33

AR6
AR25
AR28

AT4
AT19
AT22
AT30

AU5

AU8
AU11
AU14
AU20
AU23
AU27

AV4
AV7

AV9
AV12
AV15
AV25

VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

2013/08/15

2013/08/15

2013/08/15

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

3

2013/08/15

2013/08/15

2013/08/15

Title

FP4 (VSS)

FP4 (VSS)

FP4 (VSS)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Wednesday, February 24, 2016

Wednesday, February 24, 2016

Date: Sheet

Date: Sheet

Date: Sheet

2

Wednesday, February 24, 2016

CG521

CG521

CG521

10 50

10 50

10 50

1

of

of

of

1.0

1.0

1.0

5

4

+3VS +3VS +3VS +3VALW_APU +3VALW_APU +3VALW_APU +3VALW_APU+3VALW_APU+3VALW_APU +3VALW_APU +3VS_APU

3

2

1

RC163
2K_0402_5%

@

12

RC157
10K_0402_5%

12

RC164
2K_0402_5%

@

12

RC158
10K_0402_5%

12

RC165
2K_0402_5%

@

RC81
10K_0402_5%

@

1 2

12

RC79

0_0402_5%

@

12

RC155
10K_0402_5%

@

12

RC162
2K_0402_5%

12

RC156
10K_0402_5%

12

12

12

RC173
10K_0402_5%

@

RC161
2K_0402_5%

12

RC152

D D

LPC_FRAME#{8,30,35}

LPC_CLK1{8}

CLK_PCI_EC{8,35}

AGPIO3{7}

SYS_RESET#{7}

SUSCLK{7,31}

BLINK{7}

HVB_EN{7,35}

C C

10K_0402_5%

12

12

RC169
10K_0402_5%

@

RC159
2K_0402_5%

@

12

RC153
10K_0402_5%

12

12

RC200
10K_0402_5%

@

RC160
2K_0402_5%

@

12

RC154
10K_0402_5%

@

STRAP PINS

LFRAME_L LPCCLK1 LPCCLK0 GEVENT2_L/AGPIO3 SYS_RESET_L RTCCLK BLINK(for CZL strap)

Signal

Int pull-up Int pull-up Int pull-up Int pull-up

Type II II I I I

PULL
HIGH

B B

PULL
LOW

II

SPI ROM

LPC ROM

Internal
CLK Gen

DefaultDefault

Reserved

Boot Fail Timer
Enabled

Boot Fail Timer
Disabled

Default

CZL CZ

1.8V SPI

3.3VSPI

Default

Enhanced reset
logic (for quicker
S5 resume)

Default

Default to
traditional
reset logic

III

Normal Power Up
&Reset Timing

Default Default

Reserved

Coin Battery

Direct DC

PWROK and RST_L
pin routed to APU

Default

Reserved

HVB_EN

floating

Disable HVB
on FP4 platforms

Default

connected to VSS

Enable HVB
on FP4 platforms

Type I straps become valid immediately after capture with the rising edge of RSMRST_L,they are captured only once when power is first applied to the processor
Type II straps become valid after PWR_GOOD is asserted,straps are captured every time the systems powers up from the S5 state. A transition from S3 to S0 does not trigger capture.

Type II straps should be pulled up to S0 power rail to prevent leakage when the signal is connected to a device in S0 power domain.
If the LPC bus is connected to devices that are on S0 power rail, then a pull-up resistor to VDD_33 is implemented.

All Strap pins must be configured with either external pull-up or pull-down resistors.
Platforms that are designed for AOAC complaint are recommended to use the Alternate Reset by strapping this pin to ‘1’ for CZ AGPIO3

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2013/08/15

2013/08/15

2013/08/15

3

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2013/08/15

2013/08/15

2013/08/15

2

Title

FP4 (STRAPS)

FP4 (STRAPS)

FP4 (STRAPS)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Wednesday, February 24, 2016

Wednesday, February 24, 2016

Wednesday, February 24, 2016

CG521

CG521

CG521

of

of

of

11 50

11 50

11 50

1

1.0

1.0

1.0

5

4

3

2

1

DDRB_DQ[0..63]

DDR3 SO-DIMM A

+VREF_DQ

DDRB_DQ0

D D

C C

DDRB_CKE0{5}

DDRB_BS2#{5}

DDRB_CLK0{5}
DDRB_CLK0#{5}

DDRB_BS0#{5}
DDRB_WE#{5}

DDRB_CAS#{5}

DDRB_CS1#{5}

B B

A A

+3VS

CD28

2.2U_0402_6.3V6M

1

2

SIVCD@

CD29 0.1U_0201_6.3V6-K

1

2

5

DDRB_DQ1
DDRB_DM0
DDRB_DQ2

DDRB_DQ3
DDRB_DQ8

DDRB_DQ9
DDRB_DQS#1

DDRB_DQS1
DDRB_DQ10

DDRB_DQ11
DDRB_DQ16

DDRB_DQ17
DDRB_DQS#2

DDRB_DQS2
DDRB_DQ18

DDRB_DQ19
DDRB_DQ24

DDRB_DQ25
DDRB_DM3
DDRB_DQ26

DDRB_DQ27

DDRB_CKE0

DDRB_BS2#
DDRB_MA12

DDRB_MA9
DDRB_MA8

DDRB_MA5
DDRB_MA3

DDRB_MA1
DDRB_CLK0

DDRB_CLK0#
DDRB_MA10

DDRB_BS0#
DDRB_WE#

DDRB_CAS#
DDRB_MA13

DDRB_CS1#

DDRB_DQ32
DDRB_DQ33

DDRB_DQS#4
DDRB_DQS4

DDRB_DQ34
DDRB_DQ35

DDRB_DQ40
DDRB_DQ41

DDRB_DM5
DDRB_DQ42

DDRB_DQ43
DDRB_DQ48

DDRB_DQ49
DDRB_DQS#6

DDRB_DQS6
DDRB_DQ50

DDRB_DQ51
DDRB_DQ56

DDRB_DQ57
DDRB_DM7
DDRB_DQ58

DDRB_DQ59

JDDR1

1

VREF_DQ

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS1#

29

DQS1

31

VSS11

33

DQ10

35

DQ11

37

VSS13

39

DQ16

41

DQ17

43

VSS15

45

DQS2#

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25

61

VSS22

63

DM3

65

VSS23

67

DQ26

69

DQ27

71

VSS25

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

TEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS4#

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS6#

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

GND1

207

BOSS1

LCN_DAN06-K4406-0103

ME@

VSS1

DQ4
DQ5

VSS3

DQS0#

DQS0

VSS6

DQ6
DQ7

VSS8
DQ12
DQ13

VSS10

DM1

RESET#

VSS12

DQ14
DQ15

VSS14

DQ20
DQ21

VSS16

DM2

VSS17

DQ22
DQ23

VSS19

DQ28
DQ29

VSS21
DQS3#

DQS3

VSS24

DQ30
DQ31

VSS26

CKE1
VDD2

VDD4

VDD6

VDD8

VDD10

CK1

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30

DM4

VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35
DQS5#

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42

DM6

VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47
DQS7#

DQS7

VSS50

DQ62
DQ63

VSS52

EVENT#

SDA
SCL

VTT2
GND2

BOSS2

2

DDRB_DQ4

4

DDRB_DQ5

6
8

DDRB_DQS#0

10

DDRB_DQS0

12
14

DDRB_DQ6

16

DDRB_DQ7

18
20

DDRB_DQ12

22

DDRB_DQ13

24
26

DDRB_DM1

28

MEM_MB_RST#

30
32

DDRB_DQ14

34

DDRB_DQ15

36
38

DDRB_DQ20

40

DDRB_DQ21

42
44

DDRB_DM2

46
48

DDRB_DQ22

50

DDRB_DQ23

52
54

DDRB_DQ28

56

DDRB_DQ29

58
60

DDRB_DQS#3

62

DDRB_DQS3

64
66

DDRB_DQ30

68

DDRB_DQ31

70
72

DDRB_CKE1

74
76

DDRB_MA15

78

A15
A14

A11

A7
A6

A4
A2

A0

BA1

S0#

80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206
208

DDRB_MA14
DDRB_MA11

DDRB_MA7
DDRB_MA6

DDRB_MA4
DDRB_MA2

DDRB_MA0
DDRB_CLK1

DDRB_CLK1#
DDRB_BS1#

DDRB_RAS#
DDRB_CS0#

DDRB_ODT0
DDRB_ODT1

DDRB_DQ36
DDRB_DQ37

DDRB_DM4
DDRB_DQ38

DDRB_DQ39
DDRB_DQ44

DDRB_DQ45
DDRB_DQS#5

DDRB_DQS5
DDRB_DQ46

DDRB_DQ47
DDRB_DQ52

DDRB_DQ53
DDRB_DM6
DDRB_DQ54

DDRB_DQ55
DDRB_DQ60

DDRB_DQ61
DDRB_DQS#7

DDRB_DQS7
DDRB_DQ62

DDRB_DQ63
MEM_MB_EVENT#

APU_SMB_DATA
APU_SMB_CLK

1

CD70
22P_0402_50V8-J

2

RF@

DDRB_CKE1 {5}

DDRB_CLK1 {5}
DDRB_CLK1# {5}

DDRB_BS1# {5}
DDRB_RAS# {5}

DDRB_CS0# {5}
DDRB_ODT0 {5}

DDRB_ODT1 {5}

+VREF_CA

+0.675VS

0.65A@0.75V

RF

4

MEM_MB_RST# {5}

CD120 0.1U_0201_6.3V6-K

1

2

@

forMEM_MB_RST#overshootissue

+1.35V+1.35V

MEM_MB_EVENT# {5}
APU_SMB_DATA {7,31}
APU_SMB_CLK {7,31}

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

APU_M_VREFDQ{5}

0.1U_0201_6.3V6-K

3

DDRB_DQS[0..7]
DDRB_DQS#[0..7]
DDRB_MA[0..15]
DDRB_DM[0..7]

3A@1.5V

+1.35V

CD16

+1.35V

CD62

CD24

2013/08/15

2013/08/15

2013/08/15

1 2

R251 0_0402_5%@

LayoutNote:
PlacenearDIMM1

1

1

2

2

10U_0805_10V6K

1

1

CD63

2

2

LayoutNote:

+0.675VS

PlacenearDIMM1

1U_0402_6.3V6K

1

1

CD25

@

2

2

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

CD17 0.1U_0201_6.3V6-K

1

2

@

10U_0805_10V6K

CD66

1U_0402_6.3V6K

1

CD26

2

Deciphered Date

Deciphered Date

Deciphered Date

DDRB_DQ[0..63] {5}
DDRB_DQS[0..7] {5}
DDRB_DQS#[0..7] {5}
DDRB_MA[0..15] {5}

DDRB_DM[0..7] {5}

+1.35V

12

RD10
1K_0402_1%

+VREF_DQ

1K_0402_1%

15mil 15mil

CD116 0.1U_0201_6.3V6-K

RD11

1

1

2

1

2

CD5 .047U_0201_6.3V6K

22U_0603_6.3V6-M

1

2

2013/08/15

2013/08/15

2013/08/15

2

CD117
1000P_0201_50V7-K

2

CD20 0.1U_0201_6.3V6-K

1

2

CD6 .047U_0201_6.3V6K

1

@

2

CD123 22P_0402_50V8-J

RF@

1K_0402_1%

CD21 0.1U_0201_6.3V6-K

CD22 0.1U_0201_6.3V6-K

1

2

@

CD7 .047U_0201_6.3V6K

1

1

@

@

2

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

1K_0402_1%

1 2

CD19

1

CD18

0.1U_0201_6.3V6-K

2

@

RF@

1

1

CD67

@

2

2

22U_0805_6.3V6M

1U_0402_6.3V6K

1

CD27

@

2

22P_0402_50V8-J

4.7U_0603_6.3V6K

+1.35V

12

RD12

12

RD25

CD23 0.1U_0201_6.3V6-K

1

2

@

CD11 22P_0402_50V8-J

1

RF@

2

DDRIII SO-DIMM A

DDRIII SO-DIMM A

DDRIII SO-DIMM A

1

2

CD58 0.1U_0201_6.3V6-K

1

2

@

CD12 22P_0402_50V8-J

CD121 22P_0402_50V8-J

1

1

RF@

2

2

Wednesday, February 24, 2016

Wednesday, February 24, 2016

Wednesday, February 24, 2016

CD118 0.1U_0201_6.3V6-K

CD59 0.1U_0201_6.3V6-K

1

2

1

RF@

2

CG521

CG521

CG521

+VREF_CA

1

CD119
1000P_0201_50V7-K

2

CD60 0.1U_0201_6.3V6-K

1

2

CD122 22P_0402_50V8-J

RF@

1

1

2

@

12 50

12 50

12 50

CD61 0.1U_0201_6.3V6-K

@

RF

1.0

1.0

1.0

of

of

of

5

D D

C C

4

3

2

1

B B

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2

2013/08/15

2013/08/15

2013/08/15

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2013/08/15

2013/08/15

2013/08/15

Title

DDRIII SO-DIMM B

DDRIII SO-DIMM B

DDRIII SO-DIMM B

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

D

D

D

Date: Sheet

Date: Sheet

Date: Sheet

1

Wednesday, February 24, 2016

Wednesday, February 24, 2016

Wednesday, February 24, 2016

CG521

CG521

CG521

of

of

of

13 50

13 50

13 50

1.0

1.0

1.0

5

4

3

2

1

Power-Up/Down Sequence

"Topaz" has the following requirements with regards to power-supply sequencing to

D D

avoid damaging the ASIC:

All the ASIC supplies must reach their respective nominal voltages within 20 ms
of the start of the ramp-up sequence, though a shorter ramp-up duration is
preferred. The maximum slew rate on all rails is 50 mV/μs.
It is recommended that the 3.3-V rail ramp up first.
The 3.3-V, 1.8-V, and 0.95-V rails must reach their ready state at least 10 μs
before VDDC, VDDCI, and VMEMIO start to ramp up.
The power rails that are shared with other components on the system should be
gated for the dGPU so that when the dGPU is powered down (for example
AMD PowerXpress idle state), all the power rails are removed from the dGPU.
The gate circuits must meet the slew rate requirement (such as ≤ 50 mV/μs).
For power down, reversing the ramp-up sequence is recommended.

VRAM ID config

Memory Type

NA

128Mx16

NA

VRAM ID PU resistor PD resistor

PS_3[3:1]

100

111

RV63 RV70

4.53K 4.99K

NC4.75K

NA

110

10K3.4K

0~20ms

VDDR3(+3VGS)

C C

VDD_CT(+1.8VGS)

0~20ms

256Mx16

PCIE_VDDC(+0.95VGS)

Hynix

H5TC4G63CFR-N0C 4Gb 900(1G)

Micron

MT41J256M16LY-091G:N 4Gb 900(1G)

Samsung

K4W4G1646E-BC1A 4Gb 900(1G)

000

010

001

NC 4.75K

4.53K 2K

8.45K 2K

10usmin.

VDDR1(+1.35VGS)

VDDC/VDDCI(+VGA_CORE)

PERSTb(GPU_RST#)

100msmin.

100usmin.

REFCLK(CLK_PCIE_VGA)

B B

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2013/08/08

2013/08/08

2013/08/08

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2013/08/05

2013/08/05

2013/08/05

Title

VGA Notes List

VGA Notes List

VGA Notes List

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Wednesday, February 24, 2016

Wednesday, February 24, 2016

Wednesday, February 24, 2016

Date: Sheet

Date: Sheet

Date: Sheet

CG521

CG521

CG521

1

of

of

of

14 50

14 50

14 50

1.0

1.0

1.0

5

PCIE_CTX_C_GRX_P[3..0]{4}
PCIE_CTX_C_GRX_N[3..0]{4}

PCIE_CTX_C_GRX_P[3..0]
PCIE_CTX_C_GRX_N[3..0]

4

UV1A

3

PCIE_CRX_GTX_P[3..0]
PCIE_CRX_GTX_N[3..0]

2

PCIE_CRX_GTX_P[3..0] {4}
PCIE_CRX_GTX_N[3..0] {4}

1

PCIE_CTX_C_GRX_P0
PCIE_CTX_C_GRX_N0

D D

C C

B B

PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_N1

PCIE_CTX_C_GRX_P2
PCIE_CTX_C_GRX_N2

PCIE_CTX_C_GRX_P3
PCIE_CTX_C_GRX_N3

AF30
AE31

AE29
AD28

AD30
AC31

AC29
AB28

AB30
AA31

AA29

Y28

Y30

W31

W29

V28

V30

U31

U29

T28

T30

R31

R29

P28

P30

N31

N29
M28

M30

L31

L29
K30

PCIE_RX0P
PCIE_RX0N

PCIE_RX1P
PCIE_RX1N

PCIE_RX2P
PCIE_RX2N

PCIE_RX3P
PCIE_RX3N

PCIE_RX4P
PCIE_RX4N

PCIE_RX5P
PCIE_RX5N

PCIE_RX6P
PCIE_RX6N

PCIE_RX7P
PCIE_RX7N

NC#V30
NC#U31

NC#U29
NC#T28

NC#T30
NC#R31

NC#R29
NC#P28

NC#P30
NC#N31

NC#N29
NC#M28

NC#M30
NC#L31

NC#L29
NC#K30

PCIE_TX0P
PCIE_TX0N

PCIE_TX1P
PCIE_TX1N

PCIE_TX2P
PCIE_TX2N

PCIE_TX3P
PCIE_TX3N

PCIE_TX4P
PCIE_TX4N

PCIE_TX5P
PCIE_TX5N

PCIE_TX6P
PCIE_TX6N

PCIE_TX7P
PCIE_TX7N

NC#W24
NC#W23

NC#V27

PCI EXPRESS INTERFACE

NC#U26

NC#U24
NC#U23

NC#T26
NC#T27

NC#T24
NC#T23

NC#P27
NC#P26

NC#P24
NC#P23

NC#M27
NC#N26

PCIE_CRX_C_GTX_P0 PCIE_CRX_GTX_P0

AH30

PCIE_CRX_C_GTX_N0 PCIE_CRX_GTX_N0

AG31

PCIE_CRX_C_GTX_P1

AG29

PCIE_CRX_C_GTX_N1

AF28

PCIE_CRX_C_GTX_P2

AF27

PCIE_CRX_C_GTX_N2

AF26

PCIE_CRX_C_GTX_P3

AD27

PCIE_CRX_C_GTX_N3

AD26

AC25
AB25

Y23
Y24

AB27
AB26

Y27
Y26

W24
W23

V27
U26

U24
U23

T26
T27

T24
T23

P27
P26

P24
P23

M27
N26

change the GPU PN to AMD(EXO-S3 PRO), symbol check ok
11/4 change to PC sample SA000074V10

CV1 0.1U_0201_6.3V6-KCZLPX@
CV2 0.1U_0201_6.3V6-KCZLPX@

CV3 0.1U_0201_6.3V6-KCZLPX@
CV4 0.1U_0201_6.3V6-KCZLPX@

CV5 0.1U_0201_6.3V6-KCZLPX@
CV6 0.1U_0201_6.3V6-KCZLPX@

CV7 0.1U_0201_6.3V6-KCZLPX@
CV8 0.1U_0201_6.3V6-KCZLPX@

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

PCIE_CRX_GTX_P1
PCIE_CRX_GTX_N1

PCIE_CRX_GTX_P2
PCIE_CRX_GTX_N2

PCIE_CRX_GTX_P3
PCIE_CRX_GTX_N3

with BOM strcture control, CV1--CV8 change to 0.22uf for CZ

AK30
AK32

N10

AL27

CLOCK

PCIE_REFCLKP
PCIE_REFCLKN

TEST_PG

PERSTB

AMD R16M-M1-30

EXO@

CALIBRATION

PCIE_CALR_TX
PCIE_CALR_RX

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Y22
AA22

2013/08/08

2013/08/08

2013/08/08

3

1 2

RV3 1.69K_0402_1%PX@

1 2

RV5 1K_0402_1%PX@

VR_VGA_PWRGD{7,48}

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

+0.95VGS

GPU_RST#
VR_VGA_PWRGD

DV3

PX@

2
3

BAT54AWT1G_SOT323-3

2013/08/05

2013/08/05

2013/08/05

1

2

VGA_PWROK

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

VGA_PWROK {48}

ATI_JET-LE_PCIE

ATI_JET-LE_PCIE

ATI_JET-LE_PCIE

Wednesday, February 24, 2016

Wednesday, February 24, 2016

Wednesday, February 24, 2016

CG521

CG521

CG521

1

of

of

of

15 50

15 50

15 50

1.0

1.0

1.0

1 2

GPU_RST#

CLK_PCIE_GPU
CLK_PCIE_GPU#

RV41K_0402_1% PX@

12

RV6
100K_0402_5%

PX@

4

CLK_PCIE_GPU{8}
CLK_PCIE_GPU#{8}

GPU_RST#{16}

1 2

RV7 0_0402_5%@

+3VGS

A A

PXS_RST#{7,8}
PLT_RST#{7,28,31}

5

5

1

IN1

VCC

OUT

2

IN2

GND

MC74VHC1G08DFT2G_SC70-5

3

PX@

UV2

GPU_RST#

4