Lenovo Ideapad 110-15IBR Schematic

A

www.laptoprepairsecrets.com

1 1

B

C

D

E

LCFC Confidential

CGx20 M/B Schematics Document

2 2

NM-A805 REV:0.1

Intel Braswell M-Processor with DDRIIIL

2015-10-09

3 3

4 4

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS S HEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS S HEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS S HEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FU TURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FU TURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FU TURE CENTER.

A

B

REV:0.1

Issued Date

Issued Date

Issued Date

2015/10/08

2015/10/08

2015/10/08

C

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2015/03/23

2015/03/23

2015/03/23

D

Title

Title

Title

Cover Page

Cover Page

Cover Page

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Tuesday, December 08, 2015

Tuesday, December 08, 2015

Date: Sheet of

Date: Sheet of

Date: Sheet of

Tuesday, December 08, 2015

CGx20

CGx20

CGx20

E

1 57

1 57

1 57

0.1

0.1

0.1

A

www.laptoprepairsecrets.com

B

C

D

E

Memory BUS (DDR3L)
Dual Channel

HDMI Conn.

Page 34

1 1

eDP Conn

Int. Camera

USB 2.0 Port3

Page 33

HDMI

eDP x2 Lane

USB 2.0 1x

Braswell-M (4.5W)

BGA-1170

25mm*27mm

SATA HDD

Page 42

2 2

SATA Port0

SATA ODD

Page 42

SATA Port1

LAN

RJ45 Conn.

Page 38

3 3

Realtek ALC3240

Page 43 Page 43

Mic

Realtek RTL8107E

(10M/100M)

Page 37

Codec

HP&Mic Combo Conn.

PCIe Port3

SPK Conn.

SATA Gen3

SATA Gen1

PCIe 1x

HD Audio

Page 4~12

EC
ITE IT8886E-LQFP

Page 44

LPC BUS

1.35V DDR3L 1600 MT/s

USB 3.0 1x

USB 2.0 1x

USB 2.0 1x

USB 2.0 1x

USB2.0 1x

PCIe 1x

USB Left 3.0 Conn

Page 41

USB Left 2.0 Conn

Page 45

Cardreader Realtek
RTS5170

Page 30

NGFF Card WLAN&BT

Page 40

TPM

ST33ZP24AR28PVSP

USB 3.0 Port1

USB 2.0 Port1

USB 2.0 Port0

USB 2.0 Port3

MD 16x DDR3L 8Pcs

UP TO 8G

SD/MMC Conn.

PCIe Port2

USB 2.0 Port2

Page 14

Sub-board ( for 15")

Touch Pad Int.KBD

Page 45 Page 45

4 4

A

B

SPI ROM
8MB

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INF ORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND TRADE SECRET INF ORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND TRADE SECRET INF ORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

C

2015/10/08

2015/10/08

2015/10/08

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

2015/03/23

2015/03/23

2015/03/23

ODD Board

Title

Title

Title

Block Diagram

Block Diagram

Block Diagram

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Tuesday, December 08, 2015

Tuesday, December 08, 2015

Tuesday, December 08, 2015

Date: Sheet of

Date: Sheet of

Date: Sheet of

CGx20

CGx20

CGx20

E

2 57

2 57

2 57

0.1

0.1

0.1

Voltage Rails

www.laptoprepairsecrets.com

A

B

C

D

E

, X --> Means OFF )( O --> Means ON

+5VS

Power Plane

B+

+3VALW

+3VL

1 1

State

S0

+5VALW

O

+3VALW_SOC

+1.0VALW

+1.8VALW

O O O

+1.35V

O

+3VS

+1.5VS

+0.68VS

CPU_CORE

GFX_CORE

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SIGNAL

SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

ON

ON

ON

ON

ON

ONONON ON

ON

OFF

OFF

HIGH HIGH HIGH HIGH

LOW

LOW

LOW

LOW LOW LOW LOW

HIGH

LOWLOWLOW

HIGHHIGHHIGH

HIGH

HIGH

ON

OFF

OFF

OFF

LOW

OFF

OFF

OFF

USB Port Table

S3

S5 S4/AC Only

S5 S4
Battery only

S5 S4
AC & Battery

2 2

don't exist

STATE SLP_S3#SLP_S1#

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk) ON

S5 (Soft OFF)

SIGNAL

O

O X X

O

XX

SLP_S4# +VS+V

LOW

HIGH HIGH

LOW

LOW HIGH

LOW

LOW LOW

LOW LOW

O

O

X

X

+VALW

HIGHHIGHHIGH

ON

ON

ON

ON

LOW OFF

ON

OO O X

XX

X

+VALW_PCH

ONONON

ONONON

ON

OFF

X

X

Clock

ONON

ON

LOW

OFF OFF

OFF

OFF

OFF

OFF

XHCI

USB 3.0

USB 2.0

USB HUB

Port

0

1

0

1

2
3
4
1
2

3
4

Port device

USB Port (Left Side)

USB3.0 Card Reader

USB Port (Left Side)

USB Port (Right Side)
BT
Camera
USB Port (Right Side)

BOM Structure Table

BTO ItemBOM Structure

AOAC@
OPT@

UMA@
14@
15@

100M@

N15SGT@

N15VGM@

GIGA@

GC6@

TS@

RANKA@

RANKB@

ME@

CD@

@

AOAC support part

GPU Part

UMA SKU ID part

For 14" part

For 15" part

100M LAN part

N15SGT Part

N15GSM Part

GIGA LAN Part

GPU GC6 Part

Touch Screen part

GPU VRAM RANKA PART

GPU VRAM RANKB PART

Connector

COST DOWN

Not stuff

PCIE PORT LIST

SMBUS Control Table

WLAN

3 3

EC_SMB_DA1

EC_SMB_CK2

EC_SMB_DA2

PCH_SMB_CLK

PCH_SMB_DATA

SOURCE

ECEC_SMB_CK1

+3VALW

EC

+3VS

PCH

+3VALW_PCH

VGA BATT SODIMM

X

V

+3VGS

X

EC SM Bus1 address

4 4

Device

Smart Battery

Charger

0001 011X b

need to update

A

IT8986E

V

+3VALW

X

V

+3VS

X X X

X

V V

+3VS +3VS

EC SM Bus2 address

Device

Thermal Sensor EMC1403-2

VGA

Thermal

WiMAX

Sensor

X XV

X

X

V

+3VS

V

Address

1001_100xb(reserve)

0x9E(base on NV default)

B

+3VALW_PCH

TP

PCH

X

PCH SM Bus address

Device

DDR DIMMA

Wlan

TP

Module

XX

X

X

charger

V

X

X

Port Device

1

Discrete GPU

2

Discrete GPU

3

WLAN

4

LAN

5

H4T@
M4T@
S4T@@

6
7
8

Address

1010 000Xb

Rsvd

need to update

Security Cl assification

Security Cl assification

Security Cl assification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

C

2015/10/08

2015/10/08

2015/10/08

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

2015/03/23

2015/03/23

2015/03/23

Hynix VRAM Part

Micron VRAM Part

Samsung VRAM Part

DDI PORT LIST

Port Device

DDI0
DDI1
DDI2

DP TO VGA
eDP
HDMI

Title

Title

Title

Notes List

Notes List

Notes List

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Tuesday, December 08, 2015

Tuesday, December 08, 2015

Date: Sheet

Date: Sheet

Date: Sheet

Tuesday, December 08, 2015

CGx20

CGx20

CGx20

E

of

of

of

3 57

3 57

3 57

0.1

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0.1

5

www.laptoprepairsecrets.com

DDI0_RCOMP_P

12

RC1
402_0402_1%

DDI0_RCOMP_N

DDI1_RCOMP_P

12

RC2

D D

402_0402_1%

DDI1_RCOMP_N

DP TO VGA Converter

CPU_EDP_TX0+33

CPU_EDP_TX0-33

CPU_EDP_TX1+33

CPU_EDP_TX1-33

DDI0_RCOMP_P
DDI0_RCOMP_N PCH_ENBKL

CPU_EDP_TX0+
CPU_EDP_TX0­CPU_EDP_TX1+
CPU_EDP_TX1-

EDP

C C

HDMI D2

HDMI D1

HDMI D0

HDMI CLK

B B

CPU_EDP_AUX33

CPU_EDP_AUX#33

PCH_ENVDD33

HDMI_TX2+34
HDMI_TX2-34

HDMI_TX1+34
HDMI_TX1-34
HDMI_TX0+34
HDMI_TX0-34

HDMI_CLK+34
HDMI_CLK-34

HDMI_HPD34

DDPB_CLK34

DDPB_DATA34

CPU_EDP_AUX
CPU_EDP_AUX#

EDP_HPD#

PCH_ENBKL
PCH_BKLT_CTRL_Q

PCH_ENVDD
DDI1_RCOMP_P
DDI1_RCOMP_N

HDMI_TX2+
HDMI_TX2-

HDMI_TX1+
HDMI_TX1­HDMI_TX0+
HDMI_TX0-

HDMI_CLK+
HDMI_CLK-

DDI PORT LIST

Port Device

DDI0
DDI1
DDI2

NA
eDP
HDMI

4

UC1C

D50

DDI0_TXP_0

C51

DDI0_TXN_0

H49

DDI0_TXP_1

H50

DDI0_TXN_1

F53

DDI0_TXP_2

F52

DDI0_TXN_2

G53

DDI0_TXP_3

G52

DDI0_TXN_3

H47

DDI0_AUXP

H46

DDI0_AUXN

W51

HV_DDI0_HPD

Y51

HV_DDI0_DDC_SCL

Y52

HV_DDI0_DDC_SDA

V52

PANEL0_BKLTEN

V51

PANEL0_BKLTCTL

W53

PANEL0_VDDEN

F38

DDI0_PLLOBS_P

G38

DDI0_PLLOBS_N

J51

DDI1_TXP_0

H51

DDI1_TXN_0

K51

DDI1_TXP_1

K52

DDI1_TXN_1

L53

DDI1_TXP_2

L51

DDI1_TXN_2

M52

DDI1_TXP_3

M51

DDI1_TXN_3

M42

DDI1_AUXP

K42

DDI1_AUXN

R51

HV_DDI1_HPD

P51

PANEL1_BKLTEN

P52

PANEL1_BKLTCTL

R53

PANEL1_VDDEN

F47

DDI1_PLLOBS_P

F49

DDI1_PLLOBS_N

F40

DDI2_TXP_0

G40

DDI2_TXN_0

J40

DDI2_TXP_1

K40

DDI2_TXN_1

F42

DDI2_TXP_2

G42

DDI2_TXN_2

D44

DDI2_TXP_3

F44

DDI2_TXN_3

D48

DDI2_AUXP

C49

DDI2_AUXN

U51

HV_DDI2_HPD

T51

HV_DDI2_DDC_SCL

T52

HV_DDI2_DDC_SDA

B53

RSVD_B53

A52

RSVD_A52

E52

RSVD_E52

D52

RSVD_D52

B50

RSVD_B50

B49

RSVD_B49

E53

RSVD_E53

C53

RSVD_C53

A51

RSVD_A51

A49

RSVD_A49

G44

RSVD_G44

BRASWELL_FCBGA151170

@

V1P0
V1P0

V1P0
V1P0

V1P0
V1P0

V1P0
V1P0

V1P0
V1P0

V1P0
V1P0

V1P0
V1P0

V1P0
V1P0

V1P0
V1P0

V1P0
V1P0

V1P0
V1P0

V1P0
V1P0

V1P0
V1P0

V1P0
V1P0

V1P0
V1P0

NC's

?

DDI0

V1P8A

V1P8
V1P8

V1P8
V1P8
V1P8

DDI1

DDI2

3 OF 13

V1P8A

V1P8
V1P8
V1P8

V1P8A

V1P8
V1P8

CHV_MCP_EDS

DDR3_M0_DQ_63

REV = 1.2

SDMMC1

SDMMC2

?

SDMMC3

V1P8
V1P8

RSVD_M44
RSVD_K44

RSVD_K48
RSVD_K47

V1P24

MCSI_1_CLKP

V1P24

MCSI_1_CLKN

V1P24

MCSI_1_DP_0

V1P24

MCSI_1_DN_0

V1P24

MCSI_1_DP_1

V1P24

MCSI_1_DN_1

V1P24

MCSI_1_DP_2

V1P24

MCSI_1_DN_2

V1P24

MCSI_1_DP_3

V1P24

MCSI_1_DN_3

MCSI and Camera interface

V1P24

MCSI_2_CLKP

V1P24

MCSI_2_CLKN

V1P24

MCSI_2_DP_0

V1P24

MCSI_2_DN_0

V1P24

MCSI_2_DP_1

V1P24

MCSI_2_DN_1

MSCI_3_CLKP
MSCI_3_CLKN

V1P24

MCSI_COMP

GP_CAMERASB00
GP_CAMERASB01
GP_CAMERASB02
GP_CAMERASB03
GP_CAMERASB04
GP_CAMERASB05
GP_CAMERASB06
GP_CAMERASB07
GP_CAMERASB08

GP_CAMERASB09
GP_CAMERASB10
GP_CAMERASB11

V1P8

SDMMC1_CLK

V1P8

SDMMC1_CMD

V1P8

SDMMC1_D0

V1P8

SDMMC1_D1

V1P8

SDMMC1_D2

V1P8

SDMMC1_D3_CD_N

V1P8

SMMC1_D4_SD_W E

V1P8

SMMC1_D5

V1P8

SMMC1_D6

V1P8

SMMC1_D7

V1P8

SMMC1_RCLK

V1P8

SDMMC1_RCOMP

V1P8

SDMMC2_CLK

V1P8

SDMMC2_CMD

V1P8

SDMMC2_D0

V1P8

SDMMC2_D1

V1P8

SDMMC2_D2

V1P8

SDMMC2_D3_CD_N

V1P8
V1P8

SDMMC3_CLK

V1P8

SDMMC3_CMD

SDMMC3_CD_N

V1P8
V1P8

SDMMC3_D0
SDMMC3_D1

V1P8

SDMMC3_D2

V1P8

SDMMC3_D3

V1P8

SDMMC3_1P8_EN

SDMMC3_PWR_ EN_N

SDMMC3_RCOMP

3

M44
K44

K48
K47

T44
T45

Y47
Y48
V45
V47
V50
V48
T41
T42

P50
P48

P47
P45
M48
M47

T50
T48

P44

AB41
AB45
AB44
AC53
AB51
AB52
AA51
AB40
Y44

Y42
Y41
V40

M7

P6

M6
M4
P9
P7
T6
T7
T10
T12
T13
P13

K10
K9

M12
M10
K7
K6

F2
D2
K3

J1
J3
H3
G2

K2
L3
P12

RC107 80.6_0402_1%

RC24

1 2

150_0402_1%

GPIO_CAM_8

RC106

1 2

100_0402_1%

1 2

GPIO_CAM_8 12

GPIO_CAM_9 12

GPIO_CAM_11 12

2

1

+1.8VALW

EDP_HPD

EDP_HPD#

QC4A

61

D

S

G

2N7002KDWH_SOT363-6

12

RC9290
1K_0402_5%

2

12

RC4

0604

100K_0402_5%

0604

CPU_EDP_HPD 33

PCH_ENBKL 33

PCH_ENBKL can direct connect to EC for costdown

+3VS

RPC26
10K_0404_4P2R_5%

G25

QC2A
PJT138K_SOT363-6

QC2B

D2 3

PJT138K_SOT363-6

S2

4

PCH_EDP_PWM 33

PCH_BKLT_CTRL_Q

+3VALW

1 4

2 3

D1 6S11

2

G1

A A

Title

Title

Security Cl assification

Security Cl assification

Security Cl assification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

3

2015/10/08

2015/10/08

2015/10/08

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2015/03/23

2015/03/23

2015/03/23

Title

SOC (DDI,EDP,HDMI)

SOC (DDI,EDP,HDMI)

SOC (DDI,EDP,HDMI)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Tuesday, December 08, 2015

Tuesday, December 08, 2015

Tuesday, December 08, 2015

Date: Sheet

Date: Sheet

Date: Sheet

CGx20

CGx20

CGx20

of

4 57

of

4 57

of

4 57

1

0.1

0.1

0.1

5

www.laptoprepairsecrets.com

DDRA_MA15
DDRA_MA14
DDRA_MA13
DDRA_MA12

12

M0_RCOMPPD

RC34
182_0402_1%

DDRA_MA11
DDRA_MA10
DDRA_MA9
DDRA_MA8
DDRA_MA7
DDRA_MA6
DDRA_MA5
DDRA_MA4
DDRA_MA3
DDRA_MA2
DDRA_MA1
DDRA_MA0

DDRA_DRAMRST#_R
DDR_PWROK

D D

DDRA_BS2#14
DDRA_BS1#14
DDRA_BS0#14

DDRA_CAS#14
DDRA_RAS#14
DDRA_WE#14

DDRA_CS0#14

DDRA_CLK014

DDRA_CLK0#14

DDRA_CKE014

DDRA_ODT014

C C

INTEL PDG 182 ohm
SD00001KG00

DDRA_DRAMRST#14

B B

DDRA_DM6
DDRA_DM7
DDRA_DM5
DDRA_DM4
DDRA_DM3
DDRA_DM1
DDRA_DM2
DDRA_DM0

DDRA_DQS6
DDRA_DQS#6
DDRA_DQS7
DDRA_DQS#7
DDRA_DQS5
DDRA_DQS#5
DDRA_DQS4
DDRA_DQS#4
DDRA_DQS3
DDRA_DQS#3
DDRA_DQS1
DDRA_DQS#1
DDRA_DQS2
DDRA_DQS#2
DDRA_DQS0
DDRA_DQS#0

BD49
BD47
BF44
BF48
BB49

BJ45
BE52
BD44
BE46
BB46
BH48
BD42
BH47

BJ48
BC42
BB47

BF52
AY40
BH46

BG45
BA40
BH44
AU38
AY38

BD38
BF38
AY42

BD40
BF40
BB44

AT30
AU30

AV36
BA38

AT28
AU28

BA42
AV28

BA28

BH30
BD32
AY36
BG41
BA53
AP44
AT48
AP52

BH32
BG31
BC30
BC32
AT32
AT34
BH40
BG39
AY52
BA51
AT42
AT41
AV47
AV48

AM52
AM51

1

CC143

0.1u_0201_10V6K

2

@

DDR3_M0_MA _15
DDR3_M0_MA _14
DDR3_M0_MA _13
DDR3_M0_MA _12
DDR3_M0_MA _11
DDR3_M0_MA _10
DDR3_M0_MA _9
DDR3_M0_MA _8
DDR3_M0_MA _7
DDR3_M0_MA _6
DDR3_M0_MA _5
DDR3_M0_MA _4
DDR3_M0_MA _3
DDR3_M0_MA _2
DDR3_M0_MA _1
DDR3_M0_MA _0

DDR3_M0_B S_2
DDR3_M0_B S_1
DDR3_M0_B S_0

DDR3_M0_CA S_N
DDR3_M0_RA S_N
DDR3_M0_W E_N
DDR3_M0_CS B_1
DDR3_M0_CS B_0

DDR3_M0_CK _1
DDR3_M0_CK B_1
DDR3_M0_CK E_1

DDR3_M0_CK _0
DDR3_M0_CK B_0
DDR3_M0_CK E_0

RSVD_AT30
RSVD_AU3 0

DDR3_M0_O DT_0
DDR3_M0_O DT_1

DDR3_M0_O CAVREF
DDR3_M0_O DQVREF

DDR3_M0_DR AMRST_N
DDR3_DRAM_ PWROK

DDR3_M0_RC OMPPD

DDR3_M0_DM _7
DDR3_M0_DM _6
DDR3_M0_DM _5
DDR3_M0_DM _4
DDR3_M0_DM _3
DDR3_M0_DM _2
DDR3_M0_DM _1
DDR3_M0_DM _0

DDR3_M0_DQ S_7
DDR3_M0_DQ SB_7
DDR3_M0_DQ S_6
DDR3_M0_DQ SB_6
DDR3_M0_DQ S_5
DDR3_M0_DQ SB_5
DDR3_M0_DQ S_4
DDR3_M0_DQ SB_4
DDR3_M0_DQ S_3
DDR3_M0_DQ SB_3
DDR3_M0_DQ S_2
DDR3_M0_DQ SB_2
DDR3_M0_DQ S_1
DDR3_M0_DQ SB_1
DDR3_M0_DQ S_0
DDR3_M0_DQ SB_0

BRASWELL_FCBGA151170

REV = 1.2
@

1 2

RC9291

0_0402_5%

?

CHV_MCP_EDS

DDR0

1 OF 13

4

DDRA_DQ[63:0] 14

DDRA_MA[15:0] 14

DDRA_DQS[7:0] 14

DDRA_DQS#[7:0] 14

DDRA_DM[7:0] 14

DDR3_M0_DQ_63UC1A

DDR3_M0_DQ _63
DDR3_M0_DQ _62
DDR3_M0_DQ _61
DDR3_M0_DQ _60
DDR3_M0_DQ _59
DDR3_M0_DQ _58
DDR3_M0_DQ _57
DDR3_M0_DQ _56

DDR3_M0_DQ _55
DDR3_M0_DQ _54
DDR3_M0_DQ _53
DDR3_M0_DQ _52
DDR3_M0_DQ _51
DDR3_M0_DQ _50
DDR3_M0_DQ _49
DDR3_M0_DQ _48

DDR3_M0_DQ _47
DDR3_M0_DQ _46
DDR3_M0_DQ _45
DDR3_M0_DQ _44
DDR3_M0_DQ _43
DDR3_M0_DQ _42
DDR3_M0_DQ _41
DDR3_M0_DQ _40

DDR3_M0_DQ _39
DDR3_M0_DQ _38
DDR3_M0_DQ _37
DDR3_M0_DQ _36
DDR3_M0_DQ _35
DDR3_M0_DQ _34
DDR3_M0_DQ _33
DDR3_M0_DQ _32

DDR3_M0_DQ _31
DDR3_M0_DQ _30
DDR3_M0_DQ _29
DDR3_M0_DQ _28
DDR3_M0_DQ _27
DDR3_M0_DQ _26
DDR3_M0_DQ _25
DDR3_M0_DQ _24

DDR3_M0_DQ _23
DDR3_M0_DQ _22
DDR3_M0_DQ _21
DDR3_M0_DQ _20
DDR3_M0_DQ _19
DDR3_M0_DQ _18
DDR3_M0_DQ _17
DDR3_M0_DQ _16

DDR3_M0_DQ _15
DDR3_M0_DQ _14
DDR3_M0_DQ _13
DDR3_M0_DQ _12
DDR3_M0_DQ _11
DDR3_M0_DQ _10

DDR3_M0_DQ _9
DDR3_M0_DQ _8

DDR3_M0_DQ _7
DDR3_M0_DQ _6
DDR3_M0_DQ _5
DDR3_M0_DQ _4
DDR3_M0_DQ _3
DDR3_M0_DQ _2
DDR3_M0_DQ _1
DDR3_M0_DQ _0

DDRA_DRAMRST#_R

3

DDRB_DQ[63:0] 15

DDRB_MA[15:0] 15

DDRB_DQS[7:0] 15

DDRB_DQS#[7:0] 15

DDRB_DM[7:0] 15

DDRA_DQ55

BG33

DDRA_DQ54

BH28

DDRA_DQ53

BJ29

DDRA_DQ52

BG28

DDRA_DQ51

BG32

DDRA_DQ50

BH34

DDRA_DQ49

BG29

DDRA_DQ48

BJ33

DDRA_DQ63

BD28

DDRA_DQ62

BF30

DDRA_DQ61

BA34

DDRA_DQ60

BD34

DDRA_DQ59

BD30

DDRA_DQ58

BA32

DDRA_DQ57

BC34

DDRA_DQ56

BF34

DDRA_DQ47

AV32

DDRA_DQ46

AV34

DDRA_DQ45

BD36

DDRA_DQ44

BF36

DDRA_DQ43

AU32

DDRA_DQ42

AU34

DDRA_DQ41

BA36

DDRA_DQ40

BC36

DDRA_DQ39

BH38

DDRA_DQ38

BH36

DDRA_DQ37

BJ41

DDRA_DQ36

BH42

DDRA_DQ35

BJ37

DDRA_DQ34

BG37

DDRA_DQ33

BG43

DDRA_DQ32

BG42

DDRA_DQ31

BB51

DDRA_DQ30

AW53

DDRA_DQ29

BC52

DDRA_DQ28

AW51

DDRA_DQ27

AV51

DDRA_DQ26

BC53

DDRA_DQ25

AV52

DDRA_DQ24

BD52

DDRA_DQ15

AV42

DDRA_DQ14

AP41

DDRA_DQ13

AV41

DDRA_DQ12

AT44

DDRA_DQ11

AP40

DDRA_DQ10

AT38

DDRA_DQ9

AP42

DDRA_DQ8

AT40

DDRA_DQ23

AV45

DDRA_DQ22

AY50

DDRA_DQ21

AT50

DDRA_DQ20

AP47

DDRA_DQ19

AV50

DDRA_DQ18

AY48

DDRA_DQ17

AT47

DDRA_DQ16

AP48

DDRA_DQ7

AP51

DDRA_DQ6

AR53

DDRA_DQ5

AK52

DDRA_DQ4

AL53

DDRA_DQ3

AR51

DDRA_DQ2

AT52

DDRA_DQ1

AL51

DDRA_DQ0

AK51

?

Group 6

Group 7

Group 5

Group 4

Group 3

Group 1

Group 2

Group 0

Del CS_2(chip select: 1 per Rank)
Del CKE_2(chip select: 1 per Rank)

DDR_CORE_PWROK55

12

RC35
182_0402_1%

INTEL PDG 182 ohm

For dual rank

DDRB_BS2#15
DDRB_BS1#15
DDRB_BS0#15

DDRB_CAS#15
DDRB_RAS#15
DDRB_WE#15

DDRB_CS0#15

DDRB_CLK015

DDRB_CLK0#15

DDRB_CKE015

DDRB_ODT015

M1_RCOMPPD

DDRB_DRAMRST#15

DDRB_DRAMRST#_R
DDR_CORE_PWROK

DDRB_MA15
DDRB_MA14
DDRB_MA13
DDRB_MA12
DDRB_MA11
DDRB_MA10
DDRB_MA9
DDRB_MA8
DDRB_MA7
DDRB_MA6
DDRB_MA5
DDRB_MA4
DDRB_MA3
DDRB_MA2
DDRB_MA1
DDRB_MA0

DDRB_DM7
DDRB_DM6
DDRB_DM5
DDRB_DM4
DDRB_DM3
DDRB_DM2
DDRB_DM1
DDRB_DM0

DDRB_DQS7
DDRB_DQS#7
DDRB_DQS6
DDRB_DQS#6
DDRB_DQS5
DDRB_DQS#5
DDRB_DQS4
DDRB_DQS#4
DDRB_DQS3
DDRB_DQS#3
DDRB_DQS2
DDRB_DQS#2
DDRB_DQS1
DDRB_DQS#1
DDRB_DQS0
DDRB_DQS#0

2

BD5

DDR3_M1_MA _15

BD7

DDR3_M1_MA _14

BF10

DDR3_M1_MA _13

BF6

DDR3_M1_MA _12

BB5

DDR3_M1_MA _11

BJ9

DDR3_M1_MA _10

BE2

DDR3_M1_MA _9

BD10

DDR3_M1_MA _8

BE8

DDR3_M1_MA _7

BB8

DDR3_M1_MA _6

BH6

DDR3_M1_MA _5

BD12

DDR3_M1_MA _4

BH7

DDR3_M1_MA _3

BJ6

DDR3_M1_MA _2

BC12

DDR3_M1_MA _1

BB7

DDR3_M1_MA _0

BF2

DDR3_M1_B S_2

AY14

DDR3_M1_B S_1

BH8

DDR3_M1_B S_0

BG9

DDR3_M1_CA S_N

BA14

DDR3_M1_RA S_N

BH10

DDR3_M1_W E_N

AU16

DDR3_M1_CS B_1

AY16

DDR3_M1_CS B_0

BD16

DDR3_M1_CK _1

BF16

DDR3_M1_CK B_1

AY12

DDR3_M1_CK E_1

BD14

DDR3_M1_CK _0

BF14

DDR3_M1_CK B_0

BB10

DDR3_M1_CK E_0

AT24

RSVD_AT24

AU24

RSVD_AU2 4

AV18

DDR3_M1_O DT_0

BA16

DDR3_M1_O DT_1

AT26

DDR3_M1_O CAVREF

AU26

DDR3_M1_O DQVREF

BA12

DDR3_M1_DR AMRST_N

AV26

DDR3_VCCA_ PWROK

BA26

DDR3_M1_RC OMPPD

BH24

DDR3_M1_DM _7

BD22

DDR3_M1_DM _6

AY18

DDR3_M1_DM _5

BG13

DDR3_M1_DM _4

BA1

DDR3_M1_DM _3

AP10

DDR3_M1_DM _2

AT6

DDR3_M1_DM _1

AP2

DDR3_M1_DM _0

BH22

DDR3_M1_DQ S_7

BG23

DDR3_M1_DQ SB_7

BC24

DDR3_M1_DQ S_6

BC22

DDR3_M1_DQ SB_6

AT22

DDR3_M1_DQ S_5

AT20

DDR3_M1_DQ SB_5

BH14

DDR3_M1_DQ S_4

BG15

DDR3_M1_DQ SB_4

AY2

DDR3_M1_DQ S_3

BA3

DDR3_M1_DQ SB_3

AT12

DDR3_M1_DQ S_2

AT13

DDR3_M1_DQ SB_2

AV7

DDR3_M1_DQ S_1

AV6

DDR3_M1_DQ SB_1

AM2

DDR3_M1_DQ S_0

AM3

DDR3_M1_DQ SB_0

BRASWELL_FCBGA151170

REV = 1.2
@

1

2

UC1B

RC9292

CC144

0.1u_0201_10V6K

@

?

CHV_MCP_EDS

DDR1

2 OF 13

1 2

0_0402_5%

DDR3_M0_DQ_63

DDR3_M1_DQ _63
DDR3_M1_DQ _62
DDR3_M1_DQ _61
DDR3_M1_DQ _60
DDR3_M1_DQ _59
DDR3_M1_DQ _58
DDR3_M1_DQ _57
DDR3_M1_DQ _56

DDR3_M1_DQ _55
DDR3_M1_DQ _54
DDR3_M1_DQ _53
DDR3_M1_DQ _52
DDR3_M1_DQ _51
DDR3_M1_DQ _50
DDR3_M1_DQ _49
DDR3_M1_DQ _48

DDR3_M1_DQ _47
DDR3_M1_DQ _46
DDR3_M1_DQ _45
DDR3_M1_DQ _44
DDR3_M1_DQ _43
DDR3_M1_DQ _42
DDR3_M1_DQ _41
DDR3_M1_DQ _40

DDR3_M1_DQ _39
DDR3_M1_DQ _38
DDR3_M1_DQ _37
DDR3_M1_DQ _36
DDR3_M1_DQ _35
DDR3_M1_DQ _34
DDR3_M1_DQ _33
DDR3_M1_DQ _32

DDR3_M1_DQ _31
DDR3_M1_DQ _30
DDR3_M1_DQ _29
DDR3_M1_DQ _28
DDR3_M1_DQ _27
DDR3_M1_DQ _26
DDR3_M1_DQ _25
DDR3_M1_DQ _24

DDR3_M1_DQ _23
DDR3_M1_DQ _22
DDR3_M1_DQ _21
DDR3_M1_DQ _20
DDR3_M1_DQ _19
DDR3_M1_DQ _18
DDR3_M1_DQ _17
DDR3_M1_DQ _16

DDR3_M1_DQ _15
DDR3_M1_DQ _14
DDR3_M1_DQ _13
DDR3_M1_DQ _12
DDR3_M1_DQ _11
DDR3_M1_DQ _10

DDR3_M1_DQ _9
DDR3_M1_DQ _8

DDR3_M1_DQ _7
DDR3_M1_DQ _6
DDR3_M1_DQ _5
DDR3_M1_DQ _4
DDR3_M1_DQ _3
DDR3_M1_DQ _2
DDR3_M1_DQ _1
DDR3_M1_DQ _0

DDRB_DRAMRST#_R

1

DDRB_DQ63

BG21

DDRB_DQ62

BH26

DDRB_DQ61

BJ25

DDRB_DQ60

BG26

DDRB_DQ59

BG22

DDRB_DQ58

BH20

DDRB_DQ57

BG25

DDRB_DQ56

BJ21

DDRB_DQ55

BD26

DDRB_DQ54

BF24

DDRB_DQ53

BA20

DDRB_DQ52

BD20

DDRB_DQ51

BD24

DDRB_DQ50

BA22

DDRB_DQ49

BC20

DDRB_DQ48

BF20

DDRB_DQ47

AV22

DDRB_DQ46

AV20

DDRB_DQ45

BD18

DDRB_DQ44

BF18

DDRB_DQ43

AU22

DDRB_DQ42

AU20

DDRB_DQ41

BA18

DDRB_DQ40

BC18

DDRB_DQ39

BH16

DDRB_DQ38

BH18

DDRB_DQ37

BJ13

DDRB_DQ36

BH12

DDRB_DQ35

BJ17

DDRB_DQ34

BG17

DDRB_DQ33

BG11

DDRB_DQ32

BG12

DDRB_DQ31

BB3

DDRB_DQ30

AW1

DDRB_DQ29

BC2

DDRB_DQ28

AW3

DDRB_DQ27

AV3

DDRB_DQ26

BC1

DDRB_DQ25

AV2

DDRB_DQ24

BD2

DDRB_DQ23

AV12

DDRB_DQ22

AP13

DDRB_DQ21

AV13

DDRB_DQ20

AT10

DDRB_DQ19

AP14

DDRB_DQ18

AT16

DDRB_DQ17

AP12

DDRB_DQ16

AT14

DDRB_DQ15

AV9

DDRB_DQ14

AY4

DDRB_DQ13

AT4

DDRB_DQ12

AP7

DDRB_DQ11

AV4

DDRB_DQ10

AY6

DDRB_DQ9

AT7

DDRB_DQ8

AP6

DDRB_DQ7

AP3

DDRB_DQ6

AR1

DDRB_DQ5

AK2

DDRB_DQ4

AL1

DDRB_DQ3

AR3

DDRB_DQ2

AT2

DDRB_DQ1

AL3

DDRB_DQ0

AK3

?

+3VALW +1.35V

12

RC9296
10K_0402_5%

@

34

D

5

QC5B

G

2N7002KDWH_SOT363-6

@

S

61

D

2

VDDQ_PGOOD55

A A

1

2

@

5

G

CC3

0.1u_0201_10V6K

QC5A
2N7002KDWH_SOT363-6

@

S

RC9298

1 2

0_0402_5%

12

RC9297
10K_0402_5%

1

CC1

0.1u_0201_10V6K

2

@

4

DDR_PWROK

12

RC9293
10K_0402_5%

@

34

D

5

G

QC10B
2N7002KDWH_SOT363-6

S

61

D

SYS_PWROK7,44

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

1

CC19

0.1u_0201_10V6K

2

CD@

Issued Date

Issued Date

Issued Date

2

G

QC10A
2N7002KDWH_SOT363-6

S

@

2015/10/08

2015/10/08

2015/10/08

3

@

LC Future Center Sec ret Data

LC Future Center Sec ret Data

LC Future Center Sec ret Data

Deciphered Date

Deciphered Date

Deciphered Date

+1.35V+3VALW

12

RC9294
10K_0402_5%

DDR_CORE_PWROK

1

CC18

0.1u_0201_10V6K

2

2

2015/03/23

2015/03/23

2015/03/23

Title

Title

Title

SOC(DDR3L)

SOC(DDR3L)

SOC(DDR3L)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

CGx20

CGx20

CGx20

Friday, December 11, 2015

Friday, December 11, 2015

Friday, December 11, 2015

of

5 57

of

5 57

of

5 57

1

0.1

0.1

0.1

5

www.laptoprepairsecrets.com

D D

CC103 0.1u_0201_10V6K

PCIE_PTX_C_DRX_P440

WLAN

LAN

C C

PCIE_PTX_C_DRX_N440

PCIE_PRX_DTX_P440
PCIE_PRX_DTX_N440

PCIE_PTX_C_DRX_P337
PCIE_PTX_C_DRX_N337

PCIE_PRX_DTX_P337

PCIE_PRX_DTX_N337

1 2

CC104 0.1u_0201_10V6K

1 2

CC106 0.1u_0201_10V6K

1 2

0.1u_0201_10V6K

1 2

CC105

CLK_PCIE_WLAN40
CLK_PCIE_WLAN#40
CLK_PCIE_LAN37
CLK_PCIE_LAN#37

PCIE_PTX_DRX_P4
PCIE_PTX_DRX_N4
PCIE_PRX_DTX_P4
PCIE_PRX_DTX_N4

PCIE_PTX_DRX_P3
PCIE_PTX_DRX_N3
PCIE_PRX_DTX_P3
PCIE_PRX_DTX_N3

GPU_CLKREQ#_Q
PCIE_CLKREQ_2#
WLAN_CLKREQ#_Q
LAN_CLKREQ#_Q

CLK_PCIE_WLAN
CLK_PCIE_WLAN#
CLK_PCIE_LAN
CLK_PCIE_LAN#

PCIE_RCOMP_DP
PCIE_RCOMP_DN

4

UC1D

C24

PCIE_TXP0

B24

PCIE_TXN0

G20

PCIE_RXP0

J20

PCIE_RXN0

A25

PCIE_TXP1

C25

PCIE_TXN1

D20

PCIE_RXP1

F20

PCIE_RXN1

B26

PCIE_TXP2

C26

PCIE_TXN2

D22

PCIE_RXP2

F22

PCIE_RXN2

A27

PCIE_TXP3

C27

PCIE_TXN3

G24

PCIE_RXP3

J24

PCIE_RXN3

AM10

PCIE_CLKREQ0_N

AM12

PCIE_CLKREQ1_N

AK14

PCIE_CLKREQ2_N

AM14

PCIE_CLKREQ3_N

A21

CLK_DIFF_P_0

C21

CLK_DIFF_N_0

C19

CLK_DIFF_P_1

B20

CLK_DIFF_N_1

C18

CLK_DIFF_P_2

B18

CLK_DIFF_N_2

C17

CLK_DIFF_P_3

A17

CLK_DIFF_N_3

C16

RSVD_C16

B16

RSVD_B16

D26

PCIE_RCOMP_P

F26

PCIE_RCOMP_N

V14

SPI1_CLK

Y13

SPI1_CS0_N

Y12

SPI1_CS1_N

V13

SPI1_MISO

V12

SPI1_MOSI

BRASWELL_FCBGA151170

@

V1P0
V1P0
V1P0
V1P0

V1P0
V1P0
V1P0
V1P0

V1P0
V1P0
V1P0
V1P0

V1P0
V1P0
V1P0
V1P0

V1P8
V1P8
V1P8
V1P8
V1P8

PCIe

SPI

CHV_MCP_EDS

V1P8
V1P8
V1P8
V1P8

?

DDR3_M0_DQ_63

V1P8
V1P8
V1P8
V1P8
V1P8
V1P8
V1P8
V1P8

SATA

V1P8
V1P8
V1P8
V1P8

SATA_GP2/SATA_DEVSLP0

V1P8

SATA_GP3/SATA_DEVSLP1

SATA_RCOMP_P
SATA_RCOMP_N

V1P8

V1P8

FST_SPI_CS0_N

V1P8

FST_SPI_CS1_N

V1P8

FST_SPI_CS2_N

V1P8
V1P8

FAST SPI

V1P8
V1P8

V1P5

MF_HDA_RST_N

V1P5
V1P5
V1P5
V1P5
V1P5

V1P5

MF_HDA_DOCKEN_N

V1P5

MF_HDA_DOCKRST_N

AUDIO

GP_SSP_2_CLK

GP_SSP_2_TXD
GP_SSP_2_RXD

REV = 1.2

SATA_TXP0
SATA_TXN0
SATA_RXP0
SATA_RXN0
SATA_TXP1
SATA_TXN1
SATA_RXP1
SATA_RXN1

SATA_LED_N

SATA_GP0
SATA_GP1

FST_SPI_CLK

FST_SPI_D0
FST_SPI_D1
FST_SPI_D2
FST_SPI_D3

MF_HDA_SDI1
MF_HDA_CLK
MF_HDA_SDI0

MF_HDA_SYNC

MF_HDA_SDO

V1P8

SPKR

GP_SSP_2_FS

4 OF 13

3

SATA_PTX_DRX_P0

C31

SATA_PTX_DRX_N0

B30

SATA_PRX_DTX_P0

N28

SATA_PRX_DTX_N0

M28

SATA_PTX_DRX_P1

C29

SATA_PTX_DRX_N1

A29

SATA_PRX_DTX_P1

J28

SATA_PRX_DTX_N1

K28

AH3
AH2
AG3
AG1
AF3

SATA_RCOMP_DP

N30

SATA_RCOMP_DN

M30

PCH_SPI_CLK_R

W3

PCH_SPI_CS0#_R

V4
V6
V7

PCH_SPI_D0_R

V2

PCH_SPI_D1_R

V3

PCH_SPI_D2_R

U1

PCH_SPI_D3_R

U3

HDA_RST_AUDIO#_R

AF13
AD6

HDA_BITCLK_AUDIO_R

AD9
AD7

HDA_SYNC_AUDIO_R

AF12

HDA_SDOUT_AUDIO_R

AF14
AB9
AB7

H4

AK9
AK10
AK12
AK13

RC39

1 2

75_0402_1%

RC40

1 2

75_0402_1%

1 2

RC42 75_0402_1%

1 2

RC43 75_0402_1%

SATA_PTX_DRX_P0 42
SATA_PTX_DRX_N0 42
SATA_PRX_DTX_P0 42
SATA_PRX_DTX_N0 42
SATA_PTX_DRX_P1 42
SATA_PTX_DRX_N1 42
SATA_PRX_DTX_P1 42
SATA_PRX_DTX_N1 42

12

RC13410_0402_1%

12

RC13533_0402_5%

12

RC13010_0402_1%

12

RC13110_0402_1%

12

RC13210_0402_1%

12

RC13310_0402_1%

HDA_RST_AUDIO# 43

HDA_BITCLK_AUDIO 43

HDA_SDIN0 43
HDA_SYNC_AUDIO 43
HDA_SDOUT_AUDIO 43

PCH_BEEP 43

HDD

ODD

EC_SPI_CLK 44

EC_SPI_CS0# 44

EC_SPI_D0 44
EC_SPI_D1 44
EC_SPI_D2 44
EC_SPI_D3 44

2

+1.8VALW

RPC1

WLAN_CLKREQ#_Q

45

PCIE_CLKREQ_2#

36

GPU_CLKREQ#_Q

27

LAN_CLKREQ#_Q

18

10K_0804_8P4R_5%

LAN_CLKREQ#_Q

2N7002KDWH_SOT363-6

LAN_CLKREQ#_Q LAN_CLKR EQ#

D

QC22B

2N7002KDWH_SOT363-6

RC19 0_0402_5%

@

34

S

QC22A

1 2

5

G

+3VS

RC11
10K_0402_5%

1 2

61

D

S

1

@

@

2

G

LAN_CLKREQ# 37

LAN_CLKREQ# is OD,Can pull high to 1.8V

+3VS

RC3
10K_0402_5%

QC8A

1 2

5

G

61

D

2

G

S

WLAN_CLKREQ# 40

WLAN_CLKREQ#_Q

2N7002KDWH_SOT363-6

QC8B

2N7002KDWH_SOT363-6

34

D

S

+1.8VALW

PCH_SPI_CS0#

PCH_SPI_D1

PCH_SPI_D2

PCIE_RCOMP_DP

PCIE_RCOMP_DN

@

1 2

RC84

0_0402_5%

UC2

1

CS#

2

DO

3

WP#

4

GND

W25Q64FVSSIQ_SO8

0605

PCH_SPI_CS0#
PCH_SPI_CLK
PCH_SPI_D0
PCH_SPI_D1
PCH_SPI_D2
PCH_SPI_D3

1 2

PCH_SPI_CS0#_R

VCC

HOLD#

CLK

DI

RC38
402_0402_1%

8

PCH_SPI_D3

7

PCH_SPI_CLK

6

PCH_SPI_D0

5

50mA

PCH_SPI_CS0# 44
PCH_SPI_CLK 44
PCH_SPI_D0 44
PCH_SPI_D1 44
PCH_SPI_D2 44
PCH_SPI_D3 44

4

+VCC_SPI

2

1

CC8

0.1u_0201_10V6K

Security Cl assification

Security Cl assification

Security Cl assification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

3

2015/10/08

2015/10/08

2015/10/08

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2015/03/23

2015/03/23

2015/03/23

Title

Title

Title

SOC (PCIE&HDA&SPI&SATA)

SOC (PCIE&HDA&SPI&SATA)

SOC (PCIE&HDA&SPI&SATA)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Tuesday, December 08, 2015

Tuesday, December 08, 2015

Tuesday, December 08, 2015

CGx20

CGx20

CGx20

of

6 57

of

6 57

of

6 57

1

0.1

0.1

0.1

SATA_RCOMP_DP

RC30
402_0402_1%

1 2

+VCC_SPI

PCH_SPI_CS0#

@

+3VALW

+VCC_SPI

SATA_RCOMP_DN

1 2

RC94

0_0402_5%

1 2

RC20

100K_0402_5%

B B

A A

SPI ROM

5

5

www.laptoprepairsecrets.com

32.768K need change to SJ10000IM00,

+1.8VALW +1.8VALW+3VALW

RC96
0_0402_5%

1 2

UC3

1

VCCA

VCCB

CC15

TPM@

SOC_SERIRQ

2

GND

EO

A43B4

1

G2129TL1U_SC70-6

TPM@

2

NTPM@

1 2

RC33

D D

SOC_SERIRQ

0.1u_0201_10V6K

0_0402_5%

0_0402_5%

RC98

RC97

10K_0402_5%

TPM@

1 2

1 2

6

5

4

1

CC16

0.1u_0201_10V6K

2

TPM@

SERIRQ

as in tel EDS New request

SERIRQ 32,44

CRYST AL

1,Space 15MIL
2,No trace under crystal
3,place on oppsosit side of MCP for temp influence

1 2

RC92 10M_0402_5%

RTC_X1

1 2

32.768KHZ_9PF_X1A000141000200

2

CC11
7P_0402_50V8-B

1

YC1

SERIRQ level shift need IC, no t MOS for frequence

PCH_PCI_CLK_R

?

CHV_MCP_ED S

UC1G

XDP_TCLK

1

LPC_AD032,44
LPC_AD132,44
LPC_AD232,44
LPC_AD332,44

SOC_SERIRQ

TP13 @

1

TP14 @

1

TP15 @

1

TP16 @

1

TP17 @

1

TP18 @

1

TP19 @

1 2

RC80 0_0402_5%

1 2

RC81 0_0402_5%

TPM@

100_0402_1%

1 2

RC104

1

C4932

0.1U_0201_6.3V6-K

2

EMC_NS@

CLK_PCI_EC44

CLK_PCI_TPM32

LPC_FRAME#32,44

C C

+1.8VALW

RC48
20K_0402_5%

@

1 2

H_PROCHOT#44,55

+CPU_CORE +GFX_CORE

12

RC12 100_0402_1%

12

RC13 100_0402_1%

RTC_INTRUDER

RC65

1 2

10K_0402_5%

CPU_VCC_SENSE

CPU_VSS_SENSE

H_PROCHOT# PCH_SMB_CLK

AF42

XDP_TDI

AD47

XDP_TDO

AF40

XDP_TMS

AD48

XDP_TRST#

AB48

XDP_PRDY#

AD45

XDP_PREQ#

AF41

PCH_PCI_CLK_R

RCOMP_LPC_HVT

AF50
AF48
AF44
AF45
AD50

12

RC28 100_0402_1%

12

RC29 100_0402_1%

M13

P2
R3
T3
P3

M3
M2

N3
N1

T4
T2

H5
H7

P28
P30

@

TCK
TDI
TDO
TMS
TRST_N

CX_PRDY_N
CX_PREQ_N
RSVD_M13

MF_LPC_CLKOUT0
MF_LPC_CLKOUT1
LPC_CLKRUN_N
LPC_FRAME_N

MF_LPC_AD0
MF_LPC_AD1
MF_LPC_AD2
MF_LPC_AD3

LPC_HVT_RCOMP
ILB_SERIRQ

RSVD_H5
RSVD_H7

RSVD_P28
RSVD_P30
RSVD_AF50
RSVD_AF48
RSVD_AF44
RSVD_AF45
PROCHOT_N

V1P8
V1P8
V1P8
V1P8

BRASWELL_FCBGA151170

REV = 1.2

UNCORE_VSS_SENSE

JTAG/ITP

V1P8

V3P3
V3P3
V3P3
V3P3
V1P8

V3P3

LPC

V3P3
V3P3
V3P3

V1P8

Reserved

V1P8

VCC_AXG_SENSE

DDR3_M0_DQ_63

RTC_X1
RTC_X2

RTC_EXTPAD

RTC_RST_N

RTC

COREPWROK

V3P3

RSMRST_N

V3P3

RTC_TEST_N

RSVD_VSS_G18

SUSPWRDNACK

V1P8

SUS_STAT_N

V1P8

PMU_SUSCLK

V1P8

PMU_SLP_S4_N

V1P8

PMU_SLP_S3_N

V1P8

PMU_RESETBUTTON_N

PMU

PMU_PLTRST_N

V1P8

PMU_BATLOW_N

V1P8

PMU_AC_PRESENT

V1P8

PMU_SLP_S0IX_N

V1P8

PMU_SLP_LAN_N

V1P8

PMU_WAKE_N

V1P8

PMU_PWRBTN_N

V1P8

PMU_WAKE_LAN_N

V1P8

SVID0_CLK

V1P8

SVID0_DATA

V1P8

SVID

SVID0_ALERT_N

V1P8

CORE_VCC0_SENSE

CORE_VSS0_SENSE

CORE_VCC1_SENSE

CORE_VSS1_SENSE

DDI_VGG_SENSE

UNCORE_VSS_SENSE_2

Voltage sense

UNCORE_VSS_SENSE_1

7 OF 13

M18
K18
F16

D18
G16
F18
J16
G18

AE3
D14
C15
C12
B14
AF2
F14
C14
C13
A13
B12
N16
M16
P18

AD42
AD41
AD40

AG32
AJ32
AD29
AF27
AD24
AD22
AC27

?

RTC_X1
RTC_X2
BVCCRTC_EXTPAD

RTC_RST#
SYS_PWROK
EC_RSMRST#
SRTC_RST#
RTC_INTRUDER

PMC_SUSWARN#

PMC_SUSCLK
PM_SLP_S4#
PM_SLP_S3#
PMC_RSTBTN#
PMC_PLTRST#
PMC_BATLOW#
PMC_ACIN
PMC_SLP_S0IX#

PMU_SLP_LAN#
PMC_PCIE_WAKE#

PBTN_OUT#

PMC_LAN_WAKE#

VCC0_SENSE
VSS0_SENSE
VCC1_SENSE
VSS1_SENSE
VCC_AXG_SENSE
UNCORE_VSS_SENSE
VNN_SENSE

RTC_X2

2

1

CC17

1

TP5@

1 2

RC72 20K_0402_1%

1 2

RC9284

0_0402_5%

VCC0_SENSE
VSS0_SENSE

VCC1_SENSE
VSS1_SENSE

CPU_SVID_ALERT#

4

1,Spec. request 19.2MHz, Cp=12pf, RC=200K

XTAL19_IN

1 2

RC93 200K_0402_5%

YC2

1

2

EMC@

RPC5

1 4
2 3

RPC6

1 4
2 3

RC66

1 2

CC13
27P_0402_50V8J

CC140

1 2

0.1u_0201_10V6K

+1.8VALW

100_0404_4P2R_1%

100_0404_4P2R_1%

200_0402_1%

1

19.2MHZ_12PF_7V19200001

CPU_SVID_CLK 56,57
CPU_SVID_DAT 56,57

CPU_SVID_ALERT# 56,57

CC12
7P_0402_50V8-B

SYS_PWROK

0.1u_0201_10V6K

1 2

RTC_RST# 44
SYS_PWROK 5,44
EC_RSMRST# 44

PMC_PLTRST# 32,37,40,44

1

TP4@

1

TP20@

1

TP21@

CPU_SVID_CLK

CPU_SVID_DAT

CPU_SVID_ALERT#

VCC_AXG_SENSE 57
UNCORE_VSS_SENSE 57
VNN_SENSE 55

XTAL19_OUT

4

OSC1

NC2

3

NC12OSC2

CPU_VCC_SENSE
CPU_VSS_SENSE

+1.05VA_SOC_G3

change from 1.05VA for layout

1

CC14
27P_0402_50V8J

2

CPU_VCC_SENSE 56

CPU_VSS_SENSE 56

EC_SCI#12,44

2.49K_0402_1%

TP23 @

TP22 @

GPIO_SUS_012
GPIO_SUS_112
GPIO_SUS_212

TP24

GPIO_SUS_412
GPIO_SUS_512

GPIO_SUS_912
GPIO_SUS_812

TP25

RC108 100_0402_1%

3

SRTC_RST#

RTC_RST#

1 2

RC89 20K_0402_1%

1 2

RC90 20K_0402_1%

1U_0402_6.3V6K

1U_0402_6.3V6K

CC10

1

1

CC9

2

2

12

JCMOS1
SHORT PADS

@

JCMOS/JCMOS1

Place under Bottom

RTCRST#

Space 15Mil

VCCRTC

RTC RST#

?

XTAL19_IN
XTAL19_OUT

RC45

12
12

RC4449.9_0402_1%

1

XDP_GPIO_DFX8

1

1

@

EC_SMI#

1

@

KBRST#
GPIO_RCOMP18

12

UC1E

P24

OSCIN

M22

OSCOUT

J26

RSVD_J26

N26

ICLK_ICOMP

RSVD_N26

P20

ICLK_RCOMP

ICLKICOMP

N20

ICLKRCOMP

P26

RSVD_P26

K26

RSVD_K26

M26

RSVD_M26

AH45

RSVD_AH45

A9

MF_PLT_CLK0

C9

MF_PLT_CLK1

B8

MF_PLT_CLK2

B7

MF_PLT_CLK3

B5

MF_PLT_CLK4

B4

MF_PLT_CLK5

AM40

GPIO_DFX0

AM41

PCB_ID0

GPIO_DFX1

AM44

PCB_ID1

GPIO_DFX2

AM45

PCB_ID2

GPIO_DFX3

AM47

PCB_ID3

GPIO_DFX4

AK48

PCB_ID4

GPIO_DFX5

AM48

PCB_ID5 PCB_ID4

GPIO_DFX6

AK41

GPIO_DFX7

AK42

GPIO_DFX8

AD51

GPIO_SUS0

AD52

GPIO_SUS1

AH50

GPIO_SUS2

AH48

GPIO_SUS3

AH51

GPIO_SUS4

AH52

GPIO_SUS5

AG51

GPIO_SUS6

AG53

GPIO_SUS7

AF52

SEC_GPIO_SUS9

AF51

SEC_GPIO_SUS8

AE51

SEC_GPIO_SUS10

AC51

SEC_GPIO_SUS11

AH40

GPIO0_RCOMP

Y3

GPIO_ALERT

BRASWELL_FCBGA151170

REV = 1.2

@

CHV_MCP_ED S

DDR3_M0_DQ_63

RSVD_C11
RSVD_B10
RSVD_F12

RESERVED

Internal 20K(H)

SMBUS

V1P8
V1P8

V1P8
V1P8

V1P8
V1P8

I2C

V1P8
V1P8

V1P8
V1P8

V1P8
V1P8

V1P8
V1P8

V1P8
V1P8

V1P8
V1P8

MF_SMB_DATA

V1P8

MF_SMB_ALERT_N

RSVD_F10

RSVD_D12

RSVD_E8
RSVD_C7
RSVD_D6

RSVD_J12

RSVD_F7
RSVD_J14
RSVD_L13

I2C0_SCL

I2C0_SDA

I2C1_SCL

I2C1_SDA

I2C2_SCL

I2C2_SDA

I2C3_SCL

I2C3_SDA

I2C4_SCL

I2C4_SDA

I2C5_SCL

I2C5_SDA

I2C6_SCL

I2C6_SDA

RSVD_AA3

RSVD_Y2

MF_SMB_CLK

iCLK

V1P8
V1P8
V1P8
V1P8
V1P8

PLTFM CLK's

V1P8

GPIO_DFX

GPIO_SUS

5 OF 13

PCH_SMB_CLK_Q

C11
B10
F12
F10

D12
E8
C7

PCH_SMB_DATA_Q

D6

J12
F7
J14
L13

AK6
AH7

AF6
AH6

AF9
AF7

AE4
AD2

AC1
AD3

PCH_CMOS_ON#_Q

AB2
AC3

AA1
AB3

AA3
Y2

AM6

PCH_SMB_DATA

AM7

PCH_SMB_ALERT#

AM9

?

2

PCH_SMB_CLK

PCH_SMB_DATA

6 1

@

2N7002KDWH_SOT363-6

RPC22

2.2K_0404_4P2R_5%

1 4

2 3

QC20B
PJT138K_SOT363-6

@

3 4

@

2N7002KDWH_SOT363-6

2

G

QC6A

S

D

1 2

RC124 0_0402_5%

@

+1.8VALW

2

QC20A
PJT138K_SOT363-6

@

G2 5

D2 3S24

+3VS

5

G

QC6B

S

D

1 2

RC123 0_0402_5%

@

G1

D1 6S11

+3VALW+1.8VALW

1 4

2 3

@

RPC23

2.2K_0404_4P2R_5%

PCH_SMB_CLK_Q

PCH_SMB_DATA_Q

SMB_CLK_S3 40

SMB_DATA_S3 40

PCB_ID0
PCB_ID1
PCB_ID2
PCB_ID3

PCB_ID5

PCB ID

X X X X

0

X X X X

1

0

X

X

X

X

X

X

X

X

X

X

X

X

1

PMC_PLTRST#

10K_0402_5%

PCH_SMB_ALERT#

PMC_RSTBTN#

PMC_SUSWARN#

PMC_SUSCLK

EC_RSMRST#

EC_RSMRST#

@

PMC_SUSWARN#

SMB_CLK_S3
SMB_DATA_S3

+1.8VALW

@

15@

RC58

RC59

RC64

X X X

X X X1

0 0 1

0

1 00

RC948

1 2

1 2

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%

@

14@

RC62

RC950

1 2

1 2

2.2K_0402_5%

2.2K_0402_5%

PCB_ID3PCB_ID2PCB_ID1PCB_ID0 Description

PCB_ID4 PCB_ID5

Reserve

Reserve

Reserve

Reserve

Reserve

Reserve

00 1

Reserve

1 1

Reserve

0 11

Reserve

RC70

12

@

RC120

12

@

10K_0402_5%

1 2

RC73 10K_0402_5%

RC71

1 2

100K_0402_5%@

1 2

RC83 10K_0402_5%@

12

RC930 100K_0402_5%

CC132

0.01U_0201_25V6-K

1 2

RC75

1 2

100K_0402_5%

RPC29

14
23

@

2.2K_0404_4P2R_5%

@

@

RC949

1 2

1 2

2.2K_0402_5%

@

@

RC951

1 2

1 2

2.2K_0402_5%

14'' SKU

15'' SKU

single channel DRAM CHA@

dual chanel DRAM CHA@ and CHB@

Samsung 4G(K4B4G1646E-BYK0)

Hynix 4G(H5TC4G63CFR-PBA)

Micron 4G(MT41K256M16TW-107:P)

Hynix 8G(H5TC8G63CMR-PBA)

Micron 8G(MT41K512M16HA-125:A)

RC9286

RC9287

+1.8VALW

@

1 2

2.2K_0402_5%

@

1 2

2.2K_0402_5%

+3VS

@

RC9288

1 2

2.2K_0402_5%

@

RC9289

1 2

2.2K_0402_5%

B B

+3VS+3VALW

D2 3

S2

4

5

QC15B
PJT138K_SOT363-6

@

KBRST# 44

PBTN_OUT# 44

12

1 2

RC9300
10K_0402_5%

RC105
100K_0402_5%

PLT_RST# 32,37,40,44

PMC_PCIE_WAKE#

PM_SLP_S3#

PM_SLP_S4#

+1.8VALW

+1.8VALW

4

1 4

2 3

PJA138K_SOT23-3
QC168

D

S

3

G

2

+1.8VALW

1 4

2 3

+3VALW

RPC28
10K_0404_4P2R_5%

1

RPC2
10K_0404_4P2R_5%

@

PCIE_WAKE# 40,44

PM_SLP_S3# 44

PM_SLP_S4# 44

EC_SMI#

3

+1.8VALW

RC14
10K_0402_5%

1 2

EC_SMI# 44

PMC_SUSWARN#

12

@

RC22

2.2K_0402_5%

PCH_CMOS_ON#_Q

+1.8VALW

2

G

3

S

QC12
PJA138K_SOT23-3

1

D

@

12

RC9299
10K_0402_5%

@

G25

QC15A

1

C4937

0.1U_0201_6.3V6-K

2

@

KBRST#

PBTN_OUT#

D1 6S11

2

G1

PJT138K_SOT363-6

@

+1.8VALW

RPC4
10K_0404_4P2R_5%

1 4

2 3

PMC_PLTRST#

A A

@

+3VALW

RC23
10K_0402_5%

1 2

QC18

2

G

@

PJA138K_SOT23-3

+3VS

RC112
10K_0402_5%

@

1 2

CMOS_ON#

1

D

S

3

SUSWARN# 44

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2

2015/10/08

2015/10/08

2015/10/08

PMC_SUSCLK

PMC_ACIN

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

12

@

1 2

RC932

2.2K_0402_5%

RC63
10K_0402_5%

@

+1.8VALW

2

G

3

S

QC203
PJA138K_SOT23-3

+1.8VALW

1 2

13

D

S

@

@

1

D

@

RC61

2.2K_0402_5%

QC9

2

G

2N7002KW_SOT323-3

2015/03/23

2015/03/23

2015/03/23

+3VALW

RC933
10K_0402_5%

1 2

SUSCLK 40

2

G

3

1

D

S

QC207
PJA138K_SOT23-3

0605

Title

Title

Title

SOC (RTCI&PM&SM&GPIO)

SOC (RTCI&PM&SM&GPIO)

SOC (RTCI&PM&SM&GPIO)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Friday, December 11, 2015

Friday, December 11, 2015

Friday, December 11, 2015

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

AC_PRESENT 44

ACIN# 44

CGx20

CGx20

CGx20

7 57

7 57

7 57

0.1

0.1

0.1

5

www.laptoprepairsecrets.com

4

3

2

1

D D

USB30_TX_P041

LEFT USB (3.0)

C C

RC192

402_0402_1%

B B

1 2

USB3_RCOMP_DP

USB3_RCOMP_DN

USB30_TX_N041
USB30_RX_P041

USB30_RX_N041

USB3_RCOMP_DP
USB3_RCOMP_DN

USB30_TX_P0
USB30_TX_N0
USB30_RX_P0
USB30_RX_N0

UC1F

B32

USB3_TXP0

C32

USB3_TXN0

F28

USB3_RXP0

D28

USB3_RXN0

A33

USB3_TXP1

C33

USB3_TXN1

F30

USB3_RXP1

D30

USB3_RXN1

C34

USB3_TXP2

B34

USB3_TXN2

G32

USB3_RXP2

J32

USB3_RXN2

C35

USB3_TXP3

A35

USB3_TXN3

G34

USB3_RXP3

J34

USB3_RXN3

D34

USB3_RCOMP_P

F34

USB3_RCOMP_N

C37

RSVD_C37

A37

RSVD_A37

F36

RSVD_F36

D36

RSVD_D36

M34

RSVD_M34

M32

RSVD_M32

C38

RSVD_C38

B38

RSVD_B38

G36

RSVD_G36

J36

RSVD_J36

N34

RSVD_N34

P34

RSVD_P34

BRASWELL_FCBGA151170

REV = 1.2
@

V1P05A
V1P05A
V1P05A
V1P05A

V1P05A
V1P05A
V1P05A
V1P05A

V1P05A
V1P05A
V1P05A
V1P05A

V1P05A

USB3.0

V1P05A
V1P05A
V1P05A

V1P2
V1P2

V1P2

RESERVED

DDR3_M0_DQ_63

V1P8

USB_OTG_ID

V1P8

USB_DP0

V1P8

USB_DN0

V1P8

USB_DP1

V1P8

USB_DN1

V1P8

USB_DP2

V1P8

USB_DN2

V1P8

USB_DP3

V1P8

USB_DN3

V1P8

USB_DP4

V1P8

USB_DN4

V1P8

USB_OC1_N

USB2.0

V1P8

USB_OC0_N

RSVD_B46

USB_VBUSSNS

USB_RCOMP

USB_HSIC_0_STROBE

USB_HSIC_0_DATA

USB_HSIC_1_STROBE

V1P2

HSICUART

USB_HSIC_1_DATA

V1P2

USB_HSIC_RCOMP

V1P8

UART1_TXD

V1P8

UART1_RXD

V1P8

UART1_CTS_B

V1P8

UART1_RTS_B

V1P8

UART2_TXD

V1P8

UART2_RXD

V1P8

UART2_CTS_N

V1P8

UART2_RTS_N

6 OF 13

B48
C42
B42

C43
B44

C41
A41

C45
A45

B40
C40

P16
P14

B46

USB_VBUSSNS

B47

USB_RCOMP

A48

M36
N36

K38
M38

USB_HSIC_RCOMP

N38

AD10
AD12
AD13
AD14

Y6
Y7
V9
V10

?

USB20_P0
USB20_N0

USB20_P1
USB20_N1

USB20_P2
USB20_N2

USB20_P3
USB20_N3

USB20_P4
USB20_N4

USB_OC1#
USB_OC0#

1 2

RC16 0_0402_5%

1 2

RC193 113_0402_1%

PDG 112.5 ohm
Demo 113 ohm
SD00001KH00

1 2

RC9301 45.3_0402_1%@

UART0_TXD
UART0_RXD

only for Win7 debug port

UART0_TXD

UART0_RXD

USB20_P0 41
USB20_N0 41

USB20_P1 41
USB20_N1 41

USB20_P2 30
USB20_N2 30

USB20_P3 40
USB20_N3 40

USB20_P4 33
USB20_N4 33

USB_OC1# 41

LEFT USB (3.0)

LEFT USB (2.0)

Card reader (2.0)

BT

Camera

+1.8VALW

RPC31

2.2K_0404_4P2R_5%

@

1 4

2 3

2

QC11A
PJT138K_SOT363-6

4

S2

QC11B
PJT138K_SOT363-6

G1

D1 6S11

@

+1.8VALW

G2 5

D2 3

USB_OC1#
USB_OC0#

+3VALW

RPC32

2.2K_0404_4P2R_5%

@

1 4

2 3

@

RPC18

2 3
1 4

10K_0404_4P2R_5%

only for Win7 debug port

?

CHV_MCP_EDS

+1.8VALW

UART_TX_DEBUG 40

UART_RX_DEBUG 40

A A

Title

Title

Security Cl assification

Security Cl assification

Security Cl assification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

2015/10/08

2015/10/08

2015/10/08

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2015/03/23

2015/03/23

2015/03/23

Title

SOC (USB)

SOC (USB)

SOC (USB)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Tuesday, December 08, 2015

Tuesday, December 08, 2015

Tuesday, December 08, 2015

CGx20

CGx20

CGx20

of

8 57

of

8 57

of

1

8 57

0.1

0.1

0.1

5

www.laptoprepairsecrets.com

D D

+1.15VA_DDI_G3

C C

4

+CPU_CORE

+1.15VA_SOC_G3

+1.15VA_FUSE_G3

+GFX_CORE

7.7A EDS

UC1H

AF36

CORE_VCC1_3

AG33

CORE_VCC1_7

AG35

CORE_VCC1_8

AG36

CORE_VCC1_9

AG38

CORE_VCC1_10

AJ33

CORE_VCC1_14

AJ36

CORE_VCC1_15

AJ38

CORE_VCC1_16

AF30

CORE_VCC1_2

AG27

CORE_VCC1_4

AG29

CORE_VCC1_5

AG30

CORE_VCC1_6

AJ27

CORE_VCC1_11

AJ29

CORE_VCC1_12

AJ30

CORE_VCC1_13

AF29

CORE_VCC1_1

AD16

DDI_VGG_1

AD18

DDI_VGG_2

AD19

DDI_VGG_3

AF16

DDI_VGG_4

AF18

DDI_VGG_5

AF19

DDI_VGG_6

AF21

DDI_VGG_7

AF22

DDI_VGG_8

AJ19

DDI_VGG_15

AG16

DDI_VGG_9

AG18

DDI_VGG_10

AG19

DDI_VGG_11

AG21

DDI_VGG_12

AG22

DDI_VGG_13

AG24

DDI_VGG_14

AJ21

DDI_VGG_16

AJ22

DDI_VGG_17

AJ24

DDI_VGG_18

AK24

DDI_VGG_19

AK30

CORE_V1P15_1

AK35

CORE_V1P15_2

AK36

CORE_V1P15_3

AM29

CORE_V1P15_4

AK33

FUSE_V1P15_2

AJ35

FUSE_V1P15_1

AM19

VCCSRAMGEN_1P152

AK21

VCCSRAMGEN_1P151

BRASWELL_FCBGA151170

@

?

CHV_MCP_EDS

DDR3_M0_DQ_63

UNCORE_VNN_S4_1
UNCORE_VNN_S4_2
UNCORE_VNN_S4_3
UNCORE_VNN_S4_4
UNCORE_VNN_S4_5
UNCORE_VNN_S4_6
UNCORE_VNN_S4_7
UNCORE_VNN_S4_8

UNCORE_VNN_S4_9
UNCORE_VNN_S4_10
UNCORE_VNN_S4_11
UNCORE_VNN_S4_12
UNCORE_VNN_S4_13
UNCORE_VNN_S4_14

VCCSRAMSOCIUN_1P056
VCCSRAMSOCIUN_1P051
VCCSRAMSOCIUN_1P052
VCCSRAMSOCIUN_1P053
VCCSRAMSOCIUN_1P054
VCCSRAMSOCIUN_1P055
VCCSRAMSOCIUN_1P057
VCCSRAMSOCIUN_1P058
VCCSRAMSOCIUN_1P059

VCCSRAMSOCIUN_1P0510

ICLK_GND_OFF_2
ICLK_GND_OFF_1

iCLK

DDR_V1P05A_G3_1
DDR_V1P05A_G3_4
DDR_V1P05A_G3_2
DDR_V1P05A_G3_5

DDRPCIeSATAUSBFUSE

DDR_V1P05A_G3_6
DDR_V1P05A_G3_3

PCIE_V1P05A_G3_1
PCIE_V1P05A_G3_2

SATA_V1P05A_G3_2

SATA_V1P05A_G3_1

USB3_V1P05A_G3_2

USB3_V1P05A_G3_1
USBSSIC_V1P05A_G3

FUSE3_V1P05A_G5

FUSE_V1P05A_G3

8 OF 13

REV = 1.2

3

RSVD_AA30

2

AA18
AA19
AA21
AA22
AA24
AA25
AC18
AC19
AC21
AC22
AC24
AC25
AD25
AD27

AA30
V33
AA32
AA33
AA35
AA36
AC32
Y30
Y32
Y33
Y35

V19
V18

AM21
AM33
AM22
AN22
AN32
AM32

V22
V24

U24
U22

V27
U27
V29

N18
U19

?

+VNN_1.05VA_S4

+1.05VA_SOC_G3

+1.05VA_ICLK_S4

+1.05VA_DDR_G3

+1.05VA_MPHY_G3

+1.05VA_SSIC_G3

1

+CPU_CORE

6.4 A

1

CC41
33P_0402_50V8J

RF_NS@

2

1

CC48
1U_0402_6.3V6K

2

CD@

1

CC54
1U_0402_6.3V6K

2

@

1

CC33

4.7U_0402_6.3V6M

2

CD@

1

CC39
22U_0603_6.3V6-M

2

@

1

CC34

4.7U_0402_6.3V6M

2

1

CC139
33P_0402_50V8J

RF_NS@

2

+GFX_CORE

1

CC141

22U_0603_6.3V6-M

2

CD@

Note:Place CAP Back of CPUNote:Place CAP Back of CPU

1

CC49
1U_0402_6.3V6K

2

1

2

10uF 0402 change to 4.7uF for cost down

1

2

@

+1.15VA_SOC +1.15VA_FUSE_G3

1

CC35

4.7U_0402_6.3V6M

2

CC44

22U_0603_6.3V6-M

CC50
1U_0402_6.3V6K

RC9279

1 2

4

1

2

1

2

@

0_0603_5%

CC51
1U_0402_6.3V6K

CC45

22U_0603_6.3V6-M

1

CC30

4.7U_0402_6.3V6M

2

1

CC31

4.7U_0402_6.3V6M

2

1

CC32

4.7U_0402_6.3V6M

2

Note:Place CAP Back of CPU Note:Place CAP Back of CPU

+CPU_CORE

1

CC36

22U_0603_6.3V6-M

2

CD@

B B

Note:Place Close of CPU's Edge

+GFX_CORE

1

CC37

22U_0603_6.3V6-M

2

CD@

1

CC38
22U_0603_6.3V6-M

2

@

11A

1

2

+1.15VA_SOC

A A

+1.15VA_SOC

CC40

22U_0603_6.3V6-M

RC9243

1 2

RC9244

1 2

1

CC138

4.7U_0402_6.3V6M

2

0_0603_5%

1

CC46
1U_0402_6.3V6K

2

CD@

0_0603_5%

1

2

Note:Place CAP Back of CPU

1

CC42

4.7U_0402_6.3V6M

2

+1.15VA_SOC_G3

1

CC47
1U_0402_6.3V6K

2

Note:Place CAP Back of CPU Note:Place Close of CPU's Edge

+1.15VA_DDI_G3

CC52
1U_0402_6.3V6K

1

CC53
1U_0402_6.3V6K

2

CD@

Note:Place Close of CPU's Edge

5

+1.05VA +VNN_1.05VA_S4

Need short

@

PJ1

1

CC145
33P_0402_50V8J

RF_NS@

2

2

JUMP_43X79

112

1

CC55
1U_0402_6.3V6K

2

3.5A

1

CC56
1U_0402_6.3V6K

2

1

CC57
1U_0402_6.3V6K

2

Note:Place CAP Back of CPU Note:Place Close of CPU's Edge

+1.05VA +1.05VA_SOC_G3

RC9238

1 2

0_0603_5%

1

CC63
1U_0402_6.3V6K

2

1

CC64
1U_0402_6.3V6K

2

1

CC65
1U_0402_6.3V6K

2

Note:Place CAP Back of CPU Note:Place Close of CPU's Edge

+1.05VA

RC9281

1 2

0_0603_5%

1

CC69
1U_0402_6.3V6K

2

+1.05VA_DDR_G3

1

CC70
1U_0402_6.3V6K

2

1

CC71
22U_0603_6.3V6-M

2

CD@

1

CC72
22U_0603_6.3V6-M

2

Note:Place CAP Back of CPU Note:Place Close of CPU's Edge

+1.05VA +1.05VA_SSIC_G3

RC9242

0_0603_5%

1 2

1

CC76
1U_0402_6.3V6K

2

1

CC77
1U_0402_6.3V6K

2

1

CC78
1U_0402_6.3V6K

2

@

@

Note:Place CAP Back of CPU Note:Place Close of CPU's Edge

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

3

2015/10/08

2015/10/08

2015/10/08

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

1

CC58
1U_0402_6.3V6K

2

CD@

1

CC66
1U_0402_6.3V6K

2

@

1

CC79
1U_0402_6.3V6K

2

2

CC67
1U_0402_6.3V6K

RC9240

1 2

1

CC60

22U_0603_6.3V6-M

2

CD@

0_0603_5%

CD@

1

CC59
1U_0402_6.3V6K

2

1

2

@

+1.05VA +1.05VA_MPHY_G3

1

CC61

22U_0603_6.3V6-M

2

+1.05VA +1.05VA_ICLK_S4

RC9241

1 2

1

CC73
1U_0402_6.3V6K

2

Note:Place CAP Back of CPU

1

CC80
1U_0402_6.3V6K

2

@

Title

Title

2015/03/23

2015/03/23

2015/03/23

Title

SOC (Power)

SOC (Power)

SOC (Power)

Size

Size

Size

Document Number Rev

Document Number Rev

Document Number Rev

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

2

@

0_0603_5%

1

CC68
1U_0402_6.3V6K

2

Note:Place CAP Back of CPU

1

CC74
1U_0402_6.3V6K

2

CGx20

CGx20

CGx20

Tuesday, December 08, 2015

Tuesday, December 08, 2015

Tuesday, December 08, 2015

CC62

22U_0603_6.3V6-M

1

CC75
1U_0402_6.3V6K

2

1

9 57

9 57

9 57

0.1

0.1

0.1

5

www.laptoprepairsecrets.com

+1.35V_DDRCLK +1.35V_DDR

+1.35V

2.4A EDS

D D

VCC_SD3_S3

VCC_LPC_G3

+1.8VS_HDA_S3

+1.8VALW_GPIO_E_G3

+1.8VALW_GPIO_G3

+1.35V

C C

1.9 A

1

CC81

2.2U_040 2_6.3V6 M

2

+1.35V

RC9246

1 2

Note:Place CAP Back of CPU

+1.8VALW

RC9283

1 2

0_0402_5%

B B

RC924

1 2

1

CC82

2.2U_040 2_6.3V6 M

2

+1.35V_D DR

0_0603_5%

1

CC89
1U_0402 _6.3V6K

2

Note:Place Close of CPU's Edge

VCC_SD3_S3

1

CC93
1U_0402 _6.3V6K

2

Note:Place CAP Back of CPU

+1.8VALW_GPIO_G3+1.8VALW

0_0603_5%

1

CC83

2.2U_040 2_6.3V6 M

2

1

@

2

1

CC97
1U_0402 _6.3V6K

2

1

CC90
22U_060 3_6.3V6 -M

2

@

CC94
1U_0402 _6.3V6K

@

1

CC84

330P_0 201_25 V7-K

2

EMC_NS@

+1.35V

1 2

Note:Place CAP Back of CPU

1 2

1 2

RC9278 0_0402_5%

+1.8VALW

1

CC98
1U_0402 _6.3V6K

2

1

CC85

22U_060 3_6.3V6 -M

2

Note:Place Close of CPU's EdgeNote:Place CAP Back of CPU

RC9247

RC928

@

0_0603_5%

VCC_LPC_G3+3VALW_SOC

0_0402_5%

1

2

@

1

2

CC86

22U_060 3_6.3V6 -M

+1.35V_D DRCLK

1

CC91
1U_0402 _6.3V6K

2

CC95
1U_0402 _6.3V6K

RC925

1 2

1

CC87

22U_060 3_6.3V6 -M

2

1

CC92
22U_060 3_6.3V6 -M

2

@

Note:Place Close of CPU's Edge

+1.8VALW_GPIO_E_G3+1.8VALW

0_0402_5%

1

2

CD@

UC1I

AN27

DDRSFR_VDDQ_G_S4

AM25

DDR_VDDQ_G_S4_2

BE1

DDR_VDDQ_G_S4_16

BE53

DDR_VDDQ_G_S4_19

BJ2

DDR_VDDQ_G_S4_26

BJ3

DDR_VDDQ_G_S4_27

BJ49

DDR_VDDQ_G_S4_28

BJ5

DDR_VDDQ_G_S4_29

BH50

DDR_VDDQ_G_S4_25

BH5

DDR_VDDQ_G_S4_24

BH49

DDR_VDDQ_G_S4_23

BH4

DDR_VDDQ_G_S4_22

BE3

DDR_VDDQ_G_S4_17

BG51

DDR_VDDQ_G_S4_21

BG3

DDR_VDDQ_G_S4_20

BJ51

DDR_VDDQ_G_S4_30

BJ52

DDR_VDDQ_G_S4_31

AY10

DDR_VDDQ_G_S4_14

AY44

DDR_VDDQ_G_S4_15

AV44

DDR_VDDQ_G_S4_13

AV10

DDR_VDDQ_G_S4_10

BE51

DDR_VDDQ_G_S4_18

AV38

DDR_VDDQ_G_S4_12

AV16

DDR_VDDQ_G_S4_11

AU36

DDR_VDDQ_G_S4_9

AU18

DDR_VDDQ_G_S4_8

AN36

DDR_VDDQ_G_S4_7

AN35

DDR_VDDQ_G_S4_6

AN19

DDR_VDDQ_G_S4_5

AN18

DDR_VDDQ_G_S4_4

AM36

DDR_VDDQ_G_S4_3

AM18

DDR_VDDQ_G_S4_1

E1

SDIO_V3P3A_V1P8A_G3_1

E2

SDIO_V3P3A_V1P8A_G3_2

G1

SDIO_V3P3A_V1P8A_G3_3

AH4

VCCCFIOAZA_1P802

AF4

VCCCFIOAZA_1P801

Y18

GPIO_V1P8A_G3_5

AD33

GPIO_V1P8A_G3_1

AK18

GPIO_V1P8A_G3_3

AF33

GPIO_V1P8A_G3_2

AK19

GPIO_V1P8A_G3_4

BRASWELL_FCBGA151170

@

1

CC88

22U_060 3_6.3V6 -M

2

@

+1.8VS_HDA_S3+1.8VS

RC905

1 2

0_0402_5%

1

CC96
1U_0402 _6.3V6K

2

Note:Place CAP Back of CPU

1

CC100

CC99

1U_0402 _6.3V6K

1U_0402 _6.3V6K

Note:Place CAP Back of CPU

@

2

1

CC101
1U_0402 _6.3V6K

2

?

CHV_MCP_EDS

DDR

9 OF 13

4

DDR3_M0 _DQ_63

DDI_VDDQ_G3_1
DDI_VDDQ_G3_2

MIPI_V1P2A_G3_2
MIPI_V1P2A_G3_1

ICLK_VSFR_G3_2
ICLK_VSFR_G3_1

CORE_VSFR_G3_5
CORE_VSFR_G3_6

CORE_VSFR_G3_AC30

CORE_VSFR_G3_4
CORE_VSFR_G3_2
CORE_VSFR_G3_3
CORE_VSFR_G3_1

USBHSIC_V1P2A_G3

USB_VDDQ_G3_2
USB_VDDQ_G3_3

USBRTCFUSE

USB_VDDQ_G3_1

USBSSIC_V1P2A_G3

USB_V3P3A_G3_2
USB_V3P3A_G3_1

RTC_V3P3RTC_G5_2
RTC_V3P3RTC_G5_1

RTC_V3P3A_G5_1
RTC_V3P3A_G5_2

FUSE_V1P8A_G3

FUSE1_V1P05A_G4
FUSE0_V1P05A_G3

REV = 1.2

USB_V1P8A_G3

RSVD_A3
RSVD_K20
RSVD_M20

?

3

+1.24VA_DP_G3

V36
Y36

+1.24VA_G3

T40
P40

Y27
Y25

P38
V30
AC30

AF35
AD35
AD38
AC36

M41
U35
V35
H44
P41

AA29

C23
B22

C5
B6
D4
E3

U16

H10
G10
A3
K20
M20

1 2

1 2

1 2

1 2

1 2

+1.24VA_SIO_G3

+1.24VA_PLL_G3

+1.24VA_CPUPLL_G3

+1.24VA_G3

+1.24VA_USB_G3 +1.24VA_G3

+1.24VA_USB2_G3

+1.8VALW_FUSE

+1.24VA_DP_G3+1.24VALW +1.24VA_SIO_G3+1.24VALW

RC9248

0_0603_5%

1

CC102
1U_0402 _6.3V6K

Note:Place CAP Back of CPU

2

+1.24VA_PLL_G3+1.24VALW

RC9250

0_0603_5%

1

CC136
1U_0402 _6.3V6K

2

Note:Place CAP Back of CPU

+1.24VA_USB_G3+1.24VALW

RC9253

0_0603_5%

1

CC110
1U_0402 _6.3V6K

2

+1.8VALW_USB+1.8VALW

RC9256

0_0603_5%

1

CC114
1U_0402 _6.3V6K

2

CD@

Note:Place CAP Back of CPU

+1.8VALW_FUSE+1.8VALW

RC9258

0_0402_5%

1

CC119
1U_0402 _6.3V6K

Note:Place CAP Back of CPU

2

+1.8VALW_USB

+3VALW_USB_G3

VCCRTC

+3VALW_RTC

+1.05VA_ FUSE_G 3

1

CC107
1U_0402 _6.3V6K

2

1

CC111
1U_0402 _6.3V6K

@

2

Note:Place CAP Back of CPU

1

CC115
1U_0402 _6.3V6K

2

RC898

1 2

+1.24VA_G3+1.24VALW

0_0603_5%

1

CC133
1U_0402 _6.3V6K

2

Note:Place CAP Back of CPU

RC9251

1 2

RC9254

1 2

RC9257

1 2

RC9259

1 2

0_0603_5%

0_0603_5%

@

+3VALW_USB_G3+3VALW _SOC

0_0603_5%

+1.05VA_FUSE_G3+1.05VA

0_0402_5%

+1.24VA_CPUPLL_G3+1.24VALW

+1.24VA_USB2_G3+1.24VALW

1

CC142
1U_0402 _6.3V6K

2

1

2

1

2

@

@

1

2

1

2

CC116
1U_0402 _6.3V6K

CC120
1U_0402 _6.3V6K

1

CC134
1U_0402 _6.3V6K

2

CC108
1U_0402 _6.3V6K

Note:Place CAP Back of CPU

CC112
1U_0402 _6.3V6K

Note:Place CAP Back of CPU

RC9249

0_0603_5%

1 2

CAD NOTE:FOR
PINS M41

CAD NOTE:FOR
PINS P41

VCCRTC +3VALW_SOC +3VALW_RTC

1

2

+1.24VA_G3

+1.24VA_G3

CC117

0.1u_020 1_10V6 K

1

CC135
1U_0402 _6.3V6K

Note:Place CAP Back of CPU

2

1

CC109
1U_0402 _6.3V6K

2

@

1

CC113
1U_0402 _6.3V6K

2

CD@

1 2

RC9282

0_0402_5%

@

1

CC118

0.1u_020 1_10V6 K

2

2

1

A A

Title

Title

Security Classif ication

Security Classif ication

Security Classif ication

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2

2015/10/08

2015/10/08

2015/10/08

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2015/03/23

2015/03/23

2015/03/23

Title

SOC (Power2)

SOC (Power2)

SOC (Power2)

Size

Size

Size

Document Number Rev

Document Number Rev

Document Number Rev

D

D

D

Date: Sheet of

Date: Sheet of

Date: Sheet of

Tuesday, December 08, 2015

Tuesday, December 08, 2015

Tuesday, December 08, 2015

1

CGx20

CGx20

CGx20

10 57

10 57

10 57

0.1

0.1

0.1

5

www.laptoprepairsecrets.com

4

3

2

1

Power-VSS

10 OF 13

VSS_55
VSS_54
VSS_53
VSS_51
VSS_50
VSS_49
VSS_48
VSS_47
VSS_46
VSS_45
VSS_44
VSS_43
VSS_42
VSS_41
VSS_40
VSS_39
VSS_38
VSS_37
VSS_36
VSS_35
VSS_33
VSS_26
VSS_32
VSS_31
VSS_30
VSS_29
VSS_28
VSS_27
VSS_25
VSS_24
VSS_23
VSS_22
VSS_21
VSS_20
VSS_19
VSS_18
VSS_17
VSS_16
VSS_15
VSS_14
VSS_13
VSS_12

VSS_8
VSS_7
VSS_6
VSS_5
VSS_4
VSS_3
VSS_2
VSS_1

?

?

DDR3_M0_DQ_63

AF38
AF32
AF25
AF10
AE9
AE8
AE6
AE53
AE50
AE48
AE46
AE45
AE43
AE42
AE40
AE14
AE12
AE11
AE1
AD44
AD36
AC29
AD32
AD30
AD21
AC38
AC35
AC33
AC16
AB6
AB50
AB47
AB42
AB4
AB14
AB13
AB12
AB10
AA53
AA38
AA27
AA16
A47
A43
A39
A31
A23
A19
A15
A11

BH53
BH52

BG53

BG47

BF50

BB50

CHV_MCP_EDS

UC1M

Power-VSS

F1

VSS_NCTF_F1

C1

VSS_NCTF_C1
VSS_NCTF_BH53
VSS_NVTF_BH52

BH2

VSS_NCTF_BH2

BH1

VSS_NCTF_BH1
VSS_NCTF_BG53

BG1

VSS_NCTF_BG1

B52

VSS_NCTF_B52

B2

VSS_NCTF_B2

A6

VSS_NCTF_A6

A5

VSS_NCTF_A5

M24

VSSA

A7

VSS_11
VSS_204

BF4

VSS_202
VSS_180

BB4

VSS_179

VSS_219

Y9

VSS_376

Y50

VSS_375

Y45

VSS_374

Y40

VSS_373

Y4

VSS_372

Y38

VSS_371

Y29

VSS_370

Y22

VSS_368

Y21

VSS_367

Y19

VSS_366

Y16

VSS_365

Y14

VSS_364

Y10

VSS_363

P4

VSS_324

L41

VSS_302

P36

VSS_323

BRASWELL_FCBGA151170

REV = 1.2

@

VSS_362
VSS_361
VSS_360
VSS_359
VSS_358

VSS_357
VSS_355
VSS_354
VSS_353
VSS_352
VSS_351
VSS_350
VSS_349
VSS_348
VSS_347
VSS_346
VSS_345
VSS_344
VSS_343
VSS_342
VSS_341

VSS_339
VSS_338
VSS_337
VSS_336

VSS_334
VSS_333
VSS_340
VSS_332
VSS_331
VSS_330
VSS_329
VSS_325
VSS_327
VSS_326

VSS_322

?

13 OF 13

DDR3_M0_DQ_63

W1
V44
V42
V41
V38

V32
V21
V16
U9
U8
U6
U53
U5
U49
U48
U46
U45
U43
U42
U40
U38

U33
U32
U30
U29

U21
U18
U36
U14
U12
U11
T9
P42
T14
R1

P35

?

CHV_MCP_EDS

UC1K

AN21

VSS_103

BG30

VSS_213

BG27

VSS_212

BG24

VSS_211

BG20

VSS_210

BG19

VSS_209

BG18

VSS_208

BG16

VSS_207

BG14

VSS_206

BF42

VSS_203

BF32

VSS_201

BF28

VSS_200

BF27

VSS_199

BF26

VSS_198

BF22

VSS_197

BF12

VSS_196

BE35

VSS_195

BE19

VSS_194

C20

VSS_240

BD53

VSS_193

BG7

VSS_223

BD35

VSS_192

BD27

VSS_191

BD19

VSS_190

BD1

VSS_189

BC44

VSS_188

BC40

VSS_187

BC38

VSS_186

BC28

VSS_185

BC26

VSS_184

BC16

VSS_183

BC14

VSS_182

BC10

VSS_181

BB35

VSS_178

BB27

VSS_177

BB19

VSS_176

BA35

VSS_175

BA30

VSS_174

BA27

VSS_173

BA24

VSS_172

BA19

VSS_171

B36

VSS_169

B28

VSS_168

AY7

VSS_165

AY51

VSS_164

AY47

VSS_163

AY34

VSS_161

AY32

VSS_160

AY30

VSS_159

AY3

VSS_158

AN30

VSS_108

AY45

VSS_162

BRASWELL_FCBGA151170

REV = 1.2

@

CHV_MCP_EDS

UC1J

AN3

VSS_107

AN29

VSS_106

AN25

VSS_105

AN24

VSS_104

AN16

VSS_102

AN14

VSS_101

AN12

VSS_100

AN11

VSS_99

AN1

VSS_98

D D

C C

Power-VSS

12 OF 13

VSS_369
VSS_272
VSS_271
VSS_270
VSS_269
VSS_268
VSS_267
VSS_266
VSS_265
VSS_264
VSS_263
VSS_262
VSS_261
VSS_259
VSS_257
VSS_256
VSS_255
VSS_254
VSS_253
VSS_252
VSS_251
VSS_250
VSS_249
VSS_248
VSS_284
VSS_247
VSS_246
VSS_245
VSS_244
VSS_243
VSS_242
VSS_241
VSS_152
VSS_238
VSS_237
VSS_236
VSS_235
VSS_234
VSS_233
VSS_232
VSS_231
VSS_230
VSS_229
VSS_228
VSS_221
VSS_220
VSS_218
VSS_217
VSS_216
VSS_215
VSS_214

?

?

DDR3_M0_DQ_63

Y24
G30
G28
G26
G22
G14
G12
F5
F35
F32
F27
F24
F19
E51
E35
E19
D42
D40
D38
D32
D27
D24
D16
D10
J42
C47
C39
C36
C30
C3
C28
C22
AW41
BJ7
BJ47
BJ43
BJ39
BJ35
BJ31
BJ27
BJ23
BJ19
BJ15
BJ11
BG5
BG49
BG40
BG38
BG36
BG35
BG34

CHV_MCP_EDS

UC1L

AN33

VSS_109

P32

VSS_321

P27

VSS_320

P22

VSS_319

P19

VSS_318

AF24

VSS_52

N53

VSS_316

N51

VSS_315

N32

VSS_314

N24

VSS_313

N22

VSS_312

M9

VSS_311

K45

VSS_296

M40

VSS_308

M35

VSS_307

M27

VSS_306

AW13

VSS_148

M19

VSS_304

M14

VSS_303

B B

A A

L35

VSS_301

L27

VSS_300

L19

VSS_299

L1

VSS_298

K50

VSS_297

T47

VSS_328

K4

VSS_295

K36

VSS_294

K34

VSS_293

K32

VSS_292

K30

VSS_291

K24

VSS_290

K22

VSS_289

K16

VSS_288

K14

VSS_287

K12

VSS_286

J53

VSS_285

M45

VSS_309

J38

VSS_283

J35

VSS_282

J30

VSS_281

J27

VSS_280

J22

VSS_279

J19

VSS_278

J18

VSS_277

H8

VSS_276

E46

VSS_258

H35

VSS_275

H27

VSS_274

H19

VSS_273

M50

VSS_310

V25

VSS_356

BRASWELL_FCBGA151170

REV = 1.2
@

AM50

VSS_97

AM42

VSS_96

AM4

VSS_95

AM38

VSS_94

AM35

VSS_93

AH44

VSS_64

AM30

VSS_92

AM27

VSS_91

U25

VSS_335

P10

VSS_317

AM16

VSS_89

AD4

VSS_34

AK7

VSS_87

AK50

VSS_86

AK47

VSS_85

AK45

VSS_84

AK44

VSS_83

AK40

VSS_82

AK4

VSS_81

AK38

VSS_80

AK32

VSS_79

AK27

VSS_77

AK25

VSS_76

AM24

VSS_90

AK16

VSS_74

AJ53

VSS_73

AJ51

VSS_72

AJ3

VSS_71

AJ25

VSS_70

AJ16

VSS_68

AJ1

VSS_67

AH9

VSS_66

AH47

VSS_65

AH42

VSS_63

AH41

VSS_62

AH14

VSS_61

AH13

VSS_60

AH12

VSS_59

AH10

VSS_58

AG25

VSS_57

AF47

VSS_56

BRASWELL_FCBGA151170

REV = 1.2

@

Power-VSS

11 OF 13

VSS_166
VSS_157
VSS_156
VSS_155
VSS_154
VSS_153
VSS_151
VSS_150
VSS_149

VSS_88
VSS_78

VSS_75
VSS_147
VSS_146
VSS_145
VSS_144
VSS_143
VSS_142
VSS_141

VSS_69
VSS_140
VSS_139
VSS_138
VSS_137
VSS_136
VSS_135
VSS_134
VSS_133
VSS_132
VSS_131
VSS_130
VSS_129
VSS_128
VSS_127
VSS_126
VSS_125
VSS_124
VSS_123
VSS_122
VSS_121
VSS_120
VSS_119
VSS_118
VSS_117
VSS_116
VSS_115
VSS_114
VSS_113
VSS_112
VSS_111
VSS_110

?

DDR3_M0_DQ_63

AY9
AY28
AY26
AY24
AY22
AY20
AW35
AW27
AW19
AM13
AK29
AK22
AV40
AV35
AV30
AV27
AV24
AV19
AV14
AJ18
AU53
AU51
AU3
AU1
AT9
AT51
AT45
AT36
AT35
AT3
AT27
AT19
AT18
AP9
AP50
AP45
AP4
AN9
AN8
AN6
AN53
AN51
AN5
AN49
AN48
AN46
AN45
AN43
AN42
AN40
AN38

?

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

3

Issued Date

Issued Date

Issued Date

2015/10/08

2015/10/08

2015/10/08

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2015/03/23

2015/03/23

2015/03/23

Title

Title

Title

SOC (VSS)

SOC (VSS)

SOC (VSS)

Size

Size

Size

Document Number Rev

Document Number Rev

Document Number Rev

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

CGx20

CGx20

CGx20

Tuesday, December 08, 2015

Tuesday, December 08, 2015

Tuesday, December 08, 2015

11 57

11 57

1

11 57

0.1

0.1

0.1

5

www.laptoprepairsecrets.com

4

3

2

1

Hardware STRAPS
(Follow up CRB)

+1.8VALW

+1.8VALW

D D

RC9263
10K_0402_1%

@

1 2

RC9268
100K_0402_5%

@

1 2

1 2

RC46

4.7K_0402_5%

RC9276

4.7K_0402_5%

@

1 2

GPIO_SUS_5

GPIO_SUS_0 7

GPIO_SUS_1 7

GPIO_SUS_2 7

GPIO_SUS_4 7

GPIO_SUS_5 7

GPIO_SUS_8 7

RC961

4.7K_0402_1%

1 2

0606

RC9273
100K_0402_5%

1 2

C C

RC9277

4.7K_0402_5%

1 2

B B

1 2

@

RC49
10K_0402_1%

@

1 2

RC9274
100K_0402_5%

RC9275
10K_0402_5%

1 2

RC51
10K_0402_1%

@

1 2

RC9264
10K_0402_1%

1 2

RC9262
100K_0402_5%

@

1 2

RC9266
10K_0402_1%

@

@

1 2

RC9270
100K_0402_5%

@

1 2

1 2

RC9265

4.7K_0402_5%

RC9267
1K_0402_1%

@

1 2

RC9271
10K_0402_1%

@

1 2

GPIO_SUS_6

GPIO_SUS_9 7

EC_SCI# 7,44

GPIO_CAM_8 4

GPIO_CAM_9 4

GPIO_CAM_11 4

13

D

QC214

2

ME2
SHORT PADS

1 2

A A

5

4

G

S

2N7002KW_SOT323-3

RC962

1 2

0_0402_5%

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUT URE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUT URE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUT URE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

PCH_ME_PROTECT 44

2015/10/08

2015/10/08

2015/10/08

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2015/03/23

2015/03/23

2015/03/23

Title

Title

Title

SOC (STRAPS & OTHERS)

SOC (STRAPS & OTHERS)

SOC (STRAPS & OTHERS)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Tuesday, December 08, 2015

Tuesday, December 08, 2015

Tuesday, December 08, 2015

CGx20

CGx20

CGx20

12 57

12 57

1

12 57

0.1

0.1

0.1

5

www.laptoprepairsecrets.com

D D

C C

4

3

2

1

B B

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUT URE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUT URE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUT URE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2015/10/08

2015/10/08

2015/10/08

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2015/03/23

2015/03/23

2015/03/23

Title

MCP (OTHER)

MCP (OTHER)

MCP (OTHER)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Tuesday, December 08, 2015

Tuesday, December 08, 2015

Tuesday, December 08, 2015

CGx20

CGx20

CGx20

13 57

13 57

1

13 57

0.1

0.1

0.1

5

www.laptoprepairsecrets.com

4

3

2

1

CD52

@

CD152

@

330P_0402_50V7K

EMC_NS@

+0.675VS

+0.675VS

+0.675VS

2

CD145

0.1U_020 1_6.3V6 -K

1

2

CD226

0.1U_020 1_6.3V6 -K

1

@

10U_0603_6.3V6M

1U_0402_6.3V6K

CD63

1

2

33P_0402_50V8J

1U_0402_6.3V6K

CD220

1

2

RF@

0.1U_0201_6.3V6-K

C4908

1

2

RPD1

DDRA_MA 1

1 8

DDRA_MA 4

2 7

DDRA_MA 2

3 6

DDRA_BS1#

DDRA_D Q[63:0] 5

DDRA_MA [15:0] 5

D D

C C

B B

A A

DDRA_D QS[7:0] 5

DDRA_D QS#[7:0] 5

DDRA_D M[7:0] 5

DDRA_BS0#5
DDRA_BS1#5
DDRA_BS2#5

DDRA_CLK05
DDRA_CLK0#5

DDRA_CKE05

DDRA_RAS#5
DDRA_CAS#5
DDRA_WE#5

Del CS_2(chip select: 1 per Rank)
Del CKE_2(chip select: 1 per Rank???)

DDRA_CS0#5

DDRA_ODT05

DDRA_D RAMRST#5

DDRA_MA 0
DDRA_MA 1
DDRA_MA 2
DDRA_MA 3
DDRA_MA 4
DDRA_MA 5
DDRA_MA 6
DDRA_MA 7
DDRA_MA 8
DDRA_MA 9
DDRA_MA 10
DDRA_MA 11
DDRA_MA 12
DDRA_MA 13

DDRA_MA 14
DDRA_MA 15

DDRA_BS0#
DDRA_BS1#
DDRA_BS2#

DDRA_CLK0
DDRA_CLK0#

DDRA_CKE0

DDRA_RAS#
DDRA_CAS#
DDRA_WE#

DDRA_DQS1
DDRA_DQS#1

DDRA_DQS0
DDRA_DQS#0

DDRA_D M1
DDRA_D M0

DDRA_CS0# DDRA_CS0#

DDRA_ODT0

1 2

RD64 240_0402_1%

DDRA_MA 0
DDRA_MA 1
DDRA_MA 2
DDRA_MA 3
DDRA_MA 4
DDRA_MA 5
DDRA_MA 6
DDRA_MA 7
DDRA_MA 8
DDRA_MA 9
DDRA_MA 10
DDRA_MA 11
DDRA_MA 12
DDRA_MA 13

DDRA_MA 14
DDRA_MA 15

DDRA_BS0#
DDRA_BS1#
DDRA_BS2#

DDRA_CLK0
DDRA_CLK0#

DDRA_CKE0

DDRA_RAS#
DDRA_CAS#
DDRA_WE#

DDRA_DQS6
DDRA_DQS#6

DDRA_DQS4
DDRA_DQS#4

DDRA_D M6
DDRA_D M4

DDRA_CS0#

1 2

RD61 240_0402_1%

DDRA_D RAMRST#

U46

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC#

T3

A13

T7

A14

M7

NC5

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK#

K9

CKE

VDDQ1

J9

NC2

VDDQ2
VDDQ3
VDDQ4

J3

RAS#

VDDQ5

K3

CAS#

VDDQ6

L3

WE#

VDDQ7
VDDQ8
VDDQ9

F3

DQSL

G3

DQSL#

VREFCA

C7

DQSU

VREFDQ

B7

DQSU#

E7

DML

VSSQ1

D3

DMU

VSSQ2
VSSQ3
VSSQ4
VSSQ5

L2

CS#

VSSQ6

L1

NC3

VSSQ7
VSSQ8
VSSQ9

K1

ODT

J1

NC1

L8

ZQ

L9

NC4

0603

T2

RESET#

H5TC4G6 3AFR-PB A_FBG A96

@

U45

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC#

T3

A13

T7

A14

M7

NC5

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK#

K9

CKE

J9

NC2

J3

RAS#

K3

CAS#

L3

WE#

F3

DQSL

G3

DQSL#

C7

DQSU

B7

DQSU#

E7

DML

D3

DMU

L2

CS#

L1

NC3

K1

ODT

J1

NC1

L8

ZQ

L9

NC4

T2

RESET#

H5TC4G6 3AFR-PB A_FBG A96

@

VREFCA
VREFDQ

VSS10
VSS11
VSS12

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9

VSS10
VSS11
VSS12

DDRA_DQ12

E3

DDRA_DQ8

DQL0

F7

DDRA_DQ15

DQL1

F2

DDRA_DQ11

DQL2

F8

DDRA_DQ13

DQL3

H3

DDRA_DQ14

DQL4

H8

DDRA_DQ10

DQL5

G2

DDRA_DQ9

DQL6

H7

DDRA_DQ1

DQL7

D7

DDRA_DQ2

DQU0

C3

DDRA_DQ0

DQU1

C8

DDRA_DQ3

DQU2

C2

DDRA_DQ4

DQU3

A7

DDRA_DQ7

DQU4

A2

DDRA_DQ5

DQU5

B8

DDRA_DQ6

DQU6

A3

DQU7

B2

VDD1

D9

VDD2

G7

VDD3

K2

VDD4

K8

VDD5

N1

VDD6

N9

VDD7

R1

VDD8

R9

VDD9

A1
A8
C1
C9
D2
E9
F1
H2
H9

M8
H1

B1
B9
D1
D8
E2
E8
F9
G1
G9

A9

VSS1

B3

VSS2

E1

VSS3

G8

VSS4

J2

VSS5

J8

VSS6

M1

VSS7

M9

VSS8

P1

VSS9

P9
T1
T9

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

B2

VDD1

D9

VDD2

G7

VDD3

K2

VDD4

K8

VDD5

N1

VDD6

N9

VDD7

R1

VDD8

R9

VDD9

A1
A8
C1
C9
D2
E9
F1
H2
H9

M8
H1

B1
B9
D1
D8
E2
E8
F9
G1
G9

A9

VSS1

B3

VSS2

E1

VSS3

G8

VSS4

J2

VSS5

J8

VSS6

M1

VSS7

M9

VSS8

P1

VSS9

P9
T1
T9

+1.35V

+VREF_D Q_DIMMA

DDRA_DQ49
DDRA_DQ48
DDRA_DQ52
DDRA_DQ51
DDRA_DQ53
DDRA_DQ50
DDRA_DQ54
DDRA_DQ55

DDRA_DQ32
DDRA_DQ39
DDRA_DQ33
DDRA_DQ35
DDRA_DQ37 DDRA_DQ43
DDRA_DQ38
DDRA_DQ36
DDRA_DQ34

+VREF_D Q_DIMMA

+VREF_C A

1

1

CD94

CD93

.047U_02 01_6.3V 6K

2

.047U_02 01_6.3V 6K

2

+1.35V

+VREF_C A

1

1

CD66

CD65

.047U_02 01_6.3V 6K

2

.047U_02 01_6.3V 6K

2

DDRA_MA 0
DDRA_MA 1
DDRA_MA 2
DDRA_MA 3
DDRA_MA 4
DDRA_MA 5
DDRA_MA 6
DDRA_MA 7
DDRA_MA 8
DDRA_MA 9
DDRA_MA 10
DDRA_MA 11
DDRA_MA 12
DDRA_MA 13

DDRA_MA 14
DDRA_MA 15

DDRA_BS0#
DDRA_BS1#
DDRA_BS2#

DDRA_CLK0
DDRA_CLK0#

DDRA_CKE0

DDRA_RAS#
DDRA_CAS#
DDRA_WE#

DDRA_DQS3
DDRA_DQS#3

DDRA_DQS2
DDRA_DQS#2

DDRA_D M3
DDRA_D M2

DDRA_ODT0

1 2

RD95 240_0402_1%

DDRA_D RAMRST#

DDRA_MA 0
DDRA_MA 1
DDRA_MA 2
DDRA_MA 3
DDRA_MA 4
DDRA_MA 5
DDRA_MA 6
DDRA_MA 7
DDRA_MA 8
DDRA_MA 9
DDRA_MA 10
DDRA_MA 11
DDRA_MA 12
DDRA_MA 13

DDRA_MA 14
DDRA_MA 15

DDRA_BS0#
DDRA_BS1#
DDRA_BS2#

DDRA_CLK0
DDRA_CLK0#

DDRA_CKE0

DDRA_RAS#
DDRA_CAS#
DDRA_WE#

DDRA_DQS7
DDRA_DQS#7

DDRA_DQS5
DDRA_DQS#5

DDRA_D M7
DDRA_D M5

DDRA_CS0#

DDRA_ODT0DDRA_ODT0

1 2

RD93 240_0402_1%

DDRA_D RAMRST#

U48

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC#

T3

A13

T7

A14

M7

NC5

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK#

K9

CKE

J9

NC2

J3

RAS#

K3

CAS#

L3

WE#

F3

DQSL

G3

DQSL#

C7

DQSU

B7

DQSU#

E7

DML

D3

DMU

L2

CS#

L1

NC3

K1

ODT

J1

NC1

L8

ZQ

L9

NC4

T2

RESET#

H5TC4G6 3AFR-PB A_FBG A96

@

U47

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC#

T3

A13

T7

A14

M7

NC5

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK#

K9

CKE

J9

NC2

J3

RAS#

K3

CAS#

L3

WE#

F3

DQSL

G3

DQSL#

C7

DQSU

B7

DQSU#

E7

DML

D3

DMU

L2

CS#

L1

NC3

K1

ODT

J1

NC1

L8

ZQ

L9

NC4

T2

RESET#

H5TC4G6 3AFR-PB A_FBG A96

@

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VREFCA
VREFDQ

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9

VSS10
VSS11
VSS12

VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6

DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD1

VDD2

VDD3

VDD4

VDD5

VDD6

VDD7

VDD8

VDD9

VSS1

VSS2

VSS3

VSS4

VSS5

VSS6

VSS7

VSS8

VSS9

VDDQ1

VDDQ2

VDDQ3

VDDQ4

VDDQ5

VDDQ6

VDDQ7

VDDQ8

VDDQ9

VREFCA

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9

VSS10
VSS11
VSS12

DDRA_DQ30

E3

DDRA_DQ31

F7

DDRA_DQ27

F2

DDRA_DQ29

F8

DDRA_DQ28

H3

DDRA_DQ24

H8

DDRA_DQ25

G2

DDRA_DQ26

H7

DDRA_DQ19

D7

DDRA_DQ21

C3

DDRA_DQ23

C8

DDRA_DQ20

C2

DDRA_DQ22

A7

DDRA_DQ16

A2

DDRA_DQ18

B8

DDRA_DQ17

A3

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

M8
H1

B1
B9
D1
D8
E2
E8
F9
G1
G9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9

+1.35V

+VREF_D Q_DIMMA

DDRA_DQ60

E3

DDRA_DQ58

F7

DDRA_DQ61

F2

DDRA_DQ62

F8

DDRA_DQ56

H3

DDRA_DQ59

H8

DDRA_DQ57

G2

DDRA_DQ63

H7

DDRA_DQ42

D7

DDRA_DQ45

C3

DDRA_DQ46

C8

DDRA_DQ40

C2
A7

DDRA_DQ41

A2

DDRA_DQ47

B8

DDRA_DQ44

A3

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

M8

+VREF_D Q_DIMMA

H1

B1
B9
D1
D8
E2
E8
F9
G1
G9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

+VREF_C A

1

CD98
.047U_02 01_6.3V 6K

2

+1.35V

+VREF_C A

1

CD95
.047U_02 01_6.3V 6K

2

Signal voltage level = 0.675 V
PLACE TWO 4.7K RESISTORS CLOSE TO
DIMMS ON DIMM_VREF_CA / DIMM_VREF_DQ
Decoupling caps are needed; one 0.1 μ F placed close to VREF pins

Trace width:20 mils
Space:20 mil s

12

RD12

4.7K_04 02_1%

12

RD14

4.7K_04 02_1%

1

CD97
.047U_02 01_6.3V 6K

2

1

CD96
.047U_02 01_6.3V 6K

2

+1.35V

(10uF_0603_6.3V)*6

10U_0603_6.3V6M

CD35

1

2

1U_0402_6.3V6K

CD153

1

2

1U_0402_6.3V6K

CD158

1

2

1U_0402_6.3V6K

CD164

1

2

1U_0402_6.3V6K

CD171

1

2

+VREF_C A

1

2

1

2

1

2

1

2

1

2

+1.35V+1.35V

12

RD6

+VREF_C A+VREF_D Q_DIMMA

10U_0603_6.3V6M

CD36

1U_0402_6.3V6K

CD154

1U_0402_6.3V6K

CD160

1U_0402_6.3V6K

CD166

1U_0402_6.3V6K

CD173

4.7K_04 02_1%

12

RD8

4.7K_04 02_1%

change 0.2pf

2

CD147

0.2P_04 02_50V 8-B

1

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

CD37

1

1

2

2

1U_0402_6.3V6K

CD155

1

1

2

2

1U_0402_6.3V6K

CD161

1

1

2

2

1U_0402_6.3V6K

CD167

1

1

2

2

1U_0402_6.3V6K

CD172

1

1

2

2

10U_0603_6.3V6M

CD38

CD39

CD40

1

1

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

CD157

CD159

CD156

1U_0402_6.3V6K

CD163

1U_0402_6.3V6K

CD168

1U_0402_6.3V6K

CD174

CD216

1

1

1

2

2

2

RF@

1U_0402_6.3V6K

1U_0402_6.3V6K

CD217

CD162

CD165

1

1

1

2

2

2

RF@

1U_0402_6.3V6K

1U_0402_6.3V6K

CD169

CD218

CD170

1

1

1

2

2

2

RF@

1U_0402_6.3V6K

1U_0402_6.3V6K

CD219

CD175

CD176

1

1

1

2

2

2

RF_NS@

+0.675VS

33P_0402_50V8J

33P_0402_50V8J

33P_0402_50V8J

33P_0402_50V8J

+1.35V

1

2

EMC_NS@

0.1U_0201_6.3V6-K

C4901

EMC_NS@

1U_0402_6.3V6K

CD49

1

2

1U_0402_6.3V6K

CD150

1

2

330P_0402_50V7K

330P_0402_50V7K

C4903

C4902

C4904

1

1

1

2

2

2

EMC_NS@

EMC_NS@

DDRA_MA 7
DDRA_MA 5
DDRA_MA 8
DDRA_MA 13

DDRA_CKE0
DDRA_MA 10
DDRA_BS0#
DDRA_MA 3

DDRA_RAS#
DDRA_CAS#
DDRA_WE#
DDRA_CS0#

DDRA_BS2#
DDRA_MA 0
DDRA_MA 15
DDRA_MA 12

DDRA_MA 9
DDRA_MA 11
DDRA_MA 14
DDRA_MA 6

DDRA_ODT0

RD97 82_0402_1%

DDRA_CLK0

RD63 82_0402_1%

DDRA_CLK0#

RD59 82_0402_1%

1U_0402_6.3V6K

CD51

CD50

1

1

2

2

@

1U_0402_6.3V6K

CD149

CD151

1

1

2

2

@

330P_0402_50V7K

0.1U_0201_6.3V6-K

C4906

C4905

1

1

2

2

EMC_NS@

EMC_NS@

1U_0402_6.3V6K

1U_0402_6.3V6K

330P_0402_50V7K

EMC_NS@

1 2

1 2
1 2

1

2

4 5

82_0804_8P4R_1%

RPD2

1 8
2 7
3 6
4 5

82_0804_8P4R_1%

RPD3

1 8
2 7
3 6
4 5

82_0804_8P4R_1%

RPD4

1 8
2 7
3 6
4 5

82_0804_8P4R_1%

RPD5

1 8
2 7
3 6
4 5

82_0804_8P4R_1%

RPD6

1 8
2 7
3 6
4 5

82_0804_8P4R_1%

1

2

1

2

C4907

5

4

Title

Title

Security Classif ication

Security Classif ication

Security Classif ication

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2

2015/10/08

2015/10/08

2015/10/08

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2015/03/23

2015/03/23

2015/03/23

Title

DDRIII SO-DIMM A

DDRIII SO-DIMM A

DDRIII SO-DIMM A

Size

Size

Size

Document Number Rev

Document Number Rev

Document Number Rev

D

D

D

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

Tuesday, December 08, 2015

Tuesday, December 08, 2015

Tuesday, December 08, 2015

CGx20

CGx20

CGx20

14 57

14 57

14 57

0.1

0.1

0.1

5

www.laptoprepairsecrets.com

4

3

2

1

DDRB_D Q[63:0] 5

DDRB_MA [15:0] 5

DDRB_D QS[7:0] 5

D D

C C

B B

A A

DDRB_D QS#[7:0] 5

DDRB_D M[7:0] 5

DDRB_BS0#5

DDRB_BS1#5

DDRB_BS2#5

DDRB_CLK05
DDRB_CLK0#5

DDRB_CKE05

DDRB_RAS#5
DDRB_CAS#5
DDRB_WE#5

DDRB_CS0#5

DDRB_ODT05

DDRB_D RAMRST#5

Del CS_2(chip select: 1 per Rank)
Del CKE_2(chip select: 1 per Rank???)

DDRB_MA 0
DDRB_MA 1
DDRB_MA 2
DDRB_MA 3
DDRB_MA 4
DDRB_MA 5
DDRB_MA 6
DDRB_MA 7
DDRB_MA 8
DDRB_MA 9
DDRB_MA 10
DDRB_MA11
DDRB_MA 12
DDRB_MA 13

DDRB_MA 14
DDRB_MA 15

DDRB_BS0#
DDRB_BS1#
DDRB_BS2#

DDRB_CLK0
DDRB_CLK0#

DDRB_CKE0

DDRB_RAS#
DDRB_CAS#
DDRB_WE#

DDRB_DQS1
DDRB_DQS#1

DDRB_DQS3
DDRB_DQS#3

DDRB_D M1

DDRB_D M3

DDRB_ODT0

1 2

RD21 240_0402_1%DCH@

DDRB_MA 0
DDRB_MA 1
DDRB_MA 2
DDRB_MA 3
DDRB_MA 4
DDRB_MA 5
DDRB_MA 6
DDRB_MA 7
DDRB_MA 8
DDRB_MA 9
DDRB_MA 10
DDRB_MA11
DDRB_MA 12
DDRB_MA 13

DDRB_MA 14
DDRB_MA 15

DDRB_BS0#
DDRB_BS1#
DDRB_BS2#

DDRB_CLK0
DDRB_CLK0#

DDRB_CKE0

DDRB_RAS#
DDRB_CAS#
DDRB_WE#

DDRB_DQS6
DDRB_DQS#6

DDRB_DQS5
DDRB_DQS#5

DDRB_D M6
DDRB_D M5

DDRB_CS0#

DDRB_ODT0 DDRB_ODT0

1 2

RD25 240_0402_1%

DCH@

DDRB_D RAMRST#

0603

U40

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC#

T3

A13

T7

A14

M7

NC5

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK#

K9

CKE

J9

NC2

J3

RAS#

K3

CAS#

L3

WE#

F3

DQSL

G3

DQSL#

C7

DQSU

B7

DQSU#

E7

DML

D3

DMU

L2

CS#

L1

NC3

K1

ODT

J1

NC1

L8

ZQ

L9

NC4

T2

RESET#

H5TC4G6 3AFR-PB A_FBG A96

@

U42

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC#

T3

A13

T7

A14

M7

NC5

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK#

K9

CKE

J9

NC2

J3

RAS#

K3

CAS#

L3

WE#

F3

DQSL

G3

DQSL#

C7

DQSU

B7

DQSU#

E7

DML

D3

DMU

L2

CS#

L1

NC3

K1

ODT

J1

NC1

L8

ZQ

L9

NC4

T2

RESET#

H5TC4G6 3AFR-PB A_FBG A96

@

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VREFCA
VREFDQ

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VREFCA
VREFDQ

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9

DDRB_DQ11

E3

DDRB_DQ9

DQL0

F7

DDRB_DQ10

DQL1

F2

DDRB_DQ13

DQL2

F8

DDRB_DQ15

DQL3

H3

DDRB_DQ12

DQL4

H8

DDRB_DQ14

DQL5

G2

DDRB_DQ8

DQL6

H7

DDRB_DQ28

DQL7

D7

DDRB_DQ26

DQU0

C3

DDRB_DQ25

DQU1

C8

DDRB_DQ24

DQU2

C2

DDRB_DQ27

DQU3

A7

DDRB_DQ29

DQU4

A2

DDRB_DQ30

DQU5

B8

DDRB_DQ31

DQU6

A3

DQU7

B2

VDD1

D9

VDD2

G7

VDD3

K2

VDD4

K8

VDD5

N1

VDD6

N9

VDD7

R1

VDD8

R9

VDD9

A1
A8
C1
C9
D2
E9
F1
H2
H9

M8
H1

B1
B9
D1
D8
E2
E8
F9
G1
G9

A9

VSS1

B3

VSS2

E1

VSS3

G8

VSS4

J2

VSS5

J8

VSS6

M1

VSS7

M9

VSS8

P1

VSS9

P9

VSS10

T1

VSS11

T9

VSS12

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

B2

VDD1

D9

VDD2

G7

VDD3

K2

VDD4

K8

VDD5

N1

VDD6

N9

VDD7

R1

VDD8

R9

VDD9

A1
A8
C1
C9
D2
E9
F1
H2
H9

M8
H1

B1
B9
D1
D8
E2
E8
F9
G1
G9

A9

VSS1

B3

VSS2

E1

VSS3

G8

VSS4

J2

VSS5

J8

VSS6

M1

VSS7

M9

VSS8

P1

VSS9

P9

VSS10

T1

VSS11

T9

VSS12

+1.35V +1.35V

1

CD32
.047U_02 01_6.3V 6K

2

DCH@

1

CD48
.047U_02 01_6.3V 6K

DCH@

2

+VREF_C A

+VREF_C A

1

CD31
.047U_02 01_6.3V 6K

2

DCH@

+1.35V +1.35V

+VREF_C A

1

CD47
.047U_02 01_6.3V 6K

DCH@

2

DDRB_DQ50
DDRB_DQ48
DDRB_DQ51
DDRB_DQ52
DDRB_DQ54
DDRB_DQ53
DDRB_DQ55

DDRB_DQ49
DDRB_DQ41
DDRB_DQ47
DDRB_DQ40
DDRB_DQ43
DDRB_DQ45
DDRB_DQ42
DDRB_DQ44
DDRB_DQ46

+VREF_D Q_DIMMB

+VREF_D Q_DIMMB

DDRB_MA 0
DDRB_MA 1
DDRB_MA 2
DDRB_MA 3
DDRB_MA 4
DDRB_MA 5
DDRB_MA 6
DDRB_MA 7
DDRB_MA 8
DDRB_MA 9
DDRB_MA 10
DDRB_MA11
DDRB_MA 12
DDRB_MA 13

DDRB_MA 14
DDRB_MA 15

DDRB_BS0#
DDRB_BS1#
DDRB_BS2#

DDRB_CLK0
DDRB_CLK0#

DDRB_CKE0

DDRB_RAS#
DDRB_CAS#
DDRB_WE#

DDRB_DQS0
DDRB_DQS#0

DDRB_DQS2
DDRB_DQS#2

DDRB_D M0

DDRB_D M2

DDRB_CS0#DDRB_CS0#

DDRB_ODT0

1 2

RD23 240_0402_1%

DCH@

DDRB_D RAMRST#

DDRB_MA 0
DDRB_MA 1
DDRB_MA 2
DDRB_MA 3
DDRB_MA 4
DDRB_MA 5
DDRB_MA 6
DDRB_MA 7
DDRB_MA 8
DDRB_MA 9
DDRB_MA 10
DDRB_MA11
DDRB_MA 12
DDRB_MA 13

DDRB_MA 14
DDRB_MA 15

DDRB_BS0#
DDRB_BS1#
DDRB_BS2#

DDRB_CLK0
DDRB_CLK0#

DDRB_CKE0

DDRB_RAS#
DDRB_CAS#
DDRB_WE#

DDRB_DQS4
DDRB_DQS#4

DDRB_DQS7
DDRB_DQS#7

DDRB_D M4
DDRB_D M7

DDRB_CS0#

1 2

RD27 240_0402_1%

DCH@

DDRB_D RAMRST#

U41

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC#

T3

A13

T7

A14

M7

NC5

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK#

K9

CKE

J9

NC2

J3

RAS#

K3

CAS#

L3

WE#

F3

DQSL

G3

DQSL#

C7

DQSU

B7

DQSU#

E7

DML

D3

DMU

L2

CS#

L1

NC3

K1

ODT

J1

NC1

L8

ZQ

L9

NC4

T2

RESET#

H5TC4G6 3AFR-PB A_FBG A96

@

U43

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC#

T3

A13

T7

A14

M7

NC5

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK#

K9

CKE

J9

NC2

J3

RAS#

K3

CAS#

L3

WE#

F3

DQSL

G3

DQSL#

C7

DQSU

B7

DQSU#

E7

DML

D3

DMU

L2

CS#

L1

NC3

K1

ODT

J1

NC1

L8

ZQ

L9

NC4

T2

RESET#

H5TC4G6 3AFR-PB A_FBG A96

@

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VREFCA
VREFDQ

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8

VSS9
VSS10
VSS11
VSS12

VDDQ1

VDDQ2

VDDQ3

VDDQ4

VDDQ5

VDDQ6

VDDQ7

VDDQ8

VDDQ9

VREFCA
VREFDQ

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9

VSS10
VSS11
VSS12

DDRB_DQ4

E3

DDRB_DQ3

F7

DDRB_DQ1

F2

DDRB_DQ2

F8

DDRB_DQ0

H3

DDRB_DQ7

H8

DDRB_DQ5

G2

DDRB_DQ6

H7

DDRB_DQ18

D7

DDRB_DQ17

C3

DDRB_DQ23

C8

DDRB_DQ16

C2

DDRB_DQ20

A7

DDRB_DQ19

A2

DDRB_DQ21

B8

DDRB_DQ22

A3

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

M8

+VREF_D Q_DIMMB

H1

B1
B9
D1
D8
E2
E8
F9
G1
G9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DDRB_DQ33

E3

DDRB_DQ34

DQL0

F7

DDRB_DQ32

DQL1

F2

DDRB_DQ38

DQL2

F8

DDRB_DQ36

DQL3

H3

DDRB_DQ35

DQL4

H8

DDRB_DQ37

DQL5

G2

DDRB_DQ39

DQL6

H7

DDRB_DQ57

DQL7

D7

DDRB_DQ58

DQU0

C3

DDRB_DQ61

DQU1

C8

DDRB_DQ63

DQU2

C2

DDRB_DQ62

DQU3

A7

DDRB_DQ56

DQU4

A2

DDRB_DQ60

DQU5

B8

DDRB_DQ59

DQU6

A3

DQU7

B2

VDD1

D9

VDD2

G7

VDD3

K2

VDD4

K8

VDD5

N1

VDD6

N9

VDD7

R1

VDD8

R9

VDD9

A1
A8
C1
C9
D2
E9
F1
H2
H9

M8

+VREF_D Q_DIMMB

H1

B1
B9
D1
D8
E2
E8
F9
G1
G9

A9

VSS1

B3

VSS2

E1

VSS3

G8

VSS4

J2

VSS5

J8

VSS6

M1

VSS7

M9

VSS8

P1

VSS9

P9
T1
T9

+VREF_C A

1

CD33
.047U_02 01_6.3V 6K

2

DCH@

+VREF_C A

1

CD53
.047U_02 01_6.3V 6K

2

DCH@

1

CD34
.047U_02 01_6.3V 6K

2

DCH@

1

2

Signal voltage level = 0.675 V
PLACE TWO 4.7K RESISTORS CLOSE TO
DIMMS ON DIMM_VREF_CA / DIMM_VREF_DQ
Decoupling caps are needed; one 0.1 μ F placed close to VREF pins

Trace width:20 mils
Space:20 mil s

+1.35V

12

RD11

4.7K_04 02_1%

DCH@

12

RD13

4.7K_04 02_1%

DCH@

+1.35V

CD54
.047U_02 01_6.3V 6K

DCH@

+VREF_D Q_DIMMB

(10uF_0603_6.3V)*6

10U_0603_6.3V6M

CD182

CD185

1

1

2

2

DCH@

DCH@

1U_0402_6.3V6K

CD192

CD193

1

1

2

2

DCH@

DCH@

1U_0402_6.3V6K

CD197

CD199

1

1

2

2

DCH@

DCH@

1U_0402_6.3V6K

CD203

CD205

1

1

2

2

DCH@

DCH@

1U_0402_6.3V6K

CD213

CD211

1

1

2

2

DCH@

DCH@

RPD8

DDRB_MA 13

1 8

DDRB_MA 3

2 7

DDRB_MA 2

3 6

DDRB_MA 4

4 5

82_0804_8P4R_1%
RPD9

DDRB_MA 5

1 8

DDRB_MA 9

2 7

DDRB_MA11

3 6

DDRB_MA 0

4 5

82_0804_8P4R_1%
RPD10

DDRB_MA 8

1 8

DDRB_MA 7

2 7

DDRB_MA 14

3 6

DDRB_MA 6

4 5

82_0804_8P4R_1%
RPD11

DDRB_MA 1

1 8

DDRB_MA 12

2 7

DDRB_BS2#

3 6

DDRB_MA 15

4 5

82_0804_8P4R_1%
RPD12

DDRB_BS0#

1 8

DDRB_BS1#

2 7

DDRB_MA 10

3 6

DDRB_CKE0

4 5

82_0804_8P4R_1%
RPD13

DDRB_WE#

1 8

DDRB_RAS#

2 7

DDRB_CAS#

3 6

DDRB_CS0#

4 5

82_0804_8P4R_1%

Need change to 36ohm 5%

DDRB_ODT0

1 2

RD99 82_0402_1%D CH@

change 0.2pf

2

CD148

0.2P_04 02_50V 8-B

1

DCH@

10U_0603_6.3V6M

10U_0603_6.3V6M

CD187

1

1

2

2

DCH@

DCH@

1U_0402_6.3V6K

1U_0402_6.3V6K

CD194

1

1

2

2

DCH@

DCH@

1U_0402_6.3V6K

1U_0402_6.3V6K

CD200

1

1

2

2

DCH@

DCH@

1U_0402_6.3V6K

1U_0402_6.3V6K

CD206

1

1

2

2

DCH@

DCH@

1U_0402_6.3V6K

1U_0402_6.3V6K

CD210

1

1

2

2

DCH@

DCH@

10U_0603_6.3V6M

CD183

CD184

CD186

1

1

2

2

DCH@

DCH@

1U_0402_6.3V6K

CD195

1

2

DCH@

1U_0402_6.3V6K

CD202

1

2

DCH@

1U_0402_6.3V6K

CD207

1

2

DCH@

1U_0402_6.3V6K

CD212

1

2

DCH@

33P_0402_50V8J

1U_0402_6.3V6K

1U_0402_6.3V6K

CD221

CD196

CD198

1

1

2

2

RF@

DCH@

1U_0402_6.3V6K

33P_0402_50V8J

1U_0402_6.3V6K

CD201

CD222

CD204

1

1

2

2

RF@

DCH@

33P_0402_50V8J

1U_0402_6.3V6K

1U_0402_6.3V6K

CD223

CD208

CD209

1

1

2

2

RF@

DCH@

1U_0402_6.3V6K

1U_0402_6.3V6K

33P_0402_50V8J

CD214

CD215

CD224

1

1

2

2

DCH@

RF_NS@

10U_0603_6.3V6M

10U_0603_6.3V6M

+0.675VS

Need change to 39ohm 5%

DDRB_CLK0

RD32 82_0402_1%D CH@

DDRB_CLK0#

RD29 82_0402_1%D CH@

1U_0402_6.3V6K

CD178

1

2

DCH@

1U_0402_6.3V6K

CD188

1

2

DCH@

DCH@

DCH@

1

2

1

2

1 2
1 2

1U_0402_6.3V6K

CD177

1U_0402_6.3V6K

CD189

+0.675VS

DCH@

DCH@

DCH@

DCH@

DCH@

DCH@

+0.675VS

+0.675VS

2

CD146

0.1U_020 1_6.3V6 -K

1

DCH@

2

CD227

0.1U_020 1_6.3V6 -K

1

@

1U_0402_6.3V6K

CD179

1

2

DCH@

1U_0402_6.3V6K

CD190

1

2

DCH@

10U_0603_6.3V6M

1U_0402_6.3V6K

CD180

CD181

1

1

2

2

DCH@

DCH@

33P_0402_50V8J

1U_0402_6.3V6K

CD225

CD191

1

1

2

2

RF@

DCH@

5

4

Title

Title

Security Classif ication

Security Classif ication

Security Classif ication

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2

2015/10/08

2015/10/08

2015/10/08

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2015/03/23

2015/03/23

2015/03/23

Title

DDRIII SO-DIMM B

DDRIII SO-DIMM B

DDRIII SO-DIMM B

Size

Size

Size

Document Number Rev

Document Number Rev

Document Number Rev

D

D

D

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

Tuesday, December 08, 2015

Tuesday, December 08, 2015

Tuesday, December 08, 2015

CGx20

CGx20

CGx20

15 57

15 57

15 57

0.1

0.1

0.1

5

www.laptoprepairsecrets.com

D D

C C

4

3

2

1

B B

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

2015/10/08

2015/10/08

2015/10/08

3

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2015/03/23

2015/03/23

2015/03/23

2

Title

USB Hub GL850G-OHY31

USB Hub GL850G-OHY31

USB Hub GL850G-OHY31

Size

Size

Size

Document Number Rev

Document Number Rev

Document Number Rev

B

B

B

Tuesday, December 08, 2015

Tuesday, December 08, 2015

Date: Sheet of

Date: Sheet of

Date: Sheet of

Tuesday, December 08, 2015

CGx20

CGx20

CGx20

1

16 57

16 57

16 57

0.1

0.1

0.1

5

www.laptoprepairsecrets.com

D D

C C

B B

4

3

2

1

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUT URE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUT URE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUT URE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2015/10/08

2015/10/08

2015/10/08

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2015/03/23

2015/03/23

2015/03/23

Title

Blank

Blank

Blank

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Tuesday, December 08, 2015

Tuesday, December 08, 2015

Date: Sheet of

Date: Sheet of

Date: Sheet of

Tuesday, December 08, 2015

CGx20

CGx20

CGx20

1

17 57

17 57

17 57

0.1

0.1

0.1

5

www.laptoprepairsecrets.com

D D

C C

4

3

2

1

B B

A A

Title

Title

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

3

Issued Date

Issued Date

Issued Date

2015/10/08

2015/10/08

2015/10/08

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2015/03/23

2015/03/23

2015/03/23

Title

VGA Notes List

VGA Notes List

VGA Notes List

Size

Size

Size

Document Number Rev

Document Number Rev

Document Number Rev

C

C

C

Tuesday, December 08, 2015

Tuesday, December 08, 2015

Tuesday, December 08, 2015

Date: Sheet of

Date: Sheet of

Date: Sheet of

CGx20

CGx20

CGx20

1

18 57

18 57

18 57

0.1

0.1

0.1