Lenovo G400, G500 Schematic

A

1 1

B

C

D

E

Compal Confidential

2 2

G400/G500 UMA M/B Schematics Document

Intel Ivy Bridge Processor with DDRIII + Panther Point PCH

2013-02-27

3 3

LA-9632P

REV:1.0

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Cover Page

LA-9632P

E

1 60Wednesday, February 27, 2013

1.0

of

A

B

C

D

E

Compal confidential

Project Name : VIWGP (14") / VIWGR (15")

Chief River

1 1

Intel Processor Ivy Bridge

rPGA989

37.5mm x 37.5mm

Page 5~11

Memory Bus Dual Channel

DDR3



DDR3 DDR3

1600MHz



1333MHz



1066MHz

204pin DDRIII-SO-DIMM X2

BANK 0, 1, 2

Page 12, 13

FDI *8

2.7GT/s

2 2

LVDS Conn.

Page 23

HDMI Conn.

Page 25

CRT Conn.

Page 24

Intel

DMI2 *4 5GT/s

USB30 x2

USB20 x6

Left USB3.0 x2

USB30 Port 0,1

Page 35

Touch Screen

USB20 Port 2

Page 35

Right USB2.0

USB20 Port 9

Card Reader

Realtek RTS5170

USB20 Port 11

Page 35

page 28

Int. Camera

USB20 Port 3

Page 23

PCH

Page 33

HDD Conn.

SATA Port 0

Page 30

ODD Conn.

SATA Port 2

Audio Codec

CONEXANT CX20757

Page 30

Page 31

Int. MIC Conn.

Page 31

Int. KBD

Page 33

D

Int. Speaker Conn.

Page 31

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Audio Combo Jacks

HP & MIC

MB Block Diagram

LA-9632P

E

2 60Wednesday, February 27, 2013

Page 31

of

1.0

RJ45 Conn.

Page 28

LAN

PCIe Port 0

Atheros AR8162/QCA8172(10/100)

Page 27

PCIe x1

Panther Point

FCBGA 989Balls 25mm x 25mm

3 3

PCIe Mini Card WLAN

PCIe Port 1

Page 26

PCIe x1

Page 14~22

SATA Gen3

SATA

AZALIA

Sub-borad

15" 14"

Power/B

(LID)

4 4

LS9631

USB/B

LS9632 LS9634

IO/B

(Card Reader) (LED, LID)

LS9633

ODD/B

Switch/B

A

LS9635

B

SPI ROM

2MB + 4MB

Page 14

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

EC

ENE KB9012

Page 32

Thermal Sensor

C

Page 29

2011/06/15 2012/07/11

Touch Pad

Compal Secret Data

Deciphered Date

A

B

C

D

E

Voltage Rails

+5VS

power

State

S0

S3

S5 S4/AC

plane

Address

0001 011x

1010 000x A0h

1010 010x A4h

+B

O

X

+5VALW

+3VALW

O

X

X X X

+1.5V

O

X X

X

EC SM Bus2 address

Device

Thermal Sen sor

AMD-GPU SM Bus address

Device A

Internal thermal sensor

1 1

2 2

S5 S4/ Battery only

S5 S4/AC & Battery don't exist

EC SM Bus1 address

Device

Smart Battery

PCH SM Bus address

3 3

Device Address

DDR_JDIMM1

DDR_JDIMM2

+3VS

+1.5VS

+V1.05S_VCCP

+VCC_CORE

+VGA_CORE

+VCC_GFXCORE_AXG

+1.8VS

+0.75VS

+1.05VS

OO

X

Address

0100 1100

ddress

0100 0001 41h

BOARD ID Table

Board ID

0 1 2 3 4 5 6 7

USB Port Table

EHCI1

EHCI2

PCB Revision

0.1

USB 2.0 Port

UHCI0

UHCI1

UHCI2

UHCI3

UHCI4

UHCI5

UHCI6

0 1 2 3 4 5 6 7 8 9 10 11 12 13

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

Vcc R694

Board ID

0 1 2 3

SIGNAL

3.3V

100K +/- 1%

R695 V

0

12K +/- 1%

15K +/- 1%

20K +/- 1%

SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

HIGH HIGH HIGH HIGH

Board ID / SKU ID Table for AD channel

AD_BID

0.347V

0.423V

0.541V

3 External USB Port

USB Port (Left Side) USB Port (Left Side)

USB3.0

Touch Screen Camera

USB Port (Right Side USB-BD) Mini Card(WLAN) Card Reader

LOW

LOW LOW LOW LOW

min

V

AD_BID

HIGH

LOWLOWLOW

typ

HIGHHIGHHIGH

HIGH

V

AD_BID

0 V 0 V 0 V

0.354V 0.360V

0.430V

0.550V

0.438V

0.559V

BOM Structure Table

VIWGR (15") HDMI Logo 45@ LAN 10/100 8162@

LAN Gas tube GAS@

PCH is HM76 PCH is HM70 PCH is NM70 VGA is Mars XT VGA is Sun Pro For VGA For VRAM and Strap

ON

max

0x00 - 0x0B 0x0C - 0x1C

0x27 - 0x30

BOM StructureItem

ON

OFF

EC AD

14@VIWGP (14") 15@

8172@LAN 10/100 SWR@LAN Switch mode LDO@LAN LDO Mode

CMOS@Camera HDMI@HDMI HM76@ HM70@ NM70@ Mars@ Sun@ PX@ X76@

ON ON

ON

OFF

MP PVT DVT0x1D - 0x26 EVT

LOW

OFF

UMA@For UMA Strap

Microphone MIC@ Touch Screen

SMBUS Control Table

X

XX

V

+3VS

X

Thermal Sensor

+3VS

B

SOURCE

SMB_EC_CK1 SMB_EC_DA1 SMB_EC_CK2 SMB_EC_DA2

4 4

PCH_SMBCLK PCH_SMBDATA PCH_SML0CLK PCH_SML0DATA SML1CLK SML1DATA

KB9012

+3VALW

KB9012

+3VS

PCH

+3VALW

PCH

+3VALW

PCH

+3VALW

VGA BATT KB9012 SODIMM

X V

+3VALW

V

+3VGS

X

V

+3VGS

A

X

+3VS

WLAN

X

V

+3VS

X

V

PCH

X

V

X

XX

V

X

V

+3VALW

X

XX X

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

D

Board ID for EVT

For USB2.0 (All PCH)

For share ROM For non-share ROM NOSROM@

Title

Size Document Number Rev

B

LA-9632P

Date: Sheet

TS@

ME@Connector

EVT@

DVT@Board ID for DVT

PVT@Board ID for PVT

USB2@

USB3@For USB3.0 (HM76,HM70)

SROM@

Compal Electronics, Inc.

Notes List

of

3 60Wednesday, February 27, 2013

of

3 60Wednesday, February 27, 2013

of

3 60Wednesday, February 27, 2013

E

1.0

5

D D

C C

4

3

2

1

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

2011/06/15 2012/07/11

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

VGA Notes List

LA-9632P

4 60Wednesday, February 27, 2013

1

1.0

of

5

ZZZ1

14@

ZZZ1

14@

14"_UMA_PCB_LA9632P

DA6000WP000

DA6000WP000 PCB 0Y0 LA-9632P REV0 M/B UMA 3

PCB 0Y0 LA-9632P REV0 M/B UMA 3

D D

C C

B B

eDP_COMPIO and ICOMPO signals should be shorted near balls and routed with typical impedance <25 mohms

ZZZ2

15@

ZZZ2

15@

15"_UMA_PCB_LA9632P

DA6000WP100

DA6000WP100 PCB 0Y0 LA-9632P REV0 M/B UMA 5

PCB 0Y0 LA-9632P REV0 M/B UMA 5

+V1.05S_VCCP

12

R7

24.9_0402_1%

DMI_CRX_PTX_N0<16> DMI_CRX_PTX_N1<16> DMI_CRX_PTX_N2<16> DMI_CRX_PTX_N3<16>

DMI_CRX_PTX_P0<16> DMI_CRX_PTX_P1<16> DMI_CRX_PTX_P2<16> DMI_CRX_PTX_P3<16>

DMI_CTX_PRX_N0<16> DMI_CTX_PRX_N1<16> DMI_CTX_PRX_N2<16> DMI_CTX_PRX_N3<16>

DMI_CTX_PRX_P0<16> DMI_CTX_PRX_P1<16> DMI_CTX_PRX_P2<16> DMI_CTX_PRX_P3<16>

FDI_CTX_PRX_N0<16> FDI_CTX_PRX_N1<16> FDI_CTX_PRX_N2<16> FDI_CTX_PRX_N3<16> FDI_CTX_PRX_N4<16> FDI_CTX_PRX_N5<16> FDI_CTX_PRX_N6<16> FDI_CTX_PRX_N7<16>

FDI_CTX_PRX_P0<16> FDI_CTX_PRX_P1<16> FDI_CTX_PRX_P2<16> FDI_CTX_PRX_P3<16> FDI_CTX_PRX_P4<16> FDI_CTX_PRX_P5<16> FDI_CTX_PRX_P6<16> FDI_CTX_PRX_P7<16>

FDI_FSYNC0<16> FDI_FSYNC1<16>

FDI_INT<16>

FDI_LSYNC0<16> FDI_LSYNC1<16>

EDP_COMP

eDP_HPD

4

JCPU1A

B27

DMI_RX#[0]

B25

DMI_RX#[1]

A25

DMI_RX#[2]

B24

DMI_RX#[3]

B28

DMI_RX[0]

B26

DMI_RX[1]

A24

DMI_RX[2]

B23

DMI_RX[3]

G21

DMI_TX#[0]

E22

DMI_TX#[1]

F21

DMI_TX#[2]

D21

DMI_TX#[3]

G22

DMI_TX[0]

D22

DMI_TX[1]

F20

DMI_TX[2]

C21

DMI_TX[3]

A21

FDI0_TX#[0 ]

H19

FDI0_TX#[1 ]

E19

FDI0_TX#[2 ]

F18

FDI0_TX#[3 ]

B21

FDI1_TX#[0 ]

C20

FDI1_TX#[1 ]

D18

FDI1_TX#[2 ]

E17

FDI1_TX#[3 ]

A22

FDI0_TX[0]

G19

FDI0_TX[1]

E20

FDI0_TX[2]

G18

FDI0_TX[3]

B20

FDI1_TX[0]

C19

FDI1_TX[1]

D19

FDI1_TX[2]

F17

FDI1_TX[3]

J18

FDI0_FSYNC

J17

FDI1_FSYNC

H20

FDI_INT

J19

FDI0_LSYNC

H17

FDI1_LSYNC

A18

eDP_COMP IO

A17

eDP_ICOMPO

B16

eDP_HPD#

C15

eDP_AUX

D15

eDP_AUX#

C17

eDP_TX[0]

F16

eDP_TX[1]

C16

eDP_TX[2]

G15

eDP_TX[3]

C18

eDP_TX#[0 ]

E16

eDP_TX#[1 ]

D16

eDP_TX#[2 ]

F15

eDP_TX#[3 ]

TYCO_2013620-2_IVY BRIDGE

ME@

PEG_RX[0 ] PEG_RX[1 ] PEG_RX[2 ] PEG_RX[3 ] PEG_RX[4 ] PEG_RX[5 ] PEG_RX[6 ] PEG_RX[7 ] PEG_RX[8 ] PEG_RX[9 ]

PEG_TX[0 ] PEG_TX[1 ] PEG_TX[2 ] PEG_TX[3 ] PEG_TX[4 ] PEG_TX[5 ] PEG_TX[6 ] PEG_TX[7 ] PEG_TX[8 ] PEG_TX[9 ]

J22 J21 H22

K33 M35 L34 J35 J32 H34 H31 G33 G30 F35 E34 E32 D33 D31 B33 C32

J33 L35 K34 H35 H32 G34 G31 F33 F30 E35 E33 F32 D34 E31 C33 B32

M29 M32 M31 L32 L29 K31 K28 J30 J28 H29 G27 E29 F27 D28 F26 E25

M28 M33 M30 L31 L28 K30 K27 J29 J27 H28 G28 E28 F28 D27 E26 D25

PEG_ICOMP I

PEG_ICOMP O

PEG_RCO MPO

PEG_RX# [0] PEG_RX# [1] PEG_RX# [2] PEG_RX# [3] PEG_RX# [4] PEG_RX# [5] PEG_RX# [6]

DMI

Intel(R) FDI

eDP

PEG_RX# [7] PEG_RX# [8]

PEG_RX# [9] PEG_RX# [10] PEG_RX# [11] PEG_RX# [12] PEG_RX# [13] PEG_RX# [14] PEG_RX# [15]

PEG_RX[1 0]

PEG_RX[1 1]

PEG_RX[1 2]

PEG_RX[1 3]

PEG_RX[1 4]

PEG_RX[1 5]

PEG_TX# [0]

PEG_TX# [1]

PEG_TX# [2]

PEG_TX# [3]

PEG_TX# [4]

PEG_TX# [5]

PEG_TX# [6]

PEG_TX# [7]

PEG_TX# [8]

PEG_TX# [9] PEG_TX# [10] PEG_TX# [11] PEG_TX# [12]

PCI EXPRESS* - GRAPHICS

PEG_TX# [13] PEG_TX# [14] PEG_TX# [15]

PEG_TX[1 0]

PEG_TX[1 1]

PEG_TX[1 2]

PEG_TX[1 3]

PEG_TX[1 4]

PEG_TX[1 5]

3

PEG_COMP

PEG_ICOMPI and RCOMPO signals should be shorted and routed

+V1.05S_VCCP

R1

24.9_0402_1%

12

with - max length = 500 mils - typical impedance = 43 mohms PEG_ICOMPO signals should be routed with max length = 500 mils

- typical impedance = 14.5 mohms

PEG Static Lane Reversal - CF G2 is for the 16x

CFG2

1: Normal Operation; Lane # definition matches socket pin map definition

0:Lane Reversed

*

2

1

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/15 2012/07/11

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PROCESSOR(1/7) DMI,FDI,PEG

LA-9632P

1

of

5 60Wednesday, February 27, 2013

of

5 60Wednesday, February 27, 2013

of

5 60Wednesday, February 27, 2013

1.0

5

D D

+V1.05S_VCCP

12

R9

62_0402_5%

H_PROCHOT#<32,36,37,43>

C C

H_CPUPWRGD<19>

H_PROCHOT#

22P_0402_50V8J

C549

H_PM_SYNC<16>

R27

1

10K_0402_5%

1 2

2

ESD

4

JCPU1B

H_SNB_IVB#<19>

T48T48

H_PECI<32>

R15

56_0402_5%

1 2

H_THRMTRIP#<19>

R29

1 2

130_0402_5%

H_CATERR#

H_PROCHOT#_R

PM_DRAM_PWR GD_R

BUF_CPU_RST#

C26

AN34

AL33

AN33

AL32

AN32

AM34

AP33

V8

AR33

PROC_SELECT#

SKTOCC#

CATERR#

PECI

PROCHOT#

THERMTRIP#

PM_SYNC

UNCOREPWRGOOD

SM_DRAMPWR OK

RESET#

3

BCLK

BCLK#

MISCTHERMALPWR MANAGEMENT

DPLL_REF_CLK

DPLL_REF_CLK#

CLOCKS

SM_DRAMRST#

SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]

DDR3

MISC

DDR3

MISC

PRDY#

PREQ#

TCK TMS

TRST#

TDI

TDO

DBR#

BPM#[0] BPM#[1]

JTAG & BPM

BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]

A28 A27

A16 A15

R8

AK1 A5 A4

H_DRAMRST#

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

12

R12 1K_0402_5%R12 1K_0402_5%

12

R13 1K_0402_5%R13 1K_0402_5%

H_DRAMRST# <7>

12

R16 140_0402_1%R16 140_0402_1%

12

R17 25.5_0402_1%R17 25.5_0402_1%

12

R18 200_0402_1%R18 200_0402_1%

DDR3 Compe nsation Si gnals

AP29

XDP_PRDY#

AP27

XDP_PREQ#

AR26

XDP_TCK

AR27

XDP_TMS

AP30

XDP_TRST#

AR28

XDP_TDI

AP26

XDP_TDO

AL35

XDP_DBRESET#

AT28

XDP_BPM#0

AR29

XDP_BPM#1

AR30

XDP_BPM#2

AT30

XDP_BPM#3

AP32

XDP_BPM#4

AR31

XDP_BPM#5

AT31

XDP_BPM#6

AR32

XDP_BPM#7

2

+V1.05S_VCCP

R28 1K_0402_5%R28 1K_0402_5 %

12

C45

C45 47P_0402_50V8J

47P_0402_50V8J

D

ES

CLK_CPU_DMI <15> CLK_CPU_DMI# <15>

XDP_TRST# XDP_TDI XDP_TMS XDP_TCK

12

51_0804_8P4R_5%

+3VS

@

RP13

1

+V1.05S_VCCP

18 27 36 45

12

C46

C46 100P_0402_50V8J

100P_0402_50V8J

ESD

TYCO_2013620-2_IVY BRIDGE

+3VALW

TYCO_2013620-2_IVY BRIDGE

ME@

Buffered reset to CPU

B B

U1

1 2

R161

+3VS

10K_0402_5%

PM_DRAM_PWR GD<16>

A A

5

1

P

B

O

2

A

G

74AHC1G09GW_TSSOP5

3

4

PM_SYS_PWRGD_BUF

+1.5V_CPU_VDDQ

12

R30

R30 200_0402_5%

200_0402_5%

+V1.05S_VCCP

12

R32

75_0402_5%

R34

43_0402_1%

BUF_CPU_RST#

4

1 2

BUFO_CPU_RST#

SN74LVC1G07DCKR_SC70-5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

+3VS

5

U2

4

1

P NC

Y

2

PCH_PLTRST#

A

G

3

2011/06/15 2012/07/11

3V

PCH_PLTRST# <18>

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PROCESSOR(2/7) PM,XDP,CLK

Size Document Number Rev

Custom

LA-9632P

Date: Sheet

2

Date: Sheet

1

6 60Wednesday, February 27, 2013

1.0

of

5

JCPU1C

DDR_A_D[0..63]<12>

D D

C C

DDR_A_BS0<12> DDR_A_BS1<12>

B B

DDR_A_BS2<12>

DDR_A_CAS#< 12> DDR_A_RAS#< 12> DDR_A_WE#<12>

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

G10

N10

M10

AG6 AG5 AK6 AK5 AH5 AH6

AK8

AK9 AH8 AH9 AL9

AL8 AP11 AN11

AL12 AM12 AM11

AL11 AP12 AN12

AJ14 AH14

AL15 AK15

AL14 AK14

AJ15 AH15

AE10 AF10

AE8 AD9 AF9

F10

AJ5 AJ6 AJ8

AJ9

C5 D5 D3 D2 D6 C6 C2 C3

F8

G9

F9

F7 G8 G7

K4

K5

K1

K2 M8

N8

N7

M9

N9 M7

V6

J1 J5 J4 J2

SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]

SA_BS[0] SA_BS[1] SA_BS[2]

SA_CAS# SA_RAS# SA_WE#

4

AB6

SA_CLK[0]

AA6

SA_CLK#[0]

V9

SA_CKE[0]

AA5

SA_CLK[1]

AB5

SA_CLK#[1]

V10

SA_CKE[1]

AB4

RSVD_TP[1]

AA4

RSVD_TP[2]

W9

RSVD_TP[3]

AB3

RSVD_TP[4]

AA3

RSVD_TP[5]

W10

RSVD_TP[6]

AK3

SA_CS#[0]

AL3

SA_CS#[1]

AG1

RSVD_TP[7]

AH1

RSVD_TP[8]

AH3

SA_ODT[0]

AG3

SA_ODT[1]

AG2

RSVD_TP[9]

SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]

SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]

SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8]

SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]

AH2

C4 G6 J3 M6 AL6 AM8 AR12 AM15

D4 F6 K3 N6 AL5 AM9 AR11 AM14

AD10 W1 W2 W7 V3 V2 W3 W6 V1 W5 AD8 V4 W4 AF8 V5 V7

DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

RSVD_TP[10]

DDR SYSTEM MEMORY A

M_CLK_DDR0 <12> M_CLK_DDR#0 <12 > DDR_CKE0_DIMMA <12>

M_CLK_DDR1 <12> M_CLK_DDR#1 <12 > DDR_CKE1_DIMMA <12>

DDR_CS0_DIMMA# <12> DDR_CS1_DIMMA# <12>

M_ODT0 <12> M_ODT1 <12>

3

DDR_B_D[0..63]<1 3>

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35

DDR_A_DQS#[0..7] <12>

DDR_A_DQS[0..7] <12>

DDR_A_MA[0..15] <12> DDR_B_MA[0..15] <13>

DDR_B_BS0<13> DDR_B_BS1<13> DDR_B_BS2<13>

DDR_B_CAS#<13> DDR_B_RAS#<13> DDR_B_WE#<13>

DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

AM5 AM6 AR3

AN3 AN2 AN1

AN9

AN8 AR6 AR5 AR9

AJ11

AH11

AR8

AJ12 AH12 AT11 AN14 AR14 AT14 AT12 AN15 AR15 AT15

AA10

D10

K10

AP3

AP2 AP5

AT5 AT6 AP6

AT8 AT9

AA9 AA7

AB8 AB9

C9 A7

C8 A9 A8 D9 D8

G4

F4

F1 G1 G5

F5

F2 G2

K9

J10

K8

K7 M5

N4

N2

N1 M4

N5 M2 M1

R6

J7 J8

J9

JCPU1D

SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63]

SB_BS[0] SB_BS[1] SB_BS[2]

SB_CAS# SB_RAS# SB_WE#

2

AE2

SB_CLK[0]

AD2

SB_CLK#[0]

R9

SB_CKE[0]

AE1

SB_CLK[1]

AD1

SB_CLK#[1]

R10

SB_CKE[1]

SB_CS#[0] SB_CS#[1]

SB_ODT[0] SB_ODT[1]

SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]

SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7]

SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8]

SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]

AB2 AA2 T9

AA1 AB1 T10

AD3 AE3 AD6 AE6

AE4 AD4 AD5 AE5

D7 F3 K6 N3 AN5 AP9 AK12 AP15

C7 G3 J6 M3 AN6 AP8 AK11 AP14

AA8 T7 R7 T6 T2 T4 T3 R2 T5 R3 AB7 R1 T1 AB10 R5 R4

DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15

RSVD_TP[11] RSVD_TP[12] RSVD_TP[13]

RSVD_TP[14] RSVD_TP[15] RSVD_TP[16]

RSVD_TP[17] RSVD_TP[18]

RSVD_TP[19] RSVD_TP[20]

DDR SYSTEM MEMORY B

1

M_CLK_DDR2 <13> M_CLK_DDR#2 <13> DDR_CKE2_DIMMB <13>

M_CLK_DDR3 <13> M_CLK_DDR#3 <13> DDR_CKE3_DIMMB <13>

DDR_CS2_DIMMB# <13> DDR_CS3_DIMMB# <13>

M_ODT2 <13> M_ODT3 <13>

DDR_B_DQS#[0..7] <13>

DDR_B_DQS[0..7] <13>

TYCO_2013620-2_IVY BRIDGE

Deciphered Date

TYCO_2013620-2_IVY BRIDGE

ME@

2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

PROCESSOR(3/7) DDRIII

LA-9632P

1

of

7 60Wednesday, February 27, 2013

of

7 60Wednesday, February 27, 2013

of

7 60Wednesday, February 27, 2013

1.0

TYCO_2013620-2_IVY BRIDGE

ME@

D

S

D

S

13

H_DRAMRST#<6>

R39

4.99K_0402_1%

1 2

@

A A

DRAMRST_CNTRL_PC H<10,15>

5

@

1 2

R48

0_0402_5%

DRAMRST_CNTRL_PC H_R

DDR3_DRAMRST#_RH_DRAMRST#

Q2

G

LBSS138LT1G_SOT-23-3

2

1

C35

0.047U 16V K X7R 0402

2

Eiffel used 0.01u Module design used 0.047u

4

+1.5V

R37

1K_0402_5%

12

R38

R38 1K_0402_5%

1K_0402_5%

1 2

DDR3_DRAMRST# <12,13>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07/11

Compal Secret Data

5

4

3

2

1

CFG Straps for Processor

D D

JCPU1E

AK28

CFG[0]

AK29

CFG[1]

AL26

CFG[2]

AL27

CFG[3]

CFG4

+VCC_GFXCORE_AXG

+VCC_CORE

@

R252

49.9_0402_1%

@

R255

1 2

49.9_0402_1%

1 2

R82 100_0402_1%@R82 100_0402_1%@

1 2

R88 100_0402_1%@R88 100_0402_1%@

VSS_AXG_VAL_SENSE

VSS_VAL_SENSE

R257

49.9_0402_1%

1 2

VCC_AXG_VAL_SENSE

VSS_AXG_VAL_SENSE

VCC_VAL_SENSE

VSS_VAL_SENSE

@

R253

49.9_0402_1%

C C

B B

49.9_0402_1%

AK26

CFG[4]

AL29

CFG[5]

AL30

CFG[6]

AM31

CFG[7]

AM32

CFG[8]

AM30

CFG[9]

AM28

CFG[10]

AM26

CFG[11]

AN28

CFG[12]

AN31

CFG[13]

AN26

CFG[14]

AM27

CFG[15]

AK31

CFG[16]

AN29

CFG[17]

AJ31

VAXG_VAL_SENSE

AH31

VSSAXG_VAL_SENSE

AJ33

VCC_VAL_SENSE

AH33

VSS_VAL_SENSE

AJ26

RSVD5

F25

RSVD8

F24

RSVD9

F23

RSVD10

D24

RSVD11

G25

RSVD12

G24

RSVD13

E23

RSVD14

D23

RSVD15

C30

RSVD16

A31

RSVD17

B30

RSVD18

B29

RSVD19

D30

RSVD20

B31

RSVD21

A30

RSVD22

C29

RSVD23

J20

RSVD24

B18

RSVD25

J15

RSVD27

CFG

VCC_DIE_SENSE VSS_DIE_SENSE

RESERVED

RSVD_NCTF10

RSVD_NCTF11 RSVD_NCTF12 RSVD_NCTF13

Interl request AH26 short GND check on EVT phase

AH27 AH26

L7

RSVD28

AG7

RSVD29

AE7

RSVD30

AK2

RSVD31

W8

RSVD32

AT26

RSVD33

AM33

RSVD34

AJ27

RSVD35

T8

RSVD37

J16

RSVD38

H16

RSVD39

G16

RSVD40

RSVD51 RSVD52

BCLK_ITP

BCLK_ITP#

KEY

AR35 AT34 AT33 AP35 AR34

B34 A33 A34 B35 C35

AJ32 AK32

AN35 AM35

AT2 AT1 AR1

B1

RSVD_NCTF1 RSVD_NCTF2 RSVD_NCTF3 RSVD_NCTF4 RSVD_NCTF5

RSVD_NCTF6 RSVD_NCTF7 RSVD_NCTF8 RSVD_NCTF9

PEG Static Lane Reversal - CFG2 is for the 16x

T13PAD T13PAD

CFG2

1: Normal Operation; Lane # definition matches socket pin map definition

0:Lane Reversed

*

CFG4

12

R42

@ R42

@

1K_0402_1%

Display Port Presence Strap

CFG4

1 : Disabled; No Physical Display Port attached to Embedded Display Port

*

0 : Enabled; An external Display Port device is connected to the Embedded Display Port

PCIE Port Bifurcation Straps

11: (Default) x16 - Device 1 functions 1 and 2 disabled

CFG[6:5]

10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled

*

01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)

00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

TYCO_2013620-2_IVY BRIDGE

ME@

PEG DEFER TRAINING

1: (Default) PEG Train immediately following xxRESETB

CFG7

de assertion

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

0: PEG Wait for BIOS for training

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PROCESSOR(4/7) RSVD,CFG

LA-9632P

1

8 60Wednesday, February 27, 2013

1.0

of

5

POWER

+VCC_CORE

JCPU1F

POWER

QC=94A DC=53A

D D

C C

B B

A A

AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26

AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27

AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26

VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

CORE SUPPLY

4

8.5A

AH13

VCCIO1

AH10

VCCIO2

AG10

VCCIO3

AC10

VCCIO4

Y10

VCCIO5

U10

VCCIO6

P10

VCCIO7

L10

VCCIO8

J14

VCCIO9

J13

VCCIO10

J12

VCCIO11

J11

VCCIO12

H14

VCCIO13

H12

VCCIO14

H11

VCCIO15

G14

VCCIO16

G13

VCCIO17

G12

VCCIO18

F14

VCCIO19

F13

VCCIO20

F12

VCCIO21

F11

VCCIO22

E14

VCCIO23

E12

VCCIO24

E11

VCCIO25

D14

VCCIO26

D13

VCCIO27

D12

VCCIO28

D11

VCCIO29

C14

VCCIO30

C13

VCCIO31 VCCIO32 VCCIO33 VCCIO34 VCCIO35 VCCIO36 VCCIO37 VCCIO38 VCCIO39

VCCIO40

VIDALERT#

VIDSCLK

VIDSOUT

C12 C11 B14 B12 A14 A13 A12 A11

J23

AJ29 AJ30 AJ28

AJ35 AJ34

B10 A10

PEG AND DDR

VCC_SENSE VSS_SENSE

VCCIO_SENSE

VSS_SENSE_VCCIO

SENSE LINES SVID

3

+V1.05S_VCCP

12

R46

R46 75_0402_5%

75_0402_5%

H_CPU_SVIDALRT#

1 2

R47 43_0402_5%R47 43_0402_5%

R50 130_0402_5%R50 130_0402_5%

12

+V1.05S_VCCP

VR_SVID_CL K

0.

series-res istors clo se to VR

VR_SVID_ALRT# <43> VR_SVID_CLK <43> VR_SVID_DAT <43>

1uF on power side

VCC_SENCE 100ohm +-1% pull-up to VCC near processor

Trace Impedance =27-33 ohm Trace Length Matc < 25 mils

R79

10_0402_1%

VCCIO_SENSE <42>

+V1.05S_VCCP

12

1 2

VSSIO_SENSEVSSIO_SENSE_L

R74

10_0402_1%

R74 & R79 put together

VSSIO_SENSE_L <42>

VS

S_SENCE 100ohm +-1% pull-down to GND near processor

2

+VCC_CORE

12

R51

R51 100_0402_1%

100_0402_1%

VCCSENSE <43>

R54

R54 100_0402_1%

100_0402_1%

VSSSENSE <43>

12

1

Security Classification

TYCO_2013620-2_IVY BRIDGE

ME@

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

2011/06/15 2012/07/11

3

Compal Secret Data

Deciphered Date

Title

PROCESSOR(5/7) PWR,BYPASS

Size Document Number Rev

Custom

LA-9632P

Date: Sheet

2

Date: Sheet

9 60Wednesday, February 27, 2013

1

1.0

of

5

4

3

2

1

+1.5V +1.5V_CPU_VDDQ

+VREF_DQ_DIMMA

SUSP<35>

D D

C C

B B

+1.8VS

R69 0_0805_5%

1 2

@

1

2

C130

10U_0603_6.3V6M

C130

10U_0603_6.3V6M

C345

22U_0805_6.3V6M@C345

22U_0805_6.3V6M

1

@

2

B+

12

13

D

2

G

S

+VCC_GFXCORE_AXG

1.5A

+1.8VS_VCCPLL

C132

1U_0402_6.3V6K

C132

1U_0402_6.3V6K

1

2

DMN3030LSS-13_SOP8L-8

8 7

5

R56

R56 82K_0402_5%

82K_0402_5%

RUN_ON_CPU1.5VS3

Q4

Q4 2N7002H_SOT23-3

2N7002H_SOT23-3

AT24 AT23 AT21 AT20 AT18 AT17 AR24 AR23 AR21 AR20 AR18 AR17 AP24 AP23 AP21 AP20 AP18 AP17 AN24 AN23 AN21 AN20 AN18

AN17 AM24 AM23 AM21 AM20 AM18 AM17

AL24

AL23

AL21

AL20

AL18

AL17

AK24

AK23

AK21

AK20

AK18

AK17

AJ24

AJ23

AJ21

AJ20

AJ18

AJ17 AH24 AH23 AH21 AH20 AH18 AH17

B6 A6 A2

U3

JCPU1G

VAXG1 VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36 VAXG37 VAXG38 VAXG39 VAXG40 VAXG41 VAXG42 VAXG43 VAXG44 VAXG45 VAXG46 VAXG47 VAXG48 VAXG49 VAXG50 VAXG51 VAXG52 VAXG53 VAXG54

VCCPLL1 VCCPLL2 VCCPLL3

TYCO_2013620-2_IVY BRIDGE

ME@

4

1 2

12

R57

R57 330K_0402_5%

330K_0402_5%

@

1 2 36

R885

15K_0402_1%

AP4800 Id=9.6A

R02

1

C97

0.047U_0603_25V7K

2

POWER

VSSAXG_SENSE

SENSE

LINES

SENSE

LINES

SA_DIMM_VREFDQ SB_DIMM_VREFDQ

VREFMISC

GRAPHICS

DDR3 -1.5V RAILS

SA RAIL

VCCSA_SENSE

1.8V RAIL

VAXG_SENSE

SM_VREF

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8

VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15

VCCSA1 VCCSA2 VCCSA3 VCCSA4 VCCSA5 VCCSA6 VCCSA7 VCCSA8

VCCSA_VID[0] VCCSA_VID[1]

VCCIO_SEL

+VCC_GFXCORE_AXG

12

AK35 AK34

12

AL1

+V_SM_VREF_CNT

B4

+V_DDR_REFA_R

D1

+V_DDR_REFB_R

AF7 AF4 AF1 AC7 AC4 AC1 Y7 Y4 Y1 U7 U4 U1 P7 P4 P1

M27

+VCCSA

M26 L26 J26 J25 J24 H26 H25

H23

C22 C24

A19

R616

R616 10_0402_1%

10_0402_1%

R626

R626 10_0402_1%

10_0402_1%

10U_0603_6.3V6M

1

2

10U_0603_6.3V6M

1

2

H_VCCSA_VID0 <41> H_VCCSA_VID1 <41>

C117

10U_0603_6.3V6M

C124

1

2

+VREF_DQ_DIMMB

DRAMRST_CNTRL_PCH

LBSS138LT1G_SOT-23-3

M3 Circuit (Processor Generated SO-DIMM VREF_DQ)

VCC_AXG_SENSE <43>

VSS_AXG_SENSE <43>

+V_SM_VREF should

ave 20 mil trace width

h

C98

.1U_0402_16V7K

C119

10U_0603_6.3V6M

C119

10U_0603_6.3V6M

C120

10U_0603_6.3V6M@C120

10U_0603_6.3V6M

1

@

2

+VCCSA

C125

C126

10U_0603_6.3V6M

C126

10U_0603_6.3V6M

1

2

+1.5V_CPU_VDDQ

12

1

2

+1.5V_CPU_VDDQ

1

C122

10U_0603_6.3V6M

C122

10U_0603_6.3V6M

1

+

2

1

+

C128

@+C128

@

330U_D2_2.5VY_R9M

2

+VCCSA_SENSE <41>

2

G

Q9

R67

R67 1K_0402_1%

1K_0402_1%

R78

R78 1K_0402_1%

1K_0402_1%

C123

C123 220U_6.3V_M

220U_6.3V_M

13

D

S

Q6

13

D

LBSS138LT1G_SOT-23-3

2

G

S

+V_DDR_REFA_R

+V_DDR_REFB_R

DRAMRST_CNTRL_PCH <15,7>

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07/11

Compal Secret Data

IVY Bridge drives VCCIO_SEL low VCCP_PWRCTRL:0 Sandy Bridge is NC for A19 VCCP_PWRCTRL:1

Deciphered Date

2

Title

PROCESSOR(6/7) PWR

Size Document Number Rev

Custom

LA-9632P

Date: Sheet of

10 60Wednesday, February 27, 2013

1

1.0

5

JCPU1H

AT35 AT32 AT29 AT27 AT25 AT22 AT19 AT16 AT13

D D

C C

B B

A A

5

AT10

AT7 AT4

AT3 AR25 AR22 AR19 AR16 AR13 AR10

AR7

AR4

AR2 AP34 AP31 AP28 AP25 AP22 AP19 AP16 AP13 AP10

AP7

AP4

AP1 AN30 AN27 AN25 AN22 AN19 AN16 AN13 AN10

AN7

AN4

AM29 AM25 AM22 AM19 AM16 AM13 AM10

AM7 AM4 AM3 AM2

AM1 AL34 AL31 AL28 AL25 AL22 AL19 AL16 AL13 AL10

AL7 AL4

AL2 AK33 AK30 AK27 AK25 AK22 AK19 AK16 AK13 AK10

AK7

AK4

AJ25

TYCO_2013620-2_IVY BRIDGE

ME@

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80

4

AJ22

VSS81

AJ19

VSS82

AJ16

VSS83

AJ13

VSS84

AJ10

VSS85

AJ7

VSS86

AJ4

VSS87

AJ3

VSS88

AJ2

VSS89

AJ1

VSS90

AH35

VSS91

AH34

VSS92

AH32

VSS93

AH30

VSS94

AH29

VSS95

AH28

VSS96

AH25

VSS98

AH22

VSS99

AH19

VSS100

AH16

VSS101

AH7

VSS102

AH4

VSS103

AG9

VSS104

AG8

VSS105

AG4

VSS106

AF6

VSS107

AF5

VSS108

AF3

VSS109

AF2

VSS110

AE35

VSS111

AE34

VSS112

AE33

VSS113

AE32

VSS114

AE31

VSS115

AE30

VSS116

AE29

VSS117

AE28

VSS118

VSS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160

AE27 AE26 AE9 AD7 AC9 AC8 AC6 AC5 AC3 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 Y9 Y8 Y6 Y5 Y3 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 U9 U8 U6 U5 U3 U2

3

JCPU1I

T35

VSS161

T34

VSS162

T33

VSS163

T32

VSS164

T31

VSS165

T30

VSS166

T29

VSS167

T28

VSS168

T27

VSS169

T26

VSS170

P9

VSS171

P8

VSS172

P6

VSS173

P5

VSS174

P3

VSS175

P2

VSS176

N35

VSS177

N34

VSS178

N33

VSS179

N32

VSS180

N31

VSS181

N30

VSS182

N29

VSS183

N28

VSS184

N27

VSS185

N26

VSS186

M34

VSS187

L33

VSS188

L30

VSS189

L27

VSS190

L9

VSS191

L8

VSS192

L6

VSS193

L5

VSS194

L4

VSS195

L3

VSS196

L2

VSS197

L1

VSS198

K35

VSS199

K32

VSS200

K29

VSS201

K26

VSS202

J34

VSS203

J31

VSS204

H33

VSS205

H30

VSS206

H27

VSS207

H24

VSS208

H21

VSS209

H18

VSS210

H15

VSS211

H13

VSS212

H10

VSS213

H9

VSS214

H8

VSS215

H7

VSS216

H6

VSS217

H5

VSS218

H4

VSS219

H3

VSS220

H2

VSS221

H1

VSS222

G35

VSS223

G32

VSS224

G29

VSS225

G26

VSS226

G23

VSS227

G20

VSS228

G17

VSS229

G11

VSS230

F34

VSS231

F31

VSS232

F29

VSS233

TYCO_2013620-2_IVY BRIDGE

ME@

Compal Secret Data

2011/06/15 2012/07/11

Compal Secret Data

3

Deciphered Date

VSS

2

VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285

2

F22 F19 E30 E27 E24 E21 E18 E15 E13 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 D35 D32 D29 D26 D20 D17 C34 C31 C28 C27 C25 C23 C10 C1 B22 B19 B17 B15 B13 B11 B9 B8 B7 B5 B3 B2 A35 A32 A29 A26 A23 A20 A3

1

Compal Electronics, Inc.

Title

PROCESSOR(7/7) VSS

Size Document Number Rev

Custom

LA-9632P

Date: Sheet of

11 60Wednesday, February 27, 2013

1

1.0

5

+VREF_DQ_DIMMA

.1U_0402_16V7K

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z C133

C133

C134

1

2

D D

C C

B B

+3VS

A A

2

@

DDR_CKE0_DIMMA<7>

DDR_A_BS2<7>

M_CLK_DDR0<7> M_CLK_DDR#0<7>

DDR_A_BS0<7>

DDR_A_WE#<7> DDR_A_CAS#<7>

DDR_CS1_DIMMA#<7>

2.2U_0603_6.3V4Z

.1U_0402_16V7K

C155

1

2

@

5 4

+1.5V





DDR3 SO-DIMM A

JDIMM1

VREF_DQ1VSS1

3

VSS2

DDR_A_D0 DDR_A_D1

DDR_A_DM0

DDR_A_D2 DDR_A_D3

DDR_A_D8 DDR_A_D9

DDR_A_DQS#1 DDR_A_DQS1

DDR_A_D10 DDR_A_D11

DDR_A_D16 DDR_A_D17

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D18 DDR_A_D19

DDR_A_D24 DDR_A_D25

DDR_A_DM3

DDR_A_D26 DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS2

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8 DDR_A_MA5

DDR_A_MA3 DDR_A_MA1

M_CLK_DDR0 M_CLK_DDR#0

DDR_A_MA10 DDR_A_BS0

DDR_A_WE# DDR_A_CAS# M_ODT0

DDR_A_MA13 DDR_CS1_DIMMA#

DDR_A_D32 DDR_A_D33

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_DM5

DDR_A_D42 DDR_A_D43

DDR_A_D48 DDR_A_D49

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D50 DDR_A_D51

DDR_A_D56 DDR_A_D57

DDR_A_DM7

DDR_A_D58 DDR_A_D59

C156

5

DQ0

7

DQ1 VSS49DQS#0

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET# VSS1131VSS12

33

DQ10

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

LCN_DAN06-K4806-0103

ME

@

VSS3

DQS0 VSS6

VSS8 DQ12 DQ13

VSS10

DM1

DQ14 DQ15

DQ20 DQ21

DM2

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

DM4

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

DM6

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

SDA

VTT2

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

DDR_A_D4 DDR_A_D5

DDR_A_DQS#0 DDR_A_DQS0

DDR_A_D6 DDR_A_D7

DDR_A_D12 DDR_A_D13

DDR_A_DM1 DDR3_DRAMRST#

DDR_A_D14 DDR_A_D15

DDR_A_D20 DDR_A_D21

DDR_A_DM2

DDR_A_D22 DDR_A_D23

DDR_A_D28 DDR_A_D29

DDR_A_DQS#3 DDR_A_DQS3

DDR_A_D30 DDR_A_D31

DDR_CKE1_DIMMA

DDR_A_MA15 DDR_A_MA14

DDR_A_MA11 DDR_A_MA7

DDR_A_MA6 DDR_A_MA4

DDR_A_MA2 DDR_A_MA0

M_CLK_DDR1 M_CLK_DDR#1

DDR_A_BS1 DDR_A_RAS#

DDR_CS0_DIMMA#

M_ODT1

DDR_A_D36 DDR_A_D37

DDR_A_DM4

DDR_A_D38 DDR_A_D39

DDR_A_D44 DDR_A_D45

DDR_A_DQS#5 DDR_A_DQS5

DDR_A_D46 DDR_A_D47

DDR_A_D52 DDR_A_D53

DDR_A_DM6

DDR_A_D54 DDR_A_D55

DDR_A_D60 DDR_A_D61

DDR_A_DQS#7 DDR_A_DQS7

DDR_A_D62 DDR_A_D63

SMB_DATA_S3 SMB_CLK_S3

DQ4 DQ5

DQ6 DQ7

A15 A14

A11

A7

A6 A4

A2 A0

CK1

BA1

S0#

NC2

SCL

G2

+0.75VS





DDR_A_D[0..63]<7>

DDR_A_DQS[0..7]<7>

DDR_A_DQS#[0..7]<7>

DDR_A_MA[0..15]<7>

+VREF_DQ_DIMMA

1

2

+VREF_CA

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z C136

C136

+VREF_DQ_DIMMB

DDR3_DRAMRST# <13,7>

DDR_CKE1_DIMMA <7>

M_CLK_DDR1 <7> M_CLK_DDR#1 <7>

DDR_A_BS1 <7> DDR_A_RAS# <7>

DDR_CS0_DIMMA# <7> M_ODT0 <7>

M_ODT1 <7>

.1U_0402_16V7K

C135

1

2

@

VDDQ(1.5V) =

3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)

6*0603 10uf (PER CONNECTOR)

VTT(0.75V) =

3*0805 10uf

4*0402 1uf

VREF =

1*0402 0.1uf

1*0402 2.2uf

VDDSPD (3.3V)=

1*0402 0.1uf 1*0402 2.2uf

SMB_DATA_S3 <13,15,26> SMB_CLK_S3 <13,15,26>

+VREF_CA

+VREF_CB

+VREF_CA

3

RP15

1K_0804_8P4R_1%

RP16

1K_0804_8P4R_1%

+1.5V

18 27 36 45

+1.5V

18 27 36 45

2

(220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y00)OSCAN

Layout Note: Place near DIMM

+1.5V

C139

10U_0603_6.3V6M

C139

10U_0603_6.3V6M

1

2

Layout Note: Place near DIMM

+0.75VS

C150

1U_0402_6.3V6K

C150

1U_0402_6.3V6K

C152

1U_0402_6.3V6K

C152

1U_0402_6.3V6K

1

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07/11

Compal Secret Data

(10uF_0603_6.3V)*8

(0.1uF_402_10V)*4

C140

10U_0603_6.3V6M

C140

10U_0603_6.3V6M

C141

10U_0603_6.3V6M

C141

10U_0603_6.3V6M

1

2

7/28 Update connect GND directly

DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7

Deciphered Date

2

C143

10U_0603_6.3V6M

C143

10U_0603_6.3V6M

C142

10U_0603_6.3V6M

C142

10U_0603_6.3V6M

1

2

Layout Note: Place near DIMM

1

C146

.1U_0402_16V7K

C146

.1U_0402_16V7K

C147

.1U_0402_16V7K

C147

C144

10U_0603_6.3V6M

C144

10U_0603_6.3V6M

C145

.1U_0402_16V7K@C145

.1U_0402_16V7K

1

2

@

1

2

.1U_0402_16V7K

C148

.1U_0402_16V7K

C148

.1U_0402_16V7K

1

2

Title

Size Document Number Rev

Custom

Date: Sheet

Date: Sheet of

1

+

C149

@+C149

@

220U_6.3V_M

2

Compal Electronics, Inc.

DDRIII-SODIMM SLOT1

LA-9632P

1

of

12 60Wednesday, February 27, 2013

1.0

5

4

3

2

1

+VREF_DQ_DIMMB

DDR_B_D0

1

C157

2

DDR_B_D1

DDR_B_DM0

DDR_B_D2 DDR_B_D3

DDR_B_D8 DDR_B_D9

DDR_B_DQS#1 DDR_B_DQS1

DDR_B_D10 DDR_B_D11

DDR_B_D16 DDR_B_D17

DDR_B_DQS#2 DDR_B_DQS2

DDR_B_D18 DDR_B_D19

DDR_B_D24 DDR_B_D25

DDR_B_DM3

DDR_B_D26 DDR_B_D27

DDR_CKE2_DIMMB

DDR_B_BS2

DDR_B_MA12 DDR_B_MA9

DDR_B_MA8 DDR_B_MA5

DDR_B_MA3 DDR_B_MA1

M_CLK_DDR2 M_CLK_DDR#2

DDR_B_MA10 DDR_B_BS0

DDR_B_WE# DDR_B_CAS#

DDR_B_MA13 DDR_CS3_DIMMB#

DDR_B_D32 DDR_B_D33

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D34 DDR_B_D35

DDR_B_D40 DDR_B_D41

DDR_B_DM5

DDR_B_D42 DDR_B_D43

DDR_B_D48 DDR_B_D49

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D50 DDR_B_D51

DDR_B_D56 DDR_B_D57

DDR_B_DM7

DDR_B_D58 DDR_B_D59

1 2

R97 10K_0402_5%R97 10K_0402_5%

2.2U_0603_6.3V4Z

.1U_0402_16V7K

1

C158

D D

For Arranale only +VREF_DQ_DIMMB

upply from a external 1.5V voltage divide

s circuit.

C C

B B

A A

+3VS

1

@

2

C158

2

@

DDR_CKE2_DIMMB<7>

DDR_B_BS2<7>

M_CLK_DDR2<7> M_CLK_DDR#2<7>

DDR_B_BS0<7>

DDR_B_WE#<7> DDR_B_CAS#<7>

DDR_CS3_DIMMB#<7>

2.2U_0603_6.3V4Z

.1U_0402_16V7K

C177

C178

+3VS

1

2

5





+1.5V +1.5V

JDIMM2

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET# VSS1131VSS12

33

DQ10

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16

45

DQS#2 DQS247VSS17

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

TYCO_2-2013287-1

ME@

DQ4 DQ5

VSS3

DQS#0

DQS0 VSS6

DQ6

DQ7 VSS8 DQ12 DQ13

VSS10

DM1

DQ14 DQ15

DQ20 DQ21

DM2

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

CK1

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

DM4

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35 DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

DM6

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47 DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

SDA

SCL

VTT2

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78

A15

80

A14

82 84

A11

86

A7

88 90

A6

92

A4

94 96

A2

98

A0

100 102 104 106 108

BA1

110 112 114

S0#

116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

G2

4

DDR_B_D4 DDR_B_D5

DDR_B_DQS#0 DDR_B_DQS0

DDR_B_D6 DDR_B_D7

DDR_B_D12 DDR_B_D13

DDR_B_DM1 DDR3_DRAMRST#

DDR_B_D14 DDR_B_D15

DDR_B_D20 DDR_B_D21

DDR_B_DM2

DDR_B_D22 DDR_B_D23

DDR_B_D28 DDR_B_D29

DDR_B_DQS#3 DDR_B_DQS3

DDR_B_D30 DDR_B_D31

DDR_CKE3_DIMMB

DDR_B_MA15 DDR_B_MA14

DDR_B_MA11 DDR_B_MA7

DDR_B_MA6 DDR_B_MA4

DDR_B_MA2 DDR_B_MA0

M_CLK_DDR3 M_CLK_DDR#3

DDR_B_BS1 DDR_B_RAS#

DDR_CS2_DIMMB# M_ODT2

M_ODT3

DDR_B_D36 DDR_B_D37

DDR_B_DM4

DDR_B_D38 DDR_B_D39

DDR_B_D44 DDR_B_D45

DDR_B_DQS#5 DDR_B_DQS5

DDR_B_D46 DDR_B_D47

DDR_B_D52 DDR_B_D53

DDR_B_DM6

DDR_B_D54 DDR_B_D55

DDR_B_D60 DDR_B_D61

DDR_B_DQS#7 DDR_B_DQS7

DDR_B_D62 DDR_B_D63

SMB_DATA_S3 SMB_CLK_S3





DDR_B_D[0..63]<7>

DDR_B_DQS[0..7]<7>

DDR_B_DQS#[0..7]<7>

DDR_B_MA[0..15]<7>

DDR3_DRAMRST# <12,7>

DDR_CKE3_DIMMB <7>

M_CLK_DDR3 <7> M_CLK_DDR#3 <7>

DDR_B_BS1 <7> DDR_B_RAS# <7>

DDR_CS2_DIMMB# <7> M_ODT2 <7>

M_ODT3 <7>

1

2

.1U_0402_16V7K

C159

1

2

+VREF_CB

2.2U_0603_6.3V4Z

C160

@

+VREF_CB

VDDQ(1.5V) =

3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)

6*0603 10uf (PER CONNECTOR)

VTT(0.75V) =

3*0805 10uf

1*0402 0.1uf

4*0402 1uf

1*0402 2.2uf

VDDSPD (3.3V)=

1*0402 2.2uf 1*0402 0.1uf

SMB_DATA_S3 <12,15,26> SMB_CLK_S3 <12,15,26> +0.75VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Layout Note: Place near DIMM

C163

1

2

Layout Note: Place near DIMM

+0.75VS

1U_0402_6.3V6K

C174

1U_0402_6.3V6K

C174

1U_0402_6.3V6K

1

2

Compal Secret Data

2011/06/15 2012/07/11

Compal Secret Data

(10uF_0603_6.3V)*8

(0.1uF_402_10V)*4

+1.5V

10U_0603_6.3V6M

C164

C165

1

2

C176

1

2

Deciphered Date

2

10U_0603_6.3V6M

C166

1

2

DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7

Layout Note: Place near DIMM

10U_0603_6.3V6M

C168

C167

1

2

.1U_0402_16V7K

C170

C169

@

1

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

.1U_0402_16V7K

C171

C172

1

2

DDRIII-SODIMM SLOT2

LA-9632P

1

13 60Wednesday, February 27, 2013

1.0

5

=20milsW =20mils

W

+RTCBAT T+RTCVCC

@

R99

1K_0402_5%

1 2

1

C179

C179 1U_0603_1 0V4Z

1U_0603_1 0V4Z

2

D D

R104

0_0402_5%

C180

18P_0402_5 0V8J

@

4

1 2

R98 10M _0402_5%R98 10M _0402_5%

Y1

1 2

1

2

PCH_RTC X1

PCH_RTC X2

32.768KHZ_ 12.5PF_CM31532 768DZFT

1

C181

C181 18P_0402_5 0V8J

18P_0402_5 0V8J

2

3

CLRP2

Shunt

Open

CLRP3

CMOS setting

Clear CMOS

Keep CMOS

TPM setting

2

1

Clear ME RTC RegistersShunt

Open

Keep ME RTC Registers

CMOS

CLRP2

SHORT PADS@CLRP2

+RTCVCC

1 2

R101 1M_0402_ 5%R101 1M_0402_5%

1 2

R102 330K_040 2_5%R1 02 330K_0402_5%

INTVRMEN

󶁪Integrated VRM enable

H󶁪

󶁪

*

L󶁪󶁪󶁪󶁪Integrated VRM disable

SM_INTRU DER#

PCH_INTV RMEN

(INTVRMEN should always be pull high.)

+3VS

1 2

R105 1K_0402_ 5%@R 105 1K_0402_5%@

H

IGH= Enable ( No Reboot )

LOW= Disable (Default)

*

C C

+3V_PCH

R106 1K_0402_ 5%@R106 1K_0402_5%@

Low = Disabled (Default)

*

High = Enabled [Flash Descriptor Security Overide]

+3V_PCH

R108 1K_0402_5%R108 1K_0402_5%

This signal has a weak internal pull-down On Die PLL VR is supplied by

1.5V when smaple d high

1.8V when sample d low

*

Needs to be pull ed High for Chie f River platfrom

HDA_BITC LK_AUDIO<31>

HDA_SYNC_ AUDIO<31 >

B B

HDA_RST _AUDIO#< 31>

HDA_SDO UT_AUDIO<31>

12

33_0804_8P 4R_5%

Fo

r EMI

RP12

HDA_SPK R

ME_FLAS H

HDA_SYNC

18 27 36 45

HDA_BIT_ CLK

HDA_SYNC_ R

HDA_RST #

ME_FLAS H

DPDG1.1

+RTCVCC

C183

1U_0603_1 0V4Z

1 2

R103 20K_0402_5 %R1 03 20K_04 02_5%

1 2

R100 20K_0402_5 %R1 00 20K_04 02_5%

C182

1U_0603_1 0V4Z

HDA_SPK R<31>

HDA_SDIN 0<31>

ME_FLASH<32>

+5VS

G

2

13

D

S

D

S

R878

1M_0402_5 %

1 2

check with vender

Del Q10 check with codec VDDIO using 3VALW

33_0402_5%

22P_0402_5 0V8J

SHORT PADS

@

1

12

2

CLRP3

SHORT PADS@CLRP3

SHORT PADS

1

12

@

2

Q10

Q10 LBSS138LT 1G_SOT-23-3

LBSS138LT 1G_SOT-23-3

HDA_SYNC

SPI_CLK_P CH_R

12

R124

@

C190

@

PCH_RTC X1

PCH_RTC X2

PCH_RTC RST#

PCH_SRT CRST#

SM_INTRU DER#

PCH_INTV RMEN

HDA_BIT_ CLK

HDA_SYNC

HDA_SPK R

HDA_RST #

HDA_SDIN 0

ME_FLAS H

PCH_GPIO33

PCH_GPIO13

PCH_JTA G_TCK

PCH_JTA G_TMS

PCH_JTA G_TDI

PCH_JTA G_TDO

SPI_CLK_P CH_R

SPI_SB_C S0#

SPI_SI

SPI_SO_R

For EMI

R124;c190 close to U4.T3 pin

A A

U4A

A20

RTCX1

C20

RTCX2

D20

RTCRST #

G22

SRTCRS T#

K22

INTRUDE R#

C17

INTVRME N

N34

HDA_BCL K

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST #

E34

HDA_SDIN 0

G34

HDA_SDIN 1

C34

HDA_SDIN 2

A34

HDA_SDIN 3

A36

HDA_SDO

C36

HDA_DOC K_EN# / GPIO33

N32

HDA_DOC K_RST# / GPIO13

J3

JTAG_TCK

H7

JTAG_TMS

K5

JTAG_TDI

H1

JTAG_TDO

T3

SPI_CLK

Y14

SPI_CS0#

T1

SPI_CS1#

V4

SPI_MOSI

U3

SPI_MISO

PANTHE R-POINT_FCBGA98 9

HM76@

HM76@ SA

SA

00005FH70

S IC BD82HM 76 SLJ8E C1 BGA 9 89P PCH C38!

U4

HM70@

U4

HM70@

SA00005M Q80

SA00005M Q80 IC BD82HM 70 SJTNV C1 BGA 98 9P PCH C38!

IC BD82HM 70 SJTNV C1 BGA 98 9P PCH C38!

U4

NM70@

U4

NM70@

SA00005W U60

SA00005W U60 S IC BD82NM 70 SLJTA C1 BGA 9 89P PCH C38!

S IC BD82NM 70 SLJTA C1 BGA 9 89P PCH C38!

RTCIHDA

JTAG

SPI

FWH0 / LA D0 FWH1 / LA D1 FWH2 / LA D2 FWH3 / LA D3

LPC

FWH4 / LF RAME#

LDRQ0#

LDRQ1# / GPIO23

SERIRQ

SATA0RX N SATA0RX P SATA0TX N

SATA0TX P

SATA1RX N SATA1RX P

SATA 6G

SATA1TX N

SATA1TX P

SATA2RX N SATA2RX P SATA2TX N

SATA2TX P

SATA3RX N SATA3RX P SATA3TX N

SATA3TX P

SATA4RX N SATA4RX P SATA4TX N

SATA

SATA4TX P

SATA5RX N SATA5RX P SATA5TX N

SATA5TX P

SATAICOM PO

SATAICOM PI

SATA3RC OMPO

SATA3COM PI

SATA3RB IAS

SATALED #

SATA0GP / GP IO21

SATA1GP / GP IO19

PCH_GPIO16<19>

C38

LPC_AD0

A38

LPC_AD1

B37

LPC_AD2

C37

LPC_AD3

D36

LPC_FRA ME#

E36 K36

V5

SERIRQSERIRQ

AM3

SATA_DT X_C_IRX_N0

AM1

SATA_DT X_C_IRX_P0

AP7

SATA_ITX_ C_DRX_N0

AP5

SATA_ITX_ C_DRX_P0

AM10 AM8 AP11 AP10

AD7

SATA_DT X_C_IRX_N2

AD5

SATA_DT X_C_IRX_P2

AH5

SATA_ITX_ C_DRX_N2

AH4

SATA_ITX_ C_DRX_P2

AB8 AB10 AF3 AF1

Y7 Y5 AD3 AD1

Y3 Y1 AB3 AB1

Y11

Y10

AB12

AB13

AH1

RBIAS_SA TA3

P3

SATALED #

V14

PCH_GPIO21

P1

BBS_BIT0_ R

SATA_COM P

SATA3_C OMP

BBS_BIT0_ R SATALED # PCH_GPIO16 SERIRQ

+3V_ROM

R127

R129

LPC_AD0 <32> LPC_AD1 <32> LPC_AD2 <32> LPC_AD3 <32>

LPC_FRA ME# <32>

SERIRQ <32>

R111

37.4_0402_1%

1 2

R113

49.9_0402_1%

1 2

R115

750_0402_1 %

1 2

3.3K_0402_5 %

1 2

SPI_HOLD#

3.3K_0402_5 %

RP17

18 27 36 45

10K_0804_8 P4R_5%

EC

and Mini card debug port

SATA_DT X_C_IRX_N0 <30> SATA_DT X_C_IRX_P0 < 30> SATA_ITX_ C_DRX_N0 <30> SATA_ITX_ C_DRX_P0 < 30>

SATA_DT X_C_IRX_N2 <30> SATA_DT X_C_IRX_P2 < 30> SATA_ITX_ C_DRX_N2 <30> SATA_ITX_ C_DRX_P2 <30>

+V1.05S_VCCP

SPI_WP #

+3VS

SPI_SB_C S0#

HDD

ODD

1 2

R131

R131 0_0402_5%

0_0402_5%

@

For EMI

SPI_SO_R SPI_SI SPI_CLK_P CH_R SPI_SB_C S0#

1 2 3

SPI_WP #

4

Share ROM

@

RP2

1 8 2 7 3 6 4 5

0_0804_8P4 R_5%

EC_SPI_S O EC_SPI_S I EC_SPI_C LK EC_SPI_C S#

EC_SPI_S O <32> EC_SPI_S I <32> EC_SPI_C LK <32> EC_SPI_C S# <32>

Share ROM

U5

CS# SO WP# GND

W25Q64F VSSIQ_SO8

SA000039A 30

SA000039A 30 S IC FL 64M W 25Q64FVSSIQ SOIC 8P SPI ROM

S IC FL 64M W 25Q64FVSSIQ SOIC 8P SPI ROM

VCC

HOLD#

SCLK

8 7

SPI_HOLD#SPI_SO_R SPI_SO_L

6 5

SI

1 2

For EMI

+3V_ROM

R133

R133 0_0402_5%

0_0402_5%

@

SPI_CLK_P CH_RSPI_CLK_1 SPI_SI

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PCH (1/9) SATA,HDA,SPI, LPC, XDP

Size Document Number Rev

Custom

LA-9632P

Date: Sheet

2

Date: Sheet

14 60W ednesday, March 06, 2013

1

1.0

of

5

LAN

WLAN

D D

C C

LAN

WLAN

B B

PCIE_PRX _DTX_N1<27>

PCIE_PRX _DTX_P1<27> PCIE_PTX _C_DRX_N1<27> PCIE_PTX _C_DRX_P1<27>

PCIE_PRX _DTX_N2<26>

PCIE_PRX _DTX_P2<26> PCIE_PTX _C_DRX_N2<26> PCIE_PTX _C_DRX_P2<26>

CLK_PCIE _LAN#< 27> CLK_PCIE _LAN<27>

CLKREQ_L AN#<27>

CLK_PCIE _WLAN1#<26> CLK_PCIE _WLAN1<26>

CLKREQ_W LAN#<26>

+3V_PCH

+3VS

1 2

C192 .1U_0402_ 16V7KC1 92 .1U_0402_16V7K

1 2

C193 .1U_0402_ 16V7KC1 93 .1U_0402_16V7K

1 2

C194 .1U_0402_ 16V7KC1 94 .1U_0402_16V7K

1 2

C195 .1U_0402_ 16V7KC1 95 .1U_0402_16V7K

1 2

R153 0_0402_ 5%@R153 0_0402_ 5%@

1 2

R154 0_0402_ 5%@R154 0_0402_ 5%@

R152 10K_0402_5 %R152 10K_0402_5 %

1 2

R156 0_0402_ 5%@R156 0_0402_ 5%@

1 2

R165 0_0402_ 5%@R165 0_0402_ 5%@

R158 10K_0402 _5%R158 10K_0402 _5%

12

For EMI

4

PCIE_PRX _DTX_N1 PCIE_PRX _DTX_P1 PCIE_PTX _DRX_N1 PCIE_PTX _DRX_P1

PCIE_PRX _DTX_N2 PCIE_PRX _DTX_P2 PCIE_PTX _DRX_N2 PCIE_PTX _DRX_P2

CLK_PCIE _LAN#_R CLK_PCIE _LAN_R

CLK_PCIE _WLAN1#_R CLK_PCIE _WLAN1_R

PCH_GPIO20

PCH_GPIO25

PCH_GPIO26

PCH_GPIO44

PCH_GPIO56

PCH_GPIO45

PCH_GPIO46

PCIE_CLK_8N PCIE_CLK_8P

U4B

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40

CLKOUT_P CIE0N

Y39

CLKOUT_P CIE0P

J2

PCIECLKR Q0# / GPIO73

AB49

CLKOUT_P CIE1N

AB47

CLKOUT_P CIE1P

M1

PCIECLKR Q1# / GPIO18

AA48

CLKOUT_P CIE2N

AA47

CLKOUT_P CIE2P

V10

PCIECLKR Q2# / GPIO20

Y37

CLKOUT_P CIE3N

Y36

CLKOUT_P CIE3P

A8

PCIECLKR Q3# / GPIO25

Y43

CLKOUT_P CIE4N

Y45

CLKOUT_P CIE4P

L12

PCIECLKR Q4# / GPIO26

V45

CLKOUT_P CIE5N

V46

CLKOUT_P CIE5P

L14

PCIECLKR Q5# / GPIO44

AB42

CLKOUT_P EG_B_N

AB40

CLKOUT_P EG_B_P

E6

PEG_B_CL KRQ# / GPIO56

V40

CLKOUT_P CIE6N

V42

CLKOUT_P CIE6P

T13

PCIECLKR Q6# / GPIO45

V38

CLKOUT_P CIE7N

V37

CLKOUT_P CIE7P

K12

PCIECLKR Q7# / GPIO46

AK14

CLKOUT_IT PXDP_N

AK13

CLKOUT_IT PXDP_P

PANTHE R-POINT_FCBGA98 9

HM76@

SMBUSController

SML1ALE RT# / PCHHOT# / GPIO74

PCI-E*

CLOCKS

3

SMBALER T# / GPIO11

SML0ALE RT# / GPIO60

SML0DAT A

SML1CLK / GPIO58

SML1DAT A / GPIO75

Link

PEG_A_CL KRQ# / GPIO47

CLKOUT_P EG_A_N

CLKOUT_P EG_A_P

CLKOUT_D MI_N CLKOUT_D MI_P

CLKOUT_D P_N

CLKOUT_D P_P

CLKIN_DM I_N CLKIN_DM I_P

CLKIN_GND 1_N CLKIN_GND 1_P

CLKIN_DOT _96N CLKIN_DOT _96P

CLKIN_SA TA_N CLKIN_SA TA_P

REFCLK1 4IN

CLKIN_PC ILOOPBACK

XTAL25_IN

XTAL25_OU T

XCLK_RC OMP

CLKOUTFL EX0 / GPIO64

CLKOUTFL EX1 / GPIO65

CLKOUTFL EX2 / GPIO66

CLKOUTFL EX3 / GPIO67

FLEX CLOCKS

E12

H14

SMBCLK

C9

SMBDAT A

A12

C8

SML0CLK

G12

C13

E14

M16

M7

CL_CLK1

T11

CL_DATA 1

P10

CL_RST1#

M10

AB37 AB38

AV22 AU22

AM12 AM13

BF18 BE18

BJ30 BG30

G24 E24

AK7 AK5

K45

H45

V47 V49

Y47

K43

F47

H47

K49

BIOS Request SKU ID

PCH_GPI01 1

PCH_SM BCLK

PCH_SM BDATA

DRAMRS T_CNTRL_PCH

PCH_SM L0CLK

PCH_SM L0DATA

PCH_HOT #

SML1CLK

SML1DAT A

CLK_CPU _DMI# CLK_CPU _DMI

CLK_BUF _CPU_DMI# CLK_BUF _CPU_DMI

CLKIN_DM I2# CLKIN_DM I2

CLK_BUF _DREF_96M# CLK_BUF _DREF_96M

CLK_BUF _PCIE_SATA# CLK_BUF _PCIE_SATA

CLK_BUF _ICH_14M

CLK_PCI_L PBACK

XTAL25_IN XTAL25_OU T

XCLK_RC OMP

27M_SSC

PCH_GPIO67

R140 10K_0402_ 5%R140 10K_0402_5%

+3V_PCH

1 2

12

R134 10K_0402_ 5%R134 10K_0402_5%

1K_0402_5%

12

R143

R143 10K_0402_5 %

10K_0402_5 %

1 2

R145 10K_0402_ 5%

CLK_CPU _DMI# <6> CLK_CPU _DMI <6>

1 2

R155 10K_0402_5 %R155 10K_0402_5 %

1 2

R157 10K_0402_5 %R157 10K_0402_5 %

1 2

R159 10K_0402_5 %R159 10K_0402_5 %

1 2

R160 10K_0402_5 %R160 10K_0402_5 %

1 2

R162 10K_0402_5 %R162 10K_0402_5 %

1 2

R163 10K_0402_5 %R163 10K_0402_5 %

1 2

R164 10K_0402_5 %R164 10K_0402_5 %

1 2

R166 10K_0402_5 %R166 10K_0402_5 %

1 2

R167 10K_0402_5 %R167 10K_0402_5 %

R171

90.9_0402_1%

1 2

PCH_GPIO67 <19>

1K_0402_5%

+3V_PCH

@

CLK_PCI_L PBACK <18 >

2

+3V_PCH

12

R139

+V1.05S_VCCP

DRAMRS T_CNTRL_PCH <10,7>

+3V_PCH

XTAL25_IN

XTAL25_OU T

C196

12P_0402_5 0V8J

Q60A

Q60A 2N7002DW -T/R7_SOT363-6

2N7002DW -T/R7_SOT363-6

6 1

3

6 1

3

SMB_CLK _S3SMB _CLK_S3

2

+3VS

5

4

SMB_DA TA_S3SMB_DA TA_S3

2N7002DW -T/R7_SOT363-6

2N7002DW -T/R7_SOT363-6 Q60B

Q60B

Q61A

Q61A 2N7002DW -T/R7_SOT363-6

2N7002DW -T/R7_SOT363-6

2N7002DW -T/R7_SOT363-6 Q61B

Q61B

EC_SMB _CK2

2

+3VS

5

4

EC_SMB _DA2

1 2

R169 1M_0402_5%R 169 1M_04 02_5%

3

2

Y2

25MHZ_10 PF_7V25000014

1

2

OSC

NC

1

SMB_CLK _S3 <12,13,26>

DIMM1 DIMM2 Mini Card

SMB_DA TA_S3 < 12,13,26>

EC_SMB _CK2 <29,32>

VGA EC Thermal Sensor

EC_SMB _DA2 <29,32>

2.2K_0402_5 %

PCH_SM L0CLK

PCH_SM L0DATA

SML1DAT A EC_SMB _DA2 SML1CLK EC_SMB _CK2

PCH_SM BCLK SMB_CLK _S3 PCH_SM BDATA SMB_DA TA_S3

4

NC

1

OSC

1

12P_0402_5 0V8J

2

+3V_PCH

R544

1 2

+3V_PCH

RP23

18 27 36 45

2.2K_0804_8 P4R_5%

+3V_PCH

RP24

18 27 36 45

2.2K_0804_8 P4R_5%

C197

R545

2.2K_0402_5 %

+3VS

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PCH (2/9) PCIE, SMBUS, CLK

LA-9632P

1

15 60W ednesday, February 27, 2013

1.0

of

Lenovo G400, G500 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual