Lenovo g400s,g500s Schematics
Compal Confidential
G400S/G500S UMA M/В Schematics Document
Intel Ivy Bridge Processor with DDRIII + Panther Point PCH
LA-9902P
2013-05-06
REV:1.0
Issu ed Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTO DY OF THE COMPETENT DIVISION OF R
DEPARTMEN T EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE IN FORMATION IT CONTAINS
C
2011/06/15 f D eci ph ere d Date | 2012 /07/11
__________________________1_______________________________Ū___________________________
C om p al S ecr et Dat a
C o mp al El e c t ro ni cs , In c.
SCHEMATIC M/В LA-9902
Document Number
" 4019N1
Wed nesd av.Ma v08.2 013 ISheet 1 of 52
E
|s n
_
Title
Oust.
L _
*ev
в
Voltage Rails
EC SM Busi address
Add ress
Devi ce
Sm art B atter y 0001 01I X b
PCH SW1 Bus address
Device Addres s
DDRDIM M0 1010 OOOXb
DDRDIM M2 lOIO OIOX b
NV-GPU SM Bus address
Device
Inter nal th erma l sen sor
S MB _E C_ CK 1
S M B J C . D A l
S MB _E C_ CK 2
S MB _E C _D A2
S MB C LK
S M B D AT A
S ML 0 CL K
S M L 0D A T A
S ML 1 CL K
S M L I D AT A
S OU RC E V G A
K B9 01 2
+ 3 VA L W
K B9 01 2
+ 3 VA L W
PC H
+ 3 VA L W
PC H
+ 3V A L W
PC H
+ 3V A L W
Addre ss
1001 I ll X b (0x9E)
X V
V
f 3V S V GA
X
X X
+ 3 vs 4 g a
В АТ Т
+ 3V A L W
X
X X
X
X
X
X
EC SM Bus2 address
Devic e Addr ess
Th erma l Sen sor
K B9 01 2
S O D IM M
X
X
X
X X
J s J s
X
J s
X X
X X
+5 VS
+3 VS
+ 1 . 5 VS
+ V 1 . 05 S_ VC C P
+V CC_ CO RE
+V GA_ CO RE
+V CC _G FXC OR E_A XG
+ 1 . 8VS
+ 0 .7 5 VS
+ 1 . 0 5 VS
1001 lOOxb
T h er m a l
W L A N
S en s or
X
X
X X
X
X X
X
M s
PC H
BOARD ID Table
Boa rd ID PCB Revis ion
J s
X
X
~ --—____
S T A T E -------
0
1
2
3
4
5
1.0
0.3
0.2
0.1
SI (P o w er O n S usp end ,)
S 3 (S u s p e n d t o R AM )
S4 ( S u s p e n d to D i s k)
S 5 (S o ft OF F)
F ul l ON
S I G N A L
S L P _ S 1 #
S L P _ S 3 #
H I G H HI G H
L O W H I G H
L O W H I G H
L O W
L O W L O W L O W H I G H O N O F F O F F O F F
L O W L O W L O W L O W O N O F F O F F O F F
6
7
Board !D table for AD channel
Vcc
Ra
Bo a rd ID
USB Port Table
USB 2.0
ин ею
UHCI1
EHCIl
U SB 3 .0
UHCI2
UHCI3
UHCI4
EHCI2
UHCI5
UHCI6
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PR OPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDEN ■
AND TRADE SECRET INFORMATION. TH IS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTO DY OF THE COMPETENT DIVISIO N OF R
DEPARTMEN T EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRON ICS, INC.
Port
USB Port (Left Side)osB3.o
0
USB Port (Left SidepsB3 о
1
2
Touch Screen
3
USB Camera
4
5
6
7
8
US B/B (R ight Si de U SB 2.0)
9
10
Mini Card(WLAN)
11
Card Reader
12
13
3. 3 V
1 0 0 K + / - 1 %
Rb
0
1 2 K + / - 1 %
i
1 5 K + / - 1 %
2
2 0 K + / - 1%
3
3 Externa l
USB Port
De cipher ed D ate
Vu 3 B I D m -*-n V ad _b i d
0 0 V 0 V 0.300 V
0.347 V 0.354 V
0.423 V
0.541 V
BOM Structure Table
45 L EVE L 45@
Connec to r МЕ0
For VILG2 (14")
For VIL G1 (15") 150
HDMI HDMI0
Camera CMOS0
LAN LDO M ode LDO0
LAN Swi tc h mode SWR0
10/10 0 LA N( AR8 162L)
10/1 00 LAN (QCA8172)
Gre en clo ck( DIS sku) GCLK3O4 0
Green cl ock(U MA sku)
Green elk s upport GCLK@
No G reen el k sup port
Tou ch S cre en SKU TS@
Opti mus SKU OPT0
UM A S KU UMA0
PCH (N M7 0 sku)
PCH(HM7 0 sku) HM7O0
PC H( HM 76 sku) HM7 6@
V R A M (1000MHz) 1OOOM0
V R A M (900MHz)
Unpop
S L P _ S 4 #
H I G H
H I G H
S L P _ S 5 #
+ V A L W
H I G H O N
H I G H O N
H I G H O N O N O F F O F F
V a d _ b i d max
+ V +V S
O N O N
O N
EC AD
O N L O W
0x00 - OxOB
0.360 V
OxOC - Ox lC PVT
0.430 V 0.438 V OxlD - 0x26
0.550 V 0.559 V
0x27 - 0x30 EVT
BTO Ite m BOM Str uct ure
140
81620
81720
GCLK2440
NOGCLK6
NM7O0
900M@
@
Compal Electronics, Inc.
Document Number
4019N1
Wednesday, May 08. 2013 [S heet
SCHEMATIC M/В LA-990:!
C l o c k
O N
MP
DVT
5
D D
DMI_CRX_PTX_N0<16>
DMI_CRX_PTX_N1<16>
DMI_CRX_PTX_N2<16>
DMI_CRX_PTX_N3<16>
DMI_CRX_PTX_P0<16>
DMI_CRX_PTX_P1<16>
DMI_CRX_PTX_P2<16>
DMI_CRX_PTX_P3<16>
DMI_CTX_PRX_N0<16>
DMI_CTX_PRX_N1<16>
DMI_CTX_PRX_N2<16>
DMI_CTX_PRX_N3<16>
DMI_CTX_PRX_P0<16>
DMI_CTX_PRX_P1<16>
DMI_CTX_PRX_P2<16>
DMI_CTX_PRX_P3<16>
C C
+V1.05S_VCCP
12
R7
24.9_0402_1%
B B
eDP_COMPIO and ICOMPO signals
should be shorted near balls
and routed with typical
impedance <25 mohms
FDI_CTX_PRX_N0<16>
FDI_CTX_PRX_N1<16>
FDI_CTX_PRX_N2<16>
FDI_CTX_PRX_N3<16>
FDI_CTX_PRX_N4<16>
FDI_CTX_PRX_N5<16>
FDI_CTX_PRX_N6<16>
FDI_CTX_PRX_N7<16>
FDI_CTX_PRX_P0<16>
FDI_CTX_PRX_P1<16>
FDI_CTX_PRX_P2<16>
FDI_CTX_PRX_P3<16>
FDI_CTX_PRX_P4<16>
FDI_CTX_PRX_P5<16>
FDI_CTX_PRX_P6<16>
FDI_CTX_PRX_P7<16>
FDI_FSYNC0<16>
FDI_FSYNC1<16>
FDI_INT<16>
FDI_LSYNC0<16>
FDI_LSYNC1<16>
EDP_COMP
eDP_HPD
4
JCPU1A
B27
DMI_RX#[0]
B25
DMI_RX#[1]
A25
DMI_RX#[2]
B24
DMI_RX#[3]
B28
DMI_RX[0]
B26
DMI_RX[1]
A24
DMI_RX[2]
B23
DMI_RX[3]
G21
DMI_TX#[0]
E22
DMI_TX#[1]
F21
DMI_TX#[2]
D21
DMI_TX#[3]
G22
DMI_TX[0]
D22
DMI_TX[1]
F20
DMI_TX[2]
C21
DMI_TX[3]
A21
FDI0_TX#[0]
H19
FDI0_TX#[1]
E19
FDI0_TX#[2]
F18
FDI0_TX#[3]
B21
FDI1_TX#[0]
C20
FDI1_TX#[1]
D18
FDI1_TX#[2]
E17
FDI1_TX#[3]
A22
FDI0_TX[0]
G19
FDI0_TX[1]
E20
FDI0_TX[2]
G18
FDI0_TX[3]
B20
FDI1_TX[0]
C19
FDI1_TX[1]
D19
FDI1_TX[2]
F17
FDI1_TX[3]
J18
FDI0_FSYNC
J17
FDI1_FSYNC
H20
FDI_INT
J19
FDI0_LSYNC
H17
FDI1_LSYNC
A18
eDP_COMPIO
A17
eDP_ICOMPO
B16
eDP_HPD#
C15
eDP_AUX
D15
eDP_AUX#
C17
eDP_TX[0]
F16
eDP_TX[1]
C16
eDP_TX[2]
G15
eDP_TX[3]
C18
eDP_TX#[0]
E16
eDP_TX#[1]
D16
eDP_TX#[2]
F15
eDP_TX#[3]
TYCO_2013620-2_IVY BRIDGE
ME@
3
PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
J22
J21
H22
K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32
J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32
M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25
M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
DMI
Intel(R) FDI
eDP
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PCI EXPRESS* - GRAPHICS
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
PEG_COMP
2
PEG_ICOMPI and RCOMPO signals should be
shorted and routed
+V1.05S_VCCP
12
R1
with - max length = 500 mils - typical
impedance = 43 mohms
PEG_ICOMPO signals should be routed with max length = 500 mils
- typical impedance = 14.5 mohms
PEG Static Lane Reversal - CFG2 is for the 16x
CFG2
1: Normal Operation; Lane # definition matches
socket pin map definition
0:Lane Reversed
*
1
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2011/06/15 2012/07/11
2011/06/15 2012/07/11
2011/06/15 2012/07/11
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Title
Title
Title
Size
Size
Size
Custom
Custom
Custom
Date: Sheet
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC M/B LA-9902
SCHEMATIC M/B LA-9902
SCHEMATIC M/B LA-9902
Document Number Rev
Document Number Rev
Document Number Rev
4019N1
4019N1
4019N1
1
of
of
of
552Wednesday, May 08, 2013
552Wednesday, May 08, 2013
552Wednesday, May 08, 2013
B
B
B
5
4
3
2
1
D D
H_SNB_IVB#<19>
+V1.05S_VCCP
12
R9
62_0402_5%
H_PROCHOT#<32,37,44>
C C
H_CPUPWRGD<19>
H_PROCHOT#
100P_0402_50V8J
C549
H_PM_SYNC<16>
R27
1
10K_0402_5%
1 2
2
T48
H_PECI<32>
R15
56_0402_5%
1 2
H_THRMTRIP#<19>
R29
1 2
130_0402_5%
H_CATERR#
H_PROCHOT#_R
PM_DRAM_PWRGD_R
BUF_CPU_RST#
ESD
3/20 Add (ESD request)
+3VALW +3VS
2
B B
C852
0.1U_0402_16V4Z
2
C853
0.1U_0402_16V4Z
1
1
1 2
R161
+3VS
10K_0402_5%
PM_DRAM_PWRGD<16>
+3VALW
U1
5
1
P
B
2
A
G
74AHC1G09GW_TSSOP5
3
4
PM_SYS_PWRGD_BUF
O
+1.5V_CPU_VDDQ
12
R30
200_0402_5%
BUF_CPU_RST#
JCPU1B
C26
PROC_SELECT#
AN34
SKTOCC#
AL33
CATERR#
AN33
PECI
AL32
PROCHOT#
AN32
THERMTRIP#
AM34
PM_SYNC
AP33
UNCOREPWRGOOD
V8
SM_DRAMPWROK
AR33
RESET#
TYCO_2013620-2_IVY BRIDGE
ME@
75_0402_5%
43_0402_1%
1 2
MISCTHERMALPWR MANAGEMENT
+V1.05S_VCCP
12
R32
R34
BUFO_CPU_RST#
SN74LVC1G07DCKR_SC70-5
DPLL_REF_CLK
DPLL_REF_CLK#
CLOCKS
SM_DRAMRST#
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
DDR3
MISC
JTAG & BPM
Buffered reset to CPU
+3VS
5
U2
P
NC
4
Y
A
G
3
A28
BCLK
A27
BCLK#
A16
A15
R8
H_DRAMRST#
AK1
SM_RCOMP0
A5
SM_RCOMP1
A4
SM_RCOMP2
DDR3 Compensation Signals
AP29
AP27
AR26
TCK
AR27
TMS
AP30
AR28
TDI
AP26
TDO
AL35
AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32
PCH_PLTRST#
XDP_PRDY#
XDP_PREQ#
XDP_TCK
XDP_TMS
XDP_TRST#
XDP_TDI
XDP_TDO
XDP_DBRESET#
XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_BPM#6
XDP_BPM#7
PRDY#
PREQ#
TRST#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
1
2
DBR#
R12
R13
R16
R17
R18
3V
PCH_PLTRST#
12
1K_0402_5%
12
1K_0402_5%
H_DRAMRST#
12
12
12
PAD
T18
T19
PAD
T20
T21
T22
T23
T24 PAD
T25
T26
T27
T28
<18>
140_0402_1%
25.5_0402_1%
200_0402_1%
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
+V1.05S_VCCP
<7>
R28 1K_0402_5%
12
C45
0.047U_0402_16V7K
ESD
CLK_CPU_DMI
CLK_CPU_DMI#
XDP_TRST#
XDP_TDI
XDP_TMS
XDP_TCK
12
<15>
<15>
51_0804_8P4R_5%
+3VS
+V1.05S_VCCP
RP13
18
27
36
45
@
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/06/15 2012/07/11
2011/06/15 2012/07/11
2011/06/15 2012/07/11
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Title
Title
Title
SCHEMATIC M/B LA-9902
SCHEMATIC M/B LA-9902
SCHEMATIC M/B LA-9902
Document Number Rev
Document Number Rev
Document Number Rev
Size
Size
Size
Custom
Custom
Custom
4019N1
4019N1
4019N1
Date: Sheet
Date: Sheet
2
Date: Sheet
1
652Wednesday, May 08, 2013
652Wednesday, May 08, 2013
652Wednesday, May 08, 2013
B
B
B
of
of
of
5
JCPU1C
DDR_A_D[0..63]<12>
D D
C C
DDR_A_BS0<12>
DDR_A_BS1<12>
B B
DDR_A_BS2<12>
DDR_A_CAS#<12>
DDR_A_RAS#<12>
DDR_A_WE#<12>
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15
AE10
AF10
F10
G10
N10
M10
AG6
AG5
AK6
AK5
AH5
AH6
AJ5
AJ6
AJ8
AK8
AJ9
AK9
AH8
AH9
AL9
AL8
AE8
AD9
AF9
C5
D5
D3
D2
D6
C6
C2
C3
F8
G9
F9
F7
G8
G7
K4
K5
K1
J1
J5
J4
J2
K2
M8
N8
N7
M9
N9
M7
V6
SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
SA_BS[0]
SA_BS[1]
SA_BS[2]
SA_CAS#
SA_RAS#
SA_WE#
4
AB6
SA_CLK[0]
AA6
SA_CLK#[0]
V9
SA_CKE[0]
AA5
SA_CLK[1]
AB5
SA_CLK#[1]
V10
SA_CKE[1]
AB4
RSVD_TP[1]
AA4
RSVD_TP[2]
W9
RSVD_TP[3]
AB3
RSVD_TP[4]
AA3
RSVD_TP[5]
W10
RSVD_TP[6]
AK3
SA_CS#[0]
AL3
SA_CS#[1]
AG1
RSVD_TP[7]
AH1
RSVD_TP[8]
AH3
SA_ODT[0]
AG3
SA_ODT[1]
AG2
RSVD_TP[9]
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
AH2
C4
G6
J3
M6
AL6
AM8
AR12
AM15
D4
F6
K3
N6
AL5
AM9
AR11
AM14
AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
RSVD_TP[10]
DDR SYSTEM MEMORY A
M_CLK_DDR0
M_CLK_DDR#0
DDR_CKE0_DIMMA
M_CLK_DDR1
M_CLK_DDR#1
DDR_CKE1_DIMMA <12>
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
M_ODT0
M_ODT1
<12>
<12>
<12>
<12>
<12>
<12>
DDR_A_DQS#[0..7]
DDR_A_DQS[0..7]
DDR_A_MA[0..15]
<12>
<12>
<12>
3
<12>
<12>
<12>
2
D10
K10
AM5
AM6
AR3
AP3
AN3
AN2
AN1
AP2
AP5
AN9
AT5
AT6
AP6
AN8
AR6
AR5
AR9
AJ11
AT8
AT9
AH11
AR8
AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15
AA9
AA7
AA10
AB8
AB9
J10
C9
A7
C8
A9
A8
D9
D8
G4
F4
F1
G1
G5
F5
F2
G2
J7
J8
K9
J9
K8
K7
M5
N4
N2
N1
M4
N5
M2
M1
R6
JCPU1D
SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
SB_BS[0]
SB_BS[1]
SB_BS[2]
SB_CAS#
SB_RAS#
SB_WE#
AE2
SB_CLK[0]
AD2
SB_CLK#[0]
R9
SB_CKE[0]
AE1
SB_CLK[1]
AD1
SB_CLK#[1]
R10
SB_CKE[1]
SB_CS#[0]
SB_CS#[1]
SB_ODT[0]
SB_ODT[1]
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
AB2
AA2
T9
AA1
AB1
T10
AD3
AE3
AD6
AE6
AE4
AD4
AD5
AE5
D7
F3
K6
N3
AN5
AP9
AK12
AP15
C7
G3
J6
M3
AN6
AP8
AK11
AP14
AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
RSVD_TP[11]
RSVD_TP[12]
RSVD_TP[13]
RSVD_TP[14]
RSVD_TP[15]
RSVD_TP[16]
RSVD_TP[17]
RSVD_TP[18]
RSVD_TP[19]
RSVD_TP[20]
DDR SYSTEM MEMORY B
DDR_B_D[0..63]<13>
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
DDR_B_BS0<13>
DDR_B_BS1<13>
DDR_B_BS2<13>
DDR_B_CAS#<13>
DDR_B_RAS#<13>
DDR_B_WE#<13>
1
M_CLK_DDR2
M_CLK_DDR#2
DDR_CKE2_DIMMB
M_CLK_DDR3
M_CLK_DDR#3
DDR_CKE3_DIMMB <13>
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
M_ODT2
M_ODT3
<13>
<13>
<13>
<13>
<13>
<13>
DDR_B_DQS#[0..7]
DDR_B_DQS[0..7]
DDR_B_MA[0..15]
<13>
<13>
<13>
<13>
<13>
<13>
TYCO_2013620-2_IVY BRIDGE
ME@
D
S
13
H_DRAMRST#<6>
R39
4.99K_0402_1%
1 2
A A
DRAMRST_CNTRL_PCH<10,15>
5
R48
1 2
@
0_0402_5%
DRAMRST_CNTRL_PCH_R
DDR3_DRAMRST#_RH_DRAMRST#
Q2
G
LBSS138LT1G_SOT-23-3
2
1
@
C35
0.047U 16V K X7R 0402
2
Eiffel used 0.01u
Module design used 0.047u
4
+1.5V
R37
1K_0402_5%
12
R38
1K_0402_5%
1 2
DDR3_DRAMRST#
Security Classification
Security Classification
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Issued Date
Issued Date
<12,13>
3
Compal Secret Data
Compal Secret Data
2011/06/15 2012/07/11
2011/06/15 2012/07/11
2011/06/15 2012/07/11
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
TYCO_2013620-2_IVY BRIDGE
ME@
2
Title
Title
Title
Size
Size
Size
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC M/B LA-9902
SCHEMATIC M/B LA-9902
SCHEMATIC M/B LA-9902
Document Number Rev
Document Number Rev
Document Number Rev
4019N1
4019N1
4019N1
1
75
75
75
B
B
B
of
of
of
2Wednesday, May 08, 2013
2Wednesday, May 08, 2013
2Wednesday, May 08, 2013
5
4
3
2
1
CFG Straps for Processor
D D
JCPU1E
AK28
CFG[0]
AK29
CFG[1]
AL26
CFG[2]
AL27
CFG[3]
CFG4
C C
PAD
T14
T15
PAD
T16
PAD
PAD
T17
VCC_AXG_VAL_SENSE
VSS_AXG_VAL_SENSE
VCC_VAL_SENSE
VSS_VAL_SENSE
Need PWR add new circuit on 1.05V(refer CRB)
B B
AK26
CFG[4]
AL29
CFG[5]
AL30
CFG[6]
AM31
CFG[7]
AM32
CFG[8]
AM30
CFG[9]
AM28
CFG[10]
AM26
CFG[11]
AN28
CFG[12]
AN31
CFG[13]
AN26
CFG[14]
AM27
CFG[15]
AK31
CFG[16]
AN29
CFG[17]
AJ31
VAXG_VAL_SENSE
AH31
VSSAXG_VAL_SENSE
AJ33
VCC_VAL_SENSE
AH33
VSS_VAL_SENSE
AJ26
RSVD5
F25
RSVD8
F24
RSVD9
F23
RSVD10
D24
RSVD11
G25
RSVD12
G24
RSVD13
E23
RSVD14
D23
RSVD15
C30
RSVD16
A31
RSVD17
B30
RSVD18
B29
RSVD19
D30
RSVD20
B31
RSVD21
A30
RSVD22
C29
RSVD23
J20
RSVD24
B18
RSVD25
J15
RSVD27
CFG
VCC_DIE_SENSE
VSS_DIE_SENSE
RESERVED
RSVD_NCTF10
RSVD_NCTF11
RSVD_NCTF12
RSVD_NCTF13
Interl request AH26 short GND
check on EVT phase
AH27
AH26
L7
RSVD28
AG7
RSVD29
AE7
RSVD30
AK2
RSVD31
W8
RSVD32
AT26
RSVD33
AM33
RSVD34
AJ27
RSVD35
T8
RSVD37
J16
RSVD38
H16
RSVD39
G16
RSVD40
RSVD51
RSVD52
BCLK_ITP
BCLK_ITP#
KEY
AR35
AT34
AT33
AP35
AR34
B34
A33
A34
B35
C35
AJ32
AK32
AN35
AM35
AT2
AT1
AR1
B1
RSVD_NCTF1
RSVD_NCTF2
RSVD_NCTF3
RSVD_NCTF4
RSVD_NCTF5
RSVD_NCTF6
RSVD_NCTF7
RSVD_NCTF8
RSVD_NCTF9
PEG Static Lane Reversal - CFG2 is for the 16x
T13PAD
CFG2
1: Normal Operation; Lane # definition matches
socket pin map definition
0:Lane Reversed
*
CFG4
12
@
R42
1K_0402_1%
Display Port Presence Strap
CFG4
1 : Disabled; No Physical Display Port
*
attached to Embedded Display Port
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
PCIE Port Bifurcation Straps
11: (Default) x16 - Device 1 functions 1 and 2 disabled
CFG[6:5]
10: x8, x8 - Device 1 function 1 enabled ; function 2
*
disabled
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
TYCO_2013620-2_IVY BRIDGE
ME@
PEG DEFER TRAINING
1: (Default) PEG Train immediately following xxRESETB
CFG7
de assertion
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/06/15 2012/07/11
2011/06/15 2012/07/11
2011/06/15 2012/07/11
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
0: PEG Wait for BIOS for training
Title
Title
Title
Document Number Rev
Document Number Rev
Document Number Rev
Size
Size
Size
Custom
Custom
Custom
Date: Sheet
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC M/B LA-9902
SCHEMATIC M/B LA-9902
SCHEMATIC M/B LA-9902
4019N1
4019N1
4019N1
1
B
B
852Wednesday, May 08, 2013
852Wednesday, May 08, 2013
852Wednesday, May 08, 2013
B
of
of
of
5
4
3
2
1
+VCC_CORE
JCPU1F
QC=94A
DC=53A
D D
C C
B B
A A
AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
Y35
VCC51
Y34
VCC52
Y33
VCC53
Y32
VCC54
Y31
VCC55
Y30
VCC56
Y29
VCC57
Y28
VCC58
Y27
VCC59
Y26
VCC60
V35
VCC61
V34
VCC62
V33
VCC63
V32
VCC64
V31
VCC65
V30
VCC66
V29
VCC67
V28
VCC68
V27
VCC69
V26
VCC70
U35
VCC71
U34
VCC72
U33
VCC73
U32
VCC74
U31
VCC75
U30
VCC76
U29
VCC77
U28
VCC78
U27
VCC79
U26
VCC80
R35
VCC81
R34
VCC82
R33
VCC83
R32
VCC84
R31
VCC85
R30
VCC86
R29
VCC87
R28
VCC88
R27
VCC89
R26
VCC90
P35
VCC91
P34
VCC92
P33
VCC93
P32
VCC94
P31
VCC95
P30
VCC96
P29
VCC97
P28
VCC98
P27
VCC99
P26
VCC100
POWER
PEG AND DDR
CORE SUPPLY
VCCIO_SENSE
VSS_SENSE_VCCIO
SENSE LINES SVID
VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24
VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39
VCCIO40
VIDALERT#
VIDSCLK
VIDSOUT
VCC_SENSE
VSS_SENSE
+V1.05S_VCCP
8.5A
AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12
E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11
J23
+V1.05S_VCCP
12
R46
75_0402_5%
VR_SVID_CLK
AJ29
AJ30
AJ28
H_CPU_SVIDALRT#
1 2
R47
43_0402_5%
R50 130_0402_5%
12
+V1.05S_VCCP
VR_SVID_ALRT#
VR_SVID_CLK
VR_SVID_DAT
0.1uF on power side
VCC_SENCE 100ohm +-1% pull-up to VCC near processor
Trace Impedance =27-33 ohm
Trace Length Matc < 25 mils
AJ35
AJ34
B10
A10
VSSIO_SENSE_L
1 2
R74
10_0402_1%
R74 & R79 put together
VSSIO_SENSE_L
<43>
VSS_SENCE 100ohm +-1% pull-down to GND near processor
R79
10_0402_1%
VCCIO_SENSE
+V1.05S_VCCP
12
series-resistors close to VR
<44>
<44>
<44>
+VCC_CORE
12
R51
100_0402_1%
12
<43>
R54
100_0402_1%
VCCSENSE <44>
VSSSENSE
<44>
Security Classification
Security Classification
TYCO_2013620-2_IVY BRIDGE
ME@
5
4
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2011/06/15 2012/07/11
2011/06/15 2012/07/11
2011/06/15 2012/07/11
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Title
Title
Title
SCHEMATIC M/B LA-9902
SCHEMATIC M/B LA-9902
SCHEMATIC M/B LA-9902
Document Number Rev
Document Number Rev
Size
Size
Document Number Rev
Size
Custom
Custom
Custom
4019N1
4019N1
4019N1
Date: Sheet
Date: Sheet
2
Date: Sheet
952Wednesday, May 08, 2013
952Wednesday, May 08, 2013
952Wednesday, May 08, 2013
1
B
B
B
of
of
of
5
4
3
2
1
+1.5V +1.5V_CPU_VDDQ
+VREF_DQ_DIMMA
+VREF_DQ_DIMMB
U3
R56
82K_0402_5%
RUN_ON_CPU1.5VS3
D
Q4
2N7002_SOT23
S
DMN3030LSS-13_SOP8L-8
8
7
5
4
JCPU1G
AT24
VAXG1
AT23
VAXG2
AT21
VAXG3
AT20
VAXG4
AT18
VAXG5
AT17
VAXG6
AR24
VAXG7
AR23
VAXG8
AR21
VAXG9
AR20
VAXG10
AR18
VAXG11
AR17
VAXG12
AP24
VAXG13
AP23
VAXG14
AP21
VAXG15
AP20
VAXG16
AP18
VAXG17
AP17
VAXG18
AN24
VAXG19
AN23
VAXG20
AN21
VAXG21
AN20
VAXG22
AN18
VAXG23
AN17
VAXG24
AM24
VAXG25
AM23
VAXG26
AM21
VAXG27
AM20
VAXG28
AM18
VAXG29
AM17
VAXG30
AL24
VAXG31
AL23
VAXG32
AL21
VAXG33
AL20
VAXG34
AL18
VAXG35
AL17
VAXG36
AK24
VAXG37
AK23
VAXG38
AK21
VAXG39
AK20
VAXG40
AK18
VAXG41
AK17
VAXG42
AJ24
VAXG43
AJ23
VAXG44
AJ21
VAXG45
AJ20
VAXG46
AJ18
VAXG47
AJ17
VAXG48
AH24
VAXG49
AH23
VAXG50
AH21
VAXG51
AH20
VAXG52
AH18
VAXG53
AH17
VAXG54
1
AP4800
2
Id=9.6A
36
R02
R885
1 2
15K_0402_1%
POWER
GRAPHICS
1
C97
0.047U_0603_25V7K
2
VSSAXG_SENSE
SENSE
LINES
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
VREFMISC
VAXG_SENSE
SM_VREF
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
+VCC_GFXCORE_AXG
AK35
AK34
AL1
+V_SM_VREF_CNT
B4
+V_DDR_REFA_R
D1
+V_DDR_REFB_R
AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1
DDR3 -1.5V RAILS
M27
VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8
+VCCSA
M26
L26
J26
J25
J24
H26
H25
DRAMRST_CNTRL_PCH
M3 Circuit (Processor Generated SO-DIMM VREF_DQ)
12
R616
10_0402_1%
VCC_AXG_SENSE
12
R626
10_0402_1%
1
+
2
VSS_AXG_SENSE
+V_SM_VREF should
have 20 mil trace width
C127
330U_2.5V_M
@
1/25 Follow FM-James's comments(Co-lay with C123)
C
C
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1
124
125
2
2
0.1U_0402_10V6K
10U_0603_6.3V6M
C
1
1
117
2
2
C
10U_0603_6.3V6M
1
126
2
10U_0603_6.3V6M
<44>
<44>
C98
C119
1
2
+VCCSA
2
G
LBSS138LT1G_SOT-23-3
+1.5V_CPU_VDDQ
12
R67
1K_0402_1%
12
1
R78
1K_0402_1%
2
+1.5V_CPU_VDDQ
1
10U_0603_6.3V6M
10U_0603_6.3V6M
C
C122
1
+
120
@
2
2
1
+
C128
@
330U_D2_2.5VY_R9M
2
13
D
S
Q9
C123
330U_D2_2V_Y
1/16 Change symbol & value from
SF000002Z00 to SGA20331E10
D D
SUSP<36>
C C
B B
+VSB
12
13
2
G
+VCC_GFXCORE_AXG
Q6
13
D
LBSS138LT1G_SOT-23-3
2
G
S
+V_DDR_REFA_R
+V_DDR_REFB_R
DRAMRST_CNTRL_PCH
<15,7>
SA RAIL
+1.8VS
R69
0_0805_5%
1 2
@
VCCIO_SEL
H23
C22
C24
A19
H_VCCSA_VID0
H_VCCSA_VID1
<42>
<42>
1.5A
+1.8VS_VCCPLL
1U_0402_6.3V6K
10U_0603_6.3V6M
C
130
1
1
2
2
B6
VCCPLL1
A6
C
132
VCCPLL2
A2
VCCPLL3
TYCO_2013620-2_IVY BRIDGE
ME@
1.8V RAIL
VCCSA_SENSE
VCCSA_VID[0]
VCCSA_VID[1]
+VCCSA_SENSE <42>
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/06/15 2012/07/11
2011/06/15 2012/07/11
2011/06/15 2012/07/11
Compal Secret Data
Compal Secret Data
Compal Secret Data
IVY Bridge drives VCCIO_SEL low
VCCP_PWRCTRL:0
Sandy Bridge is NC for A19
VCCP_PWRCTRL:1
Deciphered Date
Deciphered Date
Deciphered Date
2
Title
Title
Title
SCHEMATIC M/B LA-9902
SCHEMATIC M/B LA-9902
SCHEMATIC M/B LA-9902
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
4019N1
4019N1
4019N1
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
52Wednesday, May 08, 2013
52Wednesday, May 08, 2013
52Wednesday, May 08, 2013
10
10
10
B
B
B
5
JCPU1H
AT35
AT32
AT29
AT27
AT25
AT22
AT19
AT16
AT13
D D
C C
B B
A A
5
AT10
AT7
AT4
AT3
AR25
AR22
AR19
AR16
AR13
AR10
AR7
AR4
AR2
AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10
AP7
AP4
AP1
AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10
AN7
AN4
AM29
AM25
AM22
AM19
AM16
AM13
AM10
AM7
AM4
AM3
AM2
AM1
AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10
AL7
AL4
AL2
AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10
AK7
AK4
AJ25
TYCO_2013620-2_IVY BRIDGE
ME@
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
4
AJ22
VSS81
AJ19
VSS82
AJ16
VSS83
AJ13
VSS84
AJ10
VSS85
AJ7
VSS86
AJ4
VSS87
AJ3
VSS88
AJ2
VSS89
AJ1
VSS90
AH35
VSS91
AH34
VSS92
AH32
VSS93
AH30
VSS94
AH29
VSS95
AH28
VSS96
AH25
VSS98
AH22
VSS99
AH19
VSS100
AH16
VSS101
AH7
VSS102
AH4
VSS103
AG9
VSS104
AG8
VSS105
AG4
VSS106
AF6
VSS107
AF5
VSS108
AF3
VSS109
AF2
VSS110
AE35
VSS111
AE34
VSS112
AE33
VSS113
AE32
VSS114
AE31
VSS115
AE30
VSS116
AE29
VSS117
AE28
VSS118
VSS
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2
3
JCPU1I
T35
VSS161
T34
VSS162
T33
VSS163
T32
VSS164
T31
VSS165
T30
VSS166
T29
VSS167
T28
VSS168
T27
VSS169
T26
VSS170
P9
VSS171
P8
VSS172
P6
VSS173
P5
VSS174
P3
VSS175
P2
VSS176
N35
VSS177
N34
VSS178
N33
VSS179
N32
VSS180
N31
VSS181
N30
VSS182
N29
VSS183
N28
VSS184
N27
VSS185
N26
VSS186
M34
VSS187
L33
VSS188
L30
VSS189
L27
VSS190
L9
VSS191
L8
VSS192
L6
VSS193
L5
VSS194
L4
VSS195
L3
VSS196
L2
VSS197
L1
VSS198
K35
VSS199
K32
VSS200
K29
VSS201
K26
VSS202
J34
VSS203
J31
VSS204
H33
VSS205
H30
VSS206
H27
VSS207
H24
VSS208
H21
VSS209
H18
VSS210
H15
VSS211
H13
VSS212
H10
VSS213
H9
VSS214
H8
VSS215
H7
VSS216
H6
VSS217
H5
VSS218
H4
VSS219
H3
VSS220
H2
VSS221
H1
VSS222
G35
VSS223
G32
VSS224
G29
VSS225
G26
VSS226
G23
VSS227
G20
VSS228
G17
VSS229
G11
VSS230
F34
VSS231
F31
VSS232
F29
VSS233
TYCO_2013620-2_IVY BRIDGE
ME@
Compal Secret Data
Compal Secret Data
2011/06/15 2012/07/11
2011/06/15 2012/07/11
2011/06/15 2012/07/11
Compal Secret Data
3
Deciphered Date
Deciphered Date
Deciphered Date
VSS
2
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
2
F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3
1
Compal Electronics, Inc.
Title
Title
Title
SCHEMATIC M/B LA-9902
SCHEMATIC M/B LA-9902
SCHEMATIC M/B LA-9902
Document Number Rev
Document Number Rev
Document Number Rev
Size
Size
Size
Custom
Custom
Custom
4019N1
4019N1
4019N1
Date: Sheet
Date: Sheet
Date: Sheet
11
11
11
1
B
B
B
of
of
of
52Wednesday, May 08, 2013
52Wednesday, May 08, 2013
52Wednesday, May 08, 2013
5
+VREF_DQ_DIMMA
+VREF_DQ_DIMMA
0.1U_0402_10V6K
C133
1
D D
C C
B B
1 2
R136 0_0402_5%@
+3VS
A A
2
DDR_CKE0_DIMMA<7>
DDR_A_BS2<7>
M_CLK_DDR0<7>
M_CLK_DDR#0<7>
DDR_A_BS0<7>
DDR_A_WE#<7>
DDR_A_CAS#<7>
DDR_CS1_DIMMA#<7>
+3V_DIMM
0.1U_0402_10V6K
C156
1
2
5
+1.5V +1.5V
3A@1.5V
DDR3 SO-DIMM A
JDIMM1
VREF_DQ1VSS1
3
VSS2
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_CKE0_DIMMA
DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
M_CLK_DDR0
M_CLK_DDR#0
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS# M_ODT0
DDR_A_MA13
DDR_CS1_DIMMA#
DDR_A_D32
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
5
DQ0
7
DQ1
VSS49DQS#0
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1
DQS129RESET#
VSS1131VSS12
33
DQ10
35
DQ11
VSS1337VSS14
39
DQ16
41
DQ17
VSS1543VSS16
45
DQS#2
47
DQS2
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25
VSS2261DQS#3
63
DM3
VSS2365VSS24
67
DQ26
69
DQ27
VSS2571VSS26
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
A12/BC#83A11
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
VDD999VDD10
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
LCN_DAN06-K4806-0103
ME@
VREF_CA
EVENT#
VSS3
DQS0
VSS6
VSS8
DQ12
DQ13
VSS10
DQ14
DQ15
DQ20
DQ21
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS3
DQ30
DQ31
CKE1
VDD2
VDD4
VDD6
VDD8
CK1#
VDD12
RAS#
VDD14
ODT0
VDD16
ODT1
VDD18
VSS28
DQ36
DQ37
VSS30
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
VTT2
4
DDR_A_D[0..63]<7>
DDR_A_DQS[0..7]<7>
<13,7>
<7>
<7>
<7>
DDR_A_DQS#[0..7]<7>
DDR_A_MA[0..15]<7>
+VREF_DQ_DIMMA
+VREF_DQ_DIMMB
<7>
<7>
+VREF_CA
4*0402 1uf
1*0402 2.2uf
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
DDR_A_D4
DDR_A_D5
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D6
DDR_A_D7
DDR_A_D12
DDR_A_D13
DDR3_DRAMRST#
DDR_A_D14
DDR_A_D15
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31
DDR_CKE1_DIMMA
DDR_A_MA15
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
M_CLK_DDR1
M_CLK_DDR#1
DDR_A_BS1
DDR_A_RAS#
DDR_CS0_DIMMA#
M_ODT1
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
SMB_DATA_S3
SMB_CLK_S3
4
+0.75VS
0.65A@0.75V
DDR3_DRAMRST#
DDR_CKE1_DIMMA
M_CLK_DDR1
M_CLK_DDR#1
<7>
DDR_A_BS1
DDR_A_RAS#
DDR_CS0_DIMMA#
<7>
M_ODT0
<7>
M_ODT1
0.1U_0402_10V6K
C135
1
2
VDDQ(1.5V) =
3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)
6*0603 10uf (PER CONNECTOR)
VTT(0.75V) =
3*0805 10uf
VREF =
1*0402 0.1uf
VDDSPD (3.3V)=
1*0402 0.1uf 1*0402 2.2uf
SMB_DATA_S3
SMB_CLK_S3
<13,15,26>
<13,15,26>
DQ4
DQ5
DQ6
DQ7
DM1
DM2
A15
A14
A7
A6
A4
A2
A0
CK1
BA1
S0#
NC2
DM4
DM6
SDA
SCL
G2
+VREF_CA
+VREF_CB
+VREF_CA
3
RP15
1K_0804_8P4R_1%
RP16
1K_0804_8P4R_1%
+1.5V
18
27
36
45
+1.5V
18
27
36
45
2
(220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y00)OSCAN
Layout Note:
Place near DIMM
+1.5V
C139
10U_0603_6.3V6M
1
1
2
2
Layout Note:
Place near DIMM
+0.75VS
C150
1U_0402_6.3V6K
C152
1U_0402_6.3V6K
1
1
2
2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/06/15 2012/07/11
2011/06/15 2012/07/11
2011/06/15 2012/07/11
Compal Secret Data
Compal Secret Data
Compal Secret Data
(10uF_0603_6.3V)*8
(0.1uF_402_10V)*4
C140
10U_0603_6.3V6M
C141
10U_0603_6.3V6M
1
1
2
2
Deciphered Date
Deciphered Date
Deciphered Date
2
C142
10U_0603_6.3V6M
1
2
10U_0603_6.3V6M
C143
10U_0603_6.3V6M
1
2
C144
C145
0.1U_0402_10V6K
1
@
2
C147
0.1U_0402_10V6K
C146
0.1U_0402_10V6K
1
1
2
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size
Size
Size
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
Document Number Rev
Document Number Rev
Document Number Rev
4019N1
4019N1
4019N1
1
C148
0.1U_0402_10V6K
1
1
+
C149
@
220U_6.3V_M
2
2
SCHEMATIC M/B LA-9902
SCHEMATIC M/B LA-9902
SCHEMATIC M/B LA-9902
of
of
of
12 52Wednesday, May 08, 2013
12 52Wednesday, May 08, 2013
1
12 52Wednesday, May 08, 2013
B
B
B
5
4
3
2
1
+VREF_DQ_DIMMB
+VREF_DQ_DIMMB
DDR_B_D0
0.1U_0402_10V6K
1
D D
C C
B B
A A
+3V_DIMM
2
DDR_CKE2_DIMMB<7>
DDR_B_BS2<7>
M_CLK_DDR2<7>
M_CLK_DDR#2<7>
DDR_B_BS0<7>
DDR_B_WE#<7>
DDR_B_CAS#<7>
DDR_CS3_DIMMB#<7>
0.1U_0402_10V6K
C178
1
2
5
C157
+3VS
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_CKE2_DIMMB
DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
M_CLK_DDR2
M_CLK_DDR#2
DDR_B_MA10
DDR_B_BS0
DDR_B_WE#
DDR_B_CAS#
DDR_B_MA13
DDR_CS3_DIMMB#
DDR_B_D32
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
1 2
R97
10K_0402_5%
3A@1.5V
+1.5V +1.5V
JDIMM2
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
9
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1
DQS129RESET#
VSS1131VSS12
33
DQ10
35
DQ11
VSS1337VSS14
39
DQ16
41
DQ17
VSS1543VSS16
45
DQS#2
DQS247VSS17
49
VSS18
51
DQ18
DQ1953VSS19
55
VSS20
57
DQ24
DQ2559VSS21
VSS2261DQS#3
63
DM3
VSS2365VSS24
67
DQ26
69
DQ27
VSS2571VSS26
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
VDD999VDD10
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
LCN_DAN06-K4406-0103
ME@
VSS3
DQS#0
DQS0
VSS6
VSS8
DQ12
DQ13
VSS10
DQ14
DQ15
DQ20
DQ21
DQ22
DQ23
DQ28
DQ29
DQS3
DQ30
DQ31
CKE1
VDD2
VDD4
VDD6
VDD8
CK1#
VDD12
RAS#
VDD14
ODT0
VDD16
ODT1
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
VTT2
2
4
DQ4
6
DQ5
8
10
12
14
16
DQ6
18
DQ7
20
22
24
26
28
DM1
30
32
34
36
38
40
42
44
46
DM2
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
A15
80
A14
82
84
A11
86
A7
88
90
A6
92
A4
94
96
A2
98
A0
100
102
CK1
104
106
108
BA1
110
112
114
S0#
116
118
120
122
NC2
124
126
128
130
132
134
136
DM4
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
DM6
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
SDA
202
SCL
204
206
G2
4
DDR_B_D4
DDR_B_D5
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D6
DDR_B_D7
DDR_B_D12
DDR_B_D13
DDR3_DRAMRST#
DDR_B_D14
DDR_B_D15
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31
DDR_CKE3_DIMMB
DDR_B_MA15
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
M_CLK_DDR3
M_CLK_DDR#3
DDR_B_BS1
DDR_B_RAS#
DDR_CS2_DIMMB#
M_ODT2
M_ODT3
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
SMB_DATA_S3
SMB_CLK_S3
0.65A@0.75V
DDR_B_D[0..63]<7>
DDR_B_DQS[0..7]<7>
DDR_B_DQS#[0..7]<7>
DDR_B_MA[0..15]<7>
<7>
<7>
<7>
<7>
<7>
0.1U_0402_10V6K
C159
1
2
<12,7>
<7>
<7>
<7>
+VREF_CB
+VREF_CB
DDR3_DRAMRST#
DDR_CKE3_DIMMB
M_CLK_DDR3
M_CLK_DDR#3
DDR_B_BS1
DDR_B_RAS#
DDR_CS2_DIMMB#
M_ODT2
M_ODT3
VDDQ(1.5V) =
3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)
6*0603 10uf (PER CONNECTOR)
VTT(0.75V) =
3*0805 10uf
1*0402 0.1uf
4*0402 1uf
1*0402 2.2uf
VDDSPD (3.3V)=
1*0402 2.2uf 1*0402 0.1uf
SMB_DATA_S3
SMB_CLK_S3
+0.75VS
<12,15,26>
<12,15,26>
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
Layout Note:
Place near DIMM
C163
1
2
Layout Note:
Place near DIMM
+0.75VS
C174
1U_0402_6.3V6K
1U_0402_6.3V6K
1
2
Compal Secret Data
Compal Secret Data
2011/06/15 2012/07/11
2011/06/15 2012/07/11
2011/06/15 2012/07/11
Compal Secret Data
(10uF_0603_6.3V)*8
(0.1uF_402_10V)*4
+1.5V
10U_0603_6.3V6M
10U_0603_6.3V6M
C164
C165
1
1
2
2
C176
1
2
Deciphered Date
Deciphered Date
Deciphered Date
2
10U_0603_6.3V6M
10U_0603_6.3V6M
C166
1
2
10U_0603_6.3V6M
C167
1
2
10U_0603_6.3V6M
C168
1
2
0.1U_0402_10V6K
0.1U_0402_10V6K
C170
C169
1
1
@
2
2
Title
Title
Title
Document Number Rev
Document Number Rev
Document Number Rev
Size
Size
Size
4019N1
4019N1
4019N1
Date: Sheet
Date: Sheet
Date: Sheet
0.1U_0402_10V6K
0.1U_0402_10V6K
C171
C172
1
1
2
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
SCHEMATIC M/B LA-9902
SCHEMATIC M/B LA-9902
SCHEMATIC M/B LA-9902
13 52Wednesday, May 08, 2013
13 52Wednesday, May 08, 2013
1
13 52Wednesday, May 08, 2013
B
B
B
of
of
of
5
W=20milsW=20mils
+RTCBATT+RTCVCC
R99
1K_0402_5%
1 2
1
C179
1U_0603_10V4Z
2
D D
+RTCVCC
1 2
R101 1M_0402_5%
1 2
R102 330K_0402_5%
INTVRMEN
H：In
tegrated VRM enable
*
L：Integrated VRM disable
SM_INTRUDER#
PCH_INTVRMEN
(INTVRMEN should always be pull high.)
+3VS
1 2
R105 1K_0402_5%@
HIGH= Enable ( No Reboot )
LOW= Disable (Default)
*
+3V_PCH
C C
R106 1K_0402_5%@
Low = Disabled (Default)
*
High = Enabled [Flash Descriptor Security Overide]
+3V_PCH
R108 1K_0402_5%
This signal has a weak internal pull-down
On Die PLL VR is supplied by
1.5V when smapled high(For mobile only)
1.8V when sampled low(For Desktop only)
*
Needs to be pulled High for Chief River platfrom
HDA_BITCLK_AUDIO<31>
HDA_SYNC_AUDIO<31>
B B
HDA_RST_AUDIO#<31>
HDA_SDOUT_AUDIO<31>
12
12
33_0804_8P4R_5%
For EMI
RP12
HDA_SPKR
ME_FLASH
HDA_SYNC
18
27
36
45
HDA_BIT_CLK
HDA_SYNC_R
HDA_RST#
ME_FLASH
1M_0402_5%
1 2
DPDG1.1
C180
12P_0402_50V8J
NOGCLK@
+RTCVCC
R878
check with vender
Del Q10 check with codec
VDDIO using 3VALW
1U_0603_10V4Z
1 2
R103
20K_0402_5%
1 2
20K_0402_5%
R100
1U_0603_10V4Z
C183
C182
HDA_SPKR<31>
HDA_SDIN0<31>
ME_FLASH<32>
+5VS
@
G
2
Q10
LBSS138LT1G_SOT-23-3
13
D
S
R175
1 2
0_0402_5%
33_0402_5%
22P_0402_50V8J
R124;c190 close to U4.T3 pin
A A
R98
1
2
1
2
1
2
T41
T35
T36
T37
HDA_SYNC
R124
@
C190
@
4
1 2
10M_0402_5%
NOGCLK@
Y1
1 2
NOGCLK@
CMOS
CLRP2
SHO
RT PADS
12
CLRP3
SHO
12
RT PADS
PAD
PAD
PAD
PAD
SPI_CLK_PCH_R
12
PCH_RTCX1
PCH_RTCX2
32.768KHZ_12.5PF_CM31532768DZFT
1
C181
12P_0402_50V8J
NOGCLK@
2
R187
PCH_RTCX1
PCH_RTCX2
PCH_RTCRST#
PCH_SRTCRST#
SM_INTRUDER#
PCH_INTVRMEN
HDA_BIT_CLK
HDA_SYNC
HDA_SPKR
HDA_RST#
HDA_SDIN0
PCH_JTAG_TCK
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO
SPI_CLK_PCH_R
SPI_SB_CS0#
SPI_SB_CS1#
SPI_SI
SPI_SO_R
For EMI
1 2
0_0402_5%
A20
RTCX1
C20
RTCX2
D20
RTCRST#
G22
SRTCRST#
K22
INTRUDER#
C17
INTVRMEN
N34
HDA_BCLK
L34
HDA_SYNC
T10
SPKR
K34
HDA_RST#
E34
HDA_SDIN0
G34
HDA_SDIN1
C34
HDA_SDIN2
A34
HDA_SDIN3
A36
HDA_SDO
C36
HDA_DOCK_EN# / GPIO33
N32
HDA_DOCK_RST# / GPIO13
J3
JTAG_TCK
H7
JTAG_TMS
K5
JTAG_TDI
H1
JTAG_TDO
T3
SPI_CLK
Y14
SPI_CS0#
T1
SPI_CS1#
V4
SPI_MOSI
U3
SPI_MISO
PANTHER-POINT_FCBGA989
HM76@
U4
SA00005MQ80
S IC BD82HM70 SJTNV C1 BGA 989P PCH C38!
GCLK_32K
@
U4A
RTCIHDA
JTAG
SPI
HM70@
3
GCLK_32K
FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3
LPC
FWH4 / LFRAME#
LDRQ0#
LDRQ1# / GPIO23
SERIRQ
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA1RXP
SATA 6G
SATA1TXN
SATA1TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
SATA4RXN
SATA4RXP
SATA4TXN
SATA
SATA4TXP
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
SATAICOMPO
SATAICOMPI
SATA3RCOMPO
SATA3COMPI
SATA3RBIAS
SATALED#
SATA0GP / GPIO21
SATA1GP / GPIO19
PCH_GPIO16<19>
<34>
C38
LPC_AD0
A38
LPC_AD1
B37
LPC_AD2
C37
LPC_AD3
D36
LPC_FRAME#
E36
K36
V5
SERIRQ
SERIRQ
AM3
SATA_DTX_C_IRX_N0
AM1
SATA_DTX_C_IRX_P0
AP7
SATA_ITX_C_DRX_N0
AP5
SATA_ITX_C_DRX_P0
AM10
AM8
AP11
AP10
AD7
SATA_DTX_C_IRX_N2
AD5
SATA_DTX_C_IRX_P2
AH5
SATA_ITX_C_DRX_N2
AH4
SATA_ITX_C_DRX_P2
AB8
AB10
AF3
AF1
Y7
Y5
AD3
AD1
Y3
Y1
AB3
AB1
Y11
Y10
AB12
AB13
AH1
RBIAS_SATA3
P3
SATALED#
V14
P1
BBS_BIT0_R
SATA_COMP
SATA3_COMP
BBS_BIT0_R
SATALED#
PCH_GPIO16
SERIRQ
LPC_AD0
<32>
LPC_AD1
<32>
<32>
LPC_AD2
LPC_AD3
<32>
LPC_FRAME#
SERIRQ
R111
37.4_0402_1%
1 2
R113
49.9_0402_1%
1 2
1 2
R115
750_0402_1%
GPIO19 has internal Pull UP
+3V_ROM
1 2
R266
1 2
R221
1 2
R127
1 2
R129
RP17
18
27
36
45
10K_0804_8P4R_5%
EC and Mini card debug port
<32>
<32>
SATA_DTX_C_IRX_N0
SATA_DTX_C_IRX_P0
SATA_ITX_C_DRX_N0
SATA_ITX_C_DRX_P0
SATA_DTX_C_IRX_N2
SATA_DTX_C_IRX_P2
SATA_ITX_C_DRX_N2
SATA_ITX_C_DRX_P2
11/30 Add(Share ROM)
+V1.05S_VCCP
+V1.05S_VCCP
SPI_WP#1
3.3K_0402_5%
SPI_HOLD#1
3.3K_0402_5%
SPI_WP#
3.3K_0402_5%
SPI_HOLD#
3.3K_0402_5%
+3VS
2
<30>
<30>
<30>
<30>
<30>
<30>
<30>
<30>
EC_SPI_SO<32>
EC_SPI_SI<32>
EC_SPI_CLK<32>
EC_SPI_CS#<32>
SPI_SB_CS1#
SPI_SO_R
SPI_SB_CS0#
1 2
R188
For EMI
R131
For EMI
HDD
ODD
EC_SPI_SO
EC_SPI_SI
EC_SPI_CLK
0_0804_8P4R_5%
8MB SPI ROM FOR ME
& Non-share ROM.
U6
1
CS#
@
0_0402_5%
1 2
@
0_0402_5%
SPI_SO1
2
SO
3
SPI_WP#1
WP#
4
GND
64M W25Q64FVSSIQ SOIC 8P
@
U6 Rersver 4M+2M Solution
U5
1
CS#
SPI_SO_L
SPI_WP#
2
SO
3
WP#
4
GND
64M W25Q64FVSSIQ SOIC 8P
RP27
@
VCC
HOLD#
SCLK
HOLD#
Near U5
18
27
36
45
SI
VCC
SCLK
SI
+3V_ROM
8
7
SPI_HOLD#1
6
SPI_CLK_PCH_1
5
SPI_SI1
8
7
6
5
1
SPI_SO_L
SPI_SI_R
SPI_CLK_PCH_0
SPI_SB_CS0#EC_SPI_CS#
+3V_ROM
SPI_HOLD#SPI_SO_R
SPI_CLK_PCH_0
SPI_SI_R
0_0402_5%
R198
1 2
@
1 2
@
R196
0_0402_5%
For EMI
0_0402_5%
R135
1 2
1 2
R133
0_0402_5%
For EMI
@
@
SPI_CLK_PCH_R
SPI_SI
SPI_CLK_PCH_R
SPI_SI
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/06/15 2012/07/11
2011/06/15 2012/07/11
2011/06/15 2012/07/11
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Title
Title
Title
SCHEMATIC M/B LA-9902
SCHEMATIC M/B LA-9902
SCHEMATIC M/B LA-9902
Document Number Rev
Document Number Rev
Document Number Rev
Size
Size
Size
Custom
Custom
Custom
4019N1
4019N1
4019N1
Date: Sheet
Date: Sheet
2
Date: Sheet
14 52Wednesday, May 08, 2013
14 52Wednesday, May 08, 2013
14 52Wednesday, May 08, 2013
1
B
B
B
of
of
of
5
LAN
WLAN
D D
C C
LAN
WLAN
B B
PCIE_PRX_DTX_N1<27>
PCIE_PRX_DTX_P1<27>
PCIE_PTX_C_DRX_N1<27>
PCIE_PTX_C_DRX_P1<27>
PCIE_PRX_DTX_N2<26>
PCIE_PRX_DTX_P2<26>
PCIE_PTX_C_DRX_N2<26>
PCIE_PTX_C_DRX_P2<26>
CLK_PCIE_LAN#<27>
CLK_PCIE_LAN<27>
CLKREQ_LAN#<27>
CLK_PCIE_WLAN1#<26>
CLK_PCIE_WLAN1<26>
CLKREQ_WLAN#<26>
+3V_PCH
+3VS
1 2
C192 0.1U_0402_10V7K
1 2
C193 0.1U_0402_10V7K
1 2
C194 0.1U_0402_10V7K
1 2
C195 0.1U_0402_10V7K
1 2
R153 0_0402_5%@
1 2
R154 0_0402_5%@
R152 10K_0402_5%
1 2
R156 0_0402_5%@
1 2
R165 0_0402_5%@
R158 10K_0402_5%
12
12
For EMI
For EMI
4
PCIE_PRX_DTX_N1
PCIE_PRX_DTX_P1
PCIE_PTX_DRX_N1
PCIE_PTX_DRX_P1
PCIE_PRX_DTX_N2
PCIE_PRX_DTX_P2
PCIE_PTX_DRX_N2
PCIE_PTX_DRX_P2
CLK_PCIE_LAN#_R
CLK_PCIE_LAN_R
CLK_PCIE_WLAN1#_R
CLK_PCIE_WLAN1_R
PCIE_CLK_8N
PCIE_CLK_8P
U4B
BG34
PERN1
BJ34
PERP1
AV32
PETN1
AU32
PETP1
BE34
PERN2
BF34
PERP2
BB32
PETN2
AY32
PETP2
BG36
PERN3
BJ36
PERP3
AV34
PETN3
AU34
PETP3
BF36
PERN4
BE36
PERP4
AY34
PETN4
BB34
PETP4
BG37
PERN5
BH37
PERP5
AY36
PETN5
BB36
PETP5
BJ38
PERN6
BG38
PERP6
AU36
PETN6
AV36
PETP6
BG40
PERN7
BJ40
PERP7
AY40
PETN7
BB40
PETP7
BE38
PERN8
BC38
PERP8
AW38
PETN8
AY38
PETP8
Y40
CLKOUT_PCIE0N
Y39
CLKOUT_PCIE0P
J2
PCIECLKRQ0# / GPIO73
AB49
CLKOUT_PCIE1N
AB47
CLKOUT_PCIE1P
M1
PCIECLKRQ1# / GPIO18
AA48
CLKOUT_PCIE2N
AA47
CLKOUT_PCIE2P
V10
PCIECLKRQ2# / GPIO20
Y37
CLKOUT_PCIE3N
Y36
CLKOUT_PCIE3P
A8
PCIECLKRQ3# / GPIO25
Y43
CLKOUT_PCIE4N
Y45
CLKOUT_PCIE4P
L12
PCIECLKRQ4# / GPIO26
V45
CLKOUT_PCIE5N
V46
CLKOUT_PCIE5P
L14
PCIECLKRQ5# / GPIO44
AB42
CLKOUT_PEG_B_N
AB40
CLKOUT_PEG_B_P
E6
PEG_B_CLKRQ# / GPIO56
V40
CLKOUT_PCIE6N
V42
CLKOUT_PCIE6P
T13
PCIECLKRQ6# / GPIO45
V38
CLKOUT_PCIE7N
V37
CLKOUT_PCIE7P
K12
PCIECLKRQ7# / GPIO46
AK14
CLKOUT_ITPXDP_N
AK13
CLKOUT_ITPXDP_P
PANTHER-POINT_FCBGA989
HM76@
SMBUSController
SML1ALERT# / PCHHOT# / GPIO74
PCI-E*
CLOCKS
3
SMBALERT# / GPIO11
SML0ALERT# / GPIO60
SML1CLK / GPIO58
SML1DATA / GPIO75
Link
PEG_A_CLKRQ# / GPIO47
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
CLKOUT_DMI_N
CLKOUT_DMI_P
CLKOUT_DP_N
CLKOUT_DP_P
CLKIN_DMI_N
CLKIN_DMI_P
CLKIN_GND1_N
CLKIN_GND1_P
CLKIN_DOT_96N
CLKIN_DOT_96P
CLKIN_SATA_N
CLKIN_SATA_P
REFCLK14IN
CLKIN_PCILOOPBACK
XTAL25_OUT
XCLK_RCOMP
CLKOUTFLEX0 / GPIO64
CLKOUTFLEX1 / GPIO65
CLKOUTFLEX2 / GPIO66
CLKOUTFLEX3 / GPIO67
FLEX CLOCKS
E12
H14
SMBCLK
C9
SMBDATA
A12
C8
SML0CLK
G12
SML0DATA
C13
E14
M16
M7
CL_CLK1
T11
CL_DATA1
P10
CL_RST1#
M10
AB37
AB38
AV22
AU22
AM12
AM13
BF18
BE18
BJ30
BG30
G24
E24
AK7
AK5
K45
H45
V47
XTAL25_IN
V49
Y47
K43
F47
H47
K49
BIOS Request SKU ID
PCH_GPIO11
R134 10K_0402_5%
PCH_SMBCLK
PCH_SMBDATA
DRAMRST_CNTRL_PCH
PCH_SML0CLK
PCH_SML0DATA
PCH_HOT#
SML1CLK
SML1DATA
+3V_PCH
1 2
CLK_CPU_DMI#
CLK_CPU_DMI
CLK_BUF_CPU_DMI#
CLK_BUF_CPU_DMI
CLKIN_DMI2#
CLKIN_DMI2
CLK_BUF_DREF_96M#
CLK_BUF_DREF_96M
CLK_BUF_PCIE_SATA#
CLK_BUF_PCIE_SATA
CLK_BUF_ICH_14M
CLK_PCI_LPBACK
XTAL25_IN
XTAL25_OUT
XCLK_RCOMP
27M_SSC
PCH_GPIO67
12
R143
10K_0402_5%
CLK_CPU_DMI#
CLK_CPU_DMI
1 8
2 7
3 6
4 5
1 2
R162 10K_0402_5%
1 2
R163 10K_0402_5%
1 2
R164 10K_0402_5%
1 2
R166 10K_0402_5%
1 2
R167 10K_0402_5%
R171
90.9_0402_1%
1 2
PCH_GPIO67
+3V_PCH
1K_0402_5%
R140
RP8 10K_0804_8P4R_5%
CLK_PCI_LPBACK
12
@
For EMI
B Phaes change to GCLK@
<19>
2
12
R139
12
10K_0402_5%
<6>
<6>
<18>
GCLK_PCH_25MHZ
R7960_0402_5%
+V1.05S_VCCP
DRAMRST_CNTRL_PCH
+3V_PCH
+3V_PCH
GCLK_PCH_25MHZ
<10,7>
XTAL25_IN
XTAL25_OUT
C196
12P_0402_50V8J
NOGCLK@
Q60A
2N7002DW-T/R7_SOT363-6
6 1
3
6 1
3
SMB_CLK_S3
2
+3VS
5
4
SMB_DATA_S3
2N7002DW-T/R7_SOT363-6
Q60B
Q61A
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
Q61B
EC_SMB_CK2
2
+3VS
5
4
EC_SMB_DA2
<34>
1 2
R169
3
2
Y2
25MHZ_10PF_7V25000014
1
NOGCLK@
2
SML1DATA
EC_SMB_DA2
SML1CLK
EC_SMB_CK2
PCH_SMBCLK
SMB_CLK_S3
PCH_SMBDATA
SMB_DATA_S3
NOGCLK@
1M_0402_5%
OSC
NC
1
SMB_CLK_S3
DIMM1
DIMM2
MINI CARD
SMB_DATA_S3
EC_SMB_CK2
VGA
EC
thermal sensor
EC_SMB_DA2
2.2K_0402_5%
PCH_SML0CLK
PCH_SML0DATA
2.2K_0804_8P4R_5%
2.2K_0804_8P4R_5%
4
NC
1
OSC
1
12P_0402_50V8J
2
<29,32>
<29,32>
R544
1 2
RP23
RP24
C197
NOGCLK@
<12,13,26>
<12,13,26>
+3V_PCH
1 2
+3V_PCH
18
27
36
45
+3V_PCH
18
27
36
45
R545
2.2K_0402_5%
+3VS
+3VS
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/06/15 2012/07/11
2011/06/15 2012/07/11
2011/06/15 2012/07/11
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Title
Title
Title
Size
Size
Size
Custom
Custom
Custom
Date: Sheet
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC M/B LA-9902
SCHEMATIC M/B LA-9902
SCHEMATIC M/B LA-9902
Document Number Rev
Document Number Rev
Document Number Rev
4019N1
4019N1
4019N1
1
15 52Wednesday, May 08, 2013
15 52Wednesday, May 08, 2013
15 52Wednesday, May 08, 2013
of
of
of
B
B
B
5
D D
U15
MC74VHC1G08DFT2G SC70 5P
3
@
VGATE<32,44>
PCH_PWROK
C854
0.1U_0402_16V4Z
1
G
A
4
SYS_PWROK
Y
2
B
+3VS
P
5
2
1
3/20 Add (ESD request)
C C
PCH_PWROK<32>
PM_DRAM_PWRGD<6>
+3V_PCH
12
300_0402_5%
B B
R194 10K_0402_5%
R197 10K_0402_5%@
+3V_PCH
R309 200K_0402_5%
R192
12
12
1 2
PM_DRAM_PWRGD
SUSWARN#
EC_RSMRST#
AC_PRESENT_R
EC_RSMRST#<32>
PBTN_OUT#<32>
ACIN<32,37,39>
4
DMI_CTX_PRX_N0<5>
DMI_CTX_PRX_N1<5>
DMI_CTX_PRX_N2<5>
DMI_CTX_PRX_N3<5>
DMI_CTX_PRX_P0<5>
DMI_CTX_PRX_P1<5>
DMI_CTX_PRX_P2<5>
DMI_CTX_PRX_P3<5>
DMI_CRX_PTX_N0<5>
DMI_CRX_PTX_N1<5>
DMI_CRX_PTX_N2<5>
DMI_CRX_PTX_N3<5>
DMI_CRX_PTX_P0<5>
DMI_CRX_PTX_P1<5>
DMI_CRX_PTX_P2<5>
DMI_CRX_PTX_P3<5>
+V1.05S_VCCP
SUSACK# is only used on platform
that support the Deep Sx state.
D29
CH751H-40PT_SOD323-2
1 2
R177 49.9_0402_1%
1 2
R178 750_0402_1%
4mil width and place
within 500mil of the PCH
SYS_RST#<19>
SYS_PWROK<32>
21
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
DMI_IRCOMP
RBIAS_CPY
SYS_RST#
SYS_PWROK
PCH_PWROK
PM_DRAM_PWRGD
SUSWARN#
AC_PRESENT_R
RI#
U4C
BC24
DMI0RXN
BE20
DMI1RXN
BG18
DMI2RXN
BG20
DMI3RXN
BE24
DMI0RXP
BC20
DMI1RXP
BJ18
DMI2RXP
BJ20
DMI3RXP
AW24
DMI0TXN
AW20
DMI1TXN
BB18
DMI2TXN
AV18
DMI3TXN
AY24
DMI0TXP
AY20
DMI1TXP
AY18
DMI2TXP
AU18
DMI3TXP
BJ24
DMI_ZCOMP
BG25
DMI_IRCOMP
BH21
DMI2RBIAS
C12
SUSACK#
K3
SYS_RESET#
P12
SYS_PWROK
L22
PWROK
L10
APWROK
B13
DRAMPWROK
C21
RSMRST#
K16
SUSWARN#/SUSPWRDNACK/GPIO30
E20
PWRBTN#
H20
ACPRESENT / GPIO31
E10
BATLOW# / GPIO72
A10
RI#
PANTHER-POINT_FCBGA989
HM76@
3
BJ14
FDI_RXN0
AY14
FDI_RXN1
BE14
FDI_RXN2
BH13
FDI_RXN3
BC12
FDI_RXN4
BJ12
FDI_RXN5
BG10
FDI_RXN6
BG9
FDI_RXN7
BG14
FDI_RXP0
BB14
FDI_RXP1
BF14
FDI_RXP2
BG13
FDI_RXP3
BE12
FDI_RXP4
BG12
FDI_RXP5
BJ10
FDI_RXP6
DMI
FDI
CLKRUN# / GPIO32
SUS_STAT# / GPIO61
SUSCLK / GPIO62
SLP_S5# / GPIO63
System Power Management
SLP_LAN# / GPIO29
FDI_RXP7
FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
DSWVRMEN
DPWROK
WAKE#
SLP_S4#
SLP_S3#
SLP_A#
SLP_SUS#
PMSYNCH
BH9
AW16
AV12
BC10
AV14
BB10
A18
E22
B9
N3
G8
N14
D10
H4
F4
G10
G16
AP14
K14
2
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
DSWODVREN
EC_RSMRST#
PM_CLKRUN#
SUS_STAT#
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3 <5>
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>
Note:This signal must be always pulled-up to VccRTC.
PCIE_WAKE#
PAD
T38
SUSCLK
PM_SLP_S5# <32>
PM_SLP_S4#
PM_SLP_S3#
<26>
<32>
<32>
<32>
Can be left NC when IAMT is not support on the platfrom
H_PM_SYNC
H_PM_SYNC
<6>
Can be left NC if no use integrated LAN.
1
DSWODVREN
*
R299
R179 330K_0402_5%
DSWODVREN - On Die DSW VR Enable
H
：
Enable
L
：
Disable
10K_0402_5%
12
+RTCVCC
12
+3V_PCH
RP25
18
A A
10K_0804_8P4R_5%
27
36
45
5
PCIE_WAKE#
RI#
EC_SMI#
EC_SMI#
<19,32>
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/06/15 2012/07/11
2011/06/15 2012/07/11
2011/06/15 2012/07/11
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Title
Title
Title
Size
Size
Size
Custom
Custom
Custom
Date: Sheet
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC M/B LA-9902
SCHEMATIC M/B LA-9902
SCHEMATIC M/B LA-9902
Document Number Rev
Document Number Rev
Document Number Rev
4019N1
4019N1
4019N1
1
16 52Wednesday, May 08, 2013
16 52Wednesday, May 08, 2013
16 52Wednesday, May 08, 2013
of
of
of
B
B
B
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