Lenovo G400, G500, G490 Schematic
A
1 1
B
C
D
E
Compal Confidential
2 2
Gx00/Gx00 DIS M/B Schematics Document
Intel Ivy Bridge Processor with DDRIII + Panther Point PCH
AMD Mars XT / SUN Pro
2013-02-27
3 3
LA-9631P
REV:1.0
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
C
2011/06/15 2012/07/11
2011/06/15 2012/07/11
2011/06/15 2012/07/11
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
Cover Page
Cover Page
Cover Page
LA-9631P
LA-9631P
LA-9631P
E
1 60Wednesday, February 27, 2013
1 60Wednesday, February 27, 2013
1 60Wednesday, February 27, 2013
1.0
1.0
1.0
A
B
C
D
E
Compal confidential
Project Name : VIWGP (14") / VIWGR (15")
Chief River
1 1
AMD MARS XT M2 128 bits
/ SUN PRO M2 64 bits
VRAM 512MB/1GB/2GB
MARS XT : DDR3 x 8
SUN PRO : DDR3 x 4
Page 23~32
PEG 8x
Gen2 / Gen3
Intel
Processor
Ivy Bridge
rPGA989
37.5mm x 37.5mm
Page 5~11
Memory Bus
Dual Channel
DDR3
DDR3
DDR3
1600MHz
1333MHz
1066MHz
204pin DDRIII-SO-DIMM X2
BANK 0, 1, 2
Page 12, 13
FDI *8
2.7GT/s
2 2
LVDS Conn.
Page 33
HDMI Conn.
Page 35
CRT Conn.
Page 34
Intel
DMI2 *4
5GT/s
USB30 x2
USB20 x6
Left USB3.0 x2
USB30 Port 0,1
Page 45
Touch Screen
USB20 Port 2
Page 45
Right USB2.0
USB20 Port 9
Card Reader
Realtek RTS5170
USB20 Port 11
Page 45
page 28
Int. Camera
USB20 Port 3
Page 33
PCH
Page 43
HDD Conn.
SATA Port 0
Page 40
ODD Conn.
SATA Port 2
Audio Codec
CONEXANT
CX20757
Page 40
Page 41
Int. MIC Conn.
Page 41
Int. KBD
Page 43
D
Int. Speaker Conn.
Page 41
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Audio Combo Jacks
HP & MIC
MB Block Diagram
MB Block Diagram
MB Block Diagram
LA-9631P
LA-9631P
LA-9631P
E
2 60Wednesday, February 27, 2013
2 60Wednesday, February 27, 2013
2 60Wednesday, February 27, 2013
Page 41
1.0
1.0
1.0
RJ45 Conn.
Page 38
LAN
PCIe Port 0
Atheros
AR8162/QCA8172(10/100)
Page 37
PCIe x1
Panther Point
FCBGA 989Balls
25mm x 25mm
3 3
PCIe Mini Card
WLAN
PCIe Port 1
Page 36
PCIe x1
Page 14~22
SATA Gen3
SATA
AZALIA
Sub-borad
15"
14"
Power/B
(LID)
4 4
LS9631
USB/B
LS9632 LS9634
IO/B
(Card Reader) (LED, LID)
LS9633
ODD/B
Switch/B
A
LS9635
B
SPI ROM
2MB + 4MB
Page 14
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
EC
ENE KB9012
Page 42
Thermal Sensor
C
Page 39
2011/06/15 2012/07/11
2011/06/15 2012/07/11
2011/06/15 2012/07/11
Touch Pad
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
A
B
C
D
E
Voltage Rails
+5VS
power
State
S0
S3
S5 S4/AC
plane
Address
0001 011x
1010 000x A0h
1010 010x A4h
+B
O
O
O
O
X
+5VALW
+3VALW
O
O
O
X
X X X
+1.5V
O
X X
X
EC SM Bus2 address
Device
Thermal Sen sor
AMD-GPU SM Bus address
Device Address
Internal thermal sensor
1 1
2 2
S5 S4/ Battery only
S5 S4/AC & Battery
don't exist
EC SM Bus1 address
Device
Smart Battery
PCH SM Bus address
3 3
Device Address
DDR_JDIMM1
DDR_JDIMM2
+3VS
+1.5VS
+V1.05S_VCCP
+VCC_CORE
+VGA_CORE
+VCC_GFXCORE_AXG
+1.8VS
+0.75VS
+1.05VS
OO
X
X
Address
0100 1100
0100 0001 41h
BOARD ID Table
Board ID
0
1
2
3
4
5
6
7
USB Port Table
EHCI1
EHCI2
PCB Revision
0.1
USB 2.0 Port
UHCI0
UHCI1
UHCI2
UHCI3
UHCI4
UHCI5
UHCI6
0
1
2
3
4
5
6
7
8
9
10
11
12
13
STATE
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
Vcc
R694
Board ID
0
1
2
3
SIGNAL
3.3V
100K +/- 1%
R695 V
0
12K +/- 1%
15K +/- 1%
20K +/- 1%
SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
HIGH HIGH HIGH HIGH
Board ID / SKU ID Table for AD channel
AD_BID
0.347V 0.354V 0.360V
0.423V
0.541V
3 External
USB Port
USB Port (Left Side)
USB Port (Left Side)
USB3.0
USB3.0
Touch Screen
Camera
USB Port (Right Side USB-BD)
Mini Card(WLAN)
Card Reader
LOW
LOW
LOW
LOW LOW LOW LOW
min
V
AD_BID
HIGH
LOWLOWLOW
typ
HIGHHIGHHIGH
HIGH
HIGH
V
AD_BID
0 V 0 V 0 V
0.430V
0.550V
0.438V
0.559V
BOM Structure Table
VIWGP (14") 14@
VIWGR (15") 15@
LAN 10/100 8172@
LAN Switch mode SWR@
LAN LDO Mode LDO@
Camera CMOS@
HDMI HDMI@
PCH is HM76
PCH is HM70
PCH is NM70
VGA is Mars XT
VGA is Sun Pro
For VGA PX@
For VRAM and Strap
Item BOM Structure
ON
ON
ON
ON
ON
max
0x00 - 0x0B
0x0C - 0x1C
0x27 - 0x30
ON
ON
ON
OFF
OFF
EC AD
45@HDMI Logo
8162@LAN 10/100
GAS@LAN Gas tube
HM76@
HM70@
NM70@
Mars@
Sun@
X76@
ON ON
ON
OFF
OFF
OFF
MP
PVT
DVT0x1D - 0x26
EVT
LOW
OFF
OFF
OFF
For UMA Strap UMA@
MIC@Microphone
Touch Screen
SMBUS Control Table
X
XX
V
+3VS
X
Thermal
Sensor
+3VS
+3VS
B
SOURCE
SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2
4 4
PCH_SMBCLK
PCH_SMBDATA
PCH_SML0CLK
PCH_SML0DATA
SML1CLK
SML1DATA
KB9012
+3VALW
KB9012
+3VS
PCH
+3VALW
PCH
+3VALW
PCH
+3VALW
VGA BATT KB9012 SODIMM
X V
+3VALW
V
+3VGS
X
X
V
+3VGS
A
X
X
X
+3VS
WLAN
X
X
X
X
X
V
+3VS
X
V
PCH
X
V
X
XX
V
X
V
+3VALW
X
X
XX X
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
C
2011/06/15 2012/07/11
2011/06/15 2012/07/11
2011/06/15 2012/07/11
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Connector ME@
Board ID for EVT
Board ID for DVT DVT@
Board ID for PVT PVT@
For USB3.0 (HM76,HM70) USB3@
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
LA-9631P
LA-9631P
LA-9631P
Date: Sheet of
Date: Sheet of
Date: Sheet of
TS@
EVT@
USB2@For USB2.0 (All PCH)
SROM@For share ROM
NOSROM@For non-share ROM
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Notes List
Notes List
Notes List
3 60Wednesday, February 27, 2013
3 60Wednesday, February 27, 2013
3 60Wednesday, February 27, 2013
E
1.0
1.0
1.0
5
4
3
2
1
Power-Up/Down Sequence
Mars XT VRAM STRAP
Vendor
UV5, UV6, UV7, UV8
UV9, UV10, UV11, UV12
Samsung 2048Mbits
ZZZ4
D D
2GBytes
2GBytes
2GBytes
1GBytes
2GBytes 1 0 0
1GBytes
ZZZ4
ZZZ4
C C
Samsung_2G
Samsung_2G
MS2G@
MS2G@
X7646738L01
X7646738L01
SA000068U00
128Mx16 K4W2G1646E-BC1A
MS2G@
Micron 2048Mbits
ZZZ5
SA000067500
128Mx16 MT41J128M16JT-093G:K
MM2G@
Hynix 2048Mbits
ZZZ6
SA000065300
128M16 H5TQ2G63DFR-N0C
MH2G@
Samsung 1028Mbits
ZZZ7
SA00004GS00
64Mx16 K4W1G1646G-BC11
MS1G@
Hynix 2048Mbits
ZZZ15
SA00006H400
128Mx16 H5TC2G63FFR-11C
MH2GN@
Hynix 1024Mbits
ZZZ8
SA000041SB0
64Mx16 H5TQ1G63EFR-11C
MH1G@
ZZZ5
ZZZ5
Micron_2G
Micron_2G
MM2G@
MM2G@
X7646738L02
X7646738L02
ZZZ6
ZZZ6
Hynix_2G
Hynix_2G
MH2G@
MH2G@
X7646738L09
X7646738L09
ID
0
1
2
3
4
7
ZZZ15
ZZZ15
Hynix_2G
Hynix_2G
MH2GN@
MH2GN@
X7646738L10
X7646738L10
0 0
0 1 1
ZZZ7
ZZZ7
Samsung_1G
Samsung_1G
MS1G@
MS1G@
X7646738L03
X7646738L03
PS_3[ 1 ]PS_3[ 2 ]PS_3[ 3 ]
0
10 0
00 1
1 1 4.75K NC1
ZZZ8
ZZZ8
Hynix_1G
Hynix_1G
MH1G@
MH1G@
X7646738L04
X7646738L04
X76@X76@
R_pu R_pd
RV20 RV27
NC 4.75K
8.45K 2K
4.53K 2K
6.98K 4.99K
4.53K 4.99K
"Mars" has the following requirements with regards to power-supply
sequencing to avoid damaging the ASIC:
All the ASIC supplies must reach their respective nominal voltages within 20 ms
of the start of the ramp-up sequence, though a shorter ramp-up duration is
preferred. The maximum slew rate on all rails is 50 mV/µs.
The external pull ups on the DDC/AUX signals (if applicable) should ramp up
before or after both VDDC and VDD_CT have ramped up.
VDDC and VDD_CT should not ramp up simultaneously. For example, VDDC
should reach 90% before VDD_CT starts to ramp up (or vice versa).
For power down, reversing the ramp-up sequence is recommended.
VDDR3(3.3VGS)
PCIE_VDDC(0.95VGSV)
VDDR1(1.5VGS)
VDDC/VDDCI(1.12V)
VDD_CT(1.8V)
PERSTb
Sun PRO VRAM STRAP
Vendor
UV9, UV10, UV11, UV12
Samsung 4096Mbits
ZZZ9
2GBytes
2GBytes
B B
2GBytes
1GBytes
1GBytes
1GBytes
1GBytes
ZZZ9
ZZZ9
A A
Samsung_2G
Samsung_2G
SS2G@
SS2G@
X7646738L05
X7646738L05
SA000068R00
256Mx16 K4W4G1646B-HC11
SS2G@
Micron 4096Mbits
ZZZ10
SA000065D00
256Mx16/1866 MT41K256M16HA-107G:E
SM2G@
Hynix 4096Mbits
ZZZ11
SA00006DG00
256MX16 H5TQ4G63MFR-11C
SH2G@
Samsung 2048Mbits
ZZZ12
SA000068U00
128Mx16 K4W2G1646E-BC1A
SS1G@
Hynix 2048Mbits
ZZZ16
SA00006H400
128Mx16 H5TC2G63FFR-11C
SH1GN@
Micron 2048Mbits
ZZZ13
SA000067500
128Mx16 MT41J128M16JT-093G:K
SM1G@
Hynix 2048Mbits
ZZZ14
SA000065300
128M16 H5TQ2G63DFR-N0C
SH1G@
ZZZ10
ZZZ10
Micron_2G
Micron_2G
SM2G@
SM2G@
X7646738L06
X7646738L06
5
ZZZ11
ZZZ11
Hynix_2G
Hynix_2G
SH2G@
SH2G@
X7646738L11
X7646738L11
ID
0
1
2
3
4
6
7
ZZZ12
ZZZ12
Samsung_1G
Samsung_1G
SS1G@
SS1G@
X7646738L07
X7646738L07
0 0
0 1 1
1
ZZZ13
ZZZ13
Micron_1G
Micron_1G
SM1G@
SM1G@
X7646738L08
X7646738L08
4
PS_3[ 1 ]PS_3[ 2 ]PS_3[ 3 ]
1 0
1 11
0
10 0
00 1
001 4.99K4.53K
ZZZ14
ZZZ14
Hynix_1G
Hynix_1G
SH1G@
SH1G@
X7647538L01
X7647538L01
X76@X76@
R_pu R_pd
RV20 RV27
NC 4.75K
8.45K 2K
4.53K 2K
6.98K 4.99K
3.4K 10K
4.75K NC
ZZZ16
ZZZ16
Hynix_1G
Hynix_1G
SH1GN@
SH1GN@
X7646738L13
X7646738L13
Security Classification
Security Classification
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
REFCLK
Straps Reset
Straps Valid
Global ASIC Reset
Issued Date
Issued Date
Issued Date
Compal Secret Data
Compal Secret Data
2011/06/15 2012/07/11
2011/06/15 2012/07/11
2011/06/15 2012/07/11
3
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
T4+16clock
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
VGA Notes List
VGA Notes List
VGA Notes List
LA-9631P
LA-9631P
LA-9631P
4 60Wednesday, February 27, 2013
4 60Wednesday, February 27, 2013
4 60Wednesday, February 27, 2013
1
1.0
1.0
1.0
5
ZZZ1
14@
ZZZ1
14@
14"_DIS_PCB_LA9631P
14"_DIS_PCB_LA9631P
DA6000WO000
DA6000WO000
PCB 0N1 LA-9631P REV0 M/B DIS 3
PCB 0N1 LA-9631P REV0 M/B DIS 3
D D
C C
B B
eDP_COMPIO and ICOMPO signals
should be shorted near balls
and routed with typical
impedance <25 mohms
ZZZ2
15@
ZZZ2
15@
15"_DIS_PCB_LA9631P
15"_DIS_PCB_LA9631P
DA6000WO100
DA6000WO100
PCB 0N2 LA-9631P REV0 M/B DIS 5
PCB 0N2 LA-9631P REV0 M/B DIS 5
+V1.05S_VCCP
12
R7
R7
24.9_0402_1%
24.9_0402_1%
DMI_CRX_PTX_N0<16>
DMI_CRX_PTX_N1<16>
DMI_CRX_PTX_N2<16>
DMI_CRX_PTX_N3<16>
DMI_CRX_PTX_P0<16>
DMI_CRX_PTX_P1<16>
DMI_CRX_PTX_P2<16>
DMI_CRX_PTX_P3<16>
DMI_CTX_PRX_N0<16>
DMI_CTX_PRX_N1<16>
DMI_CTX_PRX_N2<16>
DMI_CTX_PRX_N3<16>
DMI_CTX_PRX_P0<16>
DMI_CTX_PRX_P1<16>
DMI_CTX_PRX_P2<16>
DMI_CTX_PRX_P3<16>
FDI_CTX_PRX_N0<16>
FDI_CTX_PRX_N1<16>
FDI_CTX_PRX_N2<16>
FDI_CTX_PRX_N3<16>
FDI_CTX_PRX_N4<16>
FDI_CTX_PRX_N5<16>
FDI_CTX_PRX_N6<16>
FDI_CTX_PRX_N7<16>
FDI_CTX_PRX_P0<16>
FDI_CTX_PRX_P1<16>
FDI_CTX_PRX_P2<16>
FDI_CTX_PRX_P3<16>
FDI_CTX_PRX_P4<16>
FDI_CTX_PRX_P5<16>
FDI_CTX_PRX_P6<16>
FDI_CTX_PRX_P7<16>
FDI_FSYNC0<16>
FDI_FSYNC1<16>
FDI_INT<16>
FDI_LSYNC0<16>
FDI_LSYNC1<16>
EDP_COMP
eDP_HPD
4
JCPU1A
JCPU1A
B27
DMI_RX#[0]
B25
DMI_RX#[1]
A25
DMI_RX#[2]
B24
DMI_RX#[3]
B28
DMI_RX[0]
B26
DMI_RX[1]
A24
DMI_RX[2]
B23
DMI_RX[3]
G21
DMI_TX#[0]
E22
DMI_TX#[1]
F21
DMI_TX#[2]
D21
DMI_TX#[3]
G22
DMI_TX[0]
D22
DMI_TX[1]
F20
DMI_TX[2]
C21
DMI_TX[3]
A21
FDI0_TX#[0 ]
H19
FDI0_TX#[1 ]
E19
FDI0_TX#[2 ]
F18
FDI0_TX#[3 ]
B21
FDI1_TX#[0 ]
C20
FDI1_TX#[1 ]
D18
FDI1_TX#[2 ]
E17
FDI1_TX#[3 ]
A22
FDI0_TX[0]
G19
FDI0_TX[1]
E20
FDI0_TX[2]
G18
FDI0_TX[3]
B20
FDI1_TX[0]
C19
FDI1_TX[1]
D19
FDI1_TX[2]
F17
FDI1_TX[3]
J18
FDI0_FSYNC
J17
FDI1_FSYNC
H20
FDI_INT
J19
FDI0_LSYNC
H17
FDI1_LSYNC
A18
eDP_COMP IO
A17
eDP_ICOMPO
B16
eDP_HPD#
C15
eDP_AUX
D15
eDP_AUX#
C17
eDP_TX[0]
F16
eDP_TX[1]
C16
eDP_TX[2]
G15
eDP_TX[3]
C18
eDP_TX#[0 ]
E16
eDP_TX#[1 ]
D16
eDP_TX#[2 ]
F15
eDP_TX#[3 ]
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
ME@
ME@
PEG_RX[0 ]
PEG_RX[1 ]
PEG_RX[2 ]
PEG_RX[3 ]
PEG_RX[4 ]
PEG_RX[5 ]
PEG_RX[6 ]
PEG_RX[7 ]
PEG_RX[8 ]
PEG_RX[9 ]
PEG_TX[0 ]
PEG_TX[1 ]
PEG_TX[2 ]
PEG_TX[3 ]
PEG_TX[4 ]
PEG_TX[5 ]
PEG_TX[6 ]
PEG_TX[7 ]
PEG_TX[8 ]
PEG_TX[9 ]
J22
J21
H22
K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32
J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32
M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25
M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25
PEG_ICOMPI
PEG_ICOMPO
PEG_RCO MPO
PEG_RX# [0]
PEG_RX# [1]
PEG_RX# [2]
PEG_RX# [3]
PEG_RX# [4]
PEG_RX# [5]
PEG_RX# [6]
DMI
DMI
Intel(R) FDI
Intel(R) FDI
eDP
eDP
PEG_RX# [7]
PEG_RX# [8]
PEG_RX# [9]
PEG_RX# [10]
PEG_RX# [11]
PEG_RX# [12]
PEG_RX# [13]
PEG_RX# [14]
PEG_RX# [15]
PEG_RX[1 0]
PEG_RX[1 1]
PEG_RX[1 2]
PEG_RX[1 3]
PEG_RX[1 4]
PEG_RX[1 5]
PEG_TX# [0]
PEG_TX# [1]
PEG_TX# [2]
PEG_TX# [3]
PEG_TX# [4]
PEG_TX# [5]
PEG_TX# [6]
PEG_TX# [7]
PEG_TX# [8]
PEG_TX# [9]
PEG_TX# [10]
PEG_TX# [11]
PEG_TX# [12]
PCI EXPRESS* - GRAPHICS
PCI EXPRESS* - GRAPHICS
PEG_TX# [13]
PEG_TX# [14]
PEG_TX# [15]
PEG_TX[1 0]
PEG_TX[1 1]
PEG_TX[1 2]
PEG_TX[1 3]
PEG_TX[1 4]
PEG_TX[1 5]
3
PEG_COMP
PCIE_CRX_GTX_N7
PCIE_CRX_GTX_N6
PCIE_CRX_GTX_N5
PCIE_CRX_GTX_N4
PCIE_CRX_GTX_N3
PCIE_CRX_GTX_N2
PCIE_CRX_GTX_N1
PCIE_CRX_GTX_N0
PCIE_CRX_GTX_P7
PCIE_CRX_GTX_P6
PCIE_CRX_GTX_P5
PCIE_CRX_GTX_P4
PCIE_CRX_GTX_P3
PCIE_CRX_GTX_P2
PCIE_CRX_GTX_P1
PCIE_CRX_GTX_P0
PCIE_CTX_GRX_C_N7
PCIE_CTX_GRX_C_N6
PCIE_CTX_GRX_C_N5
PCIE_CTX_GRX_C_N4
PCIE_CTX_GRX_C_N3
PCIE_CTX_GRX_C_N2
PCIE_CTX_GRX_C_N1
PCIE_CTX_GRX_C_N0
PCIE_CTX_GRX_C_P7
PCIE_CTX_GRX_C_P6
PCIE_CTX_GRX_C_P5
PCIE_CTX_GRX_C_P4
PCIE_CTX_GRX_C_P3
PCIE_CTX_GRX_C_P2
PCIE_CTX_GRX_C_P1
PCIE_CTX_GRX_C_P0
PEG_ICOMPI and RCOMPO signals should be
shorted and routed
+V1.05S_VCCP
R1
R1
24.9_0402_1%
24.9_0402_1%
12
with - max length = 500 mils - typical
impedance = 43 mohms
PEG_ICOMPO signals should be routed with max length = 500 mils
- typical impedance = 14.5 mohms
PEG Static Lane Reversal - CF G2 is for the 16x
1: Normal Operation; Lane # definition matches
socket pin map definition
0:Lane Reversed
*
PCIE_CTX_GRX_N7
PCIE_CTX_GRX_N6
PCIE_CTX_GRX_N5
PCIE_CTX_GRX_N4
PCIE_CTX_GRX_N3
PCIE_CTX_GRX_N2
PCIE_CTX_GRX_N1
PCIE_CTX_GRX_N0
PCIE_CTX_GRX_P7
PCIE_CTX_GRX_P6
PCIE_CTX_GRX_P5
PCIE_CTX_GRX_P4
PCIE_CTX_GRX_P3
PCIE_CTX_GRX_P2
PCIE_CTX_GRX_P1
PCIE_CTX_GRX_P0
PCIE_CRX_GTX_N[0..7] <23>
PCIE_CRX_GTX_P[0..7] <23>
1 2
C9 0.22U_0402_10V6KPX@C9 0.22U_0402_10V6KPX@
1 2
C10 0.22U_0402_10V6KPX@C10 0.22U_0402_10V6KPX@
1 2
C11 0.22U_0402_10V6KPX@C11 0.22U_0402_10V6KPX@
1 2
C12 0.22U_0402_10V6KPX@C12 0.22U_0402_10V6KPX@
1 2
C13 0.22U_0402_10V6KPX@C13 0.22U_0402_10V6KPX@
1 2
C14 0.22U_0402_10V6KPX@C14 0.22U_0402_10V6KPX@
1 2
C15 0.22U_0402_10V6KPX@C15 0.22U_0402_10V6KPX@
1 2
C16 0.22U_0402_10V6KPX@C16 0.22U_0402_10V6KPX@
1 2
C25 0.22U_0402_10V6KPX@C25 0.22U_0402_10V6KPX@
1 2
C26 0.22U_0402_10V6KPX@C26 0.22U_0402_10V6KPX@
1 2
C27 0.22U_0402_10V6KPX@C27 0.22U_0402_10V6KPX@
1 2
C28 0.22U_0402_10V6KPX@C28 0.22U_0402_10V6KPX@
1 2
C29 0.22U_0402_10V6KPX@C29 0.22U_0402_10V6KPX@
1 2
C30 0.22U_0402_10V6KPX@C30 0.22U_0402_10V6KPX@
1 2
C31 0.22U_0402_10V6KPX@C31 0.22U_0402_10V6KPX@
1 2
C32 0.22U_0402_10V6KPX@C32 0.22U_0402_10V6KPX@
CFG2
2
PCIE_CTX_GRX_N[0..7] <23>
PCIE_CTX_GRX_P[0..15] <23>
1
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2011/06/15 2012/07/11
2011/06/15 2012/07/11
2011/06/15 2012/07/11
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
PROCESSOR(1/7) DMI,FDI,PEG
PROCESSOR(1/7) DMI,FDI,PEG
PROCESSOR(1/7) DMI,FDI,PEG
LA-9631P
LA-9631P
LA-9631P
5 60W ednesday, February 27, 2013
5 60W ednesday, February 27, 2013
5 60W ednesday, February 27, 2013
1
1.0
1.0
1.0
5
D D
+V1.05S_VCCP
12
R9
R9
62_0402_5%
62_0402_5%
H_PROCHOT#<42,46,47,54>
C C
H_CPUPWRGD<19>
H_PROCHOT#
22P_0402_50V8J
22P_0402_50V8J
C549
C549
H_PM_SYNC<16>
R27
R27
1
10K_0402_5%
10K_0402_5%
1 2
2
ESD
4
JCPU1B
JCPU1B
H_SNB_IVB#<19>
T48T48
H_PECI<42>
R15
R15
56_0402_5%
56_0402_5%
1 2
H_THRMTRIP#<19>
R29
R29
1 2
130_0402_5%
130_0402_5%
H_CATERR#
H_PROCHOT#_R
PM_DRAM_PWR GD_R
BUF_CPU_RST#
C26
AN34
AL33
AN33
AL32
AN32
AM34
AP33
V8
AR33
PROC_SELECT#
SKTOCC#
CATERR#
PECI
PROCHOT#
THERMTRIP#
PM_SYNC
UNCOREPWRGOOD
SM_DRAMPWR OK
RESET#
3
BCLK
BCLK#
MISCTHERMALPWR MANAGEMENT
MISCTHERMALPWR MANAGEMENT
DPLL_REF_CLK
DPLL_REF_CLK#
CLOCKS
CLOCKS
SM_DRAMRST#
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
DDR3
DDR3
MISC
MISC
PRDY#
PREQ#
TCK
TMS
TRST#
TDI
TDO
DBR#
BPM#[0]
BPM#[1]
JTAG & BPM
JTAG & BPM
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
A28
A27
A16
A15
R8
AK1
A5
A4
H_DRAMRST#
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
12
R12 1K_0402_5%R12 1K_0402_5%
12
R13 1K_0402_5%R13 1K_0402_5%
H_DRAMRST# <7>
12
R16 140_0402_1%R16 140_0402_ 1%
12
R17 25.5_0402_1%R17 25.5_0402_1%
12
R18 200_0402_1%R18 200_0402_ 1%
DDR3 Compe nsation S ignals
AP29
XDP_PRDY#
AP27
XDP_PREQ#
AR26
XDP_TCK
AR27
XDP_TMS
AP30
XDP_TRST#
AR28
XDP_TDI
AP26
XDP_TDO
AL35
XDP_DBRESET#
AT28
XDP_BPM#0
AR29
XDP_BPM#1
AR30
XDP_BPM#2
AT30
XDP_BPM#3
AP32
XDP_BPM#4
AR31
XDP_BPM#5
AT31
XDP_BPM#6
AR32
XDP_BPM#7
2
+V1.05S_VCCP
R28 1K_0402_5%R28 1K_0402_ 5%
12
C45
C45
47P_0402_50V8J
47P_0402_50V8J
ESD
CLK_CPU_DMI <15>
CLK_CPU_DMI# <15>
XDP_TRST#
XDP_TDI
XDP_TMS
XDP_TCK
12
51_0804_8P4R_5%
51_0804_8P4R_5%
+3VS
@
@
RP13
RP13
1
+V1.05S_VCCP
18
27
36
45
12
C46
C46
100P_0402_50V8J
100P_0402_50V8J
ESD
TYCO_2013620-2_IVY BRIDGE
+3VALW
TYCO_2013620-2_IVY BRIDGE
ME@
ME@
Buffered reset to CPU
B B
U1
U1
1 2
R161
R161
+3VS
10K_0402_5%
10K_0402_5%
PM_DRAM_PWR GD<16>
A A
5
5
1
P
B
O
2
A
G
74AHC1G09GW_TSSOP5
74AHC1G09GW_TSSOP5
3
4
PM_SYS_PWRGD_BUF
+1.5V_CPU_VDDQ
12
R30
R30
200_0402_5%
200_0402_5%
+V1.05S_VCCP
12
R32
R32
75_0402_5%
75_0402_5%
R34
R34
43_0402_1%
43_0402_1%
BUF_CPU_RST#
4
1 2
BUFO_CPU_RST#
SN74LVC1G07DCKR_SC70-5
SN74LVC1G07DCKR_SC70-5
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
3
+3VS
5
U2
U2
4
1
P
NC
Y
2
PCH_PLTRST#
A
G
3
2011/06/15 2012/07/11
2011/06/15 2012/07/11
2011/06/15 2012/07/11
3V
PCH_PLTRST# <18>
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Title
Title
Title
PROCESSOR(2/7) PM,XDP,CLK
PROCESSOR(2/7) PM,XDP,CLK
PROCESSOR(2/7) PM,XDP,CLK
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
LA-9631P
LA-9631P
LA-9631P
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
1
6 60Wednesday, February 27, 2013
6 60Wednesday, February 27, 2013
6 60Wednesday, February 27, 2013
1.0
1.0
1.0
5
JCPU1C
JCPU1C
DDR_A_D[0..63]<12>
D D
C C
DDR_A_BS0<12>
DDR_A_BS1<12>
B B
DDR_A_BS2<12>
DDR_A_CAS#< 12>
DDR_A_RAS#< 12>
DDR_A_WE#<12>
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
G10
N10
M10
AG6
AG5
AK6
AK5
AH5
AH6
AK8
AK9
AH8
AH9
AL9
AL8
AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15
AE10
AF10
AE8
AD9
AF9
F10
AJ5
AJ6
AJ8
AJ9
C5
D5
D3
D2
D6
C6
C2
C3
F8
G9
F9
F7
G8
G7
K4
K5
K1
K2
M8
N8
N7
M9
N9
M7
V6
J1
J5
J4
J2
SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
SA_BS[0]
SA_BS[1]
SA_BS[2]
SA_CAS#
SA_RAS#
SA_WE#
4
AB6
SA_CLK[0]
AA6
SA_CLK#[0]
V9
SA_CKE[0]
AA5
SA_CLK[1]
AB5
SA_CLK#[1]
V10
SA_CKE[1]
AB4
RSVD_TP[1]
AA4
RSVD_TP[2]
W9
RSVD_TP[3]
AB3
RSVD_TP[4]
AA3
RSVD_TP[5]
W10
RSVD_TP[6]
AK3
SA_CS#[0]
AL3
SA_CS#[1]
AG1
RSVD_TP[7]
AH1
RSVD_TP[8]
AH3
SA_ODT[0]
AG3
SA_ODT[1]
AG2
RSVD_TP[9]
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
AH2
C4
G6
J3
M6
AL6
AM8
AR12
AM15
D4
F6
K3
N6
AL5
AM9
AR11
AM14
AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
RSVD_TP[10]
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
3
DDR_B_D[0..63]<1 3>
M_CLK_DDR0 <12>
M_CLK_DDR#0 <12 >
DDR_CKE0_DIMMA <12>
M_CLK_DDR1 <12>
M_CLK_DDR#1 <12 >
DDR_CKE1_DIMMA <12>
DDR_CS0_DIMMA# <12>
DDR_CS1_DIMMA# <12>
M_ODT0 <12>
M_ODT1 <12>
DDR_A_DQS#[0..7] <12>
DDR_A_DQS[0..7] <12>
DDR_A_MA[0..15] <12> DDR_B_MA[0..15] <13>
DDR_B_BS0<13>
DDR_B_BS1<13>
DDR_B_BS2<13>
DDR_B_CAS#<13>
DDR_B_RAS#<13>
DDR_B_WE#<13>
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
AM5
AM6
AR3
AN3
AN2
AN1
AN9
AN8
AR6
AR5
AR9
AJ11
AH11
AR8
AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15
AA10
D10
K10
J10
M5
M4
M2
M1
AP3
AP2
AP5
AT5
AT6
AP6
AT8
AT9
AA9
AA7
AB8
AB9
C9
A7
C8
A9
A8
D9
D8
G4
F4
F1
G1
G5
F5
F2
G2
J7
J8
K9
J9
K8
K7
N4
N2
N1
N5
R6
JCPU1D
JCPU1D
SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
SB_BS[0]
SB_BS[1]
SB_BS[2]
SB_CAS#
SB_RAS#
SB_WE#
2
AE2
SB_CLK[0]
AD2
SB_CLK#[0]
R9
SB_CKE[0]
AE1
SB_CLK[1]
AD1
SB_CLK#[1]
R10
SB_CKE[1]
SB_CS#[0]
SB_CS#[1]
SB_ODT[0]
SB_ODT[1]
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
AB2
AA2
T9
AA1
AB1
T10
AD3
AE3
AD6
AE6
AE4
AD4
AD5
AE5
D7
F3
K6
N3
AN5
AP9
AK12
AP15
C7
G3
J6
M3
AN6
AP8
AK11
AP14
AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
RSVD_TP[11]
RSVD_TP[12]
RSVD_TP[13]
RSVD_TP[14]
RSVD_TP[15]
RSVD_TP[16]
RSVD_TP[17]
RSVD_TP[18]
RSVD_TP[19]
RSVD_TP[20]
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY B
1
M_CLK_DDR2 <13>
M_CLK_DDR#2 <13>
DDR_CKE2_DIMMB <13>
M_CLK_DDR3 <13>
M_CLK_DDR#3 <13>
DDR_CKE3_DIMMB <13>
DDR_CS2_DIMMB# <13>
DDR_CS3_DIMMB# <13>
M_ODT2 <13>
M_ODT3 <13>
DDR_B_DQS#[0..7] <13>
DDR_B_DQS[0..7] <13>
TYCO_2013620-2_IVY BRIDGE
Deciphered Date
Deciphered Date
Deciphered Date
TYCO_2013620-2_IVY BRIDGE
ME@
ME@
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PROCESSOR(3/7) DDRIII
PROCESSOR(3/7) DDRIII
PROCESSOR(3/7) DDRIII
LA-9631P
LA-9631P
LA-9631P
1
7 60Wednesday, February 27, 2013
7 60Wednesday, February 27, 2013
7 60Wednesday, February 27, 2013
1.0
1.0
1.0
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
ME@
ME@
D
S
D
S
13
H_DRAMRST#<6>
R39
R39
4.99K_0402_1%
4.99K_0402_1%
1 2
@
A A
DRAMRST_CNTRL_PC H<1 0,15>
5
@
1 2
R48
R48
0_0402_5%
0_0402_5%
DRAMRST_CNTRL_PC H_R
DDR3_DRAMRST#_RH_DRAMRST#
Q2
Q2
G
G
LBSS138LT1G_SOT-23-3
LBSS138LT1G_SOT-23-3
2
1
C35
C35
0.047U 16V K X7R 0402
0.047U 16V K X7R 0402
2
Eiffel used 0.01u
Module design used 0.047u
4
+1.5V
R37
R37
1K_0402_5%
1K_0402_5%
12
R38
R38
1K_0402_5%
1K_0402_5%
1 2
DDR3_DRAMRST# <12,13>
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
3
2011/06/15 2012/07/11
2011/06/15 2012/07/11
2011/06/15 2012/07/11
Compal Secret Data
Compal Secret Data
Compal Secret Data
5
4
3
2
1
CFG Straps for Processor
CFG2
12
R41
R41
1K_0402_1%
1K_0402_1%
PX@
D D
PX@
JCPU1E
JCPU1E
AK28
CFG[0]
AK29
CFG[1]
CFG2
CFG4
CFG5
CFG6
CFG7
+VCC_GFXCORE_AXG
+VCC_CORE
@
@
R252
R252
49.9_0402_1%
@
@
R255
R255
1 2
49.9_0402_1%
1 2
1 2
R82 100_0402_1%@R82 100_0402_1%@
1 2
R88 100_0402_1%@R88 100_0402_1%@
VSS_AXG_VAL_SENSE
VSS_VAL_SENSE
R257
R257
49.9_0402_1%
49.9_0402_1%
1 2
1 2
VCC_AXG_VAL_SENSE
VSS_AXG_VAL_SENSE
VCC_VAL_SENSE
VSS_VAL_SENSE
@
@
@
@
R253
R253
49.9_0402_1%
C C
B B
49.9_0402_1%
49.9_0402_1%
49.9_0402_1%
AL26
CFG[2]
AL27
CFG[3]
AK26
CFG[4]
AL29
CFG[5]
AL30
CFG[6]
AM31
CFG[7]
AM32
CFG[8]
AM30
CFG[9]
AM28
CFG[10]
AM26
CFG[11]
AN28
CFG[12]
AN31
CFG[13]
AN26
CFG[14]
AM27
CFG[15]
AK31
CFG[16]
AN29
CFG[17]
AJ31
VAXG_VAL_SENSE
AH31
VSSAXG_VAL_SENSE
AJ33
VCC_VAL_SENSE
AH33
VSS_VAL_SENSE
AJ26
RSVD5
F25
RSVD8
F24
RSVD9
F23
RSVD10
D24
RSVD11
G25
RSVD12
G24
RSVD13
E23
RSVD14
D23
RSVD15
C30
RSVD16
A31
RSVD17
B30
RSVD18
B29
RSVD19
D30
RSVD20
B31
RSVD21
A30
RSVD22
C29
RSVD23
J20
RSVD24
B18
RSVD25
J15
RSVD27
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
ME@
ME@
CFG
CFG
VCC_DIE_SENSE
VSS_DIE_SENSE
RESERVED
RESERVED
RSVD_NCTF10
RSVD_NCTF11
RSVD_NCTF12
RSVD_NCTF13
Interl request AH26 short GND
check on EVT phase
AH27
AH26
L7
RSVD28
AG7
RSVD29
AE7
RSVD30
AK2
RSVD31
W8
RSVD32
AT26
RSVD33
AM33
RSVD34
AJ27
RSVD35
T8
RSVD37
J16
RSVD38
H16
RSVD39
G16
RSVD40
RSVD51
RSVD52
BCLK_ITP
BCLK_ITP#
KEY
AR35
AT34
AT33
AP35
AR34
B34
A33
A34
B35
C35
AJ32
AK32
AN35
AM35
AT2
AT1
AR1
B1
RSVD_NCTF1
RSVD_NCTF2
RSVD_NCTF3
RSVD_NCTF4
RSVD_NCTF5
RSVD_NCTF6
RSVD_NCTF7
RSVD_NCTF8
RSVD_NCTF9
PEG Static Lane Reversal - CFG2 is for the 16x
T13PAD T13PAD
CFG2
1: Normal Operation; Lane # definition matches
socket pin map definition
0:Lane Reversed
*
CFG4
12
R42
@ R42
@
1K_0402_1%
1K_0402_1%
Display Port Presence Strap
CFG4
1 : Disabled; No Physical Display Port
attached to Embedded Display Port
*
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
CFG6
CFG5
12
12
R43
PX@ R43
PX@
1K_0402_1%
1K_0402_1%
R44
@R44
@
1K_0402_1%
1K_0402_1%
PCIE Port Bifurcation Straps
11: (Default) x16 - Device 1 functions 1 and 2 disabled
CFG[6:5]
10: x8, x8 - Device 1 function 1 enabled ; function 2
disabled
*
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
CFG7
12
R45
@R45
@
1K_0402_1%
1K_0402_1%
PEG DEFER TRAINING
1: (Default) PEG Train immediately following xxRESETB
CFG7
de assertion
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
3
2011/06/15 2012/07/11
2011/06/15 2012/07/11
2011/06/15 2012/07/11
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
0: PEG Wait for BIOS for training
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
PROCESSOR(4/7) RSVD,CFG
PROCESSOR(4/7) RSVD,CFG
PROCESSOR(4/7) RSVD,CFG
LA-9631P
LA-9631P
LA-9631P
1
8 60Wednesday, February 27, 2013
8 60Wednesday, February 27, 2013
8 60Wednesday, February 27, 2013
1.0
1.0
1.0
5
POWER
+VCC_CORE
JCPU1F
JCPU1F
POWER
QC=94A
DC=53A
D D
C C
B B
A A
AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
Y35
VCC51
Y34
VCC52
Y33
VCC53
Y32
VCC54
Y31
VCC55
Y30
VCC56
Y29
VCC57
Y28
VCC58
Y27
VCC59
Y26
VCC60
V35
VCC61
V34
VCC62
V33
VCC63
V32
VCC64
V31
VCC65
V30
VCC66
V29
VCC67
V28
VCC68
V27
VCC69
V26
VCC70
U35
VCC71
U34
VCC72
U33
VCC73
U32
VCC74
U31
VCC75
U30
VCC76
U29
VCC77
U28
VCC78
U27
VCC79
U26
VCC80
R35
VCC81
R34
VCC82
R33
VCC83
R32
VCC84
R31
VCC85
R30
VCC86
R29
VCC87
R28
VCC88
R27
VCC89
R26
VCC90
P35
VCC91
P34
VCC92
P33
VCC93
P32
VCC94
P31
VCC95
P30
VCC96
P29
VCC97
P28
VCC98
P27
VCC99
P26
VCC100
CORE SUPPLY
CORE SUPPLY
4
8.5A
AH13
VCCIO1
AH10
VCCIO2
AG10
VCCIO3
AC10
VCCIO4
Y10
VCCIO5
U10
VCCIO6
P10
VCCIO7
L10
VCCIO8
J14
VCCIO9
J13
VCCIO10
J12
VCCIO11
J11
VCCIO12
H14
VCCIO13
H12
VCCIO14
H11
VCCIO15
G14
VCCIO16
G13
VCCIO17
G12
VCCIO18
F14
VCCIO19
F13
VCCIO20
F12
VCCIO21
F11
VCCIO22
E14
VCCIO23
E12
VCCIO24
E11
VCCIO25
D14
VCCIO26
D13
VCCIO27
D12
VCCIO28
D11
VCCIO29
C14
VCCIO30
C13
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39
VCCIO40
VIDALERT#
VIDSCLK
VIDSOUT
C12
C11
B14
B12
A14
A13
A12
A11
J23
AJ29
AJ30
AJ28
AJ35
AJ34
B10
A10
PEG AND DDR
PEG AND DDR
VCC_SENSE
VSS_SENSE
VCCIO_SENSE
VSS_SENSE_VCCIO
SENSE LINES SVID
SENSE LINES SVID
3
+V1.05S_VCCP
+V1.05S_VCCP
12
R46
R46
75_0402_5%
75_0402_5%
H_CPU_SVIDALRT#
1 2
R47 43_0402_5%R47 43_0402_5%
R50 130_0402_5%R 50 130_0402_5%
12
+V1.05S_VCCP
VR_SVID_CL K
0.1uF on power side
series-res istors clo se to VR
VR_SVID_ALRT# <54>
VR_SVID_CLK <54>
VR_SVID_DAT <54>
VCC_SENCE 100ohm +-1% pull-up to VCC near processor
Trace Impedance =27-33 ohm
Trace Length Matc < 25 mils
R79
R79
10_0402_1%
10_0402_1%
VCCIO_SENSE <52>
+V1.05S_VCCP
12
1 2
VSSIO_SENSEVSSIO_SENSE_L
R74
R74
10_0402_1%
10_0402_1%
R74 & R79 put together
VSSIO_SENSE_L <52>
VSS_SENCE 100ohm +-1% pull-down to GND near processor
2
+VCC_CORE
12
R51
R51
100_0402_1%
100_0402_1%
VCCSENSE <54>
R54
R54
100_0402_1%
100_0402_1%
VSSSENSE <54>
12
1
Security Classification
Security Classification
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
ME@
ME@
5
4
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
2011/06/15 2012/07/11
2011/06/15 2012/07/11
2011/06/15 2012/07/11
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Title
Title
Title
PROCESSOR(5/7) PWR,BYPASS
PROCESSOR(5/7) PWR,BYPASS
PROCESSOR(5/7) PWR,BYPASS
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
LA-9631P
LA-9631P
LA-9631P
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
9 60Wednesday, February 27, 2013
9 60Wednesday, February 27, 2013
9 60Wednesday, February 27, 2013
1
1.0
1.0
1.0
5
4
3
2
1
+1.5V +1.5V_CPU_VDDQ
+VREF_DQ_DIMMA
SUSP<45>
D D
C C
B B
+1.8VS
R69 0_0805_5%
R69 0_0805_5%
1 2
@
@
1
2
C130
C130
C345
C345
10U_0603_6.3V6M
10U_0603_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
@
@
2
B+
12
13
D
D
2
G
G
S
S
+VCC_GFXCORE_AXG
1.5A
+1.8VS_VCCPLL
C132
C132
1U_0402_6.3V6K
1U_0402_6.3V6K
1
2
DMN3030LSS-13_SOP8L-8
DMN3030LSS-13_SOP8L-8
8
7
5
R56
R56
82K_0402_5%
82K_0402_5%
RUN_ON_CPU1.5VS3
Q4
Q4
2N7002H_SOT23-3
2N7002H_SOT23-3
AT24
AT23
AT21
AT20
AT18
AT17
AR24
AR23
AR21
AR20
AR18
AR17
AP24
AP23
AP21
AP20
AP18
AP17
AN24
AN23
AN21
AN20
AN18
AN17
AM24
AM23
AM21
AM20
AM18
AM17
AL24
AL23
AL21
AL20
AL18
AL17
AK24
AK23
AK21
AK20
AK18
AK17
AJ24
AJ23
AJ21
AJ20
AJ18
AJ17
AH24
AH23
AH21
AH20
AH18
AH17
B6
A6
A2
U3
U3
JCPU1G
JCPU1G
VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
VAXG37
VAXG38
VAXG39
VAXG40
VAXG41
VAXG42
VAXG43
VAXG44
VAXG45
VAXG46
VAXG47
VAXG48
VAXG49
VAXG50
VAXG51
VAXG52
VAXG53
VAXG54
VCCPLL1
VCCPLL2
VCCPLL3
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
ME@
ME@
4
1 2
12
R57
R57
330K_0402_5%
330K_0402_5%
@
@
1
2
36
R885
R885
15K_0402_1%
15K_0402_1%
AP4800
Id=9.6A
R02
1
C97
C97
0.047U_0603_25V7K
0.047U_0603_25V7K
2
POWER
POWER
SENSE
SENSE
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
VREFMISC
VREFMISC
GRAPHICS
GRAPHICS
DDR3 -1.5V RAILS
DDR3 -1.5V RAILS
SA RAIL
SA RAIL
1.8V RAIL
1.8V RAIL
VAXG_SENSE
VSSAXG_SENSE
LINES
LINES
SM_VREF
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8
VCCSA_SENSE
VCCSA_VID[0]
VCCSA_VID[1]
VCCIO_SEL
+VCC_GFXCORE_AXG
12
AK35
AK34
12
AL1
+V_SM_VREF_CNT
B4
+V_DDR_REFA_R
D1
+V_DDR_REFB_R
AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1
M27
+VCCSA
M26
L26
J26
J25
J24
H26
H25
H23
C22
C24
A19
R616
R616
10_0402_1%
10_0402_1%
R626
R626
10_0402_1%
10_0402_1%
10U_0603_6.3V6M
10U_0603_6.3V6M
1
2
10U_0603_6.3V6M
10U_0603_6.3V6M
1
2
H_VCCSA_VID0 <51>
H_VCCSA_VID1 <51>
C117
C117
C124
C124
10U_0603_6.3V6M
10U_0603_6.3V6M
1
2
+VREF_DQ_DIMMB
DRAMRST_CNTRL_PCH
LBSS138LT1G_SOT-23-3
LBSS138LT1G_SOT-23-3
M3 Circuit (Processor Generated SO-DIMM VREF_DQ)
VCC_AXG_SENSE <54>
VSS_AXG_SENSE <54>
+V_SM_VREF should
have 20 mil trace width
1
C98
C98
.1U_0402_16V7K
C125
C125
.1U_0402_16V7K
C119
C119
10U_0603_6.3V6M
10U_0603_6.3V6M
1
2
C126
C126
10U_0603_6.3V6M
10U_0603_6.3V6M
1
2
2
C120
C120
10U_0603_6.3V6M
10U_0603_6.3V6M
1
@
@
2
+VCCSA
1
+
2
2
G
G
+1.5V_CPU_VDDQ
12
R67
R67
1K_0402_1%
1K_0402_1%
12
R78
R78
1K_0402_1%
1K_0402_1%
+1.5V_CPU_VDDQ
1
C122
C122
10U_0603_6.3V6M
10U_0603_6.3V6M
1
+
+
2
2
C128
@+C128
@
330U_D2_2.5VY_R9M
330U_D2_2.5VY_R9M
+VCCSA_SENSE <51>
13
D
D
S
S
Q9
Q9
C123
C123
220U_6.3V_M
220U_6.3V_M
Q6
Q6
13
D
D
LBSS138LT1G_SOT-23-3
LBSS138LT1G_SOT-23-3
2
G
G
S
S
+V_DDR_REFA_R
+V_DDR_REFB_R
DRAMRST_CNTRL_PCH <15,7>
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/06/15 2012/07/11
2011/06/15 2012/07/11
2011/06/15 2012/07/11
Compal Secret Data
Compal Secret Data
Compal Secret Data
IVY Bridge drives VCCIO_SEL low
VCCP_PWRCTRL:0
Sandy Bridge is NC for A19
VCCP_PWRCTRL:1
Deciphered Date
Deciphered Date
Deciphered Date
2
Title
Title
Title
PROCESSOR(6/7) PWR
PROCESSOR(6/7) PWR
PROCESSOR(6/7) PWR
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
LA-9631P
LA-9631P
LA-9631P
Date: Sheet of
Date: Sheet of
Date: Sheet of
10 60Wednesday, February 27, 2013
10 60Wednesday, February 27, 2013
10 60Wednesday, February 27, 2013
1
1.0
1.0
1.0
5
JCPU1H
JCPU1H
AT35
AT32
AT29
AT27
AT25
AT22
AT19
AT16
AT13
D D
C C
B B
A A
5
AT10
AT7
AT4
AT3
AR25
AR22
AR19
AR16
AR13
AR10
AR7
AR4
AR2
AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10
AP7
AP4
AP1
AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10
AN7
AN4
AM29
AM25
AM22
AM19
AM16
AM13
AM10
AM7
AM4
AM3
AM2
AM1
AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10
AL7
AL4
AL2
AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10
AK7
AK4
AJ25
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
ME@
ME@
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
4
AJ22
VSS81
AJ19
VSS82
AJ16
VSS83
AJ13
VSS84
AJ10
VSS85
AJ7
VSS86
AJ4
VSS87
AJ3
VSS88
AJ2
VSS89
AJ1
VSS90
AH35
VSS91
AH34
VSS92
AH32
VSS93
AH30
VSS94
AH29
VSS95
AH28
VSS96
AH25
VSS98
AH22
VSS99
AH19
VSS100
AH16
VSS101
AH7
VSS102
AH4
VSS103
AG9
VSS104
AG8
VSS105
AG4
VSS106
AF6
VSS107
AF5
VSS108
AF3
VSS109
AF2
VSS110
AE35
VSS111
AE34
VSS112
AE33
VSS113
AE32
VSS114
AE31
VSS115
AE30
VSS116
AE29
VSS117
AE28
VSS118
VSS
VSS
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2
3
JCPU1I
JCPU1I
T35
VSS161
T34
VSS162
T33
VSS163
T32
VSS164
T31
VSS165
T30
VSS166
T29
VSS167
T28
VSS168
T27
VSS169
T26
VSS170
P9
VSS171
P8
VSS172
P6
VSS173
P5
VSS174
P3
VSS175
P2
VSS176
N35
VSS177
N34
VSS178
N33
VSS179
N32
VSS180
N31
VSS181
N30
VSS182
N29
VSS183
N28
VSS184
N27
VSS185
N26
VSS186
M34
VSS187
L33
VSS188
L30
VSS189
L27
VSS190
L9
VSS191
L8
VSS192
L6
VSS193
L5
VSS194
L4
VSS195
L3
VSS196
L2
VSS197
L1
VSS198
K35
VSS199
K32
VSS200
K29
VSS201
K26
VSS202
J34
VSS203
J31
VSS204
H33
VSS205
H30
VSS206
H27
VSS207
H24
VSS208
H21
VSS209
H18
VSS210
H15
VSS211
H13
VSS212
H10
VSS213
H9
VSS214
H8
VSS215
H7
VSS216
H6
VSS217
H5
VSS218
H4
VSS219
H3
VSS220
H2
VSS221
H1
VSS222
G35
VSS223
G32
VSS224
G29
VSS225
G26
VSS226
G23
VSS227
G20
VSS228
G17
VSS229
G11
VSS230
F34
VSS231
F31
VSS232
F29
VSS233
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
ME@
ME@
Compal Secret Data
Compal Secret Data
2011/06/15 2012/07/11
2011/06/15 2012/07/11
2011/06/15 2012/07/11
Compal Secret Data
3
Deciphered Date
Deciphered Date
Deciphered Date
VSS
VSS
2
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
2
F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3
1
Compal Electronics, Inc.
Title
Title
Title
PROCESSOR(7/7) VSS
PROCESSOR(7/7) VSS
PROCESSOR(7/7) VSS
Size D ocument Number Rev
Size D ocument Number Rev
Size D ocument Number Rev
Custom
Custom
Custom
LA-9631P
LA-9631P
LA-9631P
Date: Sheet of
Date: Sheet of
Date: Sheet of
11 60Wednesday, February 27, 2013
11 60Wednesday, February 27, 2013
11 60Wednesday, February 27, 2013
1
1.0
1.0
1.0
5
+VREF_DQ_DIMMA
+VREF_DQ_DIMMA
.1U_0402_16V7K
.1U_0402_16V7K
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
C133
C133
C
C
134
134
1
1
2
D D
C C
B B
+3VS
A A
2
@
@
DDR_CKE0_DIMMA<7>
DDR_A_BS2<7>
M_CLK_DDR0<7>
M_CLK_DDR#0<7>
DDR_A_BS0<7>
DDR_A_WE#<7>
DDR_A_CAS#<7>
DDR_CS1_DIMMA#<7>
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
.1U_0402_16V7K
.1U_0402_16V7K
C155
C155
1
1
2
2
@
@
5
+1.5V +1.5V
DDR3 SO-DIMM A
JDIMM1
JDIMM1
VREF_DQ1VSS1
3
VSS2
DDR_A_D0
DDR_A_D1
DDR_A_DM0
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_DM3
DDR_A_D26
DDR_A_D27
DDR_CKE0_DIMMA
DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
M_CLK_DDR0
M_CLK_DDR#0
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS# M_ODT0
DDR_A_MA13
DDR_CS1_DIMMA#
DDR_A_D32
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_DM7
DDR_A_D58
DDR_A_D59
C156
C156
5
DQ0
7
DQ1
VSS49DQS#0
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1
DQS129RESET#
VSS1131VSS12
33
DQ10
35
DQ11
VSS1337VSS14
39
DQ16
41
DQ17
VSS1543VSS16
45
DQS#2
47
DQS2
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25
VSS2261DQS#3
63
DM3
VSS2365VSS24
67
DQ26
69
DQ27
VSS2571VSS26
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
99
VDD9
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
LCN_DAN06-K4806-0103
LCN_DAN06-K4806-0103
ME@
ME@
VREF_CA
EVENT#
VSS3
DQS0
VSS6
VSS8
DQ12
DQ13
VSS10
DQ14
DQ15
DQ20
DQ21
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS3
DQ30
DQ31
CKE1
VDD2
VDD4
VDD6
VDD8
VDD10
CK1#
VDD12
RAS#
VDD14
ODT0
VDD16
ODT1
VDD18
VSS28
DQ36
DQ37
VSS30
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
VTT2
4
DDR_A_D[0..63]<7>
DDR_A_DQS[0..7]<7>
1
2
@
@
DDR_A_DQS#[0..7]<7>
DDR_A_MA[0..15]<7>
+VREF_CA
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
C136
C136
4*0402 1uf
1*0402 2.2uf
+VREF_DQ_DIMMA
+VREF_DQ_DIMMB
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
DDR_A_D4
DDR_A_D5
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D6
DDR_A_D7
DDR_A_D12
DDR_A_D13
DDR_A_DM1
DDR3_DRAMRST#
DDR_A_D14
DDR_A_D15
DDR_A_D20
DDR_A_D21
DDR_A_DM2
DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31
DDR_CKE1_DIMMA
DDR_A_MA15
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
M_CLK_DDR1
M_CLK_DDR#1
DDR_A_BS1
DDR_A_RAS#
DDR_CS0_DIMMA#
M_ODT1
DDR_A_D36
DDR_A_D37
DDR_A_DM4
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A_DM6
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
SMB_DATA_S3
SMB_CLK_S3
4
+0.75VS
DDR3_DRAMRST# <13,7>
DDR_CKE1_DIMMA <7>
M_CLK_DDR1 <7>
M_CLK_DDR#1 <7>
DDR_A_BS1 <7>
DDR_A_RAS# <7>
DDR_CS0_DIMMA# <7>
M_ODT0 <7>
M_ODT1 <7>
.1U_0402_16V7K
.1U_0402_16V7K
C135
C135
1
2
VDDQ(1.5V) =
3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)
6*0603 10uf (PER CONNECTOR)
VTT(0.75V) =
3*0805 10uf
VREF =
1*0402 0.1uf
VDDSPD (3.3V)=
1*0402 0.1uf 1*0402 2.2uf
SMB_DATA_S3 <13,15,36>
SMB_CLK_S3 <13,15,36>
DQ4
DQ5
DQ6
DQ7
DM1
DM2
A15
A14
A11
A7
A6
A4
A2
A0
CK1
BA1
S0#
NC2
DM4
DM6
SDA
SCL
G2
+VREF_CA
+VREF_CB
+VREF_CA
3
RP15
RP15
1K_0804_8P4R_1%
1K_0804_8P4R_1%
RP16
RP16
1K_0804_8P4R_1%
1K_0804_8P4R_1%
+1.5V
18
27
36
45
+1.5V
18
27
36
45
2
(220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y00)OSCAN
Layout Note:
Place near DIMM
+1.5V
C139
C139
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1
2
2
Layout Note:
Place near DIMM
+0.75VS
C150
C150
C152
C152
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
2
2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/06/15 2012/07/11
2011/06/15 2012/07/11
2011/06/15 2012/07/11
Compal Secret Data
Compal Secret Data
Compal Secret Data
(10uF_0603_6.3V)*8
(0.1uF_402_10V)*4
C140
C140
C141
C141
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1
2
2
7/28 Update connect GND directly
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
Deciphered Date
Deciphered Date
Deciphered Date
2
C143
C143
C142
C142
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
2
Layout Note:
Place near DIMM
1
C146
C146
C147
C144
C144
C145
C145
10U_0603_6.3V6M
10U_0603_6.3V6M
.1U_0402_16V7K
.1U_0402_16V7K
@
@
1
2
1
1
2
2
C147
C148
.1U_0402_16V7K
.1U_0402_16V7K
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
C148
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
1
2
1
1
+
C149
@+C149
@
220U_6.3V_M
220U_6.3V_M
2
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
DDRIII-SODIMM SLOT1
DDRIII-SODIMM SLOT1
DDRIII-SODIMM SLOT1
LA-9631P
LA-9631P
LA-9631P
1
12 60Wednesday, February 27, 2013
12 60Wednesday, February 27, 2013
12 60Wednesday, February 27, 2013
1.0
1.0
1.0
5
4
3
2
1
+VREF_DQ_DIMMB
+VREF_DQ_DIMMB
DDR_B_D0
1
C157
C157
2
DDR_B_D1
DDR_B_DM0
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_DM3
DDR_B_D26
DDR_B_D27
DDR_CKE2_DIMMB
DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
M_CLK_DDR2
M_CLK_DDR#2
DDR_B_MA10
DDR_B_BS0
DDR_B_WE#
DDR_B_CAS#
DDR_B_MA13
DDR_CS3_DIMMB#
DDR_B_D32
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
DDR_B_DM5
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57
DDR_B_DM7
DDR_B_D58
DDR_B_D59
1 2
R97 10K_0402_5%R97 10K_0402_5%
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
.1U_0402_16V7K
.1U_0402_16V7K
1
C158
D D
For Arranale only +VREF_DQ_DIMMB
supply from a external 1.5V voltage divide
circuit.
C C
B B
A A
+3VS
1
@
@
2
C158
2
@
@
DDR_CKE2_DIMMB<7>
DDR_B_BS2<7>
M_CLK_DDR2<7>
M_CLK_DDR#2<7>
DDR_B_BS0<7>
DDR_B_WE#<7>
DDR_B_CAS#<7>
DDR_CS3_DIMMB#<7>
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
.1U_0402_16V7K
.1U_0402_16V7K
C
C
C
C
177
177
+3VS
178
178
1
2
5
+1.5V +1.5V
JDIMM2
JDIMM2
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
9
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1
DQS129RESET#
VSS1131VSS12
33
DQ10
35
DQ11
VSS1337VSS14
39
DQ16
41
DQ17
VSS1543VSS16
45
DQS#2
DQS247VSS17
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25
VSS2261DQS#3
63
DM3
VSS2365VSS24
67
DQ26
69
DQ27
VSS2571VSS26
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
99
VDD9
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
TYCO_2-2013287-1
TYCO_2-2013287-1
ME@
ME@
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
DQ14
DQ15
DQ20
DQ21
DM2
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS3
DQ30
DQ31
CKE1
VDD2
VDD4
VDD6
VDD8
VDD10
CK1
CK1#
VDD12
RAS#
VDD14
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
A15
80
A14
82
84
A11
86
A7
88
90
A6
92
A4
94
96
A2
98
A0
100
102
104
106
108
BA1
110
112
114
S0#
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
G2
4
DDR_B_D4
DDR_B_D5
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D6
DDR_B_D7
DDR_B_D12
DDR_B_D13
DDR_B_DM1
DDR3_DRAMRST#
DDR_B_D14
DDR_B_D15
DDR_B_D20
DDR_B_D21
DDR_B_DM2
DDR_B_D22
DDR_B_D23
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31
DDR_CKE3_DIMMB
DDR_B_MA15
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
M_CLK_DDR3
M_CLK_DDR#3
DDR_B_BS1
DDR_B_RAS#
DDR_CS2_DIMMB#
M_ODT2
M_ODT3
DDR_B_D36
DDR_B_D37
DDR_B_DM4
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
DDR_B_DM6
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
SMB_DATA_S3
SMB_CLK_S3
DDR_B_D[0..63]<7>
DDR_B_DQS[0..7]<7>
DDR_B_DQS#[0..7]<7>
DDR_B_MA[0..15]<7>
DDR3_DRAMRST# <12,7>
DDR_CKE3_DIMMB <7>
M_CLK_DDR3 <7>
M_CLK_DDR#3 <7>
DDR_B_BS1 <7>
DDR_B_RAS# <7>
DDR_CS2_DIMMB# <7>
M_ODT2 <7>
M_ODT3 <7>
1
2
.1U_0402_16V7K
.1U_0402_16V7K
C159
C159
1
2
+VREF_CB
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
C160
C160
@
@
+VREF_CB
VDDQ(1.5V) =
3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)
6*0603 10uf (PER CONNECTOR)
VTT(0.75V) =
3*0805 10uf
1*0402 0.1uf
4*0402 1uf
1*0402 2.2uf
VDDSPD (3.3V)=
1*0402 2.2uf 1*0402 0.1uf
SMB_DATA_S3 <12,15,36>
SMB_CLK_S3 <12,15,36>
+0.75VS
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
Layout Note:
Place near DIMM
C163
C163
1
2
Layout Note:
Place near DIMM
+0.75VS
C174
C174
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
2
Compal Secret Data
Compal Secret Data
2011/06/15 2012/07/11
2011/06/15 2012/07/11
2011/06/15 2012/07/11
Compal Secret Data
(10uF_0603_6.3V)*8
(0.1uF_402_10V)*4
+1.5V
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
C164
C164
C165
C165
1
1
2
2
C176
C176
1
2
Deciphered Date
Deciphered Date
Deciphered Date
2
10U_0603_6.3V6M
10U_0603_6.3V6M
C166
C166
1
2
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
Layout Note:
Place near DIMM
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
C168
C168
C167
C167
1
1
2
2
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
C170
C170
C169
C169
@
@
1
1
2
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
.1U_0402_16V7K
C171
C171
C172
C172
1
1
2
2
DDRIII-SODIMM SLOT2
DDRIII-SODIMM SLOT2
DDRIII-SODIMM SLOT2
LA-9631P
LA-9631P
LA-9631P
1
13 60Wednesday, February 27, 2013
13 60Wednesday, February 27, 2013
13 60Wednesday, February 27, 2013
1.0
1.0
1.0
5
W=20milsW=20mils
+RTCBAT T+RTCVCC
R99
R99
1K_0402_5%
1K_0402_5%
1 2
1
C179
C179
1U_0603_1 0V4Z
1U_0603_1 0V4Z
2
D D
+RTCVCC
1 2
R101 1M_0402_ 5%R101 1M_0402_5%
1 2
R102 330K_040 2_5%R1 02 330K_0402_5%
INTVRMEN
HIntegrated VRM enable
*
LIntegrated VRM disable
SM_INTRU DER#
PCH_INTV RMEN
+RTCVCC
R103 20K_040 2_5%R103 20K_04 02_5%
R100 20K_0402_5%R100 20K_0402_5 %
(INTVRMEN should always be pull high.)
+3VS
1 2
R105 1K_0402_ 5%@R 105 1K_0402_5%@
HIGH= Enable ( No Reboot )
LOW= Disable (Default)
*
C C
+3V_PCH
R106 1K_0402_ 5%@R106 1K_0402_5%@
Low = Disabled (Default)
*
High = Enabled [Flash Descriptor Security Overide]
+3V_PCH
R108 1K_0402_5 %R108 1K_04 02_5%
This signal has a weak internal pull-down
On Die PLL VR is supplied by
1.5V when smaple d high
1.8V when sample d low
*
Needs to be pull ed High for Chi ef River platfro m
HDA_BITC LK_AUDIO<41>
HDA_SYNC_ AUDIO<41 >
B B
HDA_RST _AUDIO#< 41>
HDA_SDO UT_AUDIO<41>
12
12
33_0804_8P 4R_5%
33_0804_8P 4R_5%
For EMI
RP12
RP12
HDA_SPK R
ME_FLAS H
HDA_SYNC
18
27
36
45
HDA_BIT_ CLK
HDA_SYNC_ R
HDA_RST #
ME_FLAS H
ME_FLASH<42>
R878
R878
1M_0402_5 %
1M_0402_5 %
1 2
check with vender
Del Q10 check with codec
VDDIO using 3VALW
DPDG1.1
0_0402_5%
0_0402_5%
18P_0402_5 0V8J
18P_0402_5 0V8J
C183
C183
1U_0603_1 0V4Z
1U_0603_1 0V4Z
1 2
1 2
C182
C182
1U_0603_1 0V4Z
1U_0603_1 0V4Z
+5VS
G
G
2
S
S
22P_0402_5 0V8J
22P_0402_5 0V8J
@
@
R104
R104
C180
C180
HDA_SPK R<41>
HDA_SDIN 0<41>
Q10
Q10
LBSS138LT 1G_SOT-23-3
LBSS138LT 1G_SOT-23-3
13
D
D
33_0402_5%
33_0402_5%
R124;c190 close to U4.T3 pin
A A
4
1 2
R98 10M _0402_5%R98 10M _0402_5%
Y1
Y1
1 2
1 2
1
2
SHORT PADS
SHORT PADS
CLRP2
CLRP2
@
@
1
12
2
SHORT PADS
SHORT PADS
CLRP3
CLRP3
1
12
@
@
2
HDA_SYNC
SPI_CLK_P CH_R
12
R124
R124
@
@
C190
C190
@
@
PCH_RTC X1
PCH_RTC X2
32.768KHZ_ 12.5PF_CM31532 768DZFT
32.768KHZ_ 12.5PF_CM31532 768DZFT
1
C181
C181
18P_0402_5 0V8J
18P_0402_5 0V8J
2
PCH_RTC X1
PCH_RTC X2
PCH_RTC RST#
PCH_SRT CRST#
SM_INTRU DER#
PCH_INTV RMEN
HDA_BIT_ CLK
HDA_SYNC
HDA_SPK R
HDA_RST #
HDA_SDIN 0
ME_FLAS H
PCH_GPIO33
PCH_GPIO13
PCH_JTA G_TCK
PCH_JTA G_TMS
PCH_JTA G_TDI
PCH_JTA G_TDO
SPI_CLK_P CH_R
SPI_SB_C S0#
SPI_SI
SPI_SO_R
For EMI
U4A
U4A
A20
RTCX1
C20
RTCX2
D20
RTCRST #
G22
SRTCRS T#
K22
INTRUDE R#
C17
INTVRME N
N34
HDA_BCL K
L34
HDA_SYNC
T10
SPKR
K34
HDA_RST #
E34
HDA_SDIN 0
G34
HDA_SDIN 1
C34
HDA_SDIN 2
A34
HDA_SDIN 3
A36
HDA_SDO
C36
HDA_DOC K_EN# / GPIO33
N32
HDA_DOC K_RST# / GPIO13
J3
JTAG_TCK
H7
JTAG_TMS
K5
JTAG_TDI
H1
JTAG_TDO
T3
SPI_CLK
Y14
SPI_CS0#
T1
SPI_CS1#
V4
SPI_MOSI
U3
SPI_MISO
PANTHE R-POINT_FCBGA98 9
PANTHE R-POINT_FCBGA98 9
HM76@
HM76@
SA00005FH 70
SA00005FH 70
S IC BD82HM 76 SLJ8E C1 BGA 9 89P PCH C38!
S IC BD82HM 76 SLJ8E C1 BGA 9 89P PCH C38!
U4
HM70@
U4
HM70@
SA00005M Q80
SA00005M Q80
IC BD82HM 70 SJTNV C1 BGA 98 9P PCH C38!
IC BD82HM 70 SJTNV C1 BGA 98 9P PCH C38!
U4
NM70@
U4
NM70@
SA00005W U60
SA00005W U60
S IC BD82NM 70 SLJTA C1 BGA 9 89P PCH C38!
S IC BD82NM 70 SLJTA C1 BGA 9 89P PCH C38!
RTCIHDA
RTCIHDA
JTAG
JTAG
SPI
SPI
3
FWH0 / LA D0
FWH1 / LA D1
FWH2 / LA D2
FWH3 / LA D3
LPC
LPC
FWH4 / LF RAME#
LDRQ0#
LDRQ1# / GPIO23
SERIRQ
SATA0RX N
SATA0RX P
SATA0TX N
SATA0TX P
SATA1RX N
SATA1RX P
SATA 6G
SATA 6G
SATA1TX N
SATA1TX P
SATA2RX N
SATA2RX P
SATA2TX N
SATA2TX P
SATA3RX N
SATA3RX P
SATA3TX N
SATA3TX P
SATA4RX N
SATA4RX P
SATA4TX N
SATA
SATA
SATA4TX P
SATA5RX N
SATA5RX P
SATA5TX N
SATA5TX P
SATAICOM PO
SATAICOM PI
SATA3RC OMPO
SATA3COM PI
SATA3RB IAS
SATALED #
SATA0GP / GP IO21
SATA1GP / GP IO19
PCH_GPIO16<19>
CLRP2
Shunt
Open
CLRP3
Open
C38
LPC_AD0
A38
LPC_AD1
B37
LPC_AD2
C37
LPC_AD3
D36
LPC_FRA ME#
E36
K36
V5
SERIRQSERIRQ
AM3
SATA_DT X_C_IRX_N0
AM1
SATA_DT X_C_IRX_P0
AP7
SATA_ITX_ C_DRX_N0
AP5
SATA_ITX_ C_DRX_P0
AM10
AM8
AP11
AP10
AD7
SATA_DT X_C_IRX_N2
AD5
SATA_DT X_C_IRX_P2
AH5
SATA_ITX_ C_DRX_N2
AH4
SATA_ITX_ C_DRX_P2
AB8
AB10
AF3
AF1
Y7
Y5
AD3
AD1
Y3
Y1
AB3
AB1
Y11
Y10
AB12
AB13
AH1
RBIAS_SA TA3
P3
SATALED #
V14
PCH_GPIO21
P1
BBS_BIT0_ R
SATA_COM P
SATA3_C OMP
BBS_BIT0_ R
SATALED #
PCH_GPIO16
SERIRQ
CMOS setting
Clear CMOS
Keep CMOS
TPM setting
Clear ME RTC RegistersShunt
Keep ME RTC Registers
LPC_AD0 <42>
LPC_AD1 <42>
LPC_AD2 <42>
LPC_AD3 <42>
LPC_FRA ME# <42>
SERIRQ <42>
R111
R111
37.4_0402_1%
37.4_0402_1%
1 2
R113
R113
49.9_0402_1%
49.9_0402_1%
1 2
1 2
R115
R115
750_0402_1 %
750_0402_1 %
+3V_ROM
1 2
R127
R127
1 2
R129
R129
RP17
RP17
10K_0804_8 P4R_5%
10K_0804_8 P4R_5%
EC and Mini card debug port
SATA_DT X_C_IRX_N0 <40>
SATA_DT X_C_IRX_P0 < 40>
SATA_ITX_ C_DRX_N0 <40>
SATA_ITX_ C_DRX_P0 < 40>
SATA_DT X_C_IRX_N2 <40>
SATA_DT X_C_IRX_P2 < 40>
SATA_ITX_ C_DRX_N2 <40>
SATA_ITX_ C_DRX_P2 <40>
+V1.05S_VCCP
+V1.05S_VCCP
SPI_WP #
3.3K_0402_5 %
3.3K_0402_5 %
SPI_HOLD#
3.3K_0402_5 %
3.3K_0402_5 %
+3VS
18
27
36
45
2
SPI_SB_C S0#
HDD
ODD
1 2
R131
R131
0_0402_5%
0_0402_5%
@
@
For EMI
SPI_SO_R
SPI_SI
SPI_CLK_P CH_R
SPI_SB_C S0#
1
2
3
SPI_WP #
4
1
Share ROM
@
@
RP2
RP2
1 8
2 7
3 6
4 5
0_0804_8P4 R_5%
0_0804_8P4 R_5%
EC_SPI_S O
EC_SPI_S I
EC_SPI_C LK
EC_SPI_C S#
EC_SPI_S O <42>
EC_SPI_S I <42>
EC_SPI_C LK <42>
EC_SPI_C S# <42>
Share ROM
U5
U5
CS#
SO
WP#
GND
W25Q64F VSSIQ_SO8
W25Q64F VSSIQ_SO8
SA000039A 30
SA000039A 30
S IC FL 64M W 25Q64FVSSIQ SOIC 8P SPI ROM
S IC FL 64M W 25Q64FVSSIQ SOIC 8P SPI ROM
VCC
HOLD#
SCLK
8
7
SPI_HOLD#SPI_SO_R SPI_SO_L
6
5
SI
1 2
For EMI
+3V_ROM
R133
R133
0_0402_5%
0_0402_5%
@
@
SPI_CLK_P CH_RSPI_CLK_1
SPI_SI
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
3
2011/06/15 2012/07/11
2011/06/15 2012/07/11
2011/06/15 2012/07/11
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Title
Title
Title
PCH (1/9) SATA,HDA,SPI, LPC, XDP
PCH (1/9) SATA,HDA,SPI, LPC, XDP
PCH (1/9) SATA,HDA,SPI, LPC, XDP
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
LA-9631P
LA-9631P
LA-9631P
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
14 60Wednesday, M arch 06, 2013
14 60Wednesday, M arch 06, 2013
14 60Wednesday, M arch 06, 2013
1
1.0
1.0
1.0
5
LAN
WLAN
D D
C C
LAN
WLAN
B B
PCIE_PRX _DTX_N1<37>
PCIE_PRX _DTX_P1<37>
PCIE_PTX _C_DRX_N1<37>
PCIE_PTX _C_DRX_P1<37>
PCIE_PRX _DTX_N2<36>
PCIE_PRX _DTX_P2<36>
PCIE_PTX _C_DRX_N2<36>
PCIE_PTX _C_DRX_P2<36>
CLK_PCIE _LAN#< 37>
CLK_PCIE _LAN<37>
CLKREQ_L AN#<37>
CLK_PCIE _WLAN1#<36>
CLK_PCIE _WLAN1<36>
CLKREQ_W LAN#<36>
+3V_PCH
+3VS
1 2
C192 .1U_0402_ 16V7KC192 .1U_0402_ 16V7K
1 2
C193 .1U_0402_ 16V7KC193 .1U_0402_ 16V7K
1 2
C194 .1U_0402_ 16V7KC194 .1U_0402_ 16V7K
1 2
C195 .1U_0402_ 16V7KC195 .1U_0402_ 16V7K
1 2
R153 0_0402_ 5%@R153 0_0402_ 5%@
1 2
R154 0_0402_ 5%@R154 0_0402_ 5%@
R152 10K_0402_ 5%R1 52 10K_0402_5%
1 2
R156 0_0402_ 5%@R156 0_0402_ 5%@
1 2
R165 0_0402_ 5%@R165 0_0402_ 5%@
R158 10K_0402 _5%R158 10K_0402_5 %
12
12
For EMI
For EMI
4
PCIE_PRX _DTX_N1
PCIE_PRX _DTX_P1
PCIE_PTX _DRX_N1
PCIE_PTX _DRX_P1
PCIE_PRX _DTX_N2
PCIE_PRX _DTX_P2
PCIE_PTX _DRX_N2
PCIE_PTX _DRX_P2
CLK_PCIE _LAN#_R
CLK_PCIE _LAN_R
CLK_PCIE _WLAN1#_R
CLK_PCIE _WLAN1_R
PCH_GPIO20
PCH_GPIO25
PCH_GPIO26
PCH_GPIO44
PCH_GPIO56
PCH_GPIO45
PCH_GPIO46
PCIE_CLK_8N
PCIE_CLK_8P
U4B
U4B
BG34
PERN1
BJ34
PERP1
AV32
PETN1
AU32
PETP1
BE34
PERN2
BF34
PERP2
BB32
PETN2
AY32
PETP2
BG36
PERN3
BJ36
PERP3
AV34
PETN3
AU34
PETP3
BF36
PERN4
BE36
PERP4
AY34
PETN4
BB34
PETP4
BG37
PERN5
BH37
PERP5
AY36
PETN5
BB36
PETP5
BJ38
PERN6
BG38
PERP6
AU36
PETN6
AV36
PETP6
BG40
PERN7
BJ40
PERP7
AY40
PETN7
BB40
PETP7
BE38
PERN8
BC38
PERP8
AW38
PETN8
AY38
PETP8
Y40
CLKOUT_P CIE0N
Y39
CLKOUT_P CIE0P
J2
PCIECLKR Q0# / GPIO73
AB49
CLKOUT_P CIE1N
AB47
CLKOUT_P CIE1P
M1
PCIECLKR Q1# / GPIO18
AA48
CLKOUT_P CIE2N
AA47
CLKOUT_P CIE2P
V10
PCIECLKR Q2# / GPIO20
Y37
CLKOUT_P CIE3N
Y36
CLKOUT_P CIE3P
A8
PCIECLKR Q3# / GPIO25
Y43
CLKOUT_P CIE4N
Y45
CLKOUT_P CIE4P
L12
PCIECLKR Q4# / GPIO26
V45
CLKOUT_P CIE5N
V46
CLKOUT_P CIE5P
L14
PCIECLKR Q5# / GPIO44
AB42
CLKOUT_P EG_B_N
AB40
CLKOUT_P EG_B_P
E6
PEG_B_CL KRQ# / GPIO56
V40
CLKOUT_P CIE6N
V42
CLKOUT_P CIE6P
T13
PCIECLKR Q6# / GPIO45
V38
CLKOUT_P CIE7N
V37
CLKOUT_P CIE7P
K12
PCIECLKR Q7# / GPIO46
AK14
CLKOUT_IT PXDP_N
AK13
CLKOUT_IT PXDP_P
PANTHE R-POINT_FCBGA98 9
PANTHE R-POINT_FCBGA98 9
HM76@
HM76@
SMBUSController
SMBUSController
SML1ALE RT# / PCHHOT# / GPIO74
PCI-E*
PCI-E*
CLOCKS
CLOCKS
3
SMBALER T# / GPIO11
SML0ALE RT# / GPIO60
SML0DAT A
SML1CLK / GPIO58
SML1DAT A / GPIO75
Link
Link
PEG_A_CL KRQ# / GPIO47
CLKOUT_P EG_A_N
CLKOUT_P EG_A_P
CLKOUT_D MI_N
CLKOUT_D MI_P
CLKOUT_D P_N
CLKOUT_D P_P
CLKIN_DM I_N
CLKIN_DM I_P
CLKIN_GND 1_N
CLKIN_GND 1_P
CLKIN_DOT _96N
CLKIN_DOT _96P
CLKIN_SA TA_N
CLKIN_SA TA_P
REFCLK1 4IN
CLKIN_PC ILOOPBACK
XTAL25_IN
XTAL25_OU T
XCLK_RC OMP
CLKOUTFL EX0 / GPIO64
CLKOUTFL EX1 / GPIO65
CLKOUTFL EX2 / GPIO66
CLKOUTFL EX3 / GPIO67
FLEX CLOCKS
FLEX CLOCKS
E12
H14
SMBCLK
C9
SMBDAT A
A12
C8
SML0CLK
G12
C13
E14
M16
M7
CL_CLK1
T11
CL_DATA 1
P10
CL_RST1#
M10
AB37
AB38
AV22
AU22
AM12
AM13
BF18
BE18
BJ30
BG30
G24
E24
AK7
AK5
K45
H45
V47
V49
Y47
K43
F47
H47
K49
BIOS Request SKU ID
PCH_GPI01 1
PCH_SM BCLK
PCH_SM BDATA
DRAMRS T_CNTRL_PCH
PCH_SM L0CLK
PCH_SM L0DATA
PCH_HOT #
SML1CLK
SML1DAT A
CLK_PCIE _VGA#_R
CLK_PCIE _VGA_R
CLK_CPU _DMI#
CLK_CPU _DMI
CLK_BUF _CPU_DMI#
CLK_BUF _CPU_DMI
CLKIN_DM I2#
CLKIN_DM I2
CLK_BUF _DREF_96M#
CLK_BUF _DREF_96M
CLK_BUF _PCIE_SATA#
CLK_BUF _PCIE_SATA
CLK_BUF _ICH_14M
CLK_PCI_L PBACK
XTAL25_IN
XTAL25_OU T
XCLK_RC OMP
27M_SSC
PCH_GPIO67
R140 10K_0402_ 5%R140 10K_0402_5%
+3V_PCH
1 2
12
R134 10K_0402_ 5%R134 10K_0402_5%
1K_0402_5%
12
R143
R143
10K_0402_5 %
10K_0402_5 %
1 2
R145 10K_0402_ 5%
R145 10K_0402_ 5%
1 2
R168 0_0402_5%@R168 0_0402_5%@
1 2
R172 0_0402_5%@R172 0_0402_5%@
CLK_CPU _DMI# <6>
CLK_CPU _DMI <6>
1 2
R155 10K_0402_ 5%R1 55 10K_0402_5%
1 2
R157 10K_0402_ 5%R1 57 10K_0402_5%
1 2
R159 10K_0402_ 5%R1 59 10K_0402_5%
1 2
R160 10K_0402_ 5%R1 60 10K_0402_5%
1 2
R162 10K_0402_ 5%R1 62 10K_0402_5%
1 2
R163 10K_0402_ 5%R1 63 10K_0402_5%
1 2
R164 10K_0402_ 5%R1 64 10K_0402_5%
1 2
R166 10K_0402_ 5%R1 66 10K_0402_5%
1 2
R167 10K_0402_ 5%R1 67 10K_0402_5%
R171
R171
90.9_0402_1%
90.9_0402_1%
1 2
PCH_GPIO67 <19>
1K_0402_5%
+3V_PCH
@
@
For EMI
CLK_PCI_L PBACK <18 >
2
+3V_PCH
12
R139
R139
+V1.05S_VCCP
DRAMRS T_CNTRL_PCH <10,7>
+3V_PCH
CLK_REQ_ VGA# <24>
CLK_PCIE _VGA# <23>
CLK_PCIE _VGA <23>
XTAL25_IN
XTAL25_OU T
C196
C196
12P_0402_5 0V8J
12P_0402_5 0V8J
Q60A
Q60A
2N7002DW -T/R7_SOT363-6
2N7002DW -T/R7_SOT363-6
6 1
3
6 1
3
SMB_CLK _S3SMB _CLK_S3
2
+3VS
5
4
SMB_DA TA_S3SMB_DA TA_S3
2N7002DW -T/R7_SOT363-6
2N7002DW -T/R7_SOT363-6
Q60B
Q60B
Q61A
Q61A
2N7002DW -T/R7_SOT363-6
2N7002DW -T/R7_SOT363-6
2N7002DW -T/R7_SOT363-6
2N7002DW -T/R7_SOT363-6
Q61B
Q61B
EC_SMB _CK2
2
+3VS
5
4
EC_SMB _DA2
1 2
R169 1M_0402 _5%R169 1M _0402_5%
3
2
Y2
Y2
25MHZ_10 PF_7V25000014
25MHZ_10 PF_7V25000014
1
2
OSC
NC
1
SMB_CLK _S3 <12,13,36>
DIMM1
DIMM2
Mini Card
SMB_DA TA_S3 < 12,13,36>
EC_SMB _CK2 <24,39,42>
VGA
EC
Thermal Sensor
EC_SMB _DA2 <24,39,42>
2.2K_0402_5 %
2.2K_0402_5 %
PCH_SM L0CLK
PCH_SM L0DATA
SML1DAT A
EC_SMB _DA2
SML1CLK
EC_SMB _CK2
PCH_SM BCLK
SMB_CLK _S3
PCH_SM BDATA
SMB_DA TA_S3
4
NC
1
OSC
1
12P_0402_5 0V8J
12P_0402_5 0V8J
2
+3V_PCH
R544
R544
1 2
1 2
+3V_PCH
RP23
RP23
18
27
36
45
2.2K_0804_8 P4R_5%
2.2K_0804_8 P4R_5%
+3V_PCH
RP24
RP24
18
27
36
45
2.2K_0804_8 P4R_5%
2.2K_0804_8 P4R_5%
C197
C197
R545
R545
2.2K_0402_5 %
2.2K_0402_5 %
+3VS
+3VS
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
3
2011/06/15 2012/07/11
2011/06/15 2012/07/11
2011/06/15 2012/07/11
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
PCH (2/9) PCIE, SMBUS, CLK
PCH (2/9) PCIE, SMBUS, CLK
PCH (2/9) PCIE, SMBUS, CLK
LA-9631P
LA-9631P
LA-9631P
1
15 60Wednesday, February 27, 2 013
15 60Wednesday, February 27, 2 013
15 60Wednesday, February 27, 2 013
1.0
1.0
1.0
5
D D
@
@
U15
U15
MC74VHC 1G08DFT2G SC70 5P
MC74VHC 1G08DFT2G SC70 5P
3
1
VGATE<42,54>
PCH_PW ROK
C C
+3V_PCH
12
B B
R194 10K_0402 _5%R194 10K_0402 _5%
R197 10K_0402 _5%
R197 10K_0402 _5%
+3V_PCH
R309 200K_040 2_5%R309 200K_040 2_5%
R192 300_0402_5%R192 300_0402 _5%
12
12
@
@
1 2
A
2
B
+3VS
G
4
Y
P
5
PM_DRA M_PWRGD
SUSW ARN#
EC_RSMRST#
AC_PRES ENT_R
SYS_PWR OK
12
@
@
R180
R180
10K_0402_5 %
10K_0402_5 %
PCH_PW ROK<42>
PM_DRA M_PWRGD<6>
EC_RSM RST#<42>
PBTN_OUT #<42>
ACIN<24,4 2,46,48>
4
DMI_CTX_ PRX_N0<5>
DMI_CTX_ PRX_N1<5>
DMI_CTX_ PRX_N2<5>
DMI_CTX_ PRX_N3<5>
DMI_CTX_ PRX_P0<5>
DMI_CTX_ PRX_P1<5>
DMI_CTX_ PRX_P2<5>
DMI_CTX_ PRX_P3<5>
DMI_CRX _PTX_N0<5>
DMI_CRX _PTX_N1<5>
DMI_CRX _PTX_N2<5>
DMI_CRX _PTX_N3<5>
DMI_CRX _PTX_P0<5>
DMI_CRX _PTX_P1<5>
DMI_CRX _PTX_P2<5>
DMI_CRX _PTX_P3<5>
+V1.05S_VCCP
SUSACK# is only used on platfor m
that support the Deep Sx state.
D29
D29
CH751H-40 PT_SOD323-2
CH751H-40 PT_SOD323-2
1 2
R177 49.9_0402_1%R177 49.9_0402_1%
1 2
R178 750_0402_1%R178 750_0402_1%
4mil width and place
within 500mil of the PCH
SYS_RST#<19>
SYS_PWR OK<42>
21
DMI_CTX_ PRX_N0
DMI_CTX_ PRX_N1
DMI_CTX_ PRX_N2
DMI_CTX_ PRX_N3
DMI_CTX_ PRX_P0
DMI_CTX_ PRX_P1
DMI_CTX_ PRX_P2
DMI_CTX_ PRX_P3
DMI_CRX _PTX_N0
DMI_CRX _PTX_N1
DMI_CRX _PTX_N2
DMI_CRX _PTX_N3
DMI_CRX _PTX_P0
DMI_CRX _PTX_P1
DMI_CRX _PTX_P2
DMI_CRX _PTX_P3
DMI_IRCOM P
RBIAS_CP Y
SYS_RST#
SYS_PWR OK
PCH_PWROK
PM_DRA M_PWRGD
SUSW ARN#
AC_PRES ENT_R
PCH_GPIO72
RI#
U4C
U4C
BC24
DMI0RXN
BE20
DMI1RXN
BG18
DMI2RXN
BG20
DMI3RXN
BE24
DMI0RXP
BC20
DMI1RXP
BJ18
DMI2RXP
BJ20
DMI3RXP
AW24
DMI0TXN
AW20
DMI1TXN
BB18
DMI2TXN
AV18
DMI3TXN
AY24
DMI0TXP
AY20
DMI1TXP
AY18
DMI2TXP
AU18
DMI3TXP
BJ24
DMI_ZCOM P
BG25
DMI_IRCOM P
BH21
DMI2RBIAS
C12
SUSACK #
K3
SYS_RESET #
P12
SYS_PWR OK
L22
PWROK
L10
APWR OK
B13
DRAMPW ROK
C21
RSMRST #
K16
SUSW ARN#/SUSPW RDNACK/GPIO30
E20
PWRB TN#
H20
ACPRES ENT / GPIO31
E10
BATLOW # / GPIO72
A10
RI#
PANTHE R-POINT_FCBGA98 9
PANTHE R-POINT_FCBGA98 9
HM76@
HM76@
3
BJ14
FDI_RXN0
AY14
FDI_RXN1
BE14
FDI_RXN2
BH13
FDI_RXN3
BC12
FDI_RXN4
BJ12
FDI_RXN5
BG10
FDI_RXN6
BG9
FDI_RXN7
BG14
FDI_RXP0
BB14
FDI_RXP1
BF14
FDI_RXP2
BG13
FDI_RXP3
BE12
FDI_RXP4
BG12
FDI_RXP5
BJ10
FDI_RXP6
DMI
FDI
DMI
FDI
FDI_FSYNC0
FDI_FSYNC1
CLKRUN # / GPIO32
SUS_STA T# / GPIO61
SUSCLK / GP IO62
SLP_S5# / GPIO6 3
System Power Management
System Power Management
SLP_LAN# / GPIO29
FDI_RXP7
FDI_INT
FDI_LSYNC0
FDI_LSYNC1
DSWV RMEN
DPWR OK
WAKE#
SLP_S4#
SLP_S3#
SLP_A#
SLP_SUS #
PMSYNCH
BH9
AW16
AV12
BC10
AV14
BB10
A18
E22
B9
N3
G8
N14
D10
H4
F4
G10
G16
AP14
K14
2
FDI_CTX_P RX_N0
FDI_CTX_P RX_N1
FDI_CTX_P RX_N2
FDI_CTX_P RX_N3
FDI_CTX_P RX_N4
FDI_CTX_P RX_N5
FDI_CTX_P RX_N6
FDI_CTX_P RX_N7
FDI_CTX_P RX_P0
FDI_CTX_P RX_P1
FDI_CTX_P RX_P2
FDI_CTX_P RX_P3
FDI_CTX_P RX_P4
FDI_CTX_P RX_P5
FDI_CTX_P RX_P6
FDI_CTX_P RX_P7
FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
DSWOD VREN
EC_RSMRST#
PM_CLKR UN#
SUS_STA T#
FDI_CTX_P RX_N0 <5>
FDI_CTX_P RX_N1 <5>
FDI_CTX_P RX_N2 <5>
FDI_CTX_P RX_N3 <5>
FDI_CTX_P RX_N4 <5>
FDI_CTX_P RX_N5 <5>
FDI_CTX_P RX_N6 <5>
FDI_CTX_P RX_N7 <5>
FDI_CTX_P RX_P0 <5>
FDI_CTX_P RX_P1 <5>
FDI_CTX_P RX_P2 <5>
FDI_CTX_P RX_P3 <5>
FDI_CTX_P RX_P4 <5>
FDI_CTX_P RX_P5 <5>
FDI_CTX_P RX_P6 <5>
FDI_CTX_P RX_P7 <5>
FDI_INT <5>
FDI_FSYNC0 < 5>
FDI_FSYNC1 < 5>
FDI_LSYNC0 <5>
FDI_LSYNC1 <5>
PCIE_W AKE# <36>
SUSCLK <42>
PM_SLP_ S5# <4 2>
PM_SLP_ S4# <4 2>
PM_SLP_ S3# <4 2>
Can be left NC when IAMT is not support on the platfrom
H_PM_SYNC
H_PM_SYNC <6>
Can be left NC i f no use integr ated LAN.
1
DSWOD VREN
*
R299 10K_0402 _5%R299 10K_0402 _5%
R179 330K_0402 _5%R179 330K_0402 _5%
R183 330K_0402 _5%@R183 330K _0402_5%@
DSWODVREN - On D ie DSW VR Enabl e
HEnable
LDisable
12
+RTCVCC
12
12
+3V_PCH
RP25
RP25
18
A A
10K_0804_8 P4R_5%
10K_0804_8 P4R_5%
27
36
45
5
PCIE_W AKE#
RI#
EC_SMI#
EC_SMI# <19 ,42>
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
3
2011/06/15 2012/07/11
2011/06/15 2012/07/11
2011/06/15 2012/07/11
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
PCH (3/9) DMI,FDI,PM,
PCH (3/9) DMI,FDI,PM,
PCH (3/9) DMI,FDI,PM,
LA-9631P
LA-9631P
LA-9631P
1
1.0
1.0
16 60Wednesday, February 27, 2 013
16 60Wednesday, February 27, 2 013
16 60Wednesday, February 27, 2 013
1.0
5
R438
D D
C C
R438
100K_0402_1%
100K_0402_1%
+3VS
RP14
RP14
2.2K_0804_8P4R_5%
2.2K_0804_8P4R_5%
RP20
RP20
150_0804_8P4R_1%
150_0804_8P4R_1%
12
18
EDID_DATA
27
EDID_CLK
36
CTRL_DATA
45
CTRL_CLK
18
DAC_BLU
27
DAC_GRN
36
DAC_RED
45
ENBKL
Max = 800 mils
DAC_BLU<34>
B B
+3VS
12
12
R524
R559
R559
2.2K_0402_5%
2.2K_0402_5%
R524
2.2K_0402_5%
2.2K_0402_5%
CRT_DDC_CL K
CRT_DDC_DAT A
DAC_GRN<34>
DAC_RED<34>
4
U4D
U4D
CRT_IREF
12
J47
L_BKLTEN
M45
L_VDD_EN
P45
L_BKLTCTL
T40
L_DDC_CLK
K47
L_DDC_DATA
T45
L_CTRL_CLK
P39
L_CTRL_DATA
AF37
LVD_IBG
AF36
LVD_VBG
AE48
LVD_VREFH
AE47
LVD_VREFL
AK39
LVDSA_CLK#
AK40
LVDSA_CLK
AN48
LVDSA_DATA#0
AM47
LVDSA_DATA#1
AK47
LVDSA_DATA#2
AJ48
LVDSA_DATA#3
AN47
LVDSA_DATA0
AM49
LVDSA_DATA1
AK49
LVDSA_DATA2
AJ47
LVDSA_DATA3
AF40
LVDSB_CLK#
AF39
LVDSB_CLK
AH45
LVDSB_DATA#0
AH47
LVDSB_DATA#1
AF49
LVDSB_DATA#2
AF45
LVDSB_DATA#3
AH43
LVDSB_DATA0
AH49
LVDSB_DATA1
AF47
LVDSB_DATA2
AF43
LVDSB_DATA3
N48
CRT_BLUE
P49
CRT_GREEN
T49
CRT_RED
T39
CRT_DDC_CL K
M40
CRT_DDC_DAT A
M47
CRT_HSYNC
M49
CRT_VSYNC
T43
DAC_IREF
T42
CRT_IRTN
PANTHER-POINT_FCBGA989
PANTHER-POINT_FCBGA989
HM76@
HM76@
ENBKL<42>
PCH_ENVDD<33>
PCH_PWM<33>
EDID_CLK<33>
EDID_DATA<33>
12
R2062.37K_0402_1 % R20 62.37K_0402_1%
LVDS_ACLK#<33>
LVDS_ACLK<33>
LVDS_A0#<33>
LVDS_A1#<33>
LVDS_A2#<33>
LVDS_A0<33>
LVDS_A1<33>
LVDS_A2<33>
CRT_DDC_CL K<34>
CRT_DDC_DAT A<34>
CRT_HSYNC<34>
CRT_VSYNC<34>
DAC_BLU
DAC_GRN
DAC_RED
1K_0402_1%
1K_0402_1%
EDID_CLK
EDID_DATA
CTRL_CLK
CTRL_DATA
LVDS_IBG
LVD_VREF
CRT_DDC_CL K
CRT_DDC_DAT A
R211
R211
3
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
AP43
AP45
AM42
AM40
AP39
AP40
P38
M39
AT49
AT47
AT40
AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49
P46
P42
AP47
AP49
AT38
AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49
M43
M36
AT45
AT43
BH41
BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42
SDVO_TVCLKINN
SDVO_TVCLKINP
SDVO_STALLN
SDVO_STALLP
SDVO_INTN
SDVO_INTP
SDVO_CTRLCLK
SDVO_CTRLDATA
DDPB_AUXN
DDPB_AUXP
DDPB_HPD
LVDS
LVDS
DDPC_CTRLCLK
DDPC_CTRLDAT A
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
Digital Display Interface
Digital Display Interface
DDPD_CTRLCLK
DDPD_CTRLDAT A
DDPD_AUXN
DDPD_AUXP
CRT
CRT
DDPD_HPD
HDMICLK_NB
HDMIDAT_NB
TMDS_B_DATA2#_PCH
TMDS_B_DATA2_PCH
TMDS_B_DATA1#_PCH
TMDS_B_DATA1_PCH
TMDS_B_DATA0#_PCH
TMDS_B_DATA0_PCH
TMDS_B_CLK#_PCH
TMDS_B_CLK_PCH
2
HDMICLK_NB <35>
HDMIDAT_NB <3 5>
TMDS_B_HPD# <35>
1 2
C200 .1U_0402_16V7KHDMI@ C200 .1U_0402 _16V7KHDMI@
1 2
C201 .1U_0402_16V7KHDMI@ C201 .1U_0402 _16V7KHDMI@
1 2
C202 .1U_0402_16V7KHDMI@ C202 .1U_0402 _16V7KHDMI@
1 2
C203 .1U_0402_16V7KHDMI@ C203 .1U_0402 _16V7KHDMI@
1 2
C204 .1U_0402_16V7KHDMI@ C204 .1U_0402 _16V7KHDMI@
1 2
C205 .1U_0402_16V7KHDMI@ C205 .1U_0402 _16V7KHDMI@
1 2
C206 .1U_0402_16V7KHDMI@ C206 .1U_0402 _16V7KHDMI@
1 2
C207 .1U_0402_16V7KHDMI@ C207 .1U_0402 _16V7KHDMI@
CAP move on Conn, side
HDMI_TX2-_CK <35>
HDMI_TX2+_CK <35>
HDMI_TX1-_CK <35>
HDMI_TX1+_CK <35>
HDMI_TX0-_CK <35>
HDMI_TX0+_CK <35>
HDMI_CLK-_CK <35>
HDMI_CLK+_CK <35>
1
HDMI D2
HDMI D1
HDMI
HDMI D0
HDMI CLK
A A
Security Classification
Security Classification
Security Classification
2011/06/15 2012/07/11
2011/06/15 2012/07/11
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2011/06/15 2012/07/11
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Title
Title
Title
PCH (4/9) LVDS,CRT,DP,HDMI
PCH (4/9) LVDS,CRT,DP,HDMI
PCH (4/9) LVDS,CRT,DP,HDMI
Size Docum ent Number Rev
Size Docum ent Number Rev
Size Docum ent Number Rev
B
B
B
LA-9631P
LA-9631P
LA-9631P
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
17 60Wednesday, February 27, 2013
17 60Wednesday, February 27, 2013
17 60Wednesday, February 27, 2013
1
1.0
1.0
1.0
5
RP1
RP1
RP7
RP7
1 2
1 2
Bit11
0 1
1
1
0
1
2
3
4
5
8.2K_1206_10P8R_5%
8.2K_1206_10P8R_5%
18
27
36
45
Pull-up resistors are not required
on these signals
Boot BIOS
Destination
Bit10
0
1
*
0
PCI_PIRQA#
PCI_PIRQD#
PCI_PIRQC#
PCI_PIRQB#
+3VS
D D
+3VS
8.2K_0804_8P4R_5%
8.2K_0804_8P4R_5%
R292 8.2K_0402_5%@R292 8.2K_0402_5%@
R557 8.2K_0402_5%@R557 8.2K_0402_5%@
C C
Boot BIOS Strap bit1 BBS1
GNT1#/
GPIO51
B B
+3VS
10
9
PCH_GPIO2
8
DGPU_PWR_EN
7
PCH_GPIO4
6
PCH_GPIO3
DGPU_HOLD_RST#
PCH_WL_OFF#
PCH_GPIO5
PCH_GPIO52
PCH_GPIO51
PCH_GPIO53
Reserved
Reserved
SPI
(Default)
LPC
DGPU_HOLD_RST#<23>
DGPU_PWR_EN<25,42,51,53>
PCH_WL_OFF#<36>
GPIO55
PCH_WL_OFF#
A16 swap overide Strap/Top-Block
Swap Override jumper
PCI_GNT3#
A A
1 2
R215 1K_0402_5%@R215 1K_0402_5%@
Low=A16 swap
override/Top-Block
Swap Override enabled
High=Default
PLT_RST#<23,36,37,42>
1U_0402_6.3V6K
1U_0402_6.3V6K
5
C208
*
@C208
@
CLK_PCI_LPBACK<15>
CLK_PCI_EC<42>
R222
@ R222
@
1 2
0_0402_5%
0_0402_5%
12
1
R223
R223
100K_0402_5%
100K_0402_5%
2
USB3_RX1_N<44>
USB3_RX2_N<44>
USB3_RX1_P<44>
USB3_RX2_P<44>
USB3_TX1_N<44>
USB3_TX2_N<44>
USB3_TX1_P<44>
USB3_TX2_P<44>
PCH_PLTRST#
4
USB3_RX1_N
USB3_RX2_N
USB3_RX3_N
USB3_RX4_N
USB3_RX1_P
USB3_RX2_P
USB3_RX3_P
USB3_RX4_P
USB3_TX1_N
USB3_TX2_N
USB3_TX3_N
USB3_TX4_N
USB3_TX1_P
USB3_TX2_P
USB3_TX3_P
USB3_TX4_P
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCH_GPIO52
PCH_GPIO51
PCH_GPIO53
PCH_WL_OFF#
PCH_GPIO2
PCH_GPIO3
PCH_GPIO4
PCH_GPIO5
PCI_PME#
PCH_PLTRST#<6>
1 2
1 2
For EMI
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PCH_PLTRST#
CLK_PCI_LPBACK_R
R21922_0402_5% R21922_0402_5%
CLK_PCI_EC_R
R22022_0402_5% R22022_0402_5%
CLK_PCI_DB_R
3
U4E
U4E
BG26
TP1
BJ26
TP2
BH25
TP3
BJ16
TP4
BG16
TP5
AH38
TP6
AH37
TP7
AK43
TP8
AK45
TP9
C18
TP10
N30
TP11
H3
TP12
AH12
TP13
AM4
TP14
AM5
TP15
Y13
TP16
K24
TP17
L24
TP18
AB46
TP19
AB45
TP20
B21
TP21
M20
TP22
AY16
TP23
BG46
TP24
BE28
USB3Rn1
BC30
USB3Rn2
BE32
USB3Rn3
BJ32
USB3Rn4
BC28
USB3Rp1
BE30
USB3Rp2
BF32
USB3Rp3
BG32
USB3Rp4
AV26
USB3Tn1
BB26
USB3Tn2
AU28
USB3Tn3
AY30
USB3Tn4
AU26
USB3Tp1
AY26
USB3Tp2
AV28
USB3Tp3
AW30
USB3Tp4
K40
PIRQA#
K38
PIRQB#
H38
PIRQC#
G38
PIRQD#
C46
REQ1# / GPIO50
C44
REQ2# / GPIO52
E40
REQ3# / GPIO54
D47
GNT1# / GPIO51
E42
GNT2# / GPIO53
F46
GNT3# / GPIO55
G42
PIRQE# / GPIO2
G40
PIRQF# / GPIO3
C42
PIRQG# / GPIO4
D44
PIRQH# / GPIO5
K10
PME#
C6
PLTRST#
H49
CLKOUT_PCI0
H43
CLKOUT_PCI1
J48
CLKOUT_PCI2
K42
CLKOUT_PCI3
H40
CLKOUT_PCI4
PANTHER-POINT_FCBGA989
PANTHER-POINT_FCBGA989
HM76@
HM76@
2011/06/15 2012/07/11
2011/06/15 2012/07/11
2011/06/15 2012/07/11
3
RSVD
RSVD
PCI
PCI
USB
USB
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
USBRBIAS#
USBRBIAS
OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
AY7
AV7
AU3
BG4
AT10
BC8
AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6
AV5
AV10
AT8
AY5
BA2
AT12
BF3
C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32
C33
B33
A14
K20
B17
C16
L16
A16
D14
C14
2
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N9
USB20_P9
USB20_N10
USB20_P10
USB20_N11
USB20_P11
USBRBIAS
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#
2
USB Debug Port = Port1 and Port9
USB20_N0 <44>
USB20_P0 <44>
USB20_N1 <44>
USB20_P1 <44>
USB20_N2 <44>
USB20_P2 <44>
USB20_N3 <33>
USB20_P3 <33>
USB20_N9 <44>
USB20_P9 <44>
USB20_N10 <36>
USB20_P10 <36>
USB20_N11 <43>
USB20_P11 <43>
1 2
R218
R218
22.6_0402_1%
22.6_0402_1%
Within 500 mils
For LEFT USB3.0 Port
For RIGHT USB2.0 Port
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
LEFT USB
LEFT USB
Touch Screen
USB Camera
RIGHT USB
WLAN
CARD READER
USB_OC0# <44>
USB_OC4# <44>
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
+3V_PCH
PCH (5/9) PCI, USB
PCH (5/9) PCI, USB
PCH (5/9) PCI, USB
LA-9631P
LA-9631P
LA-9631P
(USB 3.0)
RP18
RP18
1
2
3
4
5
10K_1206_10P8R_5%
10K_1206_10P8R_5%
1
+3V_PCH
10
9
USB_OC4#
8
USB_OC5#
7
USB_OC6#
6
USB_OC7#
1.0
1.0
1.0
18 60Wednesday, February 27, 2013
18 60Wednesday, February 27, 2013
18 60Wednesday, February 27, 2013
1
5
D D
GPIO28
On-Die PLL Voltage Regulator
This signal has a weak internal pull up
HOn-Die voltage regulator enable
*
LOn-Die PLL Voltage Regulator disable
*
PCH_GPIO27 (Have internal Pull-High)
High: VCCVRM VR Enable
Low: VCCVRM VR Disable
C C
+3VS
12
12
@
@
B B
BIOS Request SKU ID
R711
R711
UMA@
UMA@
R708
R708
PX@
PX@
A A
1 2
R240 1K_0402_5%@R24 0 1K_0402_5 %@
1 2
R245 10K_0402_5%@R2 45 10K_0402 _5%@
GPIO36, 37
When Unused as GPIO or SATA*GP
Use 8.2K-10K pull-down to ground.
R244
@R244
@
10K_0402_5 %
10K_0402_5 %
PCH_GPIO37 PCH _GPIO36
R881
R881
10K_0402_5 %
10K_0402_5 %
+3VS
12
R246
R246
UMA@
UMA@
1 2
1 2
0K_0402_5%
0K_0402_5%
0K_0402_5%
0K_0402_5%
1
1
1
1
PCH_GPIO38
PCH_GPIO67
12
R298
R298
PX@
PX@
0K_0402_5%
0K_0402_5%
0K_0402_5%
0K_0402_5%
1
1
1
1
PCH_GPIO27
+3VS
12
R250
@R250
@
10K_0402_5 %
10K_0402_5 %
12
R547
@R547
@
10K_0402_5 %
10K_0402_5 %
PCH_GPIO67 <15>
PCH_GPIO38 PCH_GPIO67
0
0 1
1
EC_LID_OU T#< 42>
DGPU_PW ROK<53>
PU on power side
PCH_BT_ ON#<36>
+3VS
10K_0804_8 P4R_5%
10K_0804_8 P4R_5%
Function
0
SG(Optimus / PX)
Reserved
0
DIS
RP10
RP10
+3V_PCH
18
27
36
45
+3VS
INTEL_BT_ OFF#<36>
PCH_GPIO39
SYS_RST#
PCH_BT_ ON#
PCH_GPIO35
1 1 UMA
5
4
1 2
PCH_GPIO16<14>
+3V_PCH
1 2
1 2
4
EC_SCI#<42>
EC_SMI#<16,42>
R230 1K_0402_5%R230 1K_0402_ 5%
ODD_EN<40>
R241
R241
10K_0402_5 %
10K_0402_5 %
R242 10K_ 0402_5%R242 10K_0402_5 %
SYS_RST# <16>
PCH_GPIO69 PCH_GPIO70
1 1
1
0 HM76
U4F
U4F
PCH_GPIO0
PCH_GPIO1
PCH_GPIO6
EC_SCI#
EC_SMI#
PCH_GPIO12PCH_GPIO28
EC_LID_OU T#
PCH_GPIO16
PCH_BT_ ON#
ODD_EN
PCH_GPIO27
PCH_GPIO28
INTEL_BT_ OFF#
PCH_GPIO35
PCH_GPIO36
PCH_GPIO37
PCH_GPIO38
PCH_GPIO39
PCH_GPIO48
PCH_GPIO49
PCH_GPIO57
T7
BMBUSY# / GPIO 0
A42
TACH1 / GPIO1
H36
TACH2 / GPIO6
E38
TACH3 / GPIO7
C10
GPIO8
C4
LAN_PHY_PW R_CTRL / GPIO12
G2
GPIO15
U2
SATA4GP / GPIO16
D40
TACH0 / GPIO17
T5
SCLOCK / GPIO22
E8
GPIO24
E16
GPIO27
P8
GPIO28
K1
STP_PCI# / GPIO34
K4
GPIO35
V8
SATA2GP / GPIO36
M5
SATA3GP / GPIO37
N2
SLOAD / GPIO38
M3
SDATAOUT0 / G PIO39
V13
SDATAOUT1 / G PIO48
V3
SATA5GP / GPIO49 / TEMP_ALERT#
D6
GPIO57
A4
VSS_NCTF_1
A44
VSS_NCTF_2
A45
VSS_NCTF_3
A46
VSS_NCTF_4
A5
VSS_NCTF_5
A6
VSS_NCTF_6
B3
VSS_NCTF_7
B47
VSS_NCTF_8
BD1
VSS_NCTF_9
BD49
VSS_NCTF_10
BE1
VSS_NCTF_11
BE49
VSS_NCTF_12
BF1
VSS_NCTF_13
BF49
VSS_NCTF_14
PANTHE R-POINT_FCBGA98 9
PANTHE R-POINT_FCBGA98 9
HM76@
HM76@
Security Classification
Security Classification
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
0
10
0
Issued Date
Issued Date
Issued Date
3
Function
NM70
Reserved
HM70
3
+3VS +3VS
NM70@
NM70@
R702
R702
1 2
PCH_GPIO69 PCH_GPIO70
HM70@
HM70@
R707
R707
10K_0402_5 %
10K_0402_5 %
TACH4 / GPIO68
TACH5 / GPIO69
TACH6 / GPIO70
TACH7 / GPIO71
A20GATE
PECI
RCIN#
PROCPW RGD
GPIO
GPIO
THRMTRIP#
INIT3_3V#
DF_TVS
CPU/MISC
CPU/MISC
TS_VSS1
TS_VSS2
TS_VSS3
TS_VSS4
NC_1
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
NCTF
NCTF
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31
VSS_NCTF_32
2011/06/15 2012/07/11
2011/06/15 2012/07/11
2011/06/15 2012/07/11
10K_0402_5%
10K_0402_5%
HM76@
HM76@
R707
R707
1 2
10K_0402_5%
10K_0402_5%
C40
PCH_GPIO68
B41
PCH_GPIO69
C41
PCH_GPIO70
A40
PCH_GPIO71
P4
AU16
P5
KBRST#
AY11
AY10
PCH_THR MTRIP#_R
T14
AY1
AH8
AK11
AH10
AK10
P37
BG2
BG48
BH3
BH47
BJ4
BJ44
BJ45
BJ46
BJ5
BJ6
C2
C48
D1
D49
E1
E49
F1
F49
Compal Secret Data
Compal Secret Data
Compal Secret Data
INIT3_3V
This signal has weak internal P U,can't pull low
NV_CLE
Deciphered Date
Deciphered Date
Deciphered Date
2
NM70@
NM70@
R703
R703
1 2
HM76@
HM76@
R705
R705
1 2
1 2
R239 390_0402_5%R239 390_0402_5%
2
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
HM70@
HM70@
R703
R703
10K_0402_5 %
10K_0402_5 %
KBRST# <4 2>
H_CPUPW RGD < 6>
H_THRM TRIP#
PCH_GPIO71
1
0
+3VS
R236
R236
10K_0402_5 %
10K_0402_5 %
1 2
NV_CLE
Weak internal
PU,Do not pull low
GATEA20 <42>
DMI Termination Voltage
Set to Vcc when HIGH
Set to Vss when LOW
Title
Title
Title
Size Document Nu mber Rev
Size Document Nu mber Rev
Size Document Nu mber Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
Function
1 2
R216
R216
2.2K_0402_5 %
2.2K_0402_5 %
H_SNB_IV B# <6>
1
PCH_GPIO71
200K_0402_ 5%
200K_0402_ 5%
19 6 0Wednesday, February 27, 2013
19 6 0Wednesday, February 27, 2013
19 6 0Wednesday, February 27, 2013
Mars XT
Sun Pro
KBRST#
R226 10K_0402_5%R2 26 10K_0402 _5%
H_THRM TRIP# <6>
+1.8VS
12
12
R217 1K_04 02_5%R217 1K_0402_5 %
CLOSE TO THE BRA NCHING POINT
PCH (6/9) GPIO, CPU, MISC
PCH (6/9) GPIO, CPU, MISC
PCH (6/9) GPIO, CPU, MISC
LA-9631P
LA-9631P
LA-9631P
Mars@
Mars@
R704
R704
R706
R706
Sun@
Sun@
+3VS
1 2
10K_0402_5%
10K_0402_5%
1 2
+3VS
1.0
1.0
1.0
Compal Electronics, Inc.
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