Lenovo Foxcon S09 Schematics

LCD/BTN

www.hocnghetructuyen.vn

Ext MIC In

LineOut

AC'97

27

CODEC RTLALC655

27

DDR2

400/533

Audio DJ

26

S09 Block Diagram

CLK GEN

ICS954226

11

LPC BUS

28

AC-Link

MODEM

1.0

20

03

Mobile CPU

Dothan

400/533MHzHOST BUS

Alviso

06,07,08,09,10

100MHzDMI I/F

ICH6-M

04.05

GM GML

Thermal

G768D

18

T8

MAX6510

18

RGB

LVDS

S-Video

PCI BUS

CRT

12

LCD

XGA

13

TV-OUT

12

Cardbus ENE CB851 /CB1410

Mini-PCI

802.11 B/G

29

22

PWR SW

CP2211

CARDBUS

ONE SLOT

1394

23

SYSTEM DC/DC

MAX1999

INPUTS

DCBATOUT

SYSTEM DC/DC

OZ824

INPUTS OUTPUTS

DCBATOUT

SC486

DCBATOUT

OUTPUTS

5V_S5 3V_S5 5V_AUX 3D3V_AUX

1D05V_S0 1D5V_S0

1D8V_S3 0D9V_S0

MAXIM CHARGER

OZ8604

OUTPUTSINPUTS BT+

DCBATOUT

19V 3.0A

5V_AUX

5V 100mA

CPU DC/DC

SC450

INPUTS

DCBATOUT

OUTPUTS VCC_CORE

0.844~1.3V 27A

36

37

38

35

39

OP AMP

Speaker

27

TPA6017A2

USB

3 PORT

27

21

USB

14.15.16.17

PATA

HDD (master)

19 19

LCI

LPC BUS

ODD (slave)

KBC ENE 3910

Touch Pad

31 31

Intel LAN 82562GT

30

24

XD

SMBus

INT_KB

TXFM

BIOS 8/4Mb

30

MXA 6999MP

32

EEPROM AT24C01A

25 25

32

PCB LAYER

RJ45

Title

Block Diagram

Document Number Rev

S09 MAINBOARD

Date: Sheet of

L1: L2: L3: Signal 2 L4:

L6:

Signal 1 VCC

Signal 3 GNDL5: Signal 4

TECHNOLOGY COPR.

145Sunday, March 13, 2005

A

www.hocnghetructuyen.vn

B

C

D

E

Alviso Strapping Signals and Configuration

Pin Name

CFG[2:0]

4 4

CFG[3:4]

CFG5

CFG6 CFG7

CFG8

CFG9

CFG10

CFG11

CFG[13:12]

3 3

CFG[14:15]

CFG16

CFG17

CFG18

CFG19

CFG20

SDVO CRTL_DATA

All strap signals are sampled with respect to the leading

NOTE:

edge of the Alviso GMCH PWORK In signal.

Strap Description

FSB Frequency Select

Reversed

DMI x2 Select

DDR I / DDR II

CPU Strap

Reversed

PCI Express Graphics Lane reverse option for layout convenience

Reversed Reversed

XOR/ALL Z test

straps

Reversed FSB Dynamic ODT 0 = Dynamic ODT Disabled

Reversed

GMCH core VCC Select

CPU VTT Select

Reversed SDVO Present

Configuration

000 = Reserved 001 = FSB533 101 = FSB400 011-111 = Reversed

0 = DMI x2

1 = DMI x4 0 = DDR II

1 = DDR I 0= Reserved

1=Dothan

0=Reverse Lanes

1=Normal Operation

00 = Reserved

01 = XOR mode enabled

10 = All Z mode enabled

11 = Normal Operation

(Default)

1 = Dynamic ODT Enabled

(Default)

0 = 1.05V

1 = 1.5V

0 = 1.05V

1 = 1.2V

0 = No SDVO device present

1= SDVO device present

(Default) (Default)

(Default)

(For GML)

(For GM)

(Default)

page 7

(Default)

ICS954226 Spread Spectrum Select

Byte 6b7

1 1 1 1 1 1 1 1

Byte 6b6

byte 6b5 Byte 6b4 Spread Mode Spread Amount%

00 0 00 00

1

0

11 00

1

0

11 11 11 1

1

0

Down Down Down Down Center Center Center Center

PCI Routing

IRQ CB851 MiniPCI

25 0 21

1394 19 3E

E C

REQ/GNTIDSEL

1

ICH6-M IDE Integrated Series Termination Resistors

DD[15:0], DDACK#,

DCS3#,

IORDY,

IDEIRQ

DIOR#, DREQ,DIOW#,

DA[2:0],

DCS1#,

approximately 33 ohm

page 3

0.8

1.25

1.75

2.5 +-0.3 +-0.5 +-0.8 +-1.25

Pin17/18 Mhz

100 100 100 100 100 100 100 100

ICH6-M Integrated Pull-up and Pull-down Resistors

EE_DIN,EE_DOUT,

GNT[4]#/GPO[48],

GNT[6]#/GPO[16], LAD[3:0]#/FB[3:0]#, LDRQ[0], LDRQ[1]/GPI[41],PME#, PWRBTN#,

(Default)

ACZ_BITCLK,

DPRSLPVR,

USB[7:0][P,N]

DD[7],

LAN_CLK

GNT[3:0]

GNT[5]#/GPO[17],

GPIO[25]

LAN_RXD[2:0],

TP[3]

ACZ_RST#, ACZ_SDIN[2:0], ACZ_SYNC,ACZ_SDOUT,

EE_CS,

DDREQ

DPRSTP#

SPKR,

SATALED#

ICH6-M Strapping Options

REF

R275

R279

R282

FUNCTION

No Reboot A16 Swap

Override

Boot BIOS

DEFAULT OPTIONAL OVERRIDE

Dummy

Reserved

I2C/SMB Addresses

ICH6-M EDS 15851 1.5V1

ICH6 internal 20K pull-ups

ICH6 internal 20K pull-downs

ICH6 internal 15K pull-downs

ICH6 internal 11.5K pull-downs

ICH6 internal 100K pull-downs

KBC Hardware Strap

PinNumber PinName Function

2 2

125

A1

page 30

High:Enable the internal pull-up resistors on XIOCS [F:0] pins Low:Disable the internal pull-up resistors on XIOCS [F:0]

128

A4

High: Diasble DMPP(Recommended) Low : Enable DMPP

131

A5

High:Enable EMWB(Recommended for application using shared BIOS Low:Disable EMWB

11

GPIO05

High:Test Mode

Device Address Bus

Clock Generator SO-DIMM0 SO-DIMM1

Thermal Sensor Battery

Antitheft

Light Sensor SMB_KBC_S00111 001x

1101 001x 1010 000x 1010 010x

0111 101x 0001 000x

1010 000x

SMB_ICH_S0 SMB_ICH_S0 SMB_ICH_S0

SMB_KBC_S0 SMB_KBC_S5

SMB_KBC_S5

Low:32KHz clock in normal running(Recommend)

12

GPIO06

High:Test Mode(KSOUT0~15 become DPLL internal data outputs, KSO16 becomes internal power-on reset output

1 1

105

GPIO20

Low:Normal operation(Recommended) High:Normal operation(Recommended)

Low:Enable ISP mode during which the RD#,WR#,MEMSEL#,A[20:0] andD[7:0}will be controlled by ISP COntriller

TECHNOLOGY COPR.

Title

Table of content

Document Number Rev

S09 MAINBOARD

Date: Sheet

Date: Sheet of

TECHNOLOGY COPR.

of

245Tuesday, March 15, 2005

A

5

www.hocnghetructuyen.vn

3D3V_S0

+/-5%

*

3D3V_APWR_S0

BC1

4.7uF

C0805

3D3V_48MPWR_S0

BC11

4.7uF

C0805

10V, Y5V, +80%/-20%

*

BC2

0.1uF

*

16V, Y5V, +80%/-20%

C0402

BC12

0.1uF

16V, Y5V, +80%/-20%

C0402

R10R0603

10V, Y5V, +80%/-20%

D D

3D3V_S0

R20R0603

ITP_EN 0=PCIEX_6 1=CPU_2_ITP SS_SEL 0=LCDCLK 1=PCIEX/free running

3.3V PCI clock output

C C

3D3V_S0

R13

FS_A

R13 10K

10K

+/-5%

R0402

R16

R16 10K

10K

+/-5%

R0402

Dummy

ITP_EN SS_SEL

R21 0

R0402

R23 1K

R0402

R27 0

R0402

R32 1K

R0402

5

1D05V_S0

+/-5%R21 0

+/-5%

+/-5%R23 1K

+/-5%

1D05V_S0

+/-5%R27 0

+/-5%

+/-5%R32 1K

+/-5%

FS_B

FS_C

0

0 0

0 1 1

0

1 1 100M

0 1

1

R18

R18 1K

1K

+/-5%

R0402

Dummy

R24

2.2K

+/-5%

R0402

Dummy

R26

R26 1K

1K

+/-5%

R0402

Dummy

BSEL1

R33

2.2K

+/-5%

R0402

Dummy

FS_A

0

01200M 1 00333M 1 0

R627 2.2K

R0402 +/-5%

FS_C

FS_B

CPU

266M 133M

166M

400M

R12

R12 10K

10K

+/-5%

R0402

Dummy

R15

R15 10K

10K

+/-5%

R0402

B B

CPU_SEL04

MCH_BSEL07

CPU_SEL14

MCH_BSEL17

3D3V_S0

R42

A A

R42 10K

10K

+/-5%

R0402

R45

R45 10K

10K

+/-5%

R0402

Dummy

4

PM_STPPCIJ15

BSEL0

4

3D3V_S0

BC13

C0603

BC14

C0603 50V, NPO, +/-5%

BSEL0

R518 22R0402 +/-5%R518 22R0402 +/-5%

CLK_PCIE_ICH CLK_PCIE_ICHJ DREFSSCLKJ DREFSSCLK DREFCLK DREFCLKJ

FB1 FB L0603 180 OhmFB1 FB L0603 180 Ohm

PCLK_MINI29 PCLK_PCM22 PCLK_KBC30

CLK33_AUDIODJ28

CLK_ICHPCI15

VTT_PWRGDJ39 CLK48_ICH15 DREFCLK7

DREFCLKJ7

SMBC_ICH11,17

B_SMBD_ICH11,17

*

50V, NPO, +/-5%

33pF

*

1 2

33pF

CLK_ICH1415

3

21

BC3

10uF

*

C0805

10V, Y5V, +80%/-20%

3D3V_APWR_S0 3D3V_CLKGEN_S0

3D3V_S0

R626

R626 10K

10K

+/-5%

R0402

Dummy

R6 33 R0402 +/-5%R6 33 R0402 +/-5% R7 33 R0402 +/-5%R7 33 R0402 +/-5% R8 33 R0402 +/-5%R8 33 R0402 +/-5% R9 33 R0402 +/-5%R9 33 R0402 +/-5%

R11 33 R0402 +/-5%R11 33 R0402 +/-5%

H/L : CPU_ITP/SRC7

R14 22R0402 +/-5%R14 22R0402 +/-5%

RN7

1

33

2 3

X1

X1 X-14D318MHz

X-14D318MHz

R22 47R0402 +/-5%R22 47R0402 +/-5%

VTT_PWRGDJ

3D3V_CLKGEN_S0

BC4

0.1uF

*

C0402

16V, Y5V, +80%/-20%

3D3V_48MPWR_S0

SS_SEL

ITP_EN

FS_A

4P2R0402V

4

+/-5%

X2_ICS

X1_ICS

BSEL0 BSEL1

R19

475

R0402

+/-1%

BC5

0.1uF

*

C0402

16V, Y5V, +80%/-20%

37

1 7

21 28 34

42 48

11

56

3 4 5

9

55

8

10 12 14

15 46

47 49

50 53

16 39

52

*

16V, Y5V, +80%/-20%

U1

VDDA VDDPCI

VDDPCI VDDPCIEX

VDDPCIEX VDDPCIEX

VDDCPU VDDREF

VDD_48

PCICLK2/REQ_SEL PCICLK3 PCICLK4 PCICLK5

H/L: 100/96MHz

SELPCIEX_LCDCLK#/PCICLK_F1 PCI/SRC_STP# ITP_EN/PCICLK_F0

VTT_PWRGD#/PD USB_48/FS_A DOT96T

DOT96C SCLK

SDATA XOUT

XIN REF1/FS_C/TEST_SEL

FS_B/TEST_MODE IREF

REF0

ICS954226

BC6

0.1uF

C0402

CPUT2_ITP/PCIEXT6

CPUC2_ITP/PCIEXC6

LCDCLK_SS/PCIEX0T LCDCLK_SS/PCIEX0C

**

PEREQ2#/PCIEXC5

*

PEREQ1#/PCIEXT5

*

16V, Y5V, +80%/-20%

CPU_STP#

CPUT0

CPUC0 CPUT1

CPUC1

PCIEXT1 PCIEXC1

PCIEXT2 PCIEXC2

PCIEXT3 PCIEXC3

SATACLKT SATACLKC

PCIEXC4 PCIEXT4

*internal Pull-Up resistors **internal Pull-Down resistor

AC_CLK 26

To external AC'97 CLK

R28 49.9 R0402 +/-1%R28 49.9 R0402 +/-1% R30 49.9 R0402 +/-1%R30 49.9 R0402 +/-1% R31 49.9 R0402 +/-1%R31 49.9 R0402 +/-1% R34 49.9 R0402 +/-1%R34 49.9 R0402 +/-1% R36 49.9 R0402 +/-1%R36 49.9 R0402 +/-1% R38 49.9 R0402 +/-1%R38 49.9 R0402 +/-1% R40 49.9 R0402 +/-1%R40 49.9 R0402 +/-1%

3

CLK_CPU_BCLK CLK_CPU_BCLKJ CLK_MCH_BCLK CLK_MCH_BCLKJ CLK_MCH_3GPLL CLK_MCH_3GPLLJ

R29 49.9 R0402 +/-1%R29 49.9 R0402 +/-1%

R35 49.9 R0402 +/-1%R35 49.9 R0402 +/-1% R37 49.9 R0402 +/-1%R37 49.9 R0402 +/-1% R39 49.9 R0402 +/-1%R39 49.9 R0402 +/-1% R41 49.9 R0402 +/-1%R41 49.9 R0402 +/-1%

BC7

0.1uF

C0402

GND GND

GNDA

2

*

16V, Y5V, +80%/-20%

54 44

43 41

40

CLK_XDP_CPU

36

CLK_XDP_CPUJ

35 17

18 19

20 22

23 24

25 26

27 30

31 32

33

13 51

45 29

2 6

38

1

BC10

BC8

0.1uF

C0402

RN1

RN1 33

33 RN2

RN2 33

33

RN3

RN3 33

33

RN4

RN4 33

33

RN6

RN6 33

33

*

16V, Y5V, +80%/-20%

1 2 3

1 1

2 3 1

TP1TP1 TP2TP2

BC9

0.1uF

C0402

4

4P2R0402V

+/-5%

4P2R0402V

+/-5%

4P2R0402V

+/-5%

4P2R0402V

+/-5%

4P2R0402V

+/-5%

BC10

0.1uF

*

C0402

16V, Y5V, +80%/-20%

PM_STPCPUJ 15,39

CLK_CPU_BCLK 4 CLK_CPU_BCLKJ 4

CLK_MCH_BCLK 6 CLK_MCH_BCLKJ 6

DREFSSCLK 7 DREFSSCLKJ 7

CLK_MCH_3GPLL 7 CLK_MCH_3GPLLJ 7

CLK_PCIE_ICHJ 15 CLK_PCIE_ICH 15

EMI capacitor

CLK_ICH14 PCLK_PCM PCLK_MINI PCLK_KBC CLK_ICHPCI CLK48_ICH CLK33_AUDIODJ AC_CLK

Title

Clock Generator

Document Number Rev

S09 MAINBOARD

Date: Sheet

C1 10pF C0402 50V, NPO, +/-5% Dummy

*

C2 10pF C0402 50V, NPO, +/-5% Dummy

*

C3 10pF C0402 50V, NPO, +/-5% Dummy

*

C4 10pF C0402 50V, NPO, +/-5% Dummy

*

C5 10pF C0402 50V, NPO, +/-5% Dummy

*

C6 10pF C0402 50V, NPO, +/-5% Dummy

*

C7 10pF C0402 50V, NPO, +/-5% Dummy

*

C8 10pF C0402 50V, NPO, +/-5% Dummy

*

TECHNOLOGY COPR.

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345Tuesday, March 15, 2005

of

345Tuesday, March 15, 2005

of

345Tuesday, March 15, 2005

1

A

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www.hocnghetructuyen.vn

U2A

B_H_AJ[31..3]6

D D

B_H_ADSTBJ06

B_H_REQJ[4..0]6

C C

B B

B_H_ADSTBJ16

H_A20MJ14

H_FERRJ14

H_IGNNEJ14

H_STPCLKJ14

H_INTR14 H_SMIJ14

CPU_PROCHOTJ XDP_TDI XDP_TMS XDP_TDO H_CPURSTJ XDP_DBRESETJ

XDP_TCK XDP_TRSTJ

H_NMI14

B_H_AJ3

P4

B_H_AJ4

U4

B_H_AJ5

V3

B_H_AJ6

R3

B_H_AJ7

V2

B_H_AJ8

W1

B_H_AJ9

T4

B_H_AJ10

W2

B_H_AJ11

Y4

B_H_AJ12

Y1

B_H_AJ13

U1

B_H_AJ14

AA3

B_H_AJ15

Y3

B_H_AJ16

AA2

B_H_AJ17 B_H_AJ18 B_H_AJ19 B_H_AJ20 B_H_AJ21 B_H_AJ22 B_H_AJ23 B_H_AJ24 B_H_AJ25 B_H_AJ26 B_H_AJ27 B_H_AJ28 B_H_AJ29 B_H_AJ30 B_H_AJ31

AF4 AC4 AC7 AC3 AD3 AE4 AD2 AB4 AC6 AD5 AE2 AD6 AF3 AE1 AF1 AE5

U3 R2

P3 T2 P1 T1

C2 D3 A3

C6 D1 D4 B4

B_H_REQJ0 B_H_REQJ1 B_H_REQJ2 B_H_REQJ3 B_H_REQJ4

R519 56 R0402 +/-5%R519 56 R0402 +/-5% R47 150 +/-5%R0402R47 150 +/-5%R0402 R48 39.2R0402 +/-1%R48 39.2 R0402 +/-1% R52 54.9R0402 +/-1%R52 54.9 R0402 +/-1% R55 54.9R0402 +/-1%R55 54.9 R0402 +/-1% R57 150 +/-5%R0402R57 150 +/-5%R0402

R59 27.4R0402 +/-1%R59 27.4 R0402 +/-1% R60 680 R0402 +/-5%R60 680 R0402 +/-5%

A3# A4# A5# A6# A7# A8# A9# A10# A11# A12# A13# A14# A15# A16# ADSTB#0

REQ0# REQ1# REQ2# REQ3# REQ4#

A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31# ADSTB#1

A20M# FERR# IGNNE#

STPCLK# LINT0 LINT1 SMI#

Dothan_Socket479

1D05V_S0

All place within 2" to CPU

4

N2

ADS#

L1

BNR#

J3

BPRI#

L4

DEFER#

H2

DRDY#

M2

DBSY#

N4

BR0#

A4

IERR#

B5

ADDR GROUP 0

ADDR GROUP 1

INIT#

LOCK#

RESET#

RS0# RS1# RS2#

TRDY#

HIT#

HITM#

BPM#0 BPM#1 BPM#2 BPM#3 PRDY# PREQ#

TCK

TDI TDO TMS

TRST#

DBR#

PROCHOT#

THERMDA THERMDC

THERMTRIP#

ITP_CLK1 ITP_CLK0

BCLK1 BCLK0

HCLK THERM XTP/ITP SIGNALS CONTROL

J2 B11

H1 K1 L2 M3

K3 K4

C8 B8 A9 C9 A10 B10 A13 C12 A12 C11 B13 A7

B17 B18 A18

C17 A15

A16 B14 B15

TP3TP3

1

B_H_ADSJ 6 B_H_BNRJ 6

B_H_DRDYJ 6 B_H_DBSYJ 6

B_H_BREQJ0 6

B_H_LOCKJ 6

H_RSJ0 H_RSJ1 H_RSJ2

XDP_TCK

XDP_TDI

XDP_TDO XDP_TMS XDP_TRSTJ XDP_DBRESETJ

CPU_PROCHOTJ

THERMDN 18 PM_THRMTRIPJ 7,14

TP17TP17

1

TP18TP18

1

H_BPRIJ 6 H_DEFERJ 6

H_INITJ 14

H_CPURSTJ 6

H_TRDYJ 6 B_H_HITJ 6

B_H_HITMJ 6

THERMDP1 18

CLK_CPU_BCLKJ 3 CLK_CPU_BCLK 3

H_IERRJ

H_RSJ[2..0] 6

3

1D05V_S0

R46

R46 56

56

+/-5%

R0402

Place testpoint on H_IERR# with a GND

0.1" away

Put these Caps near the thermal diode.

THERMDP1

BC15

470pF

*

50V, X7R, +/-10%

C0402

THERMDN

PM_THRMTRIP# should connect to ICH6 and Alviso without T-ing

( No stub)

To V-CORE SWITCH

1D05V_S0

R58

R58 1K

1K

+/-1%

R0402

R61

R61 2K

2K

+/-1%

R0603

2

B_H_DJ[63..0] 6

U2B

B_H_DJ0

A19 A25 A22 B21 A24 B26 A21 B20

C20

B24

D24

E24

C26

B23

E23 C25 C23 C22 D25

H23 G25

L23 M26 H24

F25 G24

M23

L26 N24 M25 H26 N25

K25

K24

L24

1 C16

C14

J23 J25

J26

E1

D0# D1# D2# D3# D4# D5# D6# D7# D8# D9# D10# D11# D12# D13# D14# D15# DSTBN0# DSTBP0# DINV0#

D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# DSTBN1# DSTBP1# DINV1#

PSI# BSEL0

BSEL1

B_H_DJ1 B_H_DJ2 B_H_DJ3 B_H_DJ4 B_H_DJ5 B_H_DJ6 B_H_DJ7 B_H_DJ8 B_H_DJ9 B_H_DJ10 B_H_DJ11 B_H_DJ12 B_H_DJ13 B_H_DJ14

B_H_DSTBNJ06 B_H_DSTBPJ06

B_H_DINVJ06 B_H_DINVJ2 6

B_H_DSTBNJ16 B_H_DSTBPJ16

CPU_SEL03 CPU_SEL13

B_H_DJ15

B_H_DJ16 B_H_DJ17 B_H_DJ18 B_H_DJ19 B_H_DJ20 B_H_DJ21 B_H_DJ22 B_H_DJ23 B_H_DJ24 B_H_DJ25 B_H_DJ26 B_H_DJ27 B_H_DJ28 B_H_DJ29 B_H_DJ30 B_H_DJ31

TP20TP20

MISC

C3

RSVD2

AF7

RSVD3

AC1

RSVD4

E26

GTLREF0 TEST1

Layout Note:

0.5" max length.

AD26

RSVD5 GTLREF0

Dothan_Socket479

D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44#

DATA GRP 2

DATA GRP 0DATA GRP 1

D45# D46# D47#

DSTBN2#

DSTBP2#

DINV2#

D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60#

DATA GRP 3

D61# D62# D63#

DSTBN3#

DSTBP3#

DINV3# COMP0

COMP1 COMP2 COMP3

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

TEST1 TEST2

Y26 AA24 T25 U23 V23 R24 R26 R23 AA23 U26 V24 U25 V26 Y23 AA26 Y25 W25 W24 T24

AB25 AC23 AB24 AC20 AC22 AC25 AD23 AE22 AF23 AD24 AF20 AE21 AD21 AF25 AF22 AF26 AE24 AE25 AD20

P25 P26 AB2 AB1

G1 B7 C19 E4 A6

C5 F23

COMP0 COMP1 COMP2 COMP3

TEST2

R62

1K

+/-5%

R0402

Dummy

B_H_DJ32 B_H_DJ33 B_H_DJ34 B_H_DJ35 B_H_DJ36 B_H_DJ37 B_H_DJ38 B_H_DJ39 B_H_DJ40 B_H_DJ41 B_H_DJ42 B_H_DJ43 B_H_DJ44 B_H_DJ45 B_H_DJ46 B_H_DJ47

B_H_DJ48 B_H_DJ49 B_H_DJ50 B_H_DJ51 B_H_DJ52 B_H_DJ53 B_H_DJ54 B_H_DJ55 B_H_DJ56 B_H_DJ57 B_H_DJ58 B_H_DJ59 B_H_DJ60 B_H_DJ61 B_H_DJ62 B_H_DJ63

B_H_DSTBNJ2 6 B_H_DSTBPJ2 6

B_H_DSTBNJ3 6 B_H_DSTBPJ3 6

B_H_DINVJ3 6B_H_DINVJ16

R50 27.4R0402 +/-1%R50 27.4 R0402 +/-1% R51 54.9R0402 +/-1%R51 54.9 R0402 +/-1% R53 27.4R0402 +/-1%R53 27.4 R0402 +/-1% R54 54.9R0402 +/-1%R54 54.9 R0402 +/-1%

H_DPRSLPJ 14 H_DPSLPJ 14 H_DPWRJ 6

H_CPUSLPJ 6,14

R63

R63 1K

1K

+/-5%

R0402

Dummy

Layout Note: Comp0, 2 connect with Zo=27.4 ohm, make trace length shorter than 0.5" . Comp1, 3 connect with Zo=55 ohm, make trace length shorter than 0.5" .

1

1D05V_S0

R56

R56 200

200

+/-1%

R0402

H_PWRGD 14

A A

TECHNOLOGY COPR.

of

445Monday, March 14, 2005

of

445Monday, March 14, 2005

of

445Monday, March 14, 2005

1

A

5

Title

CPU(1 of 2)

Document Number Rev

Date: Sheet

4

3

2

Date: Sheet

CPU(1 of 2)

S09 MAINBOARD

5

www.hocnghetructuyen.vn

VCC_CORE_S0

U2C

AA11

VCC0

AA13

VCC1

AA15

VCC2

AA17

VCC3

AA19

VCC4

D D

C C

B B

A A

AA21

AA5 AA7

AA9 AB10 AB12 AB14 AB16 AB18 AB20 AB22

AB6

AB8 AC11 AC13 AC15 AC17 AC19

AC9 AD10 AD12 AD14 AD16 AD18

AD8 AE11 AE13 AE15 AE17 AE19

AE9

AF10 AF12 AF14 AF16 AF18

AF8

D18

D20

D22

E17

E19

E21

F18 F20 F22

G21

D6 D8

E5 E7 E9

F6 F8

VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58

Dothan_Socket479

VCC_CORE_S0

*

VCC_CORE_S0

*

Dummy

VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71

VCCA0 VCCA1 VCCA2 VCCA3

VCCP0 VCCP1 VCCP2 VCCP3 VCCP4 VCCP5 VCCP6 VCCP7 VCCP8

VCCP9 VCCP10 VCCP11 VCCP12 VCCP13 VCCP14 VCCP15 VCCP16 VCCP17 VCCP18 VCCP19 VCCP20 VCCP21 VCCP22 VCCP23 VCCP24

VCCQ0

VCCQ1

VID0 VID1 VID2 VID3 VID4 VID5

VCCSENSE VSSSENSE

Layout Note:

10V, Y5V, +80%/-20%

*

BC34

BC33

10uF C0805

10V, X5R, +/-10%

*

BC52

BC51

0.1uF C0402

Dummy

5

VCC_CORE_S0

G5 H22 H6 J21 J5 K22 U5 V22 V6 W21 W5 Y22 Y6

F26 B1 N1 AC26

R5100R0603 +/-5%R5100R0603 +/-5%

D10 D12 D14 D16 E11 E13 E15 F10 F12 F14 F16 K6 L21 L5 M22 M6 N21 N5 P22 P6 R21 R5 T22 T6 U21

P23 W4

E2 F2 F3 G3 G4 H4

TP_VCCSENSE

TP_VSSSENSE

VCCSENSE and VSSSENSE lines should be of equal length.

*

BC35

BC36

10uF C0805

*

BC54

BC53

0.1uF C0402

Dummy

*

10uF C0805

*

0.1uF C0402

Dummy

AE7 AF6

1D05V_S0

1D5V_S0

+/-5%

1D05V_S0

10V, Y5V, +80%/-20%

H_VID0 39 H_VID1 39 H_VID2 39 H_VID3 39 H_VID4 39 H_VID5 39

R64

54.9

+/-1%

R0402

Dummy

*

BC37

BC38

10uF C0805

*

BC56

BC55

0.1uF C0402

Dummy

*

R504

R504 0

0

R0603

3D3V_S0

Dummy

*

10uF C0805

*

0.1uF C0402

Dummy

BC16

R65

54.9

+/-1%

R0402

Dummy

BC39

BC57

4

*

BC17

BC18

0.1uF C0402

BC26

BC27

10nF

10uF

*

BC552

C0603

10uF

*

10V, Y5V, +80%/-20%

C0402

C0805

1uF

*

Layout Note: Provide a test point (with no stub) to connect a differential probe between VCCSENSE and VSSSENSE at the location where the two 54.9ohm resistors terminate the 55 ohm transmission line.

*

10uF C0805

*

0.1uF C0402

Dummy

BC40

BC58

10uF C0805

*

0.1uF C0402

Dummy

4

BC41

BC59

*

BC19

0.1uF C0402

I max = 120 mA

U27

1

SHDN#

2

GND

3

IN

G913C

Dummy

VCC_CORE_S0

*

BC28

*

BC42

10uF C0805

*

BC60

0.1uF C0402

Dummy

*

BC20

BC21

0.1uF C0402

1D5V_VCCA_S0

SET

OUT

*

BC30

BC29

10uF C0805

VCC_CORE_S0

*

BC44

BC43

10uF C0805

*

BC61

BC62

10uF C0805

*

0.1uF C0402

1D5V_VCCA_S0

5 4

*

10uF C0805

*

BC624

*

10uF C0805

*

10uF C0805

*

BC22

0.1uF C0402

*

50V, NPO, +/-5%

BC553

1uF

*

C0603

Dummy

*

BC31

10uF C0805

*

BC625

10uF C0805

*

BC45

10uF C0805

*

BC63

10uF C0805

BC23

*

BC32

BC46

BC64

*

0.1uF C0402

BC551

22pF

C0402

Dummy

10V, Y5V, +80%/-20%

C0805

*

BC626

10uF C0805

*

10uF C0805

*

10uF C0805

10uF

BC24

BC47

BC65

3

*

BC25

0.1uF C0402

Place these and dummy 12K7R3F for 1D8V_VCCA_S0

12.7K 1.56V 11K 1.52V

R599

R599 11K

11K

+/-1%

R0402

Dummy

R505

49.9K

+/-1%

R0402

Dummy

*

BC627

10uF C0805

*

BC48

10uF C0805

*

BC66

10uF C0805

3

0.1uF C0402

10uF C0805

*

10uF C0805

*

10uF C0805

*

BC628

2 1

*

TC1

220uF

2.5V, +/-20%

ctbh20

10uF C0805

*

BC49

10uF C0805

BC67

10uF C0805

VSS97 VSS98

VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191

2

D13 D15 D17 D19 D21 D23 D26 E3 E6 E8 E10 E12 E14 E16 E18 E20 E22 E25 F1 F4 F5 F7 F9 F11 F13 F15 F17 F19 F21 F24 G2 G6 G22 G23 G26 H3 H5 H21 H25 J1 J4 J6 J22 J24 K2 K5 K21 K23 K26 L3 L6 L22 L25 M1 M4 M5 M21 M24 N3 N6 N22 N23 N26 P2 P5 P21 P24 R1 R4 R6 R22 R25 T3 T5 T21 T23 T26 U2 U6 U22 U24 V1 V4 V5 V21 V25 W3 W6 W22 W23 W26 Y2 Y5 Y21 Y24

Title

CPU(2 of 2)

Document Number Rev

Date: Sheet

2

Date: Sheet

CPU(2 of 2)

S09 MAINBOARD

U2D

A2

VSS0

A5

VSS1

A8

VSS2

A11

VSS3

A14

VSS4

A17

VSS5

A20

VSS6

A23

VSS7

A26

VSS8

AA1

VSS9

AA4

VSS10

AA6

VSS11

AA8

VSS12

AA10

VSS13

AA12

VSS14

AA14

VSS15

AA16

VSS16

AA18

VSS17

AA20

VSS18

AA22

VSS19

AA25

VSS20

AB3

VSS21

AB5

VSS22

AB7

VSS23

AB9

VSS24

AB11

VSS25

AB13

VSS26

AB15

VSS27

AB17

VSS28

AB19

VSS29

AB21

VSS30

AB23

VSS31

AB26

VSS32

AC2

VSS33

AC5

VSS34

AC8

VSS35

AC10

VSS36

AC12

VSS37

AC14

VSS38

AC16

VSS39

AC18

VSS40

AC21

VSS41

AC24

VSS42

AD1

VSS43

AD4

VSS44

AD7

VSS45

AD9

VSS46

AD11

VSS47

AD13

VSS48

AD15

VSS49

AD17

VSS50

AD19

VSS51

AD22

VSS52

AD25

VSS53

AE3

VSS54

AE6

VSS55

AE8

VSS56

AE10

VSS57

AE12

VSS58

AE14

VSS59

AE16

VSS60

AE18

VSS61

AE20

VSS62

AE23

VSS63

AE26

VSS64

AF2

VSS65

AF5

VSS66

AF9

VSS67

AF11

VSS68

AF13

VSS69

AF15

VSS70

AF17

VSS71

AF19

VSS72

AF21

VSS73

AF24

VSS74

B3

VSS75

B6

VSS76

B9

VSS77

B12

VSS78

B16

VSS79

B19

VSS80

B22

VSS81

B25

VSS82

C1

VSS83

C4

VSS84

C7

VSS85

BC50

10uF C0805

C10 C13 C15 C18 C21 C24

D11

D2 D5 D7 D9

VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96

Dothan_Socket479

1

TECHNOLOGY COPR.

of

545Thursday, March 17, 2005

of

545Thursday, March 17, 2005

of

545Thursday, March 17, 2005

1

A

5

www.hocnghetructuyen.vn

H_XRCOMP

R66

24.9

+/-1%

R0402

D D

1D05V_S0

Place them near to the chip

R67

54.9

+/-1%

R0402

H_XSCOMP

B_H_DJ[63..0]4

Place them near to the chip

1D05V_S0

R68

R68 221

221

+/-1%

R0603

C C

R70

R70 100

100

+/-1%

R0402

H_XSWING

BC68

0.1uF

*

10V, X7R, +/-10%

C0402

Place them near to the chip

H_YRCOMP

R72

24.9

+/-1%

R0402

Place them near to the chip

B B

A A

1D05V_S0

R73

54.9

+/-1%

R0402

H_YSCOMP

Place them near to the chip

R75

R75 221

221

+/-1%

R0603

H_YSWING

BC70

0.1uF

R76

R76 100

100

+/-1%

R0402

0.1uF

*

10V, X7R, +/-10%

C0402

4

U3A

B_H_DJ0 B_H_DJ1 B_H_DJ2 B_H_DJ3 B_H_DJ4 B_H_DJ5 B_H_DJ6 B_H_DJ7 B_H_DJ8 B_H_DJ9 B_H_DJ10 B_H_DJ11 B_H_DJ12 B_H_DJ13 B_H_DJ14 B_H_DJ15 B_H_DJ16 B_H_DJ17 B_H_DJ18 B_H_DJ19 B_H_DJ20 B_H_DJ21 B_H_DJ22 B_H_DJ23 B_H_DJ24 B_H_DJ25 B_H_DJ26 B_H_DJ27 B_H_DJ28 B_H_DJ29 B_H_DJ30 B_H_DJ31 B_H_DJ32 B_H_DJ33 B_H_DJ34 B_H_DJ35 B_H_DJ36 B_H_DJ37 B_H_DJ38 B_H_DJ39 B_H_DJ40 B_H_DJ41 B_H_DJ42 B_H_DJ43 B_H_DJ44 B_H_DJ45 B_H_DJ46 B_H_DJ47 B_H_DJ48 B_H_DJ49 B_H_DJ50 B_H_DJ51 B_H_DJ52 B_H_DJ53 B_H_DJ54 B_H_DJ55 B_H_DJ56 B_H_DJ57 B_H_DJ58 B_H_DJ59 B_H_DJ60 B_H_DJ61 B_H_DJ62 B_H_DJ63

H_XRCOMP H_XSCOMP H_XSWING H_YRCOMP H_YSCOMP H_YSWING

E4 E1 F4 H7 E2 F1 E3 D3 K7 F2

J7

J8 H6 F3 K8 H5 H1 H2 K5 K6

J4

G3

H3

J1

L5 K4

J5 P7

L7

J3 P5

L3 U7 V6 R6 R5 P3 T8 R7 R8 U8 R4 T4 T5 R1 T3 V8 U6

W6

U3 V5

W8 W7

U2 U1 Y5 Y2 V4 Y7

W1 W3

Y3 Y6

W2

C1 C2 D1 T1

L1 P1

HD0# HD1# HD2# HD3# HD4# HD5# HD6# HD7# HD8# HD9# HD10# HD11# HD12# HD13# HD14# HD15# HD16# HD17# HD18# HD19# HD20# HD21# HD22# HD23# HD24# HD25# HD26# HD27# HD28# HD29# HD30# HD31# HD32# HD33# HD34# HD35# HD36# HD37# HD38# HD39# HD40# HD41# HD42# HD43# HD44# HD45# HD46# HD47# HD48# HD49# HD50# HD51# HD52# HD53# HD54# HD55# HD56# HD57# HD58# HD59# HD60# HD61# HD62# HD63#

HXRCOMP HXSCOMP HXSWING HYRCOMP HYSCOMP HYSWING

ALVISO-GM

71.0GMCH.08U

HCPURST#

HOST

HCPUSLP#

3

HA3# HA4# HA5# HA6# HA7# HA8#

HA9# HA10# HA11# HA12# HA13# HA14# HA15# HA16# HA17# HA18# HA19# HA20# HA21# HA22# HA23# HA24# HA25# HA26# HA27# HA28# HA29# HA30# HA31#

HADS# HADSTB#0 HADSTB#1

HVREF

HBNR#

HBPRI#

HBREQ0#

HCLKINN HCLKINP

HDBSY#

HDEFER#

HDINV#0 HDINV#1 HDINV#2 HDINV#3

HDPWR#

HDRDY# HDSTBN#0 HDSTBN#1 HDSTBN#2 HDSTBN#3 HDSTBP#0 HDSTBP#1 HDSTBP#2 HDSTBP#3

HEDRDY#

HHIT#

HHITM#

HLOCK#

HPCREQ#

HREQ#0 HREQ#1 HREQ#2 HREQ#3 HREQ#4

HRS0# HRS1# HRS2#

HTRDY#

G9 C9 E9 B7 A10 F9 D8 B10 E10 G10 D9 E11 F10 G11 G13 C10 C11 D11 C12 B13 A12 F12 G12 E12 C13 B11 D13 A13 F13

F8 B9 E13 J11 A5 D5 E7 H10

AB1 AB2

C6 E6 H8 K3 T7 U5 G6 F7 G4 K1 R3 V3 G5 K2 R2 W4 F6 D4 D6 B3 A11 A7 D7 B8 C7 A8 A4 C5 B4 G8 B5

B_H_AJ3 B_H_AJ4 B_H_AJ5 B_H_AJ6 B_H_AJ7 B_H_AJ8 B_H_AJ9 B_H_AJ10 B_H_AJ11 B_H_AJ12 B_H_AJ13 B_H_AJ14 B_H_AJ15 B_H_AJ16 B_H_AJ17 B_H_AJ18 B_H_AJ19 B_H_AJ20 B_H_AJ21 B_H_AJ22 B_H_AJ23 B_H_AJ24 B_H_AJ25 B_H_AJ26 B_H_AJ27 B_H_AJ28 B_H_AJ29 B_H_AJ30 B_H_AJ31

H_VREF

B_H_DINVJ0 B_H_DINVJ1 B_H_DINVJ2 B_H_DINVJ3

B_H_DSTBNJ0 B_H_DSTBNJ1 B_H_DSTBNJ2 B_H_DSTBNJ3 B_H_DSTBPJ0 B_H_DSTBPJ1 B_H_DSTBPJ2 B_H_DSTBPJ3 TP_H_EDRDYJ

TP_H_PCREQJ B_H_REQJ0 B_H_REQJ1 B_H_REQJ2 B_H_REQJ3 B_H_REQJ4 H_RSJ0 H_RSJ1 H_RSJ2 H_CPUSLPJ_0

B_H_ADSJ 4 B_H_ADSTBJ0 4 B_H_ADSTBJ1 4

B_H_BNRJ 4 H_BPRIJ 4 B_H_BREQJ0 4 H_CPURSTJ 4

CLK_MCH_BCLKJ 3 CLK_MCH_BCLK 3

B_H_DBSYJ 4 H_DEFERJ 4

H_DPWRJ 4 B_H_DRDYJ 4

1

B_H_HITJ 4 B_H_HITMJ 4 B_H_LOCKJ 4

1

TP26TP26

H_TRDYJ 4

TP25TP25

2

B_H_AJ[31..3] 4

1D05V_S0

BC69

0.1uF

*

10V, X7R, +/-10%

C0402

Place them near to the chip

B_H_DINVJ0 4 B_H_DINVJ1 4 B_H_DINVJ2 4 B_H_DINVJ3 4

B_H_DSTBNJ0 4 B_H_DSTBNJ1 4 B_H_DSTBNJ2 4 B_H_DSTBNJ3 4 B_H_DSTBPJ0 4 B_H_DSTBPJ1 4 B_H_DSTBPJ2 4 B_H_DSTBPJ3 4

B_H_REQJ[4..0] 4

H_RSJ[2..0] 4

R74 0 R0402 +/-5%R74 0 R0402 +/-5%

DUMMY FOR DOTHAN A STEPPING

R69

R69 100

100

+/-1%

R0402

R71

R71 200

200

+/-1%

R0402

H_CPUSLPJ 4,14

1

Place them near to the chip

5

TECHNOLOGY COPR.

Title

GMCH(1 of 5)

Document Number Rev

Date: Sheet

4

3

2

Date: Sheet

GMCH(1 of 5)

S09 MAINBOARD

TECHNOLOGY COPR.

of

645Monday, March 14, 2005

of

645Monday, March 14, 2005

of

645Monday, March 14, 2005

1

A

5

www.hocnghetructuyen.vn

U3B

DMI_TXN0

DMI_TXN015 DMI_TXN115 DMI_TXN215 DMI_TXN315

DMI_TXP015 DMI_TXP115

R96

40.2

+/-1%

R0402

Dummy

*

BC96 2.2uF

C0805

R98 10K

R0402 +/-5%

R101 10K

R0402 +/-5%

R104

80.6

+/-1%

R0402

M_RCOMPN M_RCOMPP

R110

80.6

+/-1%

R0402

DMI_TXP215 DMI_TXP315

DMI_RXN015 DMI_RXN115 DMI_RXN215 DMI_RXN315

DMI_RXP015 DMI_RXP115 DMI_RXP215 DMI_RXP315

CLK_DDR011 CLK_DDR111

CLK_DDR311 CLK_DDR411

CLK_DDR0J11 CLK_DDR1J11

CLK_DDR3J11 CLK_DDR4J11

M_CKE0_RJ11 M_CKE1_RJ11 M_CKE2_RJ11 M_CKE3_RJ11

M_CS0_RJ11 M_CS1_RJ11 M_CS2_RJ11 M_CS3_RJ11

M_OCDCOMP0 M_OCDCOMP1

*

BC97 0.1uF

BC98 2.2uF

C0402

PM_EXTTSJ0

PM_EXTTSJ1

C0805

M_ODT011 M_ODT111 M_ODT211 M_ODT311

M_RCOMPN M_RCOMPP

SMXSLEW SMYSLEW

*

BC99 0.1uF

C0402

5

D D

C C

R95

40.2

+/-1%

R0402

Dummy

DDR_VREF

B B

2D5V_S0

VDIMM

A A

DMI_TXN1 DMI_TXN2 DMI_TXN3

DMI_TXP0 DMI_TXP1 DMI_TXP2

DMI_TXP3

DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3

DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3

AA31

AB35 AC31 AD35

AA35

AB31 AC35

AA33

AB37 AC33 AD37

AA37

AB33 AC37

AM33

AE11

AJ34 AC10 AN33

AE10

AJ33 AD10

AP21 AM21 AH21

AK21 AN16

AM14 AH15 AG16

AF22

AF16

AP14

AL15 AM11 AN10

AK10

AK11

AF37

AE27

AE28

AF10

Y31

Y33

AL1

AF6

AK1

AF5

AD1

AF9

DMIRXN0 DMIRXN1 DMIRXN2 DMIRXN3

DMIRXP0 DMIRXP1 DMIRXP2 DMIRXP3

DMITXN0 DMITXN1 DMITXN2 DMITXN3

DMITXP0 DMITXP1 DMITXP2 DMITXP3

SM_CK0 SM_CK1 SM_CK2 SM_CK3 SM_CK4 SM_CK5

SM_CK0# SM_CK1# SM_CK2# SM_CK3# SM_CK4# SM_CK5#

SM_CKE0 SM_CKE1 SM_CKE2 SM_CKE3

SM_CS0# SM_CS1# SM_CS2# SM_CS3#

SM_OCDCOMP0 SM_OCDCOMP1

SM_ODT0 SM_ODT1 SM_ODT2 SM_ODT3

SMRCOMPN SMRCOMPP SMVREF0 SMVREF1 SMXSLEWIN SMXSLEWOUT SMYSLEWIN SMYSLEWOUT

ALVISO-GM

71.0GMCH.08U

DMI

CFG/RSVD

BM_BUSY#

EXT_TS0# EXT_TS1#

THRMTRIP#

PM

DDR MUXING

DREF_CLKN DREF_CLKP

DREF_SSCLKN

CLK

DREF_SSCLKP

NC

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8

CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19 CFG20

RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 RSVD26 RSVD27

PWROK

RSTIN#

NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8

NC9 NC10 NC11

G16 H13 G14 F16 F15 G15 E16 D17 J16 D15 E15 D14 E14 H12 C14 H15 J15 H14 G22 G23 D23 G25 G24 J17 A31 A30 D26 D25

J23 J21 H22 F5 AD30 AE29

A24 A23 C37 D37

AP37 AN37 AP36 AP2 AP1 AN1 B1 A2 B37 A36 A37

4

R81 10K R0402+/-5%R81 10K R0402+/-5%

TP_CFG4 CFG5 CFG6 CFG7 CFG8

TP_CFG10

TP_CFG14 CFG16 CFG18

PM_EXTTSJ0 PM_EXTTSJ1

R0402 +/-5%

MCH_BSEL1 3 MCH_BSEL0 3

TP29TP29

1

TP30TP30

1

TP31TP31

1

TP32TP32

1

PM_BMBUSYJ 15

R94 100

1D05V_S0

CFG18 CFG5 CFG6 CFG7 CFG8 CFG16

GMCH_TV_COM33

GMCH_TV_LUMA33 GMCH_TV_CRMA33

Layout Note:place this 3 resistors beside GMCH in 0.5 iches

PM_THRMTRIPJ 4,14

VROK 15,16 PLT_RST1J 15,17,30

DREFCLKJ 3 DREFCLK 3 DREFSSCLKJ 3 DREFSSCLK 3

R632 2.2K R0402+/-5% @GMR632 2.2K R0402+/-5% @GM R102 2.2K R0402+/-5% DummyR102 2.2K R0402+/-5% Dummy R103 2.2K R0402+/-5%R103 2.2K R0402+/-5% R105 2.2K R0402+/-5% DummyR105 2.2K R0402+/-5% Dummy R108 2.2K R0402+/-5% DummyR108 2.2K R0402+/-5% Dummy R109 2.2K R0402+/-5% DummyR109 2.2K R0402+/-5% Dummy

Layout Note:place this 3 resistors beside GMCH in 0.5 iches

R113

R113 150

150

+/-5%

R0402

3

Alviso will provide SDVO_CTRLCLK and CTRLDATA pulldowns on-die

R84

R84 150

150

+/-5%

R0402

GMCH_DDCCLK12

B_GMCH_DDCDATA12

GMCH_BLUE12

GMCH_GREEN12

GMCH_RED12

NO STUFF

2D5V_S0

R88 39R0402 +/-5%R88 39R0402 +/-5% R89 39R0402 +/-5%R89 39R0402 +/-5% R90 255 R0402 +/-1%R90 255 R0402 +/-1%

GMCH_BL_ON30

GMCH_LCDVDD_ON13

TP33TP33 TP34TP34 TP35TP35

GMCH_TXACLK-13 GMCH_TXACLK+13

GMCH_TXAOUT0-13 GMCH_TXAOUT1-13 GMCH_TXAOUT2-13

GMCH_TXAOUT0+13 GMCH_TXAOUT1+13 GMCH_TXAOUT2+13

GMCH_VSYNC12

GMCH_HSYNC12

For NB_CORE=1.5V Strap

For DDR2 Strap

GMCH_BLUE

GMCH_GREEN

GMCH_RED

R114

R114 150

150

+/-5%

R0402

3

R115

R115 150

150

+/-5%

R0402

2

U3G

PEG_COMP

H24

SDVOCTRL_DATA

H25

SDVOCTRL_CLK

CLK_MCH_3GPLLJ3 CLK_MCH_3GPLL3

GMCH_TV_RST

R86

R85

150

+/-5%

R0402

LBKLT_CRTL13

1 1 1

LCTLA_CLK

LCTLB_DATA LDDC_NB_CLK B_LDDC_NB_DATA

LIBG

GMCH_TXACLKGMCH_TXACLK+

GMCH_TXAOUT0GMCH_TXAOUT1GMCH_TXAOUT2-

GMCH_TXAOUT0+ GMCH_TXAOUT1+ GMCH_TXAOUT2+

LCTLA_CLK LCTLB_DATA

GMCH_BL_ON LBKLT_CRTL LIBG

AB29

GCLKN

AC29

GCLKP

A15

TVDAC_A

C16

TVDAC_B

A17

TVDAC_C

J18

TV_REFSET

B15

R83

4.99K

+/-1%

VSYNC HSYNC CRTIREF

L_LVBG L_VREFH L_VREFL

R111 2.2KR0402 +/-5%R111 2.2KR0402 +/-5% R112 2.2KR0402 +/-5%R112 2.2KR0402 +/-5%

R117 100KR0402 +/-5%R117 100KR0402 +/-5% R119 100KR0402 +/-5%R119 100KR0402 +/-5% R120 1.5KR0603 +/-1%R120 1.5KR0603 +/-1%

TV_IRTNA

B16

TV_IRTNB

B17

TV_IRTNC

E24

DDCCLK

E23

DDCDATA

E21

BLUE

D21

BLUE#

C20

GREEN

B20

GREEN#

A19

RED

B19

RED#

H21

VSYNC

G21

HSYNC

J20

REFSET

E25

LBKLT_CRTL

F25

LBKLT_EN

C23

LCTLA_CLK

C22

LCTLB_DATA

F23

LDDC_CLK

F22

LDDC_DATA

F26

LVDD_EN

C33

LIBG

C31

LVBG

F28

LVREFH

F27

LVREFL

B30

LACLKN

B29

LACLKP

C25

LBCLKN

C24

LBCLKP

B34

LADATAN0

B33

LADATAN1

B32

LADATAN2

A34

LADATAP0

A33

LADATAP1

B31

LADATAP2

C29

LBDATAN0

D28

LBDATAN1

C27

LBDATAN2

C28

LBDATAP0

D27

LBDATAP1

C26

LBDATAP2

LDDC_NB_CLK

B_LDDC_NB_DATA

2

ALVISO-GM

71.0GMCH.08U

EXP_ICOMPO

MISCTVVGALVDS

PCI-EXPRESS GRAPHICS

2D5V_S0 2D5V_S0 3D3V_S0

R106

R107

2.2K

+/-5%

R0402

2D5V_S0

D36

EXP_COMPI

D34 E30

EXP_RXN0

F34

EXP_RXN1

G30

EXP_RXN2

H34

EXP_RXN3

J30

EXP_RXN4

K34

EXP_RXN5

L30

EXP_RXN6

M34

EXP_RXN7

N30

EXP_RXN8

P34

EXP_RXN9

R30

EXP_RXN10

T34

EXP_RXN11

U30

EXP_RXN12

V34

EXP_RXN13

W30

EXP_RXN14

Y34

EXP_RXN15

D30

EXP_RXP0

E34

EXP_RXP1

F30

EXP_RXP2

G34

EXP_RXP3

H30

EXP_RXP4

J34

EXP_RXP5

K30

EXP_RXP6

L34

EXP_RXP7

M30

EXP_RXP8

N34

EXP_RXP9

P30

EXP_RXP10

R34

EXP_RXP11

T30

EXP_RXP12

U34

EXP_RXP13

V30

EXP_RXP14

W34

EXP_RXP15

E32

EXP_TXN0

F36

EXP_TXN1

G32

EXP_TXN2

H36

EXP_TXN3

J32

EXP_TXN4

K36

EXP_TXN5

L32

EXP_TXN6

M36

EXP_TXN7

N32

EXP_TXN8

P36

EXP_TXN9

R32

EXP_TXN10

T36

EXP_TXN11

U32

EXP_TXN12

V36

EXP_TXN13

W32

EXP_TXN14

Y36

EXP_TXN15

D32

EXP_TXP0

E36

EXP_TXP1

F32

EXP_TXP2

G36

EXP_TXP3

H32

EXP_TXP4

J36

EXP_TXP5

K32

EXP_TXP6

L36

EXP_TXP7

M32

EXP_TXP8

N36

EXP_TXP9

P32

EXP_TXP10

R36

EXP_TXP11

T32

EXP_TXP12

U36

EXP_TXP13

V32

EXP_TXP14

W36

EXP_TXP15

G

Q18

2N7002EPT

G

Q19

2N7002EPT

Title

Document Number Rev

Date: Sheet

R80 24.9

R506

2.2K

+/-5%

R0402

R507

2.2K

+/-5%

R0402

LDDC_CLK

DS

LDDC_DATA

DS

GMCH(2 of 5)

S09 MAINBOARD

1D5V_PCIE_S0

R0402

+/-1%R80 24.9

+/-1%

R508

2.2K

+/-5%

R0402

1

LDDC_CLK 13

LDDC_DATA 13

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M_A_DQ[63:0] 11

U3C

D D

C C

B B

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DM2 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_B_A2 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

AG35 AH35

AL35 AL37

AH36

AJ35

AK37

AL34 AM36 AN35 AP32 AM31 AM34 AM35

AL32 AM32 AN31 AP31 AN28 AP28

AL30 AM30 AM28

AL28 AP27 AM27 AM23 AM22

AL23 AM24 AN22 AP22

AM9

AL9 AL6

AP7 AP11 AP10

AL7 AM7 AN5 AN6 AN3 AP3 AP6 AM6

AL4 AM3 AK2 AK3 AG2 AG1

AL3 AM2 AH3 AG3

AF3 AE3 AD6 AC4

AF2

AF1 AD4 AD5

SADQ0 SADQ1 SADQ2 SADQ3 SADQ4 SADQ5 SADQ6 SADQ7 SADQ8 SADQ9 SADQ10 SADQ11 SADQ12 SADQ13 SADQ14 SADQ15 SADQ16 SADQ17 SADQ18 SADQ19 SADQ20 SADQ21 SADQ22 SADQ23 SADQ24 SADQ25 SADQ26 SADQ27 SADQ28 SADQ29 SADQ30 SADQ31 SADQ32 SADQ33 SADQ34 SADQ35 SADQ36 SADQ37 SADQ38 SADQ39 SADQ40 SADQ41 SADQ42 SADQ43 SADQ44 SADQ45 SADQ46 SADQ47 SADQ48 SADQ49 SADQ50 SADQ51 SADQ52 SADQ53 SADQ54 SADQ55 SADQ56 SADQ57 SADQ58 SADQ59 SADQ60 SADQ61 SADQ62 SADQ63

ALVISO-GM

AK15

SA_BS0#

AK16

SA_BS1#

AL21

SA_BS2#

AJ37

SA_DM0

AP35

SA_DM1

AL29

SA_DM2

AP24

SA_DM3

AP9

SA_DM4

AP4

SA_DM5

AJ2

SA_DM6

AD3

SA_DM7

SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7

SA_DQS0# SA_DQS1# SA_DQS2# SA_DQS3# SA_DQS4# SA_DQS5# SA_DQS6# SA_DQS7#

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6

DDR SYSTEM MEMORY A

SA_MA7 SA_MA8

SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13

SA_CAS# SA_RAS#

SA_RCVENIN#

SA_RCVENOUT#

SA_WE#

M_A_DQS0

AK36

M_A_DQS1

AP33

M_A_DQS2

AN29

M_A_DQS3

AP23

M_A_DQS4

AM8

M_A_DQS5

AM4

M_A_DQS6

AJ1

M_A_DQS7

AE5

M_A_DQSJ0

AK35

M_A_DQSJ1

AP34

M_A_DQSJ2

AN30

M_A_DQSJ3

AN23

M_A_DQSJ4

AN8

M_A_DQSJ5

AM5

M_A_DQSJ6

AH1

M_A_DQSJ7

AE4 AL17

AP17 AP18 AM17 AN18 AM18 AL19 AP20 AM19 AL20 AM16 AN20 AM20 AM15

AN15 AP16

TP_MA_RCVENINJ

AF29

TP_MA_RCVENOUTJ

AF28 AP15

M_A_DM0 M_A_DM1

M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13

M_A_BSJ0 11 M_A_BSJ1 11 M_A_BSJ2 11 M_A_DM[7:0] 11

M_A_DQS[7:0] 11

M_A_DQSJ[7:0] 11

M_A_A[13:0] 11

M_A_CASJ 11 M_A_RASJ 11

M_A_WEJ 11

TP40TP40

1

TP42TP42

1

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

M_B_DQ[63:0] 11

U3D

AE31

SBDQ0

AE32

SBDQ1

AG32

SBDQ2

AG36

SBDQ3

AE34

SBDQ4

AE33

SBDQ5

AF31

SBDQ6

AF30

SBDQ7

AH33

SBDQ8

AH32

SBDQ9

AK31

SBDQ10

AG30

SBDQ11

AG34

SBDQ12

AG33

SBDQ13

AH31

SBDQ14

AJ31

SBDQ15

AK30

SBDQ16

AJ30

SBDQ17

AH29

SBDQ18

AH28

SBDQ19

AK29

SBDQ20

AH30

SBDQ21

AH27

SBDQ22

AG28

SBDQ23

AF24

SBDQ24

AG23

SBDQ25

AJ22

SBDQ26

AK22

SBDQ27

AH24

SBDQ28

AH23

SBDQ29

AG22

SBDQ30

AJ21

SBDQ31

AG10

SBDQ32

AG9

SBDQ33

AG8

SBDQ34

AH8

SBDQ35

AH11

SBDQ36

AH10

SBDQ37

AJ9

SBDQ38

AK9

SBDQ39

AJ7

SBDQ40

AK6

SBDQ41

AJ4

SBDQ42

AH5

SBDQ43

AK8

SBDQ44

AJ8

SBDQ45

AJ5

SBDQ46

AK4

SBDQ47

AG5

SBDQ48

AG4

SBDQ49

AD8

SBDQ50

AD9

SBDQ51

AH4

SBDQ52

AG6

SBDQ53

AE8

SBDQ54

AD7

SBDQ55

AC5

SBDQ56

AB8

SBDQ57

AB6

SBDQ58

AA8

SBDQ59

AC8

SBDQ60

AC7

SBDQ61

AA4

SBDQ62

AA5

SBDQ63

ALVISO-GM

AJ15

SB_BS0#

AG17

SB_BS1#

AG21

SB_BS2#

SB_DM0 SB_DM1 SB_DM2 SB_DM3 SB_DM4 SB_DM5 SB_DM6 SB_DM7

SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7

SB_DQS0# SB_DQS1# SB_DQS2# SB_DQS3# SB_DQS4# SB_DQS5# SB_DQS6# SB_DQS7#

SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8

DDR SYSTEM MEMORY B

SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13

SB_CAS# SB_RAS#

SB_RCVENIN#

SB_RCVENOUT#

SB_WE#

M_B_DM0

AF32

M_B_DM1

AK34

M_B_DM2

AK27

M_B_DM3

AK24

M_B_DM4

AJ10

M_B_DM5

AK5

M_B_DM6

AE7

M_B_DM7

AB7

M_B_DQS0

AF34

M_B_DQS1

AK32

M_B_DQS2

AJ28

M_B_DQS3

AK23

M_B_DQS4

AM10

M_B_DQS5

AH6

M_B_DQS6

AF8

M_B_DQS7

AB4

M_B_DQSJ0

AF35

M_B_DQSJ1

AK33

M_B_DQSJ2

AK28

M_B_DQSJ3

AJ23

M_B_DQSJ4

AL10

M_B_DQSJ5

AH7

M_B_DQSJ6

AF7

M_B_DQSJ7

AB5

M_B_A0

AH17

M_B_A1

AK17 AH18

M_B_A3

AJ18

M_B_A4

AK18

M_B_A5

AJ19

M_B_A6

AK19

M_B_A7

AH19

M_B_A8

AJ20

M_B_A9

AH20

M_B_A10

AJ16

M_B_A11

AG18

M_B_A12

AG20

M_B_A13

AG15

AH14 AK14

TP_MB_RCVENINJ

AF15

TP_MB_RCVENOUTJ

AF14 AH16

M_B_BSJ0 11

M_B_BSJ1 11 M_B_BSJ2 11 M_B_DM[7:0] 11

M_B_DQS[7:0] 11

M_B_DQSJ[7:0] 11

M_B_A[13:0] 11

M_B_CASJ 11 M_B_RASJ 11

M_B_WEJ 11

Place Test PAD Near to Chip ascould as possible

1 1

TP41TP41 TP43TP43

A A

TECHNOLOGY COPR.

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845Monday, March 14, 2005

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845Monday, March 14, 2005

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Title

GMCH(3 of 5)

Document Number Rev

Date: Sheet

4

3

2

Date: Sheet

GMCH(3 of 5)

S09 MAINBOARD

5

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4

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1

1D5V_S0

D1

2 1

SSM5818D1SSM5818

F17

E17

VCCA_TVDACA0

VCCA_TVDACA1

D18

C18

VCCA_TVDACB0

F18

E18

VCCA_TVDACB1

VCCA_TVDACC0

1D5V_TVDAC_S0

1D5V_QTVDAC_S0

1D5V_DLVDS_S0 VDIMM

2D5V_ALVDS_S0

H17

B26

B25

D19

VCCD_TVDAC

VCCD_LVDS0

VCCDQ_TVDAC

A25

A35

VCCA_LVDS

VCCD_LVDS1

VCCD_LVDS2

B22

VCCHV0

H18

VCCA_TVBG

VCCA_TVDACC1

G18

VSSA_TVBG

B21

A21

VCCHV1

VCCHV2

BC110

0.1uF

*

C0402

BC115

0.1uF

*

C0402

*

BC124

0.1uF

C0402

*

BC127

0.1uF

C0402

V1.8_DDR_CAP1

V1.8_DDR_CAP2

V1.8_DDR_CAP5

AM37

AH37

AP29

AD28

AD27

AC27

VCCSM0

VCCSM1

VCCSM2

VCCSM3

VCCSM4

R128 0 R0603 +/-5%R128 0 R0603 +/-5%

Note: All VCCSM pins shorted internally

BC133

0.1uF

C0402

AP26

AN26

VCCSM5

VCCSM6

2D5V_TVDAC_S0

*

BC119

0.1uF

C0402

*

AM26

AL26

AK26

AJ26

AH26

VCCSM7

VCCSM8

VCCSM9

VCCSM10

VCCSM11

VCCSM12

R123 0 R0603 +/-5%R123 0 R0603 +/-5%

AG26

AF26

AE26

VCCSM13

VCCSM14

BC112

0.1uF

*

10V, X5R, +/-10%

C0402

BC116

0.1uF

*

10V, X5R, +/-10%

C0402

BC123

0.1uF

*

10V, X5R, +/-10%

C0402

BC126

0.1uF

*

10V, X5R, +/-10%

C0402

1D5V_S0_L

3D3V_TVDACA_S0

3D3V_TVDACB_S0

3D3V_TVDACC_S0

3D3V_ATVBG_S0

R121 10

R0603 +/-1%

D D

C C

R126 0 R0603 +/-5%R126 0 R0603 +/-5%

3D3V_S0

R130 0 R0603 +/-5%R130 0 R0603 +/-5%

R136 0 R0603 +/-5%R136 0 R0603 +/-5%

R138 0 R0603 +/-5%R138 0 R0603 +/-5%

Route ASSATVBG gnd from GMCH to decoupling cap groung lead and then connect to the gnd plane

1D5V_S0

R134 0 R0603 +/-5%R134 0 R0603 +/-5% BC120

BC120

10uF

*

10V, Y5V, +80%/-20%

C0805

AP25

AN25

AM25

AL25

AK25

AJ25

AH25

VCCSM15

VCCSM16

VCCSM17

VCCSM18

VCCSM19

VCCSM20

VCCSM21

POWER

AG25

AF25

AE25

VCCSM22

VCCSM23

VCCSM24

VCCSM25

1D5V_S0

R122 0 R0603 +/-5%R122 0 R0603 +/-5%

2D5V_S0 2D5V_ALVDS_S0

R129 0 R0603 +/-5%R129 0 R0603 +/-5%

2D5V_S0

2D5V_S0 2D5V_TXLVDS_S0

R135 0 R0603 +/-5%R135 0 R0603 +/-5%

1.8v_s3

*

BC132

BC131

AE24

AE23

AE22

AE21

VCCSM26

VCCSM27

VCCSM28

10uF C0805

AE20

VCCSM29

VCCSM30

10V, Y5V, +80%/-20%

AE19

10uF C0805

10V, Y5V, +80%/-20%

AE18

AE17

AE16

AE15

AE14

AP13

VCCSM31

VCCSM32

VCCSM33

VCCSM34

VCCSM35

VCCSM36

VCCSM37

BC108

0.1uF

C0402

BC113

0.1uF

C0402

BC121

0.1uF

C0402

BC554

10uF

*

10V, Y5V, +80%/-20%

C0805

AN13

AM13

AL13

AK13

AJ13

VCCSM38

VCCSM39

VCCSM40

VCCSM41

*

AH13

VCCSM42

VCCSM43

AG13

AF13

AE13

VCCSM44

VCCSM45

VCCSM46

1D5V_DLVDS_S0

BC549

10uF

*

10V, Y5V, +80%/-20%

C0805

BC114

10uF

*

10V, Y5V, +80%/-20%

C0805

BC122

4.7uF

*

10V, Y5V, +80%/-20%

C0805

AP12

AN12

AM12

AL12

AK12

AJ12

VCCSM47

VCCSM48

VCCSM49

VCCSM50

VCCSM51

VCCSM52

Note: All VCCSM pins shorted internally

BC134

*

0.1uF

C0402

AH12

AG12

AF12

AE12

AD11

AC11

VCCSM53

VCCSM54

VCCSM55

VCCSM56

VCCSM57

AB11

AB10

VCCSM58

VCCSM59

VCCSM60

*

BC125

0.1uF

C0402

*

BC128

0.1uF

C0402

2D5V_TXLVDS_S0

V1.8_DDR_CAP3

V1.8_DDR_CAP4

V1.8_DDR_CAP6

AB9

AP8

AM1

AE1

VCCSM61

VCCSM62

VCCSM63

VCCSM64

B28

A28

VCCTX_LVDS0

VCCTX_LVDS1

A27

VCCTX_LVDS2

AF20

VCCA_SM0

AP19

AF19

AF18

VCCA_SM1

VCCA_SM2

1D5V_PCIE_S0

*

AE37

W37

U37

VCC3G0

VCC3G1

VCC3G2

VCCA_SM3

*

BC117

10uF

C0805

R37

N37

VCC3G3

VCC3G4

BC111

0.1uF

C0402

*

L37

J37

VCC3G5

VCC3G6

Note:VCCASM: 0.76A

R125 0

TC2

220uF

*

2.5V, +/-20%

ctbh20

2 1

BC118

TC3

10uF

C0805

10uF

*

10V, Y5V, +80%/-20%

C0805

*

Note:3GIO: 1A

1D5V_3GPLL_S0

BC129

BC130

0.1uF

10uF

*

C0402

10V, Y5V, +80%/-20%

C0805

2D5V_3GBG_S0 2D5V_S0

*

F37

Y27

Y29

Y28

G37

VSSA_3GBG

VCCA_3GBG

VCCA_3GPLL2

VCCA_3GPLL0

VCCA_3GPLL1

1D5V_S01D5V_DDRDLL_S0

+/-5%R125 0

+/-5%

R0805

R133 0 R0805 +/-5%R133 0 R0805 +/-5%

R141 0 R0603 +/-5%R141 0 R0603 +/-5%

BC135

0.1uF

C0402

U3E

U3E ALVISO-GM

ALVISO-GM

71.0GMCH.08U

1D5V_S0

R140 0 R0805 +/-5%R140 0 R0805 +/-5%

VCC0

VCC1

VCC2

VCC3

VCC4

VCC5

VCC6

VCC7

VCC8

VCC9

VCC10

VCC11

VCC12

VCC13

VCC14

VCC15

VCC16

VCC17

VCC18

VCC19

VCC20

VCC21

VCC22

VCC23

VCC24

VCC25

VCC26

VCC27

VCC28

VCC29

VCC30

VCC31

VCC32

VCC33

VCC34

VCC35

VCC36

VCC37

VCC38

VCC39

VCC40

VCC41

VCC42

VCC43

VCC44

VCC45

VCC46

VCC47

VCC48

VCCH_MPLL1

VCCH_MPLL0

VCCA_DPLLA

VCCA_DPLLB

VCCA_HPLL

VCCA_MPLL

VCCA_CRTDAC0

VCCA_CRTDAC1

VSSA_CRTDAC

VCC_SYNC

VTT0

VTT1

VTT2

VTT3

VTT4

VTT5

VTT6

VTT7

VTT8

VTT9

VTT10

VTT11

VTT12

VTT13

VTT14

VTT15

VTT16

VTT17

VTT18

VTT19

VTT20

VTT21

VTT22

VTT23Y9VTT24W9VTT25U9VTT26R9VTT27P9VTT28N9VTT29M9VTT30L9VTT31J9VTT32N8VTT33M8VTT34N7VTT35M7VTT36N6VTT37M6VTT38A6VTT39N5VTT40M5VTT41N4VTT42M4VTT43N3VTT44M3VTT45N2VTT46M2VTT47B2VTT48V1VTT49N1VTT50M1VTT51

J29

T29

0.1uF C0402

R29

*

BC140

B B

NB_CORE_S0

*

BC136

10uF C0805

10V, Y5V, +80%/-20%

A A

5

*

BC137

10uF C0805

10V, Y5V, +80%/-20%

*

BC138

BC139

10uF C0805

10V, Y5V, +80%/-20%

T28

K29

V28

N29

U28

M29

*

BC141

0.1uF C0402

R28

0.1uF C0402

P28

N28

M28

*

BC142

Dummy

1D5V_S0

J28

L28

T27

K28

V27

H28

U27

G28

0.1uF C0402

10V, X5R, +/-10%

4

P27

R27

L2

*

L0805 1uH

L3

*

L0805 1uH

L4

*

L0805 1uH

L5

*

L0805 1uH

J27

K27

K26

H27

*

J25

K25

K24

K23

K22

K21

H26

BC555

10uF

10V, Y5V, +80%/-20%

C0805

BC556

10uF

10V, Y5V, +80%/-20%

C0805

BC557

10uF

10V, Y5V, +80%/-20%

C0805

BC558

10uF

10V, Y5V, +80%/-20%

C0805

W20

T20

U20

*

BC148

*

BC150

*

BC154

*

BC155

K20

V19

K19

U19

1D5V_DPLLA_S0

0.1uF C0402

10V, X5R, +/-10%

0.1uF C0402

10V, X5R, +/-10%

1D5V_DPLLB_S0

0.1uF C0402

10V, X5R, +/-10%

0.1uF C0402

10V, X5R, +/-10%

1D5V_HPLL_S0

0.1uF C0402

10V, X5R, +/-10%

0.1uF C0402

10V, X5R, +/-10%

1D5V_MPLL_S0

0.1uF C0402

10V, X5R, +/-10%

0.1uF C0402

10V, X5R, +/-10%

T18

V18

K18

K17

AC2

W18

3

F19

B23

E19

C35

AA1

AA2

AC1

L27

N27

M27

J13

K13

K12

V11

H20

G19

Layout Notes: VSSA_CRTDAC Route caps within 250mil of Alviso. Route FB within 3" of Alviso.

U11

W11

2D5V_CRTDAC_S0

L11

T11

P11

R11

N11

*

BC147

C0402

0.1uF

T10

K11

V10

P10

U10

M11

Route VSSA_CRTDAC gnd from GMCH to decoupling cap ground lead and then connect to the gnd plane.

R10

W10

R144 0 R0603 +/-5%R144 0 R0603 +/-5%

BC149

*

0.1uF

C0402

J10

K10

N10

M10

VCCP_GMCH_CAP1

16V, Y5V, +80%/-20%

BC143

2D5V_S0

R146

10

R0402

+/-5%

2

BC143

0.47uF

C0603

16V, Y5V, +80%/-20%

NB_CORE_S0_L

*

16V, Y5V, +80%/-20%

BC144

*

0.47uF

C0603

1D05V_S0

BC151

*

4.7uF

C0805

2 1

SSM5818D2SSM5818

Title

Document Number Rev

Date: Sheet

G1

VCCP_GMCH_CAP4

VCCP_GMCH_CAP3

VCCP_GMCH_CAP2

BC145

BC1460.22uF

*

0.22uF

BC152

2.2uF

C0805

NB_CORE_S0

D2

GMCH(4 of 5)

S09 MAINBOARD

16V, Y5V, +80%/-20%

BC153

0.1uF

*

10V, X5R, +/-10%

C0402

1

TECHNOLOGY COPR.

A

of

945Monday, March 14, 2005

of

945Monday, March 14, 2005

of

945Monday, March 14, 2005

5

www.hocnghetructuyen.vn

D D

ALVISO-GM

U3F

71.0GMCH.08U

C C

B36

U3H

VSSALVDS

G26

E26

A26

AN24

AL24

VSS263

VSS264

VSS265

VSS266

VSS267

Y1

VDIMM

B27

J26

VSS261

VSS262

VSS260L2VSS268J2VSS269G2VSS270D2VSS271

AC12

AB12

AB27

AA27

W27

G27

E27

VSS126

VSS127

VSS128

VSS129

VSS259P2VSS258T2VSS257V2VSS256

AE2

AD2

1.8v_s3

BC156

*

Dummy

AC14

AD13

AC13

AB13

AD12

W28

E28

AN27

AL27

AJ27

AG27

AF27

VSS119

VSS120

VSS121

VSS122

VSS123

VSS124

VSS125

VSS255

VSS254

VSS253

VSS252

VSS251A3VSS250C3VSS249

AL2

AA3

AB3

AH2

AN2

BC157

*

10uF

10V, Y5V, +80%/-20%

Dummy

AD17

AC17

AD16

AC16

AD15

AC15

AD14

F29

E29

D29

A29

AC28

AB28

AA28

VSS111

VSS112

VSS113

VSS114

VSS115

VSS116

VSS117

VSS118

VSS248

VSS247

VSS246

VSS245C4VSS244H4VSS243L4VSS242P4VSS241U4VSS240Y4VSS239

AJ3

AC3

Place these Hi-Freq decoupling caps near GMCH

BC158

*

10uF

10V, Y5V, +80%/-20%

Dummy

AC21

AD20

AC20

AD19

AC19

AD18

AC18

G29

VSS110

10V, Y5V, +80%/-20%

Dummy

AD21

L29

H29

VSS109

AF4

AN4

BC159

*

AD22

AC22

W29

V29

U29

P29

VSS104

VSS105

VSS106

VSS107

VSS108

VSS238

VSS237E5VSS236W5VSS235

VSS234

AL5

AP5

10uF

10V, Y5V, +80%/-20%

Dummy

AD24

AC24

AD23

AC23

AJ29

AG29

AD29

AA29

VSS101

VSS102

VSS103

VSS233B6VSS232J6VSS231L6VSS230P6VSS229T6VSS228

BC160

*

10uF

AD26

AC26

AD25

AC25

4

A32

AL31

AG31

AD31

W31

V31

U31

T31

R31

P31

N31

M31

L31

K31

J31

H31

G31

F31

E31

D31

AP30

AE30

AC30

AB30

AA30

Y30

C30

AM29

VSS72

VSS73

VSS74

VSS75

VSS76

VSS77

VSS78

VSS79

VSS80

VSS81

VSS82

VSS83

VSS84

VSS85

VSS86

VSS87

VSS88

VSS89

VSS90

VSS91

VSS92

VSS93

VSS94

VSS95

VSS96

VSS97

VSS98

VSS99

VSS100

VSS

VSS227

VSS226

VSS225

VSS224G7VSS223V7VSS222

VSS221

VSS220

VSS219

VSS218C8VSS217E8VSS216L8VSS215P8VSS214Y8VSS213

VSS212A9VSS211H9VSS210K9VSS209T9VSS208V9VSS207

VSS206

VSS205

VSS204

VSS203

VSS202

AA6

10V, Y5V, +80%/-20%

Dummy

L17

AE6

AC6

BC161

*

N17

M17

AJ6

AA7

AK7

AG7

*

10uF

10V, Y5V, +80%/-20%

Dummy

L18

W17

V17

U17

T17

P17

AN7

BC162

0.1uF C0402

N18

M18

AL8

BC163

*

0.1uF C0402

Dummy

Y19

R19

P19

N19

M19

L19

Y18

R18

P18

D10

AA9

AE9

AC9

AH9

AN9

BC164

*

0.1uF C0402

Dummy

L21

Y20

R20

P20

N20

M20

L20

Y32

C32

VSS71

VSS201

L10

Y10

BC165

0.1uF C0402

N21

M21

3

AC34

AB34

AA34

C34

AL33

AF33

AD33

W33

V33

U33

T33

R33

P33

N33

M33

L33

K33

J33

H33

G33

F33

E33

D33

AN32

AJ32

AD32

AC32

AB32

AA32

VSS41

VSS42

VSS43

VSS44

VSS45

VSS46

VSS47

VSS48

VSS49

VSS50

VSS51

VSS52

VSS53

VSS54

VSS55

VSS56

VSS57

VSS58

VSS59

VSS60

VSS61

VSS62

VSS63

VSS64

VSS65

VSS66

VSS67

VSS68

VSS69

VSS70

VSS196

VSS195

VSS194

VSS193

VSS192

VSS191

VSS190

VSS189

VSS188

VSS187

VSS186

VSS185

VSS184

VSS183

VSS182

VSS181

VSS180

VSS179

VSS178

VSS177

VSS176

VSS175

VSS174

VSS173

VSS172

VSS200

VSS199

VSS198

VSS197

J12

J14

F11

Y11

H11

AJ11

AL11

AF11

AA11

AA10

AG11

P21

T21

P22

N22

M22

L22

W21

V21

U21

F14

B12

A14

B14

K14

D12

AN11

V22

U22

T22

R22

AJ14

AL14

AN14

AG14

V23

U23

T23

R23

P23

N23

M23

L23

W22

VSS171

K15

A16

K16

C15

D16

H16

AL16

T24

R24

P24

N24

M24

L24

W23

2

AN36

AL36

AJ36

AF36

AE36

AD36

AC36

AB36

AA36

C36

AE35

Y35

W35

V35

U35

T35

R35

P35

N35

M35

L35

K35

J35

H35

G35

F35

E35

D35

B35

AN34

AH34

AD34

VSS9

VSS10

VSS11

VSS12

VSS13

VSS14

VSS15

VSS16

VSS17

VSS18

VSS19

VSS20

VSS21

VSS22

VSS23

VSS24

VSS25

VSS26

VSS27

VSS28

VSS29

VSS30

VSS31

VSS32

VSS33

VSS34

VSS35

VSS36

VSS37

VSS38

VSS39

VSS40

VSS170

VSS169

VSS168

VSS167

VSS166

VSS165

VSS164

VSS163

VSS162

VSS161

VSS160

VSS159

VSS158

VSS157

VSS156

VSS155

VSS154

VSS153

VSS152

VSS151

VSS150

VSS149

VSS148

VSS147

VSS146

VSS145

VSS144

VSS143

VSS142

VSS141

VSS140

VSS139

J19

A18

C17

G17

AJ17

AF17

AN17

N25

M25

L25

W24

V24

U24

T19

B18

U18

C19

H19

AL18

V25

U25

T25

R25

P25

L26

W25

F20

A20

E20

V20

D20

C21

AG19

N26

AN19

R26

P26

G20

NB_CORE_S0

W26

V26

U26

T26

AK20

W19

M26

J22

F21

A22

E22

D22

AF21

AN21

AH22

1

AG37

Y37

V37

T37

P37

M37

K37

H37

E37

VSS0

VSS1

VSS2

VSS3

VSS4

VSS5

VSS6

VSS7

VSS8

VSS138

VSS137

VSS136

VSS135

VSS134

VSS133

VSS132

VSS131

VSS130

J24

F24

B24

H23

D24

AL22

AJ24

AF23

AG24

VCC_NTTF69

VCC_NCTF63

VCC_NCTF64

VCC_NCTF65

VCC_NCTF66

VCC_NCTF67

VCC_NCTF68

VCC_NCTF70

VCC_NCTF71

VCC_NCTF72

VCC_NCTF73

VCC_NCTF74

VCC_NCTF75

VCC_NCTF76

VCC_NCTF77

VCC_NCTF78

VCCSM_NCTF0

VCCSM_NCTF1

VCCSM_NCTF2

VCCSM_NCTF3

VCCSM_NCTF4

VCCSM_NCTF5

VCCSM_NCTF6

VCCSM_NCTF7

VCCSM_NCTF8

VCCSM_NCTF9

VCCSM_NCTF10

VCCSM_NCTF11

VCCSM_NCTF12

VCCSM_NCTF13

VCCSM_NCTF14

VCCSM_NCTF15

VCCSM_NCTF16

VCCSM_NCTF17

VCCSM_NCTF18

VCCSM_NCTF19

VCCSM_NCTF20

VCCSM_NCTF21

VCCSM_NCTF22

VCCSM_NCTF23

VCCSM_NCTF24

VCCSM_NCTF25

VCCSM_NCTF26

VCCSM_NCTF27

VCCSM_NCTF28

VCCSM_NCTF29

VCCSM_NCTF30

VCCSM_NCTF31

VSS_NCTF68

VSS_NCTF67

VSS_NCTF66

VSS_NCTF65

VSS_NCTF64

VTT_NCTF17

VTT_NCTF16

VTT_NCTF15

VTT_NCTF14

VTT_NCTF13

VTT_NCTF12

VTT_NCTF11

VTT_NCTF10

VTT_NCTF9

VTT_NCTF8

VTT_NCTF7

VTT_NCTF6

VTT_NCTF5

VTT_NCTF4

VTT_NCTF3

VTT_NCTF2

VTT_NCTF1

ALVISO-GM

B B

A A

ALVISO-GM

71.0GMCH.08U

L12

N12

M12

1D05V_S0

5

L13

T12

P12

V12

R12

U12

M13

W12

VTT_NCTF0

T13

P13

V13

N13

R13

U13

W13

4

VSS_NCTF63

L14

Y12

Y13

N14

M14

AA12

AA13

VCC_NCTF56

VCC_NCTF57

VCC_NCTF58

VCC_NCTF59

VCC_NCTF60

VCC_NCTF61

VCC_NCTF62

NCTF

VSS_NCTF62

VSS_NCTF61

VSS_NCTF60

VSS_NCTF59

VSS_NCTF58

VSS_NCTF57

VSS_NCTF56

T14

P14

V14

R14

U14

W14

VCC_NCTF49

VCC_NCTF50

VCC_NCTF51

VCC_NCTF52

VCC_NCTF53

VCC_NCTF54

VCC_NCTF55

VSS_NCTF55

VSS_NCTF54

VSS_NCTF53

VSS_NCTF52

VSS_NCTF51

L15

Y14

M15

AA14

AB14

VCC_NCTF44

VCC_NCTF45

VCC_NCTF46

VCC_NCTF47

VCC_NCTF48

VSS_NCTF50

VSS_NCTF49

VSS_NCTF48

VSS_NCTF47

VSS_NCTF46

VSS_NCTF45

VSS_NCTF44

T15

P15

V15

N15

R15

U15

W15

3

VCC_NCTF37

VCC_NCTF38

VCC_NCTF39

VCC_NCTF40

VCC_NCTF41

VCC_NCTF42

VCC_NCTF43

VSS_NCTF43

VSS_NCTF42

VSS_NCTF41

VSS_NCTF40

VSS_NCTF39

VSS_NCTF38

VSS_NCTF37

L16

Y15

P16

N16

R16

M16

AA15

AB15

VCC_NCTF30

VCC_NCTF31

VCC_NCTF32

VCC_NCTF33

VCC_NCTF34

VCC_NCTF35

VCC_NCTF36

VSS_NCTF36

VSS_NCTF35

VSS_NCTF34

VSS_NCTF33

VSS_NCTF32

VSS_NCTF31

VSS_NCTF30

T16

V16

Y16

U16

W16

AA16

AB16

VCC_NCTF29

VSS_NCTF29

R17

VCC_NCTF27

VCC_NCTF28

VSS_NCTF28

VSS_NCTF27

Y17

AA17

VCC_NCTF23

VCC_NCTF24

VCC_NCTF25

VCC_NCTF26

VSS_NCTF26

VSS_NCTF25

VSS_NCTF24

VSS_NCTF23

AB17

AA18

AB18

NB_CORE_S0

VCC_NCTF18

VCC_NCTF19

VCC_NCTF20

VCC_NCTF21

VCC_NCTF22

VSS_NCTF22

VSS_NCTF21

VSS_NCTF20

VSS_NCTF19

VSS_NCTF18

R21

AA19

AB19

AA20

AB20

@GML

R149 0

R1206 +/-5%

@GML

R148 0

R1206 +/-5%

R630 0

R1206 +/-5%

@GM

R631 0

R1206 +/-5%

@GM

VCC_NCTF16

VCC_NCTF17

VSS_NCTF17

VSS_NCTF16

Y21

AA21

VCC_NCTF15

VSS_NCTF15

AB21

VCC_NCTF13

VCC_NCTF14

VSS_NCTF14

VSS_NCTF13

Y22

AA22

1D05V_S0

2

VCC_NCTF9

VCC_NCTF10

VCC_NCTF11

VCC_NCTF12

VSS_NCTF12

VSS_NCTF11

VSS_NCTF10

VSS_NCTF9

VSS_NCTF8

VSS_NCTF7

VSS_NCTF6

VSS_NCTF5

VSS_NCTF4

VSS_NCTF3

VSS_NCTF2

VSS_NCTF1

VSS_NCTF0

Y23

Y24

Y25

AB22

AA23

AB23

1D5V_S0

Y26

AA24

AB24

AA25

AB25

AA26

AB26

GML: NB_CORE=1.05V GM: NB_CORE=1.5V

TECHNOLOGY COPR.

Title

Document Number Rev

Date: Sheet

GMCH(5 of 5)

S09 MAINBOARD

TECHNOLOGY COPR.

10 45Monday, March 14, 2005

1

A

of

VCC_NCTF0

VCC_NCTF1

VCC_NCTF2

VCC_NCTF3

VCC_NCTF4

VCC_NCTF5

VCC_NCTF6

VCC_NCTF7

VCC_NCTF8

5

www.hocnghetructuyen.vn

CN1

M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7

SA0_DIM1 SA1_DIM1

10V, Y5V, +80%/-20%

BC583

2.2uF

C0603

M_A_DQS[7:0] 8

M_A_DQSJ[7:0] 8

M_A_DM[7:0] 8

*

VDIMM

M_A_A[13:0]8

D D

M_A_BSJ28

M_A_BSJ08 M_A_BSJ18

M_A_DQ[63:0]8

C C

B B

M_CS0_RJ7

M_CS1_RJ7 M_CKE0_RJ7 M_CKE1_RJ7

DDR_VREF

10V, X7R, +/-10%

B_SMBD_ICH3,17

BC588

*

0.1uF

C0402

M_A_RASJ8 M_A_CASJ8

M_A_WEJ8

SMBC_ICH3,17

BC589

2.2uF

C0603

M_A_A0

102 101 100

99 98 97 94 92 93 91

105

90 89

116

86 84 85

107 106

5

7 17 19

4

6 14 16 23 25 35 37 20 22 36 38 43 45 55 57 44 46 56 58 61 63 73 75 62 64 74 76

123 125 135 137 124 126 134 136 141 143 151 153 140 142 152 154 157 159 173 175 158 160 174 176 179 181 189 191 180 182 192 194

50 69 83

120 163

110 115

79 80

108 113 109

197 195

114 119

1

201

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16_BA2

BA0 BA1

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13

VDD_SPD DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

LOW 4.0mm DDRII SDRAM SO-DIMM (200P)

NC#50 NC#69 NC#83 NC#120 NC#163/TEST

CS0# CS1# CKE0 CKE1 RAS# CAS# WE#

SCL SDA

ODT0 ODT1

VREF GND

DDR_SO-DIMM

M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8

M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

M_ODT07 M_ODT17

10V, Y5V, +80%/-20%

DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6

DQS7 DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7#

CK0# CK1#

M_A_DQS0

13

M_A_DQS1

31

M_A_DQS2

51

M_A_DQS3

70

M_A_DQS4

131

M_A_DQS5

148

M_A_DQS6

169

M_A_DQS7

188

M_A_DQSJ0

11

M_A_DQSJ1

29

M_A_DQSJ2

49

M_A_DQSJ3

68

M_A_DQSJ4

129

M_A_DQSJ5

146

M_A_DQSJ6

167

M_A_DQSJ7

186

10

DM0

26

DM1

52

DM2

67

DM3

130

DM4

147

DM5

170

DM6

185

DM7

30

CK0

32 164

CK1

166 198

SA0

200

SA1

199

81

VDD

82

VDD

87

VDD

88

VDD

95

VDD

96

VDD

103

VDD

104

VDD

111

VDD

112

VDD

117

VDD

118

VDD

2

VSS

3

VSS

8

VSS

9

VSS

12

VSS

15

VSS

18

VSS

21

VSS

24

VSS

27

VSS

28

VSS

33

VSS

34

VSS

39

VSS

40

VSS

41

VSS

42

VSS

47

VSS

48

VSS

53

VSS

54

VSS

59

VSS

60

VSS

65

VSS

66

VSS

71

VSS

72

VSS

77

VSS

78

VSS

121

VSS

122

VSS

127

VSS

128

VSS

132

VSS

133

VSS

138

VSS

139

VSS

144

VSS

145

VSS

149

VSS

150

VSS

155

VSS

156

VSS

161

VSS

162

VSS

165

VSS

168

VSS

171

VSS

172

VSS

177

VSS

178

VSS

183

VSS

184

VSS

187

VSS

190

VSS

193

VSS

196

VSS

202

GND

CLK_DDR0 7 CLK_DDR0J 7 CLK_DDR1 7 CLK_DDR1J 7

BC582

0.1uF

*

C0402

+/-1% R52110K

+/-1% +/-1% R52310K

+/-1%

R0402

10V, X7R, +/-10%

4

3D3V_S0

R0402

3

CN2

M_B_A[13:0]8

M_B_BSJ28 M_B_BSJ08

M_B_BSJ18 M_CS2_RJ7 M_CS3_RJ7

CLK_DDR37

CLK_DDR3J7

CLK_DDR47

CLK_DDR4J7

M_CKE2_RJ7 M_CKE3_RJ7

M_B_CASJ8

R0402

R520 10K

3D3V_S0

R52110K R52310K

R522 10K

DDR_VREF

R0402

M_B_RASJ8

M_B_WEJ8

+/-1%R520 10K

+/-1% +/-1%R522 10K

+/-1%

SMBC_ICH3,17 B_SMBD_ICH3,17

M_B_DM[7:0]8

M_B_DQS[7:0]8

M_B_DQSJ[7:0]8

3D3V_S0

*

10V, X7R, +/-10%

BC586

0.1uF

*

C0402

10V, X7R, +/-10%

M_B_A0 M_B_A1 M_B_A2 M_B_A3

M_B_A4

M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13

SA0_DIM2 SA1_DIM2

M_ODT27 M_ODT37

BC580

0.1uF

C0402

*

16V, Y5V, +80%/-20%

VDIMM

BC587

2.2uF

C0805

*

M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7 M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_B_DQSJ0 M_B_DQSJ1 M_B_DQSJ2 M_B_DQSJ3 M_B_DQSJ4 M_B_DQSJ5 M_B_DQSJ6 M_B_DQSJ7

BC581

2.2uF

C0603

CN2

102

A0

101

A1

100

A2

99

A3

98

A4

97

A5

94

A6

92

A7

93

A8

91

A9

105

A10/AP

90

A11

89

A12

116

A13

86

A14

84

A15

85

A16_BA2

107

BA0

106

BA1

110

S0#

115

S1#

30

CK0

32

CK0#

164

CK1

166

CK1#

79

CKE0

80

CKE1

113

CAS#

108

RAS#

109

WE#

198

SA0

200

SA1

197

SCL

195

SDA

114

ODT0

119

ODT1

10

DM0

26

DM1

52

DM2

67

DM3

130

DM4

147

DM5

170

DM6

185

DM7

13

DQS0

31

DQS1

51

DQS2

70

DQS3

131

DQS4

148

DQS5

169

DQS6

188

DQS7

11

DQS#0

29

DQS#1

49

DQS#2

68

DQS#3

129

DQS#4

146

DQS#5

167

DQS#6

186

DQS#7

112

VDD1

111

VDD2

117

VDD3

96

VDD4

95

VDD5

118

VDD6

81

VDD7

82

VDD8

87

VDD9

103

VDD10

88

VDD11

104

VDD12

199

VDDSPD

83

NC1

120

NC2

50

NC3

69

NC4

163

NCTEST

1

VREF

201

GND0

202

GND1

47

VSS1

133

VSS2

183

VSS3

77

VSS4

12

VSS5

48

VSS6

184

VSS7

78

VSS8

71

VSS9

72

VSS10

121

VSS11

122

VSS12

196

VSS13

193

VSS14

8

VSS15

24

VSS17

18

VSS16

162

VSS57

VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27

HIGH 9.0mm DDRII SDRAM SO-DIMM (200P)

VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56

DDR_SO-DIMM

DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

M_B_DQ0

5

DQ0

M_B_DQ1

7

DQ1

M_B_DQ2

17

DQ2

M_B_DQ3

19

DQ3

M_B_DQ4

4

DQ4

M_B_DQ5

6

DQ5

M_B_DQ6

14

DQ6

M_B_DQ7

16

DQ7

M_B_DQ8

23

DQ8

M_B_DQ9

25

DQ9

M_B_DQ10

35

M_B_DQ11

37

M_B_DQ12

20

M_B_DQ13

22

M_B_DQ14

36

M_B_DQ15

38

M_B_DQ16

43

M_B_DQ17

45

M_B_DQ18

55

M_B_DQ19

57

M_B_DQ20

44

M_B_DQ21

46

M_B_DQ22

56

M_B_DQ23

58

M_B_DQ24

61

M_B_DQ25

63

M_B_DQ26

73

M_B_DQ27

75

M_B_DQ28

62

M_B_DQ29

64

M_B_DQ30

74

M_B_DQ31

76

M_B_DQ32

123

M_B_DQ33

125

M_B_DQ34

135

M_B_DQ35

137

M_B_DQ36

124

M_B_DQ37

126

M_B_DQ38

134

M_B_DQ39

136

M_B_DQ40

141

M_B_DQ41

143

M_B_DQ42

151

M_B_DQ43

153

M_B_DQ44

140

M_B_DQ45

142

M_B_DQ46

152

M_B_DQ47

154

M_B_DQ48

157

M_B_DQ49

159

M_B_DQ50

173

M_B_DQ51

175

M_B_DQ52

158

M_B_DQ53

160

M_B_DQ54

174

M_B_DQ55

176

M_B_DQ56

179

M_B_DQ57

181

M_B_DQ58

189

M_B_DQ59

191

M_B_DQ60

180

M_B_DQ61

182

M_B_DQ62

192

M_B_DQ63

194 41

53 42 54 59 65 60 66 127 139 128 145 165 171 172 177 187 178 190 9 21 33 155 34 132 144 156 168 2 3 15 27 39 149 161 28 40 138 150

M_B_DQ[63:0] 8

2

10V, X7R, +/-10%

*

C0402

*

C0402

*

C0402

*

C0402

*

C0402

*

C0402

*

C0402

*

C0402

*

C0402

*

C0402

*

C0402

*

C0402

10V, X7R, +/-10%

*

C0402

*

C0402

*

C0402

*

C0402

*

C0402

*

C0402

*

C0402

*

C0402

*

C0402

*

C0402

*

C0402

*

C0402

*

C0402

*

C0402

1

VTT_MEM

RN67

BC5590.1uF

BC5590.1uF BC5600.1uF

BC5600.1uF

BC5610.1uF

BC5610.1uF BC5620.1uF

BC5620.1uF

BC5630.1uF

BC5630.1uF BC5640.1uF

BC5640.1uF

BC5650.1uF

BC5650.1uF BC5660.1uF

BC5660.1uF

BC5670.1uF

BC5670.1uF BC5680.1uF

BC5680.1uF

BC5690.1uF

BC5690.1uF BC5700.1uF

BC5700.1uF

BC5710.1uF

BC5710.1uF BC5720.1uF

BC5720.1uF

BC5730.1uF

BC5730.1uF BC5740.1uF

BC5740.1uF

BC5750.1uF

BC5750.1uF BC5760.1uF

BC5760.1uF

BC5770.1uF

BC5780.1uF

BC5780.1uF BC5790.1uF

BC5790.1uF

BC5840.1uF

BC5840.1uF BC5850.1uF

BC5850.1uF

BC5900.1uF

BC5900.1uF BC5910.1uF

BC5910.1uF

BC5920.1uF

1

*

3 5 7 8

RN68

1

*

3 5 7 8

RN69

1

*

3 5 7 8

RN70

1

*

3 5 7 8

RN71

1

*

3 5 7 8

RN72

1

*

3 5 7 8

RN73

1

*

3 5 7 8

RN74

1

*

3 5 7 8

RN75

1

*

3 5 7 8

R524 56

R0402 +/-5%

R525 56

R0402 +/-5%

RN76

1

*

3 5 7 8

RN77

1

*

3 5 7 8

RN78

1

*

3 5 7 8

R526 56

R0402 +/-5%

R527 56

R0402 +/-5%

56 8P4R0402+/-5%

2 4 6

M_A_A6

2

M_A_A7

4

M_A_A11

6

M_CKE1_RJ

M_CS3_RJ

M_ODT3

M_A_BSJ2

2

M_A_A12

4

M_A_A9

6

M_A_A8

2 4 6

M_CKE0_RJ

M_CS1_RJ

M_CKE2_RJ M_B_BSJ2 M_B_A12 M_B_A9

M_B_A8 M_B_A5 M_B_A3 M_B_A1

M_B_A10 M_B_BSJ0 M_B_WEJ M_B_CASJ

M_B_A6 M_B_A7 M_B_A11 M_CKE3_RJ

M_A_WEJ M_A_BSJ0 M_A_CASJ M_ODT1

M_A_A13 M_ODT0 M_CS0_RJ M_A_RASJ

M_B_BSJ1 M_B_A0 M_B_A2 M_B_A4

M_ODT2 M_B_A13 M_CS2_RJ M_B_RASJ

M_A_BSJ1 M_A_A0 M_A_A2 M_A_A4

M_A_A5 M_A_A3 M_A_A1 M_A_A10

A A

VDIMM

BC606

BC605

0.1uF

2.2uF

*

C0402

C0805

16V, Y5V, +80%/-20%

5

VDIMM

TC15

BC609

BC608

BC607

0.1uF

2.2uF

*

C0402

C0805

BC610

2.2uF

0.1uF

*

C0805

C0402

BC612

BC613

BC611

2.2uF

*

C0805

BC613

BC614

BC615

0.1uF

2.2uF

*

C0402

C0805

4

BC615

0.1uF

2.2uF

*

C0402

*

C0805

BC616

0.1uF

C0402

TC15

220uF

*

4V, +/-20%

ctdh19

2 1

10V, X7R, +/-10%

BC593

BC594

BC595

2.2uF

*

C0805

16V, Y5V, +80%/-20%

2.2uF

0.1uF

2.2uF

*

C0805

C0402

C0805

3

BC597

BC596

2.2uF

0.1uF

*

C0805

C0402

BC599

BC598

2.2uF

0.1uF

*

C0805

C0402

BC601

BC602

BC600

0.1uF

*

C0402

BC602

2.2uF

0.1uF

*

C0805

C0402

2

VDIMM

BC603

BC604

2.2uF

0.1uF

*

C0805

C0402

10V, X7R, +/-10%

Title

DDR2_SOCKET

Document Number Rev

Date: Sheet

Date: Sheet of

S09 MAINBOARD

1

TECHNOLOGY COPR.

of

11 45Tuesday, March 15, 2005

A

5

www.hocnghetructuyen.vn

4

3

2

1

BC249

33pF

C0603

21

*

50V, NPO, +/-5%

R186

2.2K

+/-5%

R0402

5V_CRT_S05V_S0

BC250

33pF

C0603

2D5V_S02D5V_S0

Q1

2N7002EPT

BC248

10nF

*

25V, X7R, +/-10%

C0402

R184

2.2K

+/-5%

R0402

G

Q2

VGA_CN1

17

5 15 10

4 14

9

3 13

8

2 12

7

1 11

6

16

DS

G

2N7002EPT

VGA15P

DS

DAT_DDC1_5

CLK_DDC1_5

5V @ ext. CRT side

D4

F1

*

C15

100pF

C0402

*

R172

3.3K

+/-5%

R0402

*

50V, NPO, +/-5%

F1210_1.1A

*

CRT I/F & CONNECTOR

D D

GMCH_RED7

GMCH_GREEN7

GMCH_BLUE7

Layout Note: Place these resistors close to the CRT-out connector

R178

R178 150

150

+/-5%

R0402

R179

R179 150

150

R0402

+/-5%

R180

R180 150

150

+/-5%

R0402

*

50V, NPO, +/-0.25pF

Layout Note:

C C

* Must be a ground return path between this ground and the ground on the VGA connector. Pi-filter & 150 Ohm pull-down resistors should be as close as to CRT

Ferrite bead impedance: 47ohm@100MHz

*

C9

3.3pF

C0402

Dummy

50V, NPO, +/-0.25pF

C10

3.3pF

C0402

Dummy

C11

3.3pF

C0402

Dummy

50V, NPO, +/-0.25pF

L6

21

FB L0603 47 Ohm

L7

21

FB L0603 47 Ohm

L8

21

FB L0603 47 Ohm

*

C12

3.3pF

C0402

Dummy

50V, NPO, +/-0.25pF

CRT_R

*

C13

3.3pF

C0402

Dummy

50V, NPO, +/-0.25pF

3

*

C14

3.3pF

C0402

Dummy

50V, NPO, +/-0.25pF

21

D5 BAV99D5BAV99

2D5V_S0

CRT_B

CRT_R

CRT_G

CLK_DDC1_5

JVGA_VS CRT_B

JVGA_HS CRT_G

DAT_DDC1_5 CRT_R

50V, NPO, +/-5%

CONN. RGB will hit 75 Ohm first, pi-filter, then CRT CONN.

Hsync & Vsync level shift

GMCH_HSYNC7

5

GMCH_VSYNC7

B B

2 4

3

1

U39

5V_S0

2 4

74HCT1G125

CRT_G

CRT_B

+/-5%

+/-5% +/-5%

+/-5%

JVGA_HS JVGA_VS

R181 0 R0402

16V, Y5V, +80%/-20%

R181 0 R0402 R183 0 R0402

R183 0 R0402

BC251

0.1uF

*

C0402

1

5

U38

HSYNC_5

74HCT1G125

3

VSYNC_5

21

D6 BAV99D6BAV99

3

21

D7 BAV99D7BAV99

3

B_GMCH_DDCDATA7

GMCH_DDCCLK7

D4

CH501H-40

R173

3.3K

+/-5%

R0402

C16

*

100pF

C0402

50V, NPO, +/-5%

DDC_CLK & DATA level shift

R185

2.2K

+/-5%

R0402

A A

TECHNOLOGY COPR.

5

Title

Document Number Rev

Date: Sheet

4

3

2

Date: Sheet

CRT

S09 MAINBOARD

1

TECHNOLOGY COPR.

A

of

12 45Monday, March 14, 2005

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12 45Monday, March 14, 2005

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12 45Monday, March 14, 2005

5

www.hocnghetructuyen.vn

4

3D3V_S0

3 5

U5

1 2

NC7SZ32U5NC7SZ32

R204

R204 100K

100K

+/-5%

R0402

WLANONLEDJ

WLANONLED

2

Q3

Q3 DTC144EUA

DTC144EUA

1 3

D D

LED

3D3V_S0 3D3V_S5 3D3V_S0 3D3V_S03D3V_S5 3D3V_S0

R214

R212

R211

R211 330

330

+/-5%

R0603

PWR_LED3

R212 330

330

+/-5%

R0603

12

LED_Blue

WLAN_LED1

CHG_LEDJ

330

+/-5%

R0603

Orange

MEDIA_LED1

CHG_LED2J

R215

R215 330

330

+/-5%

R0603

1

2

4 3

CHG_LED1

LED_Blue Yellow Orange

BLUE

CAPSJ

R213

R213 330

330

R223

330

+/-5%

C C

+/-5%

R0603

PWR_LEDRJ

12

PWR_LED1

LED_Blue

+/-5%

R0603

12

PWR_LED2

LED_Blue

WLANONLEDJ

R216

R216 330

330

+/-5%

R0603

12

CAP_LED1

LED_Blue

NUMJ

R205

R205 100K

100K

+/-5%

R0402

12

NUM_LED1

LED_Blue

4

R217

R217 330

330

+/-5%

R0603

802.11_LINK 29

802.11_ACT 29

LCD / INVERTER

CN17

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

31 32 33 34

EC_BLON30

MEDIA_LEDJ19

NUMJ30 CAPSJ30

CHG_LED2J30 CHG_LEDJ30 PWR_LED30

25 26

PAD1

27

PAD2

28

PAD3

29

PAD4

30

LVDS-CON30-LF

MEDIA_LEDJ

BRIGHTNESS_PWM_1 COVERUPCOVER_SWJ

PWR_LEDMEDIA_LEDJ

WLANONLEDJ

BC372

*

1nF

C0402

3

TP19TP19

1

BRIGHTNESS_PWM_1

EC_BLON

BC271

BC273

1nF

C0402

BC273

*

1nF

C0402

*

LCDVDD_S0

LDDC_CLK 7

LDDC_DATA 7 GMCH_TXAOUT0- 7 GMCH_TXAOUT0+ 7

GMCH_TXAOUT1- 7

GMCH_TXAOUT1+ 7 GMCH_TXAOUT2- 7

GMCH_TXAOUT2+ 7

GMCH_TXACLK- 7

GMCH_TXACLK+ 7

BC692

*

1nF

C0402

*

INVT_PWR

BC266

0.1uF

C0603

BC275

1nF

C0402

*

BC276

*

1nF

C0402

3D3V_S0

25V, Y5V, +80%/-20%

BC370

0.1uF

C0603

FB L0805 300 Ohm

BC265

1nF

*

C0402

Dummy

R208 0

R0402 +/-5%

R206 0

R0402 +/-5%

BC277

*

1nF

C0402

2 1

Dummy

*

2

LCDVDD_S0

BC283

10uF

*

C0805

FB9

BC264

10uF

*

25V, Y5V, +80%/-20%

C1210

PWM from KBC

BRIGHTNESS_PWM 30 LBKLT_CRTL 7

PWM from Alviso

16V, Y5V, +80%/-20%

BC269

0.1uF

*

C0402

BC278

BC267

*

1nF

C0402

BC284

0.1uF

C0402

DCBATOUT

1

3D3V_S5

BC285

0.1uF

*

C0402

TO ALARM BOARD

ALARM_J1

ANTI_THEFTR_LEDJ

8 7 6 5 4 3 2 1

WTB CONN_8P

9 10

25V, X7R, +/-10%

R20

R20 10K

10K

+/-5%

R0402

C0402 Dummy

BC528

10nF

*

C0402

Dummy

25V, X7R, +/-10%

ANTI_THEFT_ARMJ 30

BC529 10nF

*

B_KBC_SCL1 18,30 B_KBC_DAT1 18,30

3D3V_S5 3D3V_S0

BC527

10nF

*

C0402

Dummy

Pull High IN EC page

CVR1

NC

4

NC

123

Header_1X2

C17

*

1nF

50V, X7R, +/-10%

C0402

R218

R218 100

100

R0402

+/-5%

C18

0.22uF

*

16V, Y5V, +80%/-20%

C0603

COVER_SWJ

COVERUP 30

3D3V_S5

21

D18

D18 BAV99

BAV99

3

Dummy

B B

Green for Another Sku

A A

WLANONLEDJ

For Another SKU

MEDIA_LEDJ

5

R233

R233 330

330

+/-5%

R0603

Dummy

12

WLAN_LED2

LED_Green

Dummy

R224

R224 330

330

+/-5%

R0603

Dummy

12

MEDIA_LED2

LED_Green

Dummy

CHG_LEDJ

CHG_LED2J

12

Y

CHG_LED2

R226

R226 330

330

+/-5%

R0603

Dummy

34

G

Dummy

LED_Yellow Green

CAPSJ

R221

R221 330

330

+/-5%

R0603

Dummy

12

CAP_LED2

LED_Green

Dummy

NUMJ

3D3V_S03D3V_S03D3V_S53D3V_S0 3D3V_S0

Dummy

12

LED_Green

R225

R225 330

330

+/-5%

R0603

NUM_LED2

Dummy

MEDIA_LEDJ NUMJ CAPSJ CHG_LED2J CHG_LEDJ

4

WLANONLEDJ

*

Dummy

BC286

1nF

C0402

*

Dummy

BC274

1nF

C0402

*

Dummy

BC693

1nF

C0402

*

Dummy

BC371

1nF

C0402

*

Dummy

BC379

1nF

C0402

*

Dummy

BC268

C0402

SI3865_R2

R222

47K

+/-5%

R0402

LCDVDD_S0

1

*

Layout 40 mil

BC282

1uF

10V, Y5V, +80%/-20%

C0603

TECHNOLOGY COPR.

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13 45Monday, March 14, 2005

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13 45Monday, March 14, 2005

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13 45Monday, March 14, 2005

A

3D3V_S0

3D3V_S5

GMCH_LCDVDD_ON7

R971

R971 100K

100K

R0402

+/-5%

Q13

Q13 2N7002EPT

2N7002EPT

ANTI_THEFT_LED30

PWR_LEDRJ

DS

PWR_LED

G

1nF

3

*

R220 1K

R0402 +/-5%

3D3V_S5

G

BC380

1nF

C0402

DS

R972

R972 100K

100K

R0402

+/-5%

Q20

Q20 2N7002EPT

2N7002EPT

2

R219 100K

R0402 +/-5%

*

ANTI_THEFTR_LEDJ

BC280

1uF

C0603

*

SI3865_R1C1

BC281

0.1uF

16V, Y5V, +80%/-20%

C0402

BC279 5.6nF

C0603 50V, X7R, +/-10%

*

U6

Si3865DVU6Si3865DV

1

R2

2

D2

3

D2

6

R1/C1

5

ON/OFF

4

S2

Title

LCD/Inverter

Document Number Rev

S09 MAINBOARD

Date: Sheet

5

www.hocnghetructuyen.vn

RTC circuitry

3D3V_AUX_S5

D37

D D

R231

1K

+/-5%

R0402

RTC_J1

RTC_J1 Header_1X3

Header_1X3

C C

B B

1

BAT_D

2

BAT

12345

D37

BAT54C

3

R229 180K

R0402 +/-5%

R230 1M

R0402 +/-5%

RTC_SENSEJ 30

R625

R625 100K

100K

+/-5%

R0402

RTC_AUX_S5

C19

1uF

*

10V, Y5V, +80%/-20%

C0603

3D3V_S0

BC289

0.1uF

*

16V, Y5V, +80%/-20%

C0402

LAN_RSTSYNC24

ACZ_BITCLK26 ACZ_SYNC20,28

ACZ_RSTJ20,28

ACZ_SDATAOUT20,28

R_LAN_RXD024 R_LAN_RXD124

R_LAN_RXD224

4

BC287 4.7pF

C0402 50V, NPO, +/-0.25pF

*

41

R227

R227 10M

10M

+/-5%

R0402

X2

2 3

XTAL-32.768kHz

*

BC288 4.7pF

C0402 50V, NPO, +/-0.25pF

EEP_CS24 EEP_SK24 EEP_DOUT24

EEP_DIN24

R989 22R0402 +/-5%R989 22R0402 +/-5%

LAN_TXD024 LAN_TXD124 LAN_TXD224

R986 22R0402 +/-5%R986 22R0402 +/-5% R987 22R0402 +/-5%R987 22R0402 +/-5% R988 22R0402 +/-5%R988 22R0402 +/-5%

ACZ_BITCLK

R239 39 R0402 +/-5%R239 39 R0402 +/-5% R240 39 R0402 +/-5%R240 39 R0402 +/-5%

R242 39 R0402 +/-5%R242 39 R0402 +/-5%

LAN_CLK24

ACZ_SDATAIN026,28 ACZ_SDATAIN120

IDE_IORDY19 IDE_IRQ1419 IDE_DACKJ19 IDE_IOWJ19 IDE_IORJ19

ACZ_RSTJ_R

TP44TP44

ACZ_SDATAOUT_R

X1_RTC

X2_RTC RCT_RSTJ INTRUDERJ

LAN_CLK

LAN_RSTSYNC_R

R_LAN_RXD0 R_LAN_RXD1 R_LAN_RXD2

LAN_TXD0_R LAN_TXD1_R LAN_TXD2_R

ACZ_SYNC_R

1

AA2 AA3

AA5

D12

B12

D11

F13 F12 B11 E12

E11

C13 C12

C11

E13

C10

A10 F11

F10 B10

AC19

AE3 AD3

AG2

AF2 AD7

AC7 AF6

AG6

AC2 AC1

AG11

AF11

AF16 AB16 AB15 AC14 AE16

Y1 Y2

B9

C9

3

RTCX1 RTCX2

RTCRST# INTRUDER#

INTVRMEN

EE_CS EE_SHCLK EE_DOUT EE_DIN

LAN_CLK LAN_RSTSYNC LANRXD[0]

LANRXD[1] LANRXD[2]

LANTXD[0] LANTXD[1] LANTXD[2]

ACZ_BIT_CLK ACZ_SYNC

ACZ_RST# ACZ_SDIN[0]

ACZ_SDIN[1] ACZ_SDIN[2]

ACZ_SDO

SATALED# SATA[0]RXN

SATA[0]RXP SATA[0]TXN SATA[0]TXP

SATA[2]RXN SATA[2]RXP SATA[2]TXN SATA[2]TXP

SATA_CLKN SATA_CLKP

SATARBIAS# SATARBIAS

IORDY IDEIRQ DDACK# DIOW# DIOR#

U7A

LAD[0]/FWH[0] LAD[1]/FWH[1] LAD[2]/FWH[2] LAD[3]/FWH[3]

LPC

RTCLAN

LDRQ[0]#

LDRQ[1]#/GPI[41]

LFRAME#/FWH[4]

A20GATE

A20M# CPUSLP# DPRSLP#

DPSLP#

FERR#

CPU

CPUPWRGD/GPO[49]

IGNNE#

INIT3_3V#

STPCLK#

THRMTRIP#

DCS1#

DCS3#

SATA AC-97/AZALIA

IDE

DDREQ

ICH6-M

INIT#

INTR

RCIN#

NMI

SMI#

DA[0] DA[1] DA[2]

DD[0] DD[1] DD[2] DD[3] DD[4] DD[5] DD[6] DD[7] DD[8]

DD[9] DD[10] DD[11] DD[12] DD[13] DD[14] DD[15]

P2 N3 N5 N4

N6 P4

P3

AF22 AF23

AE27 AE24

AD27 AF24 AG25 AG26

AE22 AF27 AG24

AD23 AF25

AG27 AE26 AE23

AC16 AB17 AC17

AD16 AE17

AD14 AF15 AF14 AD12 AE14 AC11 AD11 AB11 AE13 AF13 AB12 AB13 AC13 AE15 AG15 AD13

AB14

B_LPC_LAD0 B_LPC_LAD1 B_LPC_LAD2 B_LPC_LAD3

LPC_LDRQ1J 28

B_LPC_LFRAMEJ 28,30

H_A20MJ 4 H_CPUSLPJ 4,6

H_DPRSLPJ H_DPSLPJ

H_FERR_R

H_PWRGD 4 H_IGNNEJ 4 H_INITJ 4

H_INTR 4

H_RCINJ_1

H_NMI 4 H_SMIJ 4

H_THERMTRIP_R

H_STPCLKJ 4

IDE_A0 19 IDE_A1 19 IDE_A2 19

IDE_CSJ0 19 IDE_CSJ1 19

IDE_D0 19 IDE_D1 19 IDE_D2 19 IDE_D3 19 IDE_D4 19 IDE_D5 19 IDE_D6 19 IDE_D7 19 IDE_D8 19 IDE_D9 19 IDE_D10 19 IDE_D11 19 IDE_D12 19 IDE_D13 19 IDE_D14 19 IDE_D15 19

IDE_DREQ 19

2

B_LPC_LAD0 28,30 B_LPC_LAD1 28,30 B_LPC_LAD2 28,30 B_LPC_LAD3 28,30

H_A20GATE_1

H_DPRSLPJ 4 H_DPSLPJ 4

R243

56

R0402

+/-5%

3D3V_S0

R232

R232 10K

10K

+/-5%

R0402

D21

21

H_DPSLPJ

H_A20GATE 30

H_RCINJ 30

CH501H-40

R236 56

R0402 +/-5%

3D3V_S0

R237

R237 10K

10K

+/-5%

R0402

D22

CH501H-40

Layout Note: R632 needs to placed within 2" of ICH6, R634 must be placed within 2" of R632 w/o stub.

1D05V_S0

R511

R511 56

56

+/-5%

R0402

Dummy

1

1D05V_S0

R241

R241 75

75

+/-5%

R0402

NO_STUFF

R234

R234 56

56

+/-5%

R0402

H_FERRJ 4

PM_THRMTRIPJ 4,7

A A

TECHNOLOGY COPR.

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14 45Tuesday, March 15, 2005

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14 45Tuesday, March 15, 2005

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14 45Tuesday, March 15, 2005

1

A

5

Title

ICH6(1 of 4)

Document Number Rev

S09 MAINBOARD

Date: Sheet

4

3

2

Date: Sheet

Lenovo Foxcon S09 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual