LENOVO FLEX 14 Schematics

A

1 1

B

C

D

E

Compal Confidential

E

L4C1 & EL451 (C340/S540-14)

2 2

D

IS M/B Schematic Document

I

ntel Whiskey Lake Processor with DDR4

M

X110 (23x23mm)

2018-10-18

3 3

L

A-H081P

R E V

4 4

A

B

0

：

. 3

S

ecurity Classification

I

ssued Date

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BYOR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BYOR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2

018/04/09 2019/04/09

C

ompal Secret Data

D

eciphered Date

D

C

ompal Electronics, Inc.

T

itle

Size Document Number Re v

C

ustom

Date : Sheet

ompal Electronics, Inc.

Cover Page

L

A-H081P

o

f

1 53Monday, October 22, 2018

f

1 53Monday, October 22, 2018

f

E

1 53Monday, October 22, 2018

0

.2

A

www.schematic-x.blogspot.com

NVIDIA N17S-G0 NVIDIA N17S-G2

1 1

S

540-14 Only

2 2

TDP:18W VRAM(GDDR5) X2 2GB

NGFF (Key M)

PCIE/SATA SSD 2242/2280 conn.

N

GFF (Key M)

PC

IE/SATA SSD

2242/2280 conn.

N

GFF (Key E)

W

LAN/BT

2230 conn.

e

DP Panel

F

HD LCD

HDMI Conn.

V

3 3

T

ype-C Conn.

U

SB3.1 Gen1

Bus

U

SB3.1 Gen1

CC/Vconn

5V Switch

M

ux/CC

RTS5448

U

SB3.1x1, Gen 1

I

2C_3VLP

EC

B

U

SB3 redriver

P

arade PS8713B

Parade PS8407A

PCIe x4 , Gen3 8Gb/s

PCIe x4 , Gen3 8Gb/s SATA , Gen3 6Gb/s

P

CIe x2 , Gen3 8Gb/s

SATA , Gen3 6Gb/s

PCIe x1 , Gen1 2.5Gb/s

U

SB2.0 x 1, 480Mb/s

e

DP x2 , HBR 2.7Gb/s

D

DI x4 , 2.9GT/s

U

SB2.0 x 1, 480Mb/s

USB3.1x1, Gen 1

C

I

ntel WHL/CML-U

1

5W

1

528pin BGA

DDR4 3200MHz

USB2.0 x1, 480Mb/s

USB3.1 x1, Gen1 5Gb/s

U

SB3.1 x1, Gen1 5Gb/s

U

SB2.0 x 1, 480Mb/s

U

SB2.0 x 1, 480Mb/s

U

SB2.0 x 1, 480Mb/s

S540-14 Only , use on-cell module

U

SB2.0 x 1, 480Mb/s

I

2C

C340-14 Only , use T-S module

P

CIe x1 , Gen1 2.5Gb/s

H

DA

I

2C (C340)

U

SB2.0 (S540)

SPI

D

CH-A SO-DIMM X1 CH-B memory down x4

USB Charger

TI SN1702001

U

SB3 redriver

P

arade PS8713B

USB3 redriver

P

arade PS8713B

F

ingerPrint

I

nt. Camera

T

ouch Panel

C

ard Reader

R

ealtek RTS5232S

A

udio Codec

C

X11880

T

ouchPad

S

PI ROM

1

6MB

USB2.0 x1, 480Mb/s

USB3.1 x1, Gen1 5Gb/s

S

DIO

HP

S

PK

DMIC

USB Conn. with AOU

U

SB Conn.

O

n Sub Board

O

n Sub Board

S

D Card Conn.

Combo Jack

I

nt. Speaker

Int. Array Mic *2

On Sub Board

E

L

PC

4 4

Int. KBD

K

H

all Sensor

L

ED

A

B

BC

E

NE KB9022

C

S

ecurity Classification

I

ssued Date

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZEDBY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE I NFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZEDBY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE I NFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZEDBY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE I NFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

C

ompal Secret Data

Deciphered Date

C

ompal Electronics, Inc.

T

itle

S

ize

D

Date: Sheetof

B

lock Diagram

D

lock Diagram

ocument Number Rev

L

A-H081P

2

E

2

53Monday, Octobe r 22, 201 8

0

.2

1

Voltage Rails

A

ddress

1

001 100x 98h

A

ddress

1

001 111x 9Eh

X

V

+3VS

X

V

+

3VS

+5VS

+3VS

+1.05VS_ VCCSTG

+VCC_COR E

+VCC_G T

+VCC_S A

+1.05VS_ VCCIO

+1.8VS

+0.6VS

O

X

XX

X

XXX

S

ODIMMNECP388BATT

X

V

+

3VS

XX

X

power plane

+5VALW

+3VALW

B+

A A

State

S

0

S3

S5 S4/AC

S

5 S4/ Battery only

S5 S4/AC & Battery don't exist

B B

E

C SM Bus1 address

D

evice

Smart Battery

P

CH SM Bus address

D

evice

D

DR_JDI MM1

T

ouch Pad

S

MBUS Control Table

C C

EC_SMB_CK1 EC_SMB_DA1 E

C_SMB_CK2 EC_SMB_DA2 EC_SMB_CK4 EC_SMB_DA4 SOC_SMBC LK SOC_SMBDAT A SOC_SML 0CLK SOC_SML0DA TA EC_SMB_CK2 EC_SMB_DA2

A

ddress

0

001 011x 16h

Address

1010 000x A0h

SOURCE

NECP38 8

+3VL

N

ECP388

+

3VS

NECP38 8

+3VS

PCH

+3VALW

PCH

+3VALW

P

CH

+

3VS

+1.8VAL W

+1.05VAL W

O

X

E

G

DGPU

+3VALW

V

+

3VS

X

V

+3VS

+1.2V

+2.5V

O

X

C SM Bus2 address

D

evice

N

CT7718W

t

hermal sensor 1001 101xb 21h

PU SM Bus address

D

evice

Internal thermal sensor

C

HARGER

VX

V

+

19V_VIN

X

X X X X X

X

XX

X

2

BOM Structure Table

Item

DIS Only Components DIS@ UMA Only Components UMA@ HDMI Logo 45@

Memory Down - DDP Package

Colay SATA/PCIE on M2 SSD_D ET@

ESD Cate gory ESD@ RF Categor y RF@ Test Point TP@

Keyboard BackLight

Project select

OneKey Batt ery

Intel CNVi

GPU select

Conne ctors ME@

G

T

-

T

P

CH

X

V

+

3VS

V

X

+

3VS

X

SENSOR

X

V

+

3VS

X

HM

se

nsor

X

V

+

3VS

X

BOM Structure

TS@Touch Sc reen SDP@Memory Down - SDP Package DDP@ GC6@GPU GC6 Com ponents NOGC6 @Un-Mount GPU GC6 Compon ents

EMI@EMI Cate gory

KBL@ NOKBL @ S540@ S340@ C340@ ONEKE Y@ NON_ON EKEY @ CNVi@ NONCN Vi@ N17S_ G0@ N17S_ G2@ N16S@ N17S@

3

Item

X4E

On Bo ard RAM no On Boar d RAM On Board RAM X76 Resistors X76RA M@ DRAM (Hynix 4GB) DRAM (Micron 4GB) DRAM (Samsung 4GB)

VRAM (Hynix 4GB)

VRAM (Samsung 4GB)

VRAM (Micron 4GB)

C

PU

U

C1

I3_8145U@

QQK9 W0 2.1G BGA

SA0000C6R20

U

C1

I3_8145U_R3@

S

RD1V W0 2.1G

SA0000C6R30

D

RAM S540

Z

ZZ

S4G_S540@

K

4A8G165WC-BCTD

X7680638L05

DRAM C340

Z

ZZ3

S4G_C340@

K4A8G165WC-BCTD

X7680538L06

BOM Structure

X4ES5 40@ X4EC3 40@ MD@ NO_MD @

H4G_S 540@ M4G_S 540@ S4G_S 540@

H4G_V RAM@ H4G@ H4G_R 1@ H4G_R 3@ S4G_V RAM@ S4G@ S4G_R 1@ S4G_R 3@ M4G_V RAM@ M4G@ M4G_R 1@ M4G_R 3@

U

C1

I5_8265U@

QQTG W0 1.6G BGA

SA0000C6Q20

U

C1

I5_8265U_R3@

S

REJQ W0 1.6G

SA0000C6Q30

Z

ZZ

H4G_S540@

H

5AN8G6NCJR-VKC

X7680638L04

Z

ZZ2

H4G_C340@

H5AN8G6NCJR-VKC

X7680538L04

U

C1

I7_8565U@

QQK6 W0 1.8G BGA

SA0000C6P20

U

C1

I7_8565U_R3@

S

REJP W0 1.8G

SA0000C6P30

Z

ZZ

M4G_S540@

M

T40A512M16LY-075:E

X7680638L06

Z

ZZ1

M4G_C340@

MT40A512M16LY-075:E

X7680538L05

4

USB 2.0 Port Table

External USB PortPort

1

USB2/3 Port (IO - 1)

2

USB2/3 Port (IO - 2)

3

USB2/3 Port (Type-C)

4

Touch Screen

5 6

Camera

7

Fingrt Print

8 9 10

NGFF WLAN+BT

USB 3.0 Port Table PCIE Port Table

P

ort

1

USB2/3 Port (IO - 1)

2

USB2/3 Port (IO - 2)

3

U

SB2/3 Port (Type-C)

4 5 6

S

ATA Port Table

Port

0 1A

S

SD1

1B 2

SSD2

P

CB

Z

ZZ

PCB@

P

CB 2GA LA-H081P REV0 M/B 4

D

A8001H4000

X

4E X4E_S540_14 X4E_C340_14

Z

ZZ

X4ES540@

X

4E_S540_14

X

4EAF638L51

P

ort

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

GPU

U

N

V1

17S_G0@

N

17S-G0-A1

SA0000CC900

V

RAM S540

Z

ZZ

VH4G_S540@

H

5GC8H24AJR-R2C

X7680638L01

VRAM C340

Z

ZZ

VH4G_C340@

H

5GC8H24AJR-R2C

X7680538L01

Z

ZZ

VM4G_S540@

M

T51J256M32HF-80:B

X7680638L03

Z

ZZ

VM4G_C340@

M

T51J256M32HF-80:B

X7680538L03

U

V1

N

17S-G2-A1

SA0000CCB00

N

17S_G2@

Lane

0 0 1 2 3 3 2 1 0 0 0 1 0

5

DGPU

SSD1

CardReader NGFF WLAN+BT

SSD2

Z

ZZ

X4EC340@

X

4E_C340_14

X

4EAF638L01

STATE

Full ON

S

1(Power On Suspend)

D D

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SIGNAL

1

SLP_S1 #

LOW

HIGH HIGH HIGH

LOW

LOW LOW LOW

LOWLOW

SLP_S4 #SLP_S3 # +V+VAL WSLP_S5 # Clock+VS

O

HIGH

NONON

ON

OFF

LOWLOW

ON

OFF

ON

OFF

HIGHHIGHHIGH

HIGH

ONON

LOW

OFF

S

ecurity Classification

I

ssued Date

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROP ERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R& D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R& D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. N EITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. N EITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. N EITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAYB E USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAYB E USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

3

MAYB E USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

018/04/09 2019/04/09

C

ompal Secret Data

Deciphered Date

4

C

ompal Electronics, Inc.

T

S

C

ustom

Date : Sheet

ompal Electronics, Inc.

itle

N

otes List

ize

D

ocument Numb er Re v

L

A-H081P

5

0

o

f

3 53Monday, October 22, 2018

f

3 53Monday, October 22, 2018

f

3 53Monday, October 22, 2018

.2

5

4

3

2

1

-PowerMap_KBL_DDR4_Volume_NON CS]

B+

D D

C C

B B

A A

S

ecurity Classification

I

ssued Date

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENTEXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZED BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

C

ompal Secret Data

2

018/04/09 2019/04/09

Deciphered Date

C

ompal Electronics, Inc.

Tit

T

le

itle

Power MAP

Size Document Number Rev

L

Date: Sheetof

A-C071P

4 53Monday, October 22, 2018

1

4 53Monday, October 22, 2018

0

.2

5

4

3

2

1

G3->S0 S0->S3 ->S0

+3VL_RTC

SOC_RTCRST#

B+

D D

+3VLP/+5V LP

EC_ON

+5VALW/+3VALW/+3VALW _DSW

PM_BATLOW#

tPCH01_Min : 9 ms

tPCH04_Min : 9 ms

Pull-up to DSW well if not implemented.

/DS3 DS3S0/

PCH_PWR_EN (SLP_SUS#)

+3V_PRIM

+1.8V_PRIM

EXT_PWR_GATE#

+1.0V_MPHYPLL

+1.0V_PRIM_CORE

+1.0V_PRIM

tPCH06_Min : 200 us

SUSACK#

PCH_DPWROK

E

C_RSMRST#

C C

A

C_PRESENT

tPCH34_Max : 20 ms

tPCH02_Min : 10 ms

tPCH03_Min : 10 ms

tPLT02_Min : 0 ms Max : 90 ms

ON/OFF

P

BTN_OUT#

P

M_SLP_S5#

Minimum duration of PWRBTN# assertion = 16mS. PWRBTN# can assert before or after RSMRST#

ESPI_RST#

If EXT_PWR_GATE# Toffmin is too small, Pwr gate may choose to completely ignore it

tPCH43_Min : 95 ms

tPCH18_Min : 90 us

PM_SLP_S4#

SYSON

+1.0V_VCCST/+1.0V_VCCSFR

+1.35V_VDDQ/+1.35V_VCCSFR_OC

PM_SLP_S3#

S

USP#

+1.0VS_VCCSTG

+1.0VS_VCCIO

B B

+5VS/+3VS/+1.5VS /+1.05VS

E

C_VCCST_PG

VR_ON

tCPU04 Min : 100 ns

tCPU10 Min : 1 ms

T <=10msec

T = 10msec

tCPU19 Max : 100 ns

tCPU18 Max : 35 us

+VCC_SA

+

VCC_CORE

+

VCC_GT

VR_PWRGD

PCH_PWROK

tCPU16 Min : 0 ns

tCPU09 Min : 1 ms

H_CPUPWRGD

SYS_PWROK

A A

SUS_STAT#

SOC_PLTRST#

S0->S5

+3VL_RTC

SOC_RTCRST#

B+

+3VLP/+5V LP

EC_ON

+5VALW/+3VALW/+3VALW _DSW

PM_BATLOW#

PCH_PWR_EN (SLP_SUS#)

+3V_PRIM

+

1.8V_PRIM

EXT_PWR_GATE#

+1.0V_MPHYPLL

+1.0V_PRIM_CORE

+1.0V_PRIM

SUSACK#

PCH_DPWROK

E

C_RSMRST#

A

C_PRESENT

ON/OFF

P

BTN_OUT#

PM_SLP_S5#

ESPI_RST#

PM_SLP_S4#

SYSON

+

1.0V_VCCST/+1.0V_VCCSFR

+1.35V_VDDQ/+1.35V_VCCSFR_OC

PM_SLP_S3#

S

USP#

+1.0VS_VCCSTG

+1.0VS_VCCIO

+5VS/+3VS/+1.5VS /+1.05VS

E

C_VCCST_PG

VR_ON

SM_PG_CTRL

+0.675VS_VTT

+VCC_SA

+VCC_CORE

+

VCC_GT

VR_PWRGD

PCH_PWROK

H_CPUPWRGD

SYS_PWROK

SUS_STAT#

SOC_PLTRST#

S

ecurity Classification

I

ssued Date

T

HIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF T HE COMPET ENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF T HE COMPET ENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED T O ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED T O ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECT RONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED T O ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECT RONICS, INC.

2

C

ompal Secret Data

2

ompal Secret Data

018/04/09 2019/04/09

D

eciphered Date

C

ompal Electronics, Inc.

T

itle

Power Sequence

Size Document Number Rev

Date: Sheetof

Power Sequence

L

A-H081P

1

5 53Monday, October 2 2, 2018

0

.2

A

1 1

<

Compensation PU For eDP >

+

1.05VS_VCCIO

2 2

R

C2

T

race width=20 mils, Spacing=25mil, Max leng th=600mils

1 2

E

DP_COMP

24.9_0201_1 %

B

H

DMI DDC (Port 2)

<HDMI>

C

UC1A

AL5

DDI1_TXN_0

AL6

DDI1_TXP_0

AJ5

DDI1_TXN_1

AJ6

DDI1_TXP_1

AF6

DDI1_TXN_2

AF5

DDI1_TXP_2

AE5

DDI1_TXN_3

AE6

DDI1_TXP_3

CPU_DP2_N 0[29] CPU_DP2_P0[29] CPU_DP2_N 1[29] CPU_DP2_P1[29] CPU_DP2_N 2[29] CPU_DP2_P2[29] CPU_DP2_N 3[29] CPU_DP2_P3[29]

E

DP_COMP

C

PU_DP2_CT RL_CLK[29]

C

PU_DP2_CT RL_DATA[29]

T

S_I2C_RST#[28]

AC4

DDI2_TXN_0

AC3

DDI2_TXP_0

AC1

DDI2_TXN_1

AC2

DDI2_TXP_1

AE4

DDI2_TXN_2

AE3

DDI2_TXP_2

AE1

DDI2_TXN_3

AE2

DDI2_TXP_3

AM6

D

ISP_RCOMP

CC8

G

PP_E18/DPPB_CTRLCLK/CNV_BT_HOST_WAKE#

CC9

G

PP_E19/DPPB_CTRLDATA

CH4

G

PP_E20/DPPC_CTRLCLK

CH3

G

PP_E21/DPPC_CTRLDATA

CP4

G

PP_E22/DPPD_CTRLCLK

CN4

G

PP_E23/DPPD_CTRLDATA

CR26

G

PP_H16/DDPF_CTRLCLK

CP26

G

PP_H17/DDPF_CTRLDATA

CFLU-43E_BGA15 28

@

GPP_E13/DDPB_HPD0/DISP_MISC0 G

PP_E14/DDPC_HPD1/DISP_MISC1

G

PP_E15/DPPD_HPD2/DISP_MISC2

G

PP_E16/DPPE_HPD3/DISP_MISC3

G

PP_E17/EDP_HPD/DISP_MISC4

1

of 20

EDP_TXN_0 EDP_TXP_0 EDP_TXN_1 EDP_TXP_1 EDP_TXN_2 EDP_TXP_2 EDP_TXN_3 EDP_TXP_3

EDP_AUX_N EDP_AUX_P

DISP_UTILS

DDI1_AUX_N DDI1_AUX_P DDI2_AUX_N DDI2_AUX_P DDI3_AUX_N DDI3_AUX_P

E

DP_BKLTEN

E

DP_VDDEN

E

DP_BKLTCTL

AG4 AG3 AG2 AG1 AJ4 AJ3 AJ2 AJ1

AH4 AH3

AM7

AC7 AC6 AD4 AD3 AG7 AG6

CN6 CM6 CP7 CP6 CM7

CK11 CG11 CH11

D

EDP_TXN0 [28] EDP_TXP0 [28] EDP_TXN1 [28] EDP_TXP1 [28] EDP_TXN2 [28] EDP_TXP2 [28] EDP_TXN3 [28] EDP_TXP3 [28]

EDP_AUXN [28 ] EDP_AUXP [28]

C

PU_DP2_HPD [29]

E

C_SCI# [33]

E

DP_HPD [28]

E

NBKL [33]

P

CH_ENVDD [28]

I

NVPWM [28]

<eDP>

F

rom HDMI

From eDP

EC_SCI#

E

1 2

RC1 10K_0201_5 %

+3VS

+

1.05VS_VCCIO

12

I

f routed MS, PECI requires 18 mils spacing to other signals

R

C3

1

K_0201_5%

H

+

1.05V_VCCST

H

_THERMTR IP#

3 3

4 4

1 2

R

C8

R

C10 49.9_0402_1 %

A

1

K_0201_5%

@

12

C

ATERR#

_PROCHOT#[33]

B

1 2

R

C4 499_0402_ 1%

R R R

R

12

C11 49.9_0402_1 %

12

C12 49.9_0402_1 %

12

C14 49.9_0402_1 %@

12

C15 49.9_0402_1 %@

H

_PECI[33]

C

ATERR#

H

_PECI

H

_PROCHOT#_ R

H

_THERMTR IP#

C

PU_POPIRCOMP

P

CH_OPIRCOMP

E

DRAM_OPIO_RCOMP

E

OPIO_RCOMP

U

C1D

AA4

C

ATERR#

AR1

P

ECI

Y4

P

ROCHOT#

BJ1

T

HRMTRIP#

U1

B

PM#_0

U2

B

PM#_1

U3

B

PM#_2

U4

B

PM#_3

CE9

G

PP_E3/CPU_GP0

CN3

G

PP_E7/CPU_GP1

CB34

G

PP_B3/CPU_GP2

CC35

G

PP_B4/CPU_GP3

BP27

P

ROC_POPIRCOMP

BW25

P

CH_OPIRCOMP

L5

O

PCE_RCOMP

N5

O

PC_RCOMP

CFLU-43E_BGA15 28

@

S

ecurity Classification

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

I

ssued Date

4

of 20

P

ROC_TCK

P

ROC_TDI

P

ROC_TDO

P

ROC_TMS

P

ROC_TRST#

P

CH_TCK

P

CH_TDI

P

CH_TDO

P

CH_TMS

P

CH_TRST#

P

CH_JTAGX

P

ROC_PREQ#

P

ROC_PRDY#

< Test Point for CMC Debug >

C

PU_XDP_TCK0

T6

S

OC_XDP_TDI

U6

S

OC_XDP_TDO

Y5

S

OC_XDP_TMS

T5

S

OC_XDP_TRST #

AB6

P

CH_JTAG_TCK 1

W6

S

OC_XDP_TDI

U5

S

OC_XDP_TDO

W5

S

OC_XDP_TMS

P5

S

OC_XDP_TRST #

Y6

C

PU_XDP_TCK0

P6

W2 W1

C

2

018/04/09 2019/04/09

C

T

2408TP@

T

2409TP@

T

2410TP@

T

2411TP@

T

2412TP@

T

2413TP@

T1T

P@

T2T

P@

ompal Secret Data

D

eciphered Date

D

Compal Electronics, Inc.

T

Size Document Number Re v

Date : Sheet

Compal Electronics, Inc.

itle

WHL-U(1/12)DDI,EDP,MISC,CMC

C

ustom

LA-H081P

E

o

f

6 53Monday, October 22, 2018

f

6 53Monday, October 22, 2018

f

6 53Monday, October 22, 2018

0

.2

5

4

3

2

1

Non-Interleaved Memory

D D

DDR_A_D[0..15][18]

D

DR_A_D[32..47][18]

C C

D

DR_B_D[0..15][19]

D

DR_B_D[32..47][19]

B B

A A

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 D

DR_A_D11

D

DR_A_D12

D

DR_A_D13

D

DR_A_D14

D

DR_A_D15

D

DR_A_D32

D

DR_A_D33

D

DR_A_D34

D

DR_A_D35

D

DR_A_D36

D

DR_A_D37

D

DR_A_D38

D

DR_A_D39

D

DR_A_D40

D

DR_A_D41

D

DR_A_D42

D

DR_A_D43

D

DR_A_D44

D

DR_A_D45

D

DR_A_D46

D

DR_A_D47

D

DR_B_D0

D

DR_B_D1

D

DR_B_D2

D

DR_B_D3

D

DR_B_D4

D

DR_B_D5

D

DR_B_D6

D

DR_B_D7

D

DR_B_D8

D

DR_B_D9

D

DR_B_D10

D

DR_B_D11

D

DR_B_D12

D

DR_B_D13

D

DR_B_D14

D

DR_B_D15

D

DR_B_D32

D

DR_B_D33

D

DR_B_D34

D

DR_B_D35

D

DR_B_D36

D

DR_B_D37

D

DR_B_D38

D

DR_B_D39

D

DR_B_D40

D

DR_B_D41

D

DR_B_D42

D

DR_B_D43

D

DR_B_D44

D

DR_B_D45

D

DR_B_D46

D

DR_B_D47

<

For ODT & VTT Power Control >

DDR_VTT_CNTL to DDR VTT supplied ramped <35u S (tCPU 18)

D

DR_PG_CTRL

UC1B

A26

DDR0_DQ_0/DDR0_DQ_0

D26

DDR0_DQ_1/DDR0_DQ_1

D28

DDR0_DQ_2/DDR0_DQ_2

C28

DDR0_DQ_3/DDR0_DQ_3

B26

DDR0_DQ_4/DDR0_DQ_4

C26

DDR0_DQ_5/DDR0_DQ_5

B28

DDR0_DQ_6/DDR0_DQ_6

A28

DDR0_DQ_7/DDR0_DQ_7

B30

DDR0_DQ_8/DDR0_DQ_8

D30

DDR0_DQ_9/DDR0_DQ_9

B33

D

DR0_DQ_10/DDR0_DQ_10

D32

D

DR0_DQ_11/DDR0_DQ_11

A30

D

DR0_DQ_12/DDR0_DQ_12

C30

D

DR0_DQ_13/DDR0_DQ_13

B32

D

DR0_DQ_14/DDR0_DQ_14

C32

D

DR0_DQ_15/DDR0_DQ_15

H37

D

DR0_DQ_16/DDR0_DQ_32

H34

D

DR0_DQ_17/DDR0_DQ_33

K34

D

DR0_DQ_18/DDR0_DQ_34

K35

D

DR0_DQ_19/DDR0_DQ_35

H36

D

DR0_DQ_20/DDR0_DQ_36

H35

D

DR0_DQ_21/DDR0_DQ_37

K36

D

DR0_DQ_22/DDR0_DQ_38

K37

D

DR0_DQ_23/DDR0_DQ_39

N36

D

DR0_DQ_24/DDR0_DQ_40

N34

D

DR0_DQ_25/DDR0_DQ_41

R37

D

DR0_DQ_26/DDR0_DQ_42

R34

D

DR0_DQ_27/DDR0_DQ_43

N37

D

DR0_DQ_28/DDR0_DQ_44

N35

D

DR0_DQ_29/DDR0_DQ_45

R36

D

DR0_DQ_30/DDR0_DQ_46

R35

D

DR0_DQ_31/DDR0_DQ_47

AN35

D

DR0_DQ_32/DDR1_DQ_0

AN34

D

DR0_DQ_33/DDR1_DQ_1

AR35

D

DR0_DQ_34/DDR1_DQ_2

AR34

D

DR0_DQ_35/DDR1_DQ_3

AN37

D

DR0_DQ_36/DDR1_DQ_4

AN36

D

DR0_DQ_37/DDR1_DQ_5

AR36

D

DR0_DQ_38/DDR1_DQ_6

AR37

D

DR0_DQ_39/DDR1_DQ_7

AU35

D

DR0_DQ_40/DDR1_DQ_8

AU34

D

DR0_DQ_41/DDR1_DQ_9

AW35

D

DR0_DQ_42/DDR1_DQ_10

AW34

D

DR0_DQ_43/DDR1_DQ_11

AU37

D

DR0_DQ_44/DDR1_DQ_12

AU36

D

DR0_DQ_45/DDR1_DQ_13

AW36

D

DR0_DQ_46/DDR1_DQ_14

AW37

D

DR0_DQ_47/DDR1_DQ_15

BA35

D

DR0_DQ_48/DDR1_DQ_32

BA34

D

DR0_DQ_49/DDR1_DQ_33

BC35

D

DR0_DQ_50/DDR1_DQ_34

BC34

D

DR0_DQ_51/DDR1_DQ_35

BA37

D

DR0_DQ_52/DDR1_DQ_36

BA36

D

DR0_DQ_53/DDR1_DQ_37

BC36

D

DR0_DQ_54/DDR1_DQ_38

BC37

D

DR0_DQ_55/DDR1_DQ_39

BE35

D

DR0_DQ_56/DDR1_DQ_40

BE34

D

DR0_DQ_57/DDR1_DQ_41

BG35

D

DR0_DQ_58/DDR1_DQ_42

BG34

D

DR0_DQ_59/DDR1_DQ_43

BE37

D

DR0_DQ_60/DDR1_DQ_44

BE36

D

DR0_DQ_61/DDR1_DQ_45

BG36

D

DR0_DQ_62/DDR1_DQ_46

BG37

D

DR0_DQ_63/DDR1_DQ_47

CFLU-43E_BGA1528

@

U

C11

1

N

C

2

A

3

G

ND

74AUP1G07GW_TSSOP5

SA00005U600

DDR_A_CLK#0

V32

DDR0_CKN_0/DDR0_CKN_0 DDR0_CKP_0/DDR0_CKP_0 DDR0_CKN_1/DDR0_CKN_1 DDR0_CKP_1/DDR0_CKP_1

DDR0_CKE_0/DDR0_CKE_0 DDR0_CKE_1/DDR0_CKE_1

DDR0_CKE_2/NC DDR0_CKE_3/NC

D

DR0_CS#_0/DDR0_CS#_0

D

DR0_CS#_1/DDR0_CS#_1

D

DR0_ODT_0/DDR0_ODT_0

N

C/DDR0_ODT_1

D

DR0_CAB_9/DDR0_MA_0

D

DR0_CAB_8/DDR0_MA_1

D

DR0_CAB_5/DDR0_MA_2

N

C/DDR0_MA_3

N

C/DDR0_MA_4

D

DR0_CAA_0/DDR0_MA_5

D

DR0_CAA_2/DDR0_MA_6

D

DR0_CAA_4/DDR0_MA_7

D

DR0_CAA_3/DDR0_MA_8

D

DR0_CAA_1/DDR0_MA_9

D

DR0_CAB_7/DDR0_MA_10

D

DR0_CAA_7/DDR0_MA_11

D

DR0_CAA_6/DDR0_MA_12

D

DR0_CAB_0/DDR0_MA_13

D

DR0_CAB_2/DDR0_MA_14

D

DR0_CAB_1/DDR0_MA_15

D

DR0_CAB_3/DDR0_MA_16

D

DR0_CAB_4/DDR0_BA_0

D

DR0_CAB_6/DDR0_BA_1

D

DR0_CAA_5/DDR0_BG_0

D

DR0_CAA_8/DDR0_ACT#

D

DR0_CAA_9/DDR0_BG_1

D

DR0_DQSN_0/DDR0_DQSN_0

D

DR0_DQSP_0/DDR0_DQSP_0

D

DR0_DQSN_1/DDR0_DQSN_1

D

DR0_DQSP_1/DDR0_DQSP_1

D

DR0_DQSN_2/DDR0_DQSN_4

D

DR0_DQSP_2/DDR0_DQSP_4

D

DR0_DQSN_3/DDR0_DQSN_5

D

DR0_DQSP_3/DDR0_DQSP_5

D

DR0_DQSN_4/DDR1_DQSN_0

D

DR0_DQSP_4/DDR1_DQSP_0

D

DR0_DQSN_5/DDR1_DQSN_1

D

DR0_DQSP_5/DDR1_DQSP_1

D

DR0_DQSN_6/DDR1_DQSN_4

D

DR0_DQSP_6/DDR1_DQSP_4

D

DR0_DQSN_7/DDR1_DQSN_5

D

DR0_DQSP_7/DDR1_DQSP_5

N

C/DDR0_ALERT#

N

C/DDR0_PAR

D

DR_VREF_CA

D

DR0_VREF_DQ_0

D

DR0_VREF_DQ_1

D

DR1_VREF_DQ

D

DR_VTT_CNTL

2

of 20

1

C

C1

0.1U_0201_10V6K

@

2

+

3VS

12

R

C21

1

00K_0201_5%

+

1.2V

5

V

CC

4

Y

DDR_A_CLK0

V31

DDR_A_CLK#1

T32

DDR_A_CLK1

T31

DDR_A_CKE0

U36

DDR_A_CKE1

U37

U34

U35

D

DR_A_CS#0

AE32

D

DR_A_CS#1

AF32

D

DR_A_ODT0

AE31

D

DR_A_ODT1

AF31

D

DR_A_MA0

AC37

D

DR_A_MA1

AC36

D

DR_A_MA2

AC34

D

DR_A_MA3

AC35

D

DR_A_MA4

AA35

D

DR_A_MA5

AB35

D

DR_A_MA6

AA37

D

DR_A_MA7

AA36

D

DR_A_MA8

AB34

D

DR_A_MA9

W36

D

DR_A_MA10

Y31

D

DR_A_MA11

W34

D

DR_A_MA12

AA34

D

DR_A_MA13

AC32

D

DR_A_MA14

AC31

D

DR_A_MA15

AB32

D

DR_A_MA16

Y32

D

DR_A_BA0

W32

D

DR_A_BA1

AB31

D

DR_A_BG0

V34

D

DR_A_ACT#

V35

D

DR_A_BG1

W35

D

DR_A_DQS#0

C27

D

DR_A_DQS0

D27

D

DR_A_DQS#1

D31

D

DR_A_DQS1

C31

D

DR_A_DQS#4

J35

D

DR_A_DQS4

J34

D

DR_A_DQS#5

P34

D

DR_A_DQS5

P35

D

DR_B_DQS#0

AP35

D

DR_B_DQS0

AP34

D

DR_B_DQS#1

AV34

D

DR_B_DQS1

AV35

D

DR_B_DQS#4

BB35

D

DR_B_DQS4

BB34

D

DR_B_DQS#5

BF34

D

DR_B_DQS5

BF35

D

DR_A_ALERT#

W37

D

DR_A_PARITY

W31

+

0.6V_A_VREFCA

F36

D35

D37

+

0.6V_B_VREFDQ

E36

D

DR_PG_CTRL

C35

D

DR_VTT_PG_CTRL [44]

DDR_A_CLK#0 [18] DDR_A_CLK0 [18]

T3TP@ T4TP@

DDR_A_CKE0 [18,20]

T6TP@

D

DR_A_CS#0 [18,20]

T

5TP@

D

DR_A_ODT0 [18,20]

T

7TP@

D

DR_A_MA0 [18,20]

D

DR_A_MA1 [18,20]

D

DR_A_MA2 [18,20]

D

DR_A_MA3 [18,20]

D

DR_A_MA4 [18,20]

D

DR_A_MA5 [18,20]

D

DR_A_MA6 [18,20]

D

DR_A_MA7 [18,20]

D

DR_A_MA8 [18,20]

D

DR_A_MA9 [18,20]

D

DR_A_MA10 [18,20]

D

DR_A_MA11 [18,20]

D

DR_A_MA12 [18,20]

D

DR_A_MA13 [18,20]

D

DR_A_MA14 [18,20]

D

DR_A_MA15 [18,20]

D

DR_A_MA16 [18,20]

D

DR_A_BA0 [18,20]

D

DR_A_BA1 [18,20]

D

DR_A_BG0 [18,20]

D

DR_A_ACT# [18,20]

D

DR_A_BG1 [18]

D

DR_A_DQS#0 [18]

D

DR_A_DQS0 [18]

D

DR_A_DQS#1 [18]

D

DR_A_DQS1 [18]

D

DR_A_DQS#4 [18]

D

DR_A_DQS4 [18]

D

DR_A_DQS#5 [18]

D

DR_A_DQS5 [18]

D

DR_B_DQS#0 [19]

D

DR_B_DQS0 [19]

D

DR_B_DQS#1 [19]

D

DR_B_DQS1 [19]

D

DR_B_DQS#4 [19]

D

DR_B_DQS4 [19]

D

DR_B_DQS#5 [19]

D

DR_B_DQS5 [19]

D

DR_A_ALERT# [18]

D

DR_A_PARITY [18,20]

+

0.6V_A_VREFCA [18]

+

0.6V_B_VREFDQ [19]

T

race width/Spacing >= 20mils

DDR_A_D[16..31][18]

D

DR_A_D[48..63][18]

D

DR_B_D[16..31][19]

D

DR_B_D[48..63][19]

DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 D

DR_A_D28

D

DR_A_D29

D

DR_A_D30

D

DR_A_D31

D

DR_A_D48

D

DR_A_D49

D

DR_A_D50

D

DR_A_D51

D

DR_A_D52

D

DR_A_D53

D

DR_A_D54

D

DR_A_D55

D

DR_A_D56

D

DR_A_D57

D

DR_A_D58

D

DR_A_D59

D

DR_A_D60

D

DR_A_D61

D

DR_A_D62

D

DR_A_D63

D

DR_B_D16

D

DR_B_D17

D

DR_B_D18

D

DR_B_D19

D

DR_B_D20

D

DR_B_D21

D

DR_B_D22

D

DR_B_D23

D

DR_B_D24

D

DR_B_D25

D

DR_B_D26

D

DR_B_D27

D

DR_B_D28

D

DR_B_D29

D

DR_B_D30

D

DR_B_D31

D

DR_B_D48

D

DR_B_D49

D

DR_B_D50

D

DR_B_D51

D

DR_B_D52

D

DR_B_D53

D

DR_B_D54

D

DR_B_D55

D

DR_B_D56

D

DR_B_D57

D

DR_B_D58

D

DR_B_D59

D

DR_B_D60

D

DR_B_D61

D

DR_B_D62

D

DR_B_D63

UC1C

J22

DDR1_DQ_0/DDR0_DQ_16

H25

DDR1_DQ_1/DDR0_DQ_17

G22

DDR1_DQ_2/DDR0_DQ_18

H22

DDR1_DQ_3/DDR0_DQ_19

F25

DDR1_DQ_4/DDR0_DQ_20

J25

DDR1_DQ_5/DDR0_DQ_21

G25

DDR1_DQ_6/DDR0_DQ_22

F22

DDR1_DQ_7/DDR0_DQ_23

D22

DDR1_DQ_8/DDR0_DQ_24

C22

DDR1_DQ_9/DDR0_DQ_25

C24

DDR1_DQ_10/DDR0_DQ_26

D24

D

DR1_DQ_11/DDR0_DQ_27

A22

D

DR1_DQ_12/DDR0_DQ_28

B22

D

DR1_DQ_13/DDR0_DQ_29

A24

D

DR1_DQ_14/DDR0_DQ_30

B24

D

DR1_DQ_15/DDR0_DQ_31

G31

D

DR1_DQ_16/DDR0_DQ_48

G32

D

DR1_DQ_17/DDR0_DQ_49

H29

D

DR1_DQ_18/DDR0_DQ_50

H28

D

DR1_DQ_19/DDR0_DQ_51

G28

D

DR1_DQ_20/DDR0_DQ_52

G29

D

DR1_DQ_21/DDR0_DQ_53

H31

D

DR1_DQ_22/DDR0_DQ_54

H32

D

DR1_DQ_23/DDR0_DQ_55

L31

D

DR1_DQ_24/DDR0_DQ_56

L32

D

DR1_DQ_25/DDR0_DQ_57

N29

D

DR1_DQ_26/DDR0_DQ_58

N28

D

DR1_DQ_27/DDR0_DQ_59

L28

D

DR1_DQ_28/DDR0_DQ_60

L29

D

DR1_DQ_29/DDR0_DQ_61

N31

D

DR1_DQ_30/DDR0_DQ_62

N32

D

DR1_DQ_31/DDR0_DQ_63

AJ29

D

DR1_DQ_32/DDR1_DQ_16

AJ30

D

DR1_DQ_33/DDR1_DQ_17

AM32

D

DR1_DQ_34/DDR1_DQ_18

AM31

D

DR1_DQ_35/DDR1_DQ_19

AM30

D

DR1_DQ_36/DDR1_DQ_20

AM29

D

DR1_DQ_37/DDR1_DQ_21

AJ31

D

DR1_DQ_38/DDR1_DQ_22

AJ32

D

DR1_DQ_39/DDR1_DQ_23

AR31

D

DR1_DQ_40/DDR1_DQ_24

AR32

D

DR1_DQ_41/DDR1_DQ_25

AV30

D

DR1_DQ_42/DDR1_DQ_26

AV29

D

DR1_DQ_43/DDR1_DQ_27

AR30

D

DR1_DQ_44/DDR1_DQ_28

AR29

D

DR1_DQ_45/DDR1_DQ_29

AV32

D

DR1_DQ_46/DDR1_DQ_30

AV31

D

DR1_DQ_47/DDR1_DQ_31

BA32

D

DR1_DQ_48/DDR1_DQ_48

BA31

D

DR1_DQ_49/DDR1_DQ_49

BD31

D

DR1_DQ_50/DDR1_DQ_50

BD32

D

DR1_DQ_51/DDR1_DQ_51

BA30

D

DR1_DQ_52/DDR1_DQ_52

BA29

D

DR1_DQ_53/DDR1_DQ_53

BD29

D

DR1_DQ_54/DDR1_DQ_54

BD30

D

DR1_DQ_55/DDR1_DQ_55

BG31

D

DR1_DQ_56/DDR1_DQ_56

BG32

D

DR1_DQ_57/DDR1_DQ_57

BK32

D

DR1_DQ_58/DDR1_DQ_58

BK31

D

DR1_DQ_59/DDR1_DQ_59

BG29

D

DR1_DQ_60/DDR1_DQ_60

BG30

D

DR1_DQ_61/DDR1_DQ_61

BK30

D

DR1_DQ_62/DDR1_DQ_62

BK29

D

DR1_DQ_63/DDR1_DQ_63

CFLU-43E_BGA1528

@

D

DR_DRAMRST#

+

1.2V

12

R

C20 470_0402_5%

@

1

C

C2 100P_0402_50V8J

ESD@

2

DDR1_CKN_0/DDR1_CKN_0 DDR1_CKP_0/DDR1_CKP_0 DDR1_CKN_1/DDR1_CKN_1 DDR1_CKP_1/DDR1_CKP_1

DDR1_CKE_0/DDR1_CKE_0 DDR1_CKE_1/DDR1_CKE_1

DDR1_CKE_2/NC DDR1_CKE_3/NC

DDR1_CS#_0/DDR1_CS#_0 D

DR1_CS#_1/DDR1_CS#_1

D

DR1_ODT_0/DDR1_ODT_0

N

C/DDR1_ODT_1

D

DR1_CAB_9/DDR1_MA_0

D

DR1_CAB_8/DDR1_MA_1

D

DR1_CAB_5/DDR1_MA_2

N

C/DDR1_MA_3

N

C/DDR1_MA_4

D

DR1_CAA_0/DDR1_MA_5

D

DR1_CAA_2/DDR1_MA_6

D

DR1_CAA_4/DDR1_MA_7

D

DR1_CAA_3/DDR1_MA_8

D

DR1_CAA_1/DDR1_MA_9

D

DR1_CAB_7/DDR1_MA_10

D

DR1_CAA_7/DDR1_MA_11

D

DR1_CAA_6/DDR1_MA_12

D

DR1_CAB_0/DDR1_MA_13

D

DR1_CAB_2/DDR1_MA_14

D

DR1_CAB_1/DDR1_MA_15

D

DR1_CAB_3/DDR1_MA_16

D

DR1_CAB_4/DDR1_BA_0

D

DR1_CAB_6/DDR1_BA_1

D

DR1_CAA_5/DDR1_BG_0

D

DR1_CAA_9/DDR1_BG_1

D

DR1_CAA_8/DDR1_ACT#

D

DR1_DQSN_0/DDR0_DQSN_2

D

DR1_DQSP_0/DDR0_DQSP_2

D

DR1_DQSN_1/DDR0_DQSN_3

D

DR1_DQSP_1/DDR0_DQSP_3

D

DR1_DQSN_2/DDR0_DQSN_6

D

DR1_DQSP_2/DDR0_DQSP_6

D

DR1_DQSN_3/DDR0_DQSN_7

D

DR1_DQSP_3/DDR0_DQSP_7

D

DR1_DQSN_4/DDR1_DQSN_2

D

DR1_DQSP_4/DDR1_DQSP_2

D

DR1_DQSN_5/DDR1_DQSN_3

D

DR1_DQSP_5/DDR1_DQSP_3

D

DR1_DQSN_6/DDR1_DQSN_6

D

DR1_DQSP_6/DDR1_DQSP_6

D

DR1_DQSN_7/DDR1_DQSN_7

D

DR1_DQSP_7/DDR1_DQSP_7

N

C/DDR1_ALERT#

N

C/DDR1_PAR

D

RAM_RESET#

D

DR_COMP_0

D

DR_COMP_1

D

DR_COMP_2

3

of 20

Cl

ose to CPU

DDR_B_CLK#0

AF28

DDR_B_CLK0

AF29

DDR_B_CLK#1

AE28

DDR_B_CLK1

AE29

DDR_B_CKE0

T28

DDR_B_CKE1

T29 V28 V29

DDR_B_CS#0

AL37

DDR_B_CS#1

AL35

D

DR_B_ODT0

AL36

D

DR_B_ODT1

AL34

D

DR_B_MA0

AG36

D

DR_B_MA1

AG35

D

DR_B_MA2

AF34

D

DR_B_MA3

AG37

D

DR_B_MA4

AE35

D

DR_B_MA5

AF35

D

DR_B_MA6

AE37

D

DR_B_MA7

AC29

D

DR_B_MA8

AE36

D

DR_B_MA9

AB29

D

DR_B_MA10

AG34

D

DR_B_MA11

AC28

D

DR_B_MA12

AB28

D

DR_B_MA13

AK35

D

DR_B_MA14

AJ35

D

DR_B_MA15

AK34

D

DR_B_MA16

AJ34

D

DR_B_BA0

AJ37

D

DR_B_BA1

AJ36

D

DR_B_BG0

W29

D

DR_B_BG1

Y28

D

DR_B_ACT#

W28

D

DR_A_DQS#2

H24

D

DR_A_DQS2

G24

D

DR_A_DQS#3

C23

D

DR_A_DQS3

D23

D

DR_A_DQS#6

G30

D

DR_A_DQS6

H30

D

DR_A_DQS#7

L30

D

DR_A_DQS7

N30

D

DR_B_DQS#2

AL31

D

DR_B_DQS2

AL30

D

DR_B_DQS#3

AU31

D

DR_B_DQS3

AU30

D

DR_B_DQS#6

BC31

D

DR_B_DQS6

BC30

D

DR_B_DQS#7

BH31

D

DR_B_DQS7

BH30

D

DR_B_ALERT#

Y29

D

DR_B_PARITY

AE34

D

DR_DRAMRST#

BU31

S

M_RCOMP0

BN28

S

M_RCOMP1

BN27

S

M_RCOMP2

BN29

DDR_B_CLK#0 [19] DDR_B_CLK0 [19] DDR_B_CLK#1 [19] DDR_B_CLK1 [19]

DDR_B_CKE0 [19] DDR_B_CKE1 [19]

DDR_B_CS#0 [19] D

DR_B_CS#1 [19]

D

DR_B_ODT0 [19]

D

DR_B_ODT1 [19]

D

DR_B_MA0 [19]

D

DR_B_MA1 [19]

D

DR_B_MA2 [19]

D

DR_B_MA3 [19]

D

DR_B_MA4 [19]

D

DR_B_MA5 [19]

D

DR_B_MA6 [19]

D

DR_B_MA7 [19]

D

DR_B_MA8 [19]

D

DR_B_MA9 [19]

D

DR_B_MA10 [19]

D

DR_B_MA11 [19]

D

DR_B_MA12 [19]

D

DR_B_MA13 [19]

D

DR_B_MA14 [19]

D

DR_B_MA15 [19]

D

DR_B_MA16 [19]

D

DR_B_BA0 [19]

D

DR_B_BA1 [19]

D

DR_B_BG0 [19]

D

DR_B_BG1 [19]

D

DR_B_ACT# [19]

D

DR_A_DQS#2 [18]

D

DR_A_DQS2 [18]

D

DR_A_DQS#3 [18]

D

DR_A_DQS3 [18]

D

DR_A_DQS#6 [18]

D

DR_A_DQS6 [18]

D

DR_A_DQS#7 [18]

D

DR_A_DQS7 [18]

D

DR_B_DQS#2 [19]

D

DR_B_DQS2 [19]

D

DR_B_DQS#3 [19]

D

DR_B_DQS3 [19]

D

DR_B_DQS#6 [19]

D

DR_B_DQS6 [19]

D

DR_B_DQS#7 [19]

D

DR_B_DQS7 [19]

D

DR_B_ALERT# [19]

D

DR_B_PARITY [19]

D

DR_DRAMRST# [18,19]

1 2

R

1

C17 R R

#

543016 PDG1.5 P.168

W=12-15 Space= 20/25 L=500mil

21_0402_1%

1 2

C18 80.6_0402_1%

1 2

C19 100_0402_1%

Recommended By Intel Ma

R

emove RC17 for SDP/DDP BOM selection by PDG

x

S

ecurity Classification

I

ssued Date

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

018/04/09 2019/04/09

2

C

ompal Secret Data

D

eciphered Date

Compal Electronics, Inc.

T

itle

W

HL-U(2/12)DDR4

ustom

HL-U(2/12)DDR4

Monday, October 22, 2018

1

LA-H081P

53

o

f

7

f

7

f

7

Size Document Number Re v

C

Date: Sheet

0

.2

5

4

3

2

1

+3VALW

1 2

RC23 100K_0 201_5%

1 2

RC24 100K_0 201_5%

1 2

RC25 100K_0 201_5%

SOC_SPI_0 _SI SOC_SPI_0 _IO2 SOC_SPI_0 _IO3

SML0ALERT# (Internal Pull Down):

eSPI or LPC

0 = LPC is selected for EC ==> Default

1 = eSPI is selected for EC

D D

SOC_SPI_0 _CLK SOC_SPI_0 _SO

SPI ROM

+

3VS

K

1 2

R

C26

+

C C

B B

3VS

1 2

R

C28 8.2K_040 2_5%

F

rom SOC

From EC

1

0K_0201 _5%

E

C_SPI_CLK[33]

E

C_SPI_MOS I[33]

E

C_SPI_CS0 #[33]

E

C_SPI_MISO[33]

B_RST#

S

ERIRQ[33]

S

ERIRQ

R

PC1, RPC3 a nd RC30 are close to UC3

S

OC_SPI_0_ SO

S

OC_SPI_0_ CLK

S

OC_SPI_0_ SI

S

OC_SPI_0_ IO3

S

OC_SPI_0_ IO2

1 2

R

C29

1 2

R

C31

1 2

R

C32

1 2

R

C34

1 2

R

C36 33_0402 _5%

E

C_SPI_CLK

E

C_SPI_MOS I

E

C_SPI_CS0 #

E

C_SPI_MISO

R

C41

R

C42

R

C43

R

C44

3

3_0402_ 5%

3

3_0402_ 5%EMI@

3

3_0402_ 5%

3

3_0402_ 5%

1 2 1 2 1 2 1 2

SOC_SPI_0 _SI SOC_SPI_0 _IO2 SOC_SPI_0 _IO3 SOC_SPI_0 _CS#0

K

B_RST#

S

ERIRQ

S

OC_SPI_0_ SO_R

S

OC_SPI_0_ CLK_R

S

OC_SPI_0_ SI_R

S

OC_SPI_0_ IO3_R

S

OC_SPI_0_ IO2_R

3

3_0402_ 5%EMI@

3

3_0402_ 5%

3

3_0402_ 5%

3

3_0402_ 5%

S

OC_SPI_0_ CLK_R

S

OC_SPI_0_ SI_R

S

OC_SPI_0_ CS#0

S

OC_SPI_0_ SO_R

UC1E

CH37

SPI0_CLK

CF37

SPI0_MISO

CF36

SPI0_MOSI

CF34

SPI0_IO2

CG34

SPI0_IO3

CG36

SPI0_CS0#

CG35

S

PI0_CS1#

CH34

S

PI0_CS2#

CF20

G

PP_D1/SPI1_CLK/BK1/SBK1

CG22

G

PP_D2/SPI1_MISO_IO1/BK2/SBK2

CF22

G

PP_D3/SPI1_MOSI_IO0/BK3/SBK3

CG23

G

PP_D21/SPI1_IO2

CH23

G

PP_D22/SPI1_IO3

CG20

G

PP_D0/SPI1_CS0#/BK0/SBK0

CH7

C

L_CLK

CH8

C

L_DATA

CH9

C

L_RST#

BV29

G

PP_A0/RCIN#/TIME_SYNC1

BV28

G

PP_A6/SERIRQ

CFLU-43E _BGA1528

@

G

PP_B23/SML1ALERT#/PCHHOT#

G

PP_A5/LFRAME#/ESPI_CS#

G

PP_A14/SUS_STAT#/ESPI_RESET#

G

PP_A9/CLKOUT_LPC0/ESPI_CLK

5

of 20

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

G

PP_C5/SML0ALERT#

G

PP_C6/SML1CLK

G

PP_C7/SML1DATA

G

PP_A1/LAD0/ESPI_IO0

G

PP_A2/LAD1/ESPI_IO1

G

PP_A3/LAD2/ESPI_IO2

G

PP_A4/LAD3/ESPI_IO3

G

PP_A10/CLKOUT_LPC1

G

PP_A8/CLKRUN#

CK14 CH15 CJ15

CH14 CF15 CG15

CN15 CM15 CC34

CA29 BY29 BY27 BV27 CA28 CA27

BV32 BV30 BY30

SOC_SMB CLK SOC_SMB DATA SOC_SMB ALERT#

SOC_SML 0CLK SOC_SML 0DATA SOC_SML 0ALERT#

S

OC_SML1 ALERT#

L

PC_AD0

L

PC_AD1

L

PC_AD2

L

PC_AD3

L

PC_FRAM E#

L

PC_CLK0

P

M_CLKRU N#

1 2

R

C27 22_0402 _5%EMI@

SOC_SMB CLK [19] SOC_SMB DATA [19]

T8TP@

T

9TP@

E

C_SMB_C K2 [24,33,35 ]

E

C_SMB_D A2 [24,33,35 ]

L

PC_AD0 [33]

L

PC_AD1 [33]

L

PC_AD2 [33]

L

PC_AD3 [33]

L

PC_FRAM E# [33]

E

C_SMB_C K2

E

C_SMB_D A2

S

OC_SML1 ALERT#

S

OC_SMBC LK

S

OC_SMBD ATA

S

OC_SML0 CLK

S

OC_SML0 DATA

P

M_CLKRU N#

SMB

(Link to DDR)

S

ML1

(

Link to EC,DGPU,Thermal Sensor)

C

LK_LPC_ EC [3 3]

P

M_CLKRU N# [3 3]

1 2

R

C30

1 2

R

C33

1 2

R

C35 150K_04 02_5%

1 2

R

C37

1 2

R

C38

1 2

R

C39

1 2

R

C40

1 2

R

C45 8.2K_040 2_5%

1

K_0201_ 5%

1

K_0201_ 5%

@

1

K_0201_ 5%

1

K_0201_ 5%

1

K_0201_ 5%

1

K_0201_ 5%

+

3VS

+

3VS

<

SPI ROM - 16M >

S

OC_SPI_0_ CS#0

S

OC_SPI_0_ SO_R

S

OC_SPI_0_ IO2_R

A A

5

UC12

1

C

S#

2

D

O(IO1)

3

I

O2

4

G

ND

W

25Q128J VSIQ SOIC8P

SA00005 VV20

D

V

C

I(IO0)

CC

I LK

O

+

3VALW

8 7 6 5

@

1 2

C

C3 0.1U_020 1_10V K X5R

S

OC_SPI_0_ IO3_R

S

OC_SPI_0_ CLK_R

S

OC_SPI_0_ SI_R

S

ecurity Classification

2

018/04/0 9 2019/04/ 09

I

ssued Date

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

018/04/0 9 2019/04/ 09

3

C

ompal Secret Data

Deciphered Date

Compal Electronics, Inc.

T

itle

Size Document Nu mber Re v

C

ustom

Date : S heet

2

Date : S heet

Compal Electronics, Inc.

W

HL-U(3/12)SPI,SMB,LPC,ESPI

LA-H081P

8 53Monday, October 2 2, 2018

1

0

.2

o

f

5

4

3

2

1

< HD AUDIO >

D D

HDA_RST #_R[32 ]

HDA_BIT_C LK_R[32]

HDA_SYNC_ R[32]

1 2

RC163 33_0201 _5%

1 2

RC46 33_020 1_5%EMI@

1 2

RC48 33_020 1_5%

1 2

RC47 33_020 1_5%

< To Enable ME Override >

1 2

R

1 2

C51 0_0402_5 %@

R

C5275K_040 2_5% CNVi@

C

NV_RF_R ESET#

H

DA_SPKR

M

E_EN[33]

C C

F

ollow Jefferson Peak schematic check list.

+

B B

3VS

1 2

R

C55 2.2K_0402 _5%@

S

PKR (Internal Pull Down):

TOP Swap Override

0 = Disable TOP Swap mode. ==> Default

1 = Enable TOP Swap Mode.

+

3VS

3VALW

W

R

C58

C164

1 2

1

0K_0201 _5%@

1

0K_0201 _5%@

LBT_OFF #

12

@

HDA_RST #

HDA_BIT_C LK

HDA_SYNC

HDA_SDO UT

R

C49

499_040 2_1%

H

DA_SDOU T

F

or MX150

HDA_SYNC HDA_BIT_C LK

C

NV_CRX_ DTX_N0

C

NV_CRX_ DTX_P0

C

NV_CRX_ DTX_N1

C

NV_CRX_ DTX_P1

C

NV_CTX_ DRX_N0

C

NV_CTX_ DRX_P0

C

NV_CTX_ DRX_N1

C

NV_CTX_ DRX_P1

C

LK_CNV_ CRX_DTX_N

C

LK_CNV_ CRX_DTX_P

C

LK_CNV_ CTX_DRX_N

C

LK_CNV_ CTX_DRX_P

S

OC_GPIO_C 10

0K_0201 _5%

HDA_SDO UT

HDA_RST #

C

NV_RF_R ESET#

C

LKREQ_C NV#

H

DA_SPKR

C

NV_W T_RCOMP

G

C6_FB_E N1V8

S

OC_A4W P_PRESENT

HDA_SDIN0[3 2]HDA_SDO UT_R[32]

C

NV_RF_R ESET#[30]

C

LKREQ_C NV#[30]

H

DA_SPKR[32 ]

C

NV_CRX_ DTX_N0[30]

C

NV_CRX_ DTX_P0[30]

C

NV_CRX_ DTX_N1[30]

C

NV_CRX_ DTX_P1[30]

C

NV_CTX_ DRX_N0[30]

C

NV_CTX_ DRX_P0[30]

C

NV_CTX_ DRX_N1[30]

C

NV_CTX_ DRX_P1[30]

C

LK_CNV_ CRX_DTX_N[30]

C

LK_CNV_ CRX_DTX_P[30]

C

LK_CNV_ CTX_DRX_N[30]

C

LK_CNV_ CTX_DRX_P[30]

1 2

CNVi@

R

C56 150_040 2_1%

G

C6_FB_E N1V8[11 ]

T

P_INT#[34]

W

LBT_OFF #[30]

1 2

R

C57

1

UC1G

BN34

HDA_SYNC/I2S0_SFRM

BN37

HDA_BCLK/I2S0_SCLK

BN36

HDA_SDO/I2S0_TXD

BN35

HDA_SDI0/I2S0_RXD

BL36

HDA_SDI1/I2S1_RXD/SNDW1_DATA

BL35

HDA_RST#/I2S1_SCLK/SNDW1_CLK

CK23

G

PP_D23/I2S_MCLK

BL37

I

2S1_SFRM/SNDW2_CLK

BL34

I

2S1_TXD/SNDW2_DATA

CJ32

G

PP_H1/I2S2_SFRM/CNV_BT_I2S_BCLK/CNV_RF_RESET#

CH32

G

PP_H0/I2S2_SCLK/CNV_BT_I2S_SCLK

CH29

G

PP_H2/I2S2_TXD/CNV_BT_I2S_SDI/MODEM_CLKREQ

CH30

G

PP_H3/I2S2_RXD/CNV_BT_I2S_SDO

CP24

G

PP_D19/DMIC_CLK0/SNDW4_CLK

CN24

G

PP_D20/DMIC_DATA0/SNDW4_DATA

CK25

G

PP_D17/DMIC_CLK1/SNDW3_CLK

CJ25

G

PP_D18/DMIC_DATA1/SNDW3_DATA

CF35

G

PP_B14/SPKR

CFLU-43E _BGA1528

@

U

C1I

CR30

C

NV_WR_D0N

CP30

C

NV_WR_D0P

CM30

C

NV_WR_D1N

CN30

C

NV_WR_D1P

CN32

C

NV_WT_D0N

CM32

C

NV_WT_D0P

CP33

C

NV_WT_D1N

CN33

C

NV_WT_D1P

CN31

C

NV_WR_CLKN

CP31

C

NV_WR_CLKP

CP34

C

NV_WT_CLKN

CN34

C

NV_WT_CLKP

CP32

C

NV_WT_RCOMP_0

CR32

C

NV_WT_RCOMP_1

CP20

G

PP_F0/CNV_PA_BLANKING

CK19

G

PP_F1

CG17

G

PP_F2

CR14

G

PP_C8/UART0_RXD

CP14

G

PP_C9/UART0_TXD

CN14

G

PP_C10/UART0_RTS#

CM14

G

PP_C11/UART0_CTS#

CJ17

G

PP_F8/CNV_MFUART2_RXD

CH17

G

PP_F9/CNV_MFUART2_TXD

CF17

G

PP_F23/A4WP_PRESENT

CFLU-43E _BGA1528

@

G

PP_D4/IMGCLKOUT0/BK4/SBK4

9

of 20

G

PP_A17/SD_VDD1_PWR_EN#/ISH_GP7

7

of 20

G

PP_H18/CPU_C10_GATE#

G

PP_H19/TIMESYNC_0

G

PP_H21

G

PP_H22

G

PP_H23

G

PP_F10

G

PP_H20/IMGCLKOUT_1

G

PP_F12/EMMC_DATA0

G

PP_F13/EMMC_DATA1

G

PP_F14/EMMC_DATA2

G

PP_F15/EMMC_DATA3

G

PP_F16/EMMC_DATA4

G

PP_F17/EMMC_DATA5

G

PP_F18/EMMC_DATA6

G

PP_F19/EMMC_DATA7

G

PP_F20/EMMC_RCLK

G

PP_F21/EMMC_CLK

G

PP_F11/EMMC_CMD

G

PP_F22/EMMC_RESET#

E

MMC_RCOMP

G

PD7

PP_F3

GPP_G0/SD_CMD GPP_G1/SD3_DATA0 GPP_G2/SD3_DATA1 GPP_G3/SD3_DATA2

GPP_G4/SD_DATA3

G

PP_G5/SD_CD#

G

PP_G6/SD_CLK

G

PP_G7/SD_WP

G

PP_A16/SD_1P8_SEL

S

D_1P8_RCOMP

S

D_3P3_RCOMP

GPP_H21 XTAL frequency select.

0: 38.4 / 19.2 MHz

1: 24MHz XTAL select.

S

OC_C10_ GATE#

CN27

CM27

S

OC_GPP_ H21

CF25 CN26 CM26 CK17

S

OC_GPD7

BV35 CN20

CG25

XTAL INPUT MODE (HVM ONLY)

CH25

LOW: XTAL INPUT IS SINGLE ENDED

CR20

HIGH: XTAL IS ATTACHED

CM20 CN19 CM19 CN18 CR18 CP18 CM18

CM16 CP16 CR16 CN16

CK15

CH36 CL35 CL36 CM35 CN35 CH35 CK36 CK34

BW36 BY31

CK33 CM34

R

C53

R

C54

S

OC_SD_R COMP

S

1 2

OC_SD_R COMP

T10T

P@

4

.7K_0201 _5%

1

00K_020 1_5%

1 2

R

C50 200_040 2_1%

+

3VALW

S

A A

TO DGPU

OC_GPIO_C 10

5

1 2

R

C59 0_0402_ 5%@

G

PU_EVEN T#

4

G

PU_EVEN T# [24]

S

ecurity Classification

2

018/04/0 9 2019/04/ 09

I

ssued Date

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

018/04/0 9 2019/04/ 09

3

C

ompal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

T

itle

Size Document Nu mber Re v

C

ustom

Date : S heet

Compal Electronics, Inc.

W

HL-U(4/12)HDA,EMMC,SDIO,CSI2

LA-H081P

Monday, October 2 2, 2018

LA-H081P

1

o

f

9

f

9

f

9

53

0

.2

5

4

3

2

1

+3VS

1 2

RC66 10K_0201_5%

1 2

RC61 10K_0201_5%

1 2

RC62 10K_0201_5%

1 2

RC63 10K_0201_5%

1 2

RC64 10K_0201_5%

D D

1 2

RC67 10K_0201_5%@

1 2

RC68 10K_0201_5%@

CLKREQ_PEG#0 CLKREQ_PCIE#1 CLKREQ_PCIE#2 CLKREQ_PCIE#3 CLKREQ_PCIE#4

CLKREQ_PEG#0 CLKREQ_PCIE#4

DGPU

SSD1

SSD2

WLAN

+

3VL_RTC

S

YS_RESET#

E

C_RSMRST#

S

YS_PWROK

W

AKE#

OC_SRTCRST #

CLR CMOS

S

M_INTRUDER#

S

YS_RESET#

P

CH_PWRO K

E

C_RSMRST#

+

1.05V_VCCST

12

R

1

C 100P_0402_ 50V8J

ESD@

2

E

C_CLEAR_CMOS # [33]

R

C89

1

K_0201_5%

1 2

C90 60.4_0402_1 %

C15

1 2

R

C70 20K_0402_5 %

1 2

C

C5 1U_0201_6 .3V6M

R

C71 20K_0402_5 %

C

C6 1U_0201_6 .3V6M

C

LRP1 SHORT PADS

R

C75 1M_0402_5 %

C C

+

3VALW

R

C77

R

C78

R

C79

ESD@

C

C10 100P_0402_5 0V8J

ESD@

C

C11 100P_0402_5 0V8J

ESD@

C

C12 100P_0402_5 0V8J

B B

+

3VALW

R

C82

F

rom EC (Open-Drain)

V

CCST_PW RGD[33]

A A

1 2

1 2 1 2 1 2

1 2

SE00000UC0 0

1

0K_0201_5%

1

0K_0201_5%

1

0K_0201_5%

1

K_0201_5%

Card Reader

E

C_VCCST_PG

CLK_PEG_N0[21] CLK_PEG_P0[21]

CLKREQ_PEG#0[21]

CLK_PCIE_N1[31] CLK_PCIE_P1[31] CLKREQ_PCIE#1[31]

CLK_PCIE_N2[31] CLK_PCIE_P2[31] CLKREQ_PCIE#2[31]

CLK_PCIE_N3[30] CLK_PCIE_P3[30] CLKREQ_PCIE#3[30]

CLK_PCIE_N4[36] C

LK_PCIE_P4[36]

C

LKREQ_PCIE#4[36]

CLKREQ_PEG#0

CLKREQ_PCIE#1

CLKREQ_PCIE#2

CLKREQ_PCIE#3

C

LKREQ_PCIE#4

< PCH PLTRST Buffer >

S

OC_PLTRST #

U

C1K

S

OC_PLTRST #

S

YS_RESET#

E

C_RSMRST#[33]

T

11 T P@

S

YS_PWROK[33]

P

CH_PWRO K[33]

C_RSMRST#

H

_CPUPWR GD

E

C_VCCST_PG

S

YS_PWROK

P

CH_PWRO K

E

C_RSMRST#

W

AKE#

BJ35

G

PP_B13/PLTRST#

CN10

S

YS_RESET#

BR36

R

SMRST#

AR2

P

ROCPWRGD

BJ2

V

CCST_PWRGOOD

CR10

S

YS_PWROK

BP31

P

CH_PWROK

BP30

D

SW_PWROK

BV34

G

PP_A13/SUSWARN#/SUSPWRDACK

BY32

G

PP_A15/SUSACK#

BU30

W

AKE#

BU32

G

PD2/LAN_WAKE#

BU34

G

PD11/LANPHYPC

CFLU-43E_BGA15 28

@

UC1J

AW2

CLKOUT_PCIE_N_0

AY3

CLKOUT_PCIE_P_0

CF32

GPP_B5/SRCCLKREQ0#

BC1

CLKOUT_PCIE_N_1

BC2

CLKOUT_PCIE_P_1

CE32

GPP_B6/SRCCLKREQ1#

BD3

CLKOUT_PCIE_N_2

BC3

CLKOUT_PCIE_P_2

CF30

GPP_B7/SRCCLKREQ2#

BH3

CLKOUT_PCIE_N_3

BH4

CLKOUT_PCIE_P_3

CE31

GPP_B8/SRCCLKREQ3#

BA1

CLKOUT_PCIE_N_4

BA2

C

LKOUT_PCIE_P_4

CE30

G

PP_B9/SRCCLKREQ4#

BE1

C

LKOUT_PCIE_N_5

BE2

C

LKOUT_PCIE_P_5

CF31

G

PP_B10/SRCCLKREQ5#

CFLU-43E_BGA15 28

@

1 2

R

C76 0_0402_5%

R

C80

1

00K_0201_5 %

G

1

1 of 20

CLKOUT_ITPXDP_N

CLKOUT_ITPXDP_P

GPD8/SUSCLK

CLK_BIASREF

CLKIN_XTAL

1

0 of 20

12

C

C9

100P_0402_ 50V8J

G

PP_B12/SLP_S0#

G

PD4/SLP_S3#

G

PD5/SLP_S4#

G

PD10/SLP_S5#

S

LP_SUS#

S

LP_LAN#

G

PD9/SLP_WLAN#

G

PD6/SLP_A#

G

PD3/PWRBTN#

G

PD1/ACPRESENT

G

PD0/BATLOW#

I

NTRUDER#

PP_B11/EXT_PWR_GATE#

G

PP_B2/VRALERT#

I

NPUT3VSEL

XTAL_IN

XTAL_OUT

RTCX1 RTCX2

SRTCRST#

RTCRST#

P

CI_RST# [21,30,31,33,3 6]

ESD@

BJ37 BU36 BU27 BT29

BU29 BT31 BT30 BU37

BU28 BU35 BV36

BR35

CC37 CC36

BT27

AU1 AU2

BT32

SUSCLK

33E_SOC_XTAL24 _IN_R

CK3

33E_SOC_XTAL24 _OUT_R

CK2

XCLK_BIASREF

CJ1

CLKIN_XTAL

CM3

SOC_RTCX1

BN31

SOC_RTCX2

BN32

SOC_SRTCRS T#

BR37

EC_CLEAR_CMOS #

BR34

P

M_SLP_S0#

P

M_SLP_S3#

P

M_SLP_S4#

P

M_SLP_S5#

S

LP_WLAN#

P

M_SLP_A#

P

BTN_OUT#

P

M_BATLOW#

S

M_INTRUDER#

S

OC_VRALERT#

S

OC_INPUT3VSEL

SUSCLK [30 ]

CLKIN_XTAL [30 ]

T

12TP@

P

M_SLP_S3# [33]

P

M_SLP_S4# [33,42 ,45]

T

13TP@

T

14TP@

T

15TP@

33E_SOC_XTAL24 _IN_R

3

3E_SOC_XTAL24_ OUT_R

P

BTN_OUT# [33]

A

C_PRESENT [24,33 ]

XCLK_BIASREF

CLKIN_XTAL

Follow CFL-U PDG_Rev_0.7 Stuff 60.4 ohm(RC110) PD for CNL-U/ WHL-U and CFL-U

R

S

OC_RTCX2

S

OC_RTCX1

1 2

RC60 60.4_0402_1 %

1 2

RC65 10K_0201_5%

1 2

C69 33_0201_5%EM I@

L

C1

@EMI@

1

4

DLM0NSN90 0HY2D_4P

1 2

C73 33_0201_5%EM I@

2

3

1

C

C13

6.8P_0402_5 0V8C

2

P

M_BATLOW#

A

C_PRESENT

S

OC_VRALERT#

S

OC_INPUT3VSEL

33E_SOC_XTAL24 _IN

3

3E_SOC_XTAL24_ OUT

R

C74 200K_0402_ 1%

Y

C1 24MHZ_18PF_XRC GB24M000F2P51R0

SJ10000UJ00

3

27P_0402_50V8J

C C7

1

2

1 2

R

C81 10M_0402_5 %

Y

C2

1 2

32.768KHZ_9P F_X1A000141000200

SJ10000PW 00

C

ommon part

1 2

R

C84 8.2K_0402_5 %

1 2

@

R

C85

1 2

@

R

C86

1 2

@

R

C87

1 2

R

C88

1 2

N

C

4

1

0K_0201_5%

1

0K_0201_5%

4

.7K_0402_5%

4

.7K_0402_5%

N

C

2

1

C

C14

6.8P_0402_5 0V8C

2

+

3VALW

27P_0402_50V8J

C C8

1

2

S

ecurity Classification

I

ssued Date

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

018/04/09 2019/04/09

C

ompal Secret Data

D

eciphered Date

Compal Electronics, Inc.

T

itle

W

HL-U(5/12)CLK,PM,GPIO

Size Document Number Re v

C

ustom

Date : Sheet

2

Date : Sheet

LA-H081P

1

10 53Monday, October 22, 2018

0

.2

o

f

5

GSPI0_MOSI (Internal Pull Down):

No Reboot

Capacit

y

0 = Disable No Reboot mode. ==> Default

1 = Enable No Reboot Mode. (PCH will disable the TCO

Timer system reboot feature). This funct i on i s usef ul

when running ITP/XDP.

D D

4GB

GSPI1_MOSI (Internal Pull Down):

Boot BIOS Strap Bit

0 = SPI Mode ==> Default

1 = LPC Mode

+

3VS

G

1

00P_0402_5 0V8J

1

00P_0402_5 0V8J

1

00P_0402_5 0V8J

SPI0_MOSI

G

SPI1_MOSI

D

GPU_PWR_ EN

S

OC_GPIO_A7

I

2C_1_SDA

I

2C_1_SCL

U

ART0_RX

U

ART0_TX

I

2C_0_SDA

I

2C_0_SCL

D

GPU_HOLD_RS T#

C

NV_RGI_CRX_DTX

C

NV_BRI_CRX_DTX

I

2C_0_SDA

I

2C_0_SCL

I

2C_1_SDA

I

2C_1_SCL

I

2C_2_SDA

I

2C_2_SCL

To

uch PAD

To

uch Screen

EC sensor Hub

S

ENSOR_EC_INT[33]

C

NV_BRI_CRX_DTX[30]

C

NV_RGI_CTX_DRX[30]

C

NV_BRI_CTX_DRX[30]

C

NV_RGI_CRX_DTX[30]

U

ART0_RX[30]

U

I

2C_0_SDA[34]

I

2C_0_SCL[34]

I

2C_1_SDA[28]

I

2C_1_SCL[28]

I

2C_2_SDA[33]

I

2C_2_SCL[33]

1 2

R

C97 4.7K_0402_5%@

1 2

R

C98 150K_0402_5 %@

+

3VS

1 2

R

C101

R

C102

R

C167 2.2K_0402 _5%

R

C C

B B

C168 2.2K_0402 _5%

R

C103 49.9K_040 2_1%

R

C108 49.9K_040 2_1%

R

C109 2.2K_0402 _5%

R

C105 2.2K_0402 _5%

R

C106

R

C112

+

1.8VALW

R R

1

0K_0201_5%

1 2

1

0K_0201_5%

1 2 1 2

1 2 1 2 1 2 1 2 1 2

1

0K_0201_5%@

1 2

1

0K_0201_5%DIS@

1 2

C113 20K_0201 _5%@

1 2

C114 20K_0201 _5%@

1 2

C

C182 100P_0402_ 50V8J

1 2

C

C185

1 2

C

C183 100P_0402_ 50V8J

1 2

C

C186

1 2

C

C184 100P_0402_ 50V8J

1 2

C

C187

PCH EDS : M.2 CNV Mode Select

GPP_F6/CNV_RGI_DT

0 = Integrated CNVi enable.

4

Description

WITHOUT ON-BOARD RA

SAMSUNG 2666MHz

HYNIX 2666MHz

M

(K4A8G165WC-BCTD) EL45

(K4A8G165WC-BCTD) EL4C

(H5AN8G6NCJR-VKC) EL45

(H5AN8G6NCJR-VKC) EL4C

1

MICRON 2666MHz (MT40A512M16LY-075:E) EL45

MICRON 2666MHz (MT40A512M16LY-075:E) EL4C

N/A

RC94 NO_MD @

10K_0201_5 %

ART0_TX[30]

RC95 NO_ MD@ 10K_0201_5 %

S

OC_GPIO_A7

S

OC_GPIO_B16

S

ENSOR_EC_INT

GS

PI0_MOSI

O

BRAM_ID0

O

BRAM_ID1

O

BRAM_ID2

G

SPI1_MOSI

C

NV_BRI_CRX_DTX

C

NV_RGI_CTX_DRX

C

NV_BRI_CTX_DRX

C

NV_RGI_CRX_DTX

RC96 NO_ MD@ 10K_0201_5 %

U

C1F

CC27

G

PP_B15/GSPI0_CS0#

CC32

G

PP_A7/PIRQA#/GSPI0_CS1#

CE28

G

PP_B16/GSPI0_CLK

CE27

G

PP_B17/GSPI0_MISO

CE29

G

PP_B18/GSPI0_MOSI

CA31

G

PP_B19/GSPI1_CS0#

CA32

G

PP_A11/PME#/GSPI1_CS1#/SD_VDD2_PWR_EN#

CC29

G

PP_B20/GSPI1_CLK

CC30

G

PP_B21/GSPI1_MISO

CA30

G

PP_B22/GSPI1_MOSI

CK20

G

PP_F5/CNV_BRI_RSP

CG19

G

PP_F6/CNV_RGI_DT

CJ20

G

PP_F4/CNV_BRI_DT

CH19

G

PP_F7/CNV_RGI_RSP

CR12

G

PP_C20/UART2_RXD

CP12

G

PP_C21/UART2_TXD

CN12

G

PP_C22/UART2_RTS#

CM12

G

PP_C23/UART2_CTS#

CM11

G

PP_C16/I2C0_SDA

CN11

G

PP_C17/I2C0_SCL

CK12

G

PP_C18/I2C1_SDA

CJ12

G

PP_C19/I2C1_SCL

CF27

G

PP_H4/I2C2_SDA

CF29

G

PP_H5/I2C2_SCL

CH27

G

PP_H6/I2C3_SDA

CH28

G

PP_H7/I2C3_SCL

CJ30

G

PP_H8/I2C4_SDA

CJ31

G

PP_H9/I2C4_SCL

CFLU-43E_BGA15 28

@

3

X76

N/A

1

X7680638L05

X7680538L06

1

X7680638L04 X7680538L04

1

X7680638L06 X7680538L05

1

N/A

PART NUMBER(R

N/A

SA0000B6F00

SA0000BMN00

SA0000BMN00 SA0000ARD20

SA0000ARD20

N/A

G G

G

PP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA

G

PP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL

G

PP_D15/ISH_UART0_RTS#/GSPI2_CS1#

G

PP_D16/ISH_UART0_CTS#/SML0BALERT#

G

PP_C12/UART1_RXD/ISH_UART1_RXD

G

PP_C13/UART1_TXD/ISH_UART1_TXD

G

PP_C14/UART1_RTS#/ISH_UART1_RTS#

G

PP_C15/UART1_CTS#/ISH_UART1_CTS#

G

PP_A12/ISH_GP6/BM_BUSY#/SX_EXIT_HOLDOFF#

6

of 20

GPP_B19

1

)

OBRAM_ID0OBRA

12

R

C91

1

0K_0201_5%

X76RAM@

O

BRAM_ID0

12

R

C94

1

0K_0201_5%

X76RAM@

G

PP_D9/ISH_SPI_CS#/GSPI2_CS0#

G

PP_D10/ISH_SPI_CLK/GSPI2_CLK PP_D11/ISH_SPI_MISO/GSPI2_MISO PP_D12/ISH_SPI_MOSI/GSPI2_MOSI

G

PP_D5/ISH_I2C0_SDA

G

PP_D6/ISH_I2C0_SCL

G

PP_D7/ISH_I2C1_SDA

G

PP_D8/ISH_I2C1_SCL

G

PP_H10/I2C5_SDA/ISH_I2C2_SDA

G

PP_H11/I2C5_SCL/ISH_I2C2_SCL

G

PP_A18/ISH_GP0

G

PP_A19/ISH_GP1

G

PP_A20/ISH_GP2

G

PP_A21/ISH_GP3

G

PP_A22/ISH_GP4

G

PP_A23/ISH_GP5

GPP_B20

M_ID1OBRA

0

1

+3VS+ 3VS +3VS

12

R

C92

1

0K_0201_5%

X76RAM@

O

BRAM_ID1

12

R

C95

1

0K_0201_5%

X76RAM@

CN22 CR22 CM22 CP22

CK22 CH20

CH22 CJ22

CJ27 CJ29

CM24 CN23 CM23 CR24

CG12 CH12 CF12 CG14

BW35 BW34 CA37 CA36 CA35 CA34 BW37

M

ODEL_SETTING0

M

ODEL_SETTING1

D

GPU_PWR_ EN

D

GPU_HOLD_RS T#

G

PU_ALL_PGOOD

D

GPU_PRSNT

T

S_INT#

D

GPU_SEL0

D

GPU_SEL1

GPP_B21

0

1

0

1

12

R

C93

1

0K_0201_5%

X76RAM@

12

R

C96

1

0K_0201_5%

X76RAM@

M_ID2

O

2

BRAM_ID2

D

GPU_PWR_ EN [26,33]

D

GPU_HOLD_RS T# [21]

G

PU_ALL_PGOOD [26]

T

S_INT# [28]

Functio

C34

S34

S54

+

3VS

+

3VS

Functio

DIS

UMA Onl

+

+3VS

+

3VS

Functio

n

0

R

C99

R

C100

R

C107

R

C104

n

y

R

C115

R

C116

Arrary MI

Single MI

R

C119

R

C120

RTOUCH5

1 2

4.7K_0402_5 %

MODEL_SETTING

GPP_D12

(

1 2 1 2

R

C100S340@

10K_0201_5 %

DGP

GPP_C15

(

1 2

MODEL_SETTING

n

(

C

@

1 2

@

)

0

0 1

1

0K_0201_5%S540@

1

0K_0201_5%C340@

1

0K_0201_5%S340@

1

0K_0201_5%C340@

U_PRSNT

0

1

0K_0201_5%UMA@

1

0K_0201_5%DIS@

GPP_A20

1

0K_0201_5%

1

0K_0201_5%

1

)

0 1

TS_INT#

1

MODEL_SETTING

GPP_D11

(

M

ODEL_SETTING1

M

ODEL_SETTING0

R

C104S540@

10K_0201_5 %

D

GPU_PRSNT

2

D

GPU_SEL1

0

)

0

1

0

1 = Integrated CNVi disable.

+

1.8VALW

NONCNVi@

12

R

C162 20K_0201_5 %

C

NV_RGI_CTX_DRX

3VS

1 2

R

C160

R

C159

1 2

1

0K_0201_5%@

1

0K_0201_5%@

D

GPU_SEL0

C

NVi RGI_DT pin gets the pull-down resistor (1K ohm) from the internal CRF module when CNVi is enabled.

There must not be any pull-down resistor connected on the board.

A A

S

OC_GPIO_B16

G

C6_FB_EN1V8[9]

C6_FB_EN1V8

5

1 2

R

C121

N16S@

1 2

R

C122

N17S@

0

_0201_5%

0

_0201_5%

G

C6_FB_EN

G

C6_FB_EN [24,2 5]

4

TO DGPU

S

ecurity Classification

I

ssued Date

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

018/04/09 2019/04/09

C

ompal Secret Data

D

eciphered Date

2

Compal Electronics, Inc.

T

Size Document Number Re v

C

ustom

Date : Sheet

Compal Electronics, Inc.

itle

W

HL-U(6/12)GPIO,I2C,GSPI

LA-H081P

o

f

11 53Monday, October 22, 2018

f

11 53Monday, October 22, 2018

f

1

11 53Monday, October 22, 2018

0

.2

5

4

3

2

1

D D

PCIE_CRX_DTX_N5[21]

PCIE_CRX_DTX_P5[21] PCIE_CTX_ C_DRX_N5[21] PCIE_CTX_ C_DRX_P5[21]

PCIE_CRX_DTX_N6[21]

PCIE_CRX_DTX_P6[21] P

CIE_CTX_C _DRX_N6[21]

P

dGPU

C C

SSD1

Card Reader

NGFF WLAN+BT

B B

A A

SSD2

CIE_CTX_C _DRX_P6[21]

P

CIE_CRX_DTX_N7[21]

P

CIE_CRX_DTX_P7[21]

P

CIE_CTX_C _DRX_N7[21]

P

CIE_CTX_C _DRX_P7[21]

P

CIE_CRX_DTX_N8[21]

P

CIE_CRX_DTX_P8[21]

P

CIE_CTX_C _DRX_N8[21]

P

CIE_CTX_C _DRX_P8[21]

P

CIE_CRX_D TX_N9[31]

P

CIE_CRX_D TX_P9[31]

P

CIE_CTX_D RX_N9[31]

P

CIE_CTX_D RX_P9[31]

P

CIE_CRX_D TX_N10[31]

P

CIE_CRX_D TX_P10[31]

P

CIE_CTX_D RX_N10[31]

P

CIE_CTX_D RX_P10[31]

P

CIE_CRX_D TX_N11[31]

P

CIE_CRX_D TX_P11[31]

P

CIE_CTX_D RX_N11[31]

P

CIE_CTX_D RX_P11[31]

S

ATA_CRX _DTX_N1[31]

S

ATA_CRX _DTX_P1[31]

S

ATA_CTX _DRX_N1[31]

S

ATA_CTX _DRX_P1[31]

P

CIE_CRX_D TX_N13[36]

P

CIE_CRX_D TX_P13[36]

P

CIE_CTX_D RX_N13[36]

P

CIE_CTX_D RX_P13[36]

P

CIE_CRX_D TX_N14[30]

P

CIE_CRX_D TX_P14[30]

P

CIE_CTX_D RX_N14[30]

P

CIE_CTX_D RX_P14[30]

P

CIE_CRX_D TX_N15[31]

P

CIE_CRX_D TX_P15[31]

P

CIE_CTX_D RX_N15[31]

P

CIE_CTX_D RX_P15[31]

S

ATA_CRX _DTX_N2[31]

S

ATA_CRX _DTX_P2[31]

S

ATA_CTX _DRX_N2[31]

S

ATA_CTX _DRX_P2[31]

1 2

R

C126 100_0402_ 1%

CC17 0.22U_0 201_6.3V6MDIS@ CC18 0.22U_0 201_6.3V6MDIS@

C

C19

C

C20

C

C16

C

C21

C

C22

C

C23

1 2 1 2

0

.22U_020 1_6.3V6MDIS@

0

.22U_020 1_6.3V6MDIS@

0

.22U_020 1_6.3V6MDIS@

0

.22U_020 1_6.3V6MDIS@

0

.22U_020 1_6.3V6MDIS@

0

.22U_020 1_6.3V6MDIS@

P

CIE_RCOMP N

P

CIE_RCOMP P

PCIE_CTX_ DRX_N5 PCIE_CTX_ DRX_P5

PCIE_CTX_ DRX_N6 P

CIE_CTX_D RX_P6

P

CIE_CTX_D RX_N7

P

CIE_CTX_D RX_P7

P

CIE_CTX_D RX_N8

P

CIE_CTX_D RX_P8

UC1H

BW9

PCIE5_RXN/USB31_5_RXN

BW8

PCIE5_RXP/USB31_5_RXP

BW4

PCIE5_TXN/USB31_5_TXN

BW3

PCIE5_TXP/USB31_5_TXP

BU6

PCIE6_RXN/USB31_6_RXN

BU5

PCIE6_RXP/USB31_6_RXP

BU4

P

CIE6_TXN/USB31_6_TXN

BU3

P

CIE6_TXP/USB31_6_TXP

BT7

P

CIE7_RXN

BT6

P

CIE7_RXP

BU2

P

CIE7_TXN

BU1

P

CIE7_TXP

BU9

P

CIE8_RXN

BU8

P

CIE8_RXP

BT4

P

CIE8_TXN

BT3

P

CIE8_TXP

BP5

P

CIE9_RXN

BP6

P

CIE9_RXP

BR2

P

CIE9_TXN

BR1

P

CIE9_TXP

BN6

P

CIE10_RXN

BN5

P

CIE10_RXP

BR4

P

CIE10_TXN

BR3

P

CIE10_TXP

BN10

P

CIE11_RXN/SATA0_RXN

BN8

P

CIE11_RXP/SATA0_RXP

BN4

P

CIE11_TXN/SATA0_TXN

BN3

P

CIE11_TXP/SATA0_TXP

BL6

P

CIE12_RXN/SATA1A_RXN

BL5

P

CIE12_RXP/SATA1A_RXP

BN2

P

CIE12_TXN/SATA1A_TXN

BN1

P

CIE12_TXP/SATA1A_TXP

BK6

P

CIE13_RXN

BK5

P

CIE13_RXP

BM4

P

CIE13_TXN

BM3

P

CIE13_TXP

BJ6

P

CIE14_RXN

BJ5

P

CIE14_RXP

BL2

P

CIE14_TXN

BL1

P

CIE14_TXP

BG5

P

CIE15_RXN/SATA1B_RXN

BG6

P

CIE15_RXP/SATA1B_RXP

BL4

P

CIE15_TXN/SATA1B_TXN

BL3

P

CIE15_TXP/SATA1B_TXP

BE5

P

CIE16_RXN/SATA2_RXN

BE6

P

CIE16_RXP/SATA2_RXP

BJ4

P

CIE16_TXN/SATA2_TXN

BJ3

P

CIE16_TXP/SATA2_TXP

CE6

P

CIE_RCOMP_N

CE5

P

CIE_RCOMP_P

CR28

G

PP_H12/M2_SKT2/CFG_0

CP28

G

PP_H13/M2_SKT2/CFG_1

CN28

G

PP_H14/M2_SKT2/CFG_2

CM28

G

PP_H15/M2_SKT2/CFG_3

CFLU-43E _BGA1528

@

W

hen PCIE16/SATA2 is used as SATA Port 1 (ODD), then

PCIE15/SATA1B (M.2 SSD) cannot be used as SATA Port 1.

8

of 20

PCIE1_RXN/USB31_1_RXN PCIE1_RXP/USB31_1_RXP

PCIE2_RXN/USB31_2_RXN/SSIC_1_RXN

PCIE2_RXP/USB31_2_RXP/SSIC_1_RXP

PCIE2_TXN/USB31_2_TXN/SSIC_1_TXN

P

CIE2_TXP/USB31_2_TXP/SSIC_1_TXP

P P

G

PP_E9/USB2_OC0#/GP_BSSB_CLK

G

PP_E10/USB2_OC1#/GP_BSSB_DI

G

PP_E0/SATAXPCIE0/SATAGP0

G

PP_E1/SATAXPCIE1/SATAGP1

G

PP_E2/SATAXPCIE2/SATAGP2

G

PP_E8/SATALED#/SPI1_CS1#

PCIE1_TXN/USB31_1_TXN

PCIE1_TXP/USB31_1_TXP

CIE3_RXN/USB31_3_RXN

CIE3_RXP/USB31_3_RXP

P

CIE3_TXN/USB31_3_TXN

P

CIE3_TXP/USB31_3_TXP

CIE4_RXN/USB31_4_RXN

CIE4_RXP/USB31_4_RXP

P

CIE4_TXN/USB31_4_TXN

P

CIE4_TXP/USB31_4_TXP

U

SB2_1N

U

SB2_1P

U

SB2_2N

U

SB2_2P

U

SB2_3N

U

SB2_3P

U

SB2_4N

U

SB2_4P

U

SB2_5N

U

SB2_5P

U

SB2_6N

U

SB2_6P

U

SB2_7N

U

SB2_7P

U

SB2_8N

U

SB2_8P

U

SB2_9N

U

SB2_9P

U

SB2_10N

U

SB2_10P

U

SB2_COMP

U

SB2_ID

U

SB2_VBUSSENSE

G

PP_E11/USB2_OC2#

G

PP_E12/USB2_OC3#

G

PP_E4/DEVSLP0

G

PP_E5/DEVSLP1

G

PP_E6/DEVSLP2

U

FS_RESET#

CB5 CB6 CA4 CA3

BY8 BY9 CA2 CA1

BY7 BY6 BY4 BY3

BW6 BW5 BW2 BW1

CE3 CE4

CE1 CE2

CG3 CG4

CD3 CD4

CG5 CG6

CC1 CC2

CG8 CG9

CB8 CB9

CH5 CH6

CC3 CC4

CC5 CE8 CC6

CK6 CK5 CK8 CK9

CP8 CR8 CM8

CN8 CM10 CP10

CN7

AR3

U

SB20_N1

U

SB20_P1

U

SB20_N2

U

SB20_P2

U

SB20_N3

U

SB20_P3

U

SB20_N4

U

SB20_P4

U

SB20_N6

U

SB20_P6

U

SB20_N7

U

SB20_P7

U

SB20_N1 0

U

SB20_P1 0

U

SB2_COM P

U

SB2_ID

U

SB2_SEN SE

U

SB_OC0#

U

SB_OC1#

U

SB_OC2#

U

SB_OC3#

W

L_OFF#

D

EVSLP1

D

EVSLP2

N

GFF_SSD _PEDET

N

GFF_SSD 2_PEDET

USB3_CR X_DTX_N1 [36] USB3_CR X_DTX_P1 [36] USB3_CT X_DRX_N1 [36] USB3_CT X_DRX_P1 [36]

USB3_CR X_DTX_N2 [36] USB3_CR X_DTX_P2 [36] USB3_CT X_DRX_N2 [36] U

SB3_CTX _DRX_P2 [36]

U

SB3_CRX _DTX_N3 [37]

U

SB3_CRX _DTX_P3 [37]

U

SB3_CTX _DRX_N3 [37]

U

SB3_CTX _DRX_P3 [37]

U

SB20_N1 [36 ]

U

SB20_P1 [36]

U

SB20_N2 [36 ]

U

SB20_P2 [36]

U

SB20_N3 [38 ]

U

SB20_P3 [38]

U

SB20_N4 [28]

U

SB20_P4 [28]

U

SB20_N6 [28 ]

U

SB20_P6 [28]

U

SB20_N7 [34 ]

U

SB20_P7 [34]

U

SB20_N1 0 [30]

U

SB20_P1 0 [30 ]

1 2

R

C123 113_0402 _1%

1 2

R

C124

1 2

R

C125

1

K_0201_ 5%@

1

K_0201_ 5%@

U

SB_OC0# [36]

U

SB_OC1# [36]

W

L_OFF# [30]

D

EVSLP1 [31]

D

EVSLP2 [31]

N

GFF_SSD _PEDET [31 ]

N

GFF_SSD 2_PEDET [3 1]

N

W

USB2.0 / 3.0 Port (IO - 1)

USB2.0 / 3.0 Port (IO - 2)

USB2.0 / 3.0 Port (Type-C)

USB2.0 / 3.0 Port (MB - 1)

USB2.0 / 3.0 Port (MB - 2)

USB2.0 / 3.0 Port (Type-C)

Touch Screen

Camer a

Finger Print

NGFF WLAN+BT

Trace length max: 450mils

U

SB_OC0#

U

SB_OC1#

U

SB_OC2#

U

SB_OC3#

GFF_SSD _PEDET

GFF_SSD 2_PEDET

L_OFF#

R

C166

R

C131

R

C132

R

C165

1

0K_0201 _5%

1

0K_0201 _5%

1

0K_0201 _5%@

1

0K_0201 _5%@

12 12 12 12

+

3VS+3VALW

R

C127 10K_0201 _5%

R

C128 10K_0201 _5%

R

C129 10K_0201 _5%

R

C130 10K_0201 _5%

1 2

+

3VALW

S

ecurity Classification

2

018/04/0 9 2019/04/ 09

I

ssued Date

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

018/04/0 9 2019/04/ 09

3

C

ompal Secret Data

Deciphered Date

Compal Electronics, Inc.

T

Size Document Nu mber Re v

C

ustom

Date : S heet

2

Date : S heet

Compal Electronics, Inc.

itle

W

HL-U(7/12)PCIE,USB,SATA

LA-H081P

0

.2

o

f

12 53Monday, October 22, 20 18

f

12 53Monday, October 22, 20 18

f

12 53Monday, October 22, 20 18

1

5

+1.05VALW TO +1.05V_VCCST

D D

+

1.8VALW TO +1.8VS

C C

SYSON[33,44]

SUSP#[3 3,39,44]

+

VL

0.1U_0201_10V K X5R

C

1

C29

@

2

S

USP#

1 2

RC134 0_0402_ 5%@

1 2

RC135 0_0402_ 5%@

+

1.05VALW

1U_0201_6.3V6M

1

CC30

2

+VL

1U_0201_6.3V6M

1

C C24

2

+

1.05VALW TO +1.05VS_VCCIO

I RON(Max) : 6.2 mohm V drop : 0.019 V

UC15

1

V

2

V

7

V

3

V

4

O

+1.05VAL W

EN_1.0V_ VCCSTU

EN_1.8VS

+1.8VALW

I

(Max) : 0.2 A(+1.8VS) RON(Max) : 25 mohm V drop : 0.005 V

(Max) : 3.675 A(+1.05VS_VCCIO)

IN1 IN2

IN thermal

BIAS

N

E

M5201V_ DFN8_3X3

SA00008 R600

6

V

OUT

5

G

ND

4

I(Max) : 0.16 A(+1.05V_VCCST) RON(Max) : 25 mohm V drop : 0.004 V

UC14

1

VIN1

2

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2

7

VIN2

AOZ1331 DFN 14P

SA0000B KC00

+

1.05VS_V CCIO_STG

VOUT1 VOUT1

CT1

GND

CT2

VOUT2 VOUT2

G

PAD

R

C137 0_0805_ 5%@

14 13

12

11

10

9 8

15

1 2

RC133 0_0402_ 5%

1 2

CC26 8200P_0 402_25V7K

1 2

CC27 1000P_0 402_50V7K

R

C136 0_0 603_5%@

3

+1.05V_V CCST

1 2

Follow 543977_SKL_P DDG_Rev0_91 CC24 10PF ->22us(Spe c:<= 65us)

+

1.8VS

1 2

+

1.05VS_V CCIO

1

2

C

C31

@

0.1U_020 1_10V K X5R

0.1U_0201_10V6K

1

2

+1.2V

UC1N

AD36

3.3 A

0.1U_0201_10V6K

C C25

1

@

2

+1.05V_V CCST

+1.2V

+1.05VS_ VCCIO

0.0 2A

PSC Side

@

C C34

0.1 2A

10U_0402_6.3V6M

1

C

C35

2

C36

2

C C28

@

1

uF X1

0.1uF X1

+

1.05V_VC CST

10U_0402_6.3V6M

1

@

C C32

2

0.1 9A

10U_0402_6.3V6M

1

C C33

2

VDDQ1

AH32

VDDQ2

AH36

VDDQ3

AM36

VDDQ4

AN32

VDDQ5

AW32

VDDQ6

AY36

VDDQ7

BE32

VDDQ8

BH36

VDDQ9

R32

VDDQ10

Y36

VDDQ11

BC28

RSVD1

BP11

VCCST1

BP2

VCCST2

BG1

V

BG2

V

BL27

V

BM26

V

BR11

V

BT11

V

CFLU-43E _BGA1528

@

CCSTG1 CCSTG2

CCPLL_OC1 CCPLL_OC2

CCPLL1 CCPLL2

+

1.2V

V

CCIO_SENSE

V

SSIO_SENSE

V

SSSA_SENSE

V

CCSA_SENSE

1

4 of 20

1U_0201_6.3V6M

1

2

VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO8

VCCIO9 VCCIO10 VCCIO11 VCCIO12 VCCIO13 VCCIO14 VCCIO15 VCCIO16

VCCSA2 VCCSA1 V

CCSA3

V

CCSA5

V

CCSA6

V

CCSA4

V

CCSA9

V

CCSA7

V

CCSA8

V

CCSA13

V

CCSA14

V

CCSA10

V

CCSA11

V

CCSA12

V

CCSA15

V

CCSA16

PSC Side

C C37

AK24 AK26 AL24 AL25 AL26 AL27 AM25 AM27 BH24 BH25 BH26 BH27 BJ24 BJ26 BP16 BP18

BG8 BG10 BH9 BJ8 BJ9 BJ10 BK8 BK25 BK27 BL8 BL9 BL10 BL24 BL26 BM24 BN25

BP28 BP29

BE7 BG7

1

+1.05VS_ VCCIO

3.67 9A

+VCCSA

6A

Trace Length Match < 25 mils

V

SSSA_SE NSE

V

CCSA_SE NSE

+

1.05VS_V CCIO

PSC Side

1U_0201_6.3V6M

1

C C38

2

V

SSSA_SE NSE [47]

V

CCSA_SE NSE [47]

Close to BP11 & BP2 Close to BG1 & BG2

+

1.2V

c

+

1.05VS_V CCIO

B B

1

2

hange package of 1U from 0201 to 0402

P

SC SideBSC Side

1U_0201_6.3V6M

1

C

CC40

C39

2

1U_0201_6.3V6M

1

C C41

2

10U_0402_6.3V6M

1

C

C42

C43

2

10U_0402_6.3V6M

@

1

C

C45

C44

2

4.7U_0402_6.3V6M

1

C C49

10U_0402_6.3V6M

@

1

C C46

2

@

1

2

C

C48

C47

2

10U_0402_6.3V6M

2

C

lose to BR1 1 & BT11 Close to BM2 6

change package of 1U from 0201 to 0402

10U_0402_6.3V6M

1

C C50

2

@

1

0U_0402_6.3V6M

1

C C51

2

1

C C52

2

BSC SidePSC Side

1U_0201_6.3V6M

@

1

C C53

2

1U_0201_6.3V6M

C

@

1

C

C55

C54

2

lose to CPUUnderneath CPU

1U_0201_6.3V6M

1

C C56

2

C C57

Close to CPU Underneath CPU

A A

S

ecurity Classification

2

018/04/0 9 2019/04/ 09

I

ssued Date

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

018/04/0 9 2019/04/ 09

3

C

ompal Secret Data

Deciphered Date

Compal Electronics, Inc.

T

Size Document Nu mber Re v

C

ustom

Date : S heet

2

Date : S heet

Compal Electronics, Inc.

itle

W

HL-U(8/12)Power

LA-H081P

0

.2

o

f

13 53Monday, October 22, 20 18

f

13 53Monday, October 22, 20 18

f

13 53Monday, October 22, 20 18

1

+1.05VALW

1

2

@

CC61 1U_0201_6.3V6M

5

+1.05VALW

1

2

CC62 1U_0201_6.3V6M

4

3

2

1

Close to BP20Close to BV18

D D

1

CC63 1U_0201_6.3V6M

2

Close to BV2

+

1.8VALW

1

C

C68

1U_0201_6.3V6M

2

C

lose to CP17

C C

+

3VALW

1

@

C

C71

1U_0201_6.3V6M

2

C

lose to CP29

+

3VALW

1

@

C

C74

0.1U_0201_10 V K X5R

2

C

lose to BR24

+

3VALW

B B

A A

1 2

BLM15BB221SN 1D_2P

SM01000BV00

R

F request

RF@

L

1

@

C

C72

0.1U_0201_10 V K X5R

2

C2

+1.05VALW+1.05VALW

+

3V_1.8V_HDA

12

1

CC64

4.7U_0402_6.3 V6M

2

Close to BV12

C

C76

0

.1U_0402_25V6

RF@

1

CC65 10U_0402_6 .3V6M

2

+1.8VALW

Imax : 0.702A

+

3VALW

I

max : 0.21A

Close to BT24

1 2

C

C73 1U_0201_6.3V6M

+

3VALW

+

3V_1.8V_HDA

I

nternal LDO

D

CPDSW

Imax : 4.982A

+1.05VALW

UC1P

BP20

VCCPRIM_1P05_1

BW16

VCCPRIM_1P05_9

BW18

VCCPRIM_1P05_10

BW19

VCCPRIM_1P05_11

BY16

VCCPRIM_1P05_12

CA14

VCCPRIM_1P05_14

CC15

VCCPRIM_1P8_1

CD15

V

CCPRIM_1P8_4

CD16

V

CCPRIM_1P8_5

CP17

V

CCPRIM_1P8_8

CB22

V

CCPRIM_3P3_4

CB23

V

CCPRIM_3P3_5

CC22

V

CCPRIM_3P3_6

CC23

V

CCPRIM_3P3_7

CD22

V

CCPRIM_3P3_8

CD23

V

CCPRIM_3P3_9

CP29

V

CCPRIM_3P3_10

BU15

V

CCPRIM_CORE1

BU22

V

CCPRIM_CORE2

BV15

V

CCPRIM_CORE3

BV16

V

CCPRIM_CORE4

BV18

V

CCPRIM_CORE5

BV19

V

CCPRIM_CORE6

BV20

V

CCPRIM_CORE7

BV22

V

CCPRIM_CORE8

BW20

V

CCPRIM_CORE9

BW22

V

CCPRIM_CORE10

CA12

V

CCPRIM_CORE11

CA16

V

CCPRIM_CORE12

CA18

V

CCPRIM_CORE13

CA19

V

CCPRIM_CORE14

CA20

V

CCPRIM_CORE15

CB12

V

CCPRIM_CORE16

CB14

V

CCPRIM_CORE17

CB15

V

CCPRIM_CORE18

BT24

V

CCDSW_1P05

BU14

V

CCAPLL_1P05_4

BV12

V

CCPRIM_MPHY_1P05_1

BW12

V

CCPRIM_MPHY_1P05_3

BW14

V

CCPRIM_MPHY_1P05_4

BY12

V

CCPRIM_MPHY_1P05_5

BY14

V

CCPRIM_MPHY_1P05_6

BV2

V

CCAMPHYPLL_1P05

BR15

V

CCAPLL_1P05_2

CC12

V

CCDUSB_1P05

BR24

V

CCDSW_3P3_1

BT20

V

CCHDA

BV23

V

CCSPI

BT18

V

CCPRIM_1P05_4

BT19

V

CCPRIM_1P05_5

BU18

V

CCPRIM_1P05_7

BU19

V

CCPRIM_1P05_8

BT22

V

CCPRIM_1P05_6

BP22

V

CCPRIM_1P05_2

BV14

V

CCPRIM_MPHY_1P05_2

CFLU-43E_BGA1528

@

U

C1O

K12

V

CCOPC1

K14

V

CCOPC2

K15

V

CCOPC3

K17

V

CCOPC4

K18

V

CCOPC5

K20

V

CCOPC6

L25

V

CCOPC7

M24

V

CCOPC8

M26

V

CCOPC9

P24

V

CCOPC10

P26

V

CCOPC11

R24

V

CCOPC12

R25

V

CCOPC13

R26

V

CCOPC14

W25

V

CC_OPC_1P8_2

V24

V

CC_OPC_1P8_1

Y25

V

CC_OPC_1P8_4

Y24

V

CC_OPC_1P8_3

CFLU-43E_BGA1528

@

VCCOPC and VCCEOPIO for CFL U43e only

V

G G

1

6 of 20

V

CCEOPIO1

V

CCEOPIO2

V

CCEOPIO3

V

CCEOPIO4

V

CCEOPIO5

V

CCEOPIO6

V

CCEOPIO7

V

CCEOPIO8

V

CCEOPIO_SENSE

V

SSEOPIO_SENSE

1

5 of 20

VCCPRIM_3P3_3

VCCRTC

VCCPRIM_1P05_13

D

CPRTC

V

CCPRIM_1P05_3

V

CCAPLL_1P05_3

V

CCA_BCLK_1P05

V

CCAPLL_1P05_1

V

CCA_SRC_1P05

V

CCA_XTAL_1P05

V

CCDPHY_1P24_2

V

CCDPHY_1P24_4

V

CCDPHY_1P24_1

V

CCDPHY_1P24_3

CCDPHY_EC_1P24

V

CCDSW_3P3_2

V

CCA_19P2_1P05

V

CCPRIM_1P8_2

V

CCPRIM_1P8_3

V

CCPRIM_1P8_6

V

CCPRIM_1P8_7

V

CCPRIM_1P8_9

V

CCPRIM_3P3_2

V

CCPRIM_3P3_1

PP_B0/CORE_VID0 PP_B1/CORE_VID1

AA24 AA26 AB25 AC24 AC25 AC26 AD24 AD26

V25 T25

CB16

BR23

BY20 BP24

BR20

BT12

BP14

BR14

BU12

CP5

BY24 CA24

BY23 CA23 CP25

BT23

BR12

CC18 CC19 CD18 CD19 CP23

BW23

BP23

CB36 CB35

+1.05VALW

+3VALW

I

ntenal LDO

V

CCDPHY_EC_1P2 4

I

max : 0.702A

+3VL_RTC

D

CPRTC

+

VCCDPHY_1.24V

+

C

1.05VALW

+

@

1 2

C

C66 1U_0201_6.3V6M

Close to BP24

Close to CP25

1 2

4

C69

1.8VALW

.7U_0402_6.3V6M

+

1.8VALW

1

C 1U_0201_6.3V6M

2

C

lose to CP23

RTC Bat t er y

+3VL_RTC +RTCBATT

W=20mil s

1 2

RC141 0_0402_5%

1

C

C67

1U_0201_6.3V6M

2

Close to BR23

Saf t y s uggest i on r emove EE s i de , Keep P WR s i de

+

1.05VALW

1

C

C70

1U_0201_6.3V6M

2

C

lose to CP5

+

VCCDPHY_1.24V

V

CCDPHY_EC_1P2 4

W

@

C75

hen CNVi is not used in the design: VCCDPHY_1P24 pin shall be disconnected from the VCCLDOSRAM_IN_1P24 pin. The decoupling capacitor shall remain connected to the VCCDPHY_1P24 pin.

1 2

R

1 0_0201_5%CNVi@

S

ecurity Classification

I

ssued Date

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

018/04/09 2019/04/09

C

ompal Secret Data

D

eciphered Date

Compal Electronics, Inc.

T

itle

W

HL-U(9/12)Power

Size Document Number Re v

C

ustom

Date : Sheet

2

Date : Sheet

HL-U(9/12)Power

LA-H081P

1

0

.2

o

f

14 53Monday, October 22, 2018

f

14 53Monday, October 22, 2018

f

14 53Monday, October 22, 2018

5

4

3

2

1

+VCC_CO RE +VCC_CO RE

UC1L

AN9

VCCCORE5

AN10

VCCCORE1

D D

C C

S

VID ALERT

B B

AN24 AN26 AN27

AP2

AP9 AP24 AP26

AR5

AR6

AR7

AR8

AR10 AR25 AR27

AT9 AT24 AT26

AU5

AU6

AU7

AU8

AU9

AU24 AU25 AU26 AU27

AV2

AV5

AV7 AV10 AV27

AW5 AW6 AW7 AW8 AW9

AW10

BB9

BC24

AY9 BB24

CFLU-43E _BGA1528

@

VCCCORE2 VCCCORE3 VCCCORE4 VCCCORE6 VCCCORE9 VCCCORE7 VCCCORE8 VCCCORE13 VCCCORE14 V

CCCORE15

V

CCCORE16

V

CCCORE10

V

CCCORE11

V

CCCORE12

V

CCCORE19

V

CCCORE17

V

CCCORE18

V

CCCORE24

V

CCCORE25

V

CCCORE26

V

CCCORE27

V

CCCORE28

V

CCCORE20

V

CCCORE21

V

CCCORE22

V

CCCORE23

V

CCCORE30

V

CCCORE32

V

CCCORE33

V

CCCORE29

V

CCCORE31

V

CCCORE39

V

CCCORE40

V

CCCORE41

V

CCCORE42

V

CCCORE43

V

CCCORE34

R

SVD3

R

SVD4

R

SVD1

R

SVD2

1

2 of 20

+

1.05V_VC CST

VCCCORE35 VCCCORE36 VCCCORE37 VCCCORE38 VCCCORE44 VCCCORE45 VCCCORE48 VCCCORE49 VCCCORE50 VCCCORE46 VCCCORE47 V

CCCORE51

V

CCCORE52

V

CCCORE56

V

CCCORE57

V

CCCORE58

V

CCCORE59

V

CCCORE53

V

CCCORE54

V

CCCORE55

V

CCCORE63

V

CCCORE64

V

CCCORE60

V

CCCORE61

V

CCCORE62

V

CCCORE69

V

CCCORE65

V

CCCORE66

V

CCCORE67

V

CCCORE68

V

CCCORE70

V

CCCORE73

V

CCCORE71

V

CCCORE72

V

CCCORE74

V

CC_SENSE

V

12

AW24 AW25 AW26 AW27 AY24 AY26 BA5 BA7 BA8 BA25 BA27 BB2 BB26 BC5 BC6 BC7 BC9 BC10 BC26 BC27 BD5 BD8 BD10 BD25 BD27 BE9 BE24 BE25 BE26 BE27 BF2 BF9 BF24 BF26 BG27

AN6 AN5

SS_SENSE

AA3

IDALERT#

AA1

V

IDSCK

AA2

V

IDSOUT

Y3

R

SVD5

BG3

V

CCSTG1

P

lace the PU

resistors close to CPU

R

C147

56_0402 _5%

S

OC_SVID_A LERT#

V

R_SVID_CL K

V

R_SVID_DA TA

V

CCCORE_ SENSE [47]

V

SSCORE_ SENSE [47]

V

R_SVID_CL K [47]

+

1.05VS_V CCIO

+VCC_CO RE

Trace Length Match < 25 mils

+VCC_GT +VCC_GT

UC1M

A5

VCCGT8

A6

VCCGT9

A8

VCCGT10

A11

VCCGT1

A12

VCCGT2

A14

VCCGT3

A15

VCCGT4

A17

VCCGT5

A18

VCCGT6

A20

VCCGT7

AA9

VCCGT11

AB2

VCCGT13

AB8

V

AB9

V

AB10

V

AC8

V

AD9

V

AE8

V

AE9

V

AE10

V

AF2

V

AF8

V

AF10

V

AG8

V

AG9

V

AH9

V

AJ8

V

AJ10

V

AK2

V

AK9

V

AL8

V

AL9

V

AL10

V

AM8

V

B3

V

B4

V

B6

V

B8

V

B11

V

B14

V

B17

V

B20

V

C2

V

C3

V

C6

V

C7

V

C8

V

C11

V

C12

V

C14

V

C15

V

C17

V

C18

V

C20

V

D4

V

D7

V

D11

V

D12

V

D14

V

Y10

V

CFLU-43E _BGA1528

@

CCGT14 CCGT15 CCGT12 CCGT16 CCGT17 CCGT19 CCGT20 CCGT18 CCGT22 CCGT23 CCGT21 CCGT24 CCGT25 CCGT26 CCGT28 CCGT27 CCGT29 CCGT30 CCGT32 CCGT33 CCGT31 CCGT34 CCGT39 CCGT40 CCGT41 CCGT42 CCGT35 CCGT36 CCGT37 CCGT38 CCGT49 CCGT51 CCGT52 CCGT53 CCGT54 CCGT43 CCGT44 CCGT45 CCGT46 CCGT47 CCGT48 CCGT50 CCGT62 CCGT63 CCGT55 CCGT56 CCGT57 CCGT119

V

CCGT_SENSE

V

SSGT_SENSE

1

3 of 20

VCCGT58 VCCGT59 VCCGT60 VCCGT61 VCCGT64 VCCGT69 VCCGT70 VCCGT71 VCCGT72 VCCGT65 VCCGT66 VCCGT67 V

CCGT68

V

CCGT73

V

CCGT74

V

CCGT75

V

CCGT76

V

CCGT77

V

CCGT78

V

CCGT79

V

CCGT87

V

CCGT88

V

CCGT89

V

CCGT90

V

CCGT80

V

CCGT81

V

CCGT82

V

CCGT83

V

CCGT84

V

CCGT85

V

CCGT86

V

CCGT95

V

CCGT96

V

CCGT91

V

CCGT92

V

CCGT93

V

CCGT94

V

CCGT98

V

CCGT97

V

CCGT100

V

CCGT101 V

CCGT99

V

CCGT102

V

CCGT104

V

CCGT105

V

CCGT106

V

CCGT103

V

CCGT107

V

CCGT108

V

CCGT109

V

CCGT111

V

CCGT112

V

CCGT110

V

CCGT114

V

CCGT113

V

CCGT115

V

CCGT116

V

CCGT117

V

CCGT118

V

CCGT120

D15 D17 D18 D20 E4 F5 F6 F7 F8 F11 F14 F17 F20 G11 G12 G14 G15 G17 G18 G20 H5 H6 H7 H8 H11 H12 H14 H15 H17 H18 H20 J7 J8 J11 J14 J17 J20 K2 K11 L7 L8 L10 M9 N7 N8 N9 N10 P2 P8 R9 T8 T9 T10 U8 U10 V2 V9 W8 W9 Y8

E3 D2

V

CCGT_SE NSE

V

SSGT_SE NSE

V

CCGT_SE NSE [47 ]

V

SSGT_SE NSE [47]

T

race Length Match < 25 mils

S

OC_SVID_A LERT#

SVID DATA

V

A A

R_SVID_DA TA

5

1 2

R

C148 220_0 402_5%

+

1.05V_VC CST

12

V

R_ALERT # [47]

Place the PU resistors close to CPU

R

C149

100_040 2_1%

V

R_SVID_DA TA [47]

4

(To VR)

S

ecurity Classification

2

018/04/0 9 2019/04/ 09

I

ssued Date

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

018/04/0 9 2019/04/ 09

3

C

ompal Secret Data

Deciphered Date

Compal Electronics, Inc.

T

itle

W

HL-U(10/12)Power,SVID

Size Document Nu mber Re v

C

ustom

Date : S heet

2

Date : S heet

HL-U(10/12)Power,SVID

LA-H081P

15 53Monday, October 22, 20 18

1

0

.2

o

f

5

D D

UC1R

CR34

VSS_1

BT5

VSS_2

BY5

VSS_3

CP35

VSS_4

CM37

V

SS_5

CK37

V

SS_6

AW1

V

SS_7

CM1

V

SS_8

BD6

V

SS_9

AY4

V

SS_10

B34

V

SS_11

E35

V

SS_12

A4

V

SS_13

AE24

V

SS_14

AE26

V

SS_15

AF25

V

SS_16

AG24

V

SS_17

AG26

V

SS_18

AH24

V

SS_19

AH25

V

SS_20

B2

V

SS_21

B36

V

SS_22

C36

V

SS_23

C37

V

C C

B B

SS_24

CN1

V

SS_25

CN2

V

SS_26

CN37

V

SS_27

CP2

V

SS_28

D1

V

SS_29

A32

V

SS_30

F33

V

SS_31

A3

V

SS_32

BJ7

V

SS_33

CJ36

V

SS_34

A36

V

SS_35

BK10

V

SS_36

CJ4

V

SS_37

AB27

V

SS_38

BK2

V

SS_39

CK1

V

SS_40

AB3

V

SS_41

BK28

V

SS_42

AB30

V

SS_43

BK3

V

SS_44

CK4

V

SS_45

AB33

V

SS_46

BK33

V

SS_47

CK7

V

SS_48

AB36

V

SS_49

BK4

V

SS_50

CL2

V

SS_51

AB4

V

SS_52

BK7

V

SS_53

CM13

V

SS_54

AB7

V

SS_55

BL25

V

SS_56

CM17

V

SS_57

AC10

V

SS_58

BL28

V

SS_59

CM21

V

SS_60

AC27

V

SS_61

BL29

V

SS_62

CM25

V

SS_63

AC30

V

SS_64

BL30

V

SS_65

CM29

V

SS_66

BL31

V

SS_67

CM31

V

SS_68

AD33

V

SS_69

BL32

V

SS_70

CM33

V

SS_71

AD35

V

SS_72

CFLU-43E _BGA1528

@

1

7 of 20

VSS_73 VSS_74 VSS_75 VSS_76 V

SS_77

V

SS_78

V

SS_79

V

SS_80

V

SS_81

V

SS_82

V

SS_83

V

SS_84

V

SS_85

V

SS_86

V

SS_87

V

SS_88

V

SS_89

V

SS_90

V

SS_91

V

SS_92

V

SS_93

V

SS_94

V

SS_95

V

SS_96

V

SS_97

V

SS_98

V

SS_99

V

SS_100

V

SS_101

V

SS_102

V

SS_103

V

SS_104

V

SS_105

V

SS_106

V

SS_107

V

SS_108

V

SS_109

V

SS_110

V

SS_111

V

SS_112

V

SS_113

V

SS_114

V

SS_115

V

SS_116

V

SS_117

V

SS_118

V

SS_119

V

SS_120

V

SS_121

V

SS_122

V

SS_123

V

SS_124

V

SS_125

V

SS_126

V

SS_127

V

SS_128

V

SS_129

V

SS_130

V

SS_131

V

SS_132

V

SS_133

V

SS_134

V

SS_135

V

SS_136

V

SS_137

V

SS_138

V

SS_139

V

SS_140

V

SS_141

V

SS_142

V

SS_143

V

SS_144

BL7 AE25 BM33 CM5 AE27 BM35 CM9 AE30 BM36 CN13 AE7 BM9 CN17 AF27 BN30 CN21 AF3 BN7 CN25 AF30 CN29 AF33 BP15 AF36 AF4 CN5 AF7 BP25 CN9 AG10 BP3 CP1 BP32 CP11 AH27 BP33 CP13 AH28 BP4 CP15 AH29 BP7 CP19 AH30 CP21 AH31 BR19 CP27 AH33 BR25 AH35 CP37 AJ25 BT15 AJ28 BT16 CP9 AJ7 CR2 AK3 CR36 AK33 D21 AK36 BT25 D25 AK4 BT28 AL28 BT33 D5 AL29

4

UC1S

BT35

VSS_145

D6

VSS_146

AL32

VSS_147

BT36

VSS_148

D8

VSS_149

AL7

V

SS_150

D9

V

SS_151

AM10

V

SS_152

BU11

V

SS_153

E23

V

SS_154

AM28

V

SS_155

E27

V

SS_156

AM33

V

SS_157

BU23

V

SS_158

E29

V

SS_159

AM35

V

SS_160

BU24

V

SS_161

E31

V

SS_162

BU25

V

SS_163

E33

V

SS_164

AN25

V

SS_165

BU7

V

SS_166

E9

V

SS_167

AN28

V

SS_168

BV11

V

SS_169

F12

V

SS_170

AN29

V

SS_171

F15

V

SS_172

AN30

V

SS_173

F18

V

SS_174

AN31

V

SS_175

BV3

V

SS_176

F2

V

SS_177

AN7

V

SS_178

BV31

V

SS_179

F21

V

SS_180

AN8

V

SS_181

BV33

V

SS_182

F24

V

SS_183

BV4

V

SS_184

F3

V

SS_185

AP3

V

SS_186

BW11

V

SS_187

F4

V

SS_188

AP33

V

SS_189

BW15

V

SS_190

G21

V

SS_191

AP36

V

SS_192

G27

V

SS_193

AP4

V

SS_194

G33

V

SS_195

AR28

V

SS_196

G35

V

SS_197

G36

V

SS_198

AT33

V

SS_199

BW24

V

SS_200

G9

V

SS_201

AT35

V

SS_202

H21

V

SS_203

AT36

V

SS_204

BW7

V

SS_205

H27

V

SS_206

AT4

V

SS_207

BY11

V

SS_208

AU10

V

SS_209

BY15

V

SS_210

H9

V

SS_211

AU28

V

SS_212

BY22

V

SS_213

J12

V

SS_214

AU29

V

SS_215

J15

V

SS_216

CFLU-43E _BGA1528

@

1

8 of 20

3

VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 V

SS_222

V

SS_223

V

SS_224

V

SS_225

V

SS_226

V

SS_227

V

SS_228

V

SS_229

V

SS_230

V

SS_231

V

SS_232

V

SS_233

V

SS_234

V

SS_235

V

SS_236

V

SS_237

V

SS_238

V

SS_239

V

SS_240

V

SS_241

V

SS_242

V

SS_243

V

SS_244

V

SS_245

V

SS_246

V

SS_247

V

SS_248

V

SS_249

V

SS_250

V

SS_251

V

SS_252

V

SS_253

V

SS_254

V

SS_255

V

SS_256

V

SS_257

V

SS_258

V

SS_259

V

SS_260

V

SS_261

V

SS_262

V

SS_263

V

SS_264

V

SS_265

V

SS_266

V

SS_267

V

SS_268

V

SS_269

V

SS_270

V

SS_271

V

SS_272

V

SS_273

V

SS_274

V

SS_275

V

SS_276

V

SS_277

V

SS_278

V

SS_279

V

SS_280

V

SS_281

V

SS_282

V

SS_283

V

SS_284

V

SS_285

V

SS_286

V

SS_287

V

SS_288

V

SS_289

BY25 J18 AU32 BY28 J21 AV25 BY33 J24 AV28 BY35 J33 AV3 BY36 J36 AV33 J6 AV36 C1 K21 AV4 C21 K22 AV6 C25 K24 AV8 C29 K25 AW28 C33 K27 AW29 C4 K28 AW3 C9 K29 AW30 CA11 K3 AW31 CA15 K30 AY33 CA22 K31 AY35 K32 B12 K4 B15 CA25 K9 B18 CB11 L27 B21 L33 B23 L35 B25 CB18 L36 B27 CB19 L6 B29 CB2 N25 B31 CB20 N27 CB25

2

UC1T

N6

VSS_290

B37

VSS_291

CB3

VSS_292

P10

VSS_293

B5

V

CB33

V

P3

V

B7

V

CB4

V

P33

V

B9

V

CB7

V

P36

V

BA10

V

CC11

V

P4

V

BA28

V

P7

V

BA3

V

CC20

V

R27

V

BB3

V

CC25

V

R28

V

BB33

V

CC28

V

R29

V

BB36

V

CC31

V

R30

V

BB4

V

CC7

V

R31

V

BC25

V

CD11

V

T27

V

CD12

V

T30

V

BC29

V

CD14

V

T33

V

T35

V

BC32

V

CD24

V

T36

V

CD25

V

T7

V

BC8

V

CE33

V

U26

V

BD28

V

CE35

V

U7

V

BD33

V

CE36

V

V26

V

BD35

V

CE7

V

V27

V

BD36

V

CF11

V

V3

V

BE10

V

CF14

V

V30

V

BE28

V

CF19

V

V33

V

BE29

V

CF2

V

V36

V

BE3

V

CFLU-43E _BGA1528

@

SS_294 SS_295 SS_296 SS_297 SS_298 SS_299 SS_300 SS_301 SS_302 SS_303 SS_304 SS_305 SS_306 SS_307 SS_308 SS_309 SS_310 SS_311 SS_312 SS_313 SS_314 SS_315 SS_316 SS_317 SS_318 SS_319 SS_320 SS_321 SS_322 SS_323 SS_324 SS_325 SS_326 SS_327 SS_328 SS_329 SS_330 SS_331 SS_332 SS_333 SS_334 SS_335 SS_336 SS_337 SS_338 SS_339 SS_340 SS_341 SS_342 SS_343 SS_344 SS_345 SS_346 SS_347 SS_348 SS_349 SS_350 SS_351 SS_352 SS_353 SS_354 SS_355 SS_356 SS_357 SS_358 SS_359 SS_360 SS_361

1

9 of 20

VSS_362 VSS_363 VSS_364 VSS_365 V

SS_366

V

SS_367

V

SS_368

V

SS_369

V

SS_370

V

SS_371

V

SS_372

V

SS_373

V

SS_374

V

SS_375

V

SS_376

V

SS_377

V

SS_378

V

SS_379

V

SS_380

V

SS_381

V

SS_382

V

SS_383

V

SS_384

V

SS_385

V

SS_386

V

SS_387

V

SS_388

V

SS_389

V

SS_390

V

SS_391

V

SS_392

V

SS_393

V

SS_394

V

SS_395

V

SS_396

V

SS_397

V

SS_398

V

SS_399

V

SS_400

V

SS_401

V

SS_402

V

SS_403

V

SS_404

V

SS_405

V

SS_406

V

SS_407

V

SS_408

V

SS_409

V

SS_410

V

SS_411

V

SS_412

V

SS_413

V

SS_414

V

SS_415

V

SS_416

V

SS_417

V

SS_418

V

SS_419

V

SS_420

V

SS_421

V

SS_422

V

SS_423

V

SS_424

V

SS_425

V

SS_426

V

SS_427

V

SS_428

V

SS_429

V

SS_430

V

SS_431

V

SS_432

V

SS_433

CF23 V4 BE30 CF28 W10 BE31 CF3 W27 CF4 W30 BF3 CG33 W7 BF33 CG7 BF36 Y26 BF4 CH31 Y27 BG25 Y30 BG28 CJ11 Y33 CJ14 Y35 BH28 CJ19 Y7 BH29 CJ23 BH32 CJ28 BH33 CJ33 BH35 CJ35 BP19 BR16 BY18 BY19 CC16 BU16 CC14 BR22 BU20 CD20 BT14 BP12 CB24 CC24 J5 U24 BD7 AR4 AU4 AW4 BA6 BC4 BE4 BE8 BA4 BD4 BG4 CJ2 CJ3 AM5 CM4 AC5 AG5 CR6

1

A A

S

ecurity Classification

2

018/04/0 9 2019/04/ 09

I

ssued Date

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

018/04/0 9 2019/04/ 09

3

C

ompal Secret Data

Deciphered Date

Compal Electronics, Inc.

T

itle

W

HL-U(11/12)GND

Size Document Nu mber Re v

C

ustom

Date : S heet

2

Date : S heet

HL-U(11/12)GND

LA-H081P

1

0

.2

o

f

16 53Monday, October 22, 20 18

f

16 53Monday, October 22, 20 18

f

16 53Monday, October 22, 20 18

LENOVO FLEX 14 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual