Lenovo CW4, F31, F31A Schematic
1
2
3
4
5
6
7
8
PCB STACK UP
CW4 BLOCK DIAGRAM
01
LAYER 1 : TOP
LAYER 2 : SGND1
A A
LAYER 3 : IN1
LAYER 4 : IN2
LAYER 5 : VCC
CPU
Merom
478P (uPGA)/35W
PAGE 3,4
LAYER 6 : IN3
LAYER 7 : SGND2
CPU THERMAL
SENSOR
PAGE 3
CLK_CPU_BCLK,CLK_CPU_BCLK#
CLK_MCH_BCLK,CLK_MCH_BCLK#
DREFCLK,DREFCLK#
DREFSSCLK,DREFSSCLK#
14.318MHz
CLOCK GEN
ICS9LPRS365AGLFT
64pinsTSSOP
PAGE 2
LAYER 8 : BOT
NVDIA NB8M
820p FCBGA
PAGE 14,15,16,17
DDRII-SODIMM1
DDRII 533,667 MHz
PCI-Express 16X
NORTH BRIDGE
PAG 13,14
B B
DDRII-SODIMM2
DDRII 533,667 MHz
PAG 13,14
Crestline
PAGE
5,6,7,8,9,10,11
DMI LINK
TV_OUT
CRT_OUT
LVDS(1 Channel)
CRT/S-VIDEO
Panel Connector
PAGE 22
PAGE 23
NBSRCCLK, NBSRCCLK#
USB2.0
SYSTEM CHARGER(MAX8724)
PAGE 41
SYSTEM POWER ISL6236
PAGE 42
C C
DDR II SMDDR_VTERM
1.8V/1.8VSUS(MAX8632ETI+)
SATA - HDD
PAGE 29
PATA-
CD-ROM
PAGE 29
SATA
PATA
(66/100/133)
PAGE 46
+1.05V / +1.5V ( ISL6269A )
PAGE 44, 45
SOUTH BRIDGE
ICH-8M
PAG 21,22,23,24
LPC
Two-element
microphone
PAGE 27
VGACORE(1.0V)MAX1993ETG
PAGE 45
CPU CORE MAX8770
PAGE 44
D D
Keyboard/ Touch Pad
PAGE 33
CIR
G-SENSOR
PAGE 36
PAGE 25
ITE KBC
ITE 8512
PAGE 35
Audio Jacks
(Phone/SPDIF/
MIC)
PAGE 27
BluetoothX1USB2.0 I/O Ports
PAGE 32
X3
PCI BUS / 33MHz
PCI-E
Azalia
Realtek
ALC 268
PAGE 26
AUDIO
Amplifier
MDC DAA
SI3080
PAGE 28PAGE 27
PAGE 29
Mini PCI-E
Card
PCI-E Mini
Card
(WLAN/WAN)
Camera
PAG 32
X1
LAN
Broadcom
PCIE-LAN
BCM5787/5906
(10/100/GagaLAN)
WLAN Card x1
WWAN Card x1
Express Card x1
Express
Card
(NEW CARD)
PAGE 34 PAGE 30,31 PAGE 32
RJ45
PAGE 31
PCI ROUTING
TABLE
IDSEL
AD25 RICOH832REQ0# / GNT0#
INTERUPT
INTE#,INTF#
RICOH
RICOH 832
PAGE 24,25
IEEE1394
CONN
DEVICE
Memory
CardReader
PAGE 25PAGE 24
X-Bus
FAN
Flash
PAGE 35PAGE 33
1
2
3
4
Jack to
Speaker
5
MODEM RJ 11
PAGE 31PAGE 27
6
PROJECT : CW4
Size Document Number Rev
Date: Sheet
Quanta Computer Inc.
BLOCK DIAGRAM
7
144Friday, November 03, 2006
of
8
1ACustom
5
Board Stack up Description
PCB Layers
4
3
2
1
02
Voltage Rails
Layer 1
Layer 2
D D
Layer 3
Layer 4
Layer 5
Layer 6
Layer 7
Layer 8
TOP
GND
IN1
IN2
SVCC
IN3
GND
BOTTOM
Power On Sequencing Timing Diagram
VID
Tboot
Tsft_star_vcc
Vboot
Tboot-vid-tr
Tcpu_up
Vid
VRON
VCC_CORE
C C
CPU_UP
Voltage Rails
VCC_CORE
+1.5V
+1.05V
5V_S5/3V_S5/1.5V_S5
5VSUS/3VSUS/1.8VSUS X X SUSON
SMDDR_VTERM/+2.5V/+3V/+5V/+12V X MAINON
+VCC_GFX_CORE/+1.2V_GFX_PCIE X MAINON
LANVCC
3VPCU
5VPCU
ON S0~S2
ON S3
ON S4
ON S5
X
X
X
X
X
X
X
XX
XXX
X
X
X
X
X
X
Control signal
VRON
MAINONX
MAINON
S5_ON
LAN_ON
VL
VL
Vccp
Vccp_UP
Vccgmch
GMCHPWRGD
CLK_ENABLE#
IMVP4_PWRGD
Tvccp_up
Tgmch_pwrgd
Tcpu_pwrgd
ACIN
5VPCU/3VPCU
NBSWON#
DNBSWON#
ACIN POWER ON TIMING
To ICH7
REQ# / GNT#
IDSEL# InterruptsPCI DEVICE
INT E#/F#REQ0# / GNT0#AD25RICOH832
YONAH Power-up Timing Specifications
RESET#
Td
B B
BCLK
Tc
Te
PWRGOOD
Tf
Vcc,boot
VCC
Ta
Tb
VID[5:0]
S5_ON
RSMRST#
SUSB#,SUSC#
SUSON
MAINON
VSUS,VCC
VRON
+1.5V/+1.05V
VCC_CORE
CLK_EN#
PWROK
PLTRST#\PCIRST#
99ms < t 214
To ICH7
From ICH7
From 97551
From 97551
From 97551
To clock generator
To GMCH/other PCI device
A A
VCCP
Ta=VCC and VCCP asseration to VID[5:0] vaild
Tb=VID[5:0] stable to VCC vaild
Tc=BCLK stable to PWRGOOD assertion
Td=PWRGOOD to RESET# de-assertion time
Te=Vcc,boot vaild to PWRGOOD assertion time
5
Size Document Number Rev
4
3
2
Date: Sheet
PROJECT : CW4
Quanta Computer Inc.
SYSTEM INFORMATION
244Friday, November 03, 2006
1
of
1ACustom
1
+3V
L36
1 2
HI0805R800R-00
A A
L35
1 2
HI0805R800R-00
L34
1 2
HI0805R800R-00
+3V
B B
C C
D D
R215
10K/04
1 2
PCLK_MINI_LPC
R218
*4.7K/04
0=overclocking
of CPU and
SRC Allowed
1 = overclocking
of CPU and SRC
not Allowed
+3V
R208
10K/04
1 2
FCTSEL1
R205
*10K/04
1 2
0=UMA
1 = External VGA
Disable ITP
10K/04
R216
1 2
ITP_EN
12
12
C396
22U/10V/12
12
C377
22U/10V/12
C350
22U/10V/12
PDAT_SMB21,33
PCLK_SMB21,33
12
12
GCLK_SEL = FCTSEL1
FCTSEL1
(PIN13)
0=UMA
1 = External
VGA
CPU Clock select
+1.05V
+1.05V
+1.05V
1
2
C346
.1U/10V/04
12
C375
.1U/10V/04
C361
.1U/10V/04
12
C364
.1U/10V/04
VDDCPU
12
C338
.1U/10V/04
+3V
Q20
2
3
2N7002E/CH2507SPT
+3V
Q19
2
3
2N7002E/CH2507SPT
12
C378
.1U/10V/04
12
C368
.1U/10V/04
R241
12
C372
.1U/10V/04
12
C348
.1U/10V/04
R242
10K
10K
CGDAT_SMB
1
CGCLK_SMB
1
PIN14
DOT96C
DOT96T SRCT1/LCDT_100
SRCC0
SRCT0
CPU_BSEL04
CPU_BSEL14 MCH_BSEL1 7
CPU_BSEL24 MCH_BSEL2 7
2
SRCT1/LCDT_100
R194 0/04
R197 *56/04
R198 1K/04
R230 0/04
R231 *0/04
R226 1K/04
R240 0/04
R238 *0/04
R237 1K/04
+CK_VDD_MAIN
12
C389
.1U/10V/04
12
C359
.1U/10V/04
CK_PWG21
PIN17
27Mout-NSS
3
+CK_VDD_MAIN2
12
C363
.1U/10V/04
CGCLK_SMB14,35
CGDAT_SMB14,35
CLK_BSEL0
CLK_BSEL1
CLK_BSEL2
3
CLK_BSEL1
PIN18PIN13
27Mout-SS
R196 0/04
R224 0/04
R234 0/04
+CK_VDD_MAIN
VDDCPU
+CK_VDD_MAIN2
R223
CGCLK_SMB
CGDAT_SMB
4
CG_XIN
CG_XOUT
0
4
12
FSB
CG_XIN
C391
27P/50V/04
16
61
39
55
20
26
45
36
49
48
60
59
56
57
64
63
15
19
11
52
58
23
29
42
Y2
1 2
14.318MHZ
U7
VDDPLL3
9
VDD48
2
VDDPCI
VDDREF
VDDSRC
VDDCPU
VDDPLL3I/O
VDDSRCI/O
VDDSRCI/O
VDDSRCI/O
VDDCPU_IO
NC
X1
X2
CK_PWRGD/PD#
FSLB/TEST_MODE
SCLK
SDATA
GND
GND
GND48
GNDCPU
8
GNDPCI
GNDREF
GNDSRC
GNDSRC
GNDSRC
ICS9LPRS365BGLFT/SLG8SP512T
CK505
FSC FSB
MCH_BSEL0 7
1330
0
0
0
00
1
1
1
5
CG_XOUT
12
C392
27P/50V/04
CPUT2_ITP/SRCT8
CPUT2_ITP/SRCC8VDD96I/O
27MHz_Nonss/SRCCLK1/SE1
27Mhz_ss/SRCCLC1/SE2
SRCCLKT2/SATACL
SRCCLKC2/SATACL
SRCCLKT11/CR#_H
SRCCLKC11/CR#_G
PCICLK4/27_SELECT
CPUCLKT0
CPUCLKC0
CPUCLKT1
CPUCLKC1
DOTT_96/SRCT0
DOTC_96/SRCC0
SRCCLKT3/CR#_C
SRCCLKC3/CR#_D
SRCCLKT4
SRCCLKC4
PCI_STOP#
CPU_STOP#
SRCCLKT6
SRCCLKC6
SRCCLKT7/CR#_F
SRCCLKC7/CR#_E
SRCCLKT9
SRCCLKC9
SRCCLKT10
SRCCLKC10
PCICLK0/CR#_A
PCICLK1/CR#_B
PCICLK2/TME
PCICLK3
PCI_F5/ITP_EN
USB_48MHZ/FSLA
FSLC/TST_SL/REF
6
CLK_3GPLLREQ#
NEW-CARD_CLK_REQ#
PCIE_LANREQ#
RHCLK_CPU
54
RHCLK_CPU#
53
RHCLK_MCH
51
RHCLK_MCH#
50
CPU_ITP
47
CPU_ITP#
4612
R_DOT96
13
R_DOT96#
14
R_DREFSSCLK
17
R_DREFSSCLK#
18
RSRC_SATA
21
RSRC_SATA#
22
R_CLK_PCIE_VGA
24
R_CLK_PCIE_VGA#
25
RSRC1_LAN
27
RSRC1_LAN#
28
PM_STPPCI#
38
PM_STPCPU#
37
RSRC_ICH
41
RSRC_ICH#
40
CLK_PCIE_MINI_
44
CLK_PCIE_MINI_#
43
RSRC_MCH
30
RSRC_MCH#
31
CLK_PCIE_NEW
34
CLK_PCIE_NEW#
35
NEW-CARD_CLK_REQ#_R
33
CLK_3GPLLREQ#_R
32
R_PCLK_8512
1
3
PCLK_MINI_LPC
4
PCI_ICH
5
FCTSEL1
6
ITP_EN
7
10
62
internal have
already build-in
33ohm damping
resistor
RP49 4P2R-S-0
RP47 4P2R-S-0
RP45 *4P2R-S-0
RP48 *4P2R-S-0
RP46 *4P2R-S-0
RP43 4P2R-S-0
RP41 *4P2R-S-0
RP39 4P2R-S-0
RP40 4P2R-S-0
RP42 4P2R-S-0
RP37 4P2R-S-0
RP38 4P2R-S-0
FSA
FSC
FSA CPU SRC PCI
1100
10
1
1
1
0
0
033
0
1
0
1
1
5
133
166
200
266
333
400
RSVD
100
100
100
100
100
100
100
100
33
33
33
33
33
33
6
7
R171 10K/04
R167 10K/04
R232 10K/04
4
3
2
1
4
3
2
1
4
3
2
1
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
4
3
2
1
4
3
2
1
2
1
4
3
2
1
4
3
R168 475/F/03
R164 475/F/03
R239 33/04
R236 475/F/03
R219 33/04
T71
R233 33/04
R206 33/04
R204 33/04
R200 4.7K/04
R225 4.7K/04
R228 33/04
C395 *33P/50V/04
C394 *33P/50V/04
C369 *33P/50V/04
C384 *33P/50V/04
C367 *33P/50V/04
C390 *33P/50V/04
12
12
12
CLK_CPU_BCLK 4
CLK_CPU_BCLK# 4
CLK_MCH_BCLK 6
CLK_MCH_BCLK# 6
CLK_CPU_ITP
CLK_CPU_ITP#
DREFCLK 7
DREFCLK# 7
DREFSSCLK 7
DREFSSCLK# 7
CLK_PCIE_SATA 19
CLK_PCIE_SATA# 19
CLK_PCIE_VGA 15
CLK_PCIE_VGA# 15
CLK_PCIE_LAN 31
CLK_PCIE_LAN# 31
PM_STPPCI# 21
PM_STPCPU# 21
CLK_PCIE_ICH 20
CLK_PCIE_ICH# 20
CLK_PCIE_MINI 35
CLK_PCIE_MINI# 35
CLK_PCIE_3GPLL 7
CLK_PCIE_3GPLL# 7
CLK_PCIE_NEW_C 33
NEW-CARD_CLK_REQ#
CLK_3GPLLREQ#
CLK_PCIE_NEW_C# 33
PCLK_LPC_8512 36
PCLK_LPC_DEBUG 35
PCI_CLK_5C832 25
PCLK_ICH 20
CLK_BSEL0
CLK_BSEL2
+3V
T68
T69
CLKUSB_48 21
14M_ICH 21
PCLK_LPC_8512
PCI_CLK_5C832
PCLK_ICH
PCLK_LPC_DEBUG
CLKUSB_48
14M_ICH
8
NEW-CARD_CLK_REQ# 33
CLK_3GPLLREQ# 7
PCIE_LANREQ# 31
for EMI
PROJECT : CW4
Size Document Number Rev
Date: Sheet
Quanta Computer Inc.
CLOCK GENERATOR
7
344Friday, November 03, 2006
8
03
1ACustom
of
1
2
3
4
5
6
7
8
H_THERMDA
H_THERMDC
444Friday, November 03, 2006
04
10/20mils
of
8
1ACustom
H_D#[0..63]
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#[0..63]
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
COMP0
R465 27.4/F/04
COMP1
R461 54.9/F/04
COMP2
R469 27.4/F/04
COMP3
R471 54.9/F/04
1
VCC
2
DXP
3
DXN
5
GND
12
12
12
12
C513
.1U/10V/04
C512
2200P/50V/06
PROJECT : CW4
Quanta Computer Inc.
Merom (HOST BUS)
H_D#[0..63] 6
H_DSTBN#2 6
H_DSTBP#2 6
H_DINV#2 6
H_D#[0..63] 6
H_DSTBN#3 6
H_DSTBP#3 6
H_DINV#3 6
H_DPRSTP# 7,19,40
H_DPSLP# 19
H_DPWR# 6
H_PWRGD 19
H_CPUSLP# 6
PM_PSI# 40
1 2
1 2
1 2
5
H_D#[0..63]
H_D#[0..63]
T22*PAD
12
T1*PAD
Q35
3
2N7002E/CH2507SPT
Q34
3
2N7002E/CH2507SPT
1 2
R452 *0/06
Q32
3
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
V_CPU_GTLREF
CPU_TEST1
CPU_TEST2
CPU_TEST3
CPU_TEST4
CPU_TEST5
CPU_TEST6
+3V
2
+3V
2
+3V
2
*2N7002E
1
1
1
AA4
AB2
AA3
D22
J4
L5
L4
K5
M3
N2
J1
N3
P5
P2
L2
P4
P1
R1
M1
K3
H2
K2
J3
L1
Y2
U5
R3
W6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
U2
V4
W3
V1
A6
A5
C4
D5
C6
B4
A3
M4
N5
T2
V3
B2
C3
D2
D3
F6
U22A
A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#
REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#
A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#
A20M#
FERR#
IGNNE#
STPCLK#
LINT0
LINT1
SMI#
RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
RSVD[09]
RSVD[10]
Merom CPU
DEFER#
ADDR GROUP
0
CONTROLXDP/ITP SIGNALS
RESET#
BPM[0]#
ADDR GROUP
1
BPM[1]#
BPM[2]#
BPM[3]#
THERMAL
PROCHOT#
THERMDA
THERMDC
ICH
THERMTRIP#
H CLK
BCLK[0]
BCLK[1]
RESERVED
ADS#
BNR#
BPRI#
DRDY#
DBSY#
BR0#
IERR#
INIT#
LOCK#
RS[0]#
RS[1]#
RS[2]#
TRDY#
HIT#
HITM#
PRDY#
PREQ#
TCK
TDO
TMS
TRST#
DBR#
H1
E2
G5
H5
F21
E1
F1
D20
B3
H4
C1
F3
F4
G3
G2
G6
E4
AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
TDI
AB3
AB5
AB6
C20
D21
A24
B25
C7
A22
A21
T13 *PAD
R23 56/04
H_IERR#
1 2
H_RESET#
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5
ITP_TCK
ITP_TDI
ITP_TDO
ITP_TMS
ITP_TRST#
ITP_DBRESET#
R26 75/04
CPU_PROCHOT#CPU_PROCHOT#
H_THERMDA
H_THERMDC
PM_THRMTRIP#
R488
1 2
12
56/04
H_ADS# 6
H_BNR# 6
H_BPRI# 6
H_DEFER# 6
H_DRDY# 6
H_DBSY# 6
H_BR0# 6
+1.05V
H_INIT# 19
H_LOCK# 6
H_RESET# 6
H_RS#0 6
H_RS#1 6
H_RS#2 6
H_TRDY# 6
H_HIT# 6
H_HITM# 6
T6 *PAD
T4 *PAD
T2 *PAD
T7 *PAD
T5 *PAD
T3 *PAD
SYS_RST# 21
+1.05V
CPU_PROCHOT# 38
PM_THRMTRIP# 7,19
+1.05V
CLK_CPU_BCLK 3
CLK_CPU_BCLK# 3
Layout Note:
Place voltage
divider within
0.5" of GTLREF
pin
+1.05V
R12
1K/F/04
1 2
R10
2K/F/04
1 2
H_D#[0..63]6
H_DSTBN#06
H_DSTBP#06
H_DINV#06
H_D#[0..63]6
H_DSTBN#16
H_DSTBP#16
H_DINV#16
R35 *1K/F/04
R28 *1K/F/04
C7 *0.1U/10V/04
R74 *0/04
CPU_BSEL03
CPU_BSEL13
CPU_BSEL23
H_A#[3..16]6
A A
H_ADSTB#06
H_REQ#[0..4]6
H_A#[17..35]6
B B
H_ADSTB#16
H_A20M#19
H_FERR#19
H_IGNNE#19
H_STPCLK#19
H_INTR19
H_NMI19
H_SMI#19
C C
H_A#[3..16]
H_REQ#[0..4]
H_A#[17..35]
T20*PAD
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
Populate ITP700Flex for bringup
+1.05V
ITP_DBRESET#
12
R467
39/F/04
T23
12
*PAD
R472
150/04
R463 27/F/04
R466 649/F/04
ITP_TDI
IT
P_TMS
ITP_TDO
H_RESET#
12
R489
51/F/04
12
R470
51/04
ITP disable guidelines
Resistor Value
Signal Resistor Placement
D D
TDI
150 ohm +/- 5%
TMS
39 ohm +/- 1%
TRST#
500-680ohm +/- 5%
27 ohm +/- 1%
TCK
TDO
150 ohm +/- 5%
1
Connect To
Within 2.0" of the ITPVTT
Within 2.0" of the ITP
VTT
Within 2.0" of the ITP
GND
GND Within 2.0" of the ITP
Within 2.0" of the ITP
VTT
2
R80
12
12
+3V
12
*150/04
ITP_TCK
ITP_TRST#
CPU_PROCHOT#
PM_THRMTRIP#
3
Q1
5VSUS
*PDTC144EU
+1.05V
Q33
1 3
*MMBT3904
2
R451
*1K/F/04
1 2
2
R2
*330
13
SYS_SHDN#
4
VR_TT# 40
MBCLK36
THRM_CLK16
THRM_DATA16
MBDATA36
THERM_ALERT#21,41
SYS_SHDN#40,41
SYS_SHDN#
E22
E26
G22
G25
E25
E23
K24
G24
H22
K22
H23
H26
H25
N22
K25
P26
R23
M24
M23
P25
P23
P22
T24
R24
T25
N25
M26
N24
AD26
C23
D25
C24
AF26
AF1
A26
B22
B23
C21
6
F24
F23
J24
J23
F26
J26
L23
L22
L25
L26
R453
10K/04
U22B
D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#
D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#
GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
BSEL[0]
BSEL[1]
BSEL[2]
Merom CPU
R456
10K/04
Y22
D[32]#
AB24
D[33]#
V24
D[34]#
V26
D[35]#
V23
D[36]#
T22
D[37]#
U25
D[38]#
U23
D[39]#
Y25
D[40]#
W22
D[41]#
Y23
D[42]#
W24
D[43]#
W25
D[44]#
AA23
D[45]#
AA24
D[46]#
AB25
D[47]#
Y26
DSTBN[2]#
AA26
DSTBP[2]#
U22
DINV[2]#
AE24
D[48]#
AD24
D[49]#
AA21
D[50]#
AB22
D[51]#
AB21
D[52]#
AC26
D[53]#
AD20
D[54]#
AE22
D[55]#
AF23
D[56]#
AC25
D[57]#
AE21
D[58]#
AD21
D[59]#
AC22
D[60]#
AD23
D[61]#
AF22
D[62]#
AC23
D[63]#
AE25
DSTBN[3]#
AF24
DSTBP[3]#
AC20
DINV[3]#
R26
COMP[0]
U26
COMP[1]
AA1
COMP[2]
Y1
COMP[3]
E5
DPRSTP#
B5
DPSLP#
D24
DPWR#
D6
PWRGOOD
D7
SLP#
AE6
PSI#
25mils
U19
8
SCLK
7
SDA
6
ALERT#
4
OVERT#
MAX6657/GMT-781
ADDRESS: 98H
Size Document Number Rev
Date: Sheet
7
+3V
DATA GRP 0 DATA GRP 1
MISC
R454
200/F/06
LM86VCC
R455
*10K/04
DATA GRP 2DATA GRP 3
1
VCC_CORE
A A
VCC_CORE
C26
10U/4V/X6S_8
C18
10U/4V/X6S_8
C524
10U/4V/X6S_8
C17
10U/4V/X6S_8
8 inside cavity, north side, secondary layer.
VCC_CORE
C13
VCC_CORE
10U/4V/X6S_8
C71
10U/4V/X6S_8
B B
C12
10U/4V/X6S_8
C70
10U/4V/X6S_8
8 inside cavity, south side, secondary layer.
VCC_CORE
C25
C C
10U/4V/X6S_8
C53
10U/4V/X6S_8
6 inside cavity, north side, primary layer.
VCC_CORE
C536
10U/4V/X6S_8
C537
10U/4V/X6S_8
6 inside cavity, south side, primary layer.
+1.05V
D D
12
C29
.1U/10V/04
Layout out:
Place these inside socket cavity on North side secondary.
1
12
C52
.1U/10V/04
2
C525
10U/4V/X6S_8
C528
10U/4V/X6S_8
C16
10U/4V/X6S_8
C11
10U/4V/X6S_8
C66
10U/4V/X6S_8
C538
10U/4V/X6S_8
12
C28
.1U/10V/04
2
C526
10U/4V/X6S_8
C529
10U/4V/X6S_8
C15
10U/4V/X6S_8
C73
10U/4V/X6S_8
C67
10U/4V/X6S_8
C539
10U/4V/X6S_8
12
C51
.1U/10V/04
C68
10U/4V/X6S_8
C540
10U/4V/X6S_8
12
C27
.1U/10V/04
3
C527
10U/4V/X6S_8
C54
10U/4V/X6S_8
C14
10U/4V/X6S_8
C72
10U/4V/X6S_8
C69
10U/4V/X6S_8
C541
10U/4V/X6S_8
12
C50
.1U/10V/04
3
4
VCC_CORE VCC_CORE
C10
C12
C13
C15
C17
C18
D10
D12
D14
D15
D17
D18
E10
E12
E13
E15
E17
E18
E20
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AB9
AC10
AB10
AB12
AB14
AB15
AB17
AB18
A10
A12
A13
A15
A17
A18
A20
B10
B12
B14
B15
B17
B18
B20
A7
A9
B7
B9
C9
D9
E7
E9
F7
F9
4
U22C
VCC[001]
VCC[002]
VCC[003]
VCC[004]
VCC[005]
VCC[006]
VCC[007]
VCC[008]
VCC[009]
VCC[010]
VCC[011]
VCC[012]
VCC[013]
VCC[014]
VCC[015]
VCC[016]
VCC[017]
VCC[018]
VCC[019]
VCC[020]
VCC[021]
VCC[022]
VCC[023]
VCC[024]
VCC[025]
VCC[026]
VCC[027]
VCC[028]
VCC[029]
VCC[030]
VCC[031]
VCC[032]
VCC[033]
VCC[034]
VCC[035]
VCC[036]
VCC[037]
VCC[038]
VCC[039]
VCC[040]
VCC[041]
VCC[042]
VCC[043]
VCC[044]
VCC[045]
VCC[046]
VCC[047]
VCC[048]
VCC[049]
VCC[050]
VCC[051]
VCC[052]
VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCC[065]
VCC[066]
VCC[067]
Merom CPU
VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]
VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]
VCCA[01]
VCCA[02]
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
VCCSENSE
VSSSENSE
.
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
B26
C26
AD6
AF5
AE5
AF4
AE3
AF3
AE2
AF7
AE7
5
TP_VCCSENSE
TP_VSSSENSE
5
ICCODE:
for Merom processors
recommended design
target is 44A
ICCP:
1before vccore stable
peak current is 4.5A
2.after vccore stable
+1.05V
continue current is
2.5A
12
+
C534
330U/2.5V
ICCA 130mA
CPU_VID0 40
CPU_VID1 40
CPU_VID2 40
CPU_VID3 40
CPU_VID4 40
CPU_VID5 40
CPU_VID6 40
VCC_CORE
R5
100/F
R6
100/F
6
12
C547
.01U/25V/04
TP_VCCSENSE 40
TP_VSSSENSE 40
6
7
+1.5V
12
C544
10U/4V/08
U22D
A4
VSS[001]
A8
VSS[002]
A11
VSS[003]
A14
VSS[004]
A16
VSS[005]
A19
VSS[006]
A23
VSS[007]
AF2
VSS[008]
B6
VSS[009]
B8
VSS[010]
B11
VSS[011]
B13
VSS[012]
B16
VSS[013]
B19
VSS[014]
B21
VSS[015]
B24
VSS[016]
C5
VSS[017]
C8
VSS[018]
C11
VSS[019]
C14
VSS[020]
C16
VSS[021]
C19
VSS[022]
C2
VSS[023]
C22
VSS[024]
C25
VSS[025]
D1
VSS[026]
D4
VSS[027]
D8
VSS[028]
D11
VSS[029]
D13
VSS[030]
D16
VSS[031]
D19
VSS[032]
D23
VSS[033]
D26
VSS[034]
E3
VSS[035]
E6
VSS[036]
E8
VSS[037]
E11
VSS[038]
E14
VSS[039]
E16
VSS[040]
E19
VSS[041]
E21
VSS[042]
E24
VSS[043]
F5
VSS[044]
F8
VSS[045]
F11
VSS[046]
F13
VSS[047]
F16
VSS[048]
F19
VSS[049]
F2
VSS[050]
F22
VSS[051]
F25
VSS[052]
G4
VSS[053]
G1
VSS[054]
G23
VSS[055]
G26
VSS[056]
H3
VSS[057]
H6
VSS[058]
H21
VSS[059]
H24
VSS[060]
J2
VSS[061]
J5
VSS[062]
J22
VSS[063]
J25
VSS[064]
K1
VSS[065]
K4
VSS[066]
K23
VSS[067]
K26
VSS[068]
L3
VSS[069]
L6
VSS[070]
L21
VSS[071]
L24
VSS[072]
M2
VSS[073]
M5
VSS[074]
M22
VSS[075]
M25
VSS[076]
N1
VSS[077]
N4
VSS[078]
N23
VSS[079]
N26
VSS[080]
P3 A25
VSS[081] VSS[162]
Merom CPU
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[163]
.
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
AF25
PROJECT : CW4
Quanta Computer Inc.
Size Document Number Rev
Date: Sheet
7
Merom (POWER/NC)
8
544Friday, November 03, 2006
8
05
1ACustom
of
1
Digitally signed by fdsf
DN: cn=fdsf, o=fsdfsd,
ou=ffsdf,
email=fdfsd@fsdff,
c=US
Date: 2010.02.13
10:50:26 +07'00'
A A
+1.05V
12
R14
221/F/04
H_SWING
12
R15
100/F/04
B B
+1.05V
impedance 55 ohm
12
12
R13
24.9/F/04
12
Layout Note:
R460
54.9/F/04
H_RCOMP
R459
54.9/F/04
H_SCOMP
H_SCOMP#
H_RCOMP trace should be
C C
10-mil wide with 20-mil
spacing.
C22
.1U/10V/04
1 2
2
H_D#[0..63]4
+1.05V
1 2
12
R19
1K/F/04
R22
2K/F/04
12
C44
.1U/10V/04
H_D#[0..63]
H_RESET#4
H_CPUSLP#4
3
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_SWING
H_RCOMP
H_SCOMP
H_SCOMP#
T19*PAD
H_REF
M10
N12
P13
W10
AD12
AE3
AD9
AC9
AC7
AC14
AD11
AC11
AB2
AD7
AB1
AC6
AE2
AC5
AG3
AJ9
AH8
AJ14
AE9
AE11
AH12
AJ5
AH5
AJ6
AE7
AJ7
AJ2
AE5
AJ3
AH2
AH13
E2
G2
G7
M6
H7
H3
G4
F3
N8
H2
N9
H5
K9
M2
Y8
V4
M3
J1
N5
N3
W6
W9
N2
Y7
Y9
P4
W3
N1
Y3
B3
C2
W1
W2
B6
E5
B9
A9
4
U23A
H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63
H_SWING
H_RCOMP
H_SCOMP
H_SCOMP#
H_CPURST#
H_CPUSLP#
H_AVREF
H_DVREF
CRESTLINE_1p0
5
H_ADSTB#_0
H_ADSTB#_1
HOST
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35
H_ADS#
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
H_RS#_0
H_RS#_1
H_RS#_2
J13
B11
C11
M11
C15
F16
L13
G17
C14
K16
B13
L16
J17
B14
K19
P15
R17
B16
H20
L19
D17
M17
N16
J19
B18
E19
B17
B15
E17
C18
A19
B19
N19
G12
H17
G20
C8
E8
F12
D6
C10
AM5
AM7
H8
K7
E4
C6
G10
B7
K5
L2
AD13
AE13
M7
K3
AD2
AH11
L7
K2
AC2
AJ10
M14
E13
A11
H13
B12
E12
D7
D8
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
6
H_A#[3..35]
7
H_A#[3..35] 4
8
06
H_ADS# 4
H_ADSTB#0 4
H_ADSTB#1 4
H_BNR# 4
H_BPRI# 4
H_BR0# 4
H_DEFER# 4
H_DBSY# 4
CLK_MCH_BCLK 3
CLK_MCH_BCLK# 3
H_DPWR# 4
H_DRDY# 4
H_HIT# 4
H_HITM# 4
H_LOCK# 4
H_TRDY# 4
H_DINV#0 4
H_DINV#1 4
H_DINV#2 4
H_DINV#3 4
H_DSTBN#0 4
H_DSTBN#1 4
H_DSTBN#2 4
H_DSTBN#3 4
H_DSTBP#0 4
H_DSTBP#1 4
H_DSTBP#2 4
H_DSTBP#3 4
H_REQ#0 4
H_REQ#1 4
H_REQ#2 4
H_REQ#3 4
H_REQ#4 4
H_RS#0 4
H_RS#1 4
H_RS#2 4
D D
1
2
Layout Note:
Place the 0.1 uF
decoupling capacitor
within 100 mils from
GMCH pins.
3
PROJECT : CW4
Quanta Computer Inc.
Size Document Number Rev
4
5
Date: Sheet
6
Crestline_A (HOST)
7
644Friday, November 03, 2006
of
1ACustom
8
1
A A
WW22 update
--- MA14 needs
to be routed if
customers are
planning on
using 2Gb
technology and
width=8 (by 8)
DIMMs
SA_MA1413,14
SB_MA1413,14
T177 *PAD
T36 *PAD
Layout Note:
B B
DELAY_VR_PWRGOOD21,40
C C
PM_THRMTRIP#4,19
+3V
R98 10K/04
R96 10K/04
SM_RCOMP_VOH
12
D D
C106
.01U/25V/04
SM_RCOMP_VOL
12
C105
.01U/25V/04
Location of all MCH_CFG strap
resistors needs to be close to
minmize stub.
MCH_CFG_512
MCH_CFG_812
MCH_CFG_912
MCH_CFG_1212
MCH_CFG_1312
MCH_CFG_1612
MCH_CFG_1912
MCH_CFG_2012
12
C116
2.2U/10V/08
12
C141
2.2U/10V/08
1
R95 0
R78 0/04
R36 100/04
R32 *0/04
R66 0/04
PM_EXTTS#0
PM_EXTTS#1
+1.8VSUS_GMCH
12
R61
1K/F/04
12
R55
3.01K/F/04
12
R73
1K/F/04
PM_BMBUSY#21
H_DPRSTP#4,19,40
PM_EXTTS#014
PM_EXTTS#121
PLT_RST-R#20
DPRSLPVR21,40
1 2
1 2
MCH_BSEL03
MCH_BSEL13
MCH_BSEL23
T18*PAD
T163
*PAD
T17
*PAD
T9
*PAD
T21
*PAD
*PAD
T10
T12
*PAD
T11
*PAD
T16
*PAD
T24*PAD
PM_THRMTRIP#_GMCH
PM_DPRSLPVR_GMCH
T175*PAD
T173*PAD
T176*PAD
T171*PAD
T168*PAD
T161*PAD
T160*PAD
T157*PAD R103 4.7K/04
T156*PAD
T158*PAD
T162*PAD
T174*PAD
T172*PAD
T170*PAD
T169*PAD
T155*PAD
MCH_CLVREF
C160
.1U/10V/04
1 2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
PM_BMBUSY#_R
ICH_DPRSTP#_R
PLTRST_MCH#
TP_NC1
TP_NC2
TP_NC3
TP_NC4
TP_NC5
TP_NC6
TP_NC7
TP_NC8
TP_NC9
TP_NC10
TP_NC11
TP_NC12
TP_NC13
TP_NC14
TP_NC15
TP_NC16
+1.25V
12
R500
1K/F/04
12
R498
392/F/04
2
U23B
P36
RSVD1
P37
RSVD2
R35
RSVD3
N35
RSVD4
AR12
RSVD5
AR13
RSVD6
AM12
RSVD7
AN13
RSVD8
J12
RSVD9
AR37
RSVD10
AM36
RSVD11
AL36
RSVD12
AM37
RSVD13
D20
RSVD14
H10
RSVD20
B51
RSVD21
BJ20
RSVD22
BK22
RSVD23
BF19
RSVD24
BH20
RSVD25
BK18
RSVD26
BJ18
RSVD27
BF23
RSVD28
BG23
RSVD29
BC23
RSVD30
BD24
RSVD31
BJ29
SA-MA14
BE24
SB_MA14
BH39
RSVD34
AW20
RSVD35
BK20
RSVD36
C48
LVDSA_DATA#_3
D47
LVDSA_DATA_3
B44
RSVD39
C44
RSVD40
A35
RSVD41
B37
RSVD42
B36
RSVD43
B34
RSVD44
C34
RSVD45
P27
CFG_0
N27
CFG_1
N24
CFG_2
C21
CFG_3
C23
CFG_4
F23
CFG_5
N23
CFG_6
G23
CFG_7
J20
CFG_8
C20
CFG_9
R24
CFG_10
L23
CFG_11
J23
CFG_12
E23
CFG_13
E20
CFG_14
K23
CFG_15
M20
CFG_16
M24
CFG_17
L32
CFG_18
N33
CFG_19
L35
CFG_20
G41
PM_BM_BUSY#
L39
PM_DPRSTP#
L36
PM_EXT_TS#_0
J36
PM_EXT_TS#_1
AW49
PWROK
AV20
RSTIN#
N20
THERMTRIP#
G36
DPRSLPVR
BJ51
NC_1
BK51
NC_2
BK50
NC_3
BL50
NC_4
BL49
NC_5
BL3
NC_6
BL2
NC_7
BK1
NC_8
BJ1
NC_9
E1
NC_10
A5
NC_11
C51
NC_12
B50
NC_13
A50
NC_14
A49
NC_15
BK2 R32
NC_16
CRESTLINE_1p0
R24
20/F/04
SMRCOMPP
SMRCOMPN
R21
20/F/04
2
CFGRSVD
PM
NC
+1.8VSUS_GMCH
12
12
SM_CK#_0
SM_CK#_1
SM_CK#_3
SM_CK#_4
SM_CKE_0
SM_CKE_1
SM_CKE_3
SM_CKE_4
SM_CS#_0
SM_CS#_1
SM_CS#_2
SM_CS#_3
SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3
SM_RCOMP
DDR MUXINGCLKDMI
SM_RCOMP#
SM_RCOMP_VOH
SM_RCOMP_VOL
SM_VREF_0
SM_VREF_1
DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
PEG_CLK#
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3
GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VR_EN
GRAPHICS VIDME
CL_PWROK
SDVO_CTRL_CLK
SDVO_CTRL_DATA
CLK_REQ#
ICH_SYNC#
MISC
3
SM_CK_0
SM_CK_1
SM_CK_3
SM_CK_4
PEG_CLK
CL_CLK
CL_DATA
CL_RST#
CL_VREF
TEST_1
TEST_2
3
AV29
BB23
BA25
AV23
AW30
BA23
AW25
AW23
BE29
AY32
BD39
BG37
BG20
BK16
BG16
BE13
BH18
BJ15
BJ14
BE16
SMRCOMPP
BL15
SMRCOMPN
BK14
SM_RCOMP_VOH
BK31
SM_RCOMP_VOL
BL31
SMDDR_VREF_MCH
AR49
AW4
B42
C42
H48
H47
K44
K45
DMI_TXN0
AN47
DMI_TXN1
AJ38
DMI_TXN2
AN42
DMI_TXN3
AN46
DMI_TXP0
AM47
DMI_TXP1
AJ39
DMI_TXP2
AN41
DMI_TXP3
AN45
DMI_RXN0
AJ46
DMI_RXN1
AJ41
DMI_RXN2
AM40
DMI_RXN3
AM44
DMI_RXP0
AJ47
DMI_RXP1
AJ42
DMI_RXP2
AM39
DMI_RXP3
AM43
DFGT_VID_0
E35
DFGT_VID_1
A39
DFGT_VID_2
C38
DFGT_VID_3
B39
DFGT_VR_EN
E36
AM49
AK50
AT43
AN49
AM50
MCH_CLVREF
H35
K36
G39
G40
A37
M_A_CLK0 14
M_A_CLK1 14
M_B_CLK0 14
M_B_CLK1 14
M_A_CLK0# 14
M_A_CLK1# 14
M_B_CLK0# 14
M_B_CLK1# 14
M_A_CKE0 13,14
M_A_CKE1 13,14
M_B_CKE0 13,14
M_B_CKE1 13,14
M_A_CS#0 13,14
M_A_CS#1 13,14
M_B_CS#0 13,14
M_B_CS#1 13,14
M_A_ODT0 13,14
M_A_ODT1 13,14
M_B_ODT0 13,14
M_B_ODT1 13,14
R101 *10K/F/06
R9 *10K/F/06
DREFCLK 3
DREFCLK# 3
DREFSSCLK 3
DREFSSCLK# 3
CLK_PCIE_3GPLL 3
CLK_PCIE_3GPLL# 3
CL_CLK0 21
CL_DATA0 21
ECPWROK 16,21,36
CL_RST#0 21
T25
SDVO_CTRL_DATA 12
CLK_3GPLLREQ# 3
MCH_ICH_SYNC# 21
R493
R50
0/04
20K/04
1 2
1 2
1 2
C150 470P/50V/X7R/04
C19 .1U/10V/04
C10 .1U/10V/04
R8 0/04
+1.8VSUS_GMCH
DMI_TXN[3:0] 20
DMI_TXP[3:0] 20
DMI_RXN[3:0] 20
DMI_RXP[3:0] 20
T26
T166
T165
T167
T164
4
4
LCD_CTL16,24
LCD_BLON16,24
EDIDCLK16,24
EDIDDATA16,24
DISP_ON16,24
SMDDR_VREF
DDCCLK23
DDCDATA23
HSYNC_COM16,23
VSYNC_COM16,23
5
LVDS_IBG
U23C
J40
L_BKLT_CTRL
H39
L_BKLT_EN
E39
L_CTRL_CLK
E40
L_CTRL_DATA
C37
L_DDC_CLK
D35
L_DDC_DATA
K40
L_VDD_EN
L41
LVDS_IBG
L43
LVDS_VBG
N41
LVDS_VREFH
N40
LVDS_VREFL
D46
LVDSA_CLK#
C45
LVDSA_CLK
D44
LVDSB_CLK#
E42
LVDSB_CLK
G51
LVDSA_DATA#_0
E51
LVDSA_DATA#_1
F49
LVDSA_DATA#_2
G50
LVDSA_DATA_0
E50
LVDSA_DATA_1
F48
LVDSA_DATA_2
G44
LVDSB_DATA#_0
B47
LVDSB_DATA#_1
B45
LVDSB_DATA#_2
E44
LVDSB_DATA_0
A47
LVDSB_DATA_1
A45
LVDSB_DATA_2
E27
TVA_DAC
G27
TVB_DAC
K27
TVC_DAC
F27
TVA_RTN
J27
TVB_RTN
L27
TVC_RTN
M35
TV_DCONSEL_0
P33
TV_DCONSEL_1
H32
CRT_BLUE
G32
CRT_BLUE#
K29
CRT_GREEN
J29
CRT_GREEN#
F29
CRT_RED
E29
CRT_RED#
K33
CRT_DDC_CLK
G35
CRT_DDC_DATA
F33
CRT_HSYNC
C32
CRT_TVO_IREF
E33
CRT_VSYNC
CRESTLINE_1p0
R104 4.7K/04
R87 4.7K/04
R94 4.7K/04
R92 0/04
R84 0/04
R53 0/04
R54 0/04
R56 0/04
R46 0/04
R47 0/04
R82 *0/04
R166 *0/04
+3V
CRT_B16,23
CRT_G16,23
CRT_R16,23
R102 *10K/04
R105 *10K/04
R81 *0/04
R64 *0/04
R83 *0/04
R79 *2.4K/04
LA_CLK#
LA_CLK
T27*PAD
LB_CLK#
T29*PAD
LB_CLK
LA_DATAN0
LA_DATAN1
LA_DATAN2
LA_DATAP0
LA_DATAP1
LA_DATAP2
LB_DATAN0
T30*PAD
LB_DATAN1
T34*PAD
LB_DATAN2
T33*PAD
LB_DATAP0
T32*PAD
LB_DATAP1
T35*PAD
LB_DATAP2
T31*PAD
R44 0/04
R42 0/04
R43 0/04
R70 0/04
R57 0/04
R482 *0/04
R478 *0/04
R477 *0/04
R97 *0/04
R77 *0/04
R72 *39/04
R48 0/04
R60 *39/04
CRT Discrete / UMA
---------------------------
R48 NC 0
R49 NC 0
R2618 NC 39
R2627 0 1.3K/F
R2623 NC 39
CRT_BLUE1
CRT_GREEN1
CRT_RED1
Resistor Discret UMA
====================
R64 0 NC
R60 0 NC
R64 0 NC
R60 0 NC
R74 0 150
R77 0 150
R65 0 150
EDIDCLK_L
EDIDDATA_L
T28
*PAD
TV_COMP1
TV_Y/G1
TV_C/R1
TV_DCONSEL_0
TV_DCONSEL_1
DDCCLK_R
DDCDATA_R
HSYNC11
CRTIREF
VSYNC11
DREFSSCLK
DREFSSCLK#
<FAE>
If no use DREFCLK PD and
DREFCLK# PU
IV&EV Dis/Enable setting
DREFCLK
DREFCLK#
<design guide>
If no use
DREFCLK PD and
DREFCLK# PU
6
LVDS
TV VGA
+1.25V
+1.25V
DDCCLK_R
DDCDATA_R
HSYNC11
VSYNC11
CRT_BLUE1
CRT_GREEN1
CRT_RED1
PEG_COMPI
PEG_COMPO
PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15
PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15
PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PCI-EXPRESS GRAPHICS
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15
PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15
VCC3G_PCIE_R
N43
M43
J51
L51
N47
T45
T50
U40
Y44
Y40
AB51
W49
AD44
AD40
AG46
AH49
AG45
AG41
J50
L50
M47
U44
T49
T41
W45
W41
AB50
Y48
AC45
AC41
AH47
AG49
AH45
AG42
C_PEG_TXN0
N45
C_PEG_TXN1
U39
C_PEG_TXN2
U47
C_PEG_TXN3
N51
C_PEG_TXN4
R50
C_PEG_TXN5
T42
C_PEG_TXN6
Y43
C_PEG_TXN7
W46
C_PEG_TXN8
W38
C_PEG_TXN9
AD39
C_PEG_TXN10
AC46
C_PEG_TXN11
AC49
C_PEG_TXN12
AC42
C_PEG_TXN13
AH39
C_PEG_TXN14
AE49
C_PEG_TXN15
AH44
C_PEG_TXP0
M45
C_PEG_TXP1
T38
C_PEG_TXP2
T46
C_PEG_TXP3
N50
C_PEG_TXP4
R51
C_PEG_TXP5
U43
C_PEG_TXP6
W42
C_PEG_TXP7
Y47
C_PEG_TXP8
Y39
C_PEG_TXP9
AC38
C_PEG
AD47
C_PEG_TXP11
AC50
C_PEG_TXP12
AD43
C_PEG_TXP13
AG39
C_PEG_TXP14
AE50
C_PEG_TXP15
AH43
TXLCLKOUT+16,24
TXLCLKOUT-16,24
PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8
PEG_RXN9
PEG_RXN10
PEG_RXN11
PEG_RXN12
PEG_RXN13
PEG_RXN14
PEG_RXN15
PEG_RXP0
PEG_RXP1
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8
PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15
_TXP10
TXLOUT0-16,24
TXLOUT0+16,24
TXLOUT1-16,24
TXLOUT1+16,24
TXLOUT2-16,24
TXLOUT2+16,24
EDIDCLK_L
EDIDDATA_L
7
+VCC_PEG
R93 24.9/F/04
1 2
C162 .1U/10V
C576 .1U/10V
C163 .1U/10V
C567 .1U/10V
C165 .1U/10V
C569 .1U/10V
C167 .1U/10V
C571 .1U/10V
C168 .1U/10V
C573 .1U/10V
C171 .1U/10V
C574 .1U/10V
C173 .1U/10V
C578 .1U/10V
C174 .1U/10V
C580 .1U/10V
C161 .1U/10V
C575 .1U/10V
C159 .1U/10V
C566 .1U/10V
C164 .1U/10V
C568 .1U/10V
C166 .1U/10V
C570 .1U/10V
C169 .1U/10V
C572 .1U/10V
C170 .1U/10V
C565 .1U/10V
C172 .1U/10V
C577 .1U/10V
C175 .1U/10V
C579 .1U/10V
RP28 *0X2
3
1
RP31 *0X2
1
3
RP30 *0X2
1
3
RP29 *0X2
1
3
R75 0/04
R65 0/04
PEG_RXN0 15
PEG_RXN1 15
PEG_RXN2 15
PEG_RXN3 15
PEG_RXN4 15
PEG_RXN5 15
PEG_RXN6 15
PEG_RXN7 15
PEG_RXN8 15
PEG_RXN9 15
PEG_RXN10 15
PEG_RXN11 15
PEG_RXN12 15
PEG_RXN13 15
PEG_RXN14 15
PEG_RXN15 15
PEG_RXP0 15
PEG_RXP1 15
PEG_RXP2 15
PEG_RXP3 15
PEG_RXP4 15
PEG_RXP5 15
PEG_RXP6 15
PEG_RXP7 15
PEG_RXP8 15
PEG_RXP9 15
PEG_RXP10 15
PEG_RXP11 15
PEG_RXP12 15
PEG_RXP13 15
PEG_RXP14 15
PEG_RXP15 15
4
2
LA_DATAN0
2
LA_DATAP0
4
LA_DATAN1
2
LA_DATAP1
4
LA_DATAN2
2
LA_DATAP2
4
PEG_TXN_C0 15
PEG_TXN_C1 15
PEG_TXN_C2 15
PEG_TXN_C3 15
PEG_TXN_C4 15
PEG_TXN_C5 15
PEG_TXN_C6 15
PEG_TXN_C7 15
PEG_TXN_C8 15
PEG_TXN_C9 15
PEG_TXN_C10 15
PEG_TXN_C11 15
PEG_TXN_C12 15
PEG_TXN_C13 15
PEG_TXN_C14 15
PEG_TXN_C15 15
PEG_TXP_C0 15
PEG_TXP_C1 15
PEG_TXP_C2 15
PEG_TXP_C3 15
PEG_TXP_C4 15
PEG_TXP_C5 15
PEG_TXP_C6 15
PEG_TXP_C7 15
PEG_TXP_C8 15
PEG_TXP_C9 15
PEG_TXP_C10 15
PEG_TXP_C11 15
PEG_TXP_C12 15
PEG_TXP_C13 15
PEG_TXP_C14 15
PEG_TXP_C15 15
LA_CLK
LA_CLK#
8
07
PROJECT : CW4
Size Document Number Rev
5
6
Date: Sheet
7
Quanta Computer Inc.
Crestline_B (VGA,DMI)
of
744Friday, November 03, 2006
8
1ACustom
1
2
3
4
5
6
7
8
M_A_DQ[63:0]14 M_B_DQ[63:0]14
A A
B B
C C
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
AR43
AW44
BA45
AY46
AR41
AR45
AT42
AW47
BB45
BF48
BG47
BJ45
BB47
BG50
BH49
BE45
AW43
BE44
BG42
BE40
BF44
BH45
BG40
BF40
AR40
AW40
AT39
AW36
AW41
AY41
AV38
AT38
AV13
AT13
AW11
AV11
AU15
AT11
BA13
BA11
BE10
BD10
BD8
AY9
BG10
AW9
BD7
BB9
BB5
AY7
AT5
AT7
AY6
BB7
AR5
AR8
AR9
AN3
AM8
AN10
AT9
AN9
AM9
AN11
U23D
SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
CRESTLINE_1p0
BB19
SA_BS_0
BK19
SA_BS_1
BF29
SA_BS_2
BL17
SA_CAS#
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_RAS#
SA_RCVEN#
DDR SYSTEM MEMORY A
SA_WE#
AT45
BD44
BD42
AW38
AW13
BG8
AY5
AN6
AT46
BE48
BB43
BC37
BB16
BH6
BB2
AP3
AT47
BD47
BC41
BA37
BA16
BH7
BC1
AP2
BJ19
BD20
BK27
BH28
BL24
BK28
BJ27
BJ25
BL28
BA28
BC19
BE28
BG30
BJ16
BE18
AY20
BA19
M_A_DQM0
M_A_DQM1
M_A_DQM2
M_A_DQM3
M_A_DQM4
M_A_DQM5
M_A_DQM6
M_A_DQM7
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
TP_SA_RCVEN#
M_A_BS#0 13,14
M_A_BS#1 13,14
M_A_BS#2 13,14
M_A_CAS# 13,14
M_A_DQM[0..7] 14
M_A_DQS[7:0] 14
M_A_DQS#[7:0] 14
M_A_A[13:0] 13,14
M_A_RAS# 13,14
T14
M_A_WE# 13,14
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
AP49
AR51
AW50
AW51
AN51
AN50
AV50
AV49
BA50
BB50
BA49
BE50
BA51
AY49
BF50
BF49
BJ50
BJ44
BJ43
BL43
BK47
BK49
BK43
BK42
BJ41
BL41
BJ37
BJ36
BK41
BJ40
BL35
BK37
BK13
BE11
BK11
BC11
BC13
BE12
BC12
BG12
BJ10
BK10
BH5
BG1
BC2
BK3
BE4
BD3
BA3
BB3
AR1
AT3
AY2
AY3
AU2
AT2
BL9
BK5
BL5
BK9
BJ8
BJ6
BF4
BJ2
U23E
SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63
CRESTLINE_1p0
08
AY17
SB_BS_0
BG18
SB_BS_1
BG36
SB_BS_2
BE17
SB_CAS#
SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_RAS#
SB_RCVEN#
SB_WE#
DDR SYSTEM MEMORY B
AR50
BD49
BK45
BL39
BH12
BJ7
BF3
AW2
AT50
BD50
BK46
BK39
BJ12
BL7
BE2
AV2
AU50
BC50
BL45
BK38
BK12
BK7
BF2
AV3
BC18
BG28
BG25
AW17
BF25
BE25
BA29
BC28
AY28
BD37
BG17
BE37
BA39
BG13
AV16
AY18
BC17
M_B_DQM0
M_B_DQM1
M_B_DQM2
M_B_DQM3
M_B_DQM4
M_B_DQM5
M_B_DQM6
M_B_DQM7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
_B_A10
M
M_B_A11
M_B_A12
M_B_A13
TP_SB_RCVEN#
M_B_BS#0 13,14
M_B_BS#1 13,14
M_B_BS#2 13,14
M_B_CAS# 13,14
M_B_DQM[0..7] 14
M_B_DQS[7:0] 14
M_B_DQS#[7:0] 14
M_B_A[13:0] 13,14
M_B_RAS# 13,14
T15 *PAD
M_B_WE# 13,14
D D
PROJECT : CW4
Quanta Computer Inc.
Size Document Number Rev
1
2
3
4
5
6
Date: Sheet
7
Crestline_C (DDR2)
844Friday, November 03, 2006
of
8
1ACustom
AT35
AT34
AH28
AC32
AC31
AK32
AJ31
AJ28
AH32
AH31
AH29
AF32
AU32
AU33
AU35
AV33
AW33
AW35
AY35
BA32
BA33
BA35
BB33
BC32
BC33
BC35
BD32
BD35
BE32
BE33
BE35
BF33
BF34
BG32
BG33
BG35
BH32
BH34
BH35
BJ32
BJ33
BJ34
BK32
BK33
BK34
BK35
BL33
AU30
W13
W14
AA20
AA23
AA26
AA28
AB21
AB24
AB29
AC20
AC21
AC23
AC24
AC26
AC28
AC29
AD20
AD23
AD24
AD28
AF21
AF26
AA31
AH20
AH21
AH23
AH24
AH26
AD31
AJ20
AN14
5
R30
R20
T14
Y12
U23G
VCC_1
VCC_2
VCC_3
VCC_5
VCC_4
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36
VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34
VCC CORE
POWER
VCC SMVCC GFX
VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8
VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55
VCC GFX NCTF
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC_AXG_NCTF_61
VCC_AXG_NCTF_62
VCC_AXG_NCTF_63
VCC_AXG_NCTF_64
VCC_AXG_NCTF_65
VCC_AXG_NCTF_66
VCC_AXG_NCTF_67
VCC_AXG_NCTF_68
VCC_AXG_NCTF_69
VCC_AXG_NCTF_70
VCC_AXG_NCTF_71
VCC_AXG_NCTF_72
VCC_AXG_NCTF_73
VCC_AXG_NCTF_74
VCC_AXG_NCTF_75
VCC_AXG_NCTF_76
VCC_AXG_NCTF_77
VCC_AXG_NCTF_78
VCC_AXG_NCTF_79
VCC_AXG_NCTF_80
VCC_AXG_NCTF_81
VCC_AXG_NCTF_82
VCC_AXG_NCTF_83
VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7
VCC SM LF
+1.05V
D D
IVCCSM supply
current 1
channel
1.615A 2
channel
3.318A
C C
B B
A A
+1.8VSUS_GMCH
+1.05V
T17
T18
T19
T21
T22
T23
T25
U15
U16
U17
U19
U20
U21
U23
U26
V16
V17
V19
V20
V21
V23
V24
Y15
Y16
Y17
Y19
Y20
Y21
Y23
Y24
Y26
Y28
Y29
AA16
AA17
AB16
AB19
AC16
AC17
AC19
AD15
AD16
AD17
AF16
AF19
AH15
AH16
AH17
AH19
AJ16
AJ17
AJ19
AK16
AK19
AL16
AL17
AL19
AL20
AL21
AL23
AM15
AM16
AM19
AM20
AM21
AM23
AP15
AP16
AP17
AP19
AP20
AP21
AP23
AP24
AR20
AR21
AR23
AR24
AR26
V26
V28
V29
Y31
AW45
BC39
BE39
BD17
BD4
AW8
AT6
4
Ivcc_AXG Graphics core supply
current 7.7A
12
+
C185
330U/6.3V
Layout Note:
Inside GMCH cavity for VCC_AXG.
12
C76
.1U/10V/04
GMCH 1.05V
VCC Core
VCC_AXG
VCC_AXD
VTT
VCC_PEG
VCC_AXM
VCCR_RX_DMI
12
+
12
C95
.1U/10V/04
current(A)
1.573
7.7
0.2
0.85
1.2
0.54
0.25
12.313SUM
VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7
12
C33
.1U/10V/04
12
3
Ivcc (External GFX 1.310 A,
integrate 1.572 A)
+1.05V
12
+
C518
Layout Note:
370 mils from edge.
12
+
C178
330U/6.3V
12
C83
0.47U/10V/06
C585
*330U/6.3V
220U/2.5V
12
+
C186
*330U/6.3V
Layout Note:
370 mils from edge.
12
12
C99
C6
1U/10V/06
10U/6.3V/08
Remark
( 1.3A for
external
GFX )
for integrated
Gfx
Ivcc_AXM
Controller
supply
current
540mA
FSB VCCP
for PCIEG
for IAMT
function
DMI
12
C36
.1U/10V/04
12
C9
0.22U/10V/06
C63
0.22U/10V/06
12
C139
0.47U/10V/06
+3V
R475 10/04
1 2
12
Layout Note:
Inside GMCH cavity.
12
+1.05V
12
C533
10U
12
C5
10U
C120
0.22U/10V/06
C176
.1U/10V/04
12
12
Layout Note:
Place close to GMCH edge.
12
12
C136
1U/10V/06
+VCC_GMCH_L
+1.05V
Layout Note:
Inside GMCH
cavity.
C124
.1U/10V/04
C118
10U
C144
1U/10V/06
12
C129
0.22U/10V/06
12
C125
.1U/10V/04
12
C92
0.22U/10V/06
2
D16
21
CH751H-40HPT
12
C110
.1U/10V/04
12
C107
.1U/10V/04
12
C117
0.22U/10V/06
1.8VSUS
12
C86
.1U/10V/04
Layout Note:
Place C901 where LVDS
and DDR2 taps.
1
U23F
AB33
VCC_NCTF_1
AB36
VCC_NCTF_2
AB37
VCC_NCTF_3
AC33
VCC_NCTF_4
AC35
VCC_NCTF_5
AC36
VCC_NCTF_6
AD35
VCC_NCTF_7
AD36
VCC_NCTF_8
AF33
VCC_NCTF_9
AF36
VCC_NCTF_10
AH33
VCC_NCTF_11
AH35
VCC_NCTF_12
AH36
VCC_NCTF_13
AH37
VCC_NCTF_14
AJ33
VCC_NCTF_15
AJ35
VCC_NCTF_16
AK33
VCC_NCTF_17
AK35
VCC_NCTF_18
AK36
VCC_NCTF_19
AK37
VCC_NCTF_20
AD33
VCC_NCTF_21
AJ36
VCC_NCTF_22
AM35
VCC_NCTF_23
AL33
VCC_NCTF_24
AL35
VCC_NCTF_25
AA33
VCC_NCTF_26
AA35
VCC_NCTF_27
AA36
VCC_NCTF_28
AP35
VCC_NCTF_29
AP36
VCC_NCTF_30
AR35
VCC_NCTF_31
AR36
VCC_NCTF_32
Y32
VCC_NCTF_33
Y33
VCC_NCTF_34
Y35
VCC_NCTF_35
Y36
VCC_NCTF_36
Y37 A3
VCC_NCTF_37 VSS_SCB1
T30
VCC_NCTF_38
T34
VCC_NCTF_39
T35
VCC_NCTF_40
U29
VCC_NCTF_41
U31
VCC_NCTF_42
U32
VCC_NCTF_43
U33
VCC_NCTF_44
U35
VCC_NCTF_45
U36
VCC_NCTF_46
V32
VCC_NCTF_47
V33
VCC_NCTF_48
V36
VCC_NCTF_49
V37
VCC_NCTF_50
AL24
VCC_AXM_NCTF_1
AL26
VCC_AXM_NCTF_2
AL28
VCC_AXM_NCTF_3
AM26
VCC_AXM_NCTF_4
AM28
VCC_AXM_NCTF_5
AM29
VCC_AXM_NCTF_6
AM31
VCC_AXM_NCTF_7
AM32
VCC_AXM_NCTF_8
AM33
VCC_AXM_NCTF_9
AP29
VCC_AXM_NCTF_10
AP31
VCC_AXM_NCTF_11
AP32
VCC_AXM_NCTF_12
AP33
VCC_AXM_NCTF_13
AL29
VCC_AXM_NCTF_14
AL31
VCC_AXM_NCTF_15
AL32
VCC_AXM_NCTF_16
AR31
VCC_AXM_NCTF_17
AR32
VCC_AXM_NCTF_18
AR33
VCC_AXM_NCTF_19
CRESTLINE_1p0
12
+
C103
330U/6.3V
VCC NCTF
POWER
12
Layout Note:
Place on the edge.
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS NCTF
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_SCB2
VSS_SCB3
VSS_SCB4
VSS_SCB5
VSS_SCB6
VSS SCBVCC AXM
VCC_AXM_1
VCC_AXM_2
VCC_AXM_3
VCC_AXM_4
VCC_AXM_5
VCC_AXM_6
VCC_AXM_7
VCC AXM NCTF
+1.8VSUS_GMCH
12
C121
C133
10U
10U
T27
T37
U24
U28
V31
V35
AA19
AB17
AB35
AD19
AD37
AF17
AF35
AK17
AM17
AM24
AP26
AP28
AR15
AR19
AR28
B2
C1
BL1
BL51
A51
AT33
AT31
AK29
AK24
AK23
AJ26
AJ23
09
+1.05V
CRESTLINE_1p0
5
PROJECT : CW4
Size Document Number Rev
4
3
2
Date: Sheet
Quanta Computer Inc.
Crestline_D (VCC,NCTF)
944Friday, November 03, 2006
1
of
1ACustom
5
IV&EV Dis/Enable setting
L55
1 2
*IV@BLM18PG181SN1/06
+VCC_TVBG
12
50mA
12
C521
.1U/10V/04
C514
22U/10V/12
150mA
+1.25V_VCCA_MPLL
+VCCA_MPLL_L
12
C128
0.1U/10V/04
12
C94
*IV@.1U/04
12
C542
*IV@10U/4V/08
+3V_VCCSYNC
C113
*IV@.1U/04
12
C558
*IV@.1U/04
12
C522
.1U/10V/04
+1.5V_VCCD_TVDAC
R71 0/04
1 2
123
C119
*22nF/3P
R41 0/04
1 2
123
C88
*IV@22N
+3V_TV_DAC
R59
EV@0/04
+VCCA_CRTDAC
12
C559
*IV@.1U/04
R492 0/04
12
123
C557
*IV@22N
+1.25V
L9
10uH/100MA/08
10uH+-20%_100mA
L13
10uH/100MA/08
0.1Caps should be
placed 200 mils
with in its pins.
+1.25V
R45 0/06
+1.5V_VCCD_TVDAC
EV@0/04
R481 0/04
1 2
123
12
C548
*IV@.1U/04
R485 0/04
1 2
123
12
C546
*IV@.1U/04
R486 0/04
1 2
123
12
C551
*IV@.1U/04
R494 0/04
1 2
R490
EV@0/04
12
12
+1.25V
R30
+1.8VSUS_GMCH
C549
*IV@22N
C552
*IV@22N
C555
*IV@22N
12
+
12
+VCC_TVDACA_R
+VCC_TVDACB_R
+VCC_TVDACC_R
R88 *IV@0/06
+3V
D D
+3V
FB_180ohm+-25%_100mHz_1500mA_0.09ohm DC
+3V_TV_DAC
R27 *IV@0.03/F
FB_120ohm+-25%_100mHz
_200mA_0.2ohm DC
+1.25V
L48
+1.25V_VCCA_HPLL
12
BLM11A121S/06
C C
12
+1.5V
B B
FB_180ohm+-25%_
100mHz_1500mA_
0.09ohm DC
12
L49
BLM11A121S/06
12
R462
0.5/F/06
1 2
+VCCA_MPLL_L
C515
22U/10V/12
L7
+VCCQ_TVDAC
1 2
*IV@BLM18PG181SN1/06
FB_180ohm+-25%_100mHz_1500mA_0.09ohm DC
L54
+3V
1 2
*IV@BLM18PG181SN1/06
22nF & 0.1uF for
VCC_TVDACA:C_R should
A A
be placed with in 250
mils from Crestline.
5
123
C560
*IV@22N
80mA
+1.25V_VCCA_DPLLA
12
C148
+
470U/4V
.1U/10V/04
80mA
+1.25V_VCCA_DPLLB
12
C156
+
470U/4V
.1U/10V/04
R11 0/08
C21
100U/6.3V
C115
22U/4V/08
+VCCA_MPLL_L
250mA
R106 *IV@0/06
R480
EV@0/04
R484
EV@0/04
R487
EV@0/04
4
+3V_VCCA_CRT_DAC
R491
EV@0/04
12
C154
12
C158
C78
4.7U/6.3V/06
1 2
12
C111
1U/10V/06
4
+1.25V
R49 EV@0/04
R51 *IV@0/06
C147
*IV@1U/06
+1.8VSUS_VCC_TX_LVDS
+1.8VSUS_VCC_TX_LVDS
10mA
R496
C153
.1U/10V/04
Ivcca_PEG_BG
supply current
100mA
12
C8
22U/4V/08
12
C102
.1U/10V/04
12
C152
.1U/10V/04
C146
*IV@10U/08
L14
1 2
BLM21PG221SN1D/08
EV@0/04
+1.25V_VCCD_PEG_PLL
+1.25V_VCCA_SM_CK
+3V
12
12
C56
22U/4V/08
12
C101
1U/10V/06
12
C520
.1U/10V/04
FB_220ohm+-25%_100MHz
_2A_0.1ohm DC
+1.25V_VCCA_DPLLA
+1.25V_VCCA_DPLLB
+1.25V_VCCA_HPLL
+1.25V_VCCA_MPLL
C563
*IV@1000P/04
100mA
+1.25V_VCCA_SM
12
C61
1U/10V/06
+VCC_TVDACA_R
+VCC_TVDACB_R
+VCC_TVDACC_R
+1.5V_VCCD_CRT
+1.5V_VCCD_TVDAC
+1.5V_VCCD_QDAC
+VCCA_MPLL_L
+1.25V_VCCD_PEG_PLL
+1.8V_VCCD_LVDS
150mA
R91
EV@0/04
100mA
12
R115
1/F/06
12
C182
10U/6.3V/06
3
CRT/TV Disable/Enable guideline
External VGA with EV@part,Internal VGA with IV@ part
VCCA_CRT_DAC
VCCD_CRT
Ball
U23H
J32
VCCSYNC
A33
VCCA_CRT_DAC_1
B33
VCCA_CRT_DAC_2
A30
VCCA_DAC_BG
B32
VSSA_DAC_BG
B49
VCCA_DPLLA
H49
VCCA_DPLLB
AL2
VCCA_HPLL
AM2
VCCA_MPLL
A41
VCCA_LVDS
B41
VSSA_LVDS
K50
VCCA_PEG_BG
K49
VSSA_PEG_BG
U51
VCCA_PEG_PLL
AW18
VCCA_SM_1
AV19
VCCA_SM_2
AU19
VCCA_SM_3
AU18
VCCA_SM_4
AU17
VCCA_SM_5
AT22
VCCA_SM_7
AT21
VCCA_SM_8
AT19
VCCA_SM_9
AT18
VCCA_SM_10
AT17
VCCA_SM_11
AR17
VCCA_SM_NCTF_1
AR16
VCCA_SM_NCTF_2
BC29
VCCA_SM_CK_1
BB29
VCCA_SM_CK_2
C25
VCCA_TVA_DAC_1
B25
VCCA_TVA_DAC_2
C27
VCCA_TVB_DAC_1
B27
VCCA_TVB_DAC_2
B28
VCCA_TVC_DAC_1
A28
VCCA_TVC_DAC_2
M32
VCCD_CRT
L29
VCCD_TVDAC
N28
VCCD_QDAC
AN2
VCCD_HPLL
U48
VCCD_PEG_PLL
J41
VCCD_LVDS_1
H42
VCCD_LVDS_2
+1.25V_VCCD_PEG_PLL
12
C155
.1U/10V/04
Enable
3.3V
1.5V
1.5V
3.3V
3.3V
+VTTLF1
+VTTLF2
+VTTLF3
3
Ball
Disable
GND VCCA_TVC_DAC
GND
VCCD_TVDAC
GND VCCA_DAC_BG
VSS_DAC_BG
GND
GND
VCCSYNC
CRTPLLA PEGA SMTV
VCC_AXD_1
VCC_AXD_2
VCC_AXD_3
VCC_AXD_4
VCC_AXD_5
VCC_AXD_6
AXD
VCC_AXD_NCTF
VCC_AXF_1
POWER
A CK A LVDS
D TV/CRTLVDS
12
C519
0.47U/10V/06
VCC_AXF_2
VCC_AXF_3
AXF
VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4
SM CK
VCC_TX_LVDS
HV
VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5
PEG
VCC_RXR_DMI_1
VCC_RXR_DMI_2
DMI
CRESTLINE_1p0
12
C20
0.47U/10V/06
VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VCC_DMI
VCC_HV_1
VCC_HV_2
VTTLF1
VTTLF2
VTTLF3
VTTLF
Enable
3.3V
1.5V
3.3VVCCD_QDAC
GNDVCCA_TVA_DAC
3.3VVCCA_TVB_DAC
12
U13
U12
U11
U9
U8
U7
U5
U3
U2
U1
T13
T11
T10
T9
T7
T6
T5
T3
T2
R3
R2
R1
AT23
AU28
AU24
AT29
AT25
AT30
AR29
B23
B21
A21
AJ50
BK24
BK23
BJ24
BJ23
A43
C40
B40
AD51
W50
W51
V49
V50
AH50
AH51
A7
F2
AH1
C532
0.47U/10V/06
Disable
+3V_VCC_HV
+VCC_RXR_DMI
+VTTLF1
+VTTLF2
+VTTLF3
GND
1.5V
GND
GND
GND
12
C55
2.2U/6.3V/06
Place on the edge.
12
C41
0.47U/6.3V/04
Place on the edge.
+1.25V_AXD
12
C89
1U/10V/06
+1.25V_VCC_AXF
+1.25V_VCC_DMI
+1.25V_VCC_DMI
+1.8VSUS_VCC_SM_CK
200mA
+1.8VSUS_VCC_TX_LVDS
12
C561
.1U/10V/04
12
12
2
LVDS Disable/Enable guideline
External VGA with EV@part,Internal VGA with IV@ part
VCCD_LVDS
VCCA_LVDS
VCC_TX_LVDS
Signal
If SDVO Disable
LVDS Disable
GND
GND
GND
If LVDS
enable
1.8V
1.8V
1.8V
+3V_VCC_HV
D4
CH751H-40HPT
Ivcc_VTT FSB
12
supply
C516
4.7U/10V/08
12
12
+
C177
220U/4V
+
C586
220U/4V
2
C517
4.7U/10V/08
1 2
C60
22U/10V/12
R497
EV@0/04
+VCC_PEG
12
current
0.85A
+1.05V
12
+
C32
220U/4V
+VCC_AXD_R
L5
0/04
Reserved L81 pad for
inductor.
Place caps close
to VCC_AXD.
Ivcc_DMI supply
current 100mA
R499 0/08
12
C564
.1U/10V/04
+1.8VSUS_VCC_TX_LVDS
100mA
12
C562
*IV@1000P/04
L10
BLM21PG220SN1D/08
12
C145
10U/6.3V
L8
BLM21PG220SN1D/08
12
C134
10U/6.3V/06
+1.8VSUS_VCC_SM_CK
12
C82
C79
.1U/10V/04
22U/10V/12
R20 0/08
L56 *IV@1UH/08
12
1uH+-20%_300mA
+
C142
*IV@220U
+1.05V
+1.05V
L6
1uH/300mA/08
12
1uH+-20%_300mA
R34
1/F/06
+VCC_SM_CK_L
12
C85
10U/6.3V/06
+3V_VCC_HV
R495 0/04
+1.25V
+1.25V_VCC_AXF
12
C48
1U/10V/06
+1.25V
12
Ivcc_PEG
supply current
1.2A
Ivcc_RX_DMI
supply current
250mA
Size Document Number Rev
Date: Sheet
12
Place caps close
to VCC_AXF
+1.8VSUS_GMCH
Quanta Computer Inc.
1
+1.05V
21
40 mil
wide
+3V_VCC_HV_L
12
R108
10/04
+3V
+1.25V
R25
0/08
12
C49
10U/6.3V/06
+1.8VSUS_GMCH
PROJECT : CW4
Crestline_E (POWER)
10 44Friday, November 03, 2006
1
10
of
1ACustom
5
4
3
2
1
U23I
A13
VSS_1
A15
VSS_2
A17
VSS_3
A24
VSS_4
AA21
VSS_5
AA24
VSS_6
AA29
VSS_7
D D
C C
B B
A A
AB20
AB23
AB26
AB28
AB31
AC10
AC13
AC39
AC43
AC47
AD21
AD26
AD29
AD41
AD45
AD49
AD50
AE10
AE14
AF20
AF23
AF24
AF31
AG2
AG38
AG43
AG47
AG50
AH3
AH40
AH41
AH7
AH9
AJ11
AJ13
AJ21
AJ24
AJ29
AJ32
AJ43
AJ45
AJ49
AK20
AK21
AK26
AK28
AK31
AK51
AM11
AM13
AM3
AM4
AM41
AM45
AN1
AN38
AN39
AN43
AN5
AN7
AP4
AP48
AP50
AR11
AR2
AR39
AR44
AR47
AR7
AT10
AT14
AT41
AT49
AU1
AU23
AU29
AU3
AU36
AU49
AU51
AV39
AV48
AW1
AW12
AW16
AC3
AD1
AD3
AD5
AD8
AE6
AL1
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
CRESTLINE_1p0
VSS
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
AW24
AW29
AW32
AW5
AW7
AY10
AY24
AY37
AY42
AY43
AY45
AY47
AY50
B10
B20
B24
B29
B30
B35
B38
B43
B46
B5
B8
BA1
BA17
BA18
BA2
BA24
BB12
BB25
BB40
BB44
BB49
BB8
BC16
BC24
BC25
BC36
BC40
BC51
BD13
BD2
BD28
BD45
BD48
BD5
BE1
BE19
BE23
BE30
BE42
BE51
BE8
BF12
BF16
BF36
BG19
BG2
BG24
BG29
BG39
BG48
BG5
BG51
BH17
BH30
BH44
BH46
BH8
BJ11
BJ13
BJ38
BJ4
BJ42
BJ46
BK15
BK17
BK25
BK29
BK36
BK40
BK44
BK6
BK8
BL11
BL13
BL19
BL22
BL37
BL47
C12
C16
C19
C28
C29
C33
C36
C41
U23J
C46
VSS_199
C50
VSS_200
C7
VSS_201
D13
VSS_202
D24
VSS_203
D3
VSS_204
D32
VSS_205
D39
VSS_206
D45
VSS_207
D49
VSS_208
E10
VSS_209
E16
VSS_210
E24
VSS_211
E28
VSS_212
E32
VSS_213
E47
VSS_214
F19
VSS_215
F36
VSS_216
F4
VSS_217
F40
VSS_218
F50
VSS_219
G1
VSS_220
G13
VSS_221
G16
VSS_222
G19
VSS_223
G24
VSS_224
G28
VSS_225
G29
VSS_226
G33
VSS_227
G42
VSS_228
G45
VSS_229
G48
VSS_230
G8
VSS_231
H24
VSS_232
H28
VSS_233
H4
VSS_234
H45
VSS_235
J11
VSS_236
J16
VSS_237
J2
VSS_238
J24
VSS_239
J28
VSS_240
J33
VSS_241
J35
VSS_242
J39
VSS_243
K12
VSS_245
K47
VSS_246
K8
VSS_247
L1
VSS_248
L17
VSS_249
L20
VSS_250
L24
VSS_251
L28
VSS_252
L3
VSS_253
L33
VSS_254
L49
VSS_255
M28
VSS_256
M42
VSS_257
M46
VSS_258
M49
VSS_259
M5
VSS_260
M50
VSS_261
M9
VSS_262
N11
VSS_263
N14
VSS_264
N17
VSS_265
N29
VSS_266
N32
VSS_267
N36
VSS_268
N39
VSS_269
N44
VSS_270
N49
VSS_271
N7
VSS_272
P19
VSS_273
P2
VSS_274
P23
VSS_275
P3
VSS_276
P50
VSS_277
R49
VSS_278
T39
VSS_279
T43
VSS_280
T47
VSS_281
U41
VSS_282
U45
VSS_283
U50
VSS_284
V2
VSS_285
V3
VSS_286
CRESTLINE_1p0
VSS
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
W11
W39
W43
W47
W5
W7
Y13
Y2
Y41
Y45
Y49
Y5
Y50
Y11
P29
T29
T31
T33
R28
AA32
AB32
AD32
AF28
AF29
AT27
AV25
H50
11
PROJECT : CW4
Size Document Number Rev
5
4
3
2
Date: Sheet
Quanta Computer Inc.
Crestline_F (VSS)
11 44Friday, November 03, 2006
1
of
1ACustom
5
Strap table
All strap are sampled with respect to the leading edge of the GMCH Power OK(PWROK) Signal
CFG[17:3] Have internal Pull-up
CFG[18:19] Have internal Pull-down
Any CFG signal strapping option not list below should be left NC Pin
Pin Name Strap description
D D
CFG[2:0]
CFG[4:3]
CFG5
CFG6
CFG7
CFG8
CFG9
CFG[11:10]
C C
CFG[13:12]
CFG[15:14]
CFG16
CFG[18:17]
SDVO_CTRLDATA
CFG19
CFG20
B B
DMI X2 Select
MCH_CFG_5 Low = DMIX2
MCH_CFG_57
High = IDMIX4(Default)
R39
*4.02K/F/04
FSB Dynamic ODT
MCH_CFG_16 Low = ODT Disable
A A
MCH_CFG_167
High = ODT Enable(Default)
R31
*4.02K/F/04
5
FSB Frequency Select
Reserved
DMI X2 Select
Reserved
CPU Strap
Low power PCI Express
PCI Express Graphics Lane Reversal
Reserved
XOR/ALLZ
Reserved
FSB Dynamic ODT
Reserved
SDVO Present
DMI Lane Reversal
SDVO/PCIe concurrent
DMI Lane Reversal
MCH_CFG_19 Low = Normal operation(Default)
MCH_CFG_197
SDVO/PCIE Concurrent operation
MCH_CFG_20
MCH_CFG_207
4
High = Reverse Lane
+3V
R67
*4.02K/F/04
Low = Only SDVO or PCIE X1 is
operational(Default)
High = SDVO andPCIE X1 are operating
simultaneously via the PEG port
+3V
R69
*4.02K/F/04
4
3
2
Configuration
010 = FSB 800MHz
011 = FSB 667MHz
0 = DMI X2
1 = DMI X4(Default)
0 = Reserved
1 = Mobile CPU(Default)
0 = Normal mode
1 = Low Power mode
0 = Reverse Lanes
1 = Normal operation(Default)
00 = Reserved
01 = XOR Mode Enable
10 = All-Z Mode Enabled
11 = Normal operation(Default)
0 = Dynamic ODT disable
1 = Dynamic ODT Enable(Default)
0 = No SDVO Card present(Default)
1 = SDVO Card Present
0 = Normal operation(Default)
1 = Reverse Lanes
0 = Only SDVO or PCIE x1 is operation(Default)
1 = SDVO and PCIE x1 are operating simultaneously via the PEG port
XOR /ALLz /Clock Un-gating
MCH_CFG_12MCH_CFG_13 Configuration
0
0
1
1
MCH_CFG_127
MCH_CFG_137
0
1
0
1
Clock gating disable
XOR Mode Enable
ALL-z Mode Enable
Normal operation(Default)
3
R38
*4.02K/F/04
R40
*4.02K/F/04
PCI Express Graphics
MCH_CFG_9 Low = Reverse Lane
MCH_CFG_97
MCH_CFG_87
SDVO_CTRL_DATA7
High = Normal operation(Default)
2
R68
*4.02K/F/04
1
12
SDVO Present
Strap define at External
DVI control page
R29
*4.02K/F/04
R33
*4.02K/F/04
PROJECT : CW4
Size Document Number Rev
Date: Sheet
Quanta Computer Inc.
Crestline_F Strap
1
of
12 44Friday, November 03, 2006
1ACustom
1
2
3
4
5
6
7
8
DDRII DUAL CHANNEL A,B.
A A
13
DDRII A CHANNEL DDRII B CHANNEL
M_A_A[13..0] M_B_A[13..0]
SMDDR_VTERM 1.8VSUS
SMDDR_VTERM
SMDDR_VTERM
C47
C122
.1U/10V
B B
M_A_ODT07,14
M_A_CKE17,14
M_A_BS#08,14
M_A_RAS#8,14
M_A_BS#18,14
C C
M_A_WE#8,14
M_A_CAS#8,14
SA_MA147,14
SB_MA147,14
.1U/10V
C114
.1U/10V
M_A_ODT0
M_A_A13
M_A_A8
M_A_A5
M_A_A3
M_A_A1
M_A_CKE1
M_A_A11
M_A_A10
M_A_BS#0
M_A_A7
M_A_A6
M_A_A2
M_A_A4
M_A_BS#1
M_A_A9
M_A_A12
C91
.1U/10V
C90
C37
.1U/10V
.1U/10V
RP4 56X2
1
3
RP17 56X2
1
3
RP13 56X2
1
3
RP24 56X2
1
3
RP9 56X2
1
3
RP20 56X2
1
3
RP16 56X2
1
3
RP5 56X2
1
3
RP26 56X2
1
3
RP7 56X2
1
3
R52 56/04
R58 56/04
M_A_A[13..0] 8,14 M_B_A[13..0] 8,14
SMDDR_VTERM 37,39 1.8VSUS 7,9,10,14,37,39,44
C43
C138
.1U/10V
C64
.1U/10V
C65
.1U/10V
C132
.1U/10V
.1U/10V
C135
.1U/10V
C97
.1U/10V
SMDDR_VTERM
C96
.1U/10V
C140
.1U/10V
C46
.1U/10V
C131
.1U/10V
C45
.1U/10V
+3V
C112
.1U/10V
+3V 3,4,7,9,10,12,14,15,16,17,19,20,21,22,24,26,27,30,33,34,35,36,37,38,39
C40
C62
.1U/10V
.1U/10V
Layout note: Place one cap close to every 2 pullup resistors terminated to SMDDR_VTERM
RP12 56X2
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
SMDDR_VTERM
SMDDR_VTERM
SMDDR_VTERM
M_B_BS#18,14
M_B_BS#28,14
M_B_CKE07,14
M_B_RAS#8,14
M_B_CS#07,14
M_B_BS#08,14
M_B_CAS#8,14
M_B_WE#8,14
M_B_A0
M_B_A5
M_B_A1
M_B_A8
M_B_A3
M_B_A4
M_B_A2
M_B_A12
M_B_A9
M_B_A7
M_B_A6
M_B_A10
1
3
RP14 56X2
1
3
RP18 56X2
1
3
RP15 56X2
1
3
RP22 56X2
1
3
RP19 56X2
1
3
RP25 56X2
1
3
RP8 56X2
1
3
RP6 56X2
1
3
RP11 56X2
1
3
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
SMDDR_VTERM
SMDDR_VTERM
SMDDR_VTERM
C57
.1U/10V
C123
.1U/10V
C42
.1U/10V
C84
.1U/10V
C137
.1U/10V
RP10 56X2
M_A_CS#07,14
M_B_ODT07,14
M_B_ODT17,14
M_B_CS#17,14
M_A_CS#17,14
M_A_ODT17,14
M_B_CKE17,14
M_A_CKE07,14
M_A_BS#28,14
D D
M_A_A0
M_B_A13
M_ODT3
M_ODT1
M_B_A11
1
3
RP3 56X2
1
3
RP2 56X2
1
3
RP1 56X2
1
3
RP23 56X2
1
3
RP21 56X2
1
3
2
4
2
4
2
4
2
4
2
4
2
4
SMDDR_VTERM
PROJECT : CW4
Quanta Computer Inc.
Size Document Number Rev
1
2
3
4
5
6
Date: Sheet
DDRII RES. ARRAY
7
of
13 44Friday, November 03, 2006
8
1AB
1
CGCLK_SMB +3V
CGDAT_SMB
M_A_CKE[0..1]
M_A_CS#[0..1]
M_A_RAS#
M_A_CAS#
M_A_WE#
CGCLK_SMB 3,35 +3V 3,4,7,9,10,12,15,16,17,19,20,21,22,24,26,27,30,33,34,35,36,37,38,39,40,41,42,43,44
CGDAT_SMB 3,35
M_A_CKE[0..1] 7,13 M_A_CLK0 7
M_A_CS#[0..1] 7,13
M_A_RAS# 8,13
M_A_CAS# 8,13
M_A_WE# 8,13
M_A_CLK0
M_A_CLK0#
M_A_CLK1
M_A_CLK1#
M_A_BS#[0..2]
M_A_ODT[0..1]
2
M_A_CLK0# 7
M_A_CLK1 7
M_A_CLK1# 7
M_A_BS#[0..2] 8,13 M_A_DQS#[0..7] 8
M_A_ODT[0..1] 7,13
3
M_A_DQM[0..7]
M_A_DQ[0..63]
M_A_DQS[0..7]
M_A_DQS#[0..7]
M_A_A[13..0]
M_A_DQM[0..7] 8
M_A_DQ[0..63] 8
M_A_DQS[0..7] 8
M_A_A[13..0] 8,13
4
M_B_CKE[0..1]
M_B_CS#[0..1]
M_B_RAS#
M_B_CAS#
M_B_WE#
5
M_B_CKE[0..1] 7,13
M_B_CS#[0..1] 7,13
M_B_RAS# 8,13
M_B_CAS# 8,13
M_B_WE# 8,13
1.8VSUS
M_B_CLK0
M_B_CLK0#
M_B_CLK1
M_B_CLK1#
M_B_BS#[0..2]
M_B_ODT[0..1]
6
1.8VSUS 7,9,10,37,39,44
M_B_CLK0 7
M_B_CLK0# 7
M_B_CLK1 7
M_B_CLK1# 7
M_B_BS#[0..2] 8,13
M_B_ODT[0..1] 7,13
M_B_DQM[0..7]
M_B_DQ[0..63]
M_B_DQS[0..7]
M_B_DQS#[0..7]
M_B_A[13..0]
7
M_B_DQM[0..7] 8
M_B_DQ[0..63] 8
M_B_DQS[0..7] 8
M_B_DQS#[0..7] 8
M_B_A[13..0] 8,13
8
14
CN13B
1
VREF
1.8VSUS
81
1.8VSUS
1.8VSUS
1.8VSUS
1.8VSUS
1.8VSUS
1.8VSUS
1.8VSUS
1.8VSUS
1.8VSUS
1.8VSUS
1.8VSUS
VDD_1
82
VDD_2
87
VDD_3
88
VDD_4
95
VDD_5
96
VDD_6
103
VDD_7
104
VDD_8
111
VDD_9
112
VDD_10
117
VDD_11
118
VDD_12
114
ODT0
119
ODT1
50
NC_1
69
NC_2
83
NC_3
84
NC_4/A15
86
NC_5/A14
116
NC_6/A13
120
NC_7
163
NC_8
162
VSS_45
165
VSS_46
168
VSS_47
171
VSS_48
172
VSS_49
177
VSS_50
178
VSS_51
183
VSS_52
184
VSS_53
187
VSS_54
190
VSS_55
193
VSS_56
196
VSS_57
201 202
VSS_58 VSS_59
DDRII_SOCKET---2ND
1.8VSUS
C550
2.2U/6.3V/06
SMDDR_VREF_DIMM
2
VSS_1
3
VSS_2
8
VSS_3
9
VSS_4
12
VSS_5
15
VSS_6
18
VSS_7
21
VSS_8
24
VSS_9
27
VSS_10
28
VSS_11
33
VSS_12
34
VSS_13
39
VSS_14
40
VSS_15
41
VSS_16
42
VSS_17
47
VSS_18
48
VSS_19
53
VSS_20
54
VSS_21
59
VSS_22
60
VSS_23
65
VSS_24
66
VSS_25
71
VSS_26
72
VSS_27
77
VSS_28
78
VSS_29
121
VSS_30
122
VSS_31
127
VSS_32
PC2100 DDR2 SDRAM
SO-DIMM (200P)
128
VSS_33
132
VSS_34
133
VSS_35
138
VSS_36
139
VSS_37
144
VSS_38
145
VSS_39
149
VSS_40
150
VSS_41
155
VSS_42
156
VSS_43
161
VSS_44
C127
C77
2.2U/6.3V/06
2.2U/6.3V/06
C59
2.2U/6.3V/06
+3V
M_A_DQ1
M_A_DQ5
M_A_DQ3
M_A_DQ2
M_A_DQ4
M_A_DQ0
M_A_DQ7
M_A_DQ6
M_A_DQ13
M_A_DQ8
M_A_DQ15
M_A_DQ10
M_A_DQ9
M_A_DQ12
M_A_DQ14
M_A_DQ11
M_A_DQ16
M_A_DQ21
M_A_DQ23
M_A_DQ19
M_A_DQ20
M_A_DQ17
M_A_DQ18
M_A_DQ22
M_A_DQ24
M_A_DQ28
M_A_DQ31
M_A_DQ30
M_A_DQ25
M_A_DQ29
M_A_DQ27
M_A_DQ26
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_BS#0
M_A_BS#1
M_A_BS#2
M_A_CLK0
M_A_CLK0#
M_A_CLK1
M_A_CLK1#
CGCLK_SMB
CGDAT_SMB
DIM1_SA0
DIM1_SA1
C81
2.2U/6.3V/06
+3V+3V
C553
.1U/10V/04
1
CN13A
5
DQ0
7
DQ1
17
DQ2
19
DQ3
4
DQ4
6
DQ5
14
DQ6
16
DQ7
23
DQ8
25
DQ9
35
DQ10
37
DQ11
20
DQ12
22
DQ13
36
DQ14
38
DQ15
43
DQ16
45
DQ17
55
DQ18
57
DQ19
44
DQ20
46
DQ21
56
DQ22
58
DQ23
61
DQ24
63
DQ25
73
DQ26
75
DQ27
62
DQ28
64
DQ29
74
DQ30
76
DQ31
102
A0
101
A1
100
A2
99
A3
98
A4
97
A5
94
A6
92
A7
93
A8
91
A9
105
A10/AP
90
A11
89
A12
107
BA0
106
BA1
85
NC/BA2
30
CLK0
32
CLK0
164
CLK1
166
CKL1
197
SCL
195
SDA
198
SA0
200
SA1
199
VDDSPD
DDRII_SOCKET---2ND
DIM2_SA0
DIM2_SA1
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DQS0
DQS0
DQS1
PC2100 DDR2 SDRAM SO-DIMM
(200P)
DQS1
DQS2
DQS2
DQS3
DQS3
DQS4
DQS4
DQS5
DQS5
DQS6
DQS6
DQS7
DQS7
CS0
CS1
RAS
CAS
WE
CKE0
CKE1
R458 10K/04
R457 10K/04
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194
10
26
52
67
130
147
170
185
13
11
31
29
51
49
70
68
131
129
148
146
169
167
188
186
110
115
108
113
109
79
80
CKEA 0,1
+3V
M_B_DQ36
M_B_DQ33
M_B_DQ35
M_B_DQ39
M_B_DQ37
M_B_DQ32
M_B_DQ34
M_B_DQ38
M_B_DQ40
M_B_DQ41
M_B_DQ46
M_B_DQ43
M_B_DQ45
M_B_DQ44
M_B_DQ47
M_B_DQ42
M_B_DQ55
M_B_DQ49
M_B_DQ51
M_B_DQ53
M_B_DQ48
M_B_DQ52
M_B_DQ50
M_B_DQ54
M_B_DQ61
M_B_DQ60
M_B_DQ59
M_B_DQ63
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ62
M_B_DQM0
M_B_DQM1
M_B_DQM2
M_B_DQM3
M_B_DQM4
M_B_DQM5
M_B_DQM6
M_B_DQM7
M_B_DQS0
M_B_DQS#0
M_B_DQS1
M_B_DQS#1
M_B_DQS2
M_B_DQS#2
M_B_DQS3
M_B_DQS#3
M_B_DQS4
M_B_DQS#4
M_B_DQS5
M_B_DQS#5
M_B_DQS6
M_B_DQS#6
M_B_DQS7
M_B_DQS#7
M_B_CS#0
M_B_CS#1
M_B_RAS#
M_B_CAS#
M_B_WE#
M_B_CKE0
M_B_CKE1
SMDDR_VREF_DIMM
1.8VSUS
PM_EXTTS#07
SB_MA147,13
M_B_ODT0
M_B_ODT1
M_B_A13
Place these Caps near So-Dimm1. Place these Caps near So-Dimm2.
C554
2.2U/6.3V/06
C543
2.2U/6.3V/06
C100
2.2U/6.3V/06
C58
2.2U/6.3V/06
+3V
C104
2.2U/6.3V/06
C545
.1U/10V/04
C126
.1U/10V/04
C80
.1U/10V/04
C74
.1U/10V/04
C556
.1U/10V/04
C75
.1U/10V/04
A A
M_B_DQ1
M_B_DQ4
M_B_DQ2
M_B_DQ3
M_B_DQ5
M_B_DQ0
M_B_DQ7
M_B_DQ6
M_B_DQ13
M_B_DQ12
M_B_DQ10
M_B_DQ11
M_B_DQ8
M_B_DQ9
M_B_DQ15
M_B_DQ14
M_B_DQ21
M_B_DQ17
M_B_DQ19
M_B_DQ23
M_B_DQ20
M_B_DQ16
M_B_DQ18
M_B_DQ22
M_B_DQ28
M_B_DQ29
M_B_DQ27
M_B_DQ26
M_B_DQ24
M_B_DQ25
M_B_DQ31
M_B_DQ30
B B
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_BS#0
M_B_BS#
M_B_BS#2
M_B_CLK0
M_B_CLK0#
M_B_CLK1
M_B_CLK1#
CGCLK_SMB
CGDAT_SMB
DIM2_SA0
DIM2_SA1
C C
1.8VSUS
SMDDR_VREF_DIMM
CN12A
5
7
17
19
4
6
14
16
23
25
35
37
20
22
36
38
43
45
55
57
44
46
56
58
61
63
73
75
62
64
74
76
102
101
100
99
98
97
94
92
93
91
105
90
89
107
106
85
30
32
164
166
197
195
198
200
199
DDRII_SOCKET---1ST
R4 10K/04
R3 10K/04
SMbus address A0SMbus address A4
C108
C93
.1U/10V/04
.1U/10V/04
123
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
BA0
BA1
NC/BA2
CLK0
CLK0
CLK1
CKL1
SCL
SDA
SA0
SA1
VDDSPD
DQ32
125
DQ33
135
DQ34
137
DQ35
124
DQ36
126
DQ37
134
DQ38
136
DQ39
141
DQ40
143
DQ41
151
DQ42
153
DQ43
140
DQ44
142
DQ45
152
DQ46
154
DQ47
157
DQ48
159
DQ49
173
DQ50
175
DQ51
158
DQ52
160
DQ53
174
DQ54
176
DQ55
179
DQ56
181
DQ57
189
DQ58
191
DQ59
180
DQ60
182
DQ61
192
DQ62
194
DQ63
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DQS0
DQS0
DQS1
PC2100 DDR2 SDRAM SO-DIMM
(200P)
DQS1
DQS2
DQS2
DQS3
DQS3
DQS4
DQS4
DQS5
DQS5
DQS6
DQS6
DQS7
DQS7
CS0
CS1
RAS
CAS
CKE0
CKE1
DIM1_SA0
DIM1_SA1
C98
C87
.1U/10V/04
.1U/10V/04
WE
C109
.1U/10V/04
10
26
52
67
130
147
170
185
13
11
31
29
51
49
70
68
131
129
148
146
169
167
188
186
110
115
108
113
109
79
80
CKEB 0,1
M_A_DQM0
M_A_DQM
M_A_DQM2
M_A_DQM3
M_A_DQM4
M_A_DQM5
M_A_DQM6
M_A_DQM7
M_A_DQS0
M_A_DQS#0
M_A_DQS1
M_A_DQS#1
M_A_DQS2
M_A_DQS#2
M_A_DQS3
M_A_DQS#3
M_A_DQS4
M_A_DQS#4
M_A_DQS5
M_A_DQS#5
M_A_DQS6
M_A_DQS#6
M_A_DQS7
M_A_DQS#7
M_A_CS#0
M_A_CS#1
M_A_RAS#
M_A_CAS#
M_A_WE#
M_A_CKE0
M_A_CKE1
H 5.2H 9.2
M_A_DQ32
M_A_DQ35
M_A_DQ37
M_A_DQ38
M_A_DQ33
M_A_DQ36
M_A_DQ39
M_A_DQ34
M_A_DQ40
M_A_DQ41
M_A_DQ46
M_A_DQ42
M_A_DQ45
M_A_DQ44
M_A_DQ43
M_A_DQ47
M_A_DQ52
M_A_DQ48
M_A_DQ55
M_A_DQ54
M_A_DQ53
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ60
M_A_DQ56
M_A_DQ62
M_A_DQ58
M_A_DQ57
M_A_DQ61
M_A_DQ59
M_A_DQ63
1
SMDDR_VREF_DIMM
1.8VSUS
M_A_ODT0
M_A_ODT1
PM_EXTTS#07
SA_MA147,13
R117
1.8VSUS
1.8VSUS
1.8VSUS
1.8VSUS
1.8VSUS
1.8VSUS
1.8VSUS
1.8VSUS
1.8VSUS
1.8VSUS
1.8VSUS
1.8VSUS
M_A_A13
C583 470P/50V/04
1 2
*10K/F/06
CN12B
1
VREF
81
VDD_1
82
VDD_2
87
VDD_3
88
VDD_4
95
VDD_5
96
VDD_6
103
VDD_7
104
VDD_8
111
VDD_9
112
VDD_10
117
VDD_11
118
VDD_12
114
ODT0
119
ODT1
50
NC_1
69
NC_2
83
NC_3
84
NC_4/A15
86
NC_5/A14
116
NC_6/A13
120
NC_7
163
NC_8
162
VSS_45
165
VSS_46
168
VSS_47
171
VSS_48
172
VSS_49
177
VSS_50
178
VSS_51
183
VSS_52
184
VSS_53
187
VSS_54
190
VSS_55
193
VSS_56
196
VSS_57
201 202
VSS_58 VSS_59
DDRII_SOCKET---1ST
SMDDR_VREF_DIMM
PC2100 DDR2 SDRAM
SO-DIMM (200P)
R112
*10K/F/06
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
R111 0/06
2
3
8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54
59
60
65
66
71
72
77
78
121
122
127
128
132
133
138
139
144
145
149
150
155
156
161
SMDDR_VREF
1.8VSUS
C2
C587
C582
.1U/10V/04
D D
2.2U/6.3V/06
C1
2.2U/6.3V/06
.1U/10V/04
SO-DIMM BYPASS PLACEMENT :
C590
.1U/10V/04
C591
2.2U/6.3V/06
C4
2.2U/6.3V/06
C3
.1U/10V/04
SO-DIMM BYPASS PLACEMENT :
Place these Caps near So-Dimm1. Place these Caps near So-Dimm2
No Vias Betwe en the Trace of PIN to CAP.
No Vias Betwe en the Trace of PIN to CAP.
PROJECT : CW4
Size Document Number Rev
1
2
3
4
5
6
Date: Sheet
7
Quanta Computer Inc.
DDRII SO-DIMM(200P)
14 44Friday, November 03, 2006
of
8
1ACustom
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