Lenovo EVEREST Schematics

A

[e-mail]

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C

D

E

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PCB

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PCB

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Compal Confidential

2 2

Everest Schematics Document

Intel Merom Processor with Calistoga + DDRII + ICH7M

3 3

2007-05-15

REV: 1.0

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/08/18 2007/8/18

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

B

D

Date: Sheet

Compal Electronics, Inc.

Cover Page

LA-3781P

146Friday, May 18, 2007

E

0.1

of

A

Compal Confidential

B

C

D

E

Model Name : Everest
File Name : LA-3781P

1 1

NB8M

CRT

CRT

page 19

CRT

128M
VGA/B

2 2

LVDS

LCD Conn.

New Card
Socket

page 33

page 18

MINI Card

WLAN,
3G/TV-Tuner
Robson

page 32

LVDS

PCI-Express

PCI-Express

LAN(10/100M)

BCM5906

page 30

Intel Merom Processor

uPGA-478 Package

page 4,5,6

H_A#(3..35) H_D#(0..63)

Intel Calistoga GMCH

DMI
X4 mode

FSB

667/800MHz

PCBGA 1466

page 7,8,9,10,11,12,13

Intel ICH7-M

mBGA-652

page 20,21,22,23

LPC BUS

Memory BUS(DDRII)

USB conn x2
TO M/B

3.3V 48MHz

3.3V 24.576MHz/48Mhz

3.3V ATA-100
S-ATA

Dual Channel

1.8V DDRII 533/667

page 33

USB

IDE

port 0

S-ATA HDD
Conn.

page 24

200pin DDRII-SO-DIMM X2

BANK 0, 1, 2, 3

USB conn x2
TO I/O/B

page 37 page 33

CDROM
Conn.

Bluetooth
Conn

HD Audio

page 24

page 14,15

MDC 1.5
Conn

page 42

Card Reader

RTS 5158

page 28

HDA Codec

ALC861VD

page 38

3 in 1
socket

page 29

Audio AMP

RJ45

3 3

page 31

page 39

BIOS

page 36

Int SPK

Mic/Int

Mic/ExtLine-out

Sub BD

Fan Control

page 4

Clock Generator

SLG8LP465VTR

page 16

USB BD

K_SW

USBx2

Audio BD

Touch Pad

page 36

ENE KB926

page 34

SPI ROM

Int.KBD

page 35

Thermal Sensor

4 4

G781F

Power circuit

page 4

page X

SW Board

HDD/ODD NUM CAP Scroll PowerUserMute

MB

A

NOVO

Power Battery W/L

B

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/08/18 2007/8/18

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D

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc.

Block Diagrams

LA-3781P

of

246Friday, May 18, 2007

E

0.1

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[e-mail]

1 1

Voltage Rails

DescriptionPower Plane
VIN
B+
+CPU_CORE

+VCCP
+1.5VS
+1.8V

+2.5VS
+3VALW
+3VS

2 2

+5VALW
+5VS

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

Adapter power supply (19V)

AC or battery power rail for power circuit.

Core voltage for CPU

0.9V switched power rail for DDR terminator+0.9VS

VCCP switched power rail

1.5V switched power rail

1.8V power rail for DDR

1.8V switched power rail+1.8VS

2.5V switched power rail

3.3V always on power rail

3.3V switched power rail

5V always on power rail

5V switched power rail

RTC power+RTCVCC

SIGNAL

SLP_S3#SLP_S1#

HIGH HIGH HIGH

LOW

LOW

LOW

LOW LOW LOW

SLP_S4#

HIGH

LOWLOWLOW

SLP_S5#

HIGHHIGHHIGHHIGH

HIGH

HIGH

LOW

B

S3S1

N/A N/A N/A

OFFON
OFFON

ON

ON

OFF

ON
ON

OFF

ON

OFF

ON
ON

ON
OFF

ON OFF

ONONON

+VALW

ON

ON

ON

ON

ON

S5
N/AN/AN/A

OFF
OFF
OFFOFFON
OFFOFFON
OFF
OFF
OFF
ON*ON
OFF
ON*

ON*ONVSB always on power rail+VSB
ON

+V +VS Clock

ON

OFF

OFF

OFF

ONON

LOW

OFF

OFF

OFF

ON

ON

ON

OFF

OFF

C

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

D

External PCI Devices

DEVIC E REQ/GNT #

IDSEL #

No PCI Device

EC SM Bus1 address

Device

Smart Battery
EEPROM(24C16/02)

Address

1010 000X b

EC SM Bus2 address

Device

GMT-781
NVIDIA NB8X

E

PIRQ

Address

1001 100X b0001 011X b

3 3

BOARD ID Table

ID

I

I

0

H

H

L

L

1

0

2V0

2

/

3

3

I

4

G
T

5

3
0

6
7 R10A (MP)

PANEL ID Table

4 4

ID

UMA_DES

0

IHL00/IGT30 UMA

1

IHLV3 UMA

BRD ID

R01 (EVT)
R02 (DVT)
R03 (PVT)
R10A (MP)
R01 (EVT)
R02 (DVT)
R03 (PVT)

Vab

3.30V

2.20V

VabR54/42(Rb)

00V

8.2K

0.25V

18K

0.50V

33K

0.82V

56K

1.19V

100K

1.65V

200K

2.20V

NC

3.30V

ICH7M SM Bus address

Device

Clock Generator
(SLG8LP465VTR)

DDR DIMM0
DDR DIMM1

Wireless
NewCard
LAN

Address

1101 001Xb

1010 000Xb
1010 010Xb

2
3

4
5
6

IHLV2 VGA

7

IHL00/IGT30 VGA

A

0.25V
0V

B

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/08/18 2007/8/18

Compal Secret Data

Deciphered Date

D

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc.

Notes List

LA-3781P

346Friday, May 18, 2007

E

of

0.1

5

H_A#[3..31]<7>

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11

PAD

T48

H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_ADSTB#0
H_ADSTB#1

CLK_CPU_BCLK
CLK_CPU_BCLK#

H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
H_IERR#
H_LOCK#
H_RESET#

H_RS#0
H_RS#1
H_RS#2
H_TRDY#

ITP_DBRESET#

H_DBSY#
H_DPSLP#
H_DPRSTP#
H_DPWR#

H_PROCHOT#
H_PWRGOOD

H_CPUSLP#
ITP_TCK
ITP_TDI
ITP_TDO
TEST1
TEST2
ITP_TMS
ITP_TRST#

H_THERMDA
H_THERMDC
H_THERMTRIP#

D D

H_REQ#[0..4]<7>

H_ADSTB#0<7>
H_ADSTB#1<7>

C C

1 2

+VCCP

B B

H_PROCHOT#<44>

+VCCP

H_THERMDA, H_THERMDC routing together.
Trace width / Spacing = 10 / 10 mil

CLK_CPU_BCLK<15>

CLK_CPU_BCLK#<15>

H_ADS#<7>
H_BNR#<7>

H_BPRI#<7>

H_BR0#<7>

H_DEFER#<7>

H_RS#[0..2]<7>

ITP_DBRESET#<21>

H_PWRGOOD<20>

1 2
1 2

H_THERMTRIP#<7,20>

H_DRDY#<7>

H_HITM#<7>

H_LOCK#<7>

H_RESET#<7>

H_TRDY#<7>

H_DBSY#<7>

H_DPSLP#<20>

H_DPRSTP#<20,44>

H_DPWR#<7>

H_CPUSLP#<7,20>

R73

56_0402_5%

R70

1 2

68_0402_5%

R499 1K_0402_5%@
R307 51_0402_5%

H_HIT#<7>

JP15A

J4

A3#

L4

A4#

M3

A5#

K5

A6#

M1

A7#

N2

A8#

J1

A9#

N3

A10#

P5

A11#

P2

A12#

L1

A13#

P4

A14#

P1

A15#

R1

A16#

Y2

A17#

U5

A18#

R3

A19#

W6

A20#

U4

A21#

Y5

A22#

U2

A23#

R4

A24#

T5

ADDR GROUP

A25#

T3

A26#

W3

A27#

W5

A28#

Y4

A29#

W2

A30#

Y1

A31#

K3

REQ0#

H2

REQ1#

K2

REQ2#

J3

REQ3#

L5

REQ4#

L2

ADSTB0#

V4

ADSTB1#

A22

BCLK0

A21

H1

E2

G5

F1

H5

F21

G6

E4

D20

H4

B1

F3

F4
G3
G2

AD4
AD3
AD1
AC4

C20

E1

B5

E5

D24
AC2
AC1
D21

D6
D7

AC5
AA6
AB3
C26
D25
AB5
AB6

A24
A25

C7

HOST CLK

BCLK1

ADS#
BNR#
BPRI#
BR0#
DEFER#
DRDY#
HIT#

CONTROL

HITM#
IERR#
LOCK#
RESET#

RS0#
RS1#
RS2#
TRDY#

BPM0#
BPM1#
BPM2#
BPM3#

DBR#
DBSY#
DPSLP#
DPRSTP#
DPWR#
PRDY#
PREQ#
PROCHOT#

PWRGOOD
SLP#
TCK
TDI
TDO
TEST1
TEST2
TMS
TRST#

THERMAL

THERMDA

DIODE

THERMDC
THERMTRIP#

TYCO_1-1674770-2_Yonah~D

ME@

YONAH

MISC

4

DATA GROUP

LEGACY CPU

D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

DINV0#
DINV1#
DINV2#
DINV3#

DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#

A20M#
FERR#

IGNNE#

INIT#
LINT0
LINT1

STPCLK#

SMI#

3

H_D#[0..63] <7>

H_D#0

E22

D0#

H_D#1

F24

D1#

H_D#2

E26

D2#

H_D#3

H22

D3#

H_D#4

F23

D4#

H_D#5

G25

D5#

H_D#6

E25

D6#

H_D#7

E23

D7#

H_D#8

K24

D8#

H_D#9

G24

D9#

H_D#10

J24

H_D#11

J23

H_D#12

H26

H_D#13

F26

H_D#14

K22
H25
N22
K25
P26
R23
L25
L22
L23
M23
P25
P22
P23
T24
R24
L26
T25
N24
AA23
AB24
V24
V26
W25
U23
U25
U22
AB25
W22
Y23
AA26
Y26
Y22
AC26
AA24
AC22
AC23
AB22
AA21
AB21
AC25
AD20
AE22
AF23
AD24
AE21
AD21
AE25
AF25
AF22
AF26

J26
M26
V23
AC20

H23
M24
W24
AD23
G22
N25
Y25
AE24

A6
A5
C4
B3
C6
B4

D5
A3

H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_A20M#
H_FERR#
H_IGNNE#
H_INIT#
H_INTR
H_NMI

H_STPCLK#
H_SMI#

H_DINV#0 <7>
H_DINV#1 <7>
H_DINV#2 <7>
H_DINV#3 <7>

H_DSTBN#[0..3] <7>

H_DSTBP#[0..3] <7>

H_A20M# <20>
H_FERR# <20>
H_IGNNE# <20>
H_INIT# <20>
H_INTR <20>
H_NMI <20>

H_STPCLK# <20>
H_SMI# <20>

EC_SMB_CK2<31>
EC_SMB_DA2<31>

FAN1 Conn

EN_FAN1<31>

ITP_DBRESET#

C328

1 2

R511 200_0402_5%@

H_THERMDA
H_THERMDC

2200P_0402_50V7K

EC_SMB_DA2

+VCC_FAN1
EN_FAN1

FAN_SPEED1<31>

+5VS

2

1 2

U19

2

D+

3

D-

8

SCLK

7

SDATA

G781F_SOP8

Address:100_1100

C100 2.2U_0603_16V6K

U6

1

VEN

2

VIN

3

VO

4

VSET

G993P1UF_SOP8

ITP_TDI
ITP_TMS
ITP_TDO

ITP_TRST#
ITP_TCK

C327

1 2

0.1U_0402_16V4Z

VDD1

ALERT#

THERM#

GND

1 2

GND
GND
GND
GND

+3VS

12

R276
1K_0402_5%

1

C341
100P_0402_50V8J

2

This shall place near CPU

R509 56_0402_5%

1 2

R510 56_0402_1%

1 2

R512 56_0402_5%

1 2

R515 56_0402_5%

1 2

@

R513 56_0402_5%

1 2

R514 56_0402_5%

1 2

T35

PAD

+3VS

R268

@

40mil

+VCC_FAN1

10K_0402_5%

1 2

R267 0_0402_5%@

+5VS

1
6
4
5

8
7
6
5

THERM_SCI#
THERM#EC_SMB_CK2

+VCCP

12

12

+3VS

R26910K_0402_5% @

DIODE
Closed to

12

Connector

D8
1SS355_SOD323

D7

@

1N4148_SOT23@

1 2

C94

2.2U_0603_16V6K

1 2

C358

1000P_0402_50V7K

1 2

EC_THERM# <21,31>

Check : to sb

JP17

1

1

2

2

3

3

4

GND

5

GND

ACES_85205-03001

ME@

1

A A

H_PROCHOT# OCP#

+VCCP

12

R68

56_0402_5%@

B

2

E

3 1

C

Q4

@

MMBT3904_SOT23

5

OCP# <21>

H_DPSLP#

H_DPRSTP#

R487

1 2

56_0402_5%@

R486

1 2

56_0402_5%@

+VCCP

4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/08/18 2007/8/18

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Merom (1/3)

LA-3781P

of

446Friday, May 18, 2007

1

0.1

5

[e-mail]

D D

+VCCP

12

+CPU_GTLREF

R263
1K_0402_1%

12

R67
2K_0402_1%

Close to CPU pin AD26
within 500mils.

C C

+CPU_CORE

R266
100_0402_1%

1 2

R516
100_0402_1%

1 2

Close to CPU pin
within 500mils.

CPU_BSEL CPU_BSEL2 CPU_BSEL1

133

166

B B

A A

00

0

12

R76

R261

54.9_0402_1%

27.4_0402_1%

VCCSENSE

VSSSENSE

12

R264

4

Length match within 25 mils
The trace width 18 mils space
7 mils

+1.5VS

1

C283

C284

2

0.01U_0402_16V7K

CPU_BSEL0

1

1

Resistor placed within

0.5" of CPU pin.Trace
should be at least 25
mils away from any
other toggling signal.

12

27.4_0402_1%

1

R517

12

54.9_0402_1%

1

2

10U_0805_10V4Z

VCCSENSE<44>

VSSSENSE<44>

H_PSI#<44>

CPU_VID0<44>
CPU_VID1<44>
CPU_VID2<44>
CPU_VID3<44>
CPU_VID4<44>
CPU_VID5<44>
CPU_VID6<44>

+CPU_GTLREF

CPU_BSEL0<15>
CPU_BSEL1<15>
CPU_BSEL2<15>

+CPU_CORE

+VCCP

3

VCCSENSE
VSSSENSE

H_PSI#
CPU_VID0

CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

COMP0
COMP1
COMP2
COMP3

JP15B

AF7

VCCSENSE

AE7

VSSSENSE

B26

VCCA

K6

VCCP

J6

VCCP

M6

VCCP

N6

VCCP

T6

VCCP

R6

VCCP

K21

VCCP

J21

VCCP

M21

VCCP

N21

VCCP

T21

VCCP

R21

VCCP

V21

VCCP

W21

VCCP

V6

VCCP

G21

VCCP

AE6

PSI#

AD6

VID0

AF5

VID1

AE5

VID2

AF4

VID3

AE3

VID4

AF2

VID5

AE2

VID6

AD26

GTLREF

B22

BSEL0

B23

BSEL1

C21

BSEL2

R26

COMP0

U26

COMP1

U1

COMP2

V1

COMP3

E7

VCC

AB20

VCC

AA20

VCC

AF20

VCC

AE20

VCC

AB18

VCC

AB17

VCC

AA18

VCC

AA17

VCC

AD18

VCC

AD17

VCC

AC18

VCC

AC17

VCC

AF18

VCC

AF17

VCC

D2

RSVD

F6

RSVD

D3

RSVD

C1

RSVD

AF1

RSVD

D22

RSVD

C23

RSVD

C24

RSVD

AA1

RSVD

AA4

RSVD

AB2

RSVD

AA3

RSVD

M4

RSVD

N5

RSVD

T2

RSVD

V3

RSVD

B2

RSVD

C3

RSVD

T22

RSVD

B25

RSVD

TYCO_1-1674770-2_Yonah~D

ME@

YONAH

POWER, GROUNG, RESERVED SIGNALS AND NC

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AB26
AA25
AD25
AE26
AB23
AC24
AF24
AE23
AA22
AD22
AC21
AF21
AB19
AA19
AD19
AC19
AF19
AE19
AB16
AA16
AD16
AC16
AF16
AE16
AB13
AA14
AD13
AC14
AF13
AE14
AB11
AA11
AD11
AC11
AF11
AE11
AB8
AA8
AD8
AC8
AF8
AE8
AA5
AD5
AC6
AF6
AB4
AC3
AF3
AE4
AB1
AA2
AD2
AE1
B6
C5
F5
E6
H6
J5
M5
L6
P6
R5
V5
U6
Y6
A4
D4
E3
H3
G4
K4
L3
P3
N4
T4
U3
Y3
W4
D1
C2
F2
G1

2

+CPU_CORE

JP15C

AE18

VCC

AE17

VCC

AB15

VCC

AA15

VCC

AD15

VCC

AC15

VCC

AF15

VCC

AE15

VCC

AB14

VCC

AA13

VCC

AD14

VCC

AC13

VCC

AF14

VCC

AE13

VCC

AB12

VCC

AA12

VCC

AD12

VCC

AC12

VCC

AF12

VCC

AE12

VCC

AB10

VCC

AB9

VCC

AA10

VCC

AA9

VCC

AD10

VCC

AD9

VCC

AC10

VCC

AC9

VCC

AF10

VCC

AF9

VCC

AE10

VCC

AE9

VCC

AB7

VCC

AA7

VCC

AD7

VCC

AC7

VCC

B20

VCC

A20

VCC

F20

VCC

E20

VCC

B18

VCC

B17

VCC

A18

VCC

A17

VCC

D18

VCC

D17

VCC

C18

VCC

C17

VCC

F18

VCC

F17

VCC

E18

VCC

E17

VCC

B15

VCC

A15

VCC

D15

VCC

C15

VCC

F15

VCC

E15

VCC

B14

VCC

A13

VCC

D14

VCC

C13

VCC

F14

VCC

E13

VCC

B12

VCC

A12

VCC

D12

VCC

C12

VCC

F12

VCC

E12

VCC

B10

VCC

B9

VCC

A10

VCC

A9

VCC

D10

VCC

D9

VCC

C10

VCC

C9

VCC

F10

VCC

F9

VCC

E10

VCC

E9

VCC

B7

VCC

A7

VCC

F7

VCC

TYCO_1-1674770-2_Yonah~D

ME@

YONAH

POWER, GROUND

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

K1
J2
M2
N1
T1
R2
V2
W1
A26
D26
C25
F25
B24
A23
D23
E24
B21
C22
F22
E21
B19
A19
D19
C19
F19
E19
B16
A16
D16
C16
F16
E16
B13
A14
D13
C14
F13
E14
B11
A11
D11
C11
F11
E11
B8
A8
D8
C8
F8
E8
G26
K26
J25
M25
N26
T26
R25
V25
W26
H24
G23
K23
L24
P24
N23
T23
U24
Y24
W23
H21
J22
M22
L21
P21
R22
V22
U21
Y21

1

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/08/18 2007/8/18

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Merom (2/3)

LA-3781P

546Friday, May 18, 2007

1

0.1

of

5

4

3

2

1

+CPU_CORE

3 x 330uF(9mOhm/2)

1

+

C298

2

330U_D2E_2.5VM_R9

D D

+CPU_CORE

1

C26

@

2

10U_0805_6.3V6M

1

+

C297
330U_D2E_2.5VM_R9

2

South Side Seco ndary North Side Sec ondary

10U_0805_6.3V6M

1

C27

2

1

C28

2

10U_0805_6.3V6M

10U_0805_6.3V6M

+CPU_CORE

1

C29

2

10U_0805_6.3V6M

3 x 330uF(9mOhm/2)

1

+

C332

2

330U_D2E_2.5VM_R9

1

C30

10U_0805_6.3V6M

2

1

+

C331
330U_D2E_2.5VM_R9

2

1

C31

@

2

10U_0805_6.3V6M

1

2

C32

10U_0805_6.3V6M

1

C33

2

(Place these capacitors on South side,Secondary Layer)

+CPU_CORE

1

C56

2

C C

10U_0805_6.3V6M

+CPU_CORE

1

C315

@

2

10U_0805_6.3V6M

1

C55

10U_0805_6.3V6M

2

(Place these capacitors on North side,Secondary Layer)

1

C316

10U_0805_6.3V6M

2

1

2

10U_0805_6.3V6M

1

2

10U_0805_6.3V6M

C54

C305

10U_0805_6.3V6M

10U_0805_6.3V6M

1

C53

2

1

C306

2

1

C52

2

10U_0805_6.3V6M

1

C307

2

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

1

2

1

2

C51

10U_0805_6.3V6M

C308

10U_0805_6.3V6M

1

2

1

2

C50

C309

10U_0805_6.3V6M

10U_0805_6.3V6M

1

C49

2

1

C310

2

9/25 10U checked. OK for use!

(Place these capacitors on South side,Primary Layer)

+CPU_CORE

1

C313

2

10U_0805_6.3V6M

B B

+CPU-CORE
Decoupling
SPCAP,Polymer

1

C314

@

10U_0805_6.3V6M

2

(Place these capacitors on North side,Primary Layer)

MLCC 0805 X5R

+VCCP

1

+

220U_B2_2.5VM_R35

A A

C324

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

2

0.1U_0402_16V4Z

C38

0.1U_0402_16V4Z

1

C323

2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

C322

2

10U_0805_6.3V6M

1

C321

2

10U_0805_6.3V6M

1

C320

2

10U_0805_6.3V6M

C,uF ESR, mohm ESL,nH
6X330uF 9m ohm/6 1.8nH/6

32X22uF 3m ohm/32 0.6nH/32
32X10uF 3m ohm/32 0.6nH/32

1

2

C43

0.1U_0402_16V4Z

1

2

2006/08/18 2007/8/18

3

1

C58

0.1U_0402_16V4Z

2

Compal Secret Data

1

C24

2

0.1U_0402_16V4Z

Deciphered Date

C39

0.1U_0402_16V4Z

1

C45

2

1

2

C319

2

10U_0805_6.3V6M

1

C318

2

Title

Size Document Number Re v

B

Date: Sheet

Compal Electronics, Inc.

Merom (3/3)

LA-3691P

0.1

646Friday, May 18, 2007

1

of

5

[e-mail]

4

3

2

1

H_D#[0..63]<4>

D D

C C

B B

A A

U20

965GM

PM@

12

R35

54.9_0402_1%

+VCCP

12

R283

54.9_0402_1%

R39

24.9_0402_1%

+VCCP

12

R31

12

R37

12

100_0402_1%

200_0402_1%

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

+H_VREF

H_XRCOMP
H_XSCOMP
H_YRCOMP
H_YSCOMP
+H_SWNG0
+H_SWNG1

12

R24

24.9_0402_1%

Layout Note:
H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 /
H_SWNG1 trace width and spacing is 10/20.

+H_VREF

1

C91

2

0.1U_0402_16V4Z

5

K11
T10

W11

U11
T11

W9

W7

W6

AB7
AA9

W4
W3

W5
Y10
AB8

W2
AA4
AA7
AA2
AA6

AA10

AA1
AB4
AC9

AB11
AC11

AB3
AC2
AD1
AD9
AC1
AD7
AC6
AB5

AD10

AD4
AC8

J13
K13

W1

U20A

F1

HD0#

J1

HD1#

H1

HD2#

J6

HD3#

H3

HD4#

K2

HD5#

G1

HD6#

G2

HD7#

K9

HD8#

K1

HD9#

K7

HD10#

J8

HD11#

H4

HD12#

J3

HD13#
HD14#

G4

HD15#
HD16#
HD17#

T3

HD18#

U7

HD19#

U9

HD20#
HD21#
HD22#
HD23#

T1

HD24#

T8

HD25#

T4

HD26#
HD27#

U5

HD28#

T9

HD29#
HD30#

T5

HD31#
HD32#
HD33#
HD34#
HD35#

Y3

HD36#

Y7

HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#

Y8

HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#

HVREF0
HVREF1

E1

HXRCOMP

E2

HXSCOMP

Y1

HYRCOMP

U1

HYSCOMP

E4

HXSWING
HYSWING

CALISTOGA_FCBGA1466~D

GM@

HA3#
HA4#
HA5#
HA6#
HA7#
HA8#

HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

HADSTB#0
HADSTB#1

HOST

HCLKN
HCLKP

HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3

HDINV#0
HDINV#1
HDINV#2
HDINV#3

HCPURST#

HADS#

HTRDY#

HDPWR#

HDRDY#

HDEFER#

HHITM#

HHIT#

HLOCK#

HBREQ0#

HBNR#

HBPRI#

HDBSY#

HCPUSLP#

HRS0#
HRS1#
HRS2#

+VCCP

12

R520

221_0603_1%

12

R168

100_0402_1%

H9
C9
E11
G11
F11
G12
F9
H11
J12
G14
D9
J14
H13
J15
F14
D12
A11
C11
A12
A13
E13
G13
F12
B12
B14
C12
A14
C14
D14

D8
G8
B8
F8
A8

B9
C13

AG1
AG2

K4
T7
Y5
AC4
K3
T6
AA5
AC5

J7
W8
U3
AB10

B7
E8
E7
J9
H8
C3
D4
D3
B3
C7
C6
F6
A7
E3

B4
E6
D6

+H_SWNG0

1

2

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_ADSTB#0
H_ADSTB#1

CLK_MCH_BCLK#
CLK_MCH_BCLK

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_RESET#
H_ADS#
H_TRDY#
H_DPWR#
H_DRDY#
H_DEFER#
H_HITM#
H_HIT#
H_LOCK#
H_BR0#
H_BNR#
H_BPRI#
H_DBSY#
H_CPUSLP#

H_RS#0
H_RS#1
H_RS#2

C303

0.1U_0402_16V4Z

4

+VCCP

12

R521

12

R28

H_A#[3..31] <4>

H_REQ#[0..4] <4>

H_ADSTB#0 <4>
H_ADSTB#1 <4>

CLK_MCH_BCLK# <15>
CLK_MCH_BCLK <15>
H_DSTBN#[0..3] <4>

H_DSTBP#[0..3] <4>

H_DINV#0 <4>
H_DINV#1 <4>
H_DINV#2 <4>
H_DINV#3 <4>

H_RESET# <4>
H_ADS# <4>
H_TRDY# <4>
H_DPWR# <4>
H_DRDY# <4>
H_DEFER# <4>
H_HITM# <4>
H_HIT# <4>
H_LOCK# <4>
H_BR0# <4>
H_BNR# <4>
H_BPRI# <4>
H_DBSY# <4>
H_CPUSLP# <4,20>

H_RS#[0..2] <4>

221_0603_1%

+H_SWNG1

1

C286

2

100_0402_1%

0.1U_0402_16V4Z

DMI_TXN0<21>
DMI_TXN1<21>
DMI_TXN2<21>
DMI_TXN3<21>

DMI_TXP0<21>
DMI_TXP1<21>
DMI_TXP2<21>
DMI_TXP3<21>

DMI_RXN0<21>
DMI_RXN1<21>
DMI_RXN2<21>
DMI_RXN3<21>

DMI_RXP0<21>
DMI_RXP1<21>
DMI_RXP2<21>
DMI_RXP3<21>

DDRA_CLK0<13>
DDRA_CLK1<13>
DDRB_CLK0<14>
DDRB_CLK1<14>

DDRA_CLK0#<13>
DDRA_CLK1#<13>
DDRB_CLK0#<14>
DDRB_CLK1#<14>

DDRA_CKE0<13>
DDRA_CKE1<13>
DDRB_CKE0<14>
DDRB_CKE1<14>

DDRA_SCS0#<13>
DDRA_SCS1#<13>
DDRB_SCS0#<14>
DDRB_SCS1#<14>

+1.8V

PM_DPRSLPVR<21,44>

0_0402_5%

PLT_RST_BUF#<16,19,21,23,24,27,29>

DDRA_ODT0<13>
DDRA_ODT1<13>
DDRB_ODT0<14>
DDRB_ODT1<14>

R33 80.6_0402_1%

1 2
1 2

R518 80.6_0402_1%

R164

+DDR_MCH_REF

PM_BMBUSY#<21>
PM_EXTTS#0<13,14>

12

H_THERMTRIP#<4,20>

ICH_POK<21,31>

R117 100_0402_1%

MCH_ICH_SYNC#<19>

Layout Note:
+DDR_MCH_REF
trace width and
spacing is 20/20.

+DDR_MCH_REF

C287

0.1U_0402_16V4Z

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

M_OCDOCMP0
M_OCDOCMP1

SMRCOMPN
SMRCOMPP

PM_BMBUSY#
PM_EXTTS#0
PM_EXTTS#1
H_THERMTRIP#
ICH_POK
PLTRST_R#

12

+1.8V

12

R282

100_0402_1%

12

1

2

2006/08/18 2007/8/18

R27

100_0402_1%

Compal Secret Data

U20B

AE35

DMIRXN0

AF39

DMIRXN1

AG35

DMIRXN2

AH39

DMIRXN3

AC35

DMIRXP0

AE39

DMIRXP1

AF35

DMIRXP2

AG39

DMIRXP3

AE37

DMITXN0

AF41

DMITXN1

AG37

DMITXN2

AH41

DMITXN3

AC37

DMITXP0

AE41

DMITXP1

AF37

DMITXP2

AG41

DMITXP3

AY35

SM_CK0

AR1

SM_CK1

AW7

SM_CK2

AW40

SM_CK3

AW35

SM_CK0#

AT1

SM_CK1#

AY7

SM_CK2#

AY40

SM_CK3#

AU20

SM_CKE0

AT20

SM_CKE1

BA29

SM_CKE2

AY29

SM_CKE3

AW13

SM_CS0#

AW12

SM_CS1#

AY21

SM_CS2#

AW21

SM_CS3#

AL20

SM_OCDCOMP0

AF10

SM_OCDCOMP1

BA13

SM_ODT0

BA12

SM_ODT1

AY20

SM_ODT2

AU21

SM_ODT3

AV9

SM_RCOMPN

AT9

SM_RCOMPP

AK1

SM_VREF0

AK41

SM_VREF1

G28

PM_BMBUSY#

F25

PM_EXTTS0#

H26

PM_EXTTS1#

G6

PM_THERMTRIP#

AH33

PWROK

AH34

RSTIN#

K28

ICH_SYNC#

CALISTOGA_FCBGA1466~D

GM@

Deciphered Date

DMI

DDR MUXING

2

PM

CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16

CFG

CFG17
CFG18
CFG19
CFG20

G_CLKP
G_CLKN

D_REF_CLKN
D_REF_CLKP

CLKNC

D_REF_SSCLKN
D_REF_SSCLKP

CLK_REQ#

RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5
RESERVED6
RESERVED7
RESERVED8

RESERVED9
RESERVED10
RESERVED11
RESERVED12
RESERVED13

RESERVED

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9

NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18

NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9

Description at page15.

MCH_CLKSEL0

K16

MCH_CLKSEL1

K18

MCH_CLKSEL2

J18

CFG3

F18

CFG4

E15

CFG5

F15

CFG6

E18

CFG7

D19

CFG8

D16

CFG9

G16

CFG10

E16

CFG11

D15

CFG12

G15

CFG13

K15

CFG14

C15

CFG15

H16

CFG16

G18

CFG17

H15

CFG18

J25

CFG19

K27

CFG20

J26

CLK_MCH_3GPLL

AG33

CLK_MCH_3GPLL#

AF33

CLK_MCH_DREFCLK#

A27

CLK_MCH_DREFCLK

A26

CLK_MCH_SS CDREF CLK#

C40

CLK_MCH_SSCDREFCLK

D41

MCH_CLKREQ#

H32

A3
A39
A4
A40
AW1
AW41
AY1
BA1
BA2
BA3
BA39
BA40
BA41
C1
AY41
B2
B41
C41
D1

T32
R32
F3
F7
AG11
AF11
H7
J19
A41
A34
D28
D27
A35

PM_EXTTS#0

PM_EXTTS#1

M_OCDOCMP0

M_OCDOCMP1

Title

Size Document Number Rev

Custom

LA-3691P

Date: Sheet

MCH_CLKSEL0 <15>
MCH_CLKSEL1 <15>
MCH_CLKSEL2 <15>

T9

PAD

T3

PAD

CFG5 <11>

T10

PAD

CFG7 <11>

T7

PAD

CFG9 <11>

T5

PAD

CFG11 <11>
CFG12 <11>
CFG13 <11>

T2

PAD

T8

PAD

CFG16 <11>

T1

PAD

CFG18 <11>
CFG19 <11>
CFG20 <11>

CLK_MCH_3GPLL <15>
CLK_MCH_3GPLL# <15>

CLK_MCH_DREFCLK# <15>
CLK_MCH_DREFCLK <15>

CLK_MCH_SSCDREF CLK# <15>
CLK_MCH_SSCDREFCLK <15>

MCH_CLKREQ# <15>

+3VS

R519

10K_0402_5%

12

R279

10K_0402_5%@

12

R112

40.2_0402_1%@

12

R32

40.2_0402_1%@

12

Compal Electronics, Inc.

Crestline (1/7)-GTL

746Friday, May 18, 2007

1

of

0.1

5

4

3

2

1

DDRA_SDQ[0..63]<13>

DDRA_SDM[0..7]<13>

DDRA_SMA[0..13]<13>

D D

DDRA_SBS0<13>
DDRA_SBS1<13>
DDRA_SBS2<13>

DDRA_SDM0
DDRA_SDM1
DDRA_SDM2
DDRA_SDM3
DDRA_SDM4
DDRA_SDM5
DDRA_SDM6
DDRA_SDM7

DDRA_SDQS0<13>
DDRA_SDQS1<13>
DDRA_SDQS2<13>
DDRA_SDQS3<13>
DDRA_SDQS4<13>
DDRA_SDQS5<13>
DDRA_SDQS6<13>

C C

B B

DDRA_SDQS7<13>

DDRA_SDQS0#<13>
DDRA_SDQS1#<13>
DDRA_SDQS2#<13>
DDRA_SDQS3#<13>
DDRA_SDQS4#<13>
DDRA_SDQS5#<13>
DDRA_SDQS6#<13>
DDRA_SDQS7#<13>

DDRA_SCAS#<13>
DDRA_SRAS#<13>

T12 PAD

DDRA_SWE#<13>

DDRA_SDQS0
DDRA_SDQS1
DDRA_SDQS2
DDRA_SDQS3
DDRA_SDQS4
DDRA_SDQS5
DDRA_SDQS6
DDRA_SDQS7

DDRA_SDQS0#
DDRA_SDQS1#
DDRA_SDQS2#
DDRA_SDQS3#
DDRA_SDQS4#
DDRA_SDQS5#
DDRA_SDQS6#
DDRA_SDQS7#

DDRA_SMA0
DDRA_SMA1
DDRA_SMA2
DDRA_SMA3
DDRA_SMA4
DDRA_SMA5
DDRA_SMA6
DDRA_SMA7
DDRA_SMA8

DDRA_SMA9
DDRA_SMA10
DDRA_SMA11
DDRA_SMA12
DDRA_SMA13

SA_RCVENIN# SB_RCVENIN#

U20D

AU12

SA_BS0

AV14

SA_BS1

BA20

SA_BS2

AJ33

SA_DM0

AM35

SA_DM1

AL26

SA_DM2

AN22

SA_DM3

AM14

SA_DM4

AL9

SA_DM5

AR3

SA_DM6

AH4

SA_DM7

AK33

SA_DQS0

AT33

SA_DQS1

AN28

SA_DQS2

AM22

SA_DQS3

AN12

SA_DQS4

AN8

SA_DQS5

AP3

SA_DQS6

AG5

SA_DQS7

AK32

SA_DQS0#

AU33

SA_DQS1#

AN27

SA_DQS2#

AM21

SA_DQS3#

AM12

SA_DQS4#

AL8

SA_DQS5#

AN3

SA_DQS6#

AH5

SA_DQS7#

AY16

SA_MA0

AU14

SA_MA1

AW16

SA_MA2

BA16

SA_MA3

BA17

SA_MA4

AU16

SA_MA5

AV17

SA_MA6

AU17

SA_MA7

AW17

SA_MA8

AT16

SA_MA9

AU13

SA_MA10

AT17

SA_MA11

AV20

SA_MA12

AV12

SA_MA13

AY13

SA_CAS#

AW14

SA_RAS#

AY14

SA_WE#

AK23

SA_RCVENIN#

AK24

SA_RCVENOUT#

CALISTOGA_FCBGA1466~D

GM@

DDRA_SDQ[0..63]
DDRA_SDM[0..7]

DDRA_SMA[0..13]

DDR SYS MEMORY A

SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8

SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

AJ35
AJ34
AM31
AM33
AJ36
AK35
AJ32
AH31
AN35
AP33
AR31
AP31
AN38
AM36
AM34
AN33
AK26
AL27
AM26
AN24
AK28
AL28
AM24
AP26
AP23
AL22
AP21
AN20
AL23
AP24
AP20
AT21
AR12
AR14
AP13
AP12
AT13
AT12
AL14
AL12
AK9
AN7
AK8
AK7
AP9
AN9
AT5
AL5
AY2
AW2
AP1
AN2
AV2
AT3
AN1
AL2
AG7
AF9
AG4
AF6
AG9
AH6
AF4
AF8

DDRA_SDQ0
DDRA_SDQ1
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ4
DDRA_SDQ5
DDRA_SDQ6
DDRA_SDQ7
DDRA_SDQ8

DDRA_SDQ9
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDQ14
DDRA_SDQ15
DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDQ22
DDRA_SDQ23
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDQ26
DDRA_SDQ27
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQ30
DDRA_SDQ31
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDQ38
DDRA_SDQ39
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQ46
DDRA_SDQ47
DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDQ54
DDRA_SDQ55
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDQ58
DDRA_SDQ59
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQ62
DDRA_SDQ63

DDRB_SBS0<14>
DDRB_SBS1<14>
DDRB_SBS2<14>

DDRB_SDQS0<14>
DDRB_SDQS1<14>
DDRB_SDQS2<14>
DDRB_SDQS3<14>
DDRB_SDQS4<14>
DDRB_SDQS5<14>
DDRB_SDQS6<14>
DDRB_SDQS7<14>

DDRB_SDQS0#<14>
DDRB_SDQS1#<14>
DDRB_SDQS2#<14>
DDRB_SDQS3#<14>
DDRB_SDQS4#<14>
DDRB_SDQS5#<14>
DDRB_SDQS6#<14>
DDRB_SDQS7#<14>

DDRB_SCAS#<14>
DDRB_SRAS#<14>

DDRB_SWE#<14>

T4 PADT6 PAD
T11 PAD

DDRB_SDQ[0..63]<14>

DDRB_SDM[0..7]<14>

DDRB_SMA[0..13]<14>

DDRB_SDM0
DDRB_SDM1
DDRB_SDM2
DDRB_SDM3
DDRB_SDM4
DDRB_SDM5
DDRB_SDM6
DDRB_SDM7

DDRB_SDQS0
DDRB_SDQS1
DDRB_SDQS2
DDRB_SDQS3
DDRB_SDQS4
DDRB_SDQS5
DDRB_SDQS6
DDRB_SDQS7

DDRB_SDQS0#
DDRB_SDQS1#
DDRB_SDQS2#
DDRB_SDQS3#
DDRB_SDQS4#
DDRB_SDQS5#
DDRB_SDQS6#
DDRB_SDQS7#

DDRB_SMA0
DDRB_SMA1
DDRB_SMA2
DDRB_SMA3
DDRB_SMA4
DDRB_SMA5
DDRB_SMA6
DDRB_SMA7
DDRB_SMA8

DDRB_SMA9
DDRB_SMA10
DDRB_SMA11
DDRB_SMA12
DDRB_SMA13

SB_RCVENOUT#SA_RCVENOUT#

U20E

AT24
AV23
AY28

AK36
AR38
AT36
BA31
AL17

AH8
BA5
AN4

AM39

AT39
AU35
AR29
AR16
AR10

AR7
AN5

AM40

AU39
AT35
AP29
AP16
AT10

AT7
AP5

AY23

AW24

AY24
AR28
AT27
AT28
AU27
AV28
AV27

AW27

AV24
BA27
AY27
AR23

AR24
AU23
AR27
AK16
AK18

CALISTOGA_FCBGA1466~D

GM@

SB_BS0
SB_BS1
SB_BS2

SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM4
SB_DM5
SB_DM6
SB_DM7

SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7

SB_DQS0#
SB_DQS1#
SB_DQS2#
SB_DQS3#
SB_DQS4#
SB_DQS5#
SB_DQS6#
SB_DQS7#

SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13

SB_CAS#
SB_RAS#
SB_WE#
SB_RCVENIN#
SB_RCVENOUT#

DDRB_SDQ[0..63]
DDRB_SDM[0..7]
DDRB_SMA[0..13]

DDR SYS MEMORY B

SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8

SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

AK39
AJ37
AP39
AR41
AJ38
AK38
AN41
AP41
AT40
AV41
AU38
AV38
AP38
AR40
AW38
AY38
BA38
AV36
AR36
AP36
BA36
AU36
AP35
AP34
AY33
BA33
AT31
AU29
AU31
AW31
AV29
AW29
AM19
AL19
AP14
AN14
AN17
AM16
AP15
AL15
AJ11
AH10
AJ9
AN10
AK13
AH11
AK10
AJ8
BA10
AW10
BA4
AW4
AY10
AY9
AW5
AY5
AV4
AR5
AK4
AK3
AT4
AK5
AJ5
AJ3

DDRB_SDQ0
DDRB_SDQ1
DDRB_SDQ2
DDRB_SDQ3
DDRB_SDQ4
DDRB_SDQ5
DDRB_SDQ6
DDRB_SDQ7
DDRB_SDQ8

DDRB_SDQ9
DDRB_SDQ10
DDRB_SDQ11
DDRB_SDQ12
DDRB_SDQ13
DDRB_SDQ14
DDRB_SDQ15
DDRB_SDQ16
DDRB_SDQ17
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ20
DDRB_SDQ21
DDRB_SDQ22
DDRB_SDQ23
DDRB_SDQ24
DDRB_SDQ25
DDRB_SDQ26
DDRB_SDQ27
DDRB_SDQ28
DDRB_SDQ29
DDRB_SDQ30
DDRB_SDQ31
DDRB_SDQ32
DDRB_SDQ33
DDRB_SDQ34
DDRB_SDQ35
DDRB_SDQ36
DDRB_SDQ37
DDRB_SDQ38
DDRB_SDQ39
DDRB_SDQ40
DDRB_SDQ41
DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ44
DDRB_SDQ45
DDRB_SDQ46
DDRB_SDQ47
DDRB_SDQ48
DDRB_SDQ49
DDRB_SDQ50
DDRB_SDQ51
DDRB_SDQ52
DDRB_SDQ53
DDRB_SDQ54
DDRB_SDQ55
DDRB_SDQ56
DDRB_SDQ57
DDRB_SDQ58
DDRB_SDQ59
DDRB_SDQ60
DDRB_SDQ61
DDRB_SDQ62
DDRB_SDQ63

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/08/18 2007/8/18

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Crestline (2/7)-DMI/DDR

LA-3691P

1

846Friday, May 18, 2007

0.1

of

5

[e-mail]

LVDS_A0<17>
LVDS_A1<17>

D D

C C

GMCH_CRT_R

R397 150_0402_1%GM@
R526 150_0402_1%GM@
R524 150_0402_1%GM@

B B

12
12
12

GMCH_CRT_G
GMCH_CRT_B

LVDS_A2<17>
LVDS_A0#<17>

LVDS_A1#<17>
LVDS_A2#<17>

LVDS_B0<17>
LVDS_B1<17>
LVDS_B2<17>

LVDS_B0#<17>
LVDS_B1#<17>
LVDS_B2#<17>

LVDS_ACLK<17>
LVDS_ACLK#<17>
LVDS_BCLK<17>
LVDS_BCLK#<17>

GMCH_ENBKL<17>

LVDS_SCL<17>

LVDS_SDA<17>

GMCH_ENVDD<17>

GMCH_CRT_CLK<18>

GMCH_CRT_DATA<18>

GMCH_CRT_VSYNC<18>
GMCH_CRT_HSYNC<18>

GMCH_CRT_B<18>
GMCH_CRT_G<18>
GMCH_CRT_R<18>

4

LVDS_A0
LVDS_A1
LVDS_A2

LVDS_A0#
LVDS_A1#
LVDS_A2#

LVDS_B0
LVDS_B1
LVDS_B2

LVDS_B0#
LVDS_B1#
LVDS_B2#

LVDS_ACLK
LVDS_ACLK#
LVDS_BCLK
LVDS_BCLK#

R104 1.5K_0402_1%

GMCH_ENBKL

12

R114

4.99K_0402_1%

R122

255_0402_1%

3

R113

U20C

H27

SDVOCTRL_DATA

H28

SDVOCTRL_CLK

B37

LA_DATA0

B34

LA_DATA1

A36

LA_DATA2

C37

LA_DATA#0

B35

LA_DATA#1

A37

LA_DATA#2

F30

LB_DATA0

D29

LB_DATA1

F28

LB_DATA2

G30

LB_DATA#0

D30

LB_DATA#1

F29

LB_DATA#2

A32

LA_CLK

A33

LA_CLK#

E26

LB_CLK

E27

LB_CLK#

D32

LBKLT_CTL

J30

LBKLT_EN

H30

LCTLA_CLK

H29

LCTLB_DATA

G26

LDDC_CLK

G25

LDDC_DATA

F32

LVDD_EN

B38

LIBG

C35

LVBG

C33

LVREFH

C32

LVREFL

A16

TVDAC_A

C18

TVDAC_B

A19

TVDAC_C

J20

12

12

TV_IREF

B16

TV_IRTNA

B18

TV_IRTNB

B19

TV_IRTNC

J29

TV_DCONSEL1

K30

TV_DCONSEL0

C26

DDCCLK

C25

DDCDATA

H23

VSYNC

G23

HSYNC

E23

BLUE

D23

BLUE#

C22

GREEN

B22

GREEN#

A21

RED

B21

RED#

J22

CRT_IREF

CALISTOGA_FCBGA1466~D

GM@

LVDS

TV CRT

EXP_COMPI

EXP_COMPO

EXP_RXN0
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8

EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15

EXP_RXP0
EXP_RXP1
EXP_RXP2
EXP_RXP3
EXP_RXP4
EXP_RXP5
EXP_RXP6
EXP_RXP7
EXP_RXP8

EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15

EXP_TXN0

EXP_TXN1

EXP_TXN2

EXP_TXN3

EXP_TXN4

EXP_TXN5

EXP_TXN6

EXP_TXN7

EXP_TXN8

PCI-EXPRESS GRAPHICS

EXP_TXN9

EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15

EXP_TXP0

EXP_TXP1

EXP_TXP2

EXP_TXP3

EXP_TXP4

EXP_TXP5

EXP_TXP6

EXP_TXP7

EXP_TXP8

EXP_TXP9

EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15

D40
D38

PCIE_GTX_C_MRX_N0

F34

PCIE_GTX_C_MRX_N1

G38

PCIE_GTX_C_MRX_N2

H34

PCIE_GTX_C_MRX_N3

J38

PCIE_GTX_C_MRX_N4

L34

PCIE_GTX_C_MRX_N5

M38

PCIE_GTX_C_MRX_N6

N34

PCIE_GTX_C_MRX_N7

P38

PCIE_GTX_C_MRX_N8

R34

PCIE_GTX_C_MRX_N9

T38

PCIE_GTX_C_MRX_N10

V34

PCIE_GTX_C_MRX_N11

W38

PCIE_GTX_C_MRX_N12

Y34

PCIE_GTX_C_MRX_N13

AA38

PCIE_GTX_C_MRX_N14

AB34

PCIE_GTX_C_MRX_N15

AC38

PCIE_GTX_C_MRX_P0

D34

PCIE_GTX_C_MRX_P1

F38

PCIE_GTX_C_MRX_P2

G34

PCIE_GTX_C_MRX_P3

H38

PCIE_GTX_C_MRX_P4

J34

PCIE_GTX_C_MRX_P5

L38

PCIE_GTX_C_MRX_P6

M34

PCIE_GTX_C_MRX_P7

N38

PCIE_GTX_C_MRX_P8

P34

PCIE_GTX_C_MRX_P9

R38

PCIE_GTX_C_MRX_P10

T34

PCIE_GTX_C_MRX_P11

V38

PCIE_GTX_C_MRX_P12

W34

PCIE_GTX_C_MRX_P13

Y38

PCIE_GTX_C_MRX_P14

AA34

PCIE_GTX_C_MRX_P15

AB38

PCIE_MTX_GRX_N0

F36

PCIE_MTX_GRX_N1

G40

PCIE_MTX_GRX_N2

H36

PCIE_MTX_GRX_N3

J40

PCIE_MTX_GRX_N4

L36

PCIE_MTX_GRX_N5

M40

PCIE_MTX_GRX_N6

N36

PCIE_MTX_GRX_N7

P40

PCIE_MTX_GRX_N8

R36

PCIE_MTX_GRX_N9

T40

PCIE_MTX_GRX_N10

V36

PCIE_MTX_GRX_N11

W40

PCIE_MTX_GRX_N12

Y36

PCIE_MTX_GRX_N13

AA40

PCIE_MTX_GRX_N14

AB36

PCIE_MTX_GRX_N15

AC40

PCIE_MTX_GRX_P0

D36

PCIE_MTX_GRX_P1

F40

PCIE_MTX_GRX_P2

G36

PCIE_MTX_GRX_P3

H40

PCIE_MTX_GRX_P4

J36

PCIE_MTX_GRX_P5

L40

PCIE_MTX_GRX_P6

M36

PCIE_MTX_GRX_P7

N40

PCIE_MTX_GRX_P8

P36

PCIE_MTX_GRX_P9

R40

PCIE_MTX_GRX_P10

T36

PCIE_MTX_GRX_P11

V40

PCIE_MTX_GRX_P12

W36

PCIE_MTX_GRX_P13

Y40

PCIE_MTX_GRX_P14

AA36

PCIE_MTX_GRX_P15

AB40

PEGCOMP

24.9_0402_1%

1 2

C404 0.1U_0402_10V7KPM@

1 2

C408 0.1U_0402_10V7KPM@

1 2

C411 0.1U_0402_10V7KPM@

1 2

C423 0.1U_0402_10V7KPM@

1 2

C465 0.1U_0402_10V7KPM@

1 2

C441 0.1U_0402_10V7KPM@

1 2

C440 0.1U_0402_10V7KPM@

1 2

C448 0.1U_0402_10V7KPM@

1 2

C407 0.1U_0402_10V7KPM@

1 2

C406 0.1U_0402_10V7KPM@

1 2

C405 0.1U_0402_10V7KPM@

1 2

C419 0.1U_0402_10V7KPM@

1 2

C426 0.1U_0402_10V7KPM@

1 2

C429 0.1U_0402_10V7KPM@

1 2

C437 0.1U_0402_10V7KPM@

1 2

C464 0.1U_0402_10V7KPM@

1 2

2

+1.5VS_PCIE

PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]

PCIE_GTX_C_MRX_N[0..15]
PCIE_GTX_C_MRX_P[0..15]

C175 0.1U_0402_10V7KPM@

1 2

C144 0.1U_0402_10V7KPM@

1 2

C142 0.1U_0402_10V7KPM@

1 2

C149 0.1U_0402_10V7KPM@

1 2

C172 0.1U_0402_10V7KPM@

1 2

C162 0.1U_0402_10V7KPM@

1 2

C166 0.1U_0402_10V7KPM@

1 2

C177 0.1U_0402_10V7KPM@

1 2

C133 0.1U_0402_10V7KPM@

1 2

C129 0.1U_0402_10V7KPM@

1 2

C178 0.1U_0402_10V7KPM@

1 2

C167 0.1U_0402_10V7KPM@

1 2

C161 0.1U_0402_10V7KPM@

1 2

C155 0.1U_0402_10V7KPM@

1 2

C173 0.1U_0402_10V7KPM@

1 2

C170 0.1U_0402_10V7KPM@

1 2

1

PCIE_MTX_C_GRX_N[0..15] <16>
PCIE_MTX_C_GRX_P[0..15] <16>

PCIE_GTX_C_MRX_N[0..15] <16>

PCIE_GTX_C_MRX_P[0..15] <16>

PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_N15

PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_P15

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/08/18 2007/8/18

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Re v

B

2

Date: Sheet

Compal Electronics, Inc.

Crestline ( 3/7)- DDRII

LA-3691P

0.1

of

946Friday, May 18, 2007

1

5

+VCCP

D21

@

RB751V-40TE17_SOD323-2

1 2
12

+2.5VS

R531

10_0402_5%@

D D

+1.5VS

D19

@

RB751V-40TE17_SOD323-2

1 2
12

+3VS

R530

10_0402_5%@

C C

B B

A A

C165

1

C168

C121

2

4.7U_0805_10V4Z

1

2

1

0.22U_0603_10V7K

2

C604

2.2U_0805_16V4Z

C163

220U_B2_2.5VM_R35

1

2

1

2

0.22U_0603_10V7K

+1.5VS

1

+

2

MCH_A6

C602

MCH_D2

C600

+VCCP

0.47U_0603_10V7K

MCH_AB1

1

2

0.47U_0603_10V7K

U20H

AC14

VTT0

AB14

VTT1

W14

VTT2

V14

VTT3

T14

VTT4

R14

VTT5

P14

VTT6

N14

VTT7

M14

VTT8

L14

VTT9

AD13

VTT10

AC13

VTT11

AB13

VTT12

AA13

VTT13

Y13

VTT14

W13

VTT15

V13

VTT16

U13

VTT17

T13

VTT18

R13

VTT19

N13

VTT20

M13

VTT21

L13

VTT22

AB12

VTT23

AA12

VTT24

Y12

VTT25

W12

VTT26

V12

VTT27

U12

VTT28

T12

VTT29

R12

VTT30

P12

VTT31

N12

VTT32

M12

VTT33

L12

VTT34

R11

VTT35

P11

VTT36

N11

VTT37

M11

VTT38

R10

VTT39

P10

VTT40

N10

VTT41

M10

VTT42

P9

VTT43

N9

VTT44

M9

VTT45

R8

VTT46

P8

VTT47

N8

VTT48

M8

VTT49

P7

VTT50

N7

VTT51

M7

VTT52

R6

VTT53

P6

VTT54

M6

VTT55

A6

VTT56

R5

VTT57

P5

VTT58

N5

VTT59

M5

VTT60

P4

VTT61

N4

VTT62

M4

VTT63

R3

VTT64

P3

VTT65

N3

VTT66

M3

VTT67

R2

VTT68

P2

VTT69

M2

VTT70

D2

VTT71

AB1

VTT72

R1

VTT73

P1

VTT74

N1

VTT75

M1

VTT76

AG14

VCCAUX32

AF14

VCCAUX33

AE14

VCCAUX34

Y14

VCCAUX35

AF13

VCCAUX36

AE13

VCCAUX37

AF12

VCCAUX38

AE12

VCCAUX39

AD12

VCCAUX40

CALISTOGA_FCBGA1466~D

GM@

P O W E R

4

VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC2

VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1

VCCD_HMPLL0
VCCD_HMPLL1

VCCDQ_TVDAC

VCC_SYNC

VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2

VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6

VCCA_3GPLL

VCCA_3GBG
VSSA_3GBG

VCCA_DPLLA
VCCA_DPLLB

VCCA_HPLL

VCCA_LVDS
VSSA_LVDS

VCCA_MPLL
VCCA_TVBG

VSSA_TVBG

VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2

VCCD_TVDAC

VCCHV0
VCCHV1
VCCHV2

VCCAUX0
VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8

VCCAUX9
VCCAUX10
VCCAUX11
VCCAUX12
VCCAUX13
VCCAUX14
VCCAUX15
VCCAUX16
VCCAUX17
VCCAUX18
VCCAUX19
VCCAUX20
VCCAUX21
VCCAUX22
VCCAUX23
VCCAUX24
VCCAUX25
VCCAUX26
VCCAUX27
VCCAUX28
VCCAUX29
VCCAUX30
VCCAUX31

H22

B30
C30
A30

AB41
AJ41
L41
N41
R41
V41
Y41

AC33
G41
H41

E21
F21
G21

B26
C39
AF1

A38
B39

AF2
H20

G20

E19
F19
C20
D20
E20
F20

AH1
AH2

A28
B28
C28

D21
H19

A23
B23
B25

AK31
AF31
AE31
AC31
AL30
AK30
AJ30
AH30
AG30
AF30
AE30
AD30
AC30
AG29
AF29
AE29
AD29
AC29
AG28
AF28
AE28
AH22
AJ21
AH21
AJ20
AH20
AH19
P19
P16
AH15
P15
AH14

+2.5VS

1 2

C396

0.1U_0402_16V4Z

+2.5VS

W=40 mils

C438

+1.5VS_3GPLL
+2.5VS

+2.5VS_CRTDAC

+1.5VS_DPLLA
+1.5VS_DPLLB
+1.5VS_HPLL

+2.5VS

+1.5VS_MPLL
+3VS_TVBG

+3VS_TVDACA
+3VS_TVDACA
+3VS_TVDACA

+1.5VS

+1.5VS_TVDAC

1

2

C394

0.1U_0402_16V4Z

+1.5VS

1

C422

2

C424

0.1U_0402_16V4Z

1

2

1

2

10U_1206_6.3V6M

+1.5VS_PCIE

+

220U_B2_2.5VM_R35

1

2

C442

+3VS

3

R86

0_0805_5%

12

+1.5VS

1

1

C134

C605

2

2

10U_1206_6.3V6M

1

C432

2

0.022U_0402_16V7K

10U_1206_6.3V6M

R878

10_0603_5%

1

2

0.1U_0402_16V4Z
C619

CRTDAC: Route caps within
250mil of Alviso. Route FB

10U_0805_6.3V6M

within 3" o f Calistoga

1

C397

2

0.01U_0402_16V7K

12

+2.5VS

+2.5VS

C126

1

2

0.1U_0402_16V4Z

+2.5VS

1

C430

2

0.1U_0402_16V4Z

close pin G41

close pin A38

+3VS+3VS_TVBG

R529

12

10_0805_1%

1

1

C608

2

2

0.1U_0402_16V4Z

C607

0.022U_0402_16V7K

2

+1.5VS_DPLLA +1.5VS_DPLLB

0.1U_0402_16V4Z

1

2

L42

1 2

FBM-L10-160808-301-T_0603

330U_D2E_2.5VM

GM@

1

C124

C417

+

2

1

C425

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

C153

2

2

C400

0.1U_0402_16V4Z

0.022U_0402_16V7K

1

1 2

FBM-L10-160808-301-T_0603

330U_D2E_2.5VM

GM@

1

C145

C431

1

+

2

2

1

1

2

2

C606

0.022U_0402_16V7K

L43

C140

0_0603_5%

0.1U_0402_16V4Z

R528

+1.5VS+1.5VS

+3VS+3VS_TVDACA+3VS_TVDACA+3VS_TVDACA

12

PCI-E/MEM/PSB PLL decoupling

+1.5VS+1.5VS_3GPLL

R87
0_0603_5%

12

1

2

R85
0_0603_5%

10U_1206_6.3V6M

C410

0.1U_0402_16V4Z

@

12

1

1

C130

C603

2

2

0.1U_0402_16V4Z

10U_1206_6.3V6M

+1.5VS_MPLL

45mA Max. 45mA Max.

1

C154

C157

2

0.1U_0402_16V4Z

+1.5VS_TVDAC +1.5VS

1

2

C143

1

2

0.1U_0402_16V4Z

+1.5VS_HPLL

C601

1

2

1

2

R527
0_0603_5%

C148

0.022U_0402_16V7K

0.1U_0402_16V4Z

C427

R17
0_0603_5%

1

2

10U_1206_6.3V6M

12

1

C402

2

0.1U_0402_16V4Z

@

12

+1.5VS+1.5VS

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/08/18 2007/8/18

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Crestline (4/7)-VGA/LVDS/TV

LA-3691P

10 46Friday, May 18, 2007

1

0.1

of

5

[e-mail]

4

3

2

1

Strap Pin Table

CFG[3:17] have internal pull up

+VCCP

D D

1

1

C159

2

0.22U_0603_10V7K

1

C136

2

10U_1206_6.3V6M

C C

C150

B B

C115

C114

0.22U_0603_10V7K

10U_1206_6.3V6M

220U_B2_2.5VM_R35

1

C127

2

2

0.22U_0603_10V7K

1

1

C119

2

2

1U_0603_10V4Z

1

+

2

+VCCP

U20F

AD27

VCC_NCTF0

AC27

VCC_NCTF1

AB27

VCC_NCTF2

AA27

VCC_NCTF3

Y27

VCC_NCTF4

W27

VCC_NCTF5

V27

VCC_NCTF6

U27

VCC_NCTF7

T27

VCC_NCTF8

R27

VCC_NCTF9

AD26

VCC_NCTF10

AC26

VCC_NCTF11

AB26

VCC_NCTF12

AA26

VCC_NCTF13

Y26

VCC_NCTF14

W26

VCC_NCTF15

V26

VCC_NCTF16

U26

VCC_NCTF17

T26

VCC_NCTF18

R26

VCC_NCTF19

AD25

VCC_NCTF20

AC25

VCC_NCTF21

AB25

VCC_NCTF22

AA25

VCC_NCTF23

Y25

VCC_NCTF24

W25

VCC_NCTF25

V25

VCC_NCTF26

U25

VCC_NCTF27

T25

VCC_NCTF28

R25

VCC_NCTF29

AD24

VCC_NCTF30

AC24

VCC_NCTF31

AB24

VCC_NCTF32

AA24

VCC_NCTF33

Y24

VCC_NCTF34

W24

VCC_NCTF35

V24

VCC_NCTF36

U24

VCC_NCTF37

T24

VCC_NCTF38

R24

VCC_NCTF39

AD23

VCC_NCTF40

V23

VCC_NCTF41

U23

VCC_NCTF42

T23

VCC_NCTF43

R23

VCC_NCTF44

AD22

VCC_NCTF45

V22

VCC_NCTF46

U22

VCC_NCTF47

T22

VCC_NCTF48

R22

VCC_NCTF49

AD21

VCC_NCTF50

V21

VCC_NCTF51

U21

VCC_NCTF52

T21

VCC_NCTF53

R21

VCC_NCTF54

AD20

VCC_NCTF55

V20

VCC_NCTF56

U20

VCC_NCTF57

T20

VCC_NCTF58

R20

VCC_NCTF59

AD19

VCC_NCTF60

V19

VCC_NCTF61

U19

VCC_NCTF62

T19

VCC_NCTF63

AD18

VCC_NCTF64

AC18

VCC_NCTF65

AB18

VCC_NCTF66

AA18

VCC_NCTF67

Y18

VCC_NCTF68

W18

VCC_NCTF69

V18

VCC_NCTF70

U18

VCC_NCTF71

T18

VCC_NCTF72

M19

VCC100

L19

VCC101

N18

VCC102

M18

VCC103

L18

VCC104

P17

VCC105

N17

VCC106

M17

VCC107

N16

VCC108

M16

VCC109

L16

VCC110

CALISTOGA_FCBGA1466~D

GM@

VCCAUX_NCTF0
VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8

VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36

P O W E R

VCCAUX_NCTF37
VCCAUX_NCTF38
VCCAUX_NCTF39
VCCAUX_NCTF40
VCCAUX_NCTF41
VCCAUX_NCTF42
VCCAUX_NCTF43
VCCAUX_NCTF44
VCCAUX_NCTF45
VCCAUX_NCTF46
VCCAUX_NCTF47
VCCAUX_NCTF48
VCCAUX_NCTF49
VCCAUX_NCTF50
VCCAUX_NCTF51
VCCAUX_NCTF52
VCCAUX_NCTF53
VCCAUX_NCTF54
VCCAUX_NCTF55
VCCAUX_NCTF56
VCCAUX_NCTF57

VSS_NCTF0
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8

VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12

VCC_SM100

VCC_SM101

VCC_SM102

VCC_SM103

VCC_SM104

VCC_SM105

VCC_SM106

VCC_SM107

AG27
AF27
AG26
AF26
AG25
AF25
AG24
AF24
AG23
AF23
AG22
AF22
AG21
AF21
AG20
AF20
AG19
AF19
R19
AG18
AF18
R18
AG17
AF17
AE17
AD17
AB17
AA17
W17
V17
T17
R17
AG16
AF16
AE16
AD16
AC16
AB16
AA16
Y16
W16
V16
U16
T16
R16
AG15
AF15
AE15
AD15
AC15
AB15
AA15
Y15
W15
V15
U15
T15
R15

AE27
AE26
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AC17
Y17
U17

AR6
AP6
AN6
AL6
AK6
AJ6
AV1
AJ1

+1.5VS

C147

+1.8V

0.47U_0603_10V7K

1

1

C164

2

2

0.47U_0603_10V7K

Place near pin AV1 & AJ1

A A

+VCCP

AA33

AA32

AA31

AA30

AA29

AB28
AA28

AB23
AA23

AC22
AB22

AC21
AA21

AC20
AB20

AB19
AA19

U20G

VCC0

W33

VCC1

P33

VCC2

N33

VCC3

L33

VCC4

J33

VCC5
VCC6

Y32

VCC7

W32

VCC8

V32

VCC9

P32

VCC10

N32

VCC11

M32

VCC12

L32

VCC13

J32

VCC14
VCC15

W31

VCC16

V31

VCC17

T31

VCC18

R31

VCC19

P31

VCC20

N31

VCC21

M31

VCC22
VCC23

Y30

VCC24

W30

VCC25

V30

VCC26

U30

VCC27

T30

VCC28

R30

VCC29

P30

VCC30

N30

VCC31

M30

VCC32

P O W E R

VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99

CALISTOGA_FCBGA1466~D

GM@

W29

M29

M28

M27

M25

M24

M23

W22

M22

W21
M21

W20

M20

L30
Y29
V29

U29
R29
P29

L29

Y28
V28
U28
T28
R28
P28
N28

L28
P27
N27

L27
P26
N26
L26
N25

L25
P24
N24

Y23
P23
N23

L23

Y22
P22

N22
L22

N21
L21

Y20
P20

N20
L20

Y19
N19

VCC_SM0
VCC_SM1
VCC_SM2
VCC_SM3
VCC_SM4
VCC_SM5
VCC_SM6
VCC_SM7
VCC_SM8

VCC_SM9
VCC_SM10
VCC_SM11
VCC_SM12
VCC_SM13
VCC_SM14
VCC_SM15
VCC_SM16
VCC_SM17
VCC_SM18
VCC_SM19
VCC_SM20
VCC_SM21
VCC_SM22
VCC_SM23
VCC_SM24
VCC_SM25
VCC_SM26
VCC_SM27
VCC_SM28
VCC_SM29
VCC_SM30
VCC_SM31
VCC_SM32
VCC_SM33
VCC_SM34
VCC_SM35
VCC_SM36
VCC_SM37
VCC_SM38
VCC_SM39
VCC_SM40
VCC_SM41
VCC_SM42
VCC_SM43
VCC_SM44
VCC_SM45
VCC_SM46
VCC_SM47
VCC_SM48
VCC_SM49
VCC_SM50
VCC_SM51
VCC_SM52
VCC_SM53
VCC_SM54
VCC_SM55
VCC_SM56
VCC_SM57
VCC_SM58
VCC_SM59
VCC_SM60
VCC_SM61
VCC_SM62
VCC_SM63
VCC_SM64
VCC_SM65
VCC_SM66
VCC_SM67
VCC_SM68
VCC_SM69
VCC_SM70
VCC_SM71
VCC_SM72
VCC_SM73
VCC_SM74
VCC_SM75
VCC_SM76
VCC_SM77
VCC_SM78
VCC_SM79
VCC_SM80
VCC_SM81
VCC_SM82
VCC_SM83
VCC_SM84
VCC_SM85
VCC_SM86
VCC_SM87
VCC_SM88
VCC_SM89
VCC_SM90
VCC_SM91
VCC_SM92
VCC_SM93
VCC_SM94
VCC_SM95
VCC_SM96
VCC_SM97
VCC_SM98
VCC_SM99

AU41
AT41
AM41
AU40
BA34
AY34
AW34
AV34
AU34
AT34
AR34
BA30
AY30
AW30
AV30
AU30
AT30
AR30
AP30
AN30
AM30
AM29
AL29
AK29
AJ29
AH29
AJ28
AH28
AJ27
AH27
BA26
AY26
AW26
AV26
AU26
AT26
AR26
AJ26
AH26
AJ25
AH25
AJ24
AH24
BA23
AJ23
BA22
AY22
AW22
AV22
AU22
AT22
AR22
AP22
AK22
AJ22
AK21
AK20
BA19
AY19
AW19
AV19
AU19
AT19
AR19
AP19
AK19
AJ19
AJ18
AJ17
AH17
AJ16
AH16
BA15
AY15
AW15
AV15
AU15
AT15
AR15
AJ15
AJ14
AJ13
AH13
AK12
AJ12
AH12
AG12
AK11
BA8
AY8
AW8
AV8
AT8
AR8
AP8
BA6
AY6
AW6
AV6
AT6

+1.8V

MCH_AT41
MCH_AM41

1

1

C139

C158

2

2

0.47U_0603_10V7K

0.47U_0603_10V7K

Place near pin AT41 & AM41

1

1

C138

C118

2

2

0.1U_0402_16V4Z

1

C141

2

0.47U_0603_10V7K

Place near pin BA23

1

1

C122

C137

C128

2

2

10U_1206_6.3V6M

10U_1206_6.3V6M

1

2

0.47U_0603_10V7K

Place near pin BA15

CFG[2:0]

CFG5

CFG7

CFG9

CFG6

PSB 4X CLK Enable 1 = Calistoga

CFG[13:12]

CFG16

0.1U_0402_16V4Z

CFG10 CFG18

CFG19

SDVO_CTRLDATA

1

1

C112

C146

2

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

CFG20

(PCIE/SDVO select)

CFG[19:18] have internal pull down

011 = 667MT/s FSB
001 = 533MT/s FSB

0 = DMI x 2
1 = DMI x 4

0 = Reserved
1 = Mobile Yonah CPU

0 = Lane Reversal Enable
1 = Normal Operation

(Default)

*

(Default)

*

(Default)

0 = Reserved

*

00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation

0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled (Default)

10 = 1.05V
01 = 1.5V

0 = Normal Operation
1 = DMI Lane Reversal Enable

0 = No SDVO Device Present

*

(Default)

(Default)

1 = SDVO Device Present

0 = Only PCIE or SDVO is
operational.
1 = PCIE/SDVO are operating
simu.

CFG5<7>
CFG7<7>

CFG9<7>
CFG11<7>
CFG12<7>
CFG13<7>
CFG16<7>

CFG18<7>
CFG19<7>
CFG20<7>

R124 2.2K_0402_5%@
R88 2.2K_0402_5%@
R110 2.2K_0402_5%@
R123 2.2K_0402_5%@
R125 2.2K_0402_5%@
R109 2.2K_0402_5%@
R108 2.2K_0402_5%@

R131 1K_0402_5%@
R130 1K_0402_5%@
R126 1K_0402_5%@

*

1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2

*

*

(Default)

*

(Default)

*

(Default)

*

+3VS

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/08/18 2007/8/18

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Crestline (5/7)-VCC

LA-3691P

11 46Friday, May 18, 2007

1

0.1

of

5

4

3

2

1

U20I

AC41

VSS0

AA41

VSS1

W41

VSS2

T41

VSS3

P41

VSS4

M41

VSS5

J41

VSS6

F41

VSS7

AV40

VSS8

AP40

VSS9

D D

C C

B B

A A

5

AN40

VSS10

AK40

VSS11

AJ40

VSS12

AH40

VSS13

AG40

VSS14

AF40

VSS15

AE40

VSS16

B40

VSS17

AY39

VSS18

AW39

VSS19

AV39

VSS20

AR39

VSS21

AN39

VSS22

AJ39

VSS23

AC39

VSS24

AB39

VSS25

AA39

VSS26

Y39

VSS27

W39

VSS28

V39

VSS29

T39

VSS30

R39

VSS31

P39

VSS32

N39

VSS33

M39

VSS34

L39

VSS35

J39

VSS36

H39

VSS37

G39

VSS38

F39

VSS39

D39

VSS40

AT38

VSS41

AM38

VSS42

AH38

VSS43

AG38

VSS44

AF38

VSS45

AE38

VSS46

C38

VSS47

AK37

VSS48

AH37

VSS49

AB37

VSS50

AA37

VSS51

Y37

VSS52

W37

VSS53

V37

VSS54

T37

VSS55

R37

VSS56

P37

VSS57

N37

VSS58

M37

VSS59

L37

VSS60

J37

VSS61

H37

VSS62

G37

VSS63

F37

VSS64

D37

VSS65

AY36

VSS66

AW36

VSS67

AN36

VSS68

AH36

VSS69

AG36

VSS70

AF36

VSS71

AE36

VSS72

AC36

VSS73

C36

VSS74

B36

VSS75

BA35

VSS76

AV35

VSS77

AR35

VSS78

AH35

VSS79

AB35

VSS80

AA35

VSS81

Y35

VSS82

W35

VSS83

V35

VSS84

T35

VSS85

R35

VSS86

P35

VSS87

N35

VSS88

M35

VSS89

L35

VSS90

J35

VSS91

H35

VSS92

G35

VSS93

F35

VSS94

D35

VSS95

AN34

VSS96

AK34

VSS97

AG34

VSS98

AF34

VSS99

CALISTOGA_FCBGA1466~D

GM@

P O W E R

4

VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199

AE34
AC34
C34
AW33
AV33
AR33
AE33
AB33
Y33
V33
T33
R33
M33
H33
G33
F33
D33
B33
AH32
AG32
AF32
AE32
AC32
AB32
G32
B32
AY31
AV31
AN31
AJ31
AG31
AB31
Y31
AB30
E30
AT29
AN29
AB29
T29
N29
K29
G29
E29
C29
B29
A29
BA28
AW28
AU28
AP28
AM28
AD28
AC28
W28
J28
E28
AP27
AM27
AK27
J27
G27
F27
C27
B27
AN26
M26
K26
F26
D26
AK25
P25
K25
H25
E25
D25
A25
BA24
AU24
AL24
AW23
AT23
AN23
AM23
AH23
AC23
W23
K23
J23
F23
C23
AA22
K22
G22
F22
E22
D22
A22
BA21
AV21
AR21

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/08/18 2007/8/18

3

U20J

AN21

VSS200

AL21

VSS201

AB21

VSS202

Y21

VSS203

P21

VSS204

K21

VSS205

J21

VSS206

H21

VSS207

C21

VSS208

AW20

VSS209

AR20

VSS210

AM20

VSS211

AA20

VSS212

K20

VSS213

B20

VSS214

A20

VSS215

AN19

VSS216

AC19

VSS217

W19

VSS218

K19

VSS219

G19

VSS220

C19

VSS221

AH18

VSS222

P18

VSS223

H18

VSS224

D18

VSS225

A18

VSS226

AY17

VSS227

AR17

VSS228

AP17

VSS229

AM17

VSS230

AK17

VSS231

AV16

VSS232

AN16

VSS233

AL16

VSS234

J16

VSS235

F16

VSS236

C16

VSS237

AN15

VSS238

AM15

VSS239

AK15

VSS240

N15

VSS241

M15

VSS242

L15

VSS243

B15

VSS244

A15

VSS245

BA14

VSS246

AT14

VSS247

AK14

VSS248

AD14

VSS249

AA14

VSS250

U14

VSS251

K14

VSS252

H14

VSS253

E14

VSS254

AV13

VSS255

AR13

VSS256

AN13

VSS257

AM13

VSS258

AL13

VSS259

AG13

VSS260

P13

VSS261

F13

VSS262

D13

VSS265

B13

VSS264

AY12

VSS263

AC12

VSS266

K12

VSS267

H12

VSS268

E12

VSS269

AD11

VSS270

AA11

VSS271

Y11

VSS272

J11

VSS273

D11

VSS274

B11

VSS275

AV10

VSS276

AP10

VSS277

AL10

VSS278

AJ10

VSS279

CALISTOGA_FCBGA1466~D

GM@

Compal Secret Data

P O W E R

Deciphered Date

VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS287
VSS288
VSS289
VSS290
VSS292
VSS291
VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299
VSS300
VSS301
VSS302
VSS303
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS314
VSS315
VSS316
VSS317
VSS318
VSS319
VSS320
VSS321
VSS322
VSS323
VSS324
VSS325
VSS326
VSS327
VSS328
VSS329
VSS330
VSS331
VSS332
VSS333
VSS334
VSS335
VSS336
VSS337
VSS338
VSS339
VSS340
VSS341
VSS342
VSS343
VSS344
VSS345
VSS346
VSS347
VSS348
VSS349
VSS350
VSS351
VSS352
VSS353
VSS354
VSS355
VSS356
VSS357
VSS358
VSS359
VSS360

AG10
AC10
W10
U10
BA9
AW9
AR9
AH9
AB9
Y9
R9
G9
E9
A9
AG8
AD8
AA8
U8
K8
C8
BA7
AV7
AP7
AL7
AJ7
AH7
AF7
AC7
R7
G7
D7
AG6
AD6
AB6
Y6
U6
N6
K6
H6
B6
AV5
AF5
AD5
AY4
AR4
AP4
AL4
AJ4
Y4
U4
R4
J4
F4
C4
AY3
AW3
AV3
AL3
AH3
AG3
AF3
AD3
AC3
AA3
G3
AT2
AR2
AP2
AK2
AJ2
AD2
AB2
Y2
U2
T2
N2
J2
H2
F2
C2
AL1

2

Title

Size Document Number Re v

B

Date: Sheet

Compal Electronics, Inc.

Crestline (6/7)-VCC

LA-3691P

12 46Friday, May 18, 2007

1

of

0.1

5

[e-mail]

4

3

2

1

+1.8V +1.8V

JP25

+DIMM_VREF

DDRA_SDQ0
DDRA_SDQ1

1

C228

0.1U_0402_16V4Z

2

DDRA_SDQS0#
DDRA_SDQS0

DDRA_SDQ2
DDRA_SDQ3

DDRA_SDQ9
DDRA_SDQ8

DDRA_SDQS1#
DDRA_SDQS1

DDRA_SDQ10
DDRA_SDQ11

DDRA_SDQ16
DDRA_SDQ17

DDRA_SDQS2#
DDRA_SDQS2

DDRA_SDQ18
DDRA_SDQ19

DDRA_SDQ24
DDRA_SDQ25

DDRA_SDM3

EC_TX_P80_DATA

DDRA_SDQ26
DDRA_SDQ27

DDRA_CKE0

EC_RX_P80_CLK

DDRA_SBS2
DDRA_SMA12

DDRA_SMA9
DDRA_SMA8

DDRA_SMA5
DDRA_SMA3
DDRA_SMA1

DDRA_SMA10
DDRA_SBS0
DDRA_SWE#

DDRA_SCAS#
DDRA_SCS1#

DDRA_ODT1
DDRA_SDQ32

DDRA_SDQ33
DDRA_SDQS4#

DDRA_SDQS4
DDRA_SDQ34

DDRA_SDQ35
DDRA_SDQ40

DDRA_SDQ41
DDRA_SDM5
DDRA_SDQ42

DDRA_SDQ43
DDRA_SDQ48

DDRA_SDQ49

EC_RX_P80_CLK_R

DDRA_SDQS6#
DDRA_SDQS6

DDRA_SDQ50
DDRA_SDQ51

DDRA_SDQ56
DDRA_SDQ57

DDRA_SDM7
DDRA_SDQ58

DDRA_SDQ59
D_CK_SDATA

D_CK_SCLK

+3VS

1

2

DIMM0 STD H:5.2mm (BOT)

DDRA_SDQS0#<8>
DDRA_SDQS0<8>

D D

DDRA_SDQS1#<8>
DDRA_SDQS1<8>

DDRA_SDQS2#<8>
DDRA_SDQS2<8>

EC_TX_P80_DATA<14,31,33>

C C

B B

EC_RX_P80_CLK

A A

DDRA_CKE0<7>

EC_RX_P80_CLK<14,31,33>

DDRA_SBS2<8>

DDRA_SBS0<8>
DDRA_SWE#<8>

DDRA_SCAS#<8>
DDRA_SCS1#<7>

DDRA_ODT1<7>

DDRA_SDQS4#<8>
DDRA_SDQS4<8>

R201 0_0402_5%

1 2

EC_RX_P80_CLK_R<14>

DDRA_SDQS6#<8>
DDRA_SDQS6<8>

D_CK_SDATA<14,15,23>
D_CK_SCLK<14,15,23>

@

+3VS

C234

2.2U_0805_10V6K

5

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

TYCO_292526-4

ME@

Change PCB F ootprint

DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0

CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

VDD

VDD

RAS#

VDD
ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1

CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

VSS

A11

BA1
S0#

SA0
SA1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106
108
110
112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

4

9/25 Change DIMM0 to SP070004Z00 (HBL50)

DDRA_SDQ4
DDRA_SDQ5

DDRA_SDM0
DDRA_SDQ6

DDRA_SDQ7
DDRA_SDQ12

DDRA_SDQ13
DDRA_SDM1

DDRA_SDQ14
DDRA_SDQ15

DDRA_SDQ20
DDRA_SDQ21

DDRA_SDM2
DDRA_SDQ22

DDRA_SDQ23
DDRA_SDQ28

DDRA_SDQ29
DDRA_SDQS3#

DDRA_SDQS3
DDRA_SDQ30

DDRA_SDQ31
DDRA_CKE1

DDRA_SMA11
DDRA_SMA7
DDRA_SMA6

DDRA_SMA4
DDRA_SMA2
DDRA_SMA0

DDRA_SBS1
DDRA_SRAS#
DDRA_SCS0#

DDRA_ODT0
DDRA_SMA13

DDRA_SDQ36
DDRA_SDQ37

DDRA_SDM4
DDRA_SDQ38

DDRA_SDQ39
DDRA_SDQ44

DDRA_SDQ45
DDRA_SDQS5#

DDRA_SDQS5
DDRA_SDQ46

DDRA_SDQ47
DDRA_SDQ52

DDRA_SDQ53

DDRA_SDM6
DDRA_SDQ54

DDRA_SDQ55
DDRA_SDQ60

DDRA_SDQ61
DDRA_SDQS7#

DDRA_SDQS7
DDRA_SDQ62

DDRA_SDQ63

R204 10K_0402_5%

1 2

R205 10K_0402_5%

1 2

DDRA_CLK0 <7>
DDRA_CLK0# <7>

R207 0_0402_5%

1 2

DDRA_SDQS3# <8>
DDRA_SDQS3 <8>

DDRA_CKE1 <7>

DDRA_SBS1 <8>
DDRA_SRAS# <8>
DDRA_SCS0# <7>

DDRA_ODT0 <7>

DDRA_SDQS5# <8>
DDRA_SDQS5 <8>

DDRA_CLK1 <7>
DDRA_CLK1# <7>

DDRA_SDQS7# <8>
DDRA_SDQS7 <8>

PM_EXTTS#0 <7,14>

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+DIMM_VREF

20mils

1

C224

0.1U_0402_16V4Z

2

DDRA_SMA[0..13]<8>
DDRA_SDQ[0..63]<8>

DDRA_SDM[0..7]<8>

DDRA_CKE0
DDRA_SBS2

DDRA_SMA12
DDRA_SMA9

DDRA_SMA8
DDRA_SMA5

DDRA_SMA3
DDRA_SMA1

DDRA_SMA10
DDRA_SBS0

DDRA_SWE#
DDRA_SCAS#

DDRA_SCS1#
DDRA_ODT1

DDRA_SMA11
DDRA_CKE1

DDRA_SMA6
DDRA_SMA7

DDRA_SMA2
DDRA_SMA4

DDRA_SBS1
DDRA_SMA0

DDRA_SCS0#
DDRA_SRAS#

DDRA_SMA13
DDRA_ODT0

Layout Note:
Place these resistor
closely JP35,all
trace length Max=1.5"

2006/08/18 2007/8/18

3

1K_0402_1%

1

C225

2.2U_0805_10V6K

2

1 4
2 3

RP14 56_0404_4P2R_5%

1 4
2 3

RP15 56_0404_4P2R_5%

1 4
2 3

RP16 56_0404_4P2R_5%

1 4
2 3

RP17 56_0404_4P2R_5%

1 4
2 3

RP18 56_0404_4P2R_5%

1 4
2 3

RP19 56_0404_4P2R_5%

1 4
2 3

RP20 56_0404_4P2R_5%

1 4
2 3

RP21 56_0404_4P2R_5%

1 4
2 3

RP22 56_0404_4P2R_5%

1 4
2 3

RP23 56_0404_4P2R_5%

1 4
2 3

RP24 56_0404_4P2R_5%

1 4
2 3

RP25 56_0404_4P2R_5%

1 4
2 3

RP26 56_0404_4P2R_5%

1K_0402_1%

DDRA_SMA[0..13]
DDRA_SDQ[0..63]
DDRA_SDM[0..7]

Compal Secret Data

Deciphered Date

+0.9VS

R195

R198

+1.8V

12

12

2

Layout Note:
Place near JP35

+DIMM_VREF

1

C245

2.2U_0805_10V6K

2

1

C244

0.1U_0402_16V4Z

2

1

C236

0.1U_0402_16V4Z

2

1

C241

0.1U_0402_16V4Z

2

1

C254

0.1U_0402_16V4Z

2

Title

Size Document Number Rev

B

Date: Sheet

1

C221
220P_0402_50V7K

2

@

+1.8V

1

C232

2.2U_0805_10V6K

2

+1.8V

1

C243

0.1U_0402_16V4Z

2

+0.9VS

1

C235

0.1U_0402_16V4Z

2

+0.9VS

1

C240

0.1U_0402_16V4Z

2

+0.9VS

1

C253

0.1U_0402_16V4Z

2

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS

1

C233

2.2U_0805_10V6K

2

1

C230

0.1U_0402_16V4Z

2

1

C237

0.1U_0402_16V4Z

2

1

C250

0.1U_0402_16V4Z

2

1

C255

0.1U_0402_16V4Z

2

1

C242

2.2U_0805_10V6K

2

1

C231

0.1U_0402_16V4Z

2

1

C238

0.1U_0402_16V4Z

2

1

C251

0.1U_0402_16V4Z

2

Compal Electronics, Inc.

DDRII-SODIMM0

LA-3691P

1

1

C246

2.2U_0805_10V6K

2

1

C614

2

220U_B2_2.5VM_R35

1

C239

0.1U_0402_16V4Z

2

1

C252

0.1U_0402_16V4Z

2

13 46Friday, May 18, 2007

+

@

0.1

of

A

B

C

D

E

9/25 Change DIMM1 to SP070006F00

JP23

+DIMM_VREF

DDRB_SDQ5
DDRB_SDQ4

1 1

2 2

3 3

4 4

EC_TX_P80_DATA<13,31,33>

EC_RX_P80_CLK<13,31,33>

EC_RX_P80_CLK_R<13>

DDRB_SDQS0#<8>
DDRB_SDQS0<8>

DDRB_SDQS1#<8>
DDRB_SDQS1<8>

DDRB_SDQS2#<8>
DDRB_SDQS2<8>

DDRB_CKE0<7>

DDRB_SBS2<8>

DDRB_SBS0<8>
DDRB_SWE#<8>

DDRB_SCAS#<8>
DDRB_SCS1#<7>

DDRB_ODT1<7>

DDRB_SDQS4#<8>
DDRB_SDQS4<8>

DDRB_SDQS6#<8>
DDRB_SDQS6<8>

D_CK_SDATA<13,15,23>
D_CK_SCLK<13,15,23>

DDRB_SDQS0#
DDRB_SDQS0

DDRB_SDQ2
DDRB_SDQ3

DDRB_SDQ8
DDRB_SDQ9

DDRB_SDQS1#
DDRB_SDQS1

DDRB_SDQ10
DDRB_SDQ11

DDRB_SDQ16
DDRB_SDQ17

DDRB_SDQS2#
DDRB_SDQS2

DDRB_SDQ19
DDRB_SDQ22

DDRB_SDQ24
DDRB_SDQ25

DDRB_SDM3
EC_TX_P80_DATA

DDRB_SDQ26
DDRB_SDQ27

DDRB_CKE0
EC_RX_P80_CLK

DDRB_SBS2
DDRB_SMA12

DDRB_SMA9
DDRB_SMA8

DDRB_SMA5
DDRB_SMA3
DDRB_SMA1

DDRB_SMA10
DDRB_SBS0
DDRB_SWE#

DDRB_SCAS#
DDRB_SCS1#

DDRB_ODT1
DDRB_SDQ32

DDRB_SDQ33
DDRB_SDQS4#

DDRB_SDQS4
DDRB_SDQ34

DDRB_SDQ35
DDRB_SDQ40

DDRB_SDQ41
DDRB_SDM5
DDRB_SDQ42

DDRB_SDQ43
DDRB_SDQ48

DDRB_SDQ49

EC_RX_P80_CLK_R

DDRB_SDQS6#
DDRB_SDQS6

DDRB_SDQ50
DDRB_SDQ54

DDRB_SDQ56
DDRB_SDQ57

DDRB_SDM7
DDRB_SDQ58

DDRB_SDQ59
D_CK_SDATA

D_CK_SCLK

+3VS

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

TYCO_292530-4

ME@

NC/CKE1

NC/A15
NC/A14

NC/A13

DIMM1 STD H:9.2mm (BOT)

A

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0

CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

VDD

VDD

VDD

VDD

BA1
RAS#

VDD
ODT0

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1

CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SAO

SA1

+1.8V+1.8V

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90

A11

92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106
108
110

S0#

112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

B

DDRB_SDQ1
DDRB_SDQ0

DDRB_SDM0
DDRB_SDQ6

DDRB_SDQ7
DDRB_SDQ12

DDRB_SDQ13
DDRB_SDM1

DDRB_SDQ14
DDRB_SDQ15

DDRB_SDQ20
DDRB_SDQ21

DDRB_SDM2
DDRB_SDQ18

DDRB_SDQ23
DDRB_SDQ28

DDRB_SDQ29
DDRB_SDQS3#

DDRB_SDQS3
DDRB_SDQ30

DDRB_SDQ31
DDRB_CKE1

DDRB_SMA11
DDRB_SMA7
DDRB_SMA6

DDRB_SMA4
DDRB_SMA2
DDRB_SMA0

DDRB_SBS1
DDRB_SRAS#
DDRB_SCS0#

DDRB_ODT0
DDRB_SMA13

DDRB_SDQ36
DDRB_SDQ37

DDRB_SDM4
DDRB_SDQ38

DDRB_SDQ39
DDRB_SDQ44

DDRB_SDQ45
DDRB_SDQS5#

DDRB_SDQS5
DDRB_SDQ46

DDRB_SDQ47
DDRB_SDQ52

DDRB_SDQ53

DDRB_SDM6
DDRB_SDQ55

DDRB_SDQ51
DDRB_SDQ60

DDRB_SDQ61
DDRB_SDQS7#

DDRB_SDQS7
DDRB_SDQ62

DDRB_SDQ63

R196 10K_0402_5%

1 2

R197 10K_0402_5%

1 2

R199

0_0402_5%

1 2

DDRB_SMA[0..13]<8>
DDRB_SDQ[0..63]<8>

DDRB_SDM[0..7]<8>

DDRB_CLK1 <7>
DDRB_CLK1# <7>

PM_EXTTS#0 <7,13>

DDRB_SDQS3# <8>
DDRB_SDQS3 <8>

DDRB_CKE1 <7>

DDRB_SBS1 <8>
DDRB_SRAS# <8>
DDRB_SCS0# <7>

DDRB_ODT0 <7>

DDRB_SDQS5# <8>
DDRB_SDQS5 <8>

DDRB_CLK0 <7>
DDRB_CLK0# <7>

DDRB_SDQS7# <8>
DDRB_SDQS7 <8>

+3VS

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/08/18 2007/8/18

DDRB_CKE0
DDRB_SBS2

DDRB_SMA12
DDRB_SMA9

DDRB_SMA8
DDRB_SMA5

DDRB_SMA3
DDRB_SMA1

DDRB_SMA10
DDRB_SBS0

DDRB_SWE#
DDRB_SCAS#

DDRB_SCS1#
DDRB_ODT1

DDRB_SMA11
DDRB_CKE1

DDRB_SMA6
DDRB_SMA7

DDRB_SMA2
DDRB_SMA4

DDRB_SBS1
DDRB_SMA0

DDRB_SCS0#
DDRB_SRAS#

DDRB_SMA13
DDRB_ODT0

Layout Note:
Place these resistor
closely JP35,all
trace length Max=1.5"

Compal Secret Data

Deciphered Date

DDRB_SMA[0..13]
DDRB_SDQ[0..63]
DDRB_SDM[0..7]

1 4
2 3

RP1 56_0404_4P2R_5%

1 4
2 3

RP2 56_0404_4P2R_5%

RP3 56_0404_4P2R_5%

RP4 56_0404_4P2R_5%

RP5 56_0404_4P2R_5%

RP6 56_0404_4P2R_5%

RP7 56_0404_4P2R_5%

RP8 56_0404_4P2R_5%

RP9 56_0404_4P2R_5%

RP10 56_0404_4P2R_5%

RP11 56_0404_4P2R_5%

RP12 56_0404_4P2R_5%

RP13 56_0404_4P2R_5%

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

+0.9VS

D

+DIMM_VREF

1

C199

2.2U_0805_10V6K

2

Layout Note:
Place near JP34

+1.8V

1

C483

C487

2.2U_0805_10V6K

2

2.2U_0805_10V6K

+1.8V

1

C218

C217

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

+0.9VS

1

C193

C192

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

+0.9VS

1

C197

C198

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

+0.9VS

1

C206

C207

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS

Title

Size Document Number Rev

B

Date: Sheet

1

C200

2

0.1U_0402_16V4Z

1

1

2

1

2

1

2

1

2

1

2

C219

2.2U_0805_10V6K

C482

0.1U_0402_16V4Z

C194

0.1U_0402_16V4Z

C203

0.1U_0402_16V4Z

C208

0.1U_0402_16V4Z

C220

2

2.2U_0805_10V6K

1

C479

0.1U_0402_16V4Z

2

1

C195

0.1U_0402_16V4Z

2

1

C204

2

0.1U_0402_16V4Z

1

2

1

2

1

2

1

2

1

2

Compal Electronics, Inc.

DDRII-SODIMM1

LA-3691P

E

1

C216

2.2U_0805_10V6K

2

1

C196

2

0.1U_0402_16V4Z

1

C205

0.1U_0402_16V4Z

2

14 46Friday, May 18, 2007

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