Lenovo EG521, EG522, EZ511, EG721 Schematic

Vinafix.com

A

1 1

B

C

D

E

LCFC Confidential

EG521/EG522 MB Schematics Document

Kabylake-U42 with DDR4

2 2

2017-04-25

REV:0.2

3 3

4 4

Title

Title

Security Cl assification

Security Cl assification

Security Cl assification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENT ER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENT ER.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENT ER.

C

2015/08/20

2015/08/20

2015/08/20

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

2016/08/20

2016/08/20

2016/08/20

Title

Cover Page

Cover Page

Cover Page

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Tuesday, April 25, 2017

Tuesday, April 25, 2017

Tuesday, April 25, 2017

EG521

EG521

EG521

1 60

1 60

E

1 60

0.2

0.2

0.2

Vinafix.com

A

LCFC confidential

B

C

D

E

DDR4 SO-DIMM x1

Page 18

Memory Bus (Dual Channel)

1 1

SATA Port0

HDMI (DDI 1)

eDP x2 Lane

USB2.0 x1

SATA Gen3 x1

Intel MCP

KBL-U22/U23E 15W

BGA-1356

HDMI Conn.

Page 34

eDP Conn

Int. Camera Conn.

USB2.0 Port4

Int. MIC Conn.

2 2

Page 33

SATA HDD

Page 42

42mm*24mm

SATA ODD

SATA Port1A

Page 42

SSD/Optane memory
(Optional)

Page 40

PCIe Port 9~12

SATA Gen1 x1

1.2V DDR4 2133MT/s

USB3.0 x1
USB2.0 x1

USB3.0 x1
USB2.0 x1

USB3.0 x1
USB2.0 x1

USB2.0 x1

USB2.0 x1

PCIe Gen1 x1
USB2.0 x1

PCIe Gen1 x1

USB3.0 Left Conn

USB3.0 Port1
USB2.0 Port1

USB3.0 Left Conn

USB3.0 Port3
USB2.0 Port3

Type-C IC

Realtek RTS5449

Touch Screen (Optional)

USB2.0 Port6

Finger Print (Optional)

USB2.0 Port7

NGFF WLAN&BT

PCIe Port6

USB2.0 Port7

Realtek_RTL8111GUL

PCIe Port5

LAN Chip

DDR4 Memory Down

4pcs x16

Page 41

Page 41

Page 43

Type-C Conn

Page 33

Page 45

Page 40

Page 37

RJ45 Conn.

Page 38

Page 17

Page 43

SD/MMC Conn.

3 3

Page 31

SPK Conn.

Page 30

HP&Mic Combo Conn.

Page 30

Codec & C/R

Realtek RTS5119

USB2.0 Port5

Page 30

USB2.0 x1

HD Audio

Page 3~16

LPC

EC

ITE IT8586E-LQFP

Page 44

SPI

I2C

TPM (Reserved)

Z32H320TC

SPI ROM (8MB)

W25Q64FVSSIQ

Touch Pad

Page 32

Page 07

Page 45

Sub-board( for 15" 17")

Int.KBD Thermal Sensor (Reserved)

Page 45

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

C

NCT7718W

2015/08/20

2015/08/20

2015/08/20

Page 39

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

ODD BOARD

2016/08/20

2016/08/20

2016/08/20

Title

Title

Title

Block Diagram

Block Diagram

Block Diagram

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date : Sheet of

Date : Sheet of

Date : Sheet of

EG521

EG521

EG521

Tuesday, April 25, 2017

Tuesday, April 25, 2017

Tuesday, April 25, 2017

2 60

2 60

2 60

E

0.2

0.2

0.2

Vinafix.com

A

B

C

D

E

Voltage Rails

Power Plane

1 1

State

S0

S3

S3

2 2

Battery only

S5 S4
AC Only

S5 S4
Battery only

S5 S4
AC & Battery
don't exist

SMBUS Control Table

3 3

EC_SMB_DA 1

EC_SMB_CK 2

EC_SMB_DA 2

EC_SMB_CK 3

EC_SMB_DA 3

( O --> Means ON , X --> Means OFF )

+3VALW

+5VALW

V20B+

+3VALW_PCH

+1.8VALW

+1.0VALW

O

O

O

O X

O

O

O

O

O

X X

X X

SOURCE

IT8586EEC_SMB_CK 1

+3VL_EC

IT8586E

IT8586E

+3VL_EC

+3VS

BATT

V

X

ChargerVDGPU

X

X

V

+3VG_AON

IT8586E

+3VL_EC

+3VS

+3VL_EC

+1.2V

+2.5V_DDR

+VCCST

Memory
Down

V

V

V

+5VS

+3VS

+VCCIO

+VCCSTG

+VCCSA

+VCC_GT

+CPU_CORE

+0.6VS

O

O

O

O

X

X

X

X

PCH

X

V

X

PMIC

X

X

X X

+3VALW_PC H

SODIMM

Thermal
Sensor

X

X

X

VX X X X X X X

STATE

Full ON

S3 (Suspen d to RAM)

S4 (Suspen d to Disk)

S5 (Soft OFF)

HSIO PORT

1

2

USB3 .0

USB2 .0

PCIE

WLAN
WiMAX

X

X

SATA

V

X

3

4

5

6

1

2

3

4

5

6

7

8

9

10

1~4

X4 PCIE

5

6

7

8

9~12

X4 PCIE

0

1A

1B

2

SIGNAL

Functio n

USB3.0 Con n Left

USB Typ e-C

USB3.0 Con n Left

NC

NC

NC

USB3.0 Con n Left

USB Typ e-C

USB3.0 Con n Left

Finger Print

Cardreade r

Touch P anel

Bluetooth

Camera

NC

NC

DGPU

LAN

WLAN

SATA HDD

SATA ODD

Optane Memory

HDD

ODD

used as PCIE

used as PCIE

SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

ON

ON

ON

ON

ON ON ON

ON

OFF

OFF

OFF

OFF

OFFLOW LOW LOW

OFF

OFF

OFF

HIGH HIGH HIGH

LOW

HIGH

HIGH

LOWLOW

LOW

BTO ItemBOM Structure

@
14@
15@
14or15@
14or17@

Cannonlake@
CD@
DUALMIC @
EMC@
EMC_15@
EMC_NS@
EMC_PX@
EMC_PXNS@
ES@
EXO@

ME@
NTS@

DIS@
OPT@
PX@
RANK A@
RANK B@
Realtek_SD@
SINGLEMIC@
SINGLERANK@
DUALRANK@
TS@
TPM@
UMA@

Not stuff

For 14" part

For 15" part

For 14" or 15" part

For 14" or 17" part

For Can nonlake part

For C cost down

For Dual MIC part

For EMC part

For EMC 15" part

For EMC nu-stuff part

For EMC PX part

For EMC PX nu-stu ff part

For ES CPU

For EXO GPU

For ME part

For nu-tou ch part

For GPU part

For NV GPU part

For AMD GPU part

For VRAM r ank A part

For VRAM r ank B part

For Realte k SD part

For single MIC part

For single VRAN rank part

For dual VRAN ran k part

For touch screen part

For TPM part

For UMA part

X

PCH_SMB_CL K

PCH_SMB_DA TA

EC SMBus1 address

Device

Smart Battery

4 4

Charger

PCH

+3VALW_PC H

need to update

0001 0010 b

X

X

X

X

X X

EC SMBus2 address

Device

Thermal Sensor(NCT7718W )

PCH

DGPU

A

1001_100xb

need to update

need to update

V

+3VALW_PC H

EC SMBus3 address

Device AddressAddress

PMIC

B

V

+3VS

need to update

X

V

+3VS

PCH SM Bus address

Device AddressAddress

DDR4 SODIMM

Wlan

Security Classifi cation

Security Classifi cation

Security Classifi cation

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS C ONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS C ONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS C ONFIDENTIAL
AND TRADE SECRET INFORM ATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORM ATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORM ATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE I NFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE I NFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE I NFORMATION IT CONTAINS
MAY BE USED BY OR DISC LOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISC LOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISC LOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

C

need to update

Rese rve d

2015/08/20

2015/08/20

2015/08/20

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

2016/08/20

2016/08/20

2016/08/20

Titl e

Titl e

Titl e

Notes List

Notes List

Notes List

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date : Sheet of

Date : Sheet o f

Date : Sheet o f

EG521

EG521

EG521

Tuesday, April 25, 2017

Tuesday, April 25, 2017

Tuesday, April 25, 2017

3 60

3 60

E

3 60

0.2

0.2

0.2

Vinafix.com

5

HDMI D2

D D

HDMI D1

HDMI D0

HDMI CLK

+VCCIO

C C

+VCCSTG

12

RC19

check PROCHOT# circuit with PWR

H_PROCHOT#44,55

check H_THRMTRIP# if need to connector to EC

B B

1K_0402_5%

RC20 499 +-1% 0402

12

RC143
1K_0402_5%

+VCCST_CPU

1 2

HDMI_TX2-34
HDMI_TX2+34
HDMI_TX1-34
HDMI_TX1+34
HDMI_TX0-34
HDMI_TX0+34
HDMI_CLK-34
HDMI_CLK+34

DDPB_CLK34
DDPB_DATA34

RC4 24.9_0402_1%

12

+VCCIO&EDP_COMP :
Trace Width: 20mil
Isolation Spa cing: 25mil
Max length: 100mil

1 2

RC155 49.9_0402_1%

1 2

RC156 49.9_0402_1%

1 2

RC157 49.9_0402_1%U23E@

1 2

RC170 49.9_0402_1%U23E@

4

?

HDMI_TX2­HDMI_TX2+
HDMI_TX1­HDMI_TX1+
HDMI_TX0­HDMI_TX0+
HDMI_CLK­HDMI_CLK+

DDPB_CLK
DDPB_DATA

DDPC_CLK
DDPC_DATA

EDP_COMP PCH_ENVDD

+VCCST_CPU

12

RC1625

49.9_0402_1%

@

CATERR#

TC11PAD @
TC12PAD @
TC13PAD @
TC14PAD @

TC162@PAD

H_PECI
H_PROCHOT#_R
H_THRMTRIP#

XDP_BPM0#

1

XDP_BPM1#

1

XDP_BPM2#

1

XDP_BPM3#

1

GPP_E3

1

PROC_OPI_RCOMP
PCH_OPI_RCOMP
EDRAM_OPIO_RCOMP
EOPIO_RCOMP

H_PECI44

UC1A

E55

DDI1_TXN[0]

F55

DDI1_TXP[0]

E58

DDI1_TXN[1]

F58

DDI1_TXP[1]

F53

DDI1_TXN[2]

G53

DDI1_TXP[2]

F56

DDI1_TXN[3]

G56

DDI1_TXP[3]

C50

DDI2_TXN[0]

D50

DDI2_TXP[0]

C52

DDI2_TXN[1]

D52

DDI2_TXP[1]

A50

DDI2_TXN[2]

B50

DDI2_TXP[2]

D51

DDI2_TXN[3]

C51

DDI2_TXP[3]

L13

GPP_E18/DDPB_CTRLCLK

L12

GPP_E19/DDPB_CTRLDATA

N7

GPP_E20/DDPC_CTRLCLK

N8

GPP_E21/DDPC_CTRLDATA

N11

GPP_E22/DDPD_CTRLCLK

N12

GPP_E23/DDPD_CTRLDATA

E52

EDP_RCOMP

SKYLAKE-U_BGA1356

REV = 1

@

UC1D

D63

CATERR#

A54

PECI

C65

PROCHOT#

C63

THERMTRIP#

A65

SKTOCC#

C55

BPM#[0]

D55

BPM#[1]

B54

BPM#[2]

C56

BPM#[3]

A6

GPP_E3/CPU_GP0

A7

GPP_E7/CPU_GP1

BA5

GPP_B3/CPU_GP2

AY5

GPP_B4/CPU_GP3

AT16

PROC_POPIRCOMP

AU16

PCH_OPIRCOMP

H66

OPCE_RCOMP

H65

OPC_RCOMP

SKYLAKE-U_BGA1356

REV = 1
@

SKL_ ULT

DDI

DISPLAY SIDEBANDS

SKL_ ULT

CPU MISC

?

1 OF 20

1 OF 20

3

EDP

JTAG

PROC_TCK

PROC_TDI
PROC_TDO
PROC_TMS

PROC_TRST#

PCH_JTAG_TCK

PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS

PCH_TRST#

EDP_TXN[0]
EDP_TXP[0]
EDP_TXN[1]
EDP_TXP[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]

EDP_AUXN
EDP_AUXP

EDP_DISP_UTIL

DDI1_AUXN
DDI1_AUXP
DDI2_AUXN
DDI2_AUXP
DDI3_AUXN
DDI3_AUXP

GPP_E13/DDPB_HPD0
GPP_E14/DDPC_HPD1
GPP_E15/DDPD_HPD2
GPP_E16/DDPE_HPD3

GPP_E17/EDP_HPD

EDP_BKLTEN

EDP_BKLTCTL

EDP_VDDEN

B61
D60
A61
C60
B59

B56
D59
A56
C59
C61
A59

JTAGX

?

C47
C46
D46
C45
A45
B45
A47
B47

E45
F45

B52

G50
F50
E48
F48
G46
F46

L9
L7
L6
N9
L10

R12
R11
U13

?

XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#

PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
PCH_JTAG_TRST#

JTAGX

1
1
1
1
1

1
1
1
1
1
1

CPU_EDP_TX0­CPU_EDP_TX0+
CPU_EDP_TX1­CPU_EDP_TX1+

CPU_EDP_AUX#
CPU_EDP_AUX

HDMI_HPD

GPP_E15

CPU_EDP_HPD

PCH_ENBKL
PCH_EDP_PWM

PAD @

TC15

PAD @

TC16

PAD @

TC17

PAD @

TC18

PAD @

TC27

PAD @

TC29

PAD @

TC31

PAD @

TC35

PAD @

TC36

PAD @

TC42

PAD @

TC43

2

CPU_EDP_TX0- 33
CPU_EDP_TX0+ 33
CPU_EDP_TX1- 33
CPU_EDP_TX1+ 33

CPU_EDP_AUX# 33
CPU_EDP_AUX 33

HDMI_HPD 34

1 2

RC181 0_0402_5%

PCH_ENBKL 33
PCH_EDP_PWM 33
PCH_ENVDD 33

XDP_TCK

XDP_TDO

1 2

RC1546 0_0402_5%

1 2

RC1547 0_0402_5%

XDP_TDI PCH_JTAG_TDI

GPP_E15

RC1601 10K_0402_5%@

12

RC13
100K_0402_5%

JTAGX

PCH_JTAG_TDO

1 2

RC1548 0_0402_5%

1 2

RC1549 0_0402_5%

1 2

RC1550 0_0402_5%

check JTAG circuit?

1 2

+3VS

EC_SCI# 44

CPU_EDP_HPD 33

1 2

RC1551 51_0402_5%

1 2

RC1543 51_0402_5%

PCH_JTAG_TMSXDP_TMS

PCH_JTAG_TRST#XDP_TRST#

1

+VCCSTG

+3VS

DDP*_CTRLDATA strapping sam pled on the rising edge of PWROK

Port

Strap Enable Disable

Port 1

DDPB_CTRLDATA

Port 2

DDPC_CTRLDATA

A A

5

Pull up to 3.3 V
with 2.2Kohm

Pull up to 3.3 V
with 2.2Kohm

4

NC

NC

check DDPC_CLK pull high or not?

3

RPC26

1 4
2 3

2.2K_0404_4P2R_5%

RPC27

1 4
2 3

2.2K_0404_4P2R_5%

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

DDPC_CLK

@

Disable DDI2 G320 SDV wei

DDPC_DATA

DDPB_CLK
DDPB_DATA

2015/08/20

2015/08/20

2015/08/20

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/08/20

2016/08/20

2016/08/20

Title

Title

Title

MCP (DDI,EDP)

MCP (DDI,EDP)

MCP (DDI,EDP)

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Tuesday, April 25, 2017

Tuesday, April 25, 2017

Tuesday, April 25, 2017

EG521

EG521

EG521

1

4 60

4 60

4 60

0.2

0.2

0.2

Vinafix.com

5

DDRA_DQ[0..63]17

D D

C C

B B

4

?

SKL_ULT

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]

DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#
DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]

DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]

DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]

DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]

DDR CH - A

+3VALW

12

RC30
100K_0402 _5%

1 OF 20

DDRA_DQ0
DDRA_DQ1
DDRA_DQ2
DDRA_DQ3
DDRA_DQ4
DDRA_DQ5
DDRA_DQ6
DDRA_DQ7
DDRA_DQ8
DDRA_DQ9
DDRA_DQ10
DDRA_DQ11
DDRA_DQ12
DDRA_DQ13
DDRA_DQ14
DDRA_DQ15
DDRA_DQ16
DDRA_DQ17
DDRA_DQ18
DDRA_DQ19
DDRA_DQ20
DDRA_DQ21
DDRA_DQ22
DDRA_DQ23
DDRA_DQ24
DDRA_DQ25
DDRA_DQ26
DDRA_DQ27
DDRA_DQ28
DDRA_DQ29
DDRA_DQ30
DDRA_DQ31
DDRA_DQ32
DDRA_DQ33
DDRA_DQ34
DDRA_DQ35
DDRA_DQ36
DDRA_DQ37
DDRA_DQ38
DDRA_DQ39
DDRA_DQ40
DDRA_DQ41
DDRA_DQ42
DDRA_DQ43
DDRA_DQ44
DDRA_DQ45
DDRA_DQ46
DDRA_DQ47
DDRA_DQ48
DDRA_DQ49
DDRA_DQ50
DDRA_DQ51
DDRA_DQ52
DDRA_DQ53
DDRA_DQ54
DDRA_DQ55
DDRA_DQ56
DDRA_DQ57
DDRA_DQ58
DDRA_DQ59
DDRA_DQ60
DDRA_DQ61
DDRA_DQ62
DDRA_DQ63

UC1B

AL71

DDR0_DQ[0]

AL68

DDR0_DQ[1]

AN68

DDR0_DQ[2]

AN69

DDR0_DQ[3]

AL70

DDR0_DQ[4]

AL69

DDR0_DQ[5]

AN70

DDR0_DQ[6]

AN71

DDR0_DQ[7]

AR70

DDR0_DQ[8]

AR68

DDR0_DQ[9]

AU71

DDR0_DQ[10]

AU68

DDR0_DQ[11]

AR71

DDR0_DQ[12]

AR69

DDR0_DQ[13]

AU70

DDR0_DQ[14]

AU69

DDR0_DQ[15]

BB65

DDR0_DQ[16]/DDR0_DQ[32]

AW65

DDR0_DQ[17]/DDR0_DQ[33]

AW63

DDR0_DQ[18]/DDR0_DQ[34]

AY63

DDR0_DQ[19]/DDR0_DQ[35]

BA65

DDR0_DQ[20]/DDR0_DQ[36]

AY65

DDR0_DQ[21]/DDR0_DQ[37]

BA63

DDR0_DQ[22]/DDR0_DQ[38]

BB63

DDR0_DQ[23]/DDR0_DQ[39]

BA61

DDR0_DQ[24]/DDR0_DQ[40]

AW61

DDR0_DQ[25]/DDR0_DQ[41]

BB59

DDR0_DQ[26]/DDR0_DQ[42]

AW59

DDR0_DQ[27]/DDR0_DQ[43]

BB61

DDR0_DQ[28]/DDR0_DQ[44]

AY61

DDR0_DQ[29]/DDR0_DQ[45]

BA59

DDR0_DQ[30]/DDR0_DQ[46]

AY59

DDR0_DQ[31]/DDR0_DQ[47]

AY39

DDR0_DQ[32]/DDR1_DQ[0]

AW39

DDR0_DQ[33]/DDR1_DQ[1]

AY37

DDR0_DQ[34]/DDR1_DQ[2]

AW37

DDR0_DQ[35]/DDR1_DQ[3]

BB39

DDR0_DQ[36]/DDR1_DQ[4]

BA39

DDR0_DQ[37]/DDR1_DQ[5]

BA37

DDR0_DQ[38]/DDR1_DQ[6]

BB37

DDR0_DQ[39]/DDR1_DQ[7]

AY35

DDR0_DQ[40]/DDR1_DQ[8]

AW35

DDR0_DQ[41]/DDR1_DQ[9]

AY33

DDR0_DQ[42]/DDR1_DQ[10]

AW33

DDR0_DQ[43]/DDR1_DQ[11]

BB35

DDR0_DQ[44]/DDR1_DQ[12]

BA35

DDR0_DQ[45]/DDR1_DQ[13]

BA33

DDR0_DQ[46]/DDR1_DQ[14]

BB33

DDR0_DQ[47]/DDR1_DQ[15]

AY31

DDR0_DQ[48]/DDR1_DQ[32]

AW31

DDR0_DQ[49]/DDR1_DQ[33]

AY29

DDR0_DQ[50]/DDR1_DQ[34]

AW29

DDR0_DQ[51]/DDR1_DQ[35]

BB31

DDR0_DQ[52]/DDR1_DQ[36]

BA31

DDR0_DQ[53]/DDR1_DQ[37]

BA29

DDR0_DQ[54]/DDR1_DQ[38]

BB29

DDR0_DQ[55]/DDR1_DQ[39]

AY27

DDR0_DQ[56]/DDR1_DQ[40]

AW27

DDR0_DQ[57]/DDR1_DQ[41]

AY25

DDR0_DQ[58]/DDR1_DQ[42]

AW25

DDR0_DQ[59]/DDR1_DQ[43]

BB27

DDR0_DQ[60]/DDR1_DQ[44]

BA27

DDR0_DQ[61]/DDR1_DQ[45]

BA25

DDR0_DQ[62]/DDR1_DQ[46]

BB25

DDR0_DQ[63]/DDR1_DQ[47]

SKYLAKE-U_BGA1356

REV = 1

@

3

DDR0_CKN[0]
DDR0_CKP[0]
DDR0_CKN[1]
DDR0_CKP[1]

DDR0_CKE[0]
DDR0_CKE[1]
DDR0_CKE[2]
DDR0_CKE[3]

DDR0_CS#[0]
DDR0_CS#[1]
DDR0_ODT[0]
DDR0_ODT[1]

DDR0_MA[3]
DDR0_MA[4]

DDR0_DQSN[0]
DDR0_DQSP[0]
DDR0_DQSN[1]

DDR0_DQSP[1]
DDR0_DQSN[2]/DDR0_DQSN[4]
DDR0_DQSP[2]/DDR0_DQSP[4]
DDR0_DQSN[3]/DDR0_DQSN[5]
DDR0_DQSP[3]/DDR0_DQSP[5]
DDR0_DQSN[4]/DDR1_DQSN[0]
DDR0_DQSP[4]/DDR1_DQSP[0]
DDR0_DQSN[5]/DDR1_DQSN[1]
DDR0_DQSP[5]/DDR1_DQSP[1]
DDR0_DQSN[6]/DDR1_DQSN[4]
DDR0_DQSP[6]/DDR1_DQSP[4]
DDR0_DQSN[7]/DDR1_DQSN[5]
DDR0_DQSP[7]/DDR1_DQSP[5]

DDR0_ALERT#

DDR0_PAR

DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ

DDR_VTT_CNTL

2

AU53
AT53
AU55
AT55

BA56
BB56
AW56
AY56

AU45
AU43
AT45
AT43

BA51
BB54
BA52
AY52
AW52
AY55
AW54
BA54
BA55
AY54

AU46
AU48
AT46
AU50
AU52
AY51
AT48
AT50
BB50
AY50
BA50
BB52

DDRA_DQS#0

AM70

DDRA_DQS0

AM69

DDRA_DQS#1

AT69

DDRA_DQS1

AT70

DDRA_DQS#2

BA64

DDRA_DQS2

AY64

DDRA_DQS#3

AY60

DDRA_DQS3

BA60

DDRA_DQS#4

BA38

DDRA_DQS4

AY38

DDRA_DQS#5

AY34

DDRA_DQS5

BA34

DDRA_DQS#6

BA30

DDRA_DQS6

AY30

DDRA_DQS#7

AY26

DDRA_DQS7

BA26

AW50
AT52

AY67
AY68
BA67

DDR_VTT_C NTL

AW67

?

DDRA_CLK0# 17
DDRA_CLK0 17

DDRA_CKE0 17

DDRA_CS0# 17

DDRA_ODT0 17

DDRA_MA5 17
DDRA_MA9 17
DDRA_MA6 17
DDRA_MA8 17
DDRA_MA7 17
DDRA_BG0 17
DDRA_MA12 17
DDRA_MA11 17
DDRA_ACT# 17

DDRA_MA13 17
DDRA_MA15_CAS# 17
DDRA_MA14_W E# 17
DDRA_MA16_RAS# 17
DDRA_BS0# 17
DDRA_MA2 17
DDRA_BS1# 17
DDRA_MA10 17
DDRA_MA1 17
DDRA_MA0 17
DDRA_MA3 17
DDRA_MA4 17

DDRA_ALERT# 17
DDRA_PAR 1 7

DDR_SA_VREFCA 17

DDR_SB_VREFCA 18

DDRA_DQS#[0..7]

DDRA_DQS[0..7]

DDRA_DQS#[0..7] 17

DDRA_DQS[0..7] 17

SMVREF

WIDTH:20MI L
SPACING: 20MIL

1

+1.2V

1 2

RC3

1K_0402_5 %

DDR_VTT_C NTL

A A

5

4

2

B

RC29

10K_0402_ 5%

C

QC18

E

3 1

MMBT3904W H_SOT323-3

@

1 2

CPU_DRAMPG_C NTL 55

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE C ENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE C ENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE C ENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

3

2015/08/20

2015/08/20

2015/08/20

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/08/20

2016/08/20

2016/08/20

Titl e

Titl e

Titl e

MCP (DDR4)

MCP (DDR4)

MCP (DDR4)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date : Sheet of

Date : Sheet of

Date : Sheet of

Tuesday, April 25, 2017

Tuesday, April 25, 2017

Tuesday, April 25, 2017

EG521

EG521

EG521

1

5 60

5 60

5 60

0.2

0.2

0.2

Vinafix.com

5

DDRB_DQ[0..63]18

D D

C C

B B

4

DDRB_DQ0
DDRB_DQ1
DDRB_DQ2
DDRB_DQ3
DDRB_DQ4
DDRB_DQ5
DDRB_DQ6
DDRB_DQ7
DDRB_DQ8
DDRB_DQ9
DDRB_DQ10
DDRB_DQ11
DDRB_DQ12
DDRB_DQ13
DDRB_DQ14
DDRB_DQ15
DDRB_DQ16
DDRB_DQ17
DDRB_DQ18
DDRB_DQ19
DDRB_DQ20
DDRB_DQ21
DDRB_DQ22
DDRB_DQ23
DDRB_DQ24
DDRB_DQ25
DDRB_DQ26
DDRB_DQ27
DDRB_DQ28
DDRB_DQ29
DDRB_DQ30
DDRB_DQ31
DDRB_DQ32
DDRB_DQ33
DDRB_DQ34
DDRB_DQ35
DDRB_DQ36
DDRB_DQ37
DDRB_DQ38
DDRB_DQ39
DDRB_DQ40
DDRB_DQ41
DDRB_DQ42
DDRB_DQ43
DDRB_DQ44
DDRB_DQ45
DDRB_DQ46
DDRB_DQ47
DDRB_DQ48
DDRB_DQ49
DDRB_DQ50
DDRB_DQ51
DDRB_DQ52
DDRB_DQ53
DDRB_DQ54
DDRB_DQ55
DDRB_DQ56
DDRB_DQ57
DDRB_DQ58
DDRB_DQ59
DDRB_DQ60
DDRB_DQ61
DDRB_DQ62
DDRB_DQ63

UC1C

AF65

DDR1_DQ[0]/DDR0_DQ[16]

AF64

DDR1_DQ[1]/DDR0_DQ[17]

AK65

DDR1_DQ[2]/DDR0_DQ[18]

AK64

DDR1_DQ[3]/DDR0_DQ[19]

AF66

DDR1_DQ[4]/DDR0_DQ[20]

AF67

DDR1_DQ[5]/DDR0_DQ[21]

AK67

DDR1_DQ[6]/DDR0_DQ[22]

AK66

DDR1_DQ[7]/DDR0_DQ[23]

AF70

DDR1_DQ[8]/DDR0_DQ[24]

AF68

DDR1_DQ[9]/DDR0_DQ[25]

AH71

DDR1_DQ[10]/DDR0_DQ[26]

AH68

DDR1_DQ[11]/DDR0_DQ[27]

AF71

DDR1_DQ[12]/DDR0_DQ[28]

AF69

DDR1_DQ[13]/DDR0_DQ[29]

AH70

DDR1_DQ[14]/DDR0_DQ[30]

AH69

DDR1_DQ[15]/DDR0_DQ[31]

AT66

DDR1_DQ[16]/DDR0_DQ[48]

AU66

DDR1_DQ[17]/DDR0_DQ[49]

AP65

DDR1_DQ[18]/DDR0_DQ[50]

AN65

DDR1_DQ[19]/DDR0_DQ[51]

AN66

DDR1_DQ[20]/DDR0_DQ[52]

AP66

DDR1_DQ[21]/DDR0_DQ[53]

AT65

DDR1_DQ[22]/DDR0_DQ[54]

AU65

DDR1_DQ[23]/DDR0_DQ[55]

AT61

DDR1_DQ[24]/DDR0_DQ[56]

AU61

DDR1_DQ[25]/DDR0_DQ[57]

AP60

DDR1_DQ[26]/DDR0_DQ[58]

AN60

DDR1_DQ[27]/DDR0_DQ[59]

AN61

DDR1_DQ[28]/DDR0_DQ[60]

AP61

DDR1_DQ[29]/DDR0_DQ[61]

AT60

DDR1_DQ[30]/DDR0_DQ[62]

AU60

DDR1_DQ[31]/DDR0_DQ[63]

AU40

DDR1_DQ[32]/DDR1_DQ[16]

AT40

DDR1_DQ[33]/DDR1_DQ[17]

AT37

DDR1_DQ[34]/DDR1_DQ[18]

AU37

DDR1_DQ[35]/DDR1_DQ[19]

AR40

DDR1_DQ[36]/DDR1_DQ[20]

AP40

DDR1_DQ[37]/DDR1_DQ[21]

AP37

DDR1_DQ[38]/DDR1_DQ[22]

AR37

DDR1_DQ[39]/DDR1_DQ[23]

AT33

DDR1_DQ[40]/DDR1_DQ[24]

AU33

DDR1_DQ[41]/DDR1_DQ[25]

AU30

DDR1_DQ[42]/DDR1_DQ[26]

AT30

DDR1_DQ[43]/DDR1_DQ[27]

AR33

DDR1_DQ[44]/DDR1_DQ[28]

AP33

DDR1_DQ[45]/DDR1_DQ[29]

AR30

DDR1_DQ[46]/DDR1_DQ[30]

AP30

DDR1_DQ[47]/DDR1_DQ[31]

AU27

DDR1_DQ[48]

AT27

DDR1_DQ[49]

AT25

DDR1_DQ[50]

AU25

DDR1_DQ[51]

AP27

DDR1_DQ[52]

AN27

DDR1_DQ[53]

AN25

DDR1_DQ[54]

AP25

DDR1_DQ[55]

AT22

DDR1_DQ[56]

AU22

DDR1_DQ[57]

AU21

DDR1_DQ[58]

AT21

DDR1_DQ[59]

AN22

DDR1_DQ[60]

AP22

DDR1_DQ[61]

AP21

DDR1_DQ[62]

AN21

DDR1_DQ[63]

SKYLAKE-U_BGA1356

REV = 1
@

3

?

SKL_U LT

DDR1_CKN[0]
DDR1_CKN[1]
DDR1_CKP[0]
DDR1_CKP[1]

DDR1_CKE[0]
DDR1_CKE[1]
DDR1_CKE[2]
DDR1_CKE[3]

DDR1_CS#[0]
DDR1_CS#[1]
DDR1_ODT[0]

DDR1_MA[5]/DDR1_CAA[0]/DDR1_M A[5]
DDR1_MA[9]/DDR1_CAA[1]/DDR1_M A[9]
DDR1_MA[6]/DDR1_CAA[2]/DDR1_M A[6]
DDR1_MA[8]/DDR1_CAA[3]/DDR1_M A[8]
DDR1_MA[7]/DDR1_CAA[4]/DDR1_M A[7]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
DDR1_MA[12]/DDR1_CAA[6]/DDR1_M A[12]
DDR1_MA[11]/DDR1_CAA[7]/DDR1_M A[11]

DDR1_MA[15]/DDR1_CAA[8]/DDR1_AC T#
DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

DDR1_MA[13]/DDR1_CAB[0]/DDR1_M A[13]

DDR1_CAS#/DDR1_CAB[1]/DDR1 _MA[15]

DDR1_WE#/DDR1_C AB[2]/DDR1_MA[14]

DDR1_RAS#/DDR1_CAB[3]/DDR1 _MA[16]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]

DDR1_MA[2]/DDR1_CAB[5]/DDR1_M A[2]

DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]
DDR1_MA[10]/DDR1_CAB[7]/DDR1_M A[10]

DDR1_MA[1]/DDR1_CAB[8]/DDR1_M A[1]
DDR1_MA[0]/DDR1_CAB[9]/DDR1_M A[0]

DDR1_DQSN[0]/DDR0_DQSN[2]
DDR1_DQSP[0]/DDR0_DQSP[2]
DDR1_DQSN[1]/DDR0_DQSN[3]
DDR1_DQSP[1]/DDR0_DQSP[3]
DDR1_DQSN[2]/DDR0_DQSN[6]
DDR1_DQSP[2]/DDR0_DQSP[6]
DDR1_DQSN[3]/DDR0_DQSN[7]
DDR1_DQSP[3]/DDR0_DQSP[7]
DDR1_DQSN[4]/DDR1_DQSN[2]
DDR1_DQSP[4]/DDR1_DQSP[2]
DDR1_DQSN[5]/DDR1_DQSN[3]
DDR1_DQSP[5]/DDR1_DQSP[3]

DDR CH - B

1 OF 20

DDR1_ODT[1]

DDR1_MA[3]
DDR1_MA[4]

DDR1_DQSN[6]
DDR1_DQSP[6]
DDR1_DQSN[7]
DDR1_DQSP[7]

DDR1_ALERT#

DRAM_RESET#
DDR_RCOMP[0]
DDR_RCOMP[1]
DDR_RCOMP[2]

DDR1_PAR

AN45
AN46
AP45
AP46

AN56
AP55
AN55
AP53

BB42
AY42
BA42
AW42

AY48
AP50
BA48
BB48
AP48
AP52
AN50
AN48
AN53
AN52

BA43
AY43
AY44
AW44
BB44
AY47
BA44
AW46
AY46
BA46
BB46
BA47

AH66
AH65
AG69
AG70
AR66
AR65
AR61
AR60
AT38
AR38
AT32
AR32
AR25
AR27
AR22
AR21

AN43
AP43
AT13
AR18
AT18
AU18

?

DDRB_DQS#0
DDRB_DQS0
DDRB_DQS#1
DDRB_DQS1
DDRB_DQS#2
DDRB_DQS2
DDRB_DQS#3
DDRB_DQS3
DDRB_DQS#4
DDRB_DQS4
DDRB_DQS#5
DDRB_DQS5
DDRB_DQS#6
DDRB_DQS6
DDRB_DQS#7
DDRB_DQS7

CPU_DRAMRST#_R
SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2

2

DDRB_CLK0# 18
DDRB_CLK1# 18
DDRB_CLK0 18
DDRB_CLK1 18

DDRB_CKE0 18
DDRB_CKE1 18

DDRB_CS0# 18
DDRB_CS1# 18
DDRB_ODT0 18
DDRB_ODT1 18

DDRB_MA5 18
DDRB_MA9 18
DDRB_MA6 18
DDRB_MA8 18
DDRB_MA7 18
DDRB_BG0 18
DDRB_MA12 18
DDRB_MA11 18
DDRB_ACT# 18
DDRB_BG1 18

DDRB_MA13 18
DDRB_MA15_CAS# 18
DDRB_MA14_WE # 18
DDRB_MA16_RAS# 18
DDRB_BS0# 18
DDRB_MA2 18
DDRB_BS1# 18
DDRB_MA10 18
DDRB_MA1 18
DDRB_MA0 18
DDRB_MA3 18
DDRB_MA4 18

DDRB_DQS#[0..7]

DDRB_DQS[0..7]

DDRB_ALERT# 18

DDRB_PAR 18

1 2

RC24 121_0402_1%

1 2

RC25 80.6_0402_1%

1 2

RC26 100_0402_1%

1

DDRB_DQS#[0..7] 18

DDRB_DQS[0..7] 18

+1.2V

12

RC22
470_0402_5%

2015/08/20

2015/08/20

2015/08/20

CPU_DRAMRST#_R

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/08/20

2016/08/20

2016/08/20

Title

Title

Title

MCP (DDR4)

MCP (DDR4)

MCP (DDR4)

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Tuesday, April 25, 2017

Tuesday, April 25, 2017

Tuesday, April 25, 2017

EG521

EG521

EG521

6 60

6 60

1

6 60

0.2

0.2

0.2

1 2

CPU_DRAMRST#17,18

A A

5

4

RC23 0_0402_5%

1

CC1

0.01U_0201_25V6-K

EMC_NS@

2

Security Cl assification

Security Cl assification

Security Cl assification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENT ER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENT ER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENT ER.

3

Vinafix.com

5

4

3

2

1

?

UC1E

AW13

AW3

AW2

AY11

AV2

AV3

AU4
AU3
AU2
AU1

M2
M3

J4
V1
V2
M1

G3
G2
G1

SPI - FLASH

SPI0_CLK
SPI0_MISO
SPI0_MOSI
SPI0_IO2
SPI0_IO3
SPI0_CS0#
SPI0_CS1#
SPI0_CS2#

SPI - TOUCH

GPP_D1/SPI1_CLK
GPP_D2/SPI1_MISO
GPP_D3/SPI1_MOSI
GPP_D21/SPI1_IO2
GPP_D22/SPI1_IO3
GPP_D0/SPI1_CS#

C LINK

CL_CLK
CL_DATA
CL_RST#

GPP_A0/RCIN#

GPP_A6/SERIRQ

SKYLAKE-U_BGA1356

REV = 1

@

2.2K_0404_4P2R_5%

PCH_SML1_CLK

PCH_SML1_DAT

D D

C C

B B

SPI_CLK44

SPI_SO44

SPI_SI44

SPI_CS0#44

Check with BIOS, SPI is Dual mode or quad mode

SPI_CLK SPI_CLK_R

SPI_SO

SPI_SI

SPI_CS0# SPI_CS0#_R

+3VS

+3V_SPI

1. If support DS3, connect to +3VS and don't support EC mirror code;

2. If don't support DS3, connect to +3VALW_PCH and support EC mirror c ode.

*

SPI_WP#_R

RC54 15_0402_5%@

SPI_HOLD#_R

RC55 15_0402_5%@

SPI_CS0#

SPI_SO

SPI_WP#

1 2

RC1539 15_0402_5%

1 2

RC53 15_0402_5%

1 2

RC52 15_0402_5%

1 2

RC51 0_0402_5%

+3VALW_PCH

RC171 0_0402_5%

RC172 0_0402_5%@

1 2

1 2

UC3

1

/CS

2

DO (IO1)

3

IO2

GND4DI (IO0)

W25Q64JVSSIQ_SO8

1 2

1 2

VCC

IO3

CLK

1K_0402_5%

8

7

6

5

RC60

SPI_SO_R

SPI_SI_R

+3V_SPI

+3V_SPI

12

SPI_HOLD#

SPI_CLK

SPI_SI

12

RC61
1K_0402_5%

SPI_WP#

SPI_HOLD#

+3V_SPI

BOARD_ID48

KBRST#44

SERIRQ32,44

1

CC8

0.1u_0201_10V6K

2

SPI_CLK_R
SPI_SO_R
SPI_SI_R
SPI_WP#_R
SPI_HOLD#_R
SPI_CS0#_R

BOARD_ID4

KBRST#

SERIRQ

SKL_U LT

SMBUS, SMLINK

GPP_B23/SML1ALERT#/PCHHOT#

LPC

GPP_A5/LFRAME#/ESPI_CS#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

1 OF 20

check CLKRUN# / SUS_STAT# signal if need to connect

PM_CLKRUN#

SERIRQ

KBRST#

KBRST#

+3VALW_PCH +3VS

RPC25

1 4

2 3

1 2

RC11 8.2K_0402_5%

1 2

RC12 10K_0402_5%

1 2

RC10 10K_0402_5%

1 2

CC1255 1000P_0201_50V7-K

EMC_NS@

2

G

6 1

QC10A

2N7002KDWH_SOT363-6

D

QC10B

S

2N7002KDWH_SOT363-6

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3

GPP_A10/CLKOUT_LPC1

GPP_A8/CLKRUN#

@

5

G

3 4

@

S

D

+3VS

PCH_SMB_CLK

R7

PCH_SMB_DATA

R8

SMB_ALERT#

R10

SML0_CLK

R9

SML0_DATA

W2

SML0_ALERT#

W1

PCH_SML1_CLK

W3

PCH_SML1_DAT

V3

SML1_ALERT#

AM7

AY13
BA13
BB13
AY12
BA12

SUS_STAT#

BA11

CLK_PCI_EC_R

AW9

CLK_PCI_TPM_R

AY9

PM_CLKRUN#

AW11

?

DIMM, NGFF

GPU, EC, Thermal Sensor

RC173 22_0402_5%
RC1541 22_0402_5%TPM@

EC_SMB_CK2 39,44

EC_SMB_DA2 39,44

LPC_AD0 32,44
LPC_AD1 32,44
LPC_AD2 32,44
LPC_AD3 32,44
LPC_FRAME# 32,44

12
12

1

TC81@

SML0_ALERT#

SML1_ALERT#

To enable Direct Connect Interface (DCI), a 150K pull up resist or will need to be
added to PCHHOT# pin. This pin must be low during the ris ing edge of RSMRST#.
(Refer to WW 52_MOW)

+3VALW_PCH +3VS +3VS

RPC20

2.2K_0404_4P2R_5%

PCH_SMB_CLK

PCH_SMB_DATA

CLK_PCI_EC 44
CLK_PCI_TPM 32
PM_CLKRUN# 32

SMB_ALERT#

SML0_CLK
SML0_DATA

This signal has a weak internal pull-down.
0 = LPC Is selected for EC. (Default)
1 = eSPI Is selected for EC.
Notes:

1. The internal pull-down is disabled after RSMRST#
de-assert s.

2. This signal is in the primary wel
Rising edge of RSMRST#

1 4

2 3

2.2K_0404_4P2R_5%

RC1564 2.2K_0402_5%@

1 2

RC1569 150K_0402_5%@

1 2

RC1655 150K_0402_5%

QC2A

2N7002KDWH_SOT363-6

12

2.2K_0402_5%

RPC23

14
23

12

2

G

6 1

D

QC2B

RC1562

S

5

G

3 4

S

D

2N7002KDWH_SOT363-6

+3VALW_PCH

+3VALW_PCH

+3VALW_PCH

+3VALW_PCH

RPC24

2.2K_0404_4P2R_5%

1 4

2 3

+3VS

SMB_CLK_S3 18,40

SMB_DATA_S3 18,40

A A

Titl e

Titl e

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

5

4

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

3

2015/08/20

2015/08/20

2015/08/20

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/08/20

2016/08/20

2016/08/20

Titl e

MCP (MISC,JTAG,SPI,LPC,SMB)

MCP (MISC,JTAG,SPI,LPC,SMB)

MCP (MISC,JTAG,SPI,LPC,SMB)

Size

Size

Size

Document Number Rev

Document Number Rev

Document Number Rev

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

Tuesday, April 25, 2017

Tuesday, April 25, 2017

Tuesday, April 25, 2017

EG521

EG521

EG521

1

7 60

7 60

7 60

0.2

0.2

0.2

Vinafix.com

5

D D

+3VS

RPC28

1 4
2 3

2.2K_0404_4P2R_5%

RC1658 10K_0402_5%

12

PCH_I2C_SDA0
PCH_I2C_SCL0

PCH_TP_INT#

10/25 SIT For I2C T/P Function wei

1 2

RC1561 2.2K_0402_5%@

+3VS

HDA_SDOUT

HDA_SDOUT

PCH_CMOS_ON#33

UART_RX_DEBUG40
UART_TX_DEBUG40

TP_I2C_SDA045
TP_I2C_SCL045

PCH_WLAN_OFF#40
PCH_BT_OFF#40

HDA_SYNC_AUDIO30
HDA_BITCLK_AUDIO30

HDA_SDIN030

HDA_RST_AUDIO#30

*

*

+3VS

PCH_CMOS_ON#
PCH_WLAN_OFF#
PCH_BT_OFF#

HDA_SDIN0

1 2
1 2

PCH_BEEP

Internal PD
0 = Disable “ Top Swap”
mode. (Default)
1 = Enable “ Top Swap”
mode.

Internal PD
0 = Disable “ No Reboot”
mode. (Default)
1 = Enable “ No Reboot”
mode

Internal PD
0 = SPI (Default)
1 = LPC

+3VS

RC1600 1K_0402_5%@

RC47 1K_0402_5%@

1 2

12
12
12

1 2

1 2

RC45 33_0402_5%
RC46 0_0402_5%

RC1595 10K_0402_5%@
RC1596 10K_0402_5%
RC1597 10K_0402_5%

double check if need the pull up resisor

C C

+3VALW_PCH

*

HDA_SDO This signal has a weak internal pull-down.
0 = Enable security measures defined in the Flash Descriptor.
1 = Disable Flash Descriptor Security(override). This strap
should only be asserted high during external pull-up in
manufacturing/debug environments ONLY.

For EMI

1

CC7
10P_0201_50V8F

EMC_NS@

2

B B

HDA_SDOUT_AUDIO30
ME_FLASH44

+3VS

RC14 2.2K_0402_5%@

Pin Name Strap Description Configurat ion

SPKR /

Top Swap

GPP_B14

Override

GSPI0_MOSI

No Reboot

A A

/GPP_B18

GSPI1_MOSI
/GPP_B22

Boot BIOS
Strap Bit
BBS

1 2

RC1563 2.2K_0402_5%@

1 2

RC1656 0_0402_5%

1 2

RC1657 0_0402_5%

PCH_BEEP30

Default

When

Value

Sampled

0*Rising edge

of PCH_PWROK

Rising edge

0

of PCH_PWROK

Rising edge

0

of PCH_PWROK

4

GPP_B18

GPP_B22

DGPU_PWROK

PCH_I2C_SDA0
PCH_I2C_SCL0

PCH_WLAN_OFF#
PCH_BT_OFF#

1 2

RC43 33_0402_5%

1 2

RC42 33_0402_5%

1 2

RC44 33_0402_5%

AM5

AH10

AH11
AH12

AF11
AF12

HDA_SYNC
HDA_BCLK
HDA_SDOUT
HDA_SDIN0

HDA_RST#

BOARD_ID10
BOARD_ID9

PCH_BEEP

UC1F

AN8

GPP_B15/GSPI0_CS#

AP7

GPP_B16/GSPI0_CLK

AP8

GPP_B17/GSPI0_MISO

AR7

GPP_B18/GSPI0_MOSI

GPP_B19/GSPI1_CS#

AN7

GPP_B20/GSPI1_CLK

AP5

GPP_B21/GSPI1_MISO

AN5

GPP_B22/GSPI1_MOSI

AB1

GPP_C8/UART0_RXD

AB2

GPP_C9/UART0_TXD

W4

GPP_C10/UART0_RTS#

AB3

GPP_C11/UART0_CTS#

AD1

GPP_C20/UART2_RXD

AD2

GPP_C21/UART2_TXD

AD3

GPP_C22/UART2_RTS#

AD4

GPP_C23/UART2_CTS#

U7

GPP_C16/I2C0_SDA

U6

GPP_C17/I2C0_SCL

U8

GPP_C18/I2C1_SDA

U9

GPP_C19/I2C1_SCL

AH9

GPP_F4/I2C2_SDA
GPP_F5/I2C2_SCL

GPP_F6/I2C3_SDA
GPP_F7/I2C3_SCL

GPP_F8/I2C4_SDA
GPP_F9/I2C4_SCL

SKYLAKE-U_BGA1356

REV = 1
@

BA22
AY22
BB22
BA21
AY21

AW22

AY20

AW20

AK7
AK6
AK9

AK10

AW5

3

?

AUDIO

SKL_U LT

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

GPP_C14/UART1_RTS#/ISH_UART1_RTS#
GPP_C15/UART1_CTS#/ISH_UART1_CTS#

1 OF 20

?

SKL_U LT

1 OF 20

GPP_C12/UART1_RXD/ISH_UART1_RXD
GPP_C13/UART1_TXD/ISH_UART1_TXD

LPSS ISH

UC1G

HDA_SYNC/I2S0_SFRM
HDA_BLK/I2S0_SCLK
HDA_SDO/I2S0_TXD
HDA_SDI0/I2S0_RXD
HDA_SDI1/I2S1_RXD
HDA_RST#/I2S1_SCLK

J5

GPP_D23/I2S_MCLK
I2S1_SFRM
I2S1_TXD

GPP_F1/I2S2_SFRM
GPP_F0/I2S2_SCLK
GPP_F2/I2S2_TXD
GPP_F3/I2S2_RXD

H5

GPP_D19/DMIC_CLK0

D7

GPP_D20/DMIC_DATA0

D8

GPP_D17/DMIC_CLK1

C8

GPP_D18/DMIC_DATA1

GPP_B14/SPKR

SKYLAKE-U_BGA1356

REV = 1
@

@UMA SKU

RC1558 10K_0402_5%UMA@

GPP_D5/ISH_I2C0_SDA
GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA
GPP_D8/ISH_I2C1_SCL

GPP_F10/I2C5_SDA/ISH_I2C2_SDA

GPP_F11/I2C5_SCL/ISH_I2C2_SCL

GPP_D15/ISH_UART0_RTS#

GPP_A18/ISH_GP0
GPP_A19/ISH_GP1
GPP_A20/ISH_GP2
GPP_A21/ISH_GP3
GPP_A22/ISH_GP4
GPP_A23/ISH_GP5

GPP_A12/BM_BUSY#/ISH_GP6

SDIO/SDXC

GPP_G0/SD_CMD
GPP_G1/SD_DATA0
GPP_G2/SD_DATA1
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3

GPP_G5/SD_CD#
GPP_G6/SD_CLK

GPP_G7/SD_WP

GPP_A17/SD_PWR_EN#/ISH_GP7

GPP_A16/SD_1P8_SEL

SD_RCOMP

GPP_F23

?

1 2

GPP_D9
GPP_D10
GPP_D11
GPP_D12

?

AB11
AB13
AB12
W12
W11
W10
W8
W7

BA9
BB9

AB7

AF13

P2
P3
P4
P1

M4
N3

N1
N2

AD11
AD12

U1
U2
U3
U4

AC1
AC2
AC3
AB4

AY8
BA8
BB7
BA7
AY7
AW7
AP13

BOARD_ID0
BOARD_ID1

BOARD_ID3

BOARD_ID6
BOARD_ID5PCH_CMOS_ON#

BOARD_ID7
BOARD_ID8

SD_RCOMP

DGPU_PWROK

12

RC49
200_0402_1%

2

BOARD_ID29

BOARD_ID47

PCH_TP_INT# 45

BOARD_ID0
BOARD_ID1
BOARD_ID2
BOARD_ID3
BOARD_ID4
BOARD_ID5

DIMM_ONLY@

BOARD_ID6
BOARD_ID7
BOARD_ID8
BOARD_ID9
BOARD_ID10

@

15@

RC1615

RC1613

1 2

1 2

10K_0402_5%

14@

RC1614

RC1616

1 2

1 2

10K_0402_5%

Board ID Descri ption

Board_ID[0:1 ]

Board_ID2

Board_ID3

Board_ID4

Board_ID5

DIMM_ONLY@

12

RC1631

10K_0402_5%

@

@

12

RC1634

10K_0402_5%

DescriptionBoard ID

00

Board_ID
[6,7]

01

10

11 SO-DIMM Only

Board_ID8

Board_ID9

Board_ID10

01320G RC 1636

01Reserved

0

1

@

RC1611

1 2

10K_0402_5%

@

RC1612

1 2

10K_0402_5%

00

14"

01

15"

10

17"

11

Reserved

0

Reserved

1

Reserved

0

UMA

1

DIS

0

NV GPU

1

AMD GPU

0

Reserved

1

Reserved

520Z@

12

RC1632

10K_0402_5%

320G@

12

RC1635

10K_0402_5%

Samsung 8Gb

2400 MT/s

Hynix 8Gb

2400 MT/s

Micron 8Gb

2400 MT/s

520Z

Reserved

Reserved

Reserved

DIS@

1 2

10K_0402_5%

UMA@

RC1610

1 2

10K_0402_5%

12

RC1633

10K_0402_5%

12

RC1636

10K_0402_5%

Stuff R

RC1634 RC1635

RC1631

RC1631

RC1633

RC1640

RC1639

RC1652

RC1651

1

PX@

RC1609

RC1608

1 2

10K_0402_5%

10K_0402_5%

OPT@

RC1607

1 2

10K_0402_5%

10K_0402_5%

Stuff R

RC1616

RC1614

RC1616 RC1613

RC1615

RC1614

RC1615 RC1613

RC1612

RC1611

RC1610

RC1609

RC1607

RC1608

RC123

RC1606

@

12

RC1639

10K_0402_5%

@

12

RC1640

10K_0402_5%

RC1632RC1634

RC1635

RC1632

@

@

+3VS

@

@

+3VS

RC1606

1 2

10K_0402_5%

RC123

10K_0402_5%

1 2

12

RC1651

10K_0402_5%

12

RC1652

10K_0402_5%

Titl e

Titl e

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

5

4

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

3

2015/08/20

2015/08/20

2015/08/20

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/08/20

2016/08/20

2016/08/20

Titl e

MCP (LPSS,ISH,AUDIO,SDIO)

MCP (LPSS,ISH,AUDIO,SDIO)

MCP (LPSS,ISH,AUDIO,SDIO)

Size

Size

Size

Document Number Rev

Document Number Rev

Document Number Rev

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

Tuesday, April 25, 2017

Tuesday, April 25, 2017

Tuesday, April 25, 2017

EG521

EG521

EG521

1

8 60

8 60

8 60

0.2

0.2

0.2

Vinafix.com

5

4

3

2

1

D D

UC1H

PCIE/U SB3/SATA

H13

PCIE1_RXN/USB3_5_RXN

G13

PCIE1_RXP/USB3_5_RXP

B17

PCIE1_TXN/USB3_5_TXN

A17

PCIE1_TXP/USB3_5_TXP

G11

PCIE2_RXN/USB3_6_RXN

F11

PCIE2_RXP/USB3_6_RXP

D16

PCIE2_TXN/USB3_6_TXN

C16

PCIE2_TXP/USB3_6_TXP

H16

PCIE3_RXN

G16

PCIE3_RXP

D17

PCIE3_TXN

C17

PCIE3_TXP

G15

PCIE4_RXN

F15

PCIE4_RXP

B19

PCIE4_TXN

A19

PCIE_PRX_DTX_N537
PCIE_PRX_DTX_P537

C C

LAN

WLAN

SATA HDD

SATA ODD

Optane Memory

B B

A A

PCIE_PTX_C_DRX_N537
PCIE_PTX_C_DRX_P537

PCIE_PRX_DTX_N640
PCIE_PRX_DTX_P640
PCIE_PTX_C_DRX_N640
PCIE_PTX_C_DRX_P640

SATA_PRX_DTX_N042

SATA_PRX_DTX_P042

SATA_PTX_DRX_N042

SATA_PTX_DRX_P042

SATA_PRX_DTX_N142
SATA_PRX_DTX_P142

SATA_PTX_DRX_N142
SATA_PTX_DRX_P142

PCIE_PRX_DTX_N940
PCIE_PRX_DTX_P940
PCIE_PTX_C_DRX_N940
PCIE_PTX_C_DRX_P940

PCIE_PRX_DTX_N1040
PCIE_PRX_DTX_P1040
PCIE_PTX_C_DRX_N1040
PCIE_PTX_C_DRX_P1040

PCIE_RCOMPN and PCIE_RCOMPP
Trace Width: 12-15mil
Differential between RCOMPP/RCOMPN

PCIE_PRX_DTX_N1140
PCIE_PRX_DTX_P1140
PCIE_PTX_C_DRX_N1140
PCIE_PTX_C_DRX_P1140
PCIE_PRX_DTX_N1240
PCIE_PRX_DTX_P1240
PCIE_PTX_C_DRX_N1240
PCIE_PTX_C_DRX_P1240

RC119 100_0402_1%

+3VS

SATA2GP

Add SSD_DET# for Optane memory wei

5

1 2

CC1262 0.1u_0201_ 10V6K

1 2

CC1261 0.1u_0201_ 10V6K

1 2

CC1264 0.1u_0201_ 10V6K

1 2

CC1263 0.1u_0201_ 10V6K

OPTANE@

1 2

CC22 0.22U_ 0201_6.3V6-K

1 2

CC23 0.22U_ 0201_6.3V6-K

OPTANE@
OPTANE@

1 2

CC1266 0.22U_0 201_6.3V6-K

1 2

CC1265 0.22U_0 201_6.3V6-K

OPTANE@

1 2

TC20PAD @
TC19PAD @

OPTANE@

1 2

CC1267 0.22U_0 201_6.3V6-K

1 2

CC1268 0.22U_0 201_6.3V6-K

OPTANE@
OPTANE@

1 2

CC1269 0.22U_0 201_6.3V6-K

1 2

CC1270 0.22U_0 201_6.3V6-K

OPTANE@

RPC2

1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

RC189 0_0402_5%

ODD_DETECT#
SATA0GP

SATA2GP
PIRQA#

1 2

OPTANE@

4

PCIE_PRX_DTX_N5
PCIE_PRX_DTX_P5
PCIE_PTX_DRX_N5
PCIE_PTX_DRX_P5

PCIE_PRX_DTX_N6
PCIE_PRX_DTX_P6
PCIE_PTX_DRX_N6
PCIE_PTX_DRX_P6

SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
SATA_PTX_DRX_N0
SATA_PTX_DRX_P0

SATA_PRX_DTX_N1
SATA_PRX_DTX_P1
SATA_PTX_DRX_N1
SATA_PTX_DRX_P1

PCIE_PRX_DTX_N9
PCIE_PRX_DTX_P9
PCIE_PTX_DRX_N9
PCIE_PTX_DRX_P9

PCIE_PRX_DTX_N10
PCIE_PRX_DTX_P10
PCIE_PTX_DRX_N10
PCIE_PTX_DRX_P10

PCIE_RCOMPN
PCIE_RCOMPP

XDP_PRDY#

1

XDP_PREQ#

1

PIRQA#

PCIE_PRX_DTX_N11
PCIE_PRX_DTX_P11
PCIE_PTX_DRX_N11
PCIE_PTX_DRX_P11
PCIE_PRX_DTX_N12
PCIE_PRX_DTX_P12
PCIE_PTX_DRX_N12
PCIE_PTX_DRX_P12

F16
E16
C19
D19

G18
F18
D20
C20

F20
E20
B21
A21

G21
F21
D21
C21

E22
E23
B23
A23

F25
E25
D23
C23

F5

E5

D56
D61

BB11

E28
E27
D24
C24
E30
F30
A25
B25

SSD_DET# 40

PCIE4_TXP

PCIE5_RXN
PCIE5_RXP
PCIE5_TXN
PCIE5_TXP

PCIE6_RXN
PCIE6_RXP
PCIE6_TXN
PCIE6_TXP

PCIE7_RXN/SATA0_RXN
PCIE7_RXP/SATA0_RXP
PCIE7_TXN/SATA0_TXN
PCIE7_TXP/SATA0_TXP

PCIE8_RXN/SATA1A_RXN
PCIE8_RXP/SATA1A_RXP
PCIE8_TXN/SATA1A_TXN
PCIE8_TXP/SATA1A_TXP

PCIE9_RXN
PCIE9_RXP
PCIE9_TXN
PCIE9_TXP

PCIE10_RXN
PCIE10_RXP
PCIE10_TXN
PCIE10_TXP

PCIE_RCOMPN
PCIE_RCOMPP

PROC_PRDY#
PROC_PREQ#
GPP_A7/PIRQA#

PCIE11_RXN/SATA1B_RXN
PCIE11_RXP/SATA1B_RXP
PCIE11_TXN/SATA1B_TXN
PCIE11_TXP/SATA1B_TXP
PCIE12_RXN/SATA2_RXN
PCIE12_RXP/SATA2_RXP
PCIE12_TXN/SATA2_TXN
PCIE12_TXP/SATA2_TXP

SKYLAKE-U_BGA1356

REV = 1
@

USB_OC0#
USB_OC1#
USB_OC3#
USB_OC2#

Security Cl assification

Security Cl assification

Security Cl assification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENT ER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENT ER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENT ER.

SKL_U LT

3

?

SSIC / USB3

USB2

GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2

1 OF 20

RPC17

18
27
36

10K_0804_8P4R_5%

45

2015/08/20

2015/08/20

2015/08/20

USB3_1_RXN

USB3_1_RXP
USB3_1_TXN
USB3_1_TXP

USB3_2_RXN/SSIC_1_RXN

USB3_2_RXP/SSIC_1_RXP
USB3_2_TXN/SSIC_1_TXN

USB3_2_TXP/SSIC_1_TXP

USB3_3_RXN/SSIC_2_RXN

USB3_3_RXP/SSIC_2_RXP
USB3_3_TXN/SSIC_2_TXN

USB3_3_TXP/SSIC_2_TXP

USB3_4_RXN

USB3_4_RXP
USB3_4_TXN
USB3_4_TXP

USB2N_1
USB2P_1

USB2N_2
USB2P_2

USB2N_3
USB2P_3

USB2N_4
USB2P_4

USB2N_5
USB2P_5

USB2N_6
USB2P_6

USB2N_7
USB2P_7

USB2N_8
USB2P_8

USB2N_9
USB2P_9

USB2N_10
USB2P_10

USB2_COMP

USB2_ID

USB2_VBUSSENSE

GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#

GPP_E4/DEVSLP0
GPP_E5/DEVSLP1
GPP_E6/DEVSLP2

GPP_E8/SATALED#

?

+3VALW_PCH

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

USB30_RX_N1

H8
G8
C13
D13

J6
H6
B13
A13

J10
H10
B15
A15

E10
F10
C15
D15

AB9
AB10

AD6
AD7

AH3
AJ3

AD9
AD10

AJ1
AJ2

AF6
AF7

AH1
AH2

AF8
AF9

AG1
AG2

AH7
AH8

AB6
AG3
AG4

A9
C9
D9
B9

J1
J2
J3

H2
H3
G4

H1

USB30_RX_P1
USB30_TX_N1
USB30_TX_P1

USB30_RX_N2
USB30_RX_P2
USB30_TX_N2
USB30_TX_P2

USB30_RX_N3
USB30_RX_P3
USB30_TX_N3
USB30_TX_P3

USB20_N1
USB20_P1

USB20_N2
USB20_P2

USB20_N3
USB20_P3

USB20_N4
USB20_P4

USB20_N5
USB20_P5

USB20_N6
USB20_P6

USB20_N7
USB20_P7

USB20_N8
USB20_P8

USB2_COMP
USB2_ID
USB2_VBUSSENSE

USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#

GPP_E4
GPP_E5

SATA0GP
ODD_DETECT#

SATA2GP

BOARD_ID2

GPP_E4

USB_OC2#

USB30_RX_N1 41
USB30_RX_P1 41
USB30_TX_N1 41

USB30_TX_P1 41

USB30_RX_N2 43
USB30_RX_P2 43
USB30_TX_N2 43
USB30_TX_P2 43

USB30_RX_N3 41
USB30_RX_P3 41
USB30_TX_N3 41
USB30_TX_P3 41

USB20_N1 41
USB20_P1 41

USB20_N2 43
USB20_P2 43

USB20_N3 41
USB20_P3 41

USB20_N4 45
USB20_P4 45

USB20_N5 30
USB20_P5 30

USB20_N6 33
USB20_P6 33

USB20_N7 40
USB20_P7 40

USB20_N8 33
USB20_P8 33

RC118 113_0402_1%
RC1626 0_0402_5%
RC1627 1K_0402_5%

USB_OC1# 41

1

BOARD_ID2 8

RC1617 10K_0402_5%@

RC1654 0_0402_5%

12
1 2
1 2

TC202PAD@

2016/05/03: Implement as Power Button
function for Windows RedStone support

12

1 2

LEFT USB3.0

Type-C

LEFT USB3.0

LEFT USB3.0

Type-C

LEFT USB3.0

Finger Print

Card reader

Touch panel

BT

Camera

RC1628 0_0402_5%

8/24 Reserve TYPE_C_OCP# to CPU USB_OC2# wei

2016/08/20

2016/08/20

Deciphered Date

Deciphered Date

Deciphered Date

2016/08/20

2

USBRBIAS

Width 20Mil
Space 15Mil
Length 500Mil

1 2

+3VS

TYPE_C_OCP# 43

Title

Title

Title

MCP (PCIE,SATA,USB3,USB2)

MCP (PCIE,SATA,USB3,USB2)

MCP (PCIE,SATA,USB3,USB2)

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Tuesday, April 25, 2017

Tuesday, April 25, 2017

Tuesday, April 25, 2017

EC_SMI# 44

EG521

EG521

EG521

9 60

9 60

1

9 60

0.2

0.2

0.2

Vinafix.com

5

D D

C C

B B

check the Pull up resistor

+3VS

RPC4

1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

Optane memory

PCIE CLK5 WLAN

PCIE CLK4 LAN

LAN_CLKREQ#
WLAN_CLKREQ#
SSD_PCIE_CLKREQ#

CLK_PCIE_SSD#40
CLK_PCIE_SSD40

SSD_PCIE_CLKREQ#40

CLK_PCIE_WLAN#40
CLK_PCIE_WLAN40
WLAN_CLKREQ#40

CLK_PCIE_LAN#37
CLK_PCIE_LAN37
LAN_CLKREQ#37

4

CLK_PCIE_SSD#
CLK_PCIE_SSD
SSD_PCIE_CLKREQ#

CLK_PCIE_WLAN#
CLK_PCIE_WLAN
WLAN_CLKREQ#

CLK_PCIE_LAN#
CLK_PCIE_LAN
LAN_CLKREQ#

A36

CSI2_DN0

B36

CSI2_DP0

C38

CSI2_DN1

D38

CSI2_DP1

C36

CSI2_DN2

D36

CSI2_DP2

A38

CSI2_DN3

B38

CSI2_DP3

C31

CSI2_DN4

D31

CSI2_DP4

C33

CSI2_DN5

D33

CSI2_DP5

A31

CSI2_DN6

B31

CSI2_DP6

A33

CSI2_DN7

B33

CSI2_DP7

A29

CSI2_DN8

B29

CSI2_DP8

C28

CSI2_DN9

D28

CSI2_DP9

A27

CSI2_DN10

B27

CSI2_DP10

C27

CSI2_DN11

D27

CSI2_DP11

SKYLAKE-U_BGA1356

REV = 1
@

UC1J

D42

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0

AR10

GPP_B5/SRCCLKREQ0#

B42

CLKOUT_PCIE_N1

A42

CLKOUT_PCIE_P1

AT7

GPP_B6/SRCCLKREQ1#

D41

CLKOUT_PCIE_N2

C41

CLKOUT_PCIE_P2

AT8

GPP_B7/SRCCLKREQ2#

D40

CLKOUT_PCIE_N3

C40

CLKOUT_PCIE_P3

AT10

GPP_B8/SRCCLKREQ3#

B40

CLKOUT_PCIE_N4

A40

CLKOUT_PCIE_P4

AU8

GPP_B9/SRCCLKREQ4#

E40

CLKOUT_PCIE_N5

E38

CLKOUT_PCIE_P5

AU7

GPP_B10/SRCCLKREQ5#

SKYLAKE-U_BGA1356

REV = 1
@

UC1I

CSI-2

SKL_U LT

SKL_U LT

CLOCK SIGNALS

?

EMMC

GPP_F13/EMMC_DATA0
GPP_F14/EMMC_DATA1
GPP_F15/EMMC_DATA2
GPP_F16/EMMC_DATA3
GPP_F17/EMMC_DATA4
GPP_F18/EMMC_DATA5
GPP_F19/EMMC_DATA6
GPP_F20/EMMC_DATA7

GPP_F21/EMMC_RCLK

GPP_F22/EMMC_CLK

GPP_F12/EMMC_CMD

1 OF 20

?

1 OF 20

3

CSI2_CLKN0
CSI2_CLKP0
CSI2_CLKN1
CSI2_CLKP1
CSI2_CLKN2
CSI2_CLKP2
CSI2_CLKN3
CSI2_CLKP3

CSI2_COMP

GPP_D4/FLASHTRIG

EMMC_RCOMP

?

CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

GPD8/SUSCLK

XCLK_BIASREF

C37
D37
C32
D32
C29
D29
B26
A26

E13
B7

AP2
AP1
AP3
AN3
AN1
AN2
AM4
AM1

AM2
AM3
AP4

AT1

XTAL24_IN

XTAL24_OUT

RTCX1
RTCX2

SRTCRST#

RTCRST#

?

CSI2_COMP

EMMC_RCOMP

F43
E43

BA17

E37
E35

E42

AM18
AM20

AN18
AM16

1 2

RC73 100_0402_1%

1 2

RC50 200_0402_1%

CLK_PCIE_XDP#
CLK_PCIE_XDP

SUSCLK

DIFFCLK_BIASREF

RTC_X1
RTC_X2

SRTC_RST#
RTC_RST#

1
1

RC72 2.7K_0402_1%

VCCRTC

RC33 20K_0402_1%
RC34 20K_0402_1%

TC85 @
TC87 @

SUSCLK 40

1 2

1 2
1 2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

SUSCLK

DIFFCLK_BIASREF

+VCCCLK5

1

CC3

2

1

CC6

2

1 2

RC95 1K_0402_5%@

1 2

RC1555 60.4_0402_1%

Cannonlake@

SRTC_RST#
RTC_RST#

12

JCMOS1
SHORT PADS

@

RC1624

1 2

@

0_0402_5%

1

EC_RTC_RST# 44

RTC_X1

RTC_X2

2

CC5
7P_0402_50V8J

1

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

when single end external clock generator used,
this pin should be grounded

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/08/20

2016/08/20

2016/08/20

Title

Title

Title

MCP (CSI2,EMMC,CLOCK)

MCP (CSI2,EMMC,CLOCK)

MCP (CSI2,EMMC,CLOCK)

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Tuesday, April 25, 2017

Tuesday, April 25, 2017

Tuesday, April 25, 2017

EG521

EG521

EG521

10 60

10 60

1

10 60

0.2

0.2

0.2

YC1

1 2

12

2015/08/20

2015/08/20

2015/08/20

RC32 10M_0402_5%

32.768KHZ_9PF_X1A0001410002

2

CC4
7P_0402_50V8J

1

A A

Security Cl assification

Security Cl assification

Security Cl assification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENT ER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENT ER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENT ER.

3

Vinafix.com

5

D D

+3VALW

C C

PLT_RST#32,37,40,44

EC_RSMRST#44

SYS_PWROK44
PCH_PWROK44

SUSWARN#44

SUSACK#44

PCIE_WAKE#37,40,44

1 2

RC74 10K_0402_5%

1 2

RC75 8.2K_0402_5%

RC76 1K_0402_5%

RC90 10K_0402_5%

12

1 2

VCCST_PWRGD_R

AC_PRESENT_R

BATLOW#

WAKE#

PCH_LAN_WAKE#

TC21PAD@

Reserve for DS3

Follow CRB change to 1kohm

4

1 2

RC84 0_0402_5%

1 2

RC85 0_0402_5%

1

1 2

RC93 60.4_0402_1%

1 2

RC139 0_0402_5%

1 2

RC126 0_0402_5%

1 2

RC86 0_0402_5%@

1 2

RC79 0_0402_5%@

1 2

RC91 0_0402_5%@

PLT_RST#_R
SYS_RESET#
PCH_RSMRST#_R

CPU_PROCPWRGD
VCCST_PWRGD

SYS_PWROK_R
PCH_PWROK_R
PCH_DPWROK_R

SUSWARN#_R
SUSACK#_R

WAKE#
PCH_LAN_WAKE#

UC1K

SYSTEM POWER MANAGEMENT

AN10

GPP_B13/PLTRST#

B5

SYS_RESET#

AY17

RSMRST#

A68

PROCPWRGD

B65

VCCST_PWRGD

B6

SYS_PWROK

BA20

PCH_PWROK

BB20

DSW_PWR OK

AR13

GPP_A13/SUSWARN#/SUS PWRDNACK

AP11

GPP_A15/SUSACK#

BB15

WAKE#

AM15

GPD2/LAN_WAKE#

AW17

GPD11/LANPHYPC

AT15

GPD7/RSVD

SKYLAKE-U_BGA1356

REV = 1
@

3

SKL_U LT

?

1 OF 20

GPP_B12/SLP_S0#

GPD4/SLP_S3#
GPD5/SLP_S4#

GPD10/SLP_S5#

SLP_SUS#
SLP_LAN#

GPD9/SLP_WLAN#

GPD6/SLP_A#

GPD3/PWRBTN#

GPD1/ACPRESENT

GPD0/BATLOW#

GPP_A11/PME#

GPP_B11/EXT_PWR_GATE#

INTRUDER#

GPP_B2/VRALERT#

?

AT11
AP15
BA16
AY16

AN15
AW15
BB17
AN16

BA15
AY15
AU13

AU11
AP16

AM10
AM11

PM_SLP_S3#_R
PM_SLP_S4#_R

PM_SLP_SUS#_R

PBTN_OUT#_R
AC_PRESENT_R

BATLOW#

PME#
INTVRMEN

AC_PRESENT44

2

1 2

RC96 0_0402_5%@

1 2

RC97 0_0402_5%@

1 2

RC89 0_0402_5%@

Reserve for DS3

1 2

RC87 0_0402_5%@

1

TC89@

RC41 330K_0402_5%

RC88 0_0402_5%@

12

1 2

ACIN#44

2

G

PM_SLP_S3# 13,44
PM_SLP_S4# 44

PM_SLP_SUS# 44

PBTN_OUT# 44

VCCRTC

AC_PRESENT_R

13

D

QC8
2N7002KW_SOT323-3

@

S

1

+3VALW_PCH

1 2

RC78 10K_0402_5%@

+3VS

1 2

RC80 10K_0402_5%

1 2

1 2

B B

1 2

1 2

1 2

Add to fix Reset&PWRGD test fail issue

RPC21

1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

A A

1 2

@

10/25 SIT Add to fix PLT_RST# glitch issue wei

5

SUSWARN#_R

SYS_RESET#

PCH_RSMRST#_R

CC12541000P_0201_50V7-K

EMC_NS@

Stuff to fix Reset&PWRGD test fail issue

PCH_PWROK

CC1040.01U_0201_10V6K

PCH_DPWROK_R

CC1031000P_0201_50V7-K

EMC_NS@

SYS_PWROK

CC10147P_0201_25V8-J

EC_RSMRST#

CC12600.01U_0201_10V6K

PCH_RSMRST#_R
PCH_PWROK
SYS_PWROK

PLT_RST#_R

12

RC92100K_0402_5%

PCH_DPWROK_R

12

RC94100K_0402_1% @

PLT_RST#

CC1294100P_0201_25V8J

1 2

EC_VCCST_PWR GD44

4

RC138 0_0402_5%@

PM_SLP_S3#

1

CC46

0.01U_0201_25V6-K

EMC_NS@

2

Security Cl assification

Security Cl assification

Security Cl assification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENT ER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENT ER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENT ER.

3

+3VALW +VCCST_CPU +VCCSTG

5

G

Deciphered Date

Deciphered Date

Deciphered Date

RC137
1K_0402_5%

1 2

34

D

QC6B
2N7002KDWH_SOT363-6

@

S

RC136
10K_0402_5%

@

1 2

61

D

2

RC1599 0_0402_5%

DC4

RB751V-40_SOD323-2

G

1 2

1 2

QC6A
2N7002KDWH_SOT363-6

@

S

@

2015/08/20

2015/08/20

2015/08/20

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

VCCST_PWRGD_R

PCH_DPWROK_R

2

RC1554
1K_0402_5%

@

1 2

RC182 0_0402_5%

RC81 0_0402_5%@

2016/08/20

2016/08/20

2016/08/20

2

CC140
1000P_0201_50V7-K

EMC_NS@

1

1 2

1 2

Reserve for DS3

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

EC_RSMRST#

DPWROK_EC 44

MCP (SYSTEM PWR MANAGEMENT)

MCP (SYSTEM PWR MANAGEMENT)

MCP (SYSTEM PWR MANAGEMENT)

EG521

EG521

Tuesday, April 25, 2017

Tuesday, April 25, 2017

Tuesday, April 25, 2017

EG521

1

11 60

11 60

11 60

0.2

0.2

0.2

Vinafix.com

5

+CPU_CORE +CPU_CORE +VCC_GT

32000mA

D D

1

TC90@

+CPU_CORE

C C

12x10uF 0402, SIT update to 0603 package

1

1

CC1085

CC1086

2

2

10U_0402_6.3V6M

1

1

CC1296

CC1295

2

2

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1

2

A30
A34
A39

A44
AK33
AK35
AK37
AK38
AK40
AL33
AL37
AL40
AM32
AM33
AM35
AM37
AM38

G30

K32

AK32

AB62

P62

V62

H63

G61

AC63
AE63

AE62
AG62

AL63
AJ62

CC1080

10U_0603_6.3V6M

UC1L

VCC_A30
VCC_A34
VCC_A39
VCC_A44
VCC_AK33
VCC_AK35
VCC_AK37
VCC_AK38
VCC_AK40
VCC_AL33
VCC_AL37
VCC_AL40
VCC_AM32
VCC_AM33
VCC_AM35
VCC_AM37
VCC_AM38
VCC_G30

RSVD_K32

RSVD_AK32

VCCOPC_AB62
VCCOPC_P62
VCCOPC_V62

VCC_OPC_1P8_H63

VCC_OPC_1P8_G61

VCCOPC_SENSE
VSSOPC_SENSE

VCCEOPIO_AE62
VCCEOPIO_AG62

VCCEOPIO_SENSE
VSSEOPIO_SENSE

SKYLAKE-U _BGA1356

REV = 1
@

1

CC1236

2

10U_0603_6.3V6M

1

CC1237

2

?

SKL_ULT

CPU POWER 1 OF 4

1

CC1093

2

10U_0603_6.3V6M

1 OF 20

10U_0603_6.3V6M

1

2

VCC_SENSE
VSS_SENSE

VCCSTG_G20

CC1092

10U_0603_6.3V6M

VCC_G32
VCC_G33
VCC_G35
VCC_G37
VCC_G38
VCC_G40
VCC_G42

VCC_J30
VCC_J33
VCC_J37

VCC_J40
VCC_K33
VCC_K35
VCC_K37
VCC_K38
VCC_K40
VCC_K42
VCC_K43

VIDALERT#

VIDSCK

VIDSOUT

1

CC1091

2

G32
G33
G35
G37
G38
G40
G42
J30
J33
J37
J40
K33
K35
K37
K38
K40
K42
K43

E32
E33

B63
A63
D64

G20

?

1

CC1089

2

10U_0603_6.3V6M

VCORE_VC C_SEN
VCORE_VS S_SEN

CPU_SVID_ ALERT#_R
CPU_SVID_ CLK_R
CPU_SVID_ DAT_R

1

CC1238

2

10U_0603_6.3V6M

10U_0603_6.3V6M

4

VCORE_VC C_SEN

VCORE_VS S_SEN VCCGT_VSS _SEN

VCORE_VC C_SEN 59
VCORE_VS S_SEN 5 9

+VCCSTG

1

1

1

CC1097

CC1305

2

2

10U_0402_6.3V6M

1

CC1104

CC1299

2

2

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1 2

RC77 100 _0402_1%

1 2

RC82 100 _0402_1%

VR_SVID_ ALRT#5 9

VR_SVID_ CLK59

VR_SVID_ DAT59

+VCC_GT

Backside Cap 8x10uF 0402, SIT update

1

1

1

CC1119

CC1240

2

CC1124

2

2

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

@

@

3

+CPU_CORE +VCC_GT

SVID

1 2

VCCGT_VCC_ SEN

+VCCST_CPU

12

12

RC131

56_0402_5%

RC132

RC1544

100_0402_1%

100_0402_1%

@

RC133 220_0 402_1%

RC134 0_040 2_5%

RC1545 0_04 02_5%

1 2

RC83 100 _0402_1%

1 2

RC98 100 _0402_1%

1

CC42

0.1u_02 01_10V6K

@

2

1 2

1 2

1 2

CPU_SVID_ ALERT#_R

CPU_SVID_ CLK_R

CPU_SVID_ DAT_R

1, Alert# Route Between CLK and Data

1

1

1

1

CC1126

CC1125

2

2

2

10U_0402_6.3V6M

10U_0402_6.3V6M

1

CC1128

CC1127

2

2

10U_0402_6.3V6M

10U_0402_6.3V6M

@

1

1

CC1129

2

10U_0402_6.3V6M

1

CC1312

CC1311

CC1313

2

2

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

2

+VCC_GT

31000m A

+CPU_CORE

VCCGT_VCC_ SEN59
VCCGT_VSS _SEN59

VCCGT_VCC_ SEN
VCCGT_VSS _SEN

UC1M

A48

VCCGT_A48

A53

VCCGT_A53

A58

VCCGT_A58

A62

VCCGT_A62

A66

VCCGT_A66

AA63

VCCGT_AA63

AA64

VCCGT_AA64

AA66

VCCGT_AA66

AA67

VCCGT_AA67

AA69

VCCGT_AA69

AA70

VCCGT_AA70

AA71

VCCGT_AA71

AC64

VCCGT_AC64

AC65

VCCGT_AC65

AC66

VCCGT_AC66

AC67

VCCGT_AC67

AC68

VCCGT_AC68

AC69

VCCGT_AC69

AC70

VCCGT_AC70

AC71

VCCGT_AC71

J43

VCCGT_J43

J45

VCCGT_J45

J46

VCCGT_J46

J48

VCCGT_J48

J50

VCCGT_J50

J52

VCCGT_J52

J53

VCCGT_J53

J55

VCCGT_J55

J56

VCCGT_J56

J58

VCCGT_J58

J60

VCCGT_J60

K48

VCCGT_K48

K50

VCCGT_K50

K52

VCCGT_K52

K53

VCCGT_K53

K55

VCCGT_K55

K56

VCCGT_K56

K58

VCCGT_K58

K60

VCCGT_K60

L62

VCCGT_L62

L63

VCCGT_L63

L64

VCCGT_L64

L65

VCCGT_L65

L66

VCCGT_L66

L67

VCCGT_L67

L68

VCCGT_L68

L69

VCCGT_L69

L70

VCCGT_L70

L71

VCCGT_L71

M62

VCCGT_M62

N63

VCCGT_N63

N64

VCCGT_N64

N66

VCCGT_N66

N67

VCCGT_N67

N69

VCCGT_N69

J70

VCCGT_SENSE

J69

VSSGT_SENSE

SKYLAKE-U _BGA1356

REV = 1
@

SKL_ULT

CPU POWER 2 OF 4

?

VCCGTX_SENSE

VSSGTX_SENSE

1 OF 20

VCCGT_N70
VCCGT_N71
VCCGT_R63
VCCGT_R64
VCCGT_R65
VCCGT_R66
VCCGT_R67
VCCGT_R68
VCCGT_R69
VCCGT_R70
VCCGT_R71
VCCGT_T62
VCCGT_U65
VCCGT_U68

VCCGT_U71
VCCGT_W63
VCCGT_W64
VCCGT_W65
VCCGT_W66
VCCGT_W67
VCCGT_W68
VCCGT_W69
VCCGT_W70
VCCGT_W71

VCCGT_Y62

VCCGTX_AK42
VCCGTX_AK43
VCCGTX_AK45
VCCGTX_AK46
VCCGTX_AK48
VCCGTX_AK50
VCCGTX_AK52
VCCGTX_AK53
VCCGTX_AK55
VCCGTX_AK56
VCCGTX_AK58
VCCGTX_AK60
VCCGTX_AK70
VCCGTX_AL43
VCCGTX_AL46
VCCGTX_AL50
VCCGTX_AL53
VCCGTX_AL56

VCCGTX_AL60
VCCGTX_AM48
VCCGTX_AM50
VCCGTX_AM52
VCCGTX_AM53
VCCGTX_AM56
VCCGTX_AM58

VCCGTX_AU58

VCCGTX_AU63

VCCGTX_BB57

VCCGTX_BB66

?

N70
N71
R63
R64
R65
R66
R67
R68
R69
R70
R71
T62
U65
U68
U71
W63
W64
W65
W66
W67
W68
W69
W70
W71
Y62

AK42
AK43
AK45
AK46
AK48
AK50
AK52
AK53
AK55
AK56
AK58
AK60
AK70
AL43
AL46
AL50
AL53
AL56
AL60
AM48
AM50
AM52
AM53
AM56
AM58
AU58
AU63
BB57
BB66

AK62
AL61

1

+CPU_CORE

VCCGTX_SE NSE
VSSGTX_S ENSE

1

TC133 @

1

TC134 @

+CPU_CORE

15x1uF 0201, SIT update to 0402 package

1

1

CC1095

CC1096

2

1U_0402_6.3V6K

1U_0402_6.3V6K

B B

+CPU_CORE

1

CC1308

CC1298

2

1U_0402_6.3V6K

1U_0402_6.3V6K

@

1

1

CC1099

CC1098

2

2

2

1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

@

1

CC1302

CC1301

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

1

CC1101

CC1100

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

CC1102

2

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

@

@

1

1

CC1303

CC1304

2

2

1U_0402_6.3V6K

1

CC1105

2

1U_0402_6.3V6K

@

1

1

CC1306

2

1U_0402_6.3V6K

@

1

CC1307

CC1309

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

@

@

1

1

CC1108

CC1109

2

2

1U_0201_6.3V6-M

1U_0201_6.3V6-M

@

@

1

1

1

CC1310

CC1297

2

1U_0402_6.3V6K

@

CC1300

2

2

1U_0201_6.3V6-M

1U_0201_6.3V6-M

@

@

+VCC_GT

Backside Cap 12x1uF 0201, SIT update

1

CC1111

2

1U_0402_6.3V6K

1

CC1115

CC1114

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

CC1116

2

2

1U_0402_6.3V6K

1

CC1118

2

1U_0402_6.3V6K

1

1

CC1122

2

1U_0402_6.3V6K

@

1

CC1123

CC1241

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

@

1

CC1314

2

1U_0402_6.3V6K

@

SDV Add for U42 wei 02/21

A A

Titl e

Titl e

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2016/12/14

2016/12/14

2016/12/14

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2017/12/13

2017/12/13

2017/12/13

Titl e

MCP (CPU PWR1)

MCP (CPU PWR1)

MCP (CPU PWR1)

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

Tuesday, April 25, 2017

Tuesday, April 25, 2017

Tuesday, April 25, 2017

EG521

EG521

EG521

1

12 60

12 60

12 60

0.2

0.2

0.2

Vinafix.com

5

+1.2V

D D

CD@

C C

2A , 3x22uF, 6x10uF, 4x1uF, SIT update

1

1

CC1257

+1.2V

CC1258

2

22U_0603_6.3V6-M

22U_0603_6.3V6-M

1

1

CC1168

2

2

10U_0603_6.3V6M

CD@

1 2

RC1497 0_04 02_5%

1 2

RC104 0_040 2_5%

1

CC1256

2

2

22U_0603_6.3V6-M

1

1

CC1171

CC1169

2

2

10U_0402_6.3V6M

10U_0402_6.3V6M

1

CC1222

CC1223

2

10U_0603_6.3V6M

10U_0603_6.3V6M

+VDDQ_CPU_ CLK

1

CC1229

2

@

1U_0201_6.3V6-M

+VCCSFR_OC

1

CC85

2

1U_0201_6.3V6-M

1

CC1244

CC1243

2

2

2

10U_0402_6.3V6M

10U_0402_6.3V6M

CD@

@

@

1

CC1228

2

10U_0402_6.3V6M

1

1

1

1

CC1224

CC1226

CC1225

2

2

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

CD@

@

+VCCIO

+VCCST_CPU

Reserved for VCCST/VCCSTG /VCCPLL
power optimi zed

+VCCST_CPU

4

1

CC1227

2

1U_0201_6.3V6-M

@

RC103 0_040 2_5%

RC1604 0_04 02_5%@

+VDDQ_CPU_ CLK

1 2

1 2

1 2

RC105 0_040 2_5%

+VCCST_CPU

+VCCSTG

+VCCSFR_OC

+VCCPLL_C PU

+VCCSTG

3

3100mA

5100mA

VCCIO_SE NSE
VSSIO_S ENSE

VCCSA_VS S_SEN
VCCSA_VC C_SEN

+VCCIO

+VCCSA

1

TC136 @

1

TC137 @

VCCSA_VS S_SEN 5 9
VCCSA_VC C_SEN 59

VCCSA_VC C_SEN

VCCSA_VS S_SEN

RC101 100_0 402_1%

RC102 100_0 402_1%

+1.2V

2800mA

130mA

+VCCST_CPU

120mA

1

1

2

CC87

1U_0402_6.3V6K

CC86

2

+VCCPLL_C PU

1U_0402_6.3V6K

UC1N

AU23

VDDQ_AU23

AU28

VDDQ_AU28

AU35

VDDQ_AU35

AU42

VDDQ_AU42

BB23

VDDQ_BB23

BB32

VDDQ_BB32

BB41

VDDQ_BB41

BB47

VDDQ_BB47

BB51

VDDQ_BB51

AM40

VDDQC

A18

VCCST

A22

VCCSTG_A22

AL23

VCCPLL_OC

K20

VCCPLL_K20

K21

VCCPLL_K21

SKYLAKE-U _BGA1356

REV = 1
@

SKL_ULT

CPU POWER 3 OF 4

1 OF 20

VCCIO_AK28
VCCIO_AK30
VCCIO_AL30
VCCIO_AL42
VCCIO_AM28
VCCIO_AM30
VCCIO_AM42

VCCSA_AK23
VCCSA_AK25

VCCSA_G23
VCCSA_G25
VCCSA_G27
VCCSA_G28

VCCSA_J22
VCCSA_J23

VCCSA_J27
VCCSA_K23
VCCSA_K25
VCCSA_K27
VCCSA_K28
VCCSA_K30

VCCIO_SENSE
VSSIO_SENSE

VSSSA_SENSE
VCCSA_SENSE

AK28
AK30
AL30
AL42
AM28
AM30
AM42

AK23
AK25
G23
G25
G27
G28
J22
J23
J27
K23
K25
K27
K28
K30

AM23
AM22

H21
H20

?

?

2

+VCCIO

3.1A 2x10uF, 4x1uF

+VCCSA

1

1

CC1152

2

2

10U_0402_6.3V6M

1

1

CC1153

CC1159

CC1158

2

2

1U_0201_6.3V6-M

1U_0201_6.3V6-M

10U_0402_6.3V6M

@

@

4.5A 10x10uF, 7x1uF, SIT update

1

2

CC1132

10U_0603_6.3V6M

1 2

1 2

1

2

1

1

CC1135

CC1133

CC1134

2

2

10U_0603_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

@

@

+VCCSA

1

1

1

1

1

CC1230

1U_0402_6.3V6K

CC1251

10U_0603_6.3V6M

@

1

CC1231

2

2

1U_0402_6.3V6K

@

1

1

CC1252

2

2

10U_0402_6.3V6M

@

RC1605 0_040 2_5%@

CC1232

1U_0402_6.3V6K

CC1253

10U_0402_6.3V6M

1 2

1

CC1139

2

1U_0402_6.3V6K

CD@

1

1

1

CC1140

2

2

1U_0402_6.3V6K

1

CC1145

CC1142

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

CD@

1

1

CC1141

CC1144

CC1143

2

2

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

@

CD@

1

CC1161

CC1160

2

@

1

CC1136

2

CC1218

2

2

2

1U_0402_6.3V6K

1U_0201_6.3V6-M

1U_0201_6.3V6-M

@

1

2

10U_0603_6.3V6M

1

CC1137

2

10U_0603_6.3V6M

+1.0VALW +VCCST_CPU

Reserved for VCCST/VCCSTG/VCCPLL power optimized

120mA

1

1

CC84

CC1249

2

2

1U_0402_6.3V6K

0.1u_0201_10V6K

CC1250

1

2

+VCCIO

1

C1102

2

@

10U_0603_6.3V6M

+VCCST_CPU

1

CC80

2

@

2016/08/20

2016/08/20

2016/08/20

22U_0603_6.3V6-M

10U_0603_6.3V6M

Titl e

Titl e

Titl e

MCP (CPU PWR2)

MCP (CPU PWR2)

MCP (CPU PWR2)

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

Tuesday, April 25, 2017

Tuesday, April 25, 2017

Tuesday, April 25, 2017

EG521

EG521

EG521

1

13 60

13 60

13 60

0.2

0.2

0.2

+1.0VALW

1 2

B B

A A

5

EC_VCCIO_ EN44

PM_SLP_ S3#11,44

EC_VCCST_E N44

RC128 0_0 402_5%

1 2

DC1

RB751V-4 0_SOD323-2

1 2

RC142 0_0 402_5%

VCCIO_EN

@

1

0.01U_02 01_6.3V7 -K
CC77

2

@

VCCST_EN

1

0.01U_02 01_6.3V7 -K
CC81

2

@

4

+1.0VALW

CC79

10U_0603_6.3V6M

1

1

CC72

CC71

2

2

@

10U_0603_6.3V6M

22U_0603_6.3V6-M

1

2

+5VALW

VCCIO_EN

VCCST_EN

UC4

1

OUT1_2

IN1_1

2

OUT1_1

IN1_2

3

EN1

4

VBIAS

5

EN2

6

IN2_1

OUT2_2

7

IN2_2

OUT2_1

G5016KD 1U_TDFN14_2X3

14
13

12

CC1293 1000P _0201_50V 7-K

CT1

11

GND

10

CC1292 1000P _0201_50V 7-K

CT2

9
8

15

GPAD

1 2

1 2

Follow DG470 change to Dual Switch 8/24 wei

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/08/20

2015/08/20

2015/08/20

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Vinafix.com

5

1 2

RC1503 0_0603_5%

+1.0VALW +VCCAMPHY

+1.0VALW +VCCAPLL_1P0

D D

+3VALW_PCH

1 2

RC1504 0_0402_5%

1 2

RC1586 0_0402_5%

+VCCHDA

4

3

1 2

RC1622 0_0402_5%

2

+VCCPGPPG+3VALW_PCH

1

+VCCDSW_1P0

+VCCHDA

1

2

CD@

VCCMPHYON_1P0_L1

+1.0VALW

PCH Internal VRM

1

CC165

2

75mA

+1.0VALW

CC171

1U_0402_6.3V6K

1

CC144

2

1U_0402_6.3V6K

+3VALW_PCH

1

CC156

2

@

@

20mA

AK15

4mA

AG15

6mA

Y16

8mA

Y15

6mA

T16

161mA

AF16

61mA

AD15

V19

T1

6mA

AA1

1mA

AK17

AK19
BB14

BB10

VCCRTCEXT

35mA

A14

29mA

K19

24mA

L21

33mA

N20

4mA

L19

10mA

A10

AN11
AN13

?

1U_0402_6.3V6K

1mA

1

1

CC172

2

Near Y15

1

CC173

2

1U_0402_6.3V6K

+VCCPGPPG

CC174

2

@

1U_0402_6.3V6K

1U_0402_6.3V6K

1

CC175

2

@

1U_0402_6.3V6K

1

2

+1.0VALW

1

CC57

2

1U_0402_6.3V6K

1 2

C1099

22U_0603_6.3V6-M

1 2

C1100

22U_0603_6.3V6-M

RC15880_0603_5%

RC15890_0603_5%

1

2

@

1

2

@

+3VALW_PCH

1

CC176

2

@

1U_0402_6.3V6K

1 2

1

CC56

C1098

2

@

1U_0402_6.3V6K

22U_0603_6.3V6-M

+1.0VALW+VCCCLK4

+1.0VALW+VCCCLK5

+1.8VALW

1

CC142

2

RC15870_0603_5%

1U_0402_6.3V6K

+1.0VALW

1

CC149

2

0.1u_0201_10V6K

1

CC55

2

0.1u_0201_10V6K

+3VALW_PCH

1

CC143

2

1U_0402_6.3V6K

1

CC146

2

VCCRTC

1

CC1242

2

1U_0402_6.3V6K

0.1u_0201_10V6K

1

CC164

2

@

1U_0402_6.3V6K

+1.8VALW

+1.0VALW

+1.0VALW

+1.0VALW

+VCCCLK4

+VCCCLK5

1

CC158

2

CC153

VCCMPHYON_1P0_L1

11mA

+1.0VALW

Near AB19

1U_0402_6.3V6K

0.696A

1

CC141

2

@

1U_0402_6.3V6K

33mA

1

2

AB19
AB20

P18

AF18
AF19

V20
V21

AL1

K17

N15
N16
N17
P15
P16

K15

L15

V15

AB17

Y18

AD17
AD18

AJ17

AJ19

AJ16

AF20
AF21

T19
T20

AJ21

AK20

N18

CC169

1U_0402_6.3V6K

UC1O

VCCPRIM_1 P0_AB19
VCCPRIM_1 P0_AB20
VCCPRIM_1 P0_P18

VCCPRIM_CO RE_AF18
VCCPRIM_CO RE_AF19
VCCPRIM_CO RE_V20
VCCPRIM_CO RE_V21

DCPDSW_ 1P0

VCCMPHYAON_ 1P0_K17

L1

VCCMPHYAON_ 1P0_L1

VCCMPHYGT_1P 0_N15
VCCMPHYGT_1P 0_N16
VCCMPHYGT_1P 0_N17
VCCMPHYGT_1P 0_P15
VCCMPHYGT_1P 0_P16

VCCAMPHYPL L_1P0_K1 5
VCCAMPHYPL L_1P0_L1 5

VCCAPLL_ 1P0

VCCPRIM_1 P0_AB17
VCCPRIM_1 P0_Y18

VCCDSW_ 3P3_AD17
VCCDSW_ 3P3_AD18
VCCDSW_ 3P3_AJ17

VCCHDA

VCCSPI

VCCSRAM_1 P0_AF20
VCCSRAM_1 P0_AF21
VCCSRAM_1 P0_T19
VCCSRAM_1 P0_T20

VCCPRIM_3 P3_AJ21

VCCPRIM_1 P0_AK20

VCCAPLLE BB

SKYLAKE-U_BGA1356

REV = 1
@

SKL_ULT

CPU POWER 4 OF 4

?

1 OF 20

VCCPGPPA
VCCPGPPB
VCCPGPPC
VCCPGPPD
VCCPGPPE

VCCPGPPF

VCCPGPPG

VCCPRIM_3 P3_V19

VCCPRIM_1 P0_T1

VCCATS_1P 8

VCCRTCPRIM_3 P3

VCCRTC_AK19
VCCRTC_BB14

DCPRTC

VCCCLK1

VCCCLK2

VCCCLK3

VCCCLK4

VCCCLK5

VCCCLK6

GPP_B0/ CORE_VID0
GPP_B1/ CORE_VID1

+1.0VALW

2.574A22mA

1

2

1

CC145

2

+3VALW_PCH

0.1u_0201_10V6K

@

Near AF18

22U_0603_6.3V6-M

1U_0402_6.3V6K

0.118A

+3VALW

68mA

Near A18

1 2

CC151

1U_0402_6.3V6K

CC154

1U_0402_6.3V6K

1

C2084

2

@

Near K15

22mA

+1.0VALW

1

2

CD@

22U_0603_6.3V6-M

CC159

+1.0VALW

1

2

@

1U_0402_6.3V6K

RC1620 0_0402_5%@

1.5A

1

CC148

2

22U_0603_6.3V6-M

Near AF20

+3VALW_PCH

CC147

1U_0201_6.3V6-M

0.642A

+1.0VALW

+1.0VALW

C C

Near N15

+VCCAMPHY

+VCCAPLL_1P0

+1.0VALW

B B

88mA

1

1

C1096

2

2

@

22U_0603_6.3V6-M

1

1

C1097

2

2

0.1u_0201_10V6K

A A

Titl e

Titl e

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/08/20

2015/08/20

2015/08/20

LC Future Center Se cret Data

LC Future Center Se cret Data

LC Future Center Se cret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/08/20

2016/08/20

2016/08/20

Titl e

MCP (PCH PWR)

MCP (PCH PWR)

MCP (PCH PWR)

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

EG521

EG521

EG521

Tuesday, April 25, 2017

Tuesday, April 25, 2017

Tuesday, April 25, 2017

1

14 60

14 60

14 60

0.2

0.2

0.2

Vinafix.com

5

?

SKL_U LT

D D

C C

B B

UC1P

A5

VSS_A5

A67

VSS_A67

A70

VSS_A70

AA2

VSS_AA2

AA4

VSS_AA4

AA65

VSS_AA65

AA68

VSS_AA68

AB15

VSS_AB15

AB16

VSS_AB16

AB18

VSS_AB18

AB21

VSS_AB21

AB8

VSS_AB8

AD13

VSS_AD13

AD16

VSS_AD16

AD19

VSS_AD19

AD20

VSS_AD20

AD21

VSS_AD21

AD62

VSS_AD62

AD8

VSS_AD8

AE64

VSS_AE64

AE65

VSS_AE65

AE66

VSS_AE66

AE67

VSS_AE67

AE68

VSS_AE68

AE69

VSS_AE69

AF1

VSS_AF1

AF10

VSS_AF10

AF15

VSS_AF15

AF17

VSS_AF17

AF2

VSS_AF2

AF4

VSS_AF4

AF63

VSS_AF63

AG16

VSS_AG16

AG17

VSS_AG17

AG18

VSS_AG18

AG19

VSS_AG19

AG20

VSS_AG20

AG21

VSS_AG21

AG71

VSS_AG71

AH13

VSS_AH13

AH6

VSS_AH6

AH63

VSS_AH63

AH64

VSS_AH64

AH67

VSS_AH67

AJ15

VSS_AJ15

AJ18

VSS_AJ18

AJ20

VSS_AJ20

AJ4

VSS_AJ4

AK11

VSS_AK11

AK16

VSS_AK16

AK18

VSS_AK18

AK21

VSS_AK21

AK22

VSS_AK22

AK27

VSS_AK27

AK63

VSS_AK63

AK68

VSS_AK68

AK69

VSS_AK69

AK8

VSS_AK8

AL2

VSS_AL2

AL28

VSS_AL28

AL32

VSS_AL32

AL35

VSS_AL35

AL38

VSS_AL38

AL4

VSS_AL4

AL45

VSS_AL45

AL48

VSS_AL48

AL52

VSS_AL52

AL55

VSS_AL55

AL58

VSS_AL58

AL64

VSS_AL64

SKYLAKE-U_BGA1356

REV = 1
@

GND 1 OF 3

1 OF 20

VSS_AL65

VSS_AL66
VSS_AM13
VSS_AM21
VSS_AM25
VSS_AM27
VSS_AM43
VSS_AM45
VSS_AM46
VSS_AM55
VSS_AM60
VSS_AM61
VSS_AM68
VSS_AM71

VSS_AM8
VSS_AN20
VSS_AN23
VSS_AN28
VSS_AN30
VSS_AN32
VSS_AN33
VSS_AN35
VSS_AN37
VSS_AN38
VSS_AN40
VSS_AN42
VSS_AN58
VSS_AN63
VSS_AP10
VSS_AP18
VSS_AP20
VSS_AP23
VSS_AP28
VSS_AP32
VSS_AP35
VSS_AP38
VSS_AP42
VSS_AP58
VSS_AP63
VSS_AP68
VSS_AP70
VSS_AR11
VSS_AR15
VSS_AR16
VSS_AR20
VSS_AR23
VSS_AR28
VSS_AR35
VSS_AR42
VSS_AR43
VSS_AR45
VSS_AR46
VSS_AR48

VSS_AR5
VSS_AR50
VSS_AR52
VSS_AR53
VSS_AR55
VSS_AR58
VSS_AR63

VSS_AR8

VSS_AT2
VSS_AT20
VSS_AT23
VSS_AT28
VSS_AT35

VSS_AT4
VSS_AT42
VSS_AT56
VSS_AT58

4

AL65
AL66
AM13
AM21
AM25
AM27
AM43
AM45
AM46
AM55
AM60
AM61
AM68
AM71
AM8
AN20
AN23
AN28
AN30
AN32
AN33
AN35
AN37
AN38
AN40
AN42
AN58
AN63
AP10
AP18
AP20
AP23
AP28
AP32
AP35
AP38
AP42
AP58
AP63
AP68
AP70
AR11
AR15
AR16
AR20
AR23
AR28
AR35
AR42
AR43
AR45
AR46
AR48
AR5
AR50
AR52
AR53
AR55
AR58
AR63
AR8
AT2
AT20
AT23
AT28
AT35
AT4
AT42
AT56
AT58

?

UC1Q

AT63

VSS_AT63

AT68

VSS_AT68

AT71

VSS_AT71

AU10

VSS_AU10

AU15

VSS_AU15

AU20

VSS_AU20

AU32

VSS_AU32

AU38

VSS_AU38

AV1

VSS_AV1

AV68

VSS_AV68

AV69

VSS_AV69

AV70

VSS_AV70

AV71

VSS_AV71

AW10

VSS_AW10

AW12

VSS_AW12

AW14

VSS_AW14

AW16

VSS_AW16

AW18

VSS_AW18

AW21

VSS_AW21

AW23

VSS_AW23

AW26

VSS_AW26

AW28

VSS_AW28

AW30

VSS_AW30

AW32

VSS_AW32

AW34

VSS_AW34

AW36

VSS_AW36

AW38

VSS_AW38

AW41

VSS_AW41

AW43

VSS_AW43

AW45

VSS_AW45

AW47

VSS_AW47

AW49

VSS_AW49

AW51

VSS_AW51

AW53

VSS_AW53

AW55

VSS_AW55

AW57

VSS_AW57

AW6

VSS_AW6

AW60

VSS_AW60

AW62

VSS_AW62

AW64

VSS_AW64

AW66

VSS_AW66

AW8

VSS_AW8

AY66

VSS_AY66

B10

VSS_B10

B14

VSS_B14

B18

VSS_B18

B22

VSS_B22

B30

VSS_B30

B34

VSS_B34

B39

VSS_B39

B44

VSS_B44

B48

VSS_B48

B53

VSS_B53

B58

VSS_B58

B62

VSS_B62

B66

VSS_B66

B71

VSS_B71

BA1

VSS_BA1

BA10

VSS_BA10

BA14

VSS_BA14

BA18

VSS_BA18

BA2

VSS_BA2

BA23

VSS_BA23

BA28

VSS_BA28

BA32

VSS_BA32

BA36

VSS_BA36

F68

VSS_F68

BA45

VSS_BA45

SKYLAKE-U_BGA1356

REV = 1
@

3

SKL_U LT

GND 2 OF 3

?

1 OF 20

VSS_BA49
VSS_BA53
VSS_BA57

VSS_BA6
VSS_BA62
VSS_BA66
VSS_BA71
VSS_BB18
VSS_BB26
VSS_BB30
VSS_BB34
VSS_BB38
VSS_BB43
VSS_BB55

VSS_BB6
VSS_BB60
VSS_BB64
VSS_BB67
VSS_BB70

VSS_C1

VSS_C25

VSS_C5
VSS_D10
VSS_D11
VSS_D14
VSS_D18
VSS_D22
VSS_D25
VSS_D26
VSS_D30
VSS_D34
VSS_D39
VSS_D44
VSS_D45
VSS_D47
VSS_D48
VSS_D53
VSS_D58

VSS_D6
VSS_D62
VSS_D66
VSS_D69
VSS_E11
VSS_E15
VSS_E18
VSS_E21
VSS_E46
VSS_E50
VSS_E53
VSS_E56

VSS_E6
VSS_E65
VSS_E71

VSS_F1
VSS_F13

VSS_F2
VSS_F22
VSS_F23
VSS_F27
VSS_F28
VSS_F32
VSS_F33
VSS_F35
VSS_F37
VSS_F38

VSS_F4
VSS_F40
VSS_F42

VSS_BA41

2

BA49
BA53
BA57
BA6
BA62
BA66
BA71
BB18
BB26
BB30
BB34
BB38
BB43
BB55
BB6
BB60
BB64
BB67
BB70
C1
C25
C5
D10
D11
D14
D18
D22
D25
D26
D30
D34
D39
D44
D45
D47
D48
D53
D58
D6
D62
D66
D69
E11
E15
E18
E21
E46
E50
E53
E56
E6
E65
E71
F1
F13
F2
F22
F23
F27
F28
F32
F33
F35
F37
F38
F4
F40
F42
BA41

?

F8

VSS_F8

G10

VSS_G10

G22

VSS_G22

G43

VSS_G43

G45

VSS_G45

G48

VSS_G48

G5

VSS_G5

G52

VSS_G52

G55

VSS_G55

G58

VSS_G58

G6

VSS_G6

G60

VSS_G60

G63

VSS_G63

G66

VSS_G66

H15

VSS_H15

H18

VSS_H18

H71

VSS_H71

J11

VSS_J11

J13

VSS_J13

J25

VSS_J25

J28

VSS_J28

J32

VSS_J32

J35

VSS_J35

J38

VSS_J38

J42

VSS_J42

J8

VSS_J8

K16

VSS_K16

K18

VSS_K18

K22

VSS_K22

K61

VSS_K61

K63

VSS_K63

K64

VSS_K64

K65

VSS_K65

K66

VSS_K66

K67

VSS_K67

K68

VSS_K68

K70

VSS_K70

K71

VSS_K71

L11

VSS_L11

L16

VSS_L16

L17

VSS_L17

SKYLAKE-U_BGA1356

REV = 1
@

SKL_U LT

UC1R

GND 3 OF 3

?

1 OF 20

VSS_L18

VSS_L2

VSS_L20

VSS_L4

VSS_L8
VSS_N10
VSS_N13
VSS_N19
VSS_N21

VSS_N6
VSS_N65
VSS_N68
VSS_P17
VSS_P19
VSS_P20
VSS_P21
VSS_R13

VSS_R6
VSS_T15
VSS_T17
VSS_T18

VSS_T2
VSS_T21

VSS_T4
VSS_U10
VSS_U63
VSS_U64
VSS_U66
VSS_U67
VSS_U69
VSS_U70
VSS_V16
VSS_V17
VSS_V18

VSS_W13

VSS_W6

VSS_W9
VSS_Y17
VSS_Y19
VSS_Y20
VSS_Y21

L18
L2
L20
L4
L8
N10
N13
N19
N21
N6
N65
N68
P17
P19
P20
P21
R13
R6
T15
T17
T18
T2
T21
T4
U10
U63
U64
U66
U67
U69
U70
V16
V17
V18
W13
W6
W9
Y17
Y19
Y20
Y21

?

1

A A

Title

Title

Security Cl assification

Security Cl assification

Security Cl assification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENT ER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENT ER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENT ER.

3

2015/08/20

2015/08/20

2015/08/20

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/08/20

2016/08/20

2016/08/20

Title

MCP (VSS)

MCP (VSS)

MCP (VSS)

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Tuesday, April 25, 2017

Tuesday, April 25, 2017

Tuesday, April 25, 2017

EG521

EG521

EG521

15 60

15 60

1

15 60

0.2

0.2

0.2

Vinafix.com

5

CPU_CFG0

*

CPU_CFG1

1

CPU_CFG2

1

XDP_CPU_CFG3

1

CPU_CFG4
CPU_CFG5

1

CPU_CFG6

1

CPU_CFG7

1

CPU_CFG8

1

CPU_CFG9

1

CPU_CFG10

1

CPU_CFG11

1

CPU_CFG12

1

CPU_CFG13

1

CPU_CFG14

1

CPU_CFG15

1

CPU_CFG16

1

CPU_CFG17

1

CPU_CFG18

1

CPU_CFG19

1

CFG_RCOMP

XDP_ITP_PMODE

1

1
1

Default
Value

1

D D

RC1618
1K_0402_5%

@

1 2

C C

B B

RC106
1K_0402_5%

1 2

RC162

49.9_0402_1%

1 2

TC142PAD @
TC143PAD @
TC144PAD @

TC146PAD @
TC147PAD @
TC148PAD @
TC153PAD @
TC150PAD @
TC151PAD @
TC152PAD @
TC157PAD @
TC154PAD @
TC155PAD @
TC156PAD @

TC159PAD @
TC158PAD @

TC161PAD @
TC160PAD @

TC166PAD @

TC169PAD @
TC170PAD @

Pin Name Strap Description Configura tion

A A

CFG[4] Display Port

Presence strap

— 1 = eDP Disabled
— 0 = eDP Enabled

5

AL25
AL27

BA70
BA68

E68
B67
D65
D67
E70
C68
D68
C67

F71

G69

F70
G68
H70
G71
H69
G70

E63

F63

E66

F66

E60

E8

AY2
AY1

D1
D3

K46
K45

C71
B70

F60

A52

J71

J68

F65
G65

F61
E61

4

UC1S

RESERVED SIGNALS-1

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]

CFG[16]
CFG[17]

CFG[18]
CFG[19]

CFG_RCOMP

ITP_PMODE

RSVD_AY2
RSVD_AY1

RSVD_D1
RSVD_D3

RSVD_K46
RSVD_K45

RSVD_AL25
RSVD_AL27

RSVD_C71
RSVD_B70

RSVD_F60

RSVD_A52

RSVD_TP_BA70
RSVD_TP_BA68

RSVD_J71
RSVD_J68

VSS_F65
VSS_G65

RSVD_F61
RSVD_E61

SKYLAKE-U_BGA1356

REV = 1
@

4

SKL_ ULT

?

1 OF 20

RSVD_TP_BB68
RSVD_TP_BB69

RSVD_TP_AK13
RSVD_TP_AK12

RSVD_BB2
RSVD_BA3

RSVD_D5
RSVD_D4
RSVD_B2
RSVD_C2

RSVD_B3
RSVD_A3

RSVD_AW 1

RSVD_E1
RSVD_E2

RSVD_BA4
RSVD_BB4

RSVD_A4
RSVD_C4

RSVD_A69
RSVD_B69

RSVD_AY3

RSVD_D71
RSVD_C70

RSVD_C54
RSVD_D54

VSS_AY71

ZVM#

RSVD_TP_AW 71
RSVD_TP_AW 70

MSM#

PROC_SELECT#

3

BB68
BB69

AK13
AK12

BB2
BA3

AU5

TP5

AT5

TP6

D5
D4
B2
C2

B3
A3

AW1

E1
E2

BA4
BB4

A4
C4

BB5

TP4

A69
B69

RSVD_AY3

AY3

D71
C70

C54
D54

AY4

TP1

BB3

TP2

?

VSS_AY71

AY71
AR56

AW71
AW70

AP56

PROC_SELECT#

C64

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUT URE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUT URE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUT URE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

1

TC167 P AD@

1

TC177 P AD@

1

TC178 P AD@

1

TC168 P AD@

1 2

2015/08/20

2015/08/20

2015/08/20

3

+1.8VALW

Cannonlake@

RC1582 0_0402_5%
RC1583 0_0402_5%

Cannonlake@

XTAL24_IN

need to check with Intel

need to check with Intel

+VCCST_CPU

R22100K_0402_5% C annonlake@

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

RC241 0_0201_5%

Deciphered Date

Deciphered Date

Deciphered Date

2

?

SKL_ ULT

UC1T

SPAR E

RSVD_AW 69
RSVD_AW 68
RSVD_AU56
RSVD_AW 48
RSVD_C7
RSVD_U12
RSVD_U11
RSVD_H11

SKYLAKE-U_BGA1356

REV = 1
@

1 OF 20

YC2

GND12OSC2

OSC1

GND2

12

RC71 1M_0402_5%

1

24MHZ_6PF_7V24000032

12
12

1 2

XTAL24_OUT
RSVD_U12
RSVD_U11

CC12

3.3P_0402_50V8-C

AW69
AW68

AU56

AW48

C7
U12
U11
H11

1

2

need to use 38.4MHz (30ohm) for Cannonlake-u

RC107
0_0402_5%

1 2

RC108
0_0402_5%

1 2

Titl e

Titl e

Titl e

2016/08/20

2016/08/20

2016/08/20

2

MCP (CFG,RESERVED)

MCP (CFG,RESERVED)

MCP (CFG,RESERVED)

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date : Shee t o f

Date : Shee t o f

Date : Shee t o f

F6

RSVD_F6

E3

RSVD_E3

C11

RSVD_C11

B11

RSVD_B11

A11

RSVD_A11

D12

RSVD_D12

C12

RSVD_C12

F52

RSVD_F52

?

3

4

Tuesday, April 25, 2017

Tuesday, April 25, 2017

Tuesday, April 25, 2017

1

+VCCST_CPU

1 2

1

12

RC1619
150_0402_5%

@

XTAL24_IN

RSVD_F52

RC240 0_0201_5%

1

CC11

2.7P_0402_50V9-B

2

EG521

EG521

EG521

XTAL24_OUT

16 60

16 60

16 60

0.2

0.2

0.2

Vinafix.com

5

12

RD39

MD@

240_0402_1%

P3
P7
R3
N7
N3
P8
P2
R8
R2
R7
M3

T2

M7

T8

L2

M8

L8

K8
K7

K2

F3
G3
A7
B7

E2
E7

N2
N8

L3
L7

P9

M2

K3

T3

N9

P1

F1
H1
A2
D2
E3
A8
D8
E8
C9
H9

F9

12

RD43

MD@

240_0402_1%

UD1

P3

A0

P7

A1

R3

A2

N7

A3

N3

A4

P8

A5

P2

A6

R8

A7

R2

A8

R7

A9

M3

A10/AP

T2

A11

M7

A12/BC_N

T8

A13

L2

WE_N/A14

M8

CAS_N/A15

L8

RAS_N/A16

K8

CK_C

K7

CK_T

K2

CKE

F3

LDQS_C

G3

LDQS_T

A7

UDQS_C

B7

UDQS_T

E2

NF/UDM_N/UDBI_N

E7

NF/LDM_N/LDBI_N

N2

BA0

N8

BA1

L3

ACT_N

L7

CS_N

P9

ALERT_N

M2

BG0

K3

ODT

T3

PAR

N9

TEN

P1

RESET_N

F1

VSSQ1

H1

VSSQ2

A2

VSSQ3

D2

VSSQ4

E3

VSSQ5

A8

VSSQ6

D8

VSSQ7

E8

VSSQ8

C9

VSSQ9

H9

VSSQ10

F9

ZQ

MT40A512M16HA083EA_FBGA96

UD3

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC_N
A13

WE_N/A14
CAS_N/A15
RAS_N/A16

CK_C
CK_T

CKE

LDQS_C
LDQS_T
UDQS_C
UDQS_T

NF/UDM_N/UDBI_N
NF/LDM_N/LDBI_N

BA0
BA1

ACT_N
CS_N
ALERT_N

BG0

ODT

PAR

TEN

RESET_N

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

ZQ

MT40A512M16HA083EA_FBGA96

DDRA_MA0
DDRA_MA1
DDRA_MA2
DDRA_MA3
DDRA_MA4
DDRA_MA5
DDRA_MA6
DDRA_MA7
DDRA_MA8
DDRA_MA9
DDRA_MA10
DDRA_MA11
DDRA_MA12
DDRA_MA13

D D

C C

B B

A A

DDRA_MA14_WE#5
DDRA_MA15_CAS#5
DDRA_MA16_RAS#5

DDRA_CLK0#5
DDRA_CLK05

DDRA_CKE05

+1.2V +1.2V

1 2

RD65 0_0402_5%@

1 2

RD68 0_0402_5%@

DDRA_BS0#5
DDRA_BS1#5

DDRA_ACT#5
DDRA_CS0#5
DDRA_ALERT#5

DDRA_BG05

DDRA_ODT05

DDRA_PAR5

1 2

RD94 10K_0402_5%MD@

CPU_DRAMRST#6,18

+1.2V

1 2

RD87 0_0402_5%@

1 2

RD88 0_0402_5%@

1 2

RD96 10K_0402_5%MD@

DDRA_MA14_WE#
DDRA_MA15_CAS#
DDRA_MA16_RAS#

DDRA_CLK0#
DDRA_CLK0

DDRA_CKE0

DDRA_DQS#0
DDRA_DQS0
DDRA_DQS#1
DDRA_DQS1

DDRA_DM1
DDRA_DM0

DDRA_BS0#
DDRA_BS1#

DDRA_ACT#
DDRA_CS0#
DDRA_ALERT#

DDRA_BG0

DDRA_ODT0

DDRA_PAR

TEN_UD1 TEN_UD2

CPU_DRAMRST#

@

1

2

CD47

0.1u_0201_10V6K

DDRA_MA0
DDRA_MA1
DDRA_MA2
DDRA_MA3
DDRA_MA4
DDRA_MA5
DDRA_MA6
DDRA_MA7
DDRA_MA8
DDRA_MA9
DDRA_MA10
DDRA_MA11
DDRA_MA12
DDRA_MA13

DDRA_MA14_WE#
DDRA_MA15_CAS# DDRA_MA14_WE#
DDRA_MA16_RAS#

DDRA_CLK0#
DDRA_CLK0

DDRA_CKE0

DDRA_DQS#5
DDRA_DQS5
DDRA_DQS#4
DDRA_DQS4

DDRA_DM4
DDRA_DM5 DDRA_DM6

DDRA_BS0#
DDRA_BS1#

DDRA_ACT#
DDRA_CS0#
DDRA_ALERT#

DDRA_BG0

DDRA_ODT0

DDRA_PAR

TEN_UD3

CPU_DRAMRST#

@

1

2

0.1u_0201_10V6K

CD107

VDDQ10

VREFCA

VDD10

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VDDQ10

VREFCA

@

DDRA_DQ2

G2

DDRA_DQ3

DQ0

F7

DDRA_DQ6

DQ1

H3

DDRA_DQ1

DQ2

H7

DDRA_DQ7

DQ3

H2

DDRA_DQ0

DQ4

H8

DDRA_DQ4

DQ5

J3

DDRA_DQ5

DQ6

J7

DDRA_DQ11

DQ7

A3

DDRA_DQ8

DQ8

B8

DDRA_DQ14

DQ9

C3

DDRA_DQ13

DQ10

C7

DDRA_DQ15

DQ11

C2

DDRA_DQ12

DQ12

C8

DDRA_DQ10

DQ13

D3

DDRA_DQ9

DQ14

D7

DQ15

+1.2V

D1

VDD1

J1

VDD2

L1

VDD3

R1

VDD4

B3

VDD5

G7

VDD6

B9

VDD7

J9

VDD8

L9

VDD9

T9

VDD10

A1

VDDQ1

C1

VDDQ2

G1

VDDQ3

F2

VDDQ4

J2

VDDQ5

F8

VDDQ6

J8

VDDQ7

A9

VDDQ8

D9

VDDQ9

G9

B1

VPP1

R9

VPP2

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9

NC

@

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9

VPP1
VPP2

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9

NC

+VREF_CA_MD

M1

E1
K1
N1
T1
B2
G8
E9
K9
M9

T7

G2
F7
H3
H7
H2
H8
J3
J7
A3
B8
C3
C7
C2
C8
D3
D7

D1
J1
L1
R1
B3
G7
B9
J9
L9
T9

A1
C1
G1
F2
J2
F8
J8
A9
D9
G9

B1
R9

M1

E1
K1
N1
T1
B2
G8
E9
K9
M9

T7

DDRA_DQ47
DDRA_DQ41
DDRA_DQ43
DDRA_DQ40
DDRA_DQ46
DDRA_DQ44
DDRA_DQ42
DDRA_DQ45
DDRA_DQ34
DDRA_DQ37
DDRA_DQ35
DDRA_DQ32
DDRA_DQ39
DDRA_DQ33
DDRA_DQ38
DDRA_DQ36

+1.2V

+VREF_CA_MD

1

MD@

MD@

2

.047U_0201_6.3V6K

CD113

1

MD@

MD@

2

.047U_0201_6.3V6K

CD115

4

DDRA_MA0

P3

DDRA_MA1

P7

DDRA_MA2

R3

DDRA_MA3

N7

DDRA_MA4

N3

DDRA_MA5

P8

DDRA_MA6

P2

DDRA_MA7

R8

DDRA_MA8

R2

DDRA_MA9

R7

DDRA_MA10

M3

DDRA_MA11
DDRA_MA12

M7

DDRA_MA13

DDRA_MA14_WE#
DDRA_MA15_CAS#

M8

DDRA_MA16_RAS#

DDRA_CLK0#

K8

DDRA_CLK0

K7

DDRA_CKE0

K2

DDRA_DQS#2
DDRA_DQS2

G3

DDRA_DQS#3
DDRA_DQS3

B7

1 2

RD66 0_0402_5%@

1 2

RD69 0_0402_5%@

+2.5V_DDR

1

1

MD@

1

2

CD120

1

2

0.1u_0201_10V6K

CD149

CD@

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

CD121

0.1u_0201_10V6K

CD123

+2.5V_DDR

1

1

CD@

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

CD@

CD151

CD150

1 2

RD95 10K_0402_5%MD@

+1.2V

1 2

RD89 0_0402_5%@

1 2

RD90 0_0402_5%@

1 2

RD97 10K_0402_5%MD@

DDRA_DM3

E2

DDRA_DM2

E7

DDRA_BS0#

N2

DDRA_BS1#

N8

DDRA_ACT#
DDRA_CS0#
DDRA_ALERT#

P9

DDRA_BG0

M2

DDRA_ODT0

K3

DDRA_PAR

N9

CPU_DRAMRST#

12

MD@

P3
P7
R3
N7
N3
P8
P2
R8
R2
R7
M3
T2
M7
T8

L2
M8
L8

K8
K7

K2

F3
G3
A7
B7

E2
E7

N2
N8

L3
L7
P9

M2

K3

T3

N9

P1

F1
H1
A2
D2
E3
A8
D8
E8
C9
H9

F9

12

RD44

MD@

240_0402_1%

P1

H1

D2
E3

D8
E8
C9
H9

RD40
240_0402_1%

UD4

MT40A512M16HA083EA_FBGA96

@

1

2

CD48

0.1u_0201_10V6K

DDRA_MA0
DDRA_MA1
DDRA_MA2
DDRA_MA3
DDRA_MA4
DDRA_MA5
DDRA_MA6
DDRA_MA7
DDRA_MA8
DDRA_MA9
DDRA_MA10
DDRA_MA11
DDRA_MA12
DDRA_MA13

DDRA_MA15_CAS#
DDRA_MA16_RAS#

DDRA_CLK0#
DDRA_CLK0

DDRA_CKE0

DDRA_DQS#7
DDRA_DQS7
DDRA_DQS#6
DDRA_DQS6

DDRA_DM7

DDRA_BS0#
DDRA_BS1#

DDRA_ACT#
DDRA_CS0#
DDRA_ALERT#

DDRA_BG0

DDRA_ODT0

DDRA_PAR

TEN_UD4

CPU_DRAMRST#

@

1

2

0.1u_0201_10V6K

CD108

UD2

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP

T2

A11
A12/BC_N

T8

A13

L2

WE_N/A14
CAS_N/A15

L8

RAS_N/A16

CK_C
CK_T

CKE

F3

LDQS_C
LDQS_T

A7

UDQS_C
UDQS_T

NF/UDM_N/UDBI_N
NF/LDM_N/LDBI_N

BA0
BA1

L3

ACT_N

L7

CS_N
ALERT_N

BG0

ODT

T3

PAR

TEN

RESET_N

F1

VSSQ1
VSSQ2

A2

VSSQ3
VSSQ4
VSSQ5

A8

VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

F9

ZQ

MT40A512M16HA083EA_FBGA96

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC_N
A13

WE_N/A14
CAS_N/A15
RAS_N/A16

CK_C
CK_T

CKE

LDQS_C
LDQS_T
UDQS_C
UDQS_T

NF/UDM_N/UDBI_N
NF/LDM_N/LDBI_N

BA0
BA1

ACT_N
CS_N
ALERT_N

BG0

ODT

PAR

TEN

RESET_N

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

ZQ

VDD10

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VDDQ10

VREFCA

3

@

DDRA_DQ18

G2

DDRA_DQ19

DQ0

F7

DDRA_DQ22

DQ1

H3

DDRA_DQ21

DQ2

H7

DDRA_DQ23

DQ3

H2

DDRA_DQ17

DQ4

H8

DDRA_DQ16

DQ5

J3

DDRA_DQ20

DQ6

J7

DDRA_DQ30

DQ7

A3

DDRA_DQ28

DQ8

B8

DDRA_DQ26

DQ9

C3

DDRA_DQ25

DQ10

C7

DDRA_DQ31

DQ11

C2

DDRA_DQ24

DQ12

C8

DDRA_DQ27

DQ13

D3

DDRA_DQ29

DQ14

D7

DQ15

+1.2V

D1

VDD1

J1

VDD2

L1

VDD3

R1

VDD4

B3

VDD5

G7

VDD6

B9

VDD7

J9

VDD8

L9

VDD9

T9

VDD10

A1

VDDQ1

C1

VDDQ2

G1

VDDQ3

F2

VDDQ4

J2

VDDQ5

F8

VDDQ6

J8

VDDQ7

A9

VDDQ8

D9

VDDQ9

G9

VDDQ10

B1

VPP1

R9

VPP2

VREFCA

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9

NC

@

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9

VPP1
VPP2

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9

NC

+VREF_CA_MD

M1

E1
K1
N1
T1
B2
G8
E9
K9
M9

T7

G2
F7
H3
H7
H2
H8
J3
J7
A3
B8
C3
C7
C2
C8
D3
D7

D1
J1
L1
R1
B3
G7
B9
J9
L9
T9

A1
C1
G1
F2
J2
F8
J8
A9
D9
G9

B1
R9

M1

E1
K1
N1
T1
B2
G8
E9
K9
M9

T7

DDRA_DQ59
DDRA_DQ60
DDRA_DQ63
DDRA_DQ56
DDRA_DQ62
DDRA_DQ61
DDRA_DQ58
DDRA_DQ57
DDRA_DQ54
DDRA_DQ53
DDRA_DQ51
DDRA_DQ49
DDRA_DQ50
DDRA_DQ52
DDRA_DQ55
DDRA_DQ48

+1.2V

+VREF_CA_MD

1

1

MD@

MD@

2

2

0.1u_0201_10V6K

.047U_0201_6.3V6K

CD114

CD122

1

1

MD@

MD@

2

2

0.1u_0201_10V6K

.047U_0201_6.3V6K

CD153

CD116

DDR_SA_VREFCA5

CD111

0.022U_0201_6.3V6-K

24.9_0402_1% MD@

+2.5V_DDR

1

1

MD@

MD@

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

CD124

CD125

+2.5V_DDR

1

1

MD@

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

CD@

CD154

CD155

2

+1.2V

1

12

MD@

MD@

RD45

CD119

2

1 2

MD@

2.7_0402_1%

(1uF_0402_6.3V) *16
Place 4 near each DRAM

1

1

MD@

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

CD@

CD127

CD126

(1OuF_0603_6.3V) *5
Place around the DRAMs

1

1

CD@

2

2

10U_0603_6.3V6M

CD143

CD142

(1OuF_0603_6.3V) *3
Place around the DRAMs

1

1

MD@

2

2

10U_0603_6.3V6M

CD152

CD156

(1uF_0402_6.3V) *8
Place 2 near each DRAM

1

1

MD@

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

CD159

CD158

12

1

2

CD128

10U_0603_6.3V6M

10U_0603_6.3V6M

1

2

CD@

CD160

1.8K_0402_1%

RD47

1.8K_0402_1%MD@

1

MD@

2

1U_0402_6.3V6K

CD129

1

MD@

2

CD144

1

CD@

2

CD147

1

CD@

2

1U_0402_6.3V6K

CD161

+VREF_CA_MD

1

MD@

CD112

0.1u_0201_10V6K

2

1

1

1

CD@

CD@

2

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

CD@

CD131

CD132

CD130

1

1

MD@

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

CD@

1U_0402_6.3V6K

10U_0603_6.3V6M

CD@

CD145

CD146

1

1

1

MD@

MD@

2

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

CD@

CD162

CD163

CD164

0.1u_0201_10V6K

RD46

1

MD@

2

12

RD48

+1.2V

MD@

+1.2V

CD@

+2.5V_DDR

MD@

+0.6VS

MD@

1

1

MD@

MD@

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

CD134

CD133

(1OuF_0603_6.3V) *2
Place around the DRAMs

1

1

MD@

2

2

1U_0402_6.3V6K

10U_0603_6.3V6M

CD@

CD165

CD166

DDRA_DQ[0..63]

DDRA_DQS#[0..7]

DDRA_DQS[0..7]

DDRA_MA[0..13]

1

MD@

2

1U_0402_6.3V6K

CD135

+1.2V

1

2

+2.5V_DDR

1

2

1

2

10U_0603_6.3V6M

CD167

1

MD@

2

1U_0402_6.3V6K

CD136

CD109
22P_0402_50V8-J

RF@

CD157
22P_0402_50V8-J

RF@

DDRA_CLK0#
DDRA_CLK0

DDRA_CS0#
DDRA_ODT0

DDRA_CKE0

DDRA_MA0
DDRA_MA1
DDRA_MA2
DDRA_MA3

DDRA_MA4
DDRA_MA5
DDRA_MA6
DDRA_MA7

DDRA_MA8
DDRA_MA9
DDRA_MA10
DDRA_MA11

DDRA_MA12
DDRA_MA13
DDRA_MA14_WE#
DDRA_MA15_CAS#

DDRA_MA16_RAS#
DDRA_BG0
DDRA_BS0#
DDRA_BS1#

DDRA_ACT#
DDRA_PAR

DDRA_ALERT#

1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

CD@

CD137

DDRA_DQ[0..63] 5

DDRA_DQS#[0..7] 5

DDRA_DQS[0..7] 5

DDRA_MA[0..13] 5

MD@

RD49 36_0402_1%MD@
RD50 36_0402_1%MD@

RD51 34.8_0402_1%MD@
RD52 34.8_0402_1%MD@

RD53 34.8_0402_1%MD@

RD54 34.8_0402_1%MD@
RD55 34.8_0402_1%MD@
RD56 34.8_0402_1%MD@
RD57 34.8_0402_1%MD@

RD58 34.8_0402_1%MD@
RD59 34.8_0402_1%MD@
RD60 34.8_0402_1%MD@
RD61 34.8_0402_1%MD@

RD62 34.8_0402_1%MD@
RD63 34.8_0402_1%MD@
RD64 34.8_0402_1%MD@
RD67 34.8_0402_1%MD@

RD70 34.8_0402_1%MD@
RD71 34.8_0402_1%MD@
RD72 34.8_0402_1%MD@
RD73 34.8_0402_1%MD@

RD74 34.8_0402_1%MD@
RD75 34.8_0402_1%MD@
RD76 34.8_0402_1%MD@
RD77 34.8_0402_1%MD@

RD78 34.8_0402_1%MD@
RD79 34.8_0402_1%MD@

RD86 49.9_0402_1%MD@

1

2

1U_0402_6.3V6K

CD138

1

CD110
22P_0402_50V8-J

RF@

2

1

CD148
22P_0402_50V8-J

RF@

2

+0.6VS

1 2
1 2

1 2
1 2

1 2

1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2

1 2
1 2

1 2

1

2

1U_0402_6.3V6K

CD@

CD139

1

CD168
22P_0402_50V8-J

RF@

2

1

+0.6VS

+1.2V

1

1

MD@

MD@

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

CD141

CD140

1

CD169
22P_0402_50V8-J

RF@

2

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

2

2016/12/14

2016/12/14

2016/12/14

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2017/12/13

2017/12/13

2017/12/13

Title

DDR4 Memory Down

DDR4 Memory Down

DDR4 Memory Down

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Tuesday, April 25, 2017

Tuesday, April 25, 2017

Tuesday, April 25, 2017

1

EG523

EG523

EG523

17 60

17 60

17 60

0.2

0.2

0.2

Vinafix.com

5

DDR4 SO-DIMM

+1.2V +1.2V +1.2V+1.2V+1.2V +1.2V +1.2V +1.2V

DDRB_DQ12

DDRB_DQ13

DDRB_DQS#1
DDRB_DQS1

12

RD93
240_0402_1%

DDRB_DQ10

DDRB_DQ14

DDRB_DQ0

DDRB_DQ6

DDRB_DQ7

DDRB_DQ3

DDRB_DQ18

DDRB_DQ16

DDRB_DQS#2
DDRB_DQS2

DDRB_DQ22

DDRB_DQ23

DDRB_DQ27

DDRB_DQ28

DDRB_DQ25

DDRB_DQ30

DDRB_DQS#8
DDRB_DQS8

DDRB_CKE0

DDRB_BG1
DDRB_BG0

DDRB_MA12
DDRB_MA9

DDRB_MA8
DDRB_MA6

1

CD13

0.022U_0201_6.3V6-K

2

12

RD6

24.9_0402_1%

0.1u_0201_10V6K

D D

+1.2V

12

RD92

240_0402_1%

C C

DDRB_CKE06

DDRB_BG16
DDRB_BG06

DDRB_MA126
DDRB_MA96

DDRB_MA86
DDRB_MA66

B B

DDR_SB_VREFCA5

RD4

101
103
105
107
109
111
113
115
117
119
121
123
125
127
129

CD117

1 2

2_0402_5%

1
3
5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99

1

2

JDDR1A

VSS_1
DQ5
VSS_3
DQ1
VSS_5
DQS0_C

DM0_n/DBIO_n/NC
DQS0_t
VSS_8
DQ7
VSS_10
DQ3
VSS_12
DQ13
VSS_14
DQ9
VSS_16
DM1_n/DBl1_n/NC
VSS_17
DQ15
VSS_19
DQ10
VSS_21
DQ21
VSS_23
DQ17
VSS_25
DQS2_c
DQS2_t
VSS_28
DQ23
VSS_30
DQ19
VSS_32
DQ29
VSS_34
DQ25
VSS_36
DM3_n/DBl3_n/NC
VSS_37
DQ30
VSS_39
DQ26
VSS_41
CB5/NC
VSS_43
CB1/NC
VSS_45
DQS8_c
DQS8_t
VSS_48
CB2/NC
VSS_50
CB3/NC
VSS_52
CKE0
VDD_1
BG1
BG0
VDD_3
A12
A9
VDD_5
A8
A6
VDD_7

ARGOS_D4AS0-26001-1P60

ME@

DM2_n/DBl2_n/NC

DM8_n/DBI8_n/NC

+1.2V

12

RD3
1K_0402_1%

12

RD5
1K_0402_1%

VSS_11

VSS_13

VSS_15

DQS1_c

DQS1_t
VSS_18

VSS_20

VSS_22

VSS_24

VSS_26

VSS_27

VSS_29

VSS_31

VSS_33

VSS_35

DQS3_c

DQS3_t
VSS_38

VSS_40

VSS_42
CB4/NC
VSS_44
CB0/NC
VSS_46

VSS_47
CB6/NC
VSS_49
CB7/NC
VSS_51

RESET_n

ALERT_n

VSS_2

VSS_4

VSS_6

VSS_7

VSS_9

DQ12

DQ14

DQ11

DQ20

DQ16

DQ22

DQ18

DQ28

DQ24

DQ31

DQ27

CKE1
VDD_2
ACT_n

VDD_4

VDD_6

VDD_8

DQ4

DQ0

DQ6

DQ2

DQ8

A11

A7

A5
A4

4

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130

Note:
VREF trace width:20 mils at least

Spacing:20mils to other signal/planes
Place near DIMM scoket

+VREF_CA_DIMM

1

CD14

0.1u_0201_10V6K

2

DDRB_DQ9

DDRB_DQ8

DDRB_DQ11

DDRB_DQ15

DDRB_DQ5

DDRB_DQ4

DDRB_DQS#0
DDRB_DQS0

DDRB_DQ1

DDRB_DQ2

DDRB_DQ20

DDRB_DQ21

DDRB_DQ17

DDRB_DQ19

DDRB_DQ24

DDRB_DQ29

DDRB_DQS#3
DDRB_DQS3

DDRB_DQ26

DDRB_DQ31

CPU_DRAMRST#
DDRB_CKE1

DDRB_ACT#
DDRB_ALERT#

DDRB_MA11
DDRB_MA7

DDRB_MA5
DDRB_MA4

DDRB_DQ[0..63]

DDRB_DQS#[0..7]

DDRB_DQS[0..7]

DDRB_CKE1 6

DDRB_ACT# 6
DDRB_ALERT# 6

DDRB_MA11 6
DDRB_MA7 6

DDRB_MA5 6
DDRB_MA4 6

1

CD3

0.1u_0201_10V6K

@

2

+1.2V

3

DDRB_DQ[0..63] 6

DDRB_DQS#[0..7] 6

DDRB_DQS[0..7] 6

CPU_DRAMRST# 6,17

RD1

+3VS

RD2

+2.5V_DDR

2

1

2

CD6

1U_0402_6.3V6K

CD118

JDDR1B

131

A3

133

A1

135

VDD_9

137

CK0_t

139

CK0_c

141

VDD_11

143

Parity

145

BA1

147

VDD_13

149

CS0_n

151

WE_n/A14

153

VDD_15

155

ODT0

157

CS1_n

159

VDD_17

161

ODT1

163

VDD_19

165

C1/CS3_n/NC

167

VSS_53

169

DQ37

171

VSS_55

173

DQ33

175

VSS_57

177

DQS4_c

179

DQS4_t

181

VSS_60

183

DQ38

185

VSS_62

187

DQ34

189

VSS_64

191

DQ44

193

VSS_66

195

DQ40

197

VSS_68

199

DM5_n/DBl5_n/NC

201

VSS_69

203

DQ46

205

VSS_71

207

DQ42

209

VSS_73

211

DQ52

213

VSS_75

215

DQ49

217

VSS_77

219

DQS6_c

221

DQS6_t

223

VSS_80

225

DQ55

227

VSS_82

229

DQ51

231

VSS_84

233

DQ61

235

VSS_86

237

DQ56

239

VSS_88

241

DM7_n/DBl7_n/NC

243

VSS_89

245

DQ62

247

VSS_91

249

DQ58

251

VSS_93

253

SCL

255

VDDSPD

257

VPP_1

259

VPP_2

261

GND_1

ARGOS_D4AS0-26001-1P60

ME@

@

1

1

2

2

1U_0402_6.3V6K

10U_0603_6.3V6M

CD7

EVENT_n

VDD_10

CK1_t

CK1_c

VDD_12

A10/AP

VDD_14

RAS_n/A16

VDD_16

CAS_n/A15

VDD_18

C0/CS2_n/NC

VREFCA

VSS_54

DQ36

VSS_56

DQ32

VSS_58

DM4_n/DBl4_n/NC

VSS_59

DQ39

VSS_61

DQ35

VSS_63

DQ45

VSS_65

DQ41

VSS_67

DQS5_c

DQS5_t
VSS_70

DQ47

VSS_72

DQ43

VSS_74

DQ53

VSS_76

DQ48

VSS_78

DM6_n/DBl6_n/NC

VSS_79

DQ54

VSS_81

DQ50

VSS_83

DQ60

VSS_85

DQ57

VSS_87

DQS7_c

DQS7_t
VSS_90

DQ63

VSS_92

DQ59

VSS_94

GND_2

1

2

10U_0603_6.3V6M

CD8

CD@

132

A2

134
136
138
140
142
144

A0

146
148
150

BA0

152
154
156
158

A13

160
162
164
166

SA2

168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
210
212
214
216
218
220
222
224
226
228
230
232
234
236
238
240
242
244
246
248
250
252
254

SDA

256

SA0

258

Vtt

260

SA1

262

+2.5V_DDR+0.6VS

CD@

DDRB_MA2
DDRB_EVENT#

DDRB_CLK1
DDRB_CLK1#

DDRB_MA0

DDRB_MA10

DDRB_BS0#
DDRB_MA16_RAS#

DDRB_MA15_CAS#
DDRB_MA13

+VREF_CA_DIMM
DDRB_SA2

DDRB_DQ36

DDRB_DQ37

DDRB_DQ34

DDRB_DQ35

DDRB_DQ45

DDRB_DQ44

DDRB_DQS#5
DDRB_DQS5

DDRB_DQ46

DDRB_DQ42

DDRB_DQ52

DDRB_DQ49

DDRB_DQ55

DDRB_DQ51

DDRB_DQ56

DDRB_DQ61

DDRB_DQS#7
DDRB_DQS7

DDRB_DQ62

DDRB_DQ63

SMB_DATA_S3
DDRB_SA0

DDRB_SA1

1

1

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

CD9

CD10

CD11

CD@

1

2

1

CD5

0.1u_0201_10V6K

2

DDRB_MA3
DDRB_MA1

DDRB_CLK0
DDRB_CLK0#

DDRB_PAR

DDRB_BS1#

DDRB_CS0#
DDRB_MA14_WE#

DDRB_ODT0
DDRB_CS1#

DDRB_ODT1

DDRB_DQ32

DDRB_DQ33

DDRB_DQS#4
DDRB_DQS4

DDRB_DQ39

DDRB_DQ38

DDRB_DQ41

DDRB_DQ40

DDRB_DQ47

DDRB_DQ43

DDRB_DQ53

DDRB_DQ48

DDRB_DQS#6
DDRB_DQS6

DDRB_DQ54

DDRB_DQ50

DDRB_DQ60

DDRB_DQ57

DDRB_DQ59

DDRB_DQ58

SMB_CLK_S3
+VDD_SPD

+VPP

DDRB_MA36
DDRB_MA16

DDRB_CLK06
DDRB_CLK0#6

DDRB_PAR6

DDRB_BS1#6

DDRB_CS0#6
DDRB_MA14_WE#6

DDRB_ODT06
DDRB_CS1#6

DDRB_ODT16

SMB_CLK_S37, 40 SMB_DATA_S3 7,40

1 2

0_0603_5%

CD4

2.2U_0402_6.3V6M

1 2

0_0603_5%

Layout Note:
Place near DIMM

1

+1.2V

12

RD91

240_0402_1%

@

DDRB_MA2 6

DDRB_CLK1 6
DDRB_CLK1# 6

DDRB_MA0 6

DDRB_MA10 6

DDRB_BS0# 6
DDRB_MA16_RAS# 6

DDRB_MA15_CAS# 6
DDRB_MA13 6

@

1

1

2

2

0.1u_0201_10V6K
CD2

CD1

2.2U_0402_6.3V6M

+0.6VS

1

1

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

CD12

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

CD28

2016/08/20

2016/08/20

2016/08/20

1

2

1U_0402_6.3V6K

CD29

CD@

1

1

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

CD31

CD30

Title

Title

Title

DDR4 SO-DIMM

DDR4 SO-DIMM

DDR4 SO-DIMM

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

1

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

CD33

CD32

CD@

EG521

EG521

EG521

Tuesday, April 25, 2017

Tuesday, April 25, 2017

Tuesday, April 25, 2017

1

2

1U_0402_6.3V6K

CD34

0.2

0.2

18 60

18 60

18 60

1

0.2

1

1

2

2

10U_0603_6.3V6M

CD19

CD20

+3VS +3VS +3VS

12

RD7
0_0402_5%

@

A A

DDRB_SA0 DDRB_SA1 DDRB_SA2

12

RD10
0_0402_5%

12

RD8
0_0402_5%

12

RD11
0_0402_5%

@

12

RD9
0_0402_5%

@

12

RD12
0_0402_5%

SPD Address = 2H

5

4

CD@

+1.2V

1

1

EMC_NS@

EMC_NS@

2

2

4.7U_0402_6.3V6M

CD15

CD16

For EMC

Security Classification LC Future Center Secret Data

Security Classification LC Future Center Secret Data

Security Classification LC Future Center Secret Data

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PRO PRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PRO PRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PRO PRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

1

1

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

CD22

CD21

1

1

EMC_NS@

EMC_NS@

2

2

0.1u_0201_10V6K

4.7U_0402_6.3V6M
CD17

CD18

1

1

2

10U_0603_6.3V6M

10U_0603_6.3V6M

CD23

CD@

RF@

0.1u_0201_10V6K
CD36

1

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

CD24

CD25

RF@

1

1

2

2

33P_0402_50V8J

33P_0402_50V8J

CD37

Near JDDRL1

2015/08/20

2015/08/20

2015/08/20

3

Deciphered Date

Deciphered Date

Deciphered Date

1

1

2

2

10U_0603_6.3V6M

CD27

CD26

2