Lenovo E560,BE560 Schematic

A

1 1

B

C

D

E

LCFC Confidential

2 2

BE560 Rev1.0 Schematic

Intel SkyLake Processor with DDRIIIL + PCH-LP

AMD Litho XT GDDR5 2GB

3 3

2015-07-28 Rev1.0

4 4

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

C

2013/11/04

LC Future Center Secret Data

Deciphered Date

D

2014/09/07

Title

COVER PAGE

Size Document Number Re v

Custom

Wednesday, September 23, 2015

Date: Sheet o f

BE560

E

1 99

0.1

A

B

C

D

E

SkyLake

Memory BUS (DDRIII)

1 1

eDP Conn.

USB Port 7 DP Port 0

Page 38

USB 2.0 Port 7

DP Port0

1DPC (Interleaved)

1.35V DDRIIIL 1333/1600 MT/s

Intel

5V 480MHzUSB 2.0 Port 2 & 3

OneLink board

Page 60

Sub/B

2 2

USB 3.0 Port 3& 4

DP Repeater

On OneLin k board

HDMI Conn.

Page 37

VGA Conn

5V 5GT/s

DDI1 HDMI

DDI2 DP

MUX

DDI1

Page 42

DP to CRT

Converter

Page 41Page 40

DDI1

DDI2

SkyLake-U 2+2 type

Processor

BGA1356

40mm*24mm

+

PCIe Gen1 Port 3

USB 2.0 port 6

USB 3.0 , Port 1,2

USB 2.0 , port 1,2

PCIE Port 9-12

NGFF Card

5V 5GT/s

5V 480MHz

NGFF Card WLAN

PCIe Port 3 USB 2.0 port6

DDR3L-SO-DIMM X2

BANK 0, 1, 2, 3

UP TO 16G

20141227_S

Litho XT 2GB GDDR5

128M*32bit *4pcs

PCIe port 9-12

page 50

JUSB1

USB 3.0 Port 2 USB 2.0 Port 2

Page 45

Page 18~19

USB Left

JUSB2

USB 3.0 Port 1 USB 2.0 Port 1 TPS2546RTER

USB charger

Page 27~36

AOU

Page 45

RJ45 Conn

Page 49

20141227_S

Intel

WGI219V-QQJZ Non Vpro WGI219LM QQJY Vpro QFN48_6X 6

PCIe port 4

Page 47

PCIe Gen1 Port 4

Intel PCH-LP

USB 2.0 x 2

Int. Camera

USB 2.0 Port 7

Page 38

Touch Panel

USB 2.0 Port 5

Page 64

Card Reader

Page 51

Page 66

PCIe Gen1 Port 6

SPI BUS

3.3V 33MHz

ITE IT8586E/FX

Int.KBD

Page 64

LPC BUS

3.3V 33MHz

EC

G-SensorThermal Sensor

LIS3D HTR

Page 61

SMB BUS

Page 68

USB 2.0 Port 5

SATA Gen3 P ort 0

SATA Gen2 P ort 1

Page 5~20

HD Audio

3.3V 24MHz

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Issued Date

Finger printer

USB 2.0 Port 9

Page 65

SATA HDD

SATA Port 0

page 43

SATA ODD

SATA Port 1

page 44

Codec

CX118 52- 11z

2013/09/07

Page 54

HP_R/L_JA CK Ext Mic

Combo Jack

Page 55

LC Future Center Secret Data

D

Deciphered Date

SP_OUTR/L

2014/09/07

SPK Conn.

Page 55

Title

BLOCK DIAGRAM

Size

Document Number Re v

A2

Wednesday, September 23, 2015

Date: Sheet of

E

BE560

2 99

0.1

Power Circuit DC/DC

3 3

One-Link Docking Board

& USB3.0 Port3

Page 73~88

Realtek RTS5227S SD/MMC/XD Conn

SPI ROM

4MB+8 MB/TPM (NPCT652LAAWX)

Page 23,69

Combon Jack Board

Mirror function

Power Board

4 4

A

Fintek F75303M

B

A

B

C

D

E

1 1

Voltage Rails

Power Plane

State

2 2

S0

S3

S5 S4/AC Only

S5 S4 Battery only

( O --> Means ON , X --> Means OFF )

+3VALW

B+

+5VALW +1.35V

+1.8VALW

+1VALW

O

O O O

OO

O

X

X X

+5VS

+3VS

+VCC_CO RE

+VCC_IO

+VCC_SA

+VCC_ST

+VCC_ST G

+VGA_CO RE

+3VS_VG A

+1.8VS_ VGA

+1.35VS _VGA

+0.675V S

X

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SIGNAL

SLP_A# SLP_ S3# SLP_S4 # SLP_S5# EC_ON2 EC_ ON SUSP#

HIGH HIGH HIGH HIGH

HIGH

LOW LOW

SMBUS Control Table

SOURCE

IT8580FEC_SMB_ CK1

EC_SMB_ DA1

EC_SMB_ CK3

EC_SMB_ DA3

PCH_SMB _CLK PCH_SMB _DATA

PCH_SML 0_CLK PCH_SML 0_DAT

+3VL

IT8580F

+3VS

PCH

+3V_PCH

PCH

+3V_PCH

+3VS_VG A +3VS

ON

ONONON

Main VGA

X

V

X X

HIGH

LOWLOWLOW

BATT SODIMM

V

+3VALW

X

+3VS

ON

HIGHHIGHHIGH

ON

HIGH

ON

HIGH

WLAN WiMAX

X X X X X

X

V

ONONOFF

ON

Thermal Sensor

V

XX

ON

OFF

OFFLOW LOW LOW LOW

PCH

V

+3V_PCH

X

CP Module

X

V

+5VS

Securit y ROM

X X X X X X X X

LAN PHY

X X

X

V

+3VS

+3VALW

X

V

G sensor

X

V

+3VALW_ GS

X

S5 S4 AC & Battery don't exist

3 3

X X

X

USB2 Port

1 2 3 4 5

Touch Panel 6 BT 7 8

DevicePor t

JUSB2 JUSB3

Sub Board

Docking

CMO S

FP/Smart

USB3 Port

DevicePor t

1

JUSB2

2

JUSB3

3

Sub Board

4

Docking

5 3D CCD(PCIE1)

PCIE Port

Por t Device

1

3D CCD(USB3) 2 3 4 5 6 CardRe ader 7 8 9 10 11 12

X

WLA N LAN

X

GPU GPU GPU GPU

SATA Port

1 2 3 4

DevicePor t

HDD ODD

X X

4 4

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

C

2013/11/04

LC Future Center Secret Data

Deciphered Date

D

2014/09/07

Title

NOTE LIST

Size Document Number Re v

Custom

Wednesday, September 23, 2015

Date: Sheet o f

BE560

E

3 99

0.1

5

4

3

2

1

VGA and DDR3 Voltage Rails (Litho XT 2GB DDR3)

OUT

IN

OUT

IN

OUT

ACTIVE

N/A

-

GPIO5_AC_BATT

-

GPIO6

N/A

-

GPIO8_ROMSO

-

GPIO9_ROMSI

-

GPIO10_ROMSCK

N/A

N/A SVI2_ SVD

N/A

GPIO19_CTF

N/A

GPIO20

N/A

GPIO22_ROMCSB

N/A

Function Description

GPIO I/ O

D D

GPIO0

GPIO5

GPIO6

GPIO7

GPIO8

GPIO9

GPIO10

GPIO11

GPIO12

GPIO13

GPIO15

C C

GPIO16

GPIO17

GPIO19

GPIO20 IN IN

GPIO21

GPIO22

GPIO29

GPIO30

20141227_S

BOM Structure Table

BOM Structure

PCB @ For PCB load BOM

XDP @ Debug port

UMA @

DIS @

DIMM2@ For DIMM2 function

ME@

EMC_2D@ For EMC function

EMC_NS@ For EMC function

RF_NS@ For RF function

S2G @ For VRAM Strap

CHA @ For VRAMA function

CHB @ For VRAMB function

RANKA@ GPU DDR5 Setting

X76 @ GPU VRAM Setting

3DCCD@ 3D Camera Setting

UMA SKU ID

Optimus SKU ID

For DIMM1 functionDIMM1@

For VPRO functionVPRO@

ME Connector

For EMC functionEMC @

NOT E

VGA @ VGA Setting

+3VS_VG A

+1VS_VG A

B B

+1.8VS_ VGA

+VGA_CO RE

+1.35VS _VGA

10us

RESET

1. all power rail ramp up time should be within 20ms

Device ID

JET-XT 0xFFFF

A A

SMB_ALT _ADDR

(ROM_SO Bit 1)

I2C Slave addrees ID

setting

0

1

0xFF

MUX @ MUX Setting

ODD @ ODD Setting

TPM @

NVPRO@

Trusted Platform Module (TPM)

For Non-VPRO function

MIRROR@ For mirror function

GPU

FB Memory (DDR3L)

Samsung 1000MHz

Hynix 1000MHz

1000MHz

K4W4G164 6D-BC1A

256Mx16

H5TC4G63 AFR-11C

256Mx16 PH 4.75K

MT41J256 M16HA-0 93GMicro

256Mx16

Litho XT 2GB DDR3

PS_3 (RV114)

PH 3.4K

PH 3.24K

PS_3 (RV117)

PD 10K

NC

PD 5.62K

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

3

2013/11/04

LC Future Center Secret Data

Deciphered Date

2

2014/09/07

Title

VGA NOTE

Size Document Number Re v

Custom

Wednesday, September 23, 2015

Date: Sheet o f

BE560

1

4 99

0.1

5

4

3

2

1

D D

DDI1_MUX_TX0-[42] DDI1_MUX_TX0+[42] DDI1_MUX_TX1-[42] DDI1_MUX_TX1+[42]

HDMI & DOCKING

VGA

C C

+VCC_IO

[SKL PDG]EDP_RCOMP Pull up to VCCIO via 24.9 ohm resistor

[SKL PDG]EDP_RCOMP

1. Trace width=20 mils, Spacing=25mil, Max length=100mils

2. RC1 close to MCP

DDI1_MUX_TX2-[42] DDI1_MUX_TX2+[42] DDI1_MUX_TX3-[42] DDI1_MUX_TX3+[42]

DDI2_VGA_TX0-[41] DDI2_VGA_TX0+[41] DDI2_VGA_TX1-[41] DDI2_VGA_TX1+[41]

PCH_MUX_CLK[42] PCH_MUX_DAT[42]

1 2

RC344 24.9_0402_1%

DDI1_MUX_TX0DDI1_MUX_TX0+ DDI1_MUX_TX1DDI1_MUX_TX1+ DDI1_MUX_TX2DDI1_MUX_TX2+ DDI1_MUX_TX3DDI1_MUX_TX3+

DDI2_VGA_TX0DDI2_VGA_TX0+ DDI2_VGA_TX1DDI2_VGA_TX1+

PCH_MUX_CLK PCH_MUX_DAT

DP_DDC_CLK DP_DDC_DAT

EDP_COMP

UC1A

E55

DDI1_TXN[0]

F55

DDI1_TXP[0]

E58

DDI1_TXN[1]

F58

DDI1_TXP[1]

F53

DDI1_TXN[2]

G53

DDI1_TXP[2]

F56

DDI1_TXN[3]

G56

DDI1_TXP[3]

C50

DDI2_TXN[0]

D50

DDI2_TXP[0]

C52

DDI2_TXN[1]

D52

DDI2_TXP[1]

A50

DDI2_TXN[2]

B50

DDI2_TXP[2]

D51

DDI2_TXN[3]

C51

DDI2_TXP[3]

L13

GPP_E18/DDPB_CTRLCLK

L12

GPP_E19/DDPB_CTRLDATA

N7

GPP_E20/DDPC_CTRLCLK

N8

GPP_E21/DDPC_CTRLDATA

N11

GPP_E22/DDPD_CTRLCLK

N12

GPP_E23/DDPD_CTRLDATA

E52

EDP_RCOMP

SKYLAKE-U_BGA1356

REV = 1

@

SKL_ ULT

HDMI

DDI

DP

DISPLAY SIDEBANDS

EDP

EDP_TXN[0] EDP_TXP[0] EDP_TXN[1] EDP_TXP[1] EDP_TXN[2] EDP_TXP[2] EDP_TXN[3] EDP_TXP[3]

EDP_AUXN EDP_AUXP

EDP_DISP_UTIL

DDI1_AUXN DDI1_AUXP DDI2_AUXN DDI2_AUXP DDI3_AUXN DDI3_AUXP

GPP_E13/DDPB_HPD0 GPP_E14/DDPC_HPD1 GPP_E15/DDPD_HPD2 GPP_E16/DDPE_HPD3

GPP_E17/EDP_HPD

EDP_BKLTEN

EDP_BKLTCTL

EDP_VDDEN

? ?1 OF 20

C47 C46 D46 C45 A45 B45 A47 B47

E45 F45

B52

G50 F50 E48 F48 G46 F46

L9 L7 L6 N9 L10

R12 R11 U13

CPU_EDP_TX0CPU_EDP_TX0+ CPU_EDP_TX1CPU_EDP_TX1+

CPU_EDP_AUX# CPU_EDP_AUX

PCH_MUX_AUX# PCH_MUX_AUX PCH_VGA_AUX# PCH_VGA_AUX

PCH_MUX_HPD PCH_VGA_HPD

CPU_EDP_HPD

ENBKL PCH_EDP_PWM

PCH_ENVDD

CPU_EDP_TX0- [38] CPU_EDP_TX0+ [38] CPU_EDP_TX1- [38] CPU_EDP_TX1+ [38]

CPU_EDP_AUX# [38] CPU_EDP_AUX [38]

PCH_MUX_AUX# [42] PCH_MUX_AUX [42] PCH_VGA_AUX# [41] PCH_VGA_AUX [41]

PCH_MUX_HPD [42] PCH_VGA_HPD [41]

CPU_EDP_HPD [38]

ENBKL [61] PCH_EDP_PWM [38] PCH_ENVDD [38]

EDP

DDPB_CTRLDATA, DDPC_CTRLDATA Internal PD 20K

+3VS

1 2

RC277 2.2K_0402_5%@

1 2

RC287 2.2K_0402_5%

1 2

RC1 2.2K_0402_5%@

1 2

RC2 2.2K_0402_5%

B B

PCH_MUX_CLK

PCH_MUX_DAT

DP_DDC_CLK

DP_DDC_DAT

ENBKL

CPU_EDP_HPD

[SKL PDG]EDP_HPD Pull down to ground via 100k ohm resistor

PCH_MUX_HPD

[SKL PDG]For DP required

PCH_VGA_HPD

1 2

RC209 100K_0402_5%

1 2

RC159 100K_0402_5%

1 2

RC288 100K_0402_5%@

1 2

RC204 100K_0402_5%

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

3

2014/05/07

LC Future Center Secret Data

Deciphered Date

2

2015/05/07

Title

SKL(1/16):DDI/EDP

Size Document Number Re v

Custom

Date: Sheet o f

BE560

Wednesday, September 23, 2015

1

5 99

0.1

5

D D

C C

H_PECI[61] VR_HOT#[61,75,79]

H_THERMTRIP#[28]

EC_WAKE#[61]

[SKL PDG]If THERMTRIP# goes active, the CPU is indicating an overheat condition, and the PCH will immediately transition to an S5 state. CPU_GP can be used from external sensors for the thermal management.

[SKL PDG]PROC_OPI_RCOMP: Signal should be pulled down to ground with a resistance of 50 ohm

∮

[SKL PDG]PCH_OPI_RCOMP: Signal should be pulled down to ground with a resistance of 50 ohm

∮

[SKL PDG]On Package Interface Compensation (OPI) Guidelines

Should be referenced to VSS plane only. VSS reference planes must be continuous



Require low DC resistance routing <0.2 ohm



Avoid routing next to clock pins or noisy signals.

B B



4

+VCC_STG

12

RC294 1K_0402_5%

H_PECI VR_HOT#

EC_WAKE# EC_WAKE#_L

1 %. 1 %.

1 2

RC5 499_0402_1%

1 2

RC54 0_0402_5%@

1 2

RC40 0_0402_5%

1 2

RC151 49.9_0402_1%

1 2

RC55 49.9_0402_1%

1 2

RC200 49.9_0402_1%

1 2

RC56 49.9_0402_1%

TC119

TC1 TC2 TC7 TC9

1

VR_HOT#_R THRMTRIP#

1

XDP_BPM#1

1

XDP_BPM#2

1

XDP_BPM#3

1

PROC_POPIRCOMP PCH_OPIRCOMP OPCE_RCOMP OPC_RCOMP

UC1D

D63

CATERR#

A54

PECI

C65

PROCHOT#

C63

THERMTRIP#

A65

SKTOCC#

C55

BPM#[0]

D55

BPM#[1]

B54

BPM#[2]

C56

BPM#[3]

A6

GPP_E3/CPU_GP0

A7

GPP_E7/CPU_GP1

BA5

GPP_B3/CPU_GP2

AY5

GPP_B4/CPU_GP3

AT16

PROC_POPIRCOMP

AU16

PCH_OPIRCOMP

H66

OPCE_RCOMP

H65

OPC_RCOMP

SKYLAKE-U_BGA1356

REV = 1

@

3

SKL_ ULT

CPU MISC

JTAG

PCH_JTAG_TCK

PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS

XDP_TCLK XDP_TDI XDP_TDO XDP_TMS XDP_TRST#

PROC_TCK

PROC_TDI PROC_TDO PROC_TMS

PROC_TRST#

PCH_TRST#

JTAGX

RC415 0_0201_5%DCI@ RC422 0_0201_5%DCI@ RC423 0_0201_5%DCI@ RC424 0_0201_5%DCI@ RC425 0_0201_5%DCI@

B61 D60 A61 C60 B59

B56 D59 A56 C59 C61 A59

?? 4 OF 20

1 2 1 2 1 2 1 2 1 2

XDP_TCLK XDP_TDI XDP_TDO XDP_TMS XDP_TRST#

PCH_JTAG_TCK PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS PCH_JTAG_TRST# PCH_JTAGX

1

15/0526

PCH_JTAGX PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS PCH_JTAG_TRST#

TC10

2

+VCC_ST

[SKL PDG]1 K pull- up t o



12

VCCST

RC53 1K_0402_1%

THRMTRIP#

[SKL PDG]Refer Figure 45-1

XDP_TDI

XDP_TMSXDP_BPM#0

XDP_TCLK

XDP_TRST#

PCH_JTAG_TCK

1 2

RC31 51_0201_5%XDP@

1 2

RC34 51_0201_5%XDP@

1 2

RC4 51_0201_5%

1 2

RC6 51_0201_5%

1 2

RC352 51_0201_5%

+VCC_ST

1

15/0526

2014122 9

[SKL PDG]Refer Figure 45-1

PCH_JTAG_TDI

PCH_JTAG_TMS

RC354 51_0201_5%XDP@

RC353 51_0201_5%XDP@

1 2

+1VALW_PCH

+VCC_STG+VCC_ST

XDP_TDO

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

3

2014/05/07

LC Future Center Secret Data

Deciphered Date

2

2015/05/07

@

1 2

RC3 51_0201_5%

1 2

RC426 51_0201_5%

Title

SKL(2/16):MISC/JTAG

Size Document Number Re v

Custom

Date: Sheet o f

AIVL2_NM-A351

Wednesday, September 23, 2015

1

6 99

0.1

5

D D

4

3

2

1

UC1B

DDR_A_D[0..63][25] DDR_A_DQS#[0..7][25] DDR_A_DQS[0..7][25] DDR_A_MA[0..15][25]

C C

B B

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

AL71

DDR0_DQ[0]

AL68

DDR0_DQ[1]

AN68

DDR0_DQ[2]

AN69

DDR0_DQ[3]

AL70

DDR0_DQ[4]

AL69

DDR0_DQ[5]

AN70

DDR0_DQ[6]

AN71

DDR0_DQ[7]

AR70

DDR0_DQ[8]

AR68

DDR0_DQ[9]

AU71

DDR0_DQ[10]

AU68

DDR0_DQ[11]

AR71

DDR0_DQ[12]

AR69

DDR0_DQ[13]

AU70

DDR0_DQ[14]

AU69

DDR0_DQ[15]

BB65

DDR0_DQ[16]/DDR0_DQ[32]

AW65

DDR0_DQ[17]/DDR0_DQ[33]

AW63

DDR0_DQ[18]/DDR0_DQ[34]

AY63

DDR0_DQ[19]/DDR0_DQ[35]

BA65

DDR0_DQ[20]/DDR0_DQ[36]

AY65

DDR0_DQ[21]/DDR0_DQ[37]

BA63

DDR0_DQ[22]/DDR0_DQ[38]

BB63

DDR0_DQ[23]/DDR0_DQ[39]

BA61

DDR0_DQ[24]/DDR0_DQ[40]

AW61

DDR0_DQ[25]/DDR0_DQ[41]

BB59

DDR0_DQ[26]/DDR0_DQ[42]

AW59

DDR0_DQ[27]/DDR0_DQ[43]

BB61

DDR0_DQ[28]/DDR0_DQ[44]

AY61

DDR0_DQ[29]/DDR0_DQ[45]

BA59

DDR0_DQ[30]/DDR0_DQ[46]

AY59

DDR0_DQ[31]/DDR0_DQ[47]

AY39

DDR0_DQ[32]/DDR1_DQ[0]

AW39

DDR0_DQ[33]/DDR1_DQ[1]

AY37

DDR0_DQ[34]/DDR1_DQ[2]

AW37

DDR0_DQ[35]/DDR1_DQ[3]

BB39

DDR0_DQ[36]/DDR1_DQ[4]

BA39

DDR0_DQ[37]/DDR1_DQ[5]

BA37

DDR0_DQ[38]/DDR1_DQ[6]

BB37

DDR0_DQ[39]/DDR1_DQ[7]

AY35

DDR0_DQ[40]/DDR1_DQ[8]

AW35

DDR0_DQ[41]/DDR1_DQ[9]

AY33

DDR0_DQ[42]/DDR1_DQ[10]

AW33

DDR0_DQ[43]/DDR1_DQ[11]

BB35

DDR0_DQ[44]/DDR1_DQ[12]

BA35

DDR0_DQ[45]/DDR1_DQ[13]

BA33

DDR0_DQ[46]/DDR1_DQ[14]

BB33

DDR0_DQ[47]/DDR1_DQ[15]

AY31

DDR0_DQ[48]/DDR1_DQ[32]

AW31

DDR0_DQ[49]/DDR1_DQ[33]

AY29

DDR0_DQ[50]/DDR1_DQ[34]

AW29

DDR0_DQ[51]/DDR1_DQ[35]

BB31

DDR0_DQ[52]/DDR1_DQ[36]

BA31

DDR0_DQ[53]/DDR1_DQ[37]

BA29

DDR0_DQ[54]/DDR1_DQ[38]

BB29

DDR0_DQ[55]/DDR1_DQ[39]

AY27

DDR0_DQ[56]/DDR1_DQ[40]

AW27

DDR0_DQ[57]/DDR1_DQ[41]

AY25

DDR0_DQ[58]/DDR1_DQ[42]

AW25

DDR0_DQ[59]/DDR1_DQ[43]

BB27

DDR0_DQ[60]/DDR1_DQ[44]

BA27

DDR0_DQ[61]/DDR1_DQ[45]

BA25

DDR0_DQ[62]/DDR1_DQ[46]

BB25

DDR0_DQ[63]/DDR1_DQ[47]

SKYLAKE-U_BGA1356

REV = 1 @

SKL_ ULT

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]

DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#

DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]

DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]

DDR0_DQSN[2]/DDR0_DQSN[4] DDR0_DQSP[2]/DDR0_DQSP[4] DDR0_DQSN[3]/DDR0_DQSN[5] DDR0_DQSP[3]/DDR0_DQSP[5] DDR0_DQSN[4]/DDR1_DQSN[0] DDR0_DQSP[4]/DDR1_DQSP[0] DDR0_DQSN[5]/DDR1_DQSN[1] DDR0_DQSP[5]/DDR1_DQSP[1] DDR0_DQSN[6]/DDR1_DQSN[4] DDR0_DQSP[6]/DDR1_DQSP[4] DDR0_DQSN[7]/DDR1_DQSN[5] DDR0_DQSP[7]/DDR1_DQSP[5]

DDR CH - A

DDR0_CKN[0] DDR0_CKP[0] DDR0_CKN[1] DDR0_CKP[1]

DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3]

DDR0_CS#[0] DDR0_CS#[1] DDR0_ODT[0] DDR0_ODT[1]

DDR0_MA[3] DDR0_MA[4]

DDR0_DQSN[0] DDR0_DQSP[0] DDR0_DQSN[1] DDR0_DQSP[1]

DDR0_ALERT#

DDR0_PAR

DDR_VREF_CA DDR0_VREF_DQ DDR1_VREF_DQ

DDR_VTT_CNTL

??2 OF 20

AU53 AT53 AU55 AT55

BA56 BB56 AW56 AY56

AU45 AU43 AT45 AT43

BA51 BB54 BA52 AY52 AW52 AY55 AW54 BA54 BA55 AY54

AU46 AU48 AT46 AU50 AU52 AY51 AT48 AT50 BB50 AY50 BA50 BB52

AM70 AM69 AT69 AT70 BA64 AY64 AY60 BA60 BA38 AY38 AY34 BA34 BA30 AY30 AY26 BA26

AW50 AT52

AY67 AY68 BA67

AW67

SA_CLK_DDR#0 SA_CLK_DDR0 SA_CLK_DDR#1 SA_CLK_DDR1

DDRA_CKE0_DIMMA DDRA_CKE1_DIMMA

DDRA_CS0_DIMMA# DDRA_CS1_DIMMA# DDRA_ODT0_DIMMA# DDRA_ODT1_DIMMA#

DDR_A_MA5 DDR_A_MA9 DDR_A_MA6 DDR_A_MA8 DDR_A_MA7 DDR_A_BS2 DDR_A_MA12 DDR_A_MA11 DDR_A_MA15 DDR_A_MA14

DDR_A_MA13 DDR_A_CAS# DDR_A_WE# DDR_A_RAS# DDR_A_BS0 DDR_A_MA2 DDR_A_BS1 DDR_A_MA10 DDR_A_MA1 DDR_A_MA0 DDR_A_MA3 DDR_A_MA4

DDR_A_DQS#0 DDR_A_DQS0 DDR_A_DQS#1 DDR_A_DQS1 DDR_A_DQS#2 DDR_A_DQS2 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_DQS#4 DDR_A_DQS4 DDR_A_DQS#5 DDR_A_DQS5 DDR_A_DQS#6 DDR_A_DQS6 DDR_A_DQS#7 DDR_A_DQS7

SM_DIMM_VREFCA SA_DIMM_VREFDQ SB_DIMM_VREFDQ

DDR_PG_CTRL

SA_CLK_DDR#0 [25] SA_CLK_DDR0 [25] SA_CLK_DDR#1 [25] SA_CLK_DDR1 [25]

DDRA_CKE0_DIMMA [25] DDRA_CKE1_DIMMA [25]

DDRA_CS0_DIMMA# [25] DDRA_CS1_DIMMA# [25] DDRA_ODT0_DIMMA# [25] DDRA_ODT1_DIMMA# [25]

DDR_A_BS2 [25]

DDR_A_CAS# [25] DDR_A_WE# [25] DDR_A_RAS# [25] DDR_A_BS0 [25]

DDR_A_BS1 [25]

20141201

SM_DIMM_VREFCA [25] SA_DIMM_VREFDQ [25] SB_DIMM_VREFDQ [26]

DDR_PG_CTRL [25]

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

3

2014/05/07

LC Future Center Secret Data

Deciphered Date

2

2015/05/07

Title

SKL(3/16):DDR3L CH.A

Size Document Number Re v

Custom

Date: Sheet o f

BE560

Wednesday, September 23, 2015

1

7 99

0.1

5

D D

4

3

2

1

UC1C

DDR_B_D[0..63][26] DDR_B_DQS#[0..7][26] DDR_B_DQS[0..7][26] DDR_B_MA[0..15][26]

C C

B B

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

AF65

DDR1_DQ[0]/DDR0_DQ[16]

AF64

DDR1_DQ[1]/DDR0_DQ[17]

AK65

DDR1_DQ[2]/DDR0_DQ[18]

AK64

DDR1_DQ[3]/DDR0_DQ[19]

AF66

DDR1_DQ[4]/DDR0_DQ[20]

AF67

DDR1_DQ[5]/DDR0_DQ[21]

AK67

DDR1_DQ[6]/DDR0_DQ[22]

AK66

DDR1_DQ[7]/DDR0_DQ[23]

AF70

DDR1_DQ[8]/DDR0_DQ[24]

AF68

DDR1_DQ[9]/DDR0_DQ[25]

AH71

DDR1_DQ[10]/DDR0_DQ[26]

AH68

DDR1_DQ[11]/DDR0_DQ[27]

AF71

DDR1_DQ[12]/DDR0_DQ[28]

AF69

DDR1_DQ[13]/DDR0_DQ[29]

AH70

DDR1_DQ[14]/DDR0_DQ[30]

AH69

DDR1_DQ[15]/DDR0_DQ[31]

AT66

DDR1_DQ[16]/DDR0_DQ[48]

AU66

DDR1_DQ[17]/DDR0_DQ[49]

AP65

DDR1_DQ[18]/DDR0_DQ[50]

AN65

DDR1_DQ[19]/DDR0_DQ[51]

AN66

DDR1_DQ[20]/DDR0_DQ[52]

AP66

DDR1_DQ[21]/DDR0_DQ[53]

AT65

DDR1_DQ[22]/DDR0_DQ[54]

AU65

DDR1_DQ[23]/DDR0_DQ[55]

AT61

DDR1_DQ[24]/DDR0_DQ[56]

AU61

DDR1_DQ[25]/DDR0_DQ[57]

AP60

DDR1_DQ[26]/DDR0_DQ[58]

AN60

DDR1_DQ[27]/DDR0_DQ[59]

AN61

DDR1_DQ[28]/DDR0_DQ[60]

AP61

DDR1_DQ[29]/DDR0_DQ[61]

AT60

DDR1_DQ[30]/DDR0_DQ[62]

AU60

DDR1_DQ[31]/DDR0_DQ[63]

AU40

DDR1_DQ[32]/DDR1_DQ[16]

AT40

DDR1_DQ[33]/DDR1_DQ[17]

AT37

DDR1_DQ[34]/DDR1_DQ[18]

AU37

DDR1_DQ[35]/DDR1_DQ[19]

AR40

DDR1_DQ[36]/DDR1_DQ[20]

AP40

DDR1_DQ[37]/DDR1_DQ[21]

AP37

DDR1_DQ[38]/DDR1_DQ[22]

AR37

DDR1_DQ[39]/DDR1_DQ[23]

AT33

DDR1_DQ[40]/DDR1_DQ[24]

AU33

DDR1_DQ[41]/DDR1_DQ[25]

AU30

DDR1_DQ[42]/DDR1_DQ[26]

AT30

DDR1_DQ[43]/DDR1_DQ[27]

AR33

DDR1_DQ[44]/DDR1_DQ[28]

AP33

DDR1_DQ[45]/DDR1_DQ[29]

AR30

DDR1_DQ[46]/DDR1_DQ[30]

AP30

DDR1_DQ[47]/DDR1_DQ[31]

AU27

DDR1_DQ[48]

AT27

DDR1_DQ[49]

AT25

DDR1_DQ[50]

AU25

DDR1_DQ[51]

AP27

DDR1_DQ[52]

AN27

DDR1_DQ[53]

AN25

DDR1_DQ[54]

AP25

DDR1_DQ[55]

AT22

DDR1_DQ[56]

AU22

DDR1_DQ[57]

AU21

DDR1_DQ[58]

AT21

DDR1_DQ[59]

AN22

DDR1_DQ[60]

AP22

DDR1_DQ[61]

AP21

DDR1_DQ[62]

AN21

DDR1_DQ[63]

SKYLAKE-U_BGA1356

REV = 1 @

SKL_ ULT

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]

DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#

DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]

DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]

DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]

DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]

DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]

DDR1_DQSN[0]/DDR0_DQSN[2] DDR1_DQSP[0]/DDR0_DQSP[2] DDR1_DQSN[1]/DDR0_DQSN[3] DDR1_DQSP[1]/DDR0_DQSP[3] DDR1_DQSN[2]/DDR0_DQSN[6] DDR1_DQSP[2]/DDR0_DQSP[6] DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQSP[3]/DDR0_DQSP[7] DDR1_DQSN[4]/DDR1_DQSN[2] DDR1_DQSP[4]/DDR1_DQSP[2] DDR1_DQSN[5]/DDR1_DQSN[3] DDR1_DQSP[5]/DDR1_DQSP[3]

DDR1_DQSN[6] DDR1_DQSP[6] DDR1_DQSN[7] DDR1_DQSP[7]

DDR1_ALERT#

DRAM_RESET# DDR_RCOMP[0] DDR_RCOMP[1]

DDR CH - B

DDR_RCOMP[2]

DDR1_CKN[0] DDR1_CKN[1] DDR1_CKP[0] DDR1_CKP[1]

DDR1_CKE[0] DDR1_CKE[1] DDR1_CKE[2] DDR1_CKE[3]

DDR1_CS#[0] DDR1_CS#[1] DDR1_ODT[0] DDR1_ODT[1]

DDR1_MA[3] DDR1_MA[4]

DDR1_PAR

??3 OF 20

AN45 AN46 AP45 AP46

AN56 AP55 AN55 AP53

BB42 AY42 BA42 AW42

AY48 AP50 BA48 BB48 AP48 AP52 AN50 AN48 AN53 AN52

BA43 AY43 AY44 AW44 BB44 AY47 BA44 AW46 AY46 BA46 BB46 BA47

AH66 AH65 AG69 AG70 AR66 AR65 AR61 AR60 AT38 AR38 AT32 AR32 AR25 AR27 AR22 AR21

AN43 AP43 AT13 AR18 AT18 AU18

SB_CLK_DDR#0 SB_CLK_DDR#1 SB_CLK_DDR0 SB_CLK_DDR1

DDRB_CKE0_DIMMB DDRB_CKE1_DIMMB

DDRB_CS0_DIMMB# DDRB_CS1_DIMMB# DDRB_ODT0_DIMMB# DDRB_ODT1_DIMMB#

DDR_B_MA5 DDR_B_MA9 DDR_B_MA6 DDR_B_MA8 DDR_B_MA7 DDR_B_BS2 DDR_B_MA12 DDR_B_MA11 DDR_B_MA15 DDR_B_MA14

DDR_B_MA13 DDR_B_CAS# DDR_B_WE# DDR_B_RAS# DDR_B_BS0 DDR_B_MA2 DDR_B_BS1 DDR_B_MA10 DDR_B_MA1 DDR_B_MA0 DDR_B_MA3 DDR_B_MA4

DDR_B_DQS#0 DDR_B_DQS0 DDR_B_DQS#1 DDR_B_DQS1 DDR_B_DQS#2 DDR_B_DQS2 DDR_B_DQS#3 DDR_B_DQS3 DDR_B_DQS#4 DDR_B_DQS4 DDR_B_DQS#5 DDR_B_DQS5 DDR_B_DQS#6 DDR_B_DQS6 DDR_B_DQS#7 DDR_B_DQS7

DDR3_DRAMRST# SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

SB_CLK_DDR#0 [26] SB_CLK_DDR#1 [26] SB_CLK_DDR0 [26] SB_CLK_DDR1 [26]

DDRB_CKE0_DIMMB [26] DDRB_CKE1_DIMMB [26]

DDRB_CS0_DIMMB# [26] DDRB_CS1_DIMMB# [26] DDRB_ODT0_DIMMB# [26] DDRB_ODT1_DIMMB# [26]

DDR_B_BS2 [26]

DDR_B_CAS# [26] DDR_B_WE# [26] DDR_B_RAS# [26] DDR_B_BS0 [26]

DDR_B_BS1 [26]

1 2

RC8 121_0402_1%

1 2

RC9 80.6_0402_1%

1 2

RC10 100_0402_1%

DDR3_DRAMRST# [25,26]

[SKL PDG]for DDR3L DDR_RCOMP[0] Pull down 121 ohm resistor DDR_RCOMP[1] Pull down 80.6 ohm resistor DDR_RCOMP[2] Pull down 100 ohm resistor

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

3

2014/05/07

LC Future Center Secret Data

Deciphered Date

2

2015/05/07

Title

SKL(4/16):DDR3L CH.B

Size Document Number Re v

Custom

Date: Sheet o f

BE560

Wednesday, September 23, 2015

1

8 99

0.1

5

D D

[SKL PDG]Manufacturing Mode Jumper

1. If strap is sampled low, the security measures def i ned i n t he Fl ash Des cri pt or will be i n e f fect ( def ault )

2. If sampled high, the Flash Descriptor Security will be overridden.

PCH_HDA_RST#[54] PCH_HDA_BCLK[54] PCH_HDA_SDOUT[54] PCH_HDA_SYNC[54]

ME_FLASH[61]

PCH_HDA_RST# HDA_RST# PCH_HDA_BCLK HDA_BCLK PCH_HDA_SDOUT HDA_SDOUT PCH_HDA_SYNC HDA_SYNC

4

RPC2

1 8 2 7 3 6 4 5

33_0804_8P4R_5%

SD30000370T

1 2

RC21 0_0402_5%

3

2

1

UC1G

C C

B B

GPP_B14, Internal PD 20K No Reboot on TCO Timer expiration pull-up to VCC3_3 through a 1 resistor to disable this capability

PCH_BEEP

Processor Strapping 543016_543016_SKL_PDG_UY_1_0_pu b P78 0

PCH_HDA_SDIN0

HDA_SDOUT

HDA_SYNC

RC95 8.2K_0402_5%

RC300 20K_0402_5%@

Internal PD already Un-mout RC300 by 7/20

RC297 1K_0402_5%

RC301 20K_0402_5%@

RC299 1K_0402_5%

RC302 20K_0402_5%@

RC356 1K_0402_5%

1 2

@

1 2

@

1 2

@

1 2

@

Default

Un-mout RC356

by 7/20



8.2 K

15/0519

 ∮∮∮∮

+3VALW_PCH



+VCC_IO

+VCC_HDA

+3VALW_PCH

5 %

Check RC377 to remove by 7/20

PCH_HDA_SDIN0[54]

PCH_BEEP[55]

HDA_SYNC HDA_BCLK HDA_SDOUT PCH_HDA_SDIN0

HDA_RST#

PCH_BEEP

BA22 AY22 BB22 BA21 AY21

AW22

AY20

AW20

AK10

AW5

AK7 AK6 AK9

HDA_SYNC/I2S0_SFRM HDA_BLK/I2S0_SCLK HDA_SDO/I2S0_TXD HDA_SDI0/I2S0_RXD HDA_SDI1/I2S1_RXD HDA_RST#/I2S1_SCLK

J5

GPP_D23/I2S_MCLK I2S1_SFRM I2S1_TXD

GPP_F1/I2S2_SFRM GPP_F0/I2S2_SCLK GPP_F2/I2S2_TXD GPP_F3/I2S2_RXD

H5

GPP_D19/DMIC_CLK0

D7

GPP_D20/DMIC_DATA0

D8

GPP_D17/DMIC_CLK1

C8

GPP_D18/DMIC_DATA1

GPP_B14/SPKR

SKYLAKE-U_BGA1356

REV = 1 @

AUDIO

SKL_ ULT

SDIO/SDXC

GPP_G0/SD_CMD GPP_G1/SD_DATA0 GPP_G2/SD_DATA1 GPP_G3/SD_DATA2 GPP_G4/SD_DATA3

GPP_G5/SD_CD# GPP_G6/SD_CLK

GPP_A17/SD_PWR_EN#/ISH_GP7

GPP_G7/SD_WP

GPP_A16/SD_1P8_SEL

SD_RCOMP

GPP_F23

[SKL PDG] internal SD Card

AB11 AB13 AB12 W12 W11 W10 W8 W7

BA9 BB9

AB7

1 2

RC378

AF13

200_0402_1%

??7 OF 20

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

3

2014/05/07

LC Future Center Secret Data

Deciphered Date

2

2015/05/07

Title

SKL(5/16):HDA/SDIO

Size Document Number Re v

Custom

Date: Sheet o f

BE560

Wednesday, September 23, 2015

1

9 99

0.1

5

4

3

2

1

2015051 4

RTC External Circuit

1 2

D D

RC11 0_0402_5%

+RTCBATT, +RTCVCC Trace width = 20mils

1

CC2 1U_0402_10V6-K

2

1

C8542

0.1U_0402_10V6-K

2

JCMOS, JME Setting, Need Under DDR Door

+RTCVCC+RTCVCC+RTCBATT

RC12

1 2

20K_0402_5%

RC14

1 2

20K_0402_5%

PCH_RTCRST#

PCH_SRTCRST#

JCMOS1 @

1 2

CC1 1U_0402_10V6K

JME1 @

1 2

CC5 1U_0402_10V6K

UC1J

D42

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0

AR10

GPP_B5/SRCCLKREQ0#

B42

CLKOUT_PCIE_N1

A42

CLKOUT_PCIE_P1

AT7

GPP_B6/SRCCLKREQ1#

D41

CLKOUT_PCIE_N2

C41

CLKOUT_PCIE_P2

AT8

GPP_B7/SRCCLKREQ2#

D40

CLKOUT_PCIE_N3

C40

CLKOUT_PCIE_P3

AT10

GPP_B8/SRCCLKREQ3#

B40

CLKOUT_PCIE_N4

A40

CLKOUT_PCIE_P4

AU8

GPP_B9/SRCCLKREQ4#

E40

CLKOUT_PCIE_N5

E38

CLKOUT_PCIE_P5

AU7

GPP_B10/SRCCLKREQ5#

SKYLAKE-U_BGA1356

REV = 1

@

[SKL PDG]Used to set BIAS reference for differential clocks. Connect to a [RC379]

2.71K

[SKL PDG]

1.A 24 MHz crystal with crystal frequency tolerance and stability of +/-30 ppm

2.Two External Load Cap acitors (Ce1 a nd Ce2)

3.A 1-Mohm bias resistor (Rf)

PCH_XTAL24_IN

PCH_XTAL24_OUT

12P_0402_50V8-J

WLAN

LAN

VGA

CR

RC13

1 2

10M_0402_5%

YC1

1 2

+3VS

1 2

RC29 10K_0402_5%DIS@

1 2

RC32 10K_0402_5%UMA@

CLK_PCIE_WLAN#[50] CLK_PCIE_WLAN[50] CLKREQ_PCIE2_WLAN#[50]

CLK_PCIE_LAN#[47] CLK_PCIE_LAN[47] CLKREQ_PCIE3_LAN#[47]

CLK_PCIE_VGA#[27] CLK_PCIE_VGA[27] CLKREQ_PCIE4_VGA#[27]

CLK_PCIE_CR#[51] CLK_PCIE_CR[51] CLKREQ_PCIE5_CR#[51]

[SKL PDG]External pu ll-up resi stor r equired if used for CLKREQ# functionality.

PCH_RTCX1

PCH_RTCX2

[SKL PDG]Max Crystal ESR = 50k Ohm.

1

CC4

5.6P_0402_50V8-D

2

DISCRETE_PRESENCE

CLK_PCIE_WLAN# SUSCLK_32K CLK_PCIE_WLAN CLKREQ_PCIE2_WLAN#

CLK_PCIE_LAN# CLK_PCIE_LAN CLKREQ_PCIE3_LAN#

CLK_PCIE_VGA# CLK_PCIE_VGA CLKREQ_PCIE4_VGA#

CLK_PCIE_CR# CLK_PCIE_CR CLKREQ_PCIE5_CR#

+3VS

UMA@

1 2

RC165 10K_0402_5%

C C

+3VS

B B

DIS@

1 2

RC166 10K_0402_5%

20141220

RPC200

1 8 2 7 3 6 4 5

CLKREQ_PCIE2_WLAN# CLKREQ_PCIE3_LAN#

CLKREQ_PCIE5_CR#

10K_0804_8P4R_5%

CLKREQ_PCIE4_VGA#

15/0519

[SKL PDG]

1.Space > 1 5mils

2.No trace under crystal

3.Place on oppsosit side of MCP for temp inf l uence

4.The exact capacitor values forC1 and C2 must be based on the crystal maker recommendat i ons. Typical values for C1 and C2 are 18 pF, based on crystal load of 12.5 pF.

RTC Crystal

32.768KHZ_12.5PF_9H03200042

1

CC3

5.6P_0402_50V8-D

2

SKL_ ULT

CLOCK SIGNALS

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

GPD8/SUSCLK

XTAL24_IN

XTAL24_OUT

XCLK_BIASREF

RTCX1 RTCX2

SRTCRST#

RTCRST#

∮∮∮∮

0.5% precision resistor to 1.0v.

RC30

1 2

1M_0402_5%

1

CC6

2

YC2

1

GND1

2

24MHZ_10PF_8Y24000011

GND2

3

1

4

CC7 12P_0402_50V8-J

2

??10 OF 20

F43 E43

BA17

E37 E35

E42

AM18 AM20

AN18 AM16

PCH_XTAL24_IN PCH_XTAL24_OUT

DIFFCLK_BIASREF

PCH_RTCX1 PCH_RTCX2

PCH_SRTCRST# PCH_RTCRST#

SUSCLK_32K [50]

1 2

RC379

2.7K_0402_1%

+1VALW

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

3

2014/05/07

LC Future Center Secret Data

Deciphered Date

2

2015/05/07

Title

SKL(6/16):CLOCK SIGNALS

Size Document Number Re v

Custom

Date: Sheet o f

BE560

Wednesday, September 23, 2015

1

10 99

0.1

5

4

3

2

1

Functional Strap Definitions

L:Disable Intel ME Crypto TLS cipher suite (no confidentiality). *H:Enable Intel ME Crypto Transport Layer Security (TLS) cipher suite (with confidentiality).Support Intel AMT with TLS and Intel SBA (Small Business Advantage) with TLS.

D D

GPP_C2

GPP_C2, Internal PD 20K

1 2

RC306 1K_0402_5%

1 2

RC307 20K_0402_5%@

+3VALW_PCH

close to CPU

JTAG ODT

+3VALW_PCH

SPI0_MOSI

C C

SPI_SI

SPI_SO

1 2

@

RC298 8.2K_0402_5%

1 2

@

RC308 8.2K_0402_5%

+3VALW_PCH

SPI_CLK[23,69]

RC380 0_0402_5%

SPI_CLK

1 2

SPI_SO[23,69] SPI_SI[23,69] SPI_IO2[23]

SPI_IO3[23] SPI_CS0#_8MB[23] SPI_CS1#_4MB[23] SPI_CS2#_TPM[69]

EC_SCI#[61]

CL_CLK_WLAN[50] CL_DATA_WLAN[50] CL_RST_WLAN#[50]

KBRST#[61]

SERIRQ[61,69]

SPI_SO SPI_SI SPI_IO2 SPI_IO3 SPI_CS0#_8MB SPI_CS1#_4MB SPI_CS2#_TPM

EC_SCI#

SPI_CLK_R

KBRST#

SERIRQ

UC1E

AV2

SPI0_CLK

AW3

SPI0_MISO

AV3

SPI0_MOSI

AW2

SPI0_IO2

AU4

SPI0_IO3

AU3

SPI0_CS0#

AU2

SPI0_CS1#

AU1

SPI0_CS2#

M2

GPP_D1/SPI1_CLK

M3

GPP_D2/SPI1_MISO

J4

GPP_D3/SPI1_MOSI

V1

GPP_D21/SPI1_IO2

V2

GPP_D22/SPI1_IO3

M1

GPP_D0/SPI1_CS#

G3

CL_CLK

G2

CL_DATA

G1

CL_RST#

AW13

GPP_A0/RCIN#

AY11

GPP_A6/SERIRQ

SKYLAKE-U_BGA1356

REV = 1 @

SPI - F LASH

SPI - TOUCH

C LINK

SKL_ ULT

LPC

SMBUS, SMLINK

GPP_B23/SML1ALERT#/PCHHOT#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A10/CLKOUT_LPC1

GPP_A8/CLKRUN#

??5 OF 20

R7 R8 R10

R9 W2 W1

W3 V3 AM7

AY13 BA13 BB13 AY12 BA12

SUS_STAT#

BA11

PCH_PCI_CLK_R

AW9 AY9 AW11

CLKRUN#

PCH_SMB_CLK PCH_SMB_DATA GPP_C2

PCH_SML0_CLK PCH_SML0_DAT GPP_C5

PCH_SML1CLK PCH_SML1DATA GPP_B23

PCH_SML0_CLK [47] PCH_SML0_DAT [47]

LPC_AD0 [61] LPC_AD1 [61] LPC_AD2 [61] LPC_AD3 [61]

LPC_FRAME# [61]

1 2

RC52 8.2K_0402_5%

DIMM1, DIMM2, Security EEPROM, Click Pad

LAN

EC,dGPU,Thermal Sensor

1 2

RC47 0_0402_5%@

1 2

RC24 22_0402_5%EMC@

+3VS

1

TC18

CLK_PCI_EC [61]

GPP_C5, Internal PD 20K

*L: LPC H: eSPI

GPP_C5

B B

RPC22

10K_0804_8P4R_5%

A A

12

@

RC83 1K_0402_5%

1 2

@

RC350 20K_0402_5%

18

SERIRQ EC_SCI#

27 36 45

KBRST#

+3VALW_PCH

PCH_SML0_CLK PCH_SML0_DAT

PCH_SMB_CLK PCH_SMB_DATA PCH_SML1CLK PCH_SML1DATA

GPP_B23

1 2

RC92 499_0402_1%

1 2

RC93 499_0402_1%

1 2

RC395 2.2K_0402_1%

1 2

RC396 2.2K_0402_1%

1 2

RC397 2.2K_0402_1%

1 2

RC398 2.2K_0402_1%

RC101 150K_0402_5%

12

SB00000EO1J

2N7002KDWH_SOT363-6

+3VALW_PCH+3VS

PCH_SMB_CLK

+3VS

PCH_SMB_DATA PCH_SML1DATA

QC1A

6 1

D

S

G

2

5

G

3 4

S

D

QC1B 2N7002KDWH_SOT363-6

SB00000EO1J

PM_SMB_CLK [23,25,26,67]

1 2

RC106 4.7K_0402_5%

1 2

RC107 4.7K_0402_5%

PM_SMB_DAT [23,25,26,67]

+3VS

PCH_SML1CLK

2N7002KDWH_SOT363-6 QC2A

SB00000EO1J

6 1

D

S

G

2

5

G

3 4

S

D

QC2B

SB00000EO1J

2N7002KDWH_SOT363-6

EC_SMB_CK3 [28,60,61,66,68]

EC_SMB_DA3 [28,60,61,66,68]

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

3

2014/05/07

LC Future Center Secret Data

Deciphered Date

2

2015/05/07

Title

SKL(7/16):LPC/SPI/SMBUS/CL

Size Document Number Re v

Custom

Date: Sheet o f

BE560

Wednesday, September 23, 2015

1

11 99

0.1

5

4

3

2

1

D D

+3VS

PLTRST#[27]

1 2

EC_RSMRST#[61]

PCH_SYSPWROK[61]

PCH_PWROK[61]

EC_RSMRST#

C C

EC_DPWROK[61]

LANPHYPC[47]

RC108 10K_0402_5%

1 2

RC41 0_0402_5%

1 2

RC286 0_0402_5%@

1 2

RC373 0_0402_5%

1 2

RC109 0_0402_5%

2015051 4

+3VALW

B B

RPC18

1 8 2 7 3 6 4 5

1 2

RC399 10K_0402_5%

1 2

RC393 10K_0402_5%

1 2

RC351 10K_0402_5%

1 2

RC392 10K_0402_5%

AC_PRESENT BATLOW#

PCIE_WAKE# PCH_SLP_LAN#

10K_0804_8P4R_5%

PBTN_OUT#

@

PCH_SLP_WLAN#

GPD7

@

EC_DPWROK

@

T59

T21

PWROK

1

VCCST_PG_EC[61]

PLTRST# SYS_RESET#

EC_RSMRST#

H_CPUPWRGD VCCST_PWRGD

PCH_SYSPWROK PWROK

EC_DPWROK_R

SUSWARN# SUSACK#

PCIE_WAKE#

LANPHYPC GPD7

RC403 10K_0402_5%

@

1 2

UC1K

AN10

GPP_B13/PLTRST#

B5

SYS_RESET#

AY17

RSMRST#

A68

PROCPWRGD

B65

VCCST_PWRGD

B6

SYS_PWROK

BA20

PCH_PWROK

BB20

DSW_PWROK

AR13

GPP_A13/SUSWARN#/SUSPWRDNACK

AP11

GPP_A15/SUSACK#

BB15

WAKE#

AM15

GPD2/LAN_WAKE#

AW17

GPD11/LANPHYPC

AT15

GPD7/RSVD

SKYLAKE-U_BGA1356

REV = 1 @

RC436

VCCST_PWRGD_GD

1 2

0_0402_5%

+VCC_STG

RC401

1K_0402_5%

SKL_ ULT

SYSTEM POWER MANAGEMENT

+VCC_STG

12

RC410

1 2

60.4_0402_1%

RC123 10K_0402_5%@

15/0519

GPP_B12/SLP_S0#

GPD4/SLP_S3# GPD5/SLP_S4#

GPD10/SLP_S5#

SLP_SUS# SLP_LAN#

GPD9/SLP_WLAN#

GPD6/SLP_A#

GPD3/PWRBTN#

GPD1/ACPRESENT

GPD0/BATLOW#

GPP_A11/PME#

INTRUDER#

GPP_B11/EXT_PWR_GATE#

GPP_B2/VRALERT#

VCCST_PWRGDVCCST_PWRGD_GD

??11 OF 20

AT11 AP15 BA16 AY16

AN15 AW15 BB17 AN16

BA15 AY15 AU13

AU11 AP16

AM10 AM11

PM_SLP_S0# PM_SLP_S3# PM_SLP_S4# PM_SLP_S5#

PCH_SLP_SUS# PCH_SLP_LAN# PCH_SLP_WLAN# PM_SLP_A#

PBTN_OUT# AC_PRESENT

BATLOW#

PME# PCH_INTRUDER#

EXT_PWR_GATE# VRALERT#

1

TC20

PM_SLP_S3# [61] PM_SLP_S4# [61] PM_SLP_S5# [61]

1

TC21

PCH_SLP_LAN# [47,61] PCH_SLP_WLAN# [61] PM_SLP_A# [61]

PBTN_OUT# [61] AC_PRESENT [61]

1

TC120

RC16 1M_0402_5%

1

TC121

1

TC24

PLTRST#

RC26

100K_0402_5%

12

Connect to Power

UC3

1

NC

2

IN_A

3

12

GND

TC7SG17FE_SON5

+RTCVCC

OUT_Y

PM_SLP_S3# PM_SLP_S4# PM_SLP_S5#

PM_SLP_A#

PBTN_OUT#

+3VALW

5

VCC

4

1

TP125

1

TP126

1

TP127

1

TP128

1

TP129

1 2

RC348 33_0402_5%

1 2

RC48 33_0402_5%

100P_0402_25V8J

1

CC9

2

1

CC102 100P_0402_25V8J

2

PLTRST_NEAR# [23,47,51]

PLTRST_FAR# [50,61,69]

EC_RSMRST#

RC27 10K_0402_5%

1 2

A A

5

4

PCH_SYSPWROK PCH_PWROK EC_DPWROK

12

RC381 5P_0402_50V8-C

EMC_NS@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

3

12

RC382 5P_0402_50V8-C

EMC_NS@

2014/05/07

12

RC383 5P_0402_50V8-C

EMC_NS@

LC Future Center Secret Data

Deciphered Date

Title

2015/05/07

2

Title

SKL(8/16):SYSTEM PM

Size Document Number Re v

Custom

Date: Sheet o f

BE560

Wednesday, September 23, 2015

1

12 99

0.1

5

4

3

2

1

D D

C C

B B

+VCC_CORE +VCC_GT

[SKL PDG]VCC

[SKL PDG]22uF x9,10uF x7,1uF x15,47uF x8,10uFx8

10U_0603_6.3V6-M

CC136

12

1U_0201_6.3V6-M

CC170

1

2

1U_0201_6.3V6-M

CC190

1

2

1U_0201_6.3V6-M

CC200

1

2

1U_0201_6.3V6-M

CC209

1

2

10U_0603_6.3V6-M

CC137

12

1U_0201_6.3V6-M

CC171

1

2

1U_0201_6.3V6-M

CC191

1

2

1U_0201_6.3V6-M

CC201

1

2

CC218

12

10U_0603_6.3V6-M

CC138

CC172

CC192

CC202

10U_0603_6.3V6-M

CC140

CC139

12

1

2

1

2

1

2

CC123

12

1U_0201_6.3V6-M

CC174

CC173

1

2

1U_0201_6.3V6-M

CC194

CC193

1

2

1U_0201_6.3V6-M

CC203

CC204

1

2

10U_0603_6.3V6-M

CC221

12

10U_0603_6.3V6-M

CC141

1U_0201_6.3V6-M

CC175

1U_0201_6.3V6-M

CC195

1U_0201_6.3V6-M

CC205

10U_0603_6.3V6-M

CC222

12

CC143

CC142

1

12

2

1U_0201_6.3V6-M

CC177

CC176

1

2

1U_0201_6.3V6-M

1

2

1U_0201_6.3V6-M

1

2

10U_0603_6.3V6-M

CC223

1U_0201_6.3V6-M

CC197

CC196

1

2

1U_0201_6.3V6-M

CC206

CC207

1

2

10U_0603_6.3V6-M

CC225

CC224

12

1U_0201_6.3V6-M

10U_0603_6.3V6-M

1U_0201_6.3V6-M

CC145

CC144

1

2

1U_0201_6.3V6-M

CC179

CC178

1

2

1U_0201_6.3V6-M

CC198

CC199

1

2

1U_0201_6.3V6-M

CC208

1

2

10U_0603_6.3V6-M

12

[SKL PDG]VCCGT

[SKL PDG]10uF x10,1uF x12,47uF x6,22uFx12

10U_0603_6.3V6-M

CC129

12

1U_0201_6.3V6-M

CC146

1

2

1U_0201_6.3V6-M

CC160

1

2

10U_0603_6.3V6-M

CC130

12

1U_0201_6.3V6-M

CC147

1

2

1U_0201_6.3V6-M

CC161

1

2

10U_0603_6.3V6-M

CC131

CC133

12

1U_0201_6.3V6-M

CC148

CC150

CC149

1

2

1U_0201_6.3V6-M

CC151

1

2

1U_0201_6.3V6-M

CC152

1

2

1U_0201_6.3V6-M

CC153

CC154

1

2

CC156

CC155

1

2

1

2

1U_0201_6.3V6-M

CC157

1

2

1U_0201_6.3V6-M

CC158

CC159

1

2

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

3

2014/05/07

LC Future Center Secret Data

Deciphered Date

2

2015/05/07

Title

SKL(9/16):Decoupling

Size Document Number Re v

Custom

Date: Sheet o f

BE560

Wednesday, September 23, 2015

1

13 99

0.1

5

D D

4

3

2

1

?

SKL_ ULT

Project ID

PLANARID0 (GPP_C8)

L

14"

H

15"

15/0603

PLANARID0

DGPU_PWROK

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_C15/UART1_CTS#/ISH_UART1_CTS#

6 OF 20

(GPP_B5) PLANARID2

UMA

DIS

GPP_D5/ISH_I2C0_SDA GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA GPP_D8/ISH_I2C1_SCL

GPP_F10/I2C5_SDA/ISH_I2C2_SDA

GPP_F11/I2C5_SCL/ISH_I2C2_SCL

GPP_D15/ISH_UART0_RTS#

?

GPP_A12/BM_BUSY#/ISH_GP6

(GPP_C10)

1(X)

* *

12

RC67

10K_0402_5%

12

@

RC71

10K_0402_5%

GPP_D9 GPP_D10 GPP_D11 GPP_D12

GPP_A18/ISH_GP0 GPP_A19/ISH_GP1 GPP_A20/ISH_GP2 GPP_A21/ISH_GP3 GPP_A22/ISH_GP4 GPP_A23/ISH_GP5

DGPU_PWROK (GPP_A7)

15/0714

+3VS

12

RC70

10K_0402_5%

PLANARID1

12

@

RC74

10K_0402_5%

P2 P3 P4 P1

M4 N3

N1 N2

AD11 AD12

U1 U2 U3 U4

AC1 AC2 AC3 AB4

AY8 BA8 BB7 BA7 AY7 AW7 AP13

FN_LED# F1_LED#

FW_GPIO

1

RC427

1 2

0_0402_5%

TC118

CP_RESET#CP_RESET#_R

FN_LED# [64] F1_LED# [64]

FW_GPIO [38]

+3VS

12

@

RC434

10K_0402_5%

12

@

RC435

10K_0402_5%

CP_RESET# [61,67]

15/0708

GPP_B18, Internal PD 20K

*L: Disable ¨ No Reboot〃 mode H: Enable ¨ No Reboot〃 mode

GPP_B18

C C

+3VALW_PCH

RC376

1 2

10K_0402_5%

B B

+3VS

@

RC98 1K_0402_5%

@

RC97 20K_0402_5%

RF_OFF#

+3VALW_PCH +3VALW_PCH

12

CP_BYPASS[61,67]

TP_REST[61,67]

DGPU_PWROK[15,36,83]

15/0519

RPC9

PCH_TSOFF#

18

VGA_ON

27

DGPU_HOLD_RST#

36

BT_ON

45

10K_0804_8P4R_5%

GPP_B22, Internal PD 20K

*L: SPI H: LPC

GPP_B22

RF_OFF#[50]

PCH_CMOS_ON[38]

CP_BYPASS TP_REST

DGPU_HOLD_RST#[27]

BT_ON[50]

F4_LED#[64] PCH_TSOFF#[64]

VGA_ON[27,36,83]

15/0708

RC99 1K_0402_5%

1 2

RC100 20K_0402_5%

RF_OFF#

PCH_CMOS_ON

BT_ON

1 2

RC428 0_0402_5%

1 2

RC429 0_0402_5%

1 2

RC411 0_0402_5%

TP941 TP942

UART2_RX

1

UART2_TX

1

F4_LED# PCH_TSOFF#

PLANARID1

VGA_ON DGPU_HOLD_RST#

@

GPP_B18

GPP_B22

PLANARID0 CP_BYPASS_R

TP_REST_R

MIC_HW_EN

1 2

@

12

RC355 0_0402_5%

UC1F

AN8

GPP_B15/GSPI0_CS#

AP7

GPP_B16/GSPI0_CLK

AP8

GPP_B17/GSPI0_MISO

AR7

GPP_B18/GSPI0_MOSI

AM5

GPP_B19/GSPI1_CS#

AN7

GPP_B20/GSPI1_CLK

AP5

GPP_B21/GSPI1_MISO

AN5

GPP_B22/GSPI1_MOSI

AB1

GPP_C8/UART0_RXD

AB2

GPP_C9/UART0_TXD

W4

GPP_C10/UART0_RTS#

AB3

GPP_C11/UART0_CTS#

AD1

GPP_C20/UART2_RXD

AD2

GPP_C21/UART2_TXD

AD3

GPP_C22/UART2_RTS#

AD4

GPP_C23/UART2_CTS#

U7

GPP_C16/I2C0_SDA

U6

GPP_C17/I2C0_SCL

U8

GPP_C18/I2C1_SDA

U9

GPP_C19/I2C1_SCL

AH9

GPP_F4/I2C2_SDA

AH10

GPP_F5/I2C2_SCL

SKYLAKE-U_BGA1356

AH11

REV = 1

GPP_F6/I2C3_SDA

AH12

GPP_F7/I2C3_SCL

AF11

GPP_F8/I2C4_SDA

AF12

GPP_F9/I2C4_SCL

LPSS ISH

15/0519

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

3

2014/05/07

LC Future Center Secret Data

Deciphered Date

2

2015/05/07

Title

SKL(10/16):GPIO/CPU/MISC

Size Document Number Re v

Custom

Date: Sheet o f

BE560

Wednesday, September 23, 2015

1

14 99

0.1

5

4

3

2

1

3D camera

CR

HDD

ODD(NGFF)

GPU

SKL_ ULT

USB3.0 on board

ChargerPort

Sub/B Charger Port

SSIC / USB3

USB3_2_RXN/SSIC_1_RXN USB3_2_RXP/SSIC_1_RXP

USB3_2_TXN/SSIC_1_TXN USB3_2_TXP/SSIC_1_TXP

USB3_3_RXN/SSIC_2_RXN USB3_3_RXP/SSIC_2_RXP

USB3_3_TXN/SSIC_2_TXN USB3_3_TXP/SSIC_2_TXP

Docking

ONE DOCK

Touch Panel

USB2

BT

Camera

WWAN

FPR

Smart Card

GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2

USB3_1_RXN USB3_1_RXP

USB3_1_TXN USB3_1_TXP

USB3_4_RXN USB3_4_RXP

USB3_4_TXN USB3_4_TXP

USB2N_1 USB2P_1

USB2N_2 USB2P_2

USB2N_3 USB2P_3

USB2N_4 USB2P_4

USB2N_5 USB2P_5

USB2N_6 USB2P_6

USB2N_7 USB2P_7

USB2N_8 USB2P_8

USB2N_9 USB2P_9

USB2N_10 USB2P_10

USB2_COMP

USB2_ID

USB2_VBUSSENSE

GPP_E9/USB2_OC0# GPP_E10/USB2_OC1# GPP_E11/USB2_OC2# GPP_E12/USB2_OC3#

GPP_E4/DEVSLP0 GPP_E5/DEVSLP1 GPP_E6/DEVSLP2

GPP_E8/SATALED#

??8 OF 20

USB3P1_RXN

H8

USB3P1_RXP

G8

USB3P1_TXN

C13

USB3P1_TXP

D13

USB3P2_RXN

J6

USB3P2_RXP

H6

USB3P2_TXN

B13

USB3P2_TXP

A13

USB3P3_RXN

J10

USB3P3_RXP

H10

USB3P3_TXN

B15

USB3P3_TXP

A15

USB3P4_RXN

E10

USB3P4_RXP

F10

USB3P4_TXN

C15

USB3P4_TXP

D15

USB20_N1

AB9

USB20_P1

AB10

USB20_N2

AD6

USB20_P2

AD7

USB20_N3

AH3

USB20_P3

AJ3

USB20_N4

AD9

USB20_P4

AD10

USB20_N5

AJ1

USB20_P5

AJ2

USB20_N6

AF6

USB20_P6

AF7

USB20_N7

AH1

USB20_P7

AH2

USB20_N9

AF8

USB20_P9

AF9

AG1 AG2

AH7 AH8

AB6

USBCOMP

AG3 AG4

USB_OC0#

A9

USB_OC1#

C9

USB_OC2#

D9

USB_OC3#

B9

HDD_DEVSLP0

J1

SSD_DEVSLP1

J2

ODD_EN

J3

ODD_DA#

H2

ODD_DETEC#

H3

ONEDOCK_DET#

G4

H1

USB2_ID

USB2_VBUSSENSE

USB3P1_RXN [45] USB3P1_RXP [45] USB3P1_TXN [45] USB3P1_TXP [45]

USB3P2_RXN [45] USB3P2_RXP [45] USB3P2_TXN [45] USB3P2_TXP [45]

USB3P3_RXN [60] USB3P3_RXP [60] USB3P3_TXN [60] USB3P3_TXP [60]

USB3P4_RXN [60] USB3P4_RXP [60] USB3P4_TXN [60] USB3P4_TXP [60]

USB20_N1 [45] USB20_P1 [45]

USB20_N2 [45] USB20_P2 [45]

USB20_N3 [60] USB20_P3 [60]

USB20_N4 [60] USB20_P4 [60]

USB20_N5 [64] USB20_P5 [64]

USB20_N6 [50] USB20_P6 [50]

USB20_N7 [38] USB20_P7 [38]

USB20_N9 [65] USB20_P9 [65]

USB_OC0# [45] USB_OC1# [45] USB_OC2# [60]

HDD_DEVSLP0 [43]

1

TC27

ODD_DETEC# [44] ONEDOCK_DET# [60]

1 2

RC384 113_0402_1%

ODD_EN [44]

ODD_DA# [44]

On Board (Right-Front)

On Board (AOU Port)

S/B (Sub board)

20141024

Docking

20141024

On Board (Right-Front)

On Board (Right-Back)(AOU Port)

S/B

DOCKING

Touch Panel

BT

CAMERA

FPR

USB_OC0 #

USB_OC1 #

USB_OC2 #

USB_OC3 #

USB_OC0# USB_OC1# USB_OC2# USB_OC3#

ONEDOCK_DET#

USB Port Number

Port 1, Port2

Port 3, Port4

Port 5, Port6

Port 7, Port8

RPC15

18 27 36 45

10K_0804_8P4R_5%

1 2

RC372 10K_0402_5%

+3VALW_PCH

D D

1 1

USB3P5_RXN USB3P5_RXP USB3P5_TXN USB3P5_TXP

PCIE3_CRX_DTX_N PCIE3_CRX_DTX_P PCIE3_CTX_DRX_N PCIE3_CTX_DRX_P

PCIE4_CRX_DTX_N PCIE4_CRX_DTX_P PCIE4_CTX_DRX_N PCIE4_CTX_DRX_P

PCIE6_CTX_DRX_N PCIE6_CTX_DRX_P

SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 SATA_PTX_DRX_N0 SATA_PTX_DRX_P0

SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 SATA_PTX_DRX_N1 SATA_PTX_DRX_P1

PCIE_CRX_GTX_N0 PCIE_CRX_GTX_P0 PCIE1_PTX_DRX_N0 PCIE1_PTX_DRX_P0

PCIE_CRX_GTX_N1 PCIE_CRX_GTX_P1 PCIE2_PTX_DRX_N1 PCIE2_PTX_DRX_P1

PCIE_RCOMP

XDP_PRDY_N XDP_PREQ_N DGPU_PWROK_RDGPU_PWROK

PCIE_CRX_GTX_N2 PCIE_CRX_GTX_P2 PCIE3_PTX_DRX_N2 PCIE3_PTX_DRX_P2 PCIE_CRX_GTX_N3 PCIE_CRX_GTX_P3 PCIE4_PTX_DRX_N3 PCIE4_PTX_DRX_P3

USB3P5_RXN[38] USB3P5_RXP[38]

3D CCD

PCIE3_CRX_DTX_N[50]

WLAN

LAN

Card Reader

C C

HDD

ODD, only for 15"

GPU

DGPU_PWROK[14,36,83]

B B

PCIE3_CRX_DTX_P[50] PCIE3_CTX_C_DRX_N[50] PCIE3_CTX_C_DRX_P[50]

PCIE4_CRX_DTX_N[47]

PCIE4_CRX_DTX_P[47] PCIE4_CTX_C_DRX_N[47] PCIE4_CTX_C_DRX_P[47]

PCIE6_CRX_DTX_N[51]

PCIE6_CRX_DTX_P[51] PCIE6_CTX_C_DRX_N[51] PCIE6_CTX_C_DRX_P[51]

SATA_PRX_DTX_N0[43] SATA_PRX_DTX_P0[43]

SATA_PTX_DRX_N0[43]

SATA_PTX_DRX_P0[43]

SATA_PRX_DTX_N1[44] SATA_PRX_DTX_P1[44]

SATA_PTX_DRX_N1[44]

SATA_PTX_DRX_P1[44]

PCIE_CRX_GTX_N0[27]

PCIE_CRX_GTX_P0[27] PCIE_CTX_C_GRX_N0[27] PCIE_CTX_C_GRX_P0[27]

PCIE_CRX_GTX_N1[27]

PCIE_CRX_GTX_P1[27] PCIE_CTX_C_GRX_N1[27] PCIE_CTX_C_GRX_P1[27]

PCIE_CRX_GTX_N2[27]

PCIE_CRX_GTX_P2[27] PCIE_CTX_C_GRX_N2[27] PCIE_CTX_C_GRX_P2[27]

PCIE_CRX_GTX_N3[27]

PCIE_CRX_GTX_P3[27] PCIE_CTX_C_GRX_N3[27] PCIE_CTX_C_GRX_P3[27]

20141124

CC86 0.1U_0402_10V7-KDIS@ CC87 0.1U_0402_10V7-KDIS@

CC88 0.1U_0402_10V7-KDIS@ CC89 0.1U_0402_10V7-KDIS@

15/0603

CC90 0.1U_0402_10V7-KDIS@ CC23 0.1U_0402_10V7-KDIS@

CC24 0.1U_0402_10V7-KDIS@ CC91 0.1U_0402_10V7-KDIS@

USB3P5_TXN[38] USB3P5_TXP[38]

1 2 1 2

CC18 0.1U_0402_10V7-K CC19 0.1U_0402_10V7-K

1 2 1 2

CC92 0.1U_0402_10V7-K CC93 0.1U_0402_10V7-K

1 2 1 2

CC20 0.1U_0402_10V7-K CC21 0.1U_0402_10V7-K

1 2 1 2

1 2

RC385 100_0402_1%

TC25

@

1 2 1 2

TC26

1 2

RC402 0_0402_5%

UC1H

PCIE/US B3/ SATA

H13

PCIE1_RXN/USB3_5_RXN

G13

PCIE1_RXP/USB3_5_RXP

B17

PCIE1_TXN/USB3_5_TXN

A17

PCIE1_TXP/USB3_5_TXP

G11

PCIE2_RXN/USB3_6_RXN

F11

PCIE2_RXP/USB3_6_RXP

D16

PCIE2_TXN/USB3_6_TXN

C16

PCIE2_TXP/USB3_6_TXP

H16

PCIE3_RXN

G16

PCIE3_RXP

D17

PCIE3_TXN

C17

PCIE3_TXP

G15

PCIE4_RXN

F15

PCIE4_RXP

B19

PCIE4_TXN

A19

PCIE4_TXP

F16

PCIE5_RXN

E16

PCIE5_RXP

C19

PCIE5_TXN

D19

PCIE5_TXP

G18

PCIE6_RXN

F18

PCIE6_RXP

D20

PCIE6_TXN

C20

PCIE6_TXP

F20

PCIE7_RXN/SATA0_RXN

E20

PCIE7_RXP/SATA0_RXP

B21

PCIE7_TXN/SATA0_TXN

A21

PCIE7_TXP/SATA0_TXP

G21

PCIE8_RXN/SATA1A_RXN

F21

PCIE8_RXP/SATA1A_RXP

D21

PCIE8_TXN/SATA1A_TXN

C21

PCIE8_TXP/SATA1A_TXP

E22

PCIE9_RXN

E23

PCIE9_RXP

B23

PCIE9_TXN

A23

PCIE9_TXP

F25

PCIE10_RXN

E25

PCIE10_RXP

D23

PCIE10_TXN

C23

PCIE10_TXP

F5

PCIE_RCOMPN

E5

PCIE_RCOMPP

D56

PROC_PRDY#

D61

PROC_PREQ#

BB11

GPP_A7/PIRQA#

E28

PCIE11_RXN/SATA1B_RXN

E27

PCIE11_RXP/SATA1B_RXP

D24

PCIE11_TXN/SATA1B_TXN

C24

PCIE11_TXP/SATA1B_TXP

E30

PCIE12_RXN/SATA2_RXN

F30

PCIE12_RXP/SATA2_RXP

A25

PCIE12_TXN/SATA2_TXN

B25

PCIE12_TXP/SATA2_TXP

SKYLAKE-U_BGA1356

REV = 1 @

USB2_ID USB2_VBUSSENSE

15/05/18

RC406

1K_0402_5%

RC407

1K_0402_5%

1 2

12

RC386 5P_0402_50V8-C

EMC_NS@

ODD_DETEC#

HDD_DEVSLP0 ODD_DETEC#

ODD_DA#

RC88 10K_0402_5% RC86 10K_0402_5%

RC409 10K_0402_5%

12 12

12

+3VS

15/0519

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

3

2014/05/07

LC Future Center Secret Data

Deciphered Date

2

15/0714

DGPU_PWROK_R

2015/05/07

RC433 10K_0402_5%

12

Title

SKL(11/16):PCIE/USB/SATA

Size Document Number Re v

Custom

Date: Sheet o f

BE560

Wednesday, September 23, 2015

1

15 99

0.1

5

SKL_ ULT

AK33 AK35 AK37 AK38 AK40

AL33 AL37

AL40 AM32 AM33 AM35 AM37 AM38

AK32

AB62

AC63 AE63

AE62 AG62

AL63

AJ62

CC69

+VCC_SFROC+1.35V

CC257

A30 A34 A39 A44

G30

K32

P62 V62

H63

G61

1

2

1

2

100_0402_1%

UC1L

CPU POWER 1 OF 4

VCC_A30 VCC_A34 VCC_A39 VCC_A44 VCC_AK33 VCC_AK35 VCC_AK37 VCC_AK38 VCC_AK40 VCC_AL33 VCC_AL37 VCC_AL40 VCC_AM32 VCC_AM33 VCC_AM35 VCC_AM37 VCC_AM38 VCC_G30

RSVD_K32

RSVD_AK32

VCCOPC_AB62 VCCOPC_P62 VCCOPC_V62

VCC_OPC_1P8_H63

VCC_OPC_1P8_G61

VCCOPC_SENSE VSSOPC_SENSE

VCCEOPIO_AE62 VCCEOPIO_AG62

VCCEOPIO_SENSE VSSEOPIO_SENSE

SKYLAKE-U_BGA1356

REV = 1 @

RC197

1 2

1U_0402_10V6K

0_0603_5%

[SKL PDG]VCCPLL

[SKL PDG]1uF x1

1U_0402_10V6K

+VCC_GT

12

RC125

RC124 0_0402_5% RC183 0_0402_5%

12

RC184

+VCC_SFR+VCC_ST

CC70

1 2 1 2

1

2

+VCC_CORE +VCC_CORE

D D

C C

+VCC_STG +VCC_ST

1U_0402_10V6K

CC68

1

2

[SKL PDG]VCCSTG

B B

A A

[SKL PDG]1uF x1

CC94

1

2

[SKL PDG]VDDQC

[SKL PDG]1uF x1

+1.35V

1U_0402_10V6K

Primary side cap Primary side cap

[SKL PDG]VCCST

[SKL PDG]1uF x1

RC293

1 2

1U_0402_10V6K

1

2

Primary side cap

[SKL PDG]VCCPLL

[SKL PDG]1uF x1

VCCGT_SENSE[79]

0_0603_5%

VSSGT_SENSE[79]

CC256

5

1U_0402_10V6K

VCC_G32 VCC_G33 VCC_G35 VCC_G37 VCC_G38 VCC_G40 VCC_G42

VCC_J30 VCC_J33 VCC_J37

VCC_J40 VCC_K33 VCC_K35 VCC_K37 VCC_K38 VCC_K40 VCC_K42 VCC_K43

VCC_SENSE

VSS_SENSE

VIDALERT#

VIDSCK

VIDSOUT

VCCSTG_G20

+VCC_GT

4

G32 G33 G35 G37 G38 G40 G42 J30 J33 J37 J40 K33 K35 K37 K38 K40 K42 K43

E32 E33

B63 A63 D64

G20

??12 OF 20

UC1M

A48

VCCGT_A48

A53

VCCGT_A53

A58

VCCGT_A58

A62

VCCGT_A62

A66

VCCGT_A66

AA63

VCCGT_AA63

AA64

VCCGT_AA64

AA66

VCCGT_AA66

AA67

VCCGT_AA67

AA69

VCCGT_AA69

AA70

VCCGT_AA70

AA71

VCCGT_AA71

AC64

VCCGT_AC64

AC65

VCCGT_AC65

AC66

VCCGT_AC66

AC67

VCCGT_AC67

AC68

VCCGT_AC68

AC69

VCCGT_AC69

AC70

VCCGT_AC70

AC71

VCCGT_AC71

J43

VCCGT_J43

J45

VCCGT_J45

J46

VCCGT_J46

J48

VCCGT_J48

J50

VCCGT_J50

J52

VCCGT_J52

J53

VCCGT_J53

J55

VCCGT_J55

J56

VCCGT_J56

J58

VCCGT_J58

J60

VCCGT_J60

K48

VCCGT_K48

K50

VCCGT_K50

K52

VCCGT_K52

K53

VCCGT_K53

K55

VCCGT_K55

K56

VCCGT_K56

K58

VCCGT_K58

K60

VCCGT_K60

L62

VCCGT_L62

L63

VCCGT_L63

L64

VCCGT_L64

L65

VCCGT_L65

L66

VCCGT_L66

L67

VCCGT_L67

L68

VCCGT_L68

L69

VCCGT_L69

L70

VCCGT_L70

L71

VCCGT_L71

M62

VCCGT_M62

N63

VCCGT_N63

N64

VCCGT_N64

N66

VCCGT_N66

N67

VCCGT_N67

N69

VCCGT_N69

J70

VCCGT_SENSE

J69

VSSGT_SENSE

SKYLAKE-U_BGA1356

REV = 1 @

4

1 2

RC121 0_0402_5%

1 2

RC142 0_0402_5%

VR_SVID_ALRT#_R VR_SVID_CLK VR_SVID_DAT

+VCC_STG

SKL_ ULT

CPU POWER 2 OF 4

VCCGTX_SENSE VSSGTX_SENSE

VCCGT_N70 VCCGT_N71 VCCGT_R63 VCCGT_R64 VCCGT_R65 VCCGT_R66 VCCGT_R67 VCCGT_R68 VCCGT_R69 VCCGT_R70 VCCGT_R71

VCCGT_T62 VCCGT_U65 VCCGT_U68 VCCGT_U71

VCCGT_W63 VCCGT_W64 VCCGT_W65 VCCGT_W66 VCCGT_W67 VCCGT_W68 VCCGT_W69 VCCGT_W70 VCCGT_W71

VCCGT_Y62

VCCGTX_AK42 VCCGTX_AK43 VCCGTX_AK45 VCCGTX_AK46 VCCGTX_AK48 VCCGTX_AK50 VCCGTX_AK52 VCCGTX_AK53 VCCGTX_AK55 VCCGTX_AK56 VCCGTX_AK58 VCCGTX_AK60 VCCGTX_AK70

VCCGTX_AL43 VCCGTX_AL46 VCCGTX_AL50 VCCGTX_AL53 VCCGTX_AL56

VCCGTX_AL60 VCCGTX_AM48 VCCGTX_AM50 VCCGTX_AM52 VCCGTX_AM53 VCCGTX_AM56 VCCGTX_AM58 VCCGTX_AU58 VCCGTX_AU63 VCCGTX_BB57 VCCGTX_BB66

3

+VCC_CORE

12

RC120 100_0402_1%

SKL_ ULT

CPU POWER 3 OF 4

2014/05/07

VR_SVID_DAT

VR_SVID_CLK

VCCIO_AK28 VCCIO_AK30 VCCIO_AL30

VCCIO_AL42 VCCIO_AM28 VCCIO_AM30 VCCIO_AM42

VCCSA_AK23 VCCSA_AK25

VCCSA_G23 VCCSA_G25 VCCSA_G27 VCCSA_G28 VCCSA_J22 VCCSA_J23 VCCSA_J27 VCCSA_K23 VCCSA_K25 VCCSA_K27 VCCSA_K28 VCCSA_K30

VCCIO_SENSE VSSIO_SENSE

VSSSA_SENSE VCCSA_SENSE

LC Future Center Secret Data

VCC_SENSE [79]

RC143 100_0402_1%

CC226

12

CC232

12

10U_0603_6.3V6-M

VSS_SENSE [79]

Primary side cap

10U_0603_6.3V6-M

CC227

CC233

CC229

CC228

12

1U_0201_6.3V6-M

CC231

CC234

1

2

+1.35V

+VCC_ST

+VCC_STG

+VCC_SFROC

+VCC_SFR

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

3

+1.35V

10U_0603_6.3V6-M

12

1U_0201_6.3V6-M

1

2

CC230

12

1U_0201_6.3V6-M

CC235

1

2

[SKL PDG]VDDQ

[SKL PDG]10uF x6, 1uF x4

UC1N

AU23

VDDQ_AU23

AU28

VDDQ_AU28

AU35

VDDQ_AU35

AU42

VDDQ_AU42

BB23

VDDQ_BB23

BB32

VDDQ_BB32

BB41

VDDQ_BB41

BB47

VDDQ_BB47

BB51

VDDQ_BB51

AM40

VDDQC

A18

VCCST

A22

VCCSTG_A22

AL23

VCCPLL_OC

K20

VCCPLL_K20

K21

VCCPLL_K21

SKYLAKE-U_BGA1356

REV = 1 @

12

+VCC_GT

N70 N71 R63 R64 R65 R66 R67 R68 R69 R70 R71 T62 U65 U68 U71 W63 W64 W65 W66 W67 W68 W69 W70 W71 Y62

AK42 AK43 AK45 AK46 AK48 AK50 AK52 AK53 AK55 AK56 AK58 AK60 AK70 AL43 AL46 AL50 AL53 AL56 AL60 AM48 AM50 AM52 AM53 AM56 AM58 AU58 AU63 BB57 BB66

AK62 AL61

? ?13 OF 20

2

+VCC_ST

Rpu2

12

RC388 100_0402_1%

+VCC_ST

Rpu1

12

RC387 100_0402_1%@

+VCC_ST

Rpu1

12

RC20 56_0402_1%

Rs1

1 2

RC19 220_0402_1%

AK28 AK30 AL30 AL42 AM28 AM30 AM42

AK23 AK25 G23 G25 G27 G28 J22 J23 J27 K23 K25 K27 K28 K30

VCCIO_SENSE

AM23

VSSIO_SENSE

AM22

H21

RC185 0_0402_5%

H20

RC126 0_0402_5%

? ?14 OF 20

Deciphered Date

2

[SKL PDG]VIDSOUT

VR_SVID_DAT [79]

[SKL PDG]VIDSCK

VR_SVID_CLK [79]

VR_SVID_ALRT#VR_SVID_ALRT#_R

+VCC_IO

CC104

12

+VCC_SA

1 2 1 2

2015/05/07

[SKL PDG]VIDALERT#

VR_SVID_ALRT# [79]

[SKL PDG]VCCIO

[SKL PDG]10uF x2, 1uF x8

10U_0603_6.3V6-M

1U_0201_6.3V6-M

CC105

CC106

CC107

1

12

2

[SKL PDG]VCCSA

[SKL PDG]10uF x13, 1uF x7

10U_0603_6.3V6-M

CC236

12

10U_0603_6.3V6-M

CC247

12

RC192 100_0402_1% RC189 100_0402_1%

CC237

CC249

CC239

12

1U_0201_6.3V6-M

CC250

1

2

1 2 1 2

10U_0603_6.3V6-M

12

1U_0201_6.3V6-M

1

2

12

1

1U_0201_6.3V6-M

1

2

CC241

12

CC251

+VCC_SA

RC374 100_0402_1%

1U_0201_6.3V6-M

CC109

CC108

1

2

10U_0603_6.3V6-M

1U_0201_6.3V6-M

1

2

Title

Size Document Number Re v

Custom

Date: Sheet o f

10U_0603_6.3V6-M

CC245

CC244

12

1U_0201_6.3V6-M

CC253

CC252

1

2

+VCC_IO

12

RC375 100_0402_1%

SKL(12/16):POWER

Wednesday, September 23, 2015

CC254

1

2

VSSSA_SENSE [79]

VCCSA_SENSE [79]

BE560

CC255

1U_0201_6.3V6-M

1

2

16 99

1

16 99

0.1

5

D D

Reserve for Sense Resistor

+1.8VALW +1.8VALW_PCH

RC173 0_0603_5%

1 2

+3VALW +3VALW_PCH

RC341 0_0805_5%

1 2

+1VALW +1VALW_PCH

RC176

0_0805_5%

1 2

+1VALW +VCC_MPHYGT

JC5

112

JUMP_43X118

@

2

CC52 please close to N18

[SKL PDG]VccAPLLEBB

[SKL PDG]1uF x1 [SKL PDG]Close N18, Placement type:Edge<3mm(118mil)

SRAM Primary Well 1.0 V. Dedicated SRAM rail and can have on board power down gate control.

CC47 please close to AF20

20150 308

[SKL PDG]VccSRAM

[SKL PDG]1uF x1 [SKL PDG]Close AF20,

C C

+VCC_MPHYGT

+1VALW_PCH

1 2

LC1 0_0805_5%

1 2

LC2 0_0805_5%

+VCC_AMPHYPLL

1U_0402_10V6K

+VCC_AMPHYPLL

+1VALW_PLL

1

@

CC46

2

15/0520

Placement type:Edge<10mm(394mil)

please close to AG15 , Y16 & T16

+3VALW_PCH

1U_0402_10V6K

4

VccMPHYGT(Mod PHY Externally Gated Primary 1.0 V: Externally gated

+VCC_MPHYGT

1U_0402_10V6K

1

CC262

2

1

CC264

CC263

2

primary supply for PCIe/DMI/USB3/SATA/MIPI MPHY logic.)

1U_0402_10V6K

1

CC52

[SKL PDG]VccMPHYGT

2

[SKL PDG]1uF x1 [SKL PDG]Close N15, Placement type:Edge<3mm(118mil)

[SKL PDG]47uF x1 [SKL PDG]Close N15, Placement type:Edge<10mm(394mil)

Mod PHY Always On Primary 1.0 V: Always on primary supply for PCIe/DMI/USB3/SATA/MIPI MPHY logic

1U_0402_10V6K

1

@

CC47

2

[SKL PDG]VccMPHYAON

[SKL PDG]1uF x1 [SKL PDG]Close K17, Placement type:Edge<3mm(118mil)

Primary Well 1.0 V: For I/O blocks, ungated ISH SRAM power, USB AFE Digital Logic, JTAG, Thermal Sensor and MIPI DPHY.

CC50 & CC 258 please close to N15

CC49 please close to K17

CC95 please close to AB19

[SKL PDG]VCCPRIM

[SKL PDG]1uF x1 [SKL PDG]Close AB19, Placement type:Edge<10mm(394mil)

+VCC_MPHYGT

1U_0402_10V6K

+1VALW_PCH

1U_0402_10V6K

+1VALW_PCH

1U_0402_10V6K

3

+1VALW_PCH

15/0520

1

CC272 47U_0805_6.3V6-M

2

1

CC50

15/0520

1

CC258

2

47U_0805_6.3V6-M

2

1

CC49

2

1

CC95

2

15/0526

0.1U_0402_10V6-K

CC273

RF@

+VCC_HDA

CC274

RF@

1

2

1

CC271 47U_0805_6.3V6-M

2

+1VALW_PLL

1

2

+VCC_AMPHYPLL

+PCH_CORE

+DCPDSW

+VCC_MPHYGT

+VCC_DSW3P3

+3V_SPI

+3VALW_PRIM

UC1O

AB19

VCCPRIM_1P0_AB19

AB20

VCCPRIM_1P0_AB20

P18

VCCPRIM_1P0_P18

AF18

VCCPRIM_CORE_AF18

AF19

VCCPRIM_CORE_AF19

V20

VCCPRIM_CORE_V20

V21

VCCPRIM_CORE_V21

AL1

DCPDSW_1P0

K17

VCCMPHYAON_1P0_K17

L1

VCCMPHYAON_1P0_L1

N15

VCCMPHYGT_1P0_N15

N16

VCCMPHYGT_1P0_N16

N17

VCCMPHYGT_1P0_N17

P15

VCCMPHYGT_1P0_P15

P16

VCCMPHYGT_1P0_P16

K15

VCCAMPHYPLL_1P0_K15

L15

VCCAMPHYPLL_1P0_L15

V15

VCCAPLL_1P0

AB17

VCCPRIM_1P0_AB17

Y18

VCCPRIM_1P0_Y18

AD17

VCCDSW_3P3_AD17

AD18

VCCDSW_3P3_AD18

AJ17

VCCDSW_3P3_AJ17

AJ19

VCCHDA

AJ16

VCCSPI

AF20

VCCSRAM_1P0_AF20

AF21

VCCSRAM_1P0_AF21

T19

VCCSRAM_1P0_T19

T20

VCCSRAM_1P0_T20

AJ21

VCCPRIM_3P3_AJ21

AK20

VCCPRIM_1P0_AK20

N18

VCCAPLLEBB

SKYLAKE-U_BGA1356

REV = 1

@

2

SKL_ULT

CPU POWER 4 OF 4

1100mA

600mA

22mA

1500mA

88mA

26mA

118mA

68mA

565mA

75mA

33mA

VCCPGPPA

VCCPGPPB VCCPGPPC VCCPGPPD VCCPGPPE VCCPGPPF VCCPGPPG

VCCPRIM_3P3_V19

VCCPRIM_1P0_T1

VCCATS_1P8

VCCRTCPRIM_3P3

VCCRTC_AK19 VCCRTC_BB14

DCPRTC

VCCCLK1

VCCCLK2

VCCCLK3

VCCCLK4

VCCCLK5

VCCCLK6

GPP_B0/CORE_VID0 GPP_B1/CORE_VID1

1

85mA

+3VALW_PCH

161mA

+DCPRTC

+1VALW_CLK2

+1VALW_CLK4

+1VALW_CLK5

+1.8VALW_PCH

1 2

LC3

1 2

LC4

1 2

LC5

1 1

T56 T57

+3VALW_PRIM

0_0805_5%

15/0520

135mA

+1VALW_PCH

+1.8VALW_PCH

+3VALW_RTCPRIM

+RTCVCC

AK15 AG15 Y16 Y15 T16 AF16 AD15

V19

T1

AA1

AK17

AK19 BB14

BB10

A14

K19

L21

N20

L19

A10

AN11 AN13

??15 OF 20

Primary Well 3.3 V

B B

A A

5

+3VALW_PCH

[SKL PDG]VCCPRIM [SKL PDG]VccHDA

[SKL PDG]1uF x1 [SKL PDG]Close V19, Placement type:Edge<3mm(118mil)

RC326 0_0402_5%

+3VALW_PRIM +VCC_HDA

1 2

HD Audio Power 3.3 V, 1.8 V, 1.5 V. For Intel High Definition Audio.

+3VALW_PCH

1U_0402_10V6K

1

CC97

2

Core Logic Primary Well: This rail scales from 0.85 V to 1.0 V.

4

RC330 0_0402_5%

[SKL PDG]1uF x1 [SKL PDG]Close AJ19, Placement type:Edge<10mm(394mil)

+1VALW

[SKL PDG]VccPRIM_Core

[SKL PDG]1uF x1 [SKL PDG]Close AF18, Placement type:Edge<10mm(394mil)

1 2

+PCH_CORE

1 2

RC304 0_0805_5%

Thermal Sensor Primary Well 1.8 V

1U_0402_10V6K

1

CC99

2

Deep Sx Well for GPD GPIOs and USB2

1U_0402_10V6K

1

+3VALW_PCH

CC96

2

Deep Sx Well 1.0 V: This rail is generated by on die DSW

+1.8VALW_PCH

1U_0402_10V6K

[SKL PDG]VccATS [SKL PDG]DcpDSW [SKL PDG]DcpRTC

[SKL PDG]1uF x1 [SKL PDG]Close AA1, Placement type:Edge<10mm(394mil)

1 2

RC127 0_0402_5%@

+3VL +VCC_DSW3P3

1 2

RC132 0_0402_5%

[SKL PDG]VccDSW

3

low dropout (LDO) linear voltage regulator to supply DSW GPIOs, DSW core logic and DSW USB2 logic. Board needs to connect 1 uF capacitor to this rail and power should NOT be driven from the board. When primary well power is up, this rail is bypassed from VCCPRIM_1p0.

1

CC61

2

[SKL PDG]1uF x1 [SKL PDG]Close AL1, Placement type:Edge<3mm(118mil)

RTC Logic Primary Well 3.3 V. This power supplies the RTC internal VRM. It will be off during Deep Sx mode.

+3VALW_PCH

1 2

RC333 0_0402_5%

[SKL PDG]VccRTCPRIM

[SKL PDG]1uF x1,0.1uF x2 [SKL PDG]Close AK17, Placement type:Edge<3mm(118mil)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

+DCPDSW

1U_0402_10V6K

1

CC60

2

+3VALW_RTCPRIM

1U_0402_10V6K

1

2

2014/05/07

0.1U_0402_10V6-K

CC58

RTC de-coupling capacitor only. This rail should NOT be driven.

[SKL PDG]0.1uF x1 [SKL PDG]Close BB10, Placement type:Edge<3mm(118mil)

RTC Logic Primary Well 3.3 V. This power supplies the RTC internal VRM. It will be off during Deep Sx mode.

0.1U_0402_10V6-K

1

CC261

CC260

[SKL PDG]VccRTC

[SKL PDG]1uF x1

2

[SKL PDG]Close AK19, Placement type:Edge<3mm(118mil)

LC Future Center Secret Data

Deciphered Date

2

2015/05/07

+DCPRTC

1

CC259

0.1U_0402_10V6-K

2

+RTCVCC

1U_0402_10V6K

1

CC59

2

Title

SKL(13/16):POWER

Size

Document Number Re v

A2

BE560

Wednesday, September 23, 2015

Date: Sheet of

1

17 99

0.1

5

D D

4

3

2

1

UC1P

SKL_ ULT

GND 1 OF 3

A5

VSS_A5

A67

VSS_A67

A70

VSS_A70

AA2

VSS_AA2

AA4

VSS_AA4

AA65

VSS_AA65

AA68

VSS_AA68

AB15

VSS_AB15

AB16

VSS_AB16

AB18

VSS_AB18

AB21

VSS_AB21

AB8

VSS_AB8

AD13

VSS_AD13

AD16

VSS_AD16

AD19

VSS_AD19

C C

B B

AD20

VSS_AD20

AD21

VSS_AD21

AD62

VSS_AD62

AD8

VSS_AD8

AE64

VSS_AE64

AE65

VSS_AE65

AE66

VSS_AE66

AE67

VSS_AE67

AE68

VSS_AE68

AE69

VSS_AE69

AF1

VSS_AF1

AF10

VSS_AF10

AF15

VSS_AF15

AF17

VSS_AF17

AF2

VSS_AF2

AF4

VSS_AF4

AF63

VSS_AF63

AG16

VSS_AG16

AG17

VSS_AG17

AG18

VSS_AG18

AG19

VSS_AG19

AG20

VSS_AG20

AG21

VSS_AG21

AG71

VSS_AG71

AH13

VSS_AH13

AH6

VSS_AH6

AH63

VSS_AH63

AH64

VSS_AH64

AH67

VSS_AH67

AJ15

VSS_AJ15

AJ18

VSS_AJ18

AJ20

VSS_AJ20

AJ4

VSS_AJ4

AK11

VSS_AK11

AK16

VSS_AK16

AK18

VSS_AK18

AK21

VSS_AK21

AK22

VSS_AK22

AK27

VSS_AK27

AK63

VSS_AK63

AK68

VSS_AK68

AK69

VSS_AK69

AK8

VSS_AK8

AL2

VSS_AL2

AL28

VSS_AL28

AL32

VSS_AL32

AL35

VSS_AL35

AL38

VSS_AL38

AL4

VSS_AL4

AL45

VSS_AL45

AL48

VSS_AL48

AL52

VSS_AL52

AL55

VSS_AL55

AL58

VSS_AL58

AL64

VSS_AL64

SKYLAKE-U_BGA1356

REV = 1

VSS_AL65

VSS_AL66 VSS_AM13 VSS_AM21 VSS_AM25 VSS_AM27 VSS_AM43 VSS_AM45 VSS_AM46 VSS_AM55 VSS_AM60 VSS_AM61 VSS_AM68 VSS_AM71

VSS_AM8 VSS_AN20 VSS_AN23 VSS_AN28 VSS_AN30 VSS_AN32 VSS_AN33 VSS_AN35 VSS_AN37 VSS_AN38 VSS_AN40 VSS_AN42 VSS_AN58 VSS_AN63 VSS_AP10 VSS_AP18 VSS_AP20 VSS_AP23 VSS_AP28 VSS_AP32 VSS_AP35 VSS_AP38 VSS_AP42 VSS_AP58 VSS_AP63 VSS_AP68 VSS_AP70 VSS_AR11 VSS_AR15 VSS_AR16 VSS_AR20 VSS_AR23 VSS_AR28 VSS_AR35 VSS_AR42 VSS_AR43 VSS_AR45 VSS_AR46 VSS_AR48

VSS_AR5 VSS_AR50 VSS_AR52 VSS_AR53 VSS_AR55 VSS_AR58 VSS_AR63

VSS_AR8

VSS_AT2 VSS_AT20 VSS_AT23 VSS_AT28 VSS_AT35

VSS_AT4 VSS_AT42 VSS_AT56 VSS_AT58

16 OF 20

AL65 AL66 AM13 AM21 AM25 AM27 AM43 AM45 AM46 AM55 AM60 AM61 AM68 AM71 AM8 AN20 AN23 AN28 AN30 AN32 AN33 AN35 AN37 AN38 AN40 AN42 AN58 AN63 AP10 AP18 AP20 AP23 AP28 AP32 AP35 AP38 AP42 AP58 AP63 AP68 AP70 AR11 AR15 AR16 AR20 AR23 AR28 AR35 AR42 AR43 AR45 AR46 AR48 AR5 AR50 AR52 AR53 AR55 AR58 AR63 AR8 AT2 AT20 AT23 AT28 AT35 AT4 AT42 AT56 AT58

? ?

UC1Q

AT63

VSS_AT63

AT68

VSS_AT68

AT71

VSS_AT71

AU10

VSS_AU10

AU15

VSS_AU15

AU20

VSS_AU20

AU32

VSS_AU32

AU38

VSS_AU38

AV1

VSS_AV1

AV68

VSS_AV68

AV69

VSS_AV69

AV70

VSS_AV70

AV71

VSS_AV71

AW10

VSS_AW10

AW12

VSS_AW12

AW14

VSS_AW14

AW16

VSS_AW16

AW18

VSS_AW18

AW21

VSS_AW21

AW23

VSS_AW23

AW26

VSS_AW26

AW28

VSS_AW28

AW30

VSS_AW30

AW32

VSS_AW32

AW34

VSS_AW34

AW36

VSS_AW36

AW38

VSS_AW38

AW41

VSS_AW41

AW43

VSS_AW43

AW45

VSS_AW45

AW47

VSS_AW47

AW49

VSS_AW49

AW51

VSS_AW51

AW53

VSS_AW53

AW55

VSS_AW55

AW57

VSS_AW57

AW6

VSS_AW6

AW60

VSS_AW60

AW62

VSS_AW62

AW64

VSS_AW64

AW66

VSS_AW66

AW8

VSS_AW8

AY66

VSS_AY66

B10

VSS_B10

B14

VSS_B14

B18

VSS_B18

B22

VSS_B22

B30

VSS_B30

B34

VSS_B34

B39

VSS_B39

B44

VSS_B44

B48

VSS_B48

B53

VSS_B53

B58

VSS_B58

B62

VSS_B62

B66

VSS_B66

B71

VSS_B71

BA1

VSS_BA1

BA10

VSS_BA10

BA14

VSS_BA14

BA18

VSS_BA18

BA2

VSS_BA2

BA23

VSS_BA23

BA28

VSS_BA28

BA32

VSS_BA32

BA36

VSS_BA36

F68

VSS_F68

BA45

VSS_BA45

SKYLAKE-U_BGA1356

REV = 1

SKL_ ULT

GND 2 OF 3

VSS_BA49 VSS_BA53 VSS_BA57

VSS_BA6 VSS_BA62 VSS_BA66 VSS_BA71 VSS_BB18 VSS_BB26 VSS_BB30 VSS_BB34 VSS_BB38 VSS_BB43 VSS_BB55

VSS_BB6 VSS_BB60 VSS_BB64 VSS_BB67 VSS_BB70

VSS_C1

VSS_C25

VSS_C5 VSS_D10 VSS_D11 VSS_D14 VSS_D18 VSS_D22 VSS_D25 VSS_D26 VSS_D30 VSS_D34 VSS_D39 VSS_D44 VSS_D45 VSS_D47 VSS_D48 VSS_D53 VSS_D58

VSS_D6 VSS_D62 VSS_D66 VSS_D69 VSS_E11 VSS_E15 VSS_E18 VSS_E21 VSS_E46 VSS_E50 VSS_E53 VSS_E56

VSS_E6 VSS_E65 VSS_E71

VSS_F1 VSS_F13

VSS_F2 VSS_F22 VSS_F23 VSS_F27 VSS_F28 VSS_F32 VSS_F33 VSS_F35 VSS_F37 VSS_F38

VSS_F4 VSS_F40 VSS_F42

VSS_BA41

17 OF 20

BA49 BA53 BA57 BA6 BA62 BA66 BA71 BB18 BB26 BB30 BB34 BB38 BB43 BB55 BB6 BB60 BB64 BB67 BB70 C1 C25 C5 D10 D11 D14 D18 D22 D25 D26 D30 D34 D39 D44 D45 D47 D48 D53 D58 D6 D62 D66 D69 E11 E15 E18 E21 E46 E50 E53 E56 E6 E65 E71 F1 F13 F2 F22 F23 F27 F28 F32 F33 F35 F37 F38 F4 F40 F42 BA41

? ?

UC1R

SKL_ ULT

GND 3 OF 3

F8

VSS_F8

G10

VSS_G10

G22

VSS_G22

G43

VSS_G43

G45

VSS_G45

G48

VSS_G48

G5

VSS_G5

G52

VSS_G52

G55

VSS_G55

G58

VSS_G58

G6

VSS_G6

G60

VSS_G60

G63

VSS_G63

G66

VSS_G66

H15

VSS_H15

H18

VSS_H18

H71

VSS_H71

J11

VSS_J11

J13

VSS_J13

J25

VSS_J25

J28

VSS_J28

J32

VSS_J32

J35

VSS_J35

J38

VSS_J38

J42

VSS_J42

J8

VSS_J8

K16

VSS_K16

K18

VSS_K18

K22

VSS_K22

K61

VSS_K61

K63

VSS_K63

K64

VSS_K64

K65

VSS_K65

K66

VSS_K66

K67

VSS_K67

K68

VSS_K68

K70

VSS_K70

K71

VSS_K71

L11

VSS_L11

L16

VSS_L16

L17

VSS_L17

SKYLAKE-U_BGA1356

REV = 1

VSS_L18

VSS_L2

VSS_L20

VSS_L4

VSS_L8 VSS_N10 VSS_N13 VSS_N19 VSS_N21

VSS_N6 VSS_N65 VSS_N68 VSS_P17 VSS_P19 VSS_P20 VSS_P21 VSS_R13

VSS_R6

VSS_T15 VSS_T17 VSS_T18

VSS_T2

VSS_T21

VSS_T4 VSS_U10 VSS_U63 VSS_U64 VSS_U66 VSS_U67 VSS_U69 VSS_U70 VSS_V16 VSS_V17 VSS_V18

VSS_W13

VSS_W6

VSS_W9 VSS_Y17 VSS_Y19 VSS_Y20 VSS_Y21

18 OF 20

L18 L2 L20 L4 L8 N10 N13 N19 N21 N6 N65 N68 P17 P19 P20 P21 R13 R6 T15 T17 T18 T2 T21 T4 U10 U63 U64 U66 U67 U69 U70 V16 V17 V18 W13 W6 W9 Y17 Y19 Y20 Y21

??

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

3

2014/05/07

LC Future Center Secret Data

Deciphered Date

2

2015/05/07

Title

SKL(14/16):GND

Size Document Number Re v

Custom

Date: Sheet o f

BE560

Wednesday, September 23, 2015

1

18 99

0.1

5

D D

4

3

2

1

UC1I

C C

B B

A36

CSI2_DN0

B36

CSI2_DP0

C38

CSI2_DN1

D38

CSI2_DP1

C36

CSI2_DN2

D36

CSI2_DP2

A38

CSI2_DN3

B38

CSI2_DP3

C31

CSI2_DN4

D31

CSI2_DP4

C33

CSI2_DN5

D33

CSI2_DP5

A31

CSI2_DN6

B31

CSI2_DP6

A33

CSI2_DN7

B33

CSI2_DP7

A29

CSI2_DN8

B29

CSI2_DP8

C28

CSI2_DN9

D28

CSI2_DP9

A27

CSI2_DN10

B27

CSI2_DP10

C27

CSI2_DN11

D27

CSI2_DP11

SKYLAKE-U_BGA1356

REV = 1 @

SKL_ ULT

CSI-2

GPP_D4/FLASHTRIG

EMMC

GPP_F13/EMMC_DATA0 GPP_F14/EMMC_DATA1 GPP_F15/EMMC_DATA2 GPP_F16/EMMC_DATA3 GPP_F17/EMMC_DATA4 GPP_F18/EMMC_DATA5 GPP_F19/EMMC_DATA6 GPP_F20/EMMC_DATA7

GPP_F21/EMMC_RCLK

GPP_F22/EMMC_CLK

GPP_F12/EMMC_CMD

EMMC_RCOMP

CSI2_CLKN0 CSI2_CLKP0 CSI2_CLKN1 CSI2_CLKP1 CSI2_CLKN2 CSI2_CLKP2 CSI2_CLKN3 CSI2_CLKP3

CSI2_COMP

C37 D37 C32 D32 C29 D29 B26 A26

E13 B7

AP2 AP1 AP3 AN3 AN1 AN2 AM4 AM1

AM2 AM3 AP4

AT1

??9 OF 20

1 2

RC389 200_0402_1%

@

15/0521

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

3

2014/05/07

LC Future Center Secret Data

Deciphered Date

2

2015/05/07

Title

SKL(15/16):CSI-2/EMMC

Size Document Number Re v

Custom

Date: Sheet o f

BE560

Wednesday, September 23, 2015

1

19 99

0.1

5

4

3

2

1

D D

RESERVED SIGNALS-1

SKL_ ULT

SPARE

SKL_ ULT

RSVD_F6

RSVD_E3 RSVD_C11 RSVD_B11 RSVD_A11 RSVD_D12 RSVD_C12 RSVD_F52

RSVD_TP_BB68 RSVD_TP_BB69

RSVD_TP_AK13 RSVD_TP_AK12

RSVD_TP_AW71 RSVD_TP_AW70

PROC_SELECT#

F6 E3 C11 B11 A11 D12 C12 F52

??20 OF 20

RSVD_BB2 RSVD_BA3

RSVD_D5 RSVD_D4 RSVD_B2 RSVD_C2

RSVD_B3 RSVD_A3

RSVD_AW1

RSVD_E1 RSVD_E2

RSVD_BA4 RSVD_BB4

RSVD_A4 RSVD_C4

RSVD_A69 RSVD_B69

RSVD_AY3

RSVD_D71 RSVD_C70

RSVD_C54 RSVD_D54

VSS_AY71

ZVM#

MSM#

BB68 BB69

AK13 AK12

BB2 BA3

AU5

TP5

AT5

TP6

D5 D4 B2 C2

B3 A3

AW1

E1 E2

BA4 BB4

A4 C4

BB5

TP4

A69 B69

AY3

D71 C70

C54 D54

AY4

TP1

BB3

TP2

AY71 AR56

AW71 AW70

AP56 C64

??19 OF 20

1 1

1 1 1 1

1 1

1

1 1

1

1 1

1 2

RC296 0_0402_5%

RC295 0_0402_5%

1 2

1 1

1

1 1

1

[SKL CRB]

1

TC104

1

TC105

1

TC107

1

TC109

1

TC111

1

TC113

1

TC115

1

TC117

TC64

TC68 TC70

TC91 TC93

TC96

TC97 TC98

TC100

TC31 TC32

TC45 TC46

TC37 TC38

TC50 TC51

TC53 TC55 TC56 TC58

TC60 TC62

TC65 TC66

TC72 TC74

TC76

TC78 TC80

TC84 TC85

TC87 TC89

+VCC_ST

@

12

RC391 100K_0402_1%

UC1S

1

TC103 TC102 TC106 TC108 TC110 TC112 TC114 TC116

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1 1

CFG_RCOMP

ITP_PMODE

1 1

1

1 1

1

1 1 1 1 1 1 1 1

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15

CFG16 CFG17

CFG18 CFG19

TC30 TC43 TC44 TC33 TC34 TC35 TC36 TC47 TC48 TC39 TC49 TC40 TC41 TC42 TC52 TC54

TC57

[SKL CRB]

RC152 49.9_0402_1%

C C

B B

+1VALW_PCH

RC390 1.5K_0402_5%

12

TC59

TC61 TC63

TC67 TC69

TC71 TC73

TC75 TC77

TC79 TC81

TC82 TC83

TC86 TC88

TP92 TP93

TC94 TC95

TC99

15/0522

E68

CFG[0]

B67

CFG[1]

D65

CFG[2]

D67

CFG[3]

E70

CFG[4]

C68

CFG[5]

D68

CFG[6]

C67

CFG[7]

F71

CFG[8]

G69

CFG[9]

F70

CFG[10]

G68

CFG[11]

H70

CFG[12]

G71

CFG[13]

H69

CFG[14]

G70

CFG[15]

E63

CFG[16]

F63

CFG[17]

E66

CFG[18]

F66

CFG[19]

E60

CFG_RCOMP

E8

ITP_PMODE

AY2

RSVD_AY2

AY1

RSVD_AY1

D1

RSVD_D1

D3

RSVD_D3

K46

RSVD_K46

K45

RSVD_K45

AL25

RSVD_AL25

AL27

RSVD_AL27

C71

RSVD_C71

B70

RSVD_B70

F60

RSVD_F60

A52

RSVD_A52

BA70

RSVD_TP_BA70

BA68

RSVD_TP_BA68

J71

RSVD_J71

J68

RSVD_J68

F65

VSS_F65

G65

VSS_G65

F61

RSVD_F61

E61

RSVD_E61

SKYLAKE-U_BGA1356

REV = 1 @

AW69 AW68

AU56

AW48

C7 U12 U11 H11

UC1T

RSVD_AW69 RSVD_AW68 RSVD_AU56 RSVD_AW48 RSVD_C7 RSVD_U12 RSVD_U11 RSVD_H11

SKYLAKE-U_BGA1356

REV = 1 @

[SKL EDS]

CFG0

L:Stall. *H:(Default) Normal Operation; No stall.

RC105 1K_0402_5%@

RC201 1K_0402_1%@

CFG4

*L: Embedded DisplayPort Enabled H: Embedded DisplayPort Disabled

RC104 1K_0402_5%@

RC144 1K_0402_1%

TABLE

CFG0 : Stall Reset Sequence after PCU PLL Lock until de-asserted

1 : No Stall

0 : Stall

CFG4 : eDP Enable 1 : Disabled 0 : Enabled

CFG9 : SVID Bus Communication 1 : Enabled 0 : Disabled

ZVM# state

0V

1V

0V

1V

VCCOPC

0V

1V

MSM# state

X

0V

1V 1V

+VCC_IO

12

+VCC_IO

12

VCCEOPI O

0V

0.8V

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

3

2014/05/07

LC Future Center Secret Data

Deciphered Date

2

2015/05/07

Title

SKL(16/16):CFG/RESERVED

Size Document Number Re v

Custom

Date: Sheet o f

BE560

Wednesday, September 23, 2015

1

20 99

0.1

5

4

3

2

1

D D

C C

B B

Security ROM

USROM1

1

NC_1

2

PLTRST_NEAR#[12,47,51]

SPI_CS0#_8MB[11] SPI_CS1#_4MB[11]

PLTRST_NEAR#

[SKL]SPI0_CS0#: SPI FLASH SPI0_CS1#: SPI FLASH SPI0_CS2#: SPI TPM

SPI_CS0#_8MB

SPI_SO_8MB

SPI_IO2_8MB

NC_2

3

PROT#

4

GND

PCA24S08AD_SO8

SA00004MK00/SA00004ML00

@

feedback to SDV rev.. 15/0522

UC8M1

1

CS#

2

DO

3

WP#

4

GND

W25Q64FVSSIQ_SO8

2nd = SA00005VN00

SPI_IO3_8MB SPI_IO3 SPI_CLK_8MB SPI_SI_8MB SPI_IO2_8MB

VCC

WP

SCL

SDA

8MB(64Mb)

VCC

HOLD#

CLK

RPC23

1 8 2 7 3 6 4 5

33_0804_8P4R_5%

SD30000370T

8 7

PM_SMB_CLK

6

PM_SMB_DAT

5

8

7

6

5

DI

SPI_CLK SPI_SI SPI_IO2

+3V_SPI

SPI_IO3_8MB

SPI_CLK_8MB

SPI_SI_8MB

PM_SMB_CLK [11,25,26,67] PM_SMB_DAT [11,25,26,67]

+3V_SPI

1

CC25

0.1U_0402_10V7-K

2

SPI_IO3 [11]

SPI_CLK [11,69]

SPI_SI [11,69]

SPI_IO2 [11]

+3VS

1

CC22

0.1U_0402_10V6-K

@

2

SPI_IO3

+3V_SPI

RC117 1K_0402_5% RC118 1K_0402_5%

1 2

@

RC394 1K_0402_5%

1 2 1 2

SPI_IO2 SPI_IO3

M3 Support + Intel LAN PHY / Wireless LAN Solut i on

0.085 A

+3V_SPI

1

CC26

0.1U_0402_10V7-K

VPRO@

2

+3VALW

1 2

RC310 0_0402_5%

20141220

4MB(32Mb) for VPRO SKU

15/0525

SPI_CS1#_4MB SPI_SO_4MB SPI_IO2_4MB

Near SPI ROM

UC4M1

1

CS#

2

DO

3

WP#

4

GND

W25Q32FVSSIQ_SO8

VPRO@

SPI_IO3_4MB SPI_IO3 SPI_CLK_4MB SPI_SI_4MB SPI_IO2_4MB

33_0804_8P4R_5%

HOLD#

RPC24

1 8 2 7 3 6 4 5

SD30000370T

VPRO@

+3V_SPI

8

VCC

SPI_IO3_4MB

7

SPI_CLK_4MB

6

CLK

SPI_SI_4MB

5

DI

SPI_CLK SPI_SI SPI_IO2

Near SPI ROM

SPI_SO_8MB SPI_SO SPI_SO_4MB SPI_SO

1 2

RC103 33_0402_5%

SPI_SO [11,69]

1 2

VPRO@

RC102 33_0402_5%

Mirror Code

1 2

FSCE#[61] SPI_FMOSI#[61] SPI_FMISO[61] SPI_FSCK[61]

RC311 0_0402_5%

1 2

RC312 0_0402_5%

1 2

RC313 0_0402_5%

1 2

RC314 0_0402_5%

SPI_CS0#_8MB SPI_SI_8MB SPI_SO_8MB SPI_CLK_8MB

Close to SPI ROM (UC8M1).

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

3

2013/09/07

LC Future Center Secret Data

Deciphered Date

2

2014/09/07

Title

SPI ROM

Size Document Number Re v

Custom

Wednesday, September 23, 2015

Date: Sheet o f

BE560

1

23 99

0.1

5

4

3

2

1

12

RD9

1.8K_0402_1%

12

RD11

1.8K_0402_1%

+VREF_CA [26]

DDR_A_DQS#[0..7] [7]

DDR_A_DQS[0..7] [7]

DDR_A_D[0..31] [7]

DDR_A_MA[0..15] [7]

DDR_A_D[32..63] [7]

All VREF traces should have 10 mil trace width

RD10

1 2

2_0402_1%

1

2

12

CD12

0.022U_0402_25V7-K

RD12

24.9_0402_1%

SM_DIMM_VREFCA [7]

Layout Note: Place near JDIMM1

CD13

CD14

10U_0603_6.3V6-M

1

2

CD16

CD15

10U_0603_6.3V6-M

1

2

CD20

CD19

10U_0603_6.3V6-M

1

2

CD21

10U_0603_6.3V6-M

1

2

+1.35V

CD22

330U_D2_2V_Y

1

+

2

For RF solution.

CD9

CD10

CD11

CD8

1U_0402_6.3VA-K

@

1

2

DDR_PG_CTRL[7]

1U_0402_6.3VA-K

@

1

2

Layout Note: Place near JDIMM1.203,204

CD24

CD23

1U_0402_6.3VA-K

1

2

+1.35V

DDR_PG_CTRL

12

RD24 10K_0402_5%

@

1U_0402_6.3VA-K

1

2

CD25

1U_0402_6.3VA-K

@

1

2

CRF1

CRF2

2200P_0402_50V7-K

47P_0402_50V8-J

RF_NS@

1

2

+0.675VS

CD26

1U_0402_6.3VA-K

@

1

2

+3V_DDR +3VS

12

RD23 100K_0402_5%

SM_PG_CTRL

1

QD1 DTC115TMT2L_VMT3

3

take care the BOM P/N

@

RD25 100K_0402_5%

1 2

SM_PG_CTRL [86]

+1.35V

12

RD1

1.8K_0402_1%

12

1.8K_0402_1%

RD3

2.2U_0402_6.3V6-K

0.1U_0402_10V7-K

1

CD1

CD3

@

2

RD2

D D

SA_DIMM_VREFDQ[7]

1 2

1

2_0402_1%

CD2

0.022U_0402_25V7-K

2

12

RD4

24.9_0402_1%

Close to JDIMM1

C C

B B

A A

DDRA_CKE0_DIMMA[7]

DDR_A_BS2[7]

SA_CLK_DDR0[7] SA_CLK_DDR#0[7]

DDR_A_BS0[7]

DDR_A_WE#[7] DDR_A_CAS#[7]

DDRA_CS1_DIMMA#[7]

+3VS

+0.675VS +0.675VS

1

CD29

@

2.2U_0402_6.3V6-K

2

DDRA_CKE0_DIMMA

DDRA_CS1_DIMMA#

1

CD30

0.1U_0402_10V6-K

2

+1.35V +1.35V

RC315

0_0402_5%

11 13 15 17 19 21 23 25 27

33 35

39 41

45 47 49 51 53 55 57 59

63

67 69

73 75 77 79 81 83 85 87 89 91 93 95 97

99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203

205

JDIMM1

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS129RESET# VSS1131VSS12 DQ10 DQ11 VSS1337VSS14 DQ16 DQ17 VSS1543VSS16 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS2261DQS#3 DM3 VSS2365VSS24 DQ26 DQ27 VSS2571VSS26

CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1

G1

LCN_DAN06-K4406-0102

Channel A

+V_DDR_REFA

DDR_A_D0 DDR_A_D1

DDR_A_D2 DDR_A_D3

DDR_A_D8 DDR_A_D9

DDR_A_DQS#1 DDR_A_DQS1

DDR_A_D10 DDR_A_D11

DDR_A_D16 DDR_A_D17

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D18 DDR_A_D19

DDR_A_D24 DDR_A_D25

DDR_A_D26 DDR_A_D27

DDR_A_BS2

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8 DDR_A_MA5

DDR_A_MA3 DDR_A_MA1

SA_CLK_DDR0 SA_CLK_DDR#0

DDR_A_MA10 DDR_A_BS0

DDR_A_WE# DDR_A_CAS#

DDR_A_MA13

DDR_A_D32 DDR_A_D33

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_D42 DDR_A_D43

DDR_A_D48 DDR_A_D49

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D50 DDR_A_D51

DDR_A_D56 DDR_A_D57

DDR_A_D58 DDR_A_D59

RC316

0_0402_5%

1 2

VSS3

DQS#0

DQS0 VSS6

VSS8 DQ12 DQ13

VSS10

DQ14 DQ15

DQ20 DQ21

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

VSS31

DQ38 DQ39

VSS33

DQ44

DQ45 VSS35 DQS#5

DQS5 VSS38

DQ46

DQ47 VSS40

DQ52

DQ53 VSS42

VSS43

DQ54

DQ55 VSS45

DQ60

DQ61 VSS47 DQS#7

DQS7 VSS50

DQ62

DQ63 VSS52

EVENT#

VTT2

DQ4 DQ5

DQ6 DQ7

DM1

DM2

A15 A14

A11

CK1

BA1

S0#

NC2

DM4

DM6

SDA SCL

ME@

A7

A6 A4

A2 A0

G2

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

DDR_A_D4 DDR_A_D5

DDR_A_DQS#0 DDR_A_DQS0

DDR_A_D6 DDR_A_D7

DDR_A_D12 DDR_A_D13

DDR3_DRAMRST#

DDR_A_D14 DDR_A_D15

DDR_A_D20 DDR_A_D21

DDR_A_D22 DDR_A_D23

DDR_A_D28 DDR_A_D29

DDR_A_DQS#3 DDR_A_DQS3

DDR_A_D30 DDR_A_D31

DDRA_CKE1_DIMMA

DDR_A_MA15 DDR_A_MA14

DDR_A_MA11 DDR_A_MA7

DDR_A_MA6 DDR_A_MA4

DDR_A_MA2 DDR_A_MA0

SA_CLK_DDR1 SA_CLK_DDR#1

DDR_A_BS1 DDR_A_RAS#

DDRA_CS0_DIMMA# DDRA_ODT0_DIMMA#

DDRA_ODT1_DIMMA#

+VREF_CA

DDR_A_D36 DDR_A_D37

DDR_A_D38 DDR_A_D39

DDR_A_D44 DDR_A_D45

DDR_A_DQS#5 DDR_A_DQS5

DDR_A_D46 DDR_A_D47

DDR_A_D52 DDR_A_D53

DDR_A_D54 DDR_A_D55

DDR_A_D60 DDR_A_D61

DDR_A_DQS#7 DDR_A_DQS7

DDR_A_D62 DDR_A_D63

+1.35V

12

RD21 470_0402_5%

1

CD59

0.1U_0402_10V7-K

EMC_NS@

2

DDRA_CKE1_DIMMA [7]

SA_CLK_DDR1 [7] SA_CLK_DDR#1 [7]

DDR_A_BS1 [7] DDR_A_RAS# [7]

DDRA_CS0_DIMMA# [7] DDRA_ODT0_DIMMA# [7]

DDRA_ODT1_DIMMA# [7]

0.1U_0402_10V7-K

2.2U_0402_6.3V6-K

1

CD17

CD18

@

2

close to JDDR3L.126

PM_SMB_DAT [11,23,26,67] PM_SMB_CLK [11,23,26,67]

DDR3_DRAMRST# [8,26]

+1.35V

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

3

2013/09/07

LC Future Center Secret Data

Deciphered Date

2

2014/09/07

Title

DDR3L DIMM1

Size Document Number Re v

Custom

Wednesday, September 23, 2015

Date: Sheet o f

BE560

1

25 99

0.1

Lenovo E560,BE560 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual