Lenovo DG42A, DG52AMB Schematic

A

1 1

B

C D E

LCFC Confidential

2 2

DG42A/DG52AMB SchematicsDocument

Kabylake-U22/U23E with DDR4

3 3

2017-01-19

REV:1.0

4 4

Security Classification LC Future Center Secret Data

Issued Date

THIIIS SHEET OF ENGIIINEERING DRAWIIING IIIS THE PROPRIETA RY PRO PERTY OF LC FUTURE CE NTER. AN D CONTAIIINS CONFIDENTIIIAL
AND TRAD E SEC RET IIINFORMATIIION... THIIIS SHEE T MAY NOT BE TRAN SFERED FROM THE CUSTOD Y OF THE COMP ETENT DIVIIISIIION OF R& D
DEPAR TMENT EXCE PT AS AUTHORIZE D BY L C FUTURE CENTER NEIIITHER THIIIS SHEET N OR THE IIINFORMATIIION IIIT CONTAIIINS
MAY BE USED BY OR DISCLO SED TO A NY THIRD PARTY WIIITHOUT PRIO R W RITTEN CONSEN T OF LC FUTU RE CE NTER.

A

B

C D

2015/08/20 DecipheredDate

2016/08/20

Title

Cover Page

Siiize Document Number

Custom

DG42A

R ev

Sheet 1 of 60Date: Su nd ay , J an ua ry 22, 2017

E

1.0

A

LCFC confidential

B

C D E

DDR4 SO-DIMM x1

Page 18

Memory Bus (DualChannel)

1 1

HDMI Conn.

Page 34

eDPConn

Int. Camera Conn.

USB2.0 Po rt4

Int. MIC Conn.

2 2

Page 33

SATA HDD

Page 42 SATA Port0

HDMI (DDI1)

eDP x2 Lane
USB2.0 x1

SATA Gen3 x1

Intel MCP

KBL-U22/U23E 15W

BGA-1356

42mm*24mm

SATA ODD

Page 42 SATA Port1 A

SSD/Optane memory
(Optional)

Page 40 PCIe Po rt 9~12

SD/MMC Conn.

3 3

Page 31

SPK Conn.

Page 30

HP&Mic Combo Conn.

Page 30

Codec &C/R

Realtek RTS5119

Page 30

USB2.0 Port5

SATA Gen1 x1

USB2.0 x1

HD Audio

Page 3 ~16

LPC

1.2V DDR4 2133MT/s

USB3.0 x1
USB2.0 x1 USB3.0Port1

USB3.0 x1
USB2.0 x1 USB3.0Port3

USB3.0 x1
USB2.0 x1

USB2.0 x1

USB2.0 x1

PCIe Gen1 x1
USB2.0 x1

PCIe Gen1 x1

SPI

I2C

USB3.0 Left Conn

USB2.0Port1

USB3.0 Left Conn

USB2.0Port3

Type-C IC

Realtek RTS5449

Touch Screen (Optional)

USB2.0 Port6 Page 33

Finger Print (Optional)

USB2.0 Port7 Page 45

NGFFWLAN&BT

PCIe Po rt6
USB2.0 Port7

LAN Chip

Realtek_RTL8111GUL

PCIe Port5 Page 37

SPI ROM (8MB)

W25Q64FVSSIQ

Touch Pad

DDR4 Memory Down

4pcs x16

Page 41

Page 41

Page 43

Page 45

Type-C Conn

Page 40

Page 07

Page 43

RJ45 Conn.

Page 38

Page 17

EC

ITE IT8586E-LQFP

Page 44

TPM (Reserved)

Z32H320TC

Page 32

Sub-board( for 15" 17")

Int.KBD

Page 45

4 4

Security Classll ifii icii ation LC Future Center Secret Data

THISII SHEE T OF ENGINEEII RINGII DRAWINGII ISII THE PROPRIEII TARY PROP ERTY OF LC FUTUR E CENTER... AND CONTAINSII CONFIDEII NTIAL
AND TRADE SE CRET INFOII RMATION... THISII SHEE T MAY NOT BE TRANS FERED FROM THE CUSTOD Y OF THE C OMPE TENT DIVISIIII IOII N OF R&D
DEPARTMENT EX CEPT AS AUTHORIZII ED BY LC FUT URE CE NTER NEITHER THISII SHEE T NOR THE INFOII RMATION IT CONTAINSII

A

B

MAY BE USED BY OR DISII CLOSE D TO ANY THIRDII PARTY W ITHOUT PRIOII R WRITTEN CONSE NT OF LC F UTURE CE NTER.

Thermal Sensor (Reserved)

NCT7718W

Issued Date

C D

2015/08/20 Deciphered Date

Page 39

ODD BOARD

2016/08/20

Title

Block Diagram

Size DocumentttNum ber

Cust om

Dattte:

DG42A

Sunday, ,, Ja nua ry 22,,, 2017

Sheet 2 of 60

E

R ev

1.0

5

D D

AC
MO DE

BATT
MODE

C C

B B

A1

VIN

BATT

B1

V

PU301

V

4

B2

A2

+3VLP

V

V

A4 B5

+3VALW

V

A2

PU904

V

B+

EC

EC_ON

A3 B4

B3

VR_REDY

V

V

VR_ON

V

10

SUSP#,SUSP

ON/OFF
NOVO

11

PU901
+CPU_CORE

3 2 1

PCH_PWR_EN#

1

4

PM_SLP_S3#
PM_SLP_S4#
PM_SLP_S5#

V

PM_SLP_SUS#

12

13

SYSON 7

SUS_VCCP

5

2

DPWROK_EC

PCH_RSMRST#

PBTN_OUT#

PCH_PWROK

SYS_PWROK

9

8

6

V

V

V

Q25,+3V_PCH

V

V V V

V

V

+1.35V
PU501

V

Q31
+5VS

Q32
+3VS

PU602

V

+1.5VS

PU502
+0.675V

PU701

V

+1.05VS

3

V

+3V_PCH

PCH

NVDD_PWR_EN

(DIS)

Vb

DGPU_PWR_EN

(DIS)

Va

PM_DRAM_PWRGD

H_CPUPWRGD

CPU_PLTRST#16

+VGA_CORE

V

PU801

DGPU_PWROK

+1.5VS_VGA

V

PU601

+1.05VSP_VGA

V

PU702

+3VS_VGA

V

Q27

14

V

15

V

V

CPU

VV

VGA

V

V V

A A

Security Classification LC Future Center Secret Data

Issued Date

THIIIS SHEET OF ENGIIINEERING DRAWIIING IIIS THE PROPRIE TARY PR OPERTY OF LC FUTURE C ENTER. A ND CONTAIIINS CONFIDENTIIIAL
AND TRAD E SEC RET IIINFORMATIIION... THIIIS SHEE T MAY NOT BE TRAN SFERED FROM THE CUSTOD Y OF THE COMP ETENT DIVIIISIIION OF R& D
DEPAR TMENT EXCE PT AS AUTHORIZE D BY L C FUTURE CENTER NEIIITHER THIIIS SHEET N OR THE IIINFORMATIIION IIIT CONTAIIINS
MAY BE USED BY OR DISCLO SED TO A NY THIRD PARTY WIIITHOUT PRIO R WR ITTEN CONSEN T OF LC FUTU RE CE NTER.

5

4

3 2

2015/08/20 DecipheredDate

2016/08/20

Title

Power sequence block

Siiize Document Number

Custom

DG42A

R ev

47 of 60Date: Su nd ay , J an ua ry 22, 2017

Sheet

1

1.0

5

4

3

2

1

Silergy

D D

SUSP#

PMIC-LV5075AGQV

Converter

EN PGOOD

FOR PCH

+1.0 VALW/ 6A

B+

Silergy

SY8288CRAC

Adaptor

EC_ON

C C

EC_ON

Converter

FOR SYSTEM

PAGE 39

Silergy

SY8286BRAC
QFN20_3X3

Converter

FOR SYSTEM

EN

PAGE39

Richtek

PMIC-LV5075AGQV

S5
S3 Switch Mode

FOR DDR

TI

BQ24780SRUYR

SYSON

SUSP#

+5VLP/ 1 00mA

+5VA LW/6A

PGOODEN ALW_PWRGD

+3VLP/ 1 00mA

+3VALW/ 5A

ALW_PWRGDPGOOD

+1.2 V/7A

+0.6 VS/2A

PGOOD

ANPEC

PMIC-LV5075AGQV

+1.8 VALW/ 1A

PGOODEN

Battery Charger

Switch Mode

PAGE 46

SMBus

B B

SYSON

SUSP#

Battery

polymer

2S1P

VR_ON

Richtek

NB685GQ-Z

S5 QFN16_3X3
S3

Switch Mode

FOR DDR

Onsemi

NCP81206MNR2G
QFN60_7X7

Switch Mode

FOR CPU Core

EN

PGOOD

PGOOD

PGOOD_NB

+1.3 5V/8A

CPU Core/23A

VCCG T/25A

VCCS A/7A

VGATE

ANPEC

PMIC-LV5075AGQV

EN

+2.5 V/1A

PGOOD

RichTek

A A

EC_VR_ON

5

NB681GD-Z

VIDs

Switch Mode

EN

FOR GPU VDDC

4

PGOOD

VCC_ OPC/4 .5A

Security Classll ifii icii ation LC Future Center Secret Data

Issued Date

THIS SHEE T OF ENGINII EERINII G DRAWINII G IS THE PROPRIETAR Y PROPERTY OF L C FUTURE CENTER... AND CONTAINS CONFIDII ENTIAL
AND TRAD E SECRET INII FORMATIOII N... THIS SHEET MAY NOT BE TRANSF ERED FR OM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENT E XCEPT AS AUTHORIZII ED BY LC FUTURE CENTER NE ITHER THIS SHEET NOR THE INII FORMATIOII N ITIICONTAINS

3

MAY BE USED BY OR DIS CLOSED TO ANY THIRDII PARTY WITIIHOUT PRIOIIR WRITTIIEN CONSE NT OF LC FUTURE CENTER.

2015/08/20 Deciphered Date

2

2016/08/20

Title

PWR-Power Diagram

Siiize Documenttt Number

Cust om

Sunday, ,, Ja nua ry 22,,, 2017

Dattte:

DG42A

1

Sheet 50 of 60

R ev

1.0

A

B

C D E

Voltage Rails

( O --> MeansON

Power Plane

1 1

V20B+

State

S0

S3

S3

2 2

Battery only

S5 S4
AC Only

S5 S4

Battery only

O O O O

O O O X

O O O X

O O X X

O X X X

S5 S4

AC & Battery
don't exist

X X X X

SMBUS Control Table

SOURCE BATT Charger DGPU IT8586E

3 3

EC_SMB_C K1

EC_SMB_DA1

EC_SMB_C K2

EC_SMB_DA2

EC_SMB_C K3

EC_SMB_DA3

PCH_SMB _CLK

PCH_SMB_DATA

IT8586E

+3VL_EC

IT8586E

+3VS

IT8586E

+3VL_EC

PCH

+3VALW_PCH

V V X

X X

X X X

X X X X X

, X --> Means OFF )

+3VALW

+5VALW

+3VALW_PCH

+1.8VALW

+1.0VALW

+3VL_EC

V

+3VG_AONV+3VS

+3VL_EC

+1.2V

+2.5V_DDR

+VCCST

Memory
Down

V

X X X X X X

X

+3VALW_ PCH

V

X X V X X X

+3VALW_ PCH

+5VS

+3VS

+VCCIO

+VCCSTG

+VCCSA

+VCC_GT

+CPU_CO RE

+0.6VS

PCH PMIC SODIMM

V

V

X X V X

X

+3VS

V

Thermal
Sensor

X

WLAN
WiMAX

V

+3VS

HSIO PORT

USB3.0

USB2.0

PC IE

SA TA

STATE

Full ON HIGH HIGH HIGH ON ON ON ON

S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF OFF

S4 (Suspend to Disk) LOW LOW LOW ON OFF OFF OFF

S5 (Soft OFF) LOW LOW LOW ON OFF OFF OFF

1 USB3.0 Conn Left

2 USB Type-C

3 USB3.0 Conn Left

4 NC

5 NC

6 NC

1 USB3.0 Conn Left

2 USB Type-C

3 USB3.0 Conn Left

4 Finger Print

5 Cardrea der

6 Touch Panel

7 Bluetoo th

8 Camera

9 NC

10 NC

1~4

X4 PCIE

5 LAN

6 WLAN

7 SATA HDD

8 SATA ODD

9~12

X4 PCIE

0 HDD

1A ODD

1B used as PCIE

2 used as PCIE

SIGNAL

Function

DGPU

Optane Memory

SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

BOM Structure BTO Item

@
14 @
15 @

14or15@

14or17@

Cannonlake@
CD @
DUALMIC@
EM C@
EMC_15@
EMC_NS@
EMC_PX@
EMC_PXNS@
ES @
EX O@

ME @

NT S@

DI S@
OP T@
PX @
RANKA@
RANKB@

Realtek_SD@
SINGLEMIC@

SINGLERANK@
DUALRANK@
TS @
TP M@
UM A@

Not stuff

For 14" part

For 15" part

For 14" or 15" part

For 14" or 17" part

For Cannonlake part

For C cost down

For Dual MIC part

For EMC part

For EMC 15" part

For EMC nu-stuff part

For EMC PX part

For EMC PX nu-stuff part

For ES CPU

For EXO GPU

For ME part

For nu-touch part

For GPU part

For NV GPU part

For AMD GPU part

For VRAM rank A part

For VRAM rank B part

For Realtek SD part
For single MIC part

For single VRAN rank part

For dual VRAN rank part

For touch screen part

For TPM part

For UMA part

EC

SMBus1 address EC SMBus2 address EC SMBus3 address

Device

Smart Battery

4 4

Charger

Address

need to update
0001 0010 b

A

Device

Thermal Sensor(NCT7718W)

PCH
DGPU

Address

1001_100xb
need to update
need to update

Device

PMIC

B

Address

need to update

PCH

SM Bus address

Device

DDR4 SODIMM
Wlan

Securiiity Clllassiiifiiicatiiion

Issued Date

THISII SHEET OF ENGINII EERINII G DRAWINII G ISII THE PROPRIETARII Y PROPERTY OF LC FUTURE CENTER... AND CONTAINII S CONFIDII ENTIALII
AND TRADE SECRE T INII FORMATIONII ... TH ISII SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISIONIIIIIIOF R&D
DEPARTMENT EXCEPT AS AUTHORIZII ED BY LC FUTURE CENTER NEITII HER THISII SHEET NOR THE INII FORMATIONII ITII CONTAINSII
MAY BE USED BY OR DISCII LOSED TO ANY THIRDII PARTY WITII HOUT PRIORII WRITTII EN CONSENT OF LC FUTURE CENTER.

C D

Address

need to update
Reserved

2015/08/20 Deciphii ered Date

LC Future Center Secret Data

2016/08/20

Tit le

Notes List

Siiize Document Number

Custom

Sun day, Jan uary 22,2 017

Date:

DG42A

E

Sheet 3 of 60

R ev

1.0

5 4 3 2 1

?

HDMI D2

D D

C C

check PRO CHOT# circuit with PWR

44,55 H_PROCHOT#

HDMI D1
HDMI D0
HDMICLK

+VCCSTG

+VCCST_CPU

+VCCIO

1

RC19
1K_0402_5%

2

RC20 1 2 499 +-1%0402

1

RC143
1K_0402_5%

2

check H_THRMT RIP# if need to connector to EC

B B

34 HDMI_TX2­34 HDMI_TX2+
34 HDMI_TX1­34 HDMI_TX1+
34 HDMI_TX0­34 HDMI_TX0+
34 HDMI_CLK­34 HDMI_CLK+

34 DDPB_CLK
34 DDPB_DATA

RC155 1 2 49.9_0402_1%

RC156 1 2 49.9_0402_1%

U23E@ RC157 1
U23E@ RC170 1

1 24.9_0402_1%RC4 2

2 49.9_0402_1%
2 49.9_0402_1%

HDMI_TX2­HDMI_TX2+
HDMI_TX1­HDMI_TX1+
HDMI_TX0­HDMI_TX0+
HDMI_CLK­HDMI_CLK+

DDPB_CLK
DDPB_DATA

DDPC_CLK
DDPC_DATA

EDP_COMP PCH_ENVDD

+VCCIO&EDP_COMP :
Trace Width: 20mil
Isolation Spacing: 25mil
Max length: 100mil

+VCCST_CPU

1

RC1625

@

49.9_0402_1%

2

CATERR#

44 H_PECI

PAD @ TC11
PAD @ TC12
PAD @ TC13
PAD @ TC14

PAD @ TC162
PAD @ TC163

H_PECI
H_PROCHOT#_R
H_THRMTRIP#

XDP_BPM0#

1

XDP_BPM1#

1

XDP_BPM2#

1

XDP_BPM3#

1

GPP_E3

1

GPP_E7

1

PROC_OPI_RCOMP
PCH_OPI_RCOMP
EDRAM_OPIO_RCOMP
EOPIO_RCOMP

UC1A

E55

DDI1_TXN[0]

F55

DDI1_TXP[0]

E58

DDI1_TXN[1]

F58

DDI1_TXP[1]

F53

DDI1_TXN[2]

G53

DDI1_TXP[2]

F56

DDI1_TXN[3]

G56

DDI1_TXP[3]

C50

DDI2_TXN[0]

D50

DDI2_TXP[0]

C52

DDI2_TXN[1]

D52

DDI2_TXP[1]

A50

DDI2_TXN[2]

B50

DDI2_TXP[2]

D51

DDI2_TXN[3]

C51

DDI2_TXP[3]

L13

GPP_E18/DDPB_CT RLCLK

L12

GPP_E19/DDPB_CT RLDATA

N7

GPP_E20/DDPC_CTRLCLK

N8

GPP_E21/DDPC_CTRLDATA

N11

GPP_E22/DDPD_CTRLCLK

N12

GPP_E23/DDPD_CTRLDATA

E52

EDP_RCOMP

SKYLAKE-U_BGA1356

REV =1
@

D63

CATERR#

A54

PECI

C65

PROCHOT#

C63

THERMTRIP#

A65

SKTOCC#

C55

BPM#[0]

D55

BPM#[1]

B54

BPM#[2]

C56

BPM#[3]

A6

GPP_E3/CPU_GP0

A7

GPP_E7/CPU_GP 1

BA5

GPP_B3/CPU_GP2

AY5

GPP_B4/CPU_GP3

AT16

PROC_POPIRCOMP

AU16

PCH_OPIRCOMP

H66

OPCE_RCOMP

H65

OPC_RCOMP

SKYLAKE-U_BGA1356

REV =1
@

UC1D

SKL _ULT

DDI

DISPLAY SIDEB ANDS

SKL _ULT ?

CPU MISC

1 OF20

1 OF20

EDP

JTAG

PROC_TCK

PROC_TDI
PROC_TDO
PROC_TMS

PROC_TRST#

PCH_JTAG_TCK

PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS

PCH_TRST#

EDP_TXN[0]
EDP_TXP[0]
EDP_TXN[1]
EDP_TXP[1]
EDP_TXN[2]
EDP_TXP[2]

EDP_TXN[3]

EDP_TXP[3]

EDP_AUXN
EDP_AUXP

EDP_DISP_UTIL

DDI1_AUXN
DDI1_AUXP
DDI2_AUXN
DDI2_AUXP
DDI3_AUXN
DDI3_AUXP

GPP_E13/DDPB_H PD0
GPP_E14/DDPC_HPD1
GPP_E15/DDPD_HPD2
GPP_E16/DDPE_H PD3

GPP_E17/EDP_HPD

EDP_BKLTEN

EDP_BKLTCTL

EDP_VDDEN

B61
D60
A61
C60
B59

B56
D59

PCH_JTAG_TDO

A56

PCH_JTAG_TMS

C59

PCH_JTAG_TRST#

C61

A59 JTAGX 1

JTAGX

?

C47
C46
D46
C45
A45

B45

A47
B47

E45
F45

B52

G50

F50

E48

F48
G46
F46

L9
L7
L6

N9

L10

R12
R11
U13

?

XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#

PCH_JTAG_TCK
PCH_JTAG_TDI

1

CPU_EDP_TX0­CPU_EDP_TX0+
CPU_EDP_TX1­CPU_EDP_TX1+

CPU_EDP_AUX#
CPU_EDP_AUX

HDMI_HPD
GPP_E15
CPU_EDP_HPD
PCH_ENBKL

PCH_EDP_PWM

1

PAD@

TC15

1

PAD@

TC16

1

PAD@

TC17

PAD@

1

TC18

PAD@

1

TC27

1

1

1

PAD@

TC29

PAD@

1

TC31

PAD@

TC35

PAD@

TC36

PAD@

TC42

PAD@

TC43

CPU_EDP_TX0- 33
CPU_EDP_TX0+ 33
CPU_EDP_TX1- 33
CPU_EDP_TX1+ 33

CPU_EDP_AUX#
CPU_EDP_AUX

HDMI_HPD 34

RC181 1 @ 2

PCH_ENBKL 33
PCH_EDP_PWM 33
PCH_ENVDD 33

XDP_TCK

RC1546 1 @

XDP_TDO

RC1547 1 @

33

33

0_0402_5%

XDP_TDI
XDP_TMS
XDP_TRST#

+3VS

GPP_E15

RC1601 1 @ 2 10K_0402_5%

EC_SCI# 44

12

RC13
100K_0402_5%

2 0_0402_5% JT AGX RC1551 1 2 51_0402_5%

PCH_JTAG_TDO

2

0_0402_5%

2

RC1548 1 @
RC1549 1 @

RC15501 @ 2 0_0402_5%

0_0402_5%

2

0_0402_5%

PCH_JTAG_TRST#

CPU_EDP_HPD 33

RC1543 1 2 51_0402_5%

PCH_JTAG_TDI
PCH_JTAG_TMS

check JTAG circuit?

+VCCSTG

+3VS

DDP*_CTR LDATA strapping sample d on the rising edge of PWROK

Port Strap Enable Disable

Port 1 DDPB_CTRLDATA

Port 2 DDPC_CTRLDATA

A A

5 4 3 2

Pull up to 3. 3 V
with 2.2Kohm

Pull up to 3.3 V

with 2.2Kohm

NC

NC

check DDP C_CLK pull high or not?

RPC26

1
2

2.2K_0404_4P2R_5%

RPC27

1
2

2.2K_0404_4P2R_5%

Securiiity Clllassiiifiiicatiiion

Issued Date

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF LC FUTURE CENTER... AND CONTAIIINS CONFIIIDENTIIIAL
AND TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D
DEPARTMENT EXCEPT AS AUTHORIIIZED BY LC FUTURE CENTER NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIIT CONTAIIINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF LC FUTURE CENTER.

DDPC_CLK

4 @

DDPC_DATA Disable DDI2 G3 20 SDV wei

3

DDPB_CLK

4

DDPB_DATA

3

2015/08/20

LC Future Center Secret Data

Deciiiphered Date

2016/08/20

Tit le

MCP (DDI,EDP)

Siiize Document Number

Custom

Date: Su nda y, J anuar y22, 2017 Sheet 4 of 60

DG42A

1

R ev

1.0

5 4 3 2 1

?

17 DDRA_DQ[0..63]

D D

C C

B B

DDRA_DQ0
DDRA_DQ1
DDRA_DQ2
DDRA_DQ3
DDRA_DQ4
DDRA_DQ5
DDRA_DQ6
DDRA_DQ7
DDRA_DQ8
DDRA_DQ9
DDRA_DQ10
DDRA_DQ11
DDRA_DQ12
DDRA_DQ13
DDRA_DQ14
DDRA_DQ15
DDRA_DQ16
DDRA_DQ17
DDRA_DQ18
DDRA_DQ19
DDRA_DQ20
DDRA_DQ21
DDRA_DQ22
DDRA_DQ23
DDRA_DQ24
DDRA_DQ25
DDRA_DQ26
DDRA_DQ27
DDRA_DQ28
DDRA_DQ29
DDRA_DQ30
DDRA_DQ31
DDRA_DQ32
DDRA_DQ33
DDRA_DQ34
DDRA_DQ35
DDRA_DQ36
DDRA_DQ37
DDRA_DQ38
DDRA_DQ39
DDRA_DQ40
DDRA_DQ41
DDRA_DQ42
DDRA_DQ43
DDRA_DQ44
DDRA_DQ45
DDRA_DQ46
DDRA_DQ47
DDRA_DQ48
DDRA_DQ49
DDRA_DQ50
DDRA_DQ51
DDRA_DQ52
DDRA_DQ53
DDRA_DQ54
DDRA_DQ55
DDRA_DQ56
DDRA_DQ57
DDRA_DQ58
DDRA_DQ59
DDRA_DQ60
DDRA_DQ61
DDRA_DQ62
DDRA_DQ63

UC1B

AL71

DDR0_DQ[0]

AL68

DDR0_DQ[1]

AN68

DDR0_DQ[2]

AN69

DDR0_DQ[3]

AL70

DDR0_DQ[4]

AL69

DDR0_DQ[5]

AN70

DDR0_DQ[6]

AN71

DDR0_DQ[7]

AR70

DDR0_DQ[8]

AR68

DDR0_DQ[9]

AU71

DDR0_DQ[10]

AU68

DDR0_DQ[11]

AR71

DDR0_DQ[12]

AR69

DDR0_DQ[13]

AU70

DDR0_DQ[14]

AU69

DDR0_DQ[15]

BB65

DDR0_DQ[16]/DDR0_DQ[32]

AW65

DDR0_DQ[17]/DDR0_DQ[33]

AW63

DDR0_DQ[18]/DDR0_DQ[34]

AY63

DDR0_DQ[19]/DDR0_DQ[35]

BA65

DDR0_DQ[20]/DDR0_DQ[36]

AY65

DDR0_DQ[21]/DDR0_DQ[37]

BA63

DDR0_DQ[22]/DDR0_DQ[38]

BB63

DDR0_DQ[23]/DDR0_DQ[39]

BA61

DDR0_DQ[24]/DDR0_DQ[40]

AW61

DDR0_DQ[25]/DDR0_DQ[41]

BB59

DDR0_DQ[26]/DDR0_DQ[42]

AW59

DDR0_DQ[27]/DDR0_DQ[43]

BB61

DDR0_DQ[28]/DDR0_DQ[44]

AY61

DDR0_DQ[29]/DDR0_DQ[45]

BA59

DDR0_DQ[30]/DDR0_DQ[46]

AY59

DDR0_DQ[31]/DDR0_DQ[47]

AY39

DDR0_DQ[32]/DDR1_DQ[0]

AW39

DDR0_DQ[33]/DDR1_DQ[1]

AY37

DDR0_DQ[34]/DDR1_DQ[2]

AW37

DDR0_DQ[35]/DDR1_DQ[3]

BB39

DDR0_DQ[36]/DDR1_DQ[4]

BA39

DDR0_DQ[37]/DDR1_DQ[5]

BA37

DDR0_DQ[38]/DDR1_DQ[6]

BB37

DDR0_DQ[39]/DDR1_DQ[7]

AY35

DDR0_DQ[40]/DDR1_DQ[8]

AW35

DDR0_DQ[41]/DDR1_DQ[9]

AY33

DDR0_DQ[42]/DDR1_DQ[10]

AW33

DDR0_DQ[43]/DDR1_DQ[11]

BB35

DDR0_DQ[44]/DDR1_DQ[12]

BA35

DDR0_DQ[45]/DDR1_DQ[13]

BA33

DDR0_DQ[46]/DDR1_DQ[14]

BB33

DDR0_DQ[47]/DDR1_DQ[15]

AY31

DDR0_DQ[48]/DDR1_DQ[32]

AW31

DDR0_DQ[49]/DDR1_DQ[33]

AY29

DDR0_DQ[50]/DDR1_DQ[34]

AW29

DDR0_DQ[51]/DDR1_DQ[35]

BB31

DDR0_DQ[52]/DDR1_DQ[36]

BA31

DDR0_DQ[53]/DDR1_DQ[37]

BA29

DDR0_DQ[54]/DDR1_DQ[38]

BB29

DDR0_DQ[55]/DDR1_DQ[39]

AY27

DDR0_DQ[56]/DDR1_DQ[40]

AW27

DDR0_DQ[57]/DDR1_DQ[41]

AY25

DDR0_DQ[58]/DDR1_DQ[42]

AW25

DDR0_DQ[59]/DDR1_DQ[43]

BB27

DDR0_DQ[60]/DDR1_DQ[44]

BA27

DDR0_DQ[61]/DDR1_DQ[45]

BA25

DDR0_DQ[62]/DDR1_DQ[46]

BB25

DDR0_DQ[63]/DDR1_DQ[47]

SKYLAKE-U_BGA1356

REV =1
@

SKL _ULT

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]

DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#
DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]

DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]

DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]

DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]

DDRCH - A

+3VALW

12

RC30
100K_0402_5%

DDR0_DQSN[2]/DDR0_DQSN[4]
DDR0_DQSP[2]/DDR0_DQSP[4]
DDR0_DQSN[3]/DDR0_DQSN[5]
DDR0_DQSP[3]/DDR0_DQSP[5]
DDR0_DQSN[4]/DDR1_DQSN[0]
DDR0_DQSP[4]/DDR1_DQSP[0]
DDR0_DQSN[5]/DDR1_DQSN[1]
DDR0_DQSP[5]/DDR1_DQSP[1]
DDR0_DQSN[6]/DDR1_DQSN[4]
DDR0_DQSP[6]/DDR1_DQSP[4]
DDR0_DQSN[7]/DDR1_DQSN[5]
DDR0_DQSP[7]/DDR1_DQSP[5]

DDR0_VREF_DQ
DDR1_VREF_DQ

1 OF20

DDR_VTT_CNTL

DDR0_CKN[0]
DDR0_CKP[0]
DDR0_CKN[1]
DDR0_CKP[1]

DDR0_CKE[0]
DDR0_CKE[1]
DDR0_CKE[2]
DDR0_CKE[3]

DDR0_CS#[0]
DDR0_CS#[1]
DDR0_ODT[0]
DDR0_ODT[1]

DDR0_MA[3]
DDR0_MA[4]

DDR0_DQSN[0]
DDR0_DQSP[0]
DDR0_DQSN[1]
DDR0_DQSP[1]

DDR0_ALERT#

DDR0_PAR

DDR_VREF_CA

AU55
AT55

BB56
AW56
AY56

AU43
AT43

AY54

AM69
AT69
AT70

BA64
AY64
AY60
BA60
BA38
AY38
AY34
BA34
BA30
AY30
AY26
BA26

AY68

?

AU53
AT53

BA56

AU45

AT45

BA51
BB54
BA52
AY52
AW52
AY55
AW54
BA54
BA55

AU46
AU48
AT46
AU50
AU52
AY51
AT48
AT50
BB50
AY50
BA50
BB52

AM70

DDRA_DQS0
DDRA_DQS#1
DDRA_DQS1
DDRA_DQS#2

DDRA_DQS2
DDRA_DQS#3
DDRA_DQS3

DDRA_DQS#4
DDRA_DQS4
DDRA_DQS#5
DDRA_DQS5

DDRA_DQS#6
DDRA_DQS6
DDRA_DQS#7
DDRA_DQS7

AW50

AT52

AY67

BA67

AW67

DDRA_DQS#0

DDR_VTT_CNTL

17

DDRA_CLK0#

17

DDRA_CLK0

DDRA_CKE0 17

DDRA_CS0# 17
DDRA_ODT0 17

17

DDRA_MA5

17

DDRA_MA9

17

DDRA_MA6

17

DDRA_MA8

17

DDRA_MA7

17

DDRA_BG0

17

DDRA_MA12
DDRA_MA11 17
DDRA_ACT# 17

DDRA_MA13 17
DDRA_MA15_CAS#
DDRA_MA14_WE#
DDRA_MA16_RAS#

17

DDRA_BS0#

17

DDRA_MA2

17

DDRA_BS1#

17

DDRA_MA10

17

DDRA_MA1

17

DDRA_MA0

17

DDRA_MA3

17

DDRA_MA4

DDRA_ALERT# 17

DDRA_PAR 17
DDR_SA_VREFCA 17
DDR_SB_VREFCA 18

17

17

17

DDRA_DQS#[0..7]
DDRA_DQS[0..7]

DDRA_DQS#[0..7] 17
DDRA_DQS[0..7] 17

SMVREF

WIDTH:20MIL

SPACING: 20MIL

+1.2V

RC3 1 2 2

1K_0402_5%

DDR_VTT_CNTL

A A

5 4 3 2

B

RC29 @

10K_0402_5%

C

QC18

E

3 1

MMBT3904WH_SOT323-3

1 2

CPU_DRAMPG_CNTL 55

Securiiity Clllassiiifiiicatiiion

Issued Date

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF LC FUTURE CENTER... AND CONTAIIINS CONFIIIDENTIIIAL
AND TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D
DEPARTMENT EXCEPT AS AUTHORIIIZED BY LC FUTURE CENTER NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIIT CONTAIIINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF LC FUTURE CENTER.

2015/08/20

LC Future Center Secret Data

Deciiiphered Date

2016/08/20

Tit le

MCP (DDR4)

Siiize Document Number

Custom

Date: Su nda y, J anuar y22, 2017 Sheet 5 of 60

DG42A

1

R ev

1.0

5

18 DDRB_DQ[0..63]

D D

C C

B B

4

DDRB_DQ0
DDRB_DQ1
DDRB_DQ2
DDRB_DQ3
DDRB_DQ4
DDRB_DQ5
DDRB_DQ6
DDRB_DQ7
DDRB_DQ8
DDRB_DQ9
DDRB_DQ10
DDRB_DQ11
DDRB_DQ12
DDRB_DQ13
DDRB_DQ14
DDRB_DQ15
DDRB_DQ16
DDRB_DQ17
DDRB_DQ18
DDRB_DQ19
DDRB_DQ20
DDRB_DQ21
DDRB_DQ22
DDRB_DQ23
DDRB_DQ24
DDRB_DQ25
DDRB_DQ26
DDRB_DQ27
DDRB_DQ28
DDRB_DQ29
DDRB_DQ30
DDRB_DQ31
DDRB_DQ32
DDRB_DQ33
DDRB_DQ34
DDRB_DQ35
DDRB_DQ36
DDRB_DQ37
DDRB_DQ38
DDRB_DQ39
DDRB_DQ40
DDRB_DQ41
DDRB_DQ42
DDRB_DQ43
DDRB_DQ44
DDRB_DQ45
DDRB_DQ46
DDRB_DQ47
DDRB_DQ48
DDRB_DQ49
DDRB_DQ50
DDRB_DQ51
DDRB_DQ52
DDRB_DQ53
DDRB_DQ54
DDRB_DQ55
DDRB_DQ56
DDRB_DQ57
DDRB_DQ58
DDRB_DQ59
DDRB_DQ60
DDRB_DQ61
DDRB_DQ62
DDRB_DQ63

UC1C

AF65

DDR1_DQ[0]/DDR 0_DQ[ 16]

AF64

DDR1_DQ[1]/DDR 0_DQ[ 17]

AK65

DDR1_DQ[2]/DDR 0_DQ[ 18]

AK64

DDR1_DQ[3]/DDR 0_DQ[ 19]

AF66

DDR1_DQ[4]/DDR 0_DQ[ 20]

AF67

DDR1_DQ[5]/DDR 0_DQ[ 21]

AK67

DDR1_DQ[6]/DDR 0_DQ[ 22]

AK66

DDR1_DQ[7]/DDR 0_DQ[ 23]

AF70

DDR1_DQ[8]/DDR 0_DQ[ 24]

AF68

DDR1_DQ[9]/DDR0_DQ[ 25]

AH71

DDR1_DQ[10]/DDR0_DQ [26]

AH68

DDR1_DQ[11]/DDR0_DQ [27]

AF71

DDR1_DQ[12]/DDR0_DQ [28]

AF69

DDR1_DQ[13]/DDR0_DQ [29]

AH70

DDR1_DQ[14]/DDR0_DQ [30]

AH69

DDR1_DQ[15]/DDR0_DQ [31]

AT66

DDR1_DQ[16]/DDR0_DQ [48]

AU66

DDR1_DQ[17]/DDR0_DQ [49]

AP65

DDR1_DQ[18]/DDR0_DQ [50]

AN65

DDR1_DQ[19]/DDR0_DQ [51]

AN66

DDR1_DQ[20]/DDR0_DQ [52]

AP66

DDR1_DQ[21]/DDR0_DQ [53]

AT65

DDR1_DQ[22]/DDR0_DQ [54]

AU65

DDR1_DQ[23]/DDR0_DQ [55]

AT61

DDR1_DQ[24]/DDR0_DQ [56]

AU61

DDR1_DQ[25]/DDR0_DQ [57]

AP60

DDR1_DQ[26]/DDR0_DQ [58]

AN60

DDR1_DQ[27]/DDR0_DQ [59]

AN61

DDR1_DQ[28]/DDR0_DQ [60]

AP61

DDR1_DQ[29]/DDR0_DQ [61]

AT60

DDR1_DQ[30]/DDR0_DQ [62]

AU60

DDR1_DQ[31]/DDR0_DQ [63]

AU40

DDR1_DQ[32]/DDR1_DQ [16]

AT40

DDR1_DQ[33]/DDR1_DQ [17]

AT37

DDR1_DQ[34]/DDR1_DQ [18]

AU37

DDR1_DQ[35]/DDR1_DQ [19]

AR40

DDR1_DQ[36]/DDR1_DQ [20]

AP40

DDR1_DQ[37]/DDR1_DQ [21]

AP37

DDR1_DQ[38]/DDR1_DQ [22]

AR37

DDR1_DQ[39]/DDR1_DQ [23]

AT33

DDR1_DQ[40]/DDR1_DQ [24]

AU33

DDR1_DQ[41]/DDR1_DQ [25]

AU30

DDR1_DQ[42]/DDR1_DQ [26]

AT30

DDR1_DQ[43]/DDR1_DQ [27]

AR33

DDR1_DQ[44]/DDR1_DQ [28]

AP33

DDR1_DQ[45]/DDR1_DQ [29]

AR30

DDR1_DQ[46]/DDR1_DQ [30]

AP30

DDR1_DQ[47]/DDR1_DQ [31]

AU27

DDR1_DQ[48]

AT27

DDR1_DQ[49]

AT25

DDR1_DQ[50]

AU25

DDR1_DQ[51]

AP27

DDR1_DQ[52]

AN27

DDR1_DQ[53]

AN25

DDR1_DQ[54]

AP25

DDR1_DQ[55]

AT22

DDR1_DQ[56]

AU22

DDR1_DQ[57]

AU21

DDR1_DQ[58]

AT21

DDR1_DQ[59]

AN22

DDR1_DQ[60]

AP22

DDR1_DQ[61]

AP21

DDR1_DQ[62]

AN21

DDR1_DQ[63]

SKYLAKE-U_BGA13 56

REV = 1
@

3 2 1

?

SKL_ULT

DDR1_CKN[0]
DDR1_CKN[1]
DDR1_CKP[0]
DDR1_CKP[1]

DDR1_CKE[0]
DDR1_CKE[1]
DDR1_CKE[2]
DDR1_CKE[3]

DDR1_CS#[0]

DDR1_CS#[1]

DDR1_O DT[0]

DDR1_MA[ 5]/DDR 1_CAA[0]/DDR1_MA[5]
DDR1_MA[ 9]/DDR 1_CAA[1]/DDR1_MA[9]
DDR1_MA[ 6]/DDR 1_CAA[2]/DDR1_MA[6]
DDR1_MA[ 8]/DDR 1_CAA[3]/DDR1_MA[8]
DDR1_MA[ 7]/DDR 1_CAA[4]/DDR1_MA[7]

DDR1_BA[2]/DDR1_CA A[5]/DDR1_BG[0]
DDR1_MA[ 12]/DDR1_CAA[6]/DDR1_ MA[12]
DDR1_MA[ 11]/DDR1_CAA[7]/DDR1_ MA[11]

DDR1_MA[ 15]/DDR1_CAA[8]/DDR1_ ACT#
DDR1_MA[ 14]/DDR1_CAA[9]/DDR1_ BG[1]

DDR1_MA[ 13]/DDR1_CAB[0]/DDR1_ MA[13]

DDR1_CAS#/DDR1_CAB [1]/DDR1_MA [15]

DDR1_W E#/DDR1_CAB[2]/DDR1_MA[ 14]

DDR1_RAS#/DDR1_CAB [3]/DDR1_MA [16]

DDR1_BA[0]/DDR1_CA B[4]/DDR1_BA[0]

DDR1_MA[ 2]/DDR 1_CAB[5]/DDR1_MA[2]

DDR1_BA[1]/DDR1_CA B[6]/DDR1_BA[1]

DDR1_MA[ 10]/DDR1_CAB[7]/DDR1_ MA[10]

DDR1_MA[ 1]/DDR 1_CAB[8]/DDR1_MA[1]
DDR1_MA[ 0]/DDR 1_CAB[9]/DDR1_MA[0]

DDR1_DQSN[0]/DDR0_DQSN[2]

DDR1_DQSP[0]/ DDR0_D QSP[2 ]

DDR1_DQSN[1]/DDR0_DQSN[3]

DDR1_DQSP[1]/ DDR0_D QSP[3 ]

DDR1_DQSN[2]/DDR0_DQSN[6]

DDR1_DQSP[2]/ DDR0_D QSP[6 ]

DDR1_DQSN[3]/DDR0_DQSN[7]

DDR1_DQSP[3]/ DDR0_D QSP[7 ]

DDR1_DQSN[4]/DDR1_DQSN[2]

DDR1_DQSP[4]/ DDR1_D QSP[2 ]

DDR1_DQSN[5]/DDR1_DQSN[3]

DDR1_DQSP[5]/ DDR1_D QSP[3 ]

DDR CH - B

1 OF20

DDR1_O DT[1]

DDR1_MA[ 3]
DDR1_MA[ 4]

DDR1_DQ SN[6]
DDR1_DQSP[6]
DDR1_DQ SN[7]
DDR1_DQSP[7]

DDR1_ALE RT#

DRAM_RESET#
DDR_RCO MP[0]
DDR_RCO MP[1]
DDR_RCO MP[2]

DDR1_PAR

AN45
AN46
AP45
AP46

AN56

AP55

AN55

AP53

BB42
AY42
BA42
AW 42

AY48
AP50
BA48
BB48
AP48
AP52
AN50
AN48
AN53
AN52

BA43

AY43

AY44
AW 44

BB44

AY47

BA44

AW 46

AY46

BA46

BB46
BA47

AH66

DDRB_DQS0

AH65

DDRB_DQS#1

AG69

DDRB_DQS1

AG70

DDRB_DQS#2

AR66

DDRB_DQS2

AR65

DDRB_DQS#3

AR61

DDRB_DQS3

AR60

DDRB_DQS#4

AT38

DDRB_DQS4

AR38

DDRB_DQS#5

AT32

DDRB_DQS5

AR32

DDRB_DQS#6

AR25

DDRB_DQS6

AR27

DDRB_DQS#7

AR22

DDRB_DQS7

AR21

AN43
AP43

CPU_DRAMRST#_R

AT13

SM_RCOMP_ 0

AR18

SM_RCOMP_ 1

AT18

SM_RCOMP_ 2

AU18

?

DDRB_DQS#0

DDRB_CLK0#
DDRB_CLK1#
DDRB_CLK0
DDRB_CLK1

DDRB_CKE0
DDRB_CKE1

DDRB_CS0#
DDRB_CS1#
DDRB_ODT 0
DDRB_ODT1

DDRB_MA5 18
DDRB_MA9 18
DDRB_MA6 18
DDRB_MA8 18
DDRB_MA7 18
DDRB_BG 0 18
DDRB_MA12 18
DDRB_MA11 18
DDRB_AC T# 18
DDRB_BG 1 18

DDRB_MA13 18
DDRB_MA15_CAS#
DDRB_MA14_WE#
DDRB_MA16_RAS#
DDRB_BS0# 18
DDRB_MA2 18
DDRB_BS1# 18
DDRB_MA10 18
DDRB_MA1 18
DDRB_MA0 18
DDRB_MA3 18
DDRB_MA4 18

DDRB_ALERT# 18
DDRB_PAR 18

RC24 1
RC25 1
RC26 1 2 100_0402_1%

18

18
18
18

18
18

18
18
18
18

18

DDRB_DQS#[0..7]

DDRB_DQS[0..7]

2 121_0402_1%
2 80.6_0402_1%

18
18

DDRB_DQS#[0..7] 18
DDRB_DQS[0..7] 18

+1.2V

1

RC22
470_0402_5%

2

17,18 CPU_DRAMRST#

A A

1

CC1

1000P_0201_50V7-

K EMC@

2

RC23 1 @ 2 0_0402_5 %

Security Classification LC Future Center Secret Data

Issued Date

THIIIS SHEET OF ENGIIINEERING DRAWIIING IIIS THE PROPRIE TARY PR OPERTY OF LC FUTURE C ENTER. A ND CONTAIIINS CONFIDENTIIIAL
AND TRAD E SEC RET IIINFORMATIIION... THIIIS SHEE T MAY NOT BE TRAN SFERED FROM THE CUSTOD Y OF THE COMP ETENT DIVIIISIIION OF R& D
DEPAR TMENT EXCE PT AS AUTHORIZE D BY L C FUTURE CENTER NEIIITHER THIIIS SHEET N OR THE IIINFORMATIIION IIIT CONTAIIINS
MAY BE USED BY OR DISCLO SED TO A NY THIRD PARTY WIIITHOUT PRIO R WR ITTEN CONSEN T OF LC FUTU RE CE NTER.

5

4

3 2

CPU_DRAMRST#_R

2015/08/20 DecipheredDate

2016/08/20

Title

MCP (DDR4)

Siiize Document Number

Custom

DG42A

R ev

Sheet 6 of 60Date: Su nd ay , J an ua ry 22, 2017

1

1.0

5 4 3 2 1

?

UC1E

D D

44 SPI_C LK

44 SPI_SO

44 SPI_SI

44 SPI_C S0#

C C

Check with BIOS, SPI is Dual mode or quad mode

B B

SPI_CLK SPI_CL K_R

RC1539 1 2 15_0402 _5%

SPI_SO

RC53 1 2 15_ 0402_5%

SPI_SI

RC52 1 2 1 5_0402_5%

SPI_CS 0#

RC51 1 @ 20_0402_5 %

W_ PCH

+3VS +3VAL

+3V_SPI

1. If support DS3, connect to +3VS and don't support EC mirror code;

2. If don't support DS3, connect to +3VALW_PCH and support EC mirror code.

*

SPI_W P#_R

SPI_HOL D#_R

SPI_CS 0#
SPI_SO

SPI_W P#

RC54 1

RC55 1

RC171

RC172

@ 2 15_04 02_5%

@ 2 15_0 402_5%

UC3

1

/CS

2

DO(IO 1)

3

IO2

4

GND DI(IO0)

W 25Q64JVSSIQ_ SO8

1@2
1

@20_0402_ 5%

VCC

CLK

1K_04 02_5%

IO3

0_0402_ 5%

RC60

8
7

6
5

SPI_SO_ R

SPI_SI_R

SPI_CS 0#_R

+3V_SPI

+3V_SPI

12

SPI_HOL D#

SPI_CLK
SPI_SI

1

RC61
1K_04 02_5%

2

8 BOAR D_ID4

44 KBRS T#

32,44 SER IRQ

SPI_W P#

SPI_HOL D#

+3V_SPI

1

2

CC8

0.1u_0 201_10V6K

SPI_CL K_R
SPI_SO_ R
SPI_SI_R
SPI_W P#_R
SPI_HOL D#_R
SPI_CS 0#_R

BOARD_ID4

KBRST#

SERIRQ

AV2

SPI 0_CL K

AW 3

SPI 0_MIS O

AV3

SPI 0_MO SI

AW 2

SPI 0_IO2

AU4

SPI0_IO3

AU3

SPI 0_CS 0#

AU2

SPI 0_CS 1#

AU1

SPI0_C S2#

M2

GPP _D1/ SPI1_ CLK

M3

GPP _D2/ SPI1_ MISO
GPP _D3/ SPI1_ MOSI
GPP _D21/ SPI1 _IO2

GPP _D22/ SPI1_ IO3

M1

GPP _D0/ SPI1_ CS#

G3

CL_ CLK

G2

CL_DATA

G1

CL_RST#

AW 13

GPP _A0/ RCIN#

AY11

GPP _A6/ SERIR Q

RESVK=YL1
@

SPI - FLASH

SPI - TOUCH

J4

V1
V2

CLINK

AKE-U_BGA1356

2.2K_0 404_4P2R_5%

PCH_SM L1_CLK

PCH_SM L1_DAT

SKL_ ULT

SMBUS,SMLINK

GPP _B23 /SML1A LERT# /PCHH OT#

LPC

GPP _A5/ LFRAM E#/ES PI_C S#

GPP_A1 4/SUS_S TAT#/ESP I_RESET#

GPP _A9/ CLKOU T_LPC 0/ESP I_CLK

1 OF20

check CLKRUN# / SUS_STAT# signal if need to connect

PM_CLK RUN#

SERIRQ

KBRST#

KBRST#

RPC25

RC11 1

RC12 1

RC10

CC1255

+3VALW _PCH +3VS

1 42

3

2

2

2

1

2

1

1000P _0201_50V7-K

EMC_NS@

2

G

6 1

QC10A

D

2N7002KDWH_S OT363-6

QC10B 3

8.2K_0 402_5%

10K_0 402_5%

10K_0 402_5%

S

GPP _C0/ SMBCL K

GPP _C1/ SMBDA TA

GPP _C2/ SMBAL ERT#

GPP _C3/ SML0CL K

GPP _C4/ SML0DA TA

GPP _C5/ SML0AL ERT#

GPP _C6/ SML1CL K

GPP _C7/ SML1DA TA

GPP _A1/ LAD0/ ESPI_ IO0
GPP _A2/ LAD1/ ESPI_ IO1
GPP _A3/ LAD2/ ESPI_ IO2
GPP _A4/ LAD3/ ESPI_ IO3

GPP _A10 /CLKO UT_LP C1

GPP _A8/ CLKRUN #

@

5

G

4

S

D

2N7002 KDWH _SOT363-6

@

?

+3VS

R7
R8
R10

R9
W2

W1

W3
V3

AM7

AY1 3

BA1 3
BB1 3
AY1 2
BA1 2

BA1 1

CLK_P CI_EC_R

AW 9

CLK_P CI_TPM_R

AY9

AW 11

SUS_S TAT#

PM_CLK RUN#

PCH_SM B_CLK
PCH_SMB_DA TA
SMB_A LERT#

SML0_ CLK
SML0_DA TA
SML0_ ALERT#

PCH_SM L1_CLK
PCH_SM L1_DAT
SML1_ ALERT#

EC_SM B_CK2 20,39,44

EC_SM B_DA2 20,39,44

DIMM, NGFF

GPU, EC, Ther mal Se nsor

LPC_A D0 32,44
LPC_A D1 32,44
LPC_A D232,44
LPC_A D3 32,44
LPC_FR AME# 32,44

RC173 2 1 22_0402_5%

1

RC1541 2 TPM@

22_0402_5%

1

To enable Direct Connect Interface (DCI), a 150K pull up resistor will need to be added
to PCHHOT# pin. This pin must be low during the rising edge of RSMRST#. (Refer to
WW52_MOW)

+3VALW _PCH +3VS +3VS

RPC20

2.2K_0 404_4P2R_5%

PCH_SM B_CLK

PCH_SM B_DATA

TC81@

CLK_P CI_EC 44
CLK_P CI_TPM 32
PM_CLK RUN# 32

SMB_A LERT#

SML0_ CLK
SML0_DA TA

SML0_ ALERT#

SML1_ ALERT#

2 31

4

6

QC2A

2N7002 KDWH _SOT363-6

2

1 RC1562

2.2K_0 402_5%

RPC23

4 1
3 2

2.2K_0 404_4P2R_5%

RC1564 2 @ 12.2K_0 402_5%

This signal has a weak internal pull-down. 0
= LPC Is selected for EC. (Default)
1 = eSPI Is selected for EC.
Notes:

1.The internal pull-down is disabled after RSMRST#
de-asserts.

2. This signal is in the primary wel
Rising edge ofRSMRST#

1

RC1569

@ 2 150K_ 0402_5%

RC1655 1

2 150 K_0402_5%

2

G

1

S

D

QC2B 3

2N7002 KDWH _SOT363-6

+3VALW _PCH

+3VALW _PCH

5

G

D

+3VALW _PCH

+3VALW_P CH

4

S

RPC24

2.2K_0 404_4P2R_5%

1 42

3

+3VS

SMB_C LK_S3 18,40

SMB_D ATA_S3 18,40

A A

Security Clllassiiifiiication

Issued Date

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPE RTY OF LC F UTURE CENTER... AND CONTAIIINS CONFIIIDENTIAL

AND TRADE SE CRET IIINFORMATION... THIIIS SHEET MAY NOT BE TR ANSFE RED FR OM T HE CU STODY OF T HE CO MPETE NT DIIIVIIISIIION OF R &D
DEPARTMENT EX CEPT AS AUTHORIIIZED BY LC FUT URE CE NTER NEI THER THIIIS SHEET NO R THE IIINFORMATION IT CONTAIIINS

5 4 3 2

MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WI THOUT PRIIIOR WRITTEN CONS ENT OF LC FUTURE CE NTER.

2015/08/20

LC Future Center Secret Data

Deciphered Date

2016/08/20

Title

MCP (MISC,JTAG,SPI,LPC,SMB)

Size Documenttt Number C R ev

Sunday, ,, Ja nua ry 22,,, 2017

Dattte: Sheet 7 of 60

PC,SMB)PC,SMB)

DG42A

1

1.0

5 4 3 2 1

0 = Disable “ Top Swap”

0 = Disable “ No Reboot”

@UMA SKU

RC1558 1

UMA@ 2 10K_0402_5%

D D

C C

B B

A A

+3VS

RPC28

4

1

3

2

2.2K_0 404_4P2R_5%

RC1658 2 1 10K_ 0402_5%

PCH_I2C _SDA0
PCH_I2C _SCL0

PCH_TP_INT#

10/25 SIT For I2C T /P Function wei

+3VS

PCH_CM OS_ON#

1

RC1595 2@

10K_0 402_5%

RC1596 2

2

RC1597

double check if need the pull up resisor

+3VALW _PCH +3VS

30 H DA_SDOUT_ AUDIO
44 M E_FLASH

RC1600 1 @ 2 1K_ 0402_5%
RC47 1 @ 2 1K _0402_5%

*

HDA_SDO This signal has a weak internal pull-down.
0 = Enable security measures defined in the Flash Descriptor.
1 = Disable Flash Descriptor Security(override). This strap
should only be asserted high during external pull-up in
manufacturing/debug environments ONLY.

ForEM I

1

CC7
10P_0201_50 V8F

EMC_NS @

2

+3VS

RC14 1@ 22.2K_0 402_5%

Pin Name Strap Descr iption Configuration

SPKR /

Top Swap

GPP_B14

Override

GSPI0_MOSI

No Reboo t

/GPP_B18

Boot BIOS

GSPI1_MOSI

Strap Bit

/GPP_B22

BBS

1

10K_0 402_5%

PCH_BT_ OFF#

1

10K_0 402_5%

1

RC45
RC46 1 @ 2 0_0402 _5%

PCH_W LAN_O FF#

HDA_SD IN0

33 PCH _CMOS_ON#

40 UART_R X_DEBUG
40 UART_TX_ DEBUG

45 TP_I2 C_SDA0
45 TP_I2 C_SCL0

40 PCH_ WLA N_OFF#
40 PCH _BT_OFF#

HDA_SD OUT

30 HDA_S YNC_AUDIO
30 HD A_BITCLK_ AUDIO

30 HDA_S DIN0

30 HDA _RST_AUDIO#

HDA_SDOU T

2

33_0402 _5%

PCH_BE EP

Interna l PD

mode. (Default)

1

= Enable “ Top

mode.

Interna l PD

mode. (Default)

1 = Enable “ No Reboot”

mode

Interna l PD
0 = SPI (Default )
1 = LPC

+3VS

30 PCH_ BEEP

Sw*ap”

*

*

RC1561 1 @ 2 2.2K_0 402_5%

RC1563 1 @ 2 2.2K_0 402_5%

RC1656 1 @ 2 0_ 0402_5%

1 2

RC1657 @ 0_0 402_5%

RC43 1
RC42

RC44 1 2 33 _0402_5%

Default

When

Value

Sampled

0

Rising edge
of PCH_PWROK

Rising edge

0

of PCH_PWROK

Rising edge

0

of PCH_PWROK

GPP_B1 8

PCH_CM OS_ON#

GPP_B2 2

DGPU_P WROK

PCH_I2C _SDA0
PCH_I2C _SCL0

PCH_W LAN_OFF#
PCH_BT_ OFF#U9GPP _C18/ I2C1 _SDA

2 33_0402_5 %
2

33_040 2_5%

1

HDA_SY NC

HDA_BC LK

HDA_SD OUT
HDA_SD IN0

HDA_RS T#

BOARD_ID1 0
BOARD_ ID9

PCH_BE EP

UC1F

AN8

GPP _B15 /GSPI 0_CS#

AP7

GPP _B16 /GSPI 0_CLK

AP8

GPP _B17 /GSPI 0_MIS O

AR7

GPP _B18 /GSPI 0_MOS I

AM5

GPP _B19 /GSP I1_CS #

AN7

GPP _B20 /GSPI 1_CLK

AP5

GPP _B21 /GSPI 1_MIS O

AN5

GPP _B22 /GSPI 1_MOS I

AB1

GPP _C8/ UART0_ RXD

AB2

GPP _C9/ UART0_ TXD

W4

GPP _C10 /UART0 _RTS #

AB3

GPP _C11/ UART0 _CTS#

AD1

GPP _C20/ UART2 _RXD

AD2

GPP _C21/ UART2 _TXD

AD3

GPP _C22/ UART2 _RTS#

AD4

GPP _C23/ UART2 _CTS#

U7

GPP _C16/ I2C0_ SDA

U6

GPP _C17/ I2C0 _SCL

U8

GPP _C19/ I2C1 _SCL

AH9

GPP _F4/ I2C2_ SDA

AH10

GPP _F5/ I2C2_ SCL

AH1 1

GPP _F6/ I2C3_S DA

AH1 2

GPP _F7/ I2C3_S CL

AF1 1

GPP _F8/ I2C4_ SDA

AF1 2

GPP _F9/ I2C4_ SCL

SKYLAK E-U_BGA135 6

REV = 1
@

LPSS ISH

UC1G

BA2 2

HDA _SYNC /I2S0 _SFRM

AY2 2

HDA _BLK/ I2S0 _SCLK

BB2 2

HDA _SDO/ I2S0 _TXD

BA2 1

HDA _SDI0 /I2S 0_RXD

AY2 1

HDA _SDI1 /I2S1 _RXD

AW 22

HDA _RST# /I2S 1_SCLK

J5

GPP _D23/ I2S_ MCLK

AY2 0

I2S1 _SF RM

AW 20

I2S1 _TXD

AK7

GPP _F1/ I2S2_ SFRM

AK6

GPP _F0/ I2S2_ SCLK

AK9

GPP _F2/ I2S2_ TXD

AK1 0

GPP _F3/ I2S2_ RXD

H5

GPP _D19/ DMIC _CLK0

D7

GPP _D20/ DMIC _DATA0

D8

GPP _D17 /DMIC _CLK1

C8

GPP _D18/ DMIC _DATA1

AW5

GPP _B14 /SPKR

SKYLAK E-U_BGA135 6

REV = 1
@

SKL_ ULT ?

GPP _D13/ ISH_ UART0_ RXD/S ML0BD ATA/I 2C4B_ SDA

GPP _D14/ ISH_ UART0_ TXD/ SML0BC LK/I2 C4B_S CL

1 OF 20

AUDIO

SKL_ ULT ?

1 OF 20

GPP _D9
GPP _D10
GPP _D11
GPP _D12

GPP _D5/ ISH_I 2C0_SD A
GPP _D6/ ISH_I 2C0_SC L

GPP _D7/ ISH_I 2C1_SD A
GPP _D8/ ISH_I 2C1_SC L

GPP _F10 /I2C5 _SDA/ ISH_I 2C2_SD A

GPP _F11 /I2C5 _SCL/ ISH_I2 C2_SC L

GPP _D15/ ISH_ UART0_ RTS#

GPP _D16/ ISH_ UART0_ CTS#/ SML0B ALERT #

GPP _C12/ UART1 _RXD/ ISH_U ART1_ RXD

GPP _C13/ UART1 _TXD /ISH_ UART1_ TXD
GPP _C14/ UART1 _RTS# /ISH _UART1 _RTS#
GPP _C15/ UART1 _CTS# /ISH _UART1 _CTS#

GPP _A17 /SD_PW R_EN# /ISH _GP7

GPP_ A18/IS H_GP0
GPP_ A19/IS H_GP1
GPP _A20/IS H_GP 2
GPP _A21 /ISH_ GP3
GPP _A22 /ISH_ GP4
GPP _A23 /ISH_ GP5

GPP _A12 /BM_B USY#/ ISH_GP 6

SDIO/SDXC

GPP _G0/ SD_CM D
GPP _G1/ SD_DA TA0
GPP _G2/ SD_DA TA1
GPP _G3/ SD_DA TA2
GPP _G4/ SD_DA TA3

GPP _G5/ SD_CD #
GPP _G6/ SD_CLK

GPP _G7/ SD_W P

GPP _A16 /SD_1P 8_SEL

SD_ RCOM P

?

GPP _F23

BB9

W1 0

AB7

AB1 1
AB1 3

W7

AF1 3

?

AB1 2
W1 2
W1 1

W8

BA9

P2

P3

P4

P1

M4

N3

N1

N2

AD11

AD1 2

U1

U2

U3

U4

AC1
AC2
AC3

AB4

AY8

BA8

BB7
BA7
AY7
AW 7
AP1 3

SD_ RCOM P

DGPU_P WROK

BOARD_ID0
BOARD_ID1

BOARD_ID3
BOARD_ID6

BOARD_ID5
BOARD_ID7

BOARD_ID8

2

RC49
200_040 2_1%

1

9 BOA RD_ID2
7 BOA RD_ID4

PCH_TP_INT# 45

@

15@

1 RC1615 2

1 RC1613 2

10K_0 402_5%

BOARD_ID0
BOARD_ID1
BOARD_ID2
BOARD_ID3
BOARD_ID4
BOARD_ID5

Board ID Description

Board_I D[0:1 ]

10K_0 402_5%

14@

1 RC1614 2

1 RC1616 2

10K_0 402_5%

10K_0 402_5%

00

01

10

11

Board_ID2

Board_ID3

Board_ID4

Board_ID5

DIMM_ON LY@ DIMM_ON LY@

2 RC1631 1

2 RC1632 1

10K_0 402_5%

BOARD_ID6
BOARD_ID7
BOARD_ID8
BOARD_ ID9
BOARD_ID10

@

2 RC1634 1

Board I D Description Stuff R

Board_ID

[6,7]

10K_0 402_5%

@

2 RC1635 1

10K_0 402_5%

10K_0 402_5%

Samsung 8Gb

00

2400 M T/s

Hynix 8Gb

01

2400 MT/s

Micron 8Gb

10

2400 M T/s

11 SO-DIMM Only RC1631 RC1632

Board_ID8

Board_ID9

Board_ID10

0 320G RC1636

1 520Z RC1633

0 Reserved RC1640

1

0

1

@

1 RC1611 2

@

1 RC1612 2

14"

15"

17"

Reserved

0

Reserved

1

Reserved

0

UMA

1

DIS

0

NV GPU

1

AMD GPU

0

Reserved

1

Reserved

Reserved

Reserved

Reserved

DIS@

10K_0 402_5%

UMA@

10K_0 402_5%

520Z@

2 RC1633 1

10K_0 402_5%

320G@

2 RC1636 1

10K_0 402_5%

RC1634 RC1635

RC1634 RC1632

RC1631 RC1635

PX@

1 RC1609 2

10K_0 402_5%

OPT@

1 RC1610 2

10K_0 402_5%

Stuff R

RC1616 RC1614

RC1616 RC1613

RC1615 RC1614

RC1615 RC1613

RC1612

RC1611

RC1610

RC1609

RC1607

RC1608

RC123

RC1606

@

@

RC1639

RC1652

RC1651

2

@

RC1608

1

10K_0 402_5%

@

1 RC1607 2

10K_0 402_5%

+3VS

@

2 RC1639 1

10K_0 402_5%

@

2 RC1640 1

10K_0 402_5%

+3VS

1 RC1606 2

10K_0 402_5%

10K_0 402_5%

1 RC12 3 2

2 RC1651 1

10K_0 402_5%

2 RC1652 1

10K_0 402_5%

Security Clllassiiifiiication

Issued Date

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPE RTY OF LC F UTURE CENTER... AND CONTAIIINS CONFIIIDENTIAL

AND TRADE SE CRET IIINFORMATION... THIIIS SHEET MAY NOT BE TR ANSFE RED FR OM T HE CU STODY OF T HE CO MPETE NT DIIIVIIISIIION OF R &D
DEPARTMENT EX CEPT AS AUTHORIIIZED BY LC FUT URE CE NTER NEI THER THIIIS SHEET NO R THE IIINFORMATION IT CONTAIIINS

5 4 3 2

MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WI THOUT PRIIIOR WRITTEN CONS ENT OF LC FUTURE CE NTER.

2015/08/20

LC Future Center Secret Data

Deciphered Date

2016/08/20

Title

MCP (LPSS,ISH,AUDIO,SDIO)

Size Documenttt Number C R ev

Sunday, ,, Ja nua ry 22,,, 2017

Dattte: Sheet 8 of 60

,SDIO),SDIO)

DG42A

1

1.0

5 4 3 2 1

D D

37 PC IE_PRX_DT X_N5
37 PCIE_PRX_DT X_P5

C C

LAN

WLAN

SATA HDD

SATA ODD

Optane Memory

B B

A A

37 PCIE_PTX_C_DRX_N5
37 PC IE_PTX_C_DRX_P5

40 PC IE_PRX_DT X_N6
40 PCIE_PRX_DT X_P6

40 PCIE_PTX_C_DRX_N6
40 PC IE_PTX_C_DRX_P6

42 SATA_PRX_DTX_N 0

42 SATA_PRX_DTX_P0

42 SATA_PTX_DRX_N 0

42 SATA_PTX _DRX_P0

42 SATA_PRX_DTX_N 1
42 SATA_PRX_DTX_P 1

42 SATA_PTX_DRX_N1
42 SATA_PTX _DRX_P1

40 PC IE_PRX_DT X_N9
40 PCIE_PRX_DT X_P9

40 PCIE_PTX_C_DRX_N9
40 PC IE_PTX_C_DRX_P9

40 PC IE_PRX_DT X_N10
40 PC IE_PRX_DT X_P10

40 PCIE_PTX_C_DRX_N10
40 PCIE_PTX_C_DRX_P10

PCIE_RCOMPN and PCIE_RCOMPP
Trace Width: 12-15mil
Differential between RCOMPP/RCOMPN

40 PC IE_PRX_DT X_N11
40 PC IE_PRX_DT X_P11

40 PCIE_PTX_C_DRX_N11
40 PCIE_PTX_C_DRX_P11
40 PC IE_PRX_DT X_N12
40 PC IE_PRX_DT X_P12

40 PCIE_PTX_C_DRX_N12
40 PCIE_PTX_C_DRX_P12

+3VS

CC1262 1
CC1261 1

CC1264 1
CC1263 1

CC22 1
CC23 1

CC1266 1 2 0.22U_0201_6.3V6-K
CC1265 1 2 0.22U_0201_6.3V6-K

RC119 1

CC1267 1 2 0.22U_0201_6.3V6-K
CC1268 1 2 0.22U_0201_6.3V6-K

CC1269 1 2 0.22U_0201_6.3V6-K
CC1270 1 2 0.22U_0201_6.3V6-K

RPC2

2
3
4

10K_0804_8P4R_5%

SATA2G P RC189

2 0.1u_0201_10V 6K
2 0.1u_0201_10V 6K

2 0.1u_0201_10V 6K
2 0.1u_0201_10V 6K

OPTANE@

2 0.22U_02 01_6.3V6- K
2 0.22U_0 201_6.3V6 -K

OPTANE@
OPTANE@

OPTANE@

2 100_0402 _1%

PAD @ TC20
PAD @ T C19

OPTANE@

OPTANE@
OPTANE@

OPTANE@

ODD_DETECT#

81
7 SATA0G P
6 SATA2G P
5 PIRQA#

1 @ 2 0_0402_5%

PCIE_PRX_DTX_N5
PCIE_PRX_DTX_P5

PCIE_PTX_DRX_N5

PCIE_PTX_DRX_P5
PCIE_PRX_DTX_N6

PCIE_PRX_DTX_P6

PCIE_PTX_DRX_N6

PCIE_PTX_DRX_P6
SATA_PRX_DTX_N0

SATA_PRX_DTX_P0
SATA_PTX_DRX_N0
SATA_PTX_DRX_P0

SATA_PRX_DTX_N1
SATA_PRX_DTX_P1
SATA_PTX_DRX_N1
SATA_PTX_DRX_P1

PCIE_PRX_DTX_P9

PCIE_PTX_DR X_N9

PCIE_PTX_DR X_P9
PCIE_PRX_DTX_N10

PCIE_PRX_DTX_P10
PCIE_PTX_DRX_N10
PCIE_PTX_DRX_P10

PCIE_RCOMPN

PCIE_RCOMPP

XDP_PRDY#

1

XDP_PREQ #

1

PIRQA#

PCIE_PRX_DTX_N11

PCIE_PRX_DTX_P11
PCIE_PTX_DRX_N11
PCIE_PTX_DRX_P11

PCIE_PRX_ DTX_N12

PCIE_PRX_ DTX_P12
PCIE_PTX_DRX_N12
PCIE_PTX_DR X_P12

Add SSD_DET# for Optane memory wei

H13

G13

B17
A17

G11

F11
D16
C16

H16

G16

D17
C17

G15

F15
B19
A19

F16
E16
C19
D19

G18

F18
D20
C20

F20
E20
B21
A21

G21

F21
D21
C21

E22
E23
B23
A23

F25
E25
D23
C23

D56
D61

BB11

E28
E27
D24
C24
E30
F30
A25
B25

SSD_DET # 40

UC1H

PCIE/USB3/SATA

PCIE1_R XN/US B3_5_R XN
PCIE1_RXP/USB3_5_RXP
PCIE1_T XN/USB3_5_TXN
PCIE1_T XP/USB3_5_ TXP

PCIE2_R XN/USB 3_6_R XN

PCIE2_R XP/USB3_6_RXP
PCIE2_T XN/USB3_6_TXN
PCIE2_T XP/US B3_6_ TXP

PCIE3_RXN

PCIE3_R XP
PCIE3_T XN
PCIE3_T XP

PCIE4_R XN

PCIE4_R XP

PCIE4_T XN
PCIE4_T XP

PCIE5_RXN
PCIE5_RXP
PCIE5_T XN

PCIE5_T XP

PCIE6_R XN

PCIE6_RXP
PCIE6_T XN

PCIE6_T XP
PCIE7_R XN/SATA0_RXN

PCIE7_RXP/SAT A0_R XP
PCIE7_T XN/SAT A0_T XN

PCIE7_T XP/SATA0_T XP

PCIE8_R XN/SATA1A_R XN
PCIE8_RXP/SATA1A_RXP

PCIE8_T XN/SAT A1A_T XN

PCIE8_T XP/SATA1A_TXP
PCIE9_RXN

PCIE9_RXP

PCIE9_T XN
PCIE9_T XP

PCIE10_RXN

PCIE10_RXP

PCIE10_TXN
PCIE10_TXP

F5

PCIE _RCO MPN

E5

PCIE _RCO MPP

PROC_PRDY#

PROC_PREQ#

GPP_A7/PIRQA#
PCIE11_RXN/SATA1B_RXN

PCIE11_RXP/S ATA1B _RXP
PCIE11_TXN/S ATA1B _TXN
PCIE11_TXP/S ATA1B _TXP
PCIE12_RXN/SATA2_RXN
PCIE12_RXP/S ATA2_RXP
PCIE12_TXN/S ATA2_TXN
PCIE12_TXP/S ATA2_ TXP

SKYLAKE-U_BGA13 56

REV = 1
@

USB_OC0# 8 1
USB_OC1# 7 2
USB_OC3# 6 3
USB_OC2# 5 4

Security Classification

IssuedDate

THIIIS SHEET OF ENGIIINEERING DRAWIIING IIIS THE PROP RIETARY PROPE RTY OF LC FU TURE C ENTER. AND CONTAIIINS CONFIDENTIIIAL
AND TRAD E SEC RET IIINFORMATIIION... THIIIS SHEE T MAY NOT BE TRAN SFERED FROM THE CUSTOD Y OF THE COMP ETENT DIVIIISIIION OF R& D
DEPAR TMENT EXCE PT AS AUTHORIZE D BY L C FUTURE CENTER NEIIITHER THIIIS SHEET N OR THE IIINFORMATIIION IIIT CONTAIIINS

5 4 3 2

MAY BE USED BY OR DISCLO SED TO A NY THIRD PARTY WIIITHOUT PRIO R W RITTEN CONSEN T OF LC FUTU RE CE NTER.

SKL_ULT

?

USB2

1 OF20

RPC17

10K_0804_8P4R_5%

SSIC /USB3

GPP_E0/SATA XPCIE0 /SATAGP0

GPP_E1/SATA XPCIE1 /SATAGP1
GPP_E2/SATA XPCIE2 /SATAGP2

USB3 _1_R XN
USB3 _1_R XP
USB3_1_TXN

USB3_1_TXP

USB3_2_RXN/S SIC_1 _RXN
USB3_2_RXP/S SIC_1_RXP

USB3_2_TXN/S SIC_1_TXN
USB3_2_TXP/S SIC_1 _TXP

USB3_3_RXN/S SIC_2 _RXN
USB3_3_RXP/SSIC_2 _RXP

USB3_3_TXN/S SIC_2_TXN
USB3_3_TXP/S SIC_2 _TXP

USB3 _4_R XN
USB3 _4_R XP
USB3_4_TXN

USB3_4_TXP

USB2 N_1
USB2P_1

USB2 N_2
USB2P_2

USB2 N_3
USB2P_3

USB2 N_4
USB2P_4

USB2 N_5
USB2P_5

USB2 N_6
USB2P_6

USB2 N_7
USB2P_7

USB2 N_8
USB2P_8

USB2 N_9
USB2P_9

USB2 N_10
USB2P_10

USB2 _COMP

USB2_ID

USB2_VBUSSEN SE

GPP_E9/USB2 _OC0#

GPP_E10/USB 2_OC1 #

GPP_E11/USB 2_OC2 #

GPP_E12/USB 2_OC3 #

GPP_E4/DEVSLP0
GPP_E5/DEVSLP1
GPP_E6/DEVSLP2

GPP_E8/SATA LED#

?

+3VALW _PCH

LC Future Center Secret Data

2015/08/20

USB30_RX_N1

H8

USB30_RX_P1

G8

USB30_T X_N1

C13

USB30_T X_P1

D13
J6

H6

USB30_T X_N2

B13

USB30_T X_P2

A13

J10
H10

B15

USB30_T X_P3

A15

E10

F10
C15
D15

AB9

AB10
AD6

AD7

AH3

USB20_P3

AJ3

AD9

USB20_P4

AD10

AJ1
AJ2

AF6

AF7

AH1

AH2

AF8

AF9

AG1
AG2

AH7
AH8

AB6

AG3

USB2_VBU SSENSE

AG4

A9
C9
D9
B9

J1
J2
J3

H2

H3

G4

H1

USB30_RX_N2
USB30_RX_P2

USB30_RX_N3
USB30_RX_P3
USB30_TX_N3

USB20_N1
USB20_P1

USB20_N2
USB20_P2

USB20_N3

USB20_N4

USB20_N5
USB20_P5

USB20_N6
USB20_P6

USB20_N7
USB20_P7

USB20_N8
USB20_P8PCIE_PRX_DTX_N9

USB2_COMP
USB2_ID

USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#

GPP_E4
GPP_E5

SATA0G P

ODD_DETECT#
SATA2G P
BOARD_ID2

GPP_E4

USB_OC2#

USB30_RX_N1 41
USB30_RX_P1 41
USB30_T X_N1 41

USB30_T X_P1 41

USB30_RX_N2 43
USB30_RX_P2 43
USB30_T X_N2 43
USB30_T X_P2 43

USB30_RX_N3 41
USB30_RX_P3 41
USB30_T X_N3 41
USB30_T X_P3 41

USB20_N1 41
USB20_P1 41

USB20_N2 43
USB20_P2 43

USB20_N3 41
USB20_P3 41

USB20_N4 45
USB20_P4 45

USB20_N5 30
USB20_P5 30

USB20_N6 33
USB20_P6 33

USB20_N7
USB20_P7

USB20_N8 33
USB20_P8 33

RC1626 1 @ 2 0_0402 _5%

RC1627 1

USB_OC1# 41

1

@ PAD TC202

BOARD_ID2 8

RC1617 2 @ 1 10K_0 402_5%

RC1654 1

LEFT USB3.0

Type-C

LEFT USB3.0

Finger Print
Card reader

Touch panel

40
40

BT

Camera

1 113_0402 _1%RC118 2

2 1K_0402_5%

RC1628 1 @ 2 0_0402_5%

2016/05/03: Implement as Power Button
function for Windows RedStone support

@ 2 0_0402_5%

8/24 Reserve TYPE_C_OCP# to CPU USB_OC2# wei

Deciphered Date

2016/08/20

LEFT USB3.0

Type-C

LEFT USB3.0

USBRBIAS

Width 20M il
Space 15Mil
Length 5 00Mil

EC_SMI# 44

+3VS

TYPE_C_OCP# 43

Title

MCP (PCIE,SATA,USB3,USB2)

Siiize Document Number

Custom

Date: S un da y, J an ua ry 22, 2017 Sheet 9 of 60

3,USB2)3,USB2)

DG42A

1

R ev

1.0

5 4 3 2 1

SKL_ULT

SKL_ULT

CLOCKSIGNALS

?

GPP_F13/EMMC_DATA0
GPP_F 14/EMMC _DATA1
GPP_F 15/EMMC _DATA2
GPP_F 16/EMMC _DATA3
GPP_F 17/EMMC _DATA4
GPP_F18 / EMMC_D ATA5
GPP_F19/EMMC_DATA6
GPP_F20/EMMC_DATA7

GPP_F21/EMMC_ RCLK

1 OF20

?

1 OF20

CSI2_CL KN0
CSI2_CL KP0
CSI2_CL KN1
CSI2_CL KP1
CSI2_CL KN2
CSI2_CL KP2
CSI2_CL KN3
CSI2_CL KP3

CSI2 _COMP

GPP_D4/ FLASHTRIG

EMMC

GPP_F22/EMMC_ CLK

GPP_F12/EMMC_ CMD

EMMC_ RCOMP

?

CLKOUT_ITPXD P_N
CLKOUT_IT PXDP_P

GPD8/SUSCLK

C37
D37
C32
D32
C29
D29
B26
A26

E13

B7

AP2

AP1

AP3
AN3
AN1
AN2

AM4
AM1

AM2
AM3
AP4

AT1

XTAL24 _IN

XTAL24 _OUT

RTC X1

RTC RST#

?

CSI2_COMP

EMMC_RCOMP

F43
E43 1

BA17 SUS CLK
E37

E35

E42
AM18

AM20

AN18
AM16

RC73 1 2 100_0402_1%

RC50 1

CLK_PCIE_XDP#
CLK_PCIE_XD P

XTAL24_IN
XTAL24_OUT

DIFFCLK_BIASREF
RTC_X1

RTC_X2

SRTC_RST #
RTC_R ST#

VCCRTC

2 200_0402_1%

1

TC85 @
TC87 @

SUSCLK 40

RC72 1 2 2.7K_0402_1%

RC33 1
RC34 1

SUSCLK RC95 1 @ 2

DIFFCLK_BIASREF

1U_0402_6.3V6K

2 20K_0402_1%
2 20K_0402_1%

1U_0402_6.3V 6K

CC3

CC6

+VCCCLK5

1

2

1

2

RC1555 1

SRTC_RST #
RTC_R ST#

JCMOS1
SHORT PADS

@

2 1

Cannonlake@

RC1624 1

1K_0402_5%

2 60.4_0402_1%

@

2

0_0402_5%

EC_RTC_RST# 44

UC1I

CSI-2

A36

CSI2_DN0

B36

CSI2_DP 0

C38

CSI2_DN1

D38

CSI2_DP 1

C36

D D

C C

B B

check the Pull up resistor

+3VS

RPC4

128

7

346

5

10K_0804_8P4R_5%

Optane memory

PCIE CLK5 WLAN

PCIE CLK4 LAN

LAN_CLKREQ#
W LAN_CLKREQ#
SSD_PCIE_ CLKREQ#

40 CLK_PCIE_SSD #
40 CLK_PCIE_SSD
40 SSD _PCIE_CLKREQ#

40 CLK_PCIE_W LAN#
40 CLK_PCIE_WLAN
40 WLAN _CLKREQ#

37 CLK_PCIE_LAN#
37 CLK_PCIE_LAN
37 L AN_CLKREQ #

CLK_PCIE_SSD #
CLK_PCIE_SSD
SSD_PCIE_ CLKREQ#

CLK_PCIE_W LAN#
CLK_PCIE_WLAN
WLAN_CLKREQ#

CLK_PCIE_LAN#
CLK_PCIE_LAN
LAN_CLKREQ#

CSI2_DN2

D36

CSI2_DP 2

A38

CSI2_DN3

B38

CSI2_DP 3

C31

CSI2 _DN4

D31

CSI2 _DP4

C33

CSI2 _DN5

D33

CSI2 _DP5

A31

CSI2 _DN6

B31

CSI2_DP 6

A33

CSI2_DN7

B33

CSI2_DP7

A29

CSI2_DN8

B29

CSI2_DP 8

C28

CSI2_DN 9

D28

CSI2_DP 9

A27

CSI2_DN 10

B27

CSI2_DP10

C27

CSI2_DN 11

D27

CSI2_DP 11

SKYLAKE-U_BGA13 56

REV = 1
@

UC1J

D42

CLKOUT _PCIE_N 0

C42

CLKOUT _PCIE_ P0

AR10

GPP_B5/SRCCL KREQ0 #

B42

CLKOUT _PCIE_N 1

A42

CLKOUT _PCIE_ P1

AT7

GPP_B6/SRCCL KREQ1 #

D41

CLKOUT _PCIE_N 2

C41

CLKOUT _PCIE_ P2

AT8

GPP_B7/SRCCL KREQ2 #

D40

CLKOUT _PCIE_N 3

C40

CLKOUT _PCIE_ P3 XCLK_BIASREF

AT10

GPP_B8/SRCCL KREQ3 #

B40

CLKOUT_PCIE_N4 RTC X2

A40

CLKOUT _PCIE_ P4

AU8

GPP_B9 /SRCCLKREQ 4# SRTC RST#

E40

CLKOUT _PCIE_N 5

E38

CLKOUT _PCIE_ P5

AU7

GPP_B10/SRCC LKREQ 5#

SKYLAKE-U_BGA13 56

REV = 1
@

RTC_X1

RTC_X2

2

CC5
7P_0402_50V8J

1

when single end external clock generator used,
this pin should be grounded

XTAL24_IN

RC241 1 2 0_0201_5%

3.3P_0402_50V8-C

CC12

1

2

1 1M_0402_5%RC71 2

YC2

2

GND 1 OS C2

1

OSC1 GN D2

24MHZ_6PF_7V24000032

3
4

1

2

RC240 1 2 0_0201_5%

CC11

2.7P_0402_5 0V9-B

XTAL24_OUT

1 2

32.768KHZ_9PF_X1A0001410002

2

CC4

7P_0402_50V8J

1

1 10M_0402_5%RC32 2

YC1

need to use 38.4MHz (30ohm) for Cannonlake-u

A A

Security Classification

IssuedDate

THIIIS SHEET OF ENGIIINEERING DRAWIIING IIIS THE PROP RIETARY PROPE RTY OF LC FU TURE C ENTER. AND CONTAIIINS CONFIDENTIIIAL
AND TRAD E SEC RET IIINFORMATIIION... THIIIS SHEE T MAY NOT BE TRAN SFERED FROM THE CUSTOD Y OF THE COMP ETENT DIVIIISIIION OF R& D
DEPAR TMENT EXCE PT AS AUTHORIZE D BY L C FUTURE CENTER NEIIITHER THIIIS SHEET N OR THE IIINFORMATIIION IIIT CONTAIIINS

5 4 3 2

MAY BE USED BY OR DISCLO SED TO A NY THIRD PARTY WIIITHOUT PRIO R W RITTEN CONSEN T OF LC FUTU RE CE NTER.

2015/08/20

LC Future Center Secret Data

Deciphered Date

2016/08/20

Title

MCP (CSI2,EMMC,CLOCK)

Siiize Document Number

Custom

Date: S un da y, J an ua ry 22, 2017 Sheet 10 of 60

CK)CK)

DG42A

1

R ev

1.0

5 4 3 2 1

?

UC1K

D D

+3VALW

C C

+3VALW _PCH

+3VS

B B

PLT_RST#20,32,37,40,44

44 EC_RSMRST#

44 SYS_PWROK
44 PCH_PWR OK

44 SUSWARN#
44 SUSACK#

37,40,44 PCIE_WAK E#

RC74 1
RC75 1 2 8.2K_0402_5% BATLO W#

RC90 1

RC78 1 @ 2 10K_04 02_5%

RC80 1 2 10K_0402_ 5%

1000P_0201_ 50V7-K 1 2 CC1254

0.01U_0201_10V6K 1 2 CC104

1000P_0201_ 50V7-K 1 2 CC103

47P_0201_25 V8-J 1 2 CC101

0.01U_0201_10V6K 1 2 CC1260

2 10K_0402_5%

1 1K_0402_5% W AKE#RC76 2

2 10K_0402_5%

SUSWARN#_R

EMC_NS@

EMC_NS@

VCCST_PWRGD_ R

AC_PRESENT_R

PCH_LAN_WAKE#

SYS_RESET#

PAD @TC21

PCH_RSMRST#_R

Stuff t o fix Res et&PWRGD tes t fail is sue

PCH_PW ROK

PCH_DPW ROK_R

SYS_PW ROK

EC_RSMRST#

RC84 1 @ 2 0_0402_5 %
RC85 1 @ 2 0_0402_5%

1

RC93 1
RC139 1 @

RC126 1 @

RC86 1 @
RC79 1 @ 2 0_0402_5%

Reserve for DS3

RC91 1 @ 2 0_0402_5% WAKE#

Follow CRB change to 1kohm

2 60.4_0402_1%
2 0_0402_5%

2 0_0402_5% BA 20

2 0_0402_5% AR13

44 EC_VCCST_PW RGD

PLT_RST#_R

SYS_RESET#

PCH_RSMRST#_R
CPU_PROCPW RGD

VCCST_PWRGD
SYS_PW ROK_R

PCH_PW ROK_R
PCH_DPW ROK_R

SUSW ARN#_R
SUSACK#_ R

PCH_LAN_WAKE#

Add to fix Reset &PWRGD test fail issu e

RPC21

128

346

10K_0804_8P4R_5%

100K_0402_1% 2 @ 1 RC94

PCH_RSMRST#_R
PCH_PW ROK

7

SYS_PW ROK

5

PLT_RST#_R

1 RC92100K_0402_5% 2

PCH_DPW ROK_R

AN10

GPP_B13/PLTRST#

B5

SYS_RESET#

AY17

RSMRST#

A68

PROCPW RGD

B65

VCCST_P WRGD

B6

SYS_ PWR OK

PCH_PWROK

BB20

DSW _PW ROK

GPP_A13/ SUSW ARN #/SU SPW RDNACK

AP11

GPP_A15/SUSA CK#

BB15

WA KE#

AM15

GPD2/LAN _WAKE#

AW 17

GPD11/LANPHY PC

AT15

GPD7/RSVD

SKYLAKE-U_BGA13 56

REV = 1
@

RC138 1 @ 2 0_0402_5%

PM_SLP_S 3#

SKL_ULT

SYSTEM POWERMANAGEMENT

1

CC46

0.01U_0201_25V6-K

EMC_NS@

2

RC1599 1 @ 2 0_0402 _5%

GPD4/SL P_S3#
GPD5/SL P_S4 #

SLP_SUS#

SLP_LAN #

GPD6/SL P_A#

GPP_A11/PME#

INTRUD ER#

AT11

PM_SLP_S3#_R

AP15

PM_SLP_S4 #_R

BA16
AY16

PM_SLP_SU S#_R

AN15
AW 15
BB17
AN16

PBTN_OUT#_R

BA15

AC_PRESENT_R

AY15

AU13

BATLOW#

AU11 PME# @1

AP16 INTVRMEN

AM10

AM11

?

2

RC137
1K_0402_5%

3 1

D

5

G

S

4

44 AC_PRESENT

VCCST_PWRGD_ R

QC6B
2N7002KDWH_SO T363-6

@

PCH_DPW ROK_R

GPP_B12/SLP_S0#

GPD10/SLP_S 5#

GPD9/SLP _WLAN#

GPD3/PW RBTN #

GPD1/ACPRESE NT

GPD0/BAT LOW #

GPP_B11/EXT _PWR_GATE#

1 OF20

2

G

DC4 1 2 @

RB751V-40_SOD323- 2

GPP_B2/VRAL ERT#

+3VALW +VCCST _CPU +VCCSTG

2

RC136
10K_0402_5%

@

6 1

D

QC6A
2N7002KDWH_SO T363-6

@

S

1

RC96 1 @ 2 0_0402_5% RC97 1 @ 2
0_0402_5%

RC89 1 @ 2 0_0402_5%

RC87 1 @ 2 0_0402_5%

TC89

RC88 1 @ 2 0_0402_5%

44 ACIN#

2

RC1554
1K_0402_5%

@

1

RC182 1 @

RC81 1 @ 2 0_0402_5%

Reserve for DS3

1 330K_0402 _5%RC41 2

2

CC140
1000P_0201_50V7-K

EMC_NS@

1

Reserve for DS3

2

G

2 0_0402_5%

PM_SLP_S3 # 13,44
PM_SLP_S4 # 44

PM_SLP_SUS# 44

PBTN_O UT# 44

VCCRTC

AC_PRESENT_R

1

D

QC8
2N7002KW_SOT 323-3

@

S

3

EC_RSMRST#

DPWR OK_EC 44

A A

100P_0201_2 5V8J 1 2 CC1294

@

10/25 SIT Add to fix PLT_RST# glitch issue wei

5 4 3 2

PLT_RST#

Security Classification

IssuedDate 2016/08/20

THIIIS SHEET OF ENGIIINEERING DRAWIIING IIIS THE PROP RIETARY PROPE RTY OF LC FU TURE C ENTER. AND CONTAIIINS CONFIDENTIIIAL
AND TRAD E SEC RET IIINFORMATIIION... THIIIS SHEE T MAY NOT BE TRAN SFERED FROM THE CUSTOD Y OF THE COMP ETENT DIVIIISIIION OF R& D
DEPAR TMENT EXCE PT AS AUTHORIZE D BY L C FUTURE CENTER NEIIITHER THIIIS SHEET N OR THE IIINFORMATIIION IIIT CONTAIIINS
MAY BE USED BY OR DISCLO SED TO A NY THIRD PARTY WIIITHOUT PRIO R W RITTEN CONSEN T OF LC FUTU RE CE NTER.

2015/08/20 Deciphered Date

LC Future Center Secret Data

Title

MCP (SYSTEM PWR MANAGEMENT)

Siiize Document Number

Date:

DG42A

Su nd ay , J a nu ary 22, 2017 Sheet 11 of 60

NAGEMENT)NAGEMENT)A

1

R ev

1.0Custom

5 4 3 2 1

+CPU_C ORE +CPU_C ORE

32000mA

D D

1

@ TC90

+VCCOP C_1.0V

+VCCOP C_1.0V

+V1.8 S_EDRAM

+V1.8 S_EDRAM
VCCOPC_S ENSE

VSSOPC_SE NSE

+VCCE OPIO

+VCCE OPIO
VCCEOPIO_SENSE

VSSEOPIO_SENSE

For UMA 2+3e

C C

+CPU_C ORE

13x10uF 0402, SI T update to 0603 packag e

1

1

CC1086

CC1085

2

2

10U_0402_6.3V6M

10U_0402_6.3V6M

@

CD@

A30

VCC_A3 0

A34
A39

A44
AK33
AK35
AK37
AK38
AK40
AL33
AL37
AL40
AM32
AM33
AM35
AM37
AM38

G30

K32
AK32
AB62

P62

V62

H63

G61
AC63

AE63
AE62

AG62
AL63

AJ62

1

CC1080

2

10U_0603_6.3V6M

UC1L

VCC_A3 4
VCC_A3 9
VCC_A4 4
VCC_AK33
VCC_AK35
VCC_AK37
VCC_AK38
VCC_AK40
VCC_AL 33
VCC_AL 37
VCC_AL 40
VCC_AM32
VCC_AM33
VCC_AM35
VCC_AM37
VCC_AM38
VCC_G3 0

RSVD_K 32
RSVD_A K32
VCCOPC_AB 62

VCCOPC _P62
VCCOPC _V62

VCC_OP C_1P8_H63
VCC_OP C_1P8_G61
VCCOPC_SE NSE

VSSOPC_SE NSE
VCCEOPIO_AE62

VCCEOPIO_AG62
VCCEOPIO_SENSE

VSSEOPIO_SENSE

SKYLAK E-U_BGA135 6

REV = 1
@

SKL_ULT

CPU POWER 1OF 4

1

CC1236

2

10U_0603_6.3V6M

?

G32

VCC_G3 2

G33

VCC_G33

G35

VCC_G35

G37

VCC_G37

G38

VCC_G38

G40

VCC_G40

G42

VCC_G42

J30

VCC_J30

J33

VCC_J33

J37

VCC_J37

J40

VCC_J40

K33

VCC_K33

K35

VCC_K35

K37

VCC_K37

K38

VCC_K38

K40

VCC_K40

K42

VCC_K42

K43

1

2

1 OF20

CC1237

10U_0603_6.3V6M

VCC_K43

VCC_SE NSE

VSS_SE NSE

VIDALE RT#

VCCSTG_ G20

1

CC1093

2 2

10U_0603_6.3V6M

VIDSCK

VIDSOUT

VCORE _VCC_SEN

E32

VCORE_ VSS_SEN

E33

CPU_SVID_A LERT#_R

B63

CPU_SV ID_CLK_R

A63

CPU_SV ID_DAT_R

D64

G20

?

1

1

CC1092

CC1091

2

10U_0603_6.3V6M

1

CC1089

2

10U_0603_6.3V6M

10U_0603_6.3V6M

VCORE_ VCC_SEN 59
VCORE_ VSS_SEN 59

+VCCSTG

1

CC1238

2

10U_0603_6.3V6M

VCORE_ VCC_SEN

VCORE_ VSS_SEN

1

RC77

1

RC82

59 VR_SV ID_ALRT#

59 VR_S VID_CLK

59 VR_S VID_DAT

+VCC_GT

1

CC1122

2

10U_0402_6.3V6M

@

Backsid e Cap 8x1 0uF 0402, SI T update

1

CC1123

2

10U_0402_6.3V6M

@

+CPU_C ORE +VCC_GT

2

100_04 02_1%

2

100_04 02_1%

SVID

RC131

1

2

1, Aler t# Route Between CLK and Data

1

1

1

CC1126

CC1125

CC1124

2

2

2

@

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

@

56_0402_5%

1

2 2

CD@ CD@

2

CC1127

@

10U_0402_6.3V6M

RC1544

1

+VCCST_CPU

100_0402_1%

1

CC1128

10U_0402_6.3V6M

VCCGT_V CC_SEN

VCCGT_V SS_SEN

RC132

2

1

100_0402_1%

RC133

RC134 1 @ 20_0402 _5%

RC1545 1 @ 20_0402_ 5%

1

CC1129

2

10U_0402_6.3V6M

1

RC83

1

RC98

1

CC42

0.1u_0 201_10V6K

@

2

1

2

220_04 02_1%

2

100_04 02_1%

2

100_04 02_1%

CPU_SV ID_ALERT#_R

CPU_SV ID_CLK_R

CPU_SV ID_DAT_R

59 VCCG T_VCC_SE N
59 VCCGT_ VSS_SEN

+VCC_GT

62000mA

VCCGT_VCC_SEN
VCCGT_VSS_S EN

SKL_ULT ?

UC1M

CPU POWER 2OF 4

A48

VCCGT_A 48

A53

VCCGT_A 53

A58

VCCGT_A 58

A62

VCCGT_A 62

A66

VCCGT_A 66

AA63

VCCGT_AA63

AA64

VCCGT_AA64

AA66

VCCGT_AA66

AA67

VCCGT_AA67

AA69

VCCGT_AA69

AA70

VCCGT_AA70

AA71

VCCGT_AA71

AC64

VCCGT_AC64

AC65

VCCGT_AC65

AC66

VCCGT_AC66

AC67

VCCGT_AC67

AC68

VCCGT_AC68

AC69

VCCGT_AC69

AC70

VCCGT_AC70

AC71

VCCGT_AC71

J43

VCCGT_J 43

J45

VCCGT_J 45

J46

VCCGT_J 46

J48

VCCGT_J 48

J50

VCCGT_J 50

J52

VCCGT_J 52

J53

VCCGT_J 53

J55

VCCGT_J 55

J56

VCCGT_J 56

J58

VCCGT_J 58

J60

VCCGT_J 60

K48

VCCGT_K 48

K50

VCCGT_K 50

K52

VCCGT_K 52

K53

VCCGT_K 53

K55

VCCGT_K 55

K56

VCCGT_K 56

K58

VCCGT_K 58

K60

VCCGT_K 60

L62

VCCGT_L6 2

L63

VCCGT_L6 3

L64

VCCGT_L6 4

L65

VCCGT_L6 5

L66

VCCGT_L6 6

L67

VCCGT_L6 7

L68

VCCGT_L6 8

L69

VCCGT_L6 9

L70

VCCGT_L7 0

L71

VCCGT_L7 1

M62

VCCGT_M 62

N63

VCCGT_N6 3

N64

VCCGT_N6 4

N66

VCCGT_N6 6

N67

VCCGT_N6 7

N69

VCCGT_N6 9

J70

VCCGT_S ENSE

J69

VSSGT_S ENSE V SSGTX_SE NSE

SKYLAK E-U_BGA13 56

REV = 1
@

1 OF 20

VCCGT_N7 0

VCCGT_N71
VCCGT_R63
VCCGT_R64
VCCGT_R65
VCCGT_R66
VCCGT_R67
VCCGT_R68
VCCGT_R69
VCCGT_R70
VCCGT_R71
VCCGT_T62
VCCGT_U65
VCCGT_U68
VCCGT_U71
VCCGT_W 63
VCCGT_W 64
VCCGT_W 65
VCCGT_W 66
VCCGT_W 67
VCCGT_W 68
VCCGT_W 69
VCCGT_W 70
VCCGT_W 71

VCCGT_Y6 2

VCCGTX_ AK42
VCCGTX_A K43
VCCGTX_A K45
VCCGTX_A K46
VCCGTX_A K48
VCCGTX_A K50
VCCGTX_A K52
VCCGTX_A K53
VCCGTX_A K55
VCCGTX_A K56
VCCGTX_A K58
VCCGTX_A K60
VCCGTX_A K70
VCCGTX_ AL43
VCCGTX_ AL46
VCCGTX_ AL50
VCCGTX_ AL53
VCCGTX_ AL56
VCCGTX_ AL60
VCCGTX_AM 48
VCCGTX_AM 50
VCCGTX_AM 52
VCCGTX_AM 53
VCCGTX_AM 56
VCCGTX_AM 58
VCCGTX_AU58
VCCGTX_AU63
VCCGTX_B B57
VCCGTX_BB 66

VCCGTX_ SENSE

+VCC_GT

N70

N71
R63
R64
R65
R66
R67
R68
R69
R70
R71
T62
U65
U68
U71
W 63
W 64

W 65
W 66
W 67
W 68
W 69
W 70
W 71

Y62

AK42

AK43
AK45
AK46
AK48
AK50
AK52
AK53
AK55
AK56
AK58
AK60
AK70
AL43
AL46
AL50
AL53
AL56
AL60
AM48
AM50
AM52
AM53
AM56
AM58
AU58
AU63
BB57

BB66

AK62

AL61

?

For UMA 2+3e

VCCGTX_ SENSE
VSSGTX_ SENSE

+VCC_GT

1
1

TC133 @
TC134 @

+CPU_C ORE

15x1uF 0201, SIT update to 0 402 package

1

1

1

1

2

CC1278

CC1101

1U_0402_6.3V6K

0_0402_ 5%

1

2

1U_0201_6.3V6-M

1

CC1102

2

2

1U_0402_6.3V6K

+V1.8 S_EDRAM

2

1

1

CC1283

CC1282

2

2

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1

1

1

CC1098

CC1099

CC1095

CC1096

CC1097

2

2

2

1U_0402_6.3V6K

B B

A A

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

For UMA 2+3e

5 4 3 2

CC1100

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

RC1642 1 U23E@ 20_0805_5 %

+1.8VA LW

RC1653 1 U23E@

1

1

CC1280

2

2

10U_0402_6.3V6-M

U23E@ U 23E@ U23 E@ U23E@ U23E@ U 23E@

U23E@

CC1104

1U_0402_6.3V6K

+VCCE OPIO+VCCOP C_1.0V

+V1.8 S_EDRAM

CC1279

1U_0201_6.3V6-M

1

1

CC1105

2

2

1U_0402_6.3V6K

1

1

CC1281

CC1274

2

2

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1

1

CC1108

CC1109

2

2

1U_0201_6.3V6-M

1U_0201_6.3V6-M

@

@

+VCCE OPIO +V 1.8S_EDRA M+VCCOP C_1.0V

U23E@

1

1

CC1276

CC1275

2

2

10U_0402_6.3V6-M

U23E@

1

CC1277

2

10U_0402_6.3V6-M

@

57 VCCOP C_SENSE

57 VSSO PC_SENSE

1U_0402_6.3V6K

+VCC_GT

Backsid e Cap 12x 1uF 0201, SI T update

1

CC1111

2

1U_0402_6.3V6K

1

CC1114

2

1U_0402_6.3V6K

1U_0402_6.3V6K

VCCEOP IO_SENSE

VSSEO PIO_SENS E

VCCOPC _SENSE

VSSOP C_SENSE

CC1115

1

1

CC1116

2

2

1U_0402_6.3V6K

VCCOPC _SENSE

VSSOP C_SENSE

RC1647 1 @

RC1648 1 @

1

CC1118

2

1U_0402_6.3V6K

RC1643 1 U23E@ 2100_040 2_1%

RC1644 1 U23E@ 2100_040 2_1%

1

U23E@ 2100_0402 _1%

RC1645

1

U23E@ 2100_04 02_1%

RC1646

2

0_0402_ 5%

2

0_0402_ 5%

1

1

1

CC1119

CC1240

CC1241

2

2

1U_0402_6.3V6K

VCCEOP IO_SENSE

VSSEOP IO_SENSE

2

1U_0402_6.3V6K

1U_0402_6.3V6K

+VCCOP C_1.0V

+VCCE OPIO

Security Clllassiiifiiication

Issued Date

THIS SHEE T OF ENGIIINEERIIING DRAWIIING IS THE PR OPRIETARY PROP ERTY OF LC FUTUR E CENTER... AND CONTAINS CONFIIIDENTIAL
AND TRAD E SECRET IIINFORMATIIION... THI S SHEET MAY NO T BE TRANSFER ED FROM THE C USTODY OF THE CO MPETENT DIVISIO N OF R& D
DEPARTMENT E XCEPT AS AUTHORIIIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE IIINFORMATIIION IIITC ONTAINS
MAY BE USED BY OR DISCLOS ED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF LC FUTURE CE NTER.

+VCC_GT

1

1

CC1290

2

2

10U_0402_6.3V6-M

U23E@ U23E@ U 23E@ U2 3E@ U23E @ U23E@ U23E@ U23E@

LC Future Center Secret Data

DecipheredDate

Backsid e Cap 8x1 0uF 0402

1

1

1

CC1284

CC1285

CC1289

CC1291

2

2

2

10U_0402_6.3V6-M

10U_0402_6.3V6-M

10U_0402_6.3V6-M

10U_0402_6.3V6-M

2016/08/20

1

1

1

CC1286

CC1287

CC1288

2

2

2

10U_0402_6.3V6-M

10U_0402_6.3V6-M

10U_0402_6.3V6-M

Title

MCP (CPU PWR1)2015/08/20

Siiize Documenttt Number

Custo m

Dattte: Sheet 1 2 of 60

DG42A

Sunday, ,, Ja nua ry 22,,, 2017

1

R ev

1.0

5 4 3 2 1

3100mA

5100mA

VCCIO_SE NSE
VSSIO_SENSE

VCCSA _VSS_SEN
VCCSA_VCC_SEN

+VCC IO

+VCCSA

1

TC136 @

1

TC137 @

VCCSA _VSS_SEN 59
VCCSA _VCC_SE N 59

VCCSA_VCC_SEN

VCCSA _VSS_SEN

?

AU23

VDDQ_A U23

AU28

VDDQ_A U28

AU35

VDDQ_A U35

AU42

VDDQ_A U42

BB23

VDDQ_B B23

BB32

VDDQ_B B32

BB41

VDDQ_B B41

BB47

VDDQ_B B47

BB51

VDDQ_B B51

AM40

VDDQC

A18

VCCST

A22

VCCSTG_ A22

AL23

VCCPLL _OC

K20

VCCPLL _K20

K21

VCCPLL _K21

SKYLAK E-U_BGA13 56

REV = 1
@

UC1N

SKL_ULT

CPU POWER 3OF 4

1 OF 20

VCCIO_A K28
VCCIO_A K30

VCCIO_A L30

VCCIO_A L42
VCCIO_A M28
VCCIO_A M30
VCCIO_A M42

VCCSA _AK23
VCCSA _AK25

VCCSA _G23

VCCSA _G25

VCCSA _G27

VCCSA _G28

VCCSA _J22
VCCSA _J23
VCCSA _J27
VCCSA _K23
VCCSA _K25
VCCSA _K27
VCCSA _K28
VCCSA _K30

VCCIO_S ENSE

VSSIO_S ENSE

VSSSA _SENSE
VCCSA _SENSE

AK28
AK30
AL30
AL42

AM28
AM30
AM42

AK23
AK25

G23
G25
G27

G28
J22
J23
J27
K23
K25
K27
K28
K30

AM23

AM22

H21

H20

?

+1.2V

2800mA

+1.2V

D D

C C

2A , 3x 22uF, 6x1 0uF, 4x1uF, SIT update

1

1

1

CC1168

CC1257

CC1258

2

2

2

10U_0603_6.3V6M

CD@

22U_0603_6.3V6-M

22U_0603_6.3V6-M

RC1497 1 @ 20_0402_5 %

+1.2V

RC104 1 @ 20_0402_ 5%

CD@

1

CC1256

2

22U_0603_6.3V6-M

1

CC1222

2

10U_0603_6.3V6M

+VDDQ_ CPU_CLK

@

+VCCSFR_OC

1

1

CC1244

CC1243

CC1223

2

2

10U_0603_6.3V6M

@

1

1

CC1229

2

2

1U_0201_6.3V6-M

1

CC85

2

1U_0201_6.3V6-M

CC1224

2

2 2

1U_0201_6.3V6-M

10U_0402_6.3V6M

10U_0402_6.3V6M

@

CD@ @

CC1228

10U_0402_6.3V6M

1

1

CC1171

CC1169

2

2

10U_0402_6.3V6M

10U_0402_6.3V6M

1

1

1

1

1

CC1227

CC1226

CC1225

2 2

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

CD@ @

RC103 1 @ 20_0402_5 %

+VCCIO

+VCCST_CPU

Reserved for VCCST/VCCSTG/VC CPLL
power optimized

+VCCST_CPU

RC1604 1@

RC105 1 @ 20_0402_ 5%

2

0_0402_ 5%

+VDDQ_CPU_ CLK

+VCCST_CPU

+VCCSTG

+VCCSFR_OC

+VCCPLL_CPU

+VCCSTG

1

2

CC87

1U_0402_6.3V6K

1

2

130mA

+VCCST_CPU

+VCCPLL_CPU

CC1249

0.1u_0201_10V6K

1

2

120mA

1

2

120mA

CC86

1U_0402_6.3V6K

CC84

1U_0402_6.3V6K

+VCCIO

3.1A 2x 10uF, 4x1uF

1

1

1

CC1153

CC1152

2

2

2

10U_0402_6.3V6M

10U_0402_6.3V6M

@

+VCCSA

4.5A 10 x10uF, 7x 1uF, SIT updat e

1

1

1

CC1133

2

2

2

CC1132

10U_0603_6.3V6M

10U_0603_6.3V6M

@

2

1

RC101

RC102

100_04 02_1%

2

1

100_04 02_1%

1

1

1

1

1

CC1230

2

2

1U_0402_6.3V6K

1

1

CC1251

2

2

10U_0603_6.3V6M

@

1

CC1231

CC1232

2

1U_0402_6.3V6K

1U_0402_6.3V6K

@

1

1

CC1252

CC1253

2

2

10U_0402_6.3V6M

10U_0402_6.3V6M

@

RC1605 1@ 20_0402_5 %

1

1

1

CC1139

2

1U_0402_6.3V6K

CD@

CC1145

CC1140

CC1142

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

CD@

1

1

1

CC1144

CC1141

CC1143

2

2

2

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

CD@

1

CC1159

CC1161

CC1158

2

2

1U_0201_6.3V6-M

1U_0201_6.3V6-M

@

@

1

1

CC1135

CC1134

2

2

10U_0402_6.3V6M

10U_0402_6.3V6M

@

+VCCSA

CC1218

CC1160

2

2

1U_0402_6.3V6K

1U_0201_6.3V6-M

1U_0201_6.3V6-M

@

1

CC1136

CC1137

2

10U_0603_6.3V6M

10U_0603_6.3V6M

+1.0VA LW +VCCS T_CPU

Reserve d for VCC ST/VCCSTG/VC CPLL powe r optimiz ed

1

2

+VCC IO

1

CC1250

2

@

10U_060 3_6.3V6M

+VCCST_CPU

1

2

@

2016/08/20

C1102

22U_0603_6.3V6-M

CC80

10U_0603_6.3V6M

Title

MCP (CPU PWR2)2015/08/20

Siiize Documenttt Number

Custo m

Dattte: Sheet 1 3 of 60

DG42A

Sunday, ,, Ja nua ry 22,,, 2017

1

R ev

1.0

+1.0VA LW

B B

A A

44 EC_VCC IO_EN

11,44 PM_SL P_S3#

44 EC_VCC ST_EN

5 4 3 2

RC128 1 @ 20_0402 _5%

1 2

DC1

RB751V -40_SOD323- 2

RC142 1 @ 20_0402_ 5%

@

VCCIO_EN

1

0.01U_ 0201_6.3V7-K
CC77

2

@

VCCST_E N

1

0.01U_ 0201_6.3V7-K
CC81

2

@

+1.0VA LW

CC79

10U_0603_6.3V6M

1

1

CC72

CC71

2

2

10U_0603_6.3V6M

@

22U_0603_6.3V6-M

1

2

+5VALW

VCCIO_EN

VCCST_E N

UC4

1

IN1_1

2

IN1_2

3

EN1

4

VBIAS

5

EN2

6

IN2_1

7

IN2_2

G5016K D1U_TDFN14_ 2X3

OUT1_2
OUT1_1

OUT2_2
OUT2_1

GPAD

14

13

12

1 2

CC1293

CT1

11

GND

10

CC1292

CT2

9
8

15

1 2

1000P _0201_50V7-K

1000P _0201_50V7-K

Follow DG470 change to Dual Switch 8/24 wei

Security Clllassiiifiiication

Issued Date

THIS SHEE T OF ENGIIINEERIIING DRAWIIING IS THE PR OPRIETARY PROP ERTY OF LC FUTUR E CENTER... AND CONTAINS CONFIIIDENTIAL
AND TRAD E SECRET IIINFORMATIIION... THI S SHEET MAY NO T BE TRANSFER ED FROM THE C USTODY OF THE CO MPETENT DIVISIO N OF R& D
DEPARTMENT E XCEPT AS AUTHORIIIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE IIINFORMATIIION IIITC ONTAINS
MAY BE USED BY OR DISCLOS ED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF LC FUTURE CE NTER.

LC Future Center Secret Data

DecipheredDate

5 4 3 2 1

RC1503 1 @ 2 0_0603_5%

+1.0VALW

RC1504 1 @ 2 0_0402_5%

+1.0VALW

D D

+3VALW_PCH

RC1586 1 @ 2

0_0402_5%

+VCCAMPHY

+VCCAPLL_1P0

+VCCHDA

+VCCPGPPG+3VALW_PCH

RC1622 1 @ 2 0_0402_5%

CC147

1U_0201_6.3V6-M

0.642A

+3VALW_PCH

VCCMPHYON_1P0_L1

+VCCDSW_1P0

+VCCHDA

1

CC171

2

1U_0402_6.3V6K

CD@

1

2

+1.0VALW

1

CC145

2

1U_0402_6.3V6K

PCH Internal VRM

1

CC165

2

+3VALW_PCH

0.1u_0201_10V6K

75mA

+1.0VALW

CC144

68mA

1U_0402_6.3V6K

+3VALW

AK15 20mA

AG15 4mA
Y16 6mA
Y15 8mA
T16 6mA
AF16 161mA
AD15 61mA

V19

T1

AA1 6mA

AK17 1mA

AK19
BB14

BB10 VCCRTCEXT

A14 35mA

K19 29mA

L21 24mA

N20 33mA

L19 4mA

A10 10mA

AN11

AN13

?

+3VALW_PCH

1mA

1

1

CC164

CC156

2

2

@

@

1U_0402_6.3V6K

1U_0402_6.3V6K

+1.8VALW

+1.0VALW

+1.0VALW
+VCCCLK4

+VCCCLK5

+VCCCLK4

+VCCCLK5

1

CC172

2

@

Near Y15

+1.0VALW

1

1

CC173

2

1U_0402_6.3V6K

2

@

1U_0402_6.3V6K

CC174

1U_0402_6.3V6K

1

CC57

2

1U_0402_6.3V6K

RC1588 1 @ 2 0_0603_5%

RC1589 1 @ 2 0_0603_5%

+VCCPGPPG

1

2

@

+1.0VALW

1

C1099

2

@

1

C1100

2

@

22U_0603_6.3V6-M 22U_0603_6.3V6-M

CC175

1U_0402_6.3V6K

1

CC176

2
@

RC1587 1 @ 2 0_0603_5%

1

1

CC56

2

2

@

1U_0402_6.3V6K

+1.0VALW

+1.0VALW

1U_0402_6.3V6K

C1098

+3VALW_PCH

22U_0603_6.3V6-M

+1.0VALW

+1.8VALW

1

CC142

2

1

1U_0402_6.3V6K

CC149

2

0.1u_0201_10V6K

1

CC55

2

0.1u_0201_10V6K

+3VALW_PCH

1

CC143

2

1U_0402_6.3V6K

VCCRTC

1

1

CC146

CC1242

2

2

1U_0402_6.3V6K

0.1u_0201_10V6K

1

CC158

CC153

VCCMPHYON_1P0_L1

11mA

+1.0VALW

Near AB19

1U_0402_6.3V6K

0.696A

1

CC141

2

@

1U_0402_6.3V6K

33mA

1

CC169

2

AB19
AB20

P18

AF18

VCCPRIM _CORE_A F18

AF19

VCCPRIM _CORE_A F19

V20

VCCPRIM _CORE_V20

V21
AL1

K17

VCCMP HYAON_1P0 _K17

L1

N15
N16

VCCMP HYGT_1P0_N 16

N17

VCCMP HYGT_1P0_N 17

P15

VCCMP HYGT_1P0_P 15

P16
K15

VCCAM PHYPLL_1P0_K 15

L15
V15

AB17

VCCPRIM _1P0_AB17

Y18

AD17

VCCDSW _3P3_AD17

AD18

VCCDSW _3P3_AD18

AJ17
AJ19
AJ16
AF20

AF21

VCCSRA M_1P0_AF21

T19

VCCSRA M_1P0_T19

T20

AJ21

AK20

N18

SKYLAKE-U_BGA1356

REV = 1
@

1U_0402_6.3V6K

UC1O

VCCPRIM _1P0_AB19
VCCPRIM _1P0_AB20
VCCPRIM _1P0_P18

VCCPRIM _CORE_V21
DCPDSW _1P0

VCCMP HYAON_1P0 _L1
VCCMP HYGT_1P0_N 15

VCCMP HYGT_1P0_P 16

VCCAM PHYPLL_1P0_L15
VCCAP LL_1P0

VCCPRIM _1P0_Y18

VCCDSW _3P3_AJ17
VCCHDA
VCCSPI
VCCSRA M_1P0_AF20

VCCSRA M_1P0_T20
VCCPRIM _3P3_AJ21
VCCPRIM _1P0_AK20
VCCAP LLEBB

SKL_ULT

CPU POWER 4OF 4

?

1 OF20

VCCPGP PA

VCCPGP PB
VCCPGP PC
VCCPGP PD

VCCPGP PE

VCCPGP PF
VCCPGP PG

VCCPRIM _3P3_V19

VCCPRIM_1P0_T1

VCCATS_1P8

VCCRTCP RIM_3P3

VCCRTC_ AK19
VCCRTC_ BB14

DCPRTC
VCCCLK 1
VCCCLK 2
VCCCLK 3
VCCCLK 4
VCCCLK 5
VCCCLK 6

GPP_B0 /CORE_VID 0
GPP_B1 /CORE_VID 1

+1.0VALW

2.574A22mA

1

2 2

@

Near AF18

22U_0603_6.3V6-M

0.118A

Near A18

1

2

1

2

CC151

1U_0402_6.3V6K

CC154

1U_0402_6.3V6K

Near K15

22mA

+1.0VALW

1

CC159

2

CD@

1U_0402_6.3V6K

+1.0VALW

1

2

@

RC1620 1 @ 2 0_0402_5%

1.5A

1

CC148

2

47U_0805_4V6-M

Near AF20

+1.0VALW

C C

+1.0VALW

Near N15

+VCCAMPHY

+VCCAPLL_1P0

+1.0VALW

B B

88mA

1

C1096

2
@

22U_0603_6.3V6-M

1

C1097

2

0.1u_0201_10V6K

A A

Securiiity Clllassiiifiiicatiiion

Issued Date

THIS SHEET OF ENGINEERING DRAWING IIIS THE PROPRIETARY PROPE RTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIIIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMP ETENT DIVIIISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEIIITHER THIS SHEET NOR THE INFORMATION IIIT CONTAINS

5 4 3 2 1

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WIIITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

2015/08/20 Deciiiphered Date

LC Future Center Secret Data

2016/08/20

Tit le

MCP (PCH PWR)

Siiize Document Number

Custom

Sunday,,, J anua ry 22 ,2017

Date:

DG42A

Sheet 14 of 60

Re v

1.0

5 4 3 2 1

?

L_ULT

?

_ULT

D D

C C

B B

USCK1LP

A5

VSS_A5

A67

VSS_A6 7

A70

VSS_A7 0

AA2

VSS_AA2

AA4

VSS_AA4

AA65

VSS_AA65

AA68

VSS_AA68

AB15

VSS_AB15

AB16

VSS_AB16

AB18

VSS_AB18

AB21

VSS_AB21

AB8

VSS_AB8

AD13

VSS_AD1 3

AD16

VSS_AD1 6

AD19

VSS_AD1 9

AD20

VSS_AD2 0

AD21

VSS_AD2 1

AD62

VSS_AD6 2

AD8

VSS_AD8

AE64

VSS_AE64

AE65

VSS_AE65

AE66

VSS_AE66

AE67

VSS_AE67

AE68

VSS_AE68

AE69

VSS_AE69

AF1

VSS_AF1

AF10

VSS_AF10

AF15

VSS_AF15

AF17

VSS_AF17

AF2

VSS_AF2

AF4

VSS_AF4

AF63

VSS_AF63

AG16

VSS_AG16

AG17

VSS_AG17

AG18

VSS_AG18

AG19

VSS_AG19

AG20

VSS_AG20

AG21

VSS_AG21

AG71

VSS_AG71

AH13

VSS_AH1 3

AH6

VSS_AH6

AH63

VSS_AH6 3

AH64

VSS_AH6 4

AH67

VSS_AH6 7

AJ15

VSS_AJ15

AJ18

VSS_AJ18

AJ20

VSS_AJ20

AJ4

VSS_AJ4

AK11

VSS_AK11

AK16

VSS_AK16

AK18

VSS_AK18

AK21

VSS_AK21

AK22

VSS_AK22

AK27

VSS_AK27

AK63

VSS_AK63

AK68

VSS_AK68

AK69

VSS_AK69

AK8

VSS_AK8

AL2

VSS_AL 2

AL28

VSS_AL 28

AL32

VSS_AL 32

AL35

VSS_AL 35

AL38

VSS_AL 38

AL4

VSS_AL 4

AL45

VSS_AL 45

AL48

VSS_AL 48

AL52

VSS_AL 52

AL55

VSS_AL 55

AL58

VSS_AL 58

AL64

VSS_AL 64

SKYLAKE-U_BGA13 56

REV = 1
@

GND 1 OF 3

1 OF20

VSS_AL 65

VSS_AL 66
VSS_AM1 3
VSS_AM2 1
VSS_AM2 5
VSS_AM2 7
VSS_AM4 3
VSS_AM4 5
VSS_AM4 6
VSS_AM5 5
VSS_AM6 0
VSS_AM6 1
VSS_AM6 8
VSS_AM7 1

VSS_AM8
VSS_AN2 0
VSS_AN2 3
VSS_AN2 8
VSS_AN3 0
VSS_AN3 2
VSS_AN3 3
VSS_AN3 5
VSS_AN3 7
VSS_AN3 8
VSS_AN4 0
VSS_AN4 2
VSS_AN5 8
VSS_AN6 3
VSS_AP10
VSS_AP18
VSS_AP20
VSS_AP23
VSS_AP28
VSS_AP32
VSS_AP35
VSS_AP38
VSS_AP42
VSS_AP58
VSS_AP63
VSS_AP68
VSS_AP70
VSS_AR1 1
VSS_AR1 5
VSS_AR1 6
VSS_AR2 0
VSS_AR2 3
VSS_AR2 8
VSS_AR3 5
VSS_AR4 2
VSS_AR4 3
VSS_AR4 5
VSS_AR4 6
VSS_AR4 8

VSS_AR5
VSS_AR5 0
VSS_AR5 2
VSS_AR5 3
VSS_AR5 5
VSS_AR5 8
VSS_AR6 3

VSS_AR8

VSS_AT2
VSS_AT20
VSS_AT23
VSS_AT28
VSS_AT35

VSS_AT4
VSS_AT42
VSS_AT56
VSS_AT58

AL65
AL66
AM13
AM21
AM25
AM27
AM43
AM45
AM46
AM55
AM60
AM61
AM68
AM71
AM8
AN20
AN23
AN28
AN30
AN32
AN33
AN35
AN37
AN38
AN40
AN42
AN58
AN63
AP10
AP18
AP20
AP23
AP28
AP32
AP35
AP38
AP42
AP58
AP63
AP68
AP70
AR11
AR15
AR16
AR20
AR23
AR28
AR35
AR42
AR43
AR45
AR46
AR48
AR5
AR50
AR52
AR53
AR55
AR58
AR63
AR8
AT2
AT20
AT23
AT28
AT35
AT4
AT42
AT56
AT58

?

UCSK1Q

AT63

VSS_AT63

AT68

VSS_AT68

AT71

VSS_AT71

AU10

VSS_AU1 0

AU15

VSS_AU1 5

AU20

VSS_AU2 0

AU32

VSS_AU3 2

AU38

VSS_AU3 8

AV1

VSS_AV1

AV68

VSS_AV68

AV69

VSS_AV69

AV70

VSS_AV70

AV71

VSS_AV71

AW 10

VSS_ AW1 0

AW 12

VSS_ AW1 2

AW 14

VSS_ AW1 4

AW 16

VSS_ AW1 6

AW 18

VSS_ AW1 8

AW 21

VSS_ AW2 1

AW 23

VSS_ AW2 3

AW 26

VSS_ AW2 6

AW 28

VSS_ AW2 8

AW 30

VSS_ AW3 0

AW 32

VSS_ AW3 2

AW 34

VSS_ AW3 4

AW 36

VSS_ AW3 6

AW 38

VSS_ AW3 8

AW 41

VSS_ AW4 1

AW 43

VSS_ AW4 3

AW 45

VSS_ AW4 5

AW 47

VSS_ AW4 7

AW 49

VSS_ AW4 9

AW 51

VSS_ AW5 1

AW 53

VSS_ AW5 3

AW 55

VSS_ AW5 5

AW 57

VSS_ AW5 7

AW 6

VSS_ AW6

AW 60

VSS_ AW6 0

AW 62

VSS_ AW6 2

AW 64

VSS_ AW6 4

AW 66

VSS_ AW6 6

AW 8

VSS_ AW8

AY66

VSS_AY66

B10

VSS_B1 0

B14

VSS_B1 4

B18

VSS_B1 8

B22

VSS_B2 2

B30

VSS_B3 0

B34

VSS_B3 4

B39

VSS_B3 9

B44

VSS_B4 4

B48

VSS_B4 8

B53

VSS_B5 3

B58

VSS_B5 8

B62

VSS_B6 2

B66

VSS_B6 6

B71

VSS_B7 1

BA1

VSS_BA1

BA10

VSS_BA10

BA14

VSS_BA14

BA18

VSS_BA18

BA2

VSS_BA2

BA23

VSS_BA23

BA28

VSS_BA28

BA32

VSS_BA32

BA36

VSS_BA36

F68

VSS_F68

BA45

VSS_BA45

SKYLAKE-U_BGA13 56

REV = 1
@

GND 2 OF 3

1 OF20

VSS_BA49
VSS_BA53
VSS_BA57

VSS_BA6
VSS_BA62
VSS_BA66
VSS_BA71
VSS_BB18
VSS_BB26
VSS_BB30
VSS_BB34
VSS_BB38
VSS_BB43
VSS_BB55

VSS_BB6
VSS_BB60
VSS_BB64
VSS_BB67
VSS_BB70

VSS_C1

VSS_C25

VSS_C5
VSS_D10
VSS_D11
VSS_D14
VSS_D18
VSS_D22
VSS_D25
VSS_D26
VSS_D30
VSS_D34
VSS_D39
VSS_D44
VSS_D45
VSS_D47
VSS_D48
VSS_D53
VSS_D58

VSS_D6
VSS_D62
VSS_D66
VSS_D69
VSS_E1 1
VSS_E1 5
VSS_E1 8
VSS_E2 1
VSS_E4 6
VSS_E5 0
VSS_E5 3
VSS_E5 6

VSS_E6
VSS_E6 5
VSS_E7 1

VSS_F1

VSS_F13

VSS_F2

VSS_F22
VSS_F23
VSS_F27
VSS_F28
VSS_F32
VSS_F33
VSS_F35
VSS_F37
VSS_F38

VSS_F4

VSS_F40
VSS_F42

VSS_BA41

BA49
BA53
BA57
BA6
BA62
BA66
BA71
BB18
BB26
BB30
BB34
BB38
BB43
BB55
BB6
BB60
BB64
BB67
BB70
C1
C25
C5
D10
D11
D14
D18
D22
D25
D26
D30
D34
D39
D44
D45
D47
D48
D53
D58
D6
D62
D66
D69
E11
E15
E18
E21
E46
E50
E53
E56
E6
E65
E71
F1
F13
F2
F22
F23
F27
F28
F32
F33
F35
F37
F38
F4
F40
F42
BA41

?

G10
G22
G43
G45
G48

G52
G55
G58

G60
G63
G66
H15
H18
H71

K16
K18
K22
K61
K63
K64
K65
K66
K67
K68
K70
K71

G5

G6

J11
J13
J25
J28
J32
J35
J38
J42

L11
L16
L17

F8

J8

VSS_ F8
VSS_G10
VSS_G22
VSS_G43
VSS_G45
VSS_G48
VSS_G5
VSS_G52
VSS_G55
VSS_G58
VSS_G6
VSS_G60
VSS_G63
VSS_G66
VSS_H15
VSS_H18
VSS_H71
VSS_J11
VSS_J13
VSS_J25
VSS_J28
VSS_J32
VSS_J35
VSS_J38
VSS_J42
VSS_J8
VSS_K1 6
VSS_K1 8
VSS_K2 2
VSS_K6 1
VSS_K6 3
VSS_K6 4
VSS_K6 5
VSS_K6 6
VSS_K6 7
VSS_K6 8
VSS_K7 0
VSS_K7 1
VSS_L1 1
VSS_L1 6
VSS_L1 7

?

SKL_ULT

UC1R

GND 3 OF 3

1 OF20

SKYLAKE-U_BGA13 56

REV = 1
@

VSS_L1 8

VSS_L2

VSS_L2 0

VSS_L4

VSS_L8
VSS_N10
VSS_N13
VSS_N19
VSS_N21

VSS_N6
VSS_N65
VSS_N68
VSS_P1 7
VSS_P1 9
VSS_P2 0
VSS_P2 1
VSS_R13

VSS_R6
VSS_T15
VSS_T17
VSS_T18

VSS_T2

VSS_T21

VSS_T4
VSS_U10
VSS_U63
VSS_U64
VSS_U66
VSS_U67
VSS_U69
VSS_U70
VSS_V1 6
VSS_V1 7
VSS_V1 8

VSS_ W13

VSS_ W6

VSS_ W9
VSS_Y1 7
VSS_Y1 9
VSS_Y2 0
VSS_Y2 1

L18
L2
L20
L4
L8
N10
N13
N19
N21
N6
N65
N68
P17
P19
P20
P21
R13
R6
T15
T17
T18
T2
T21
T4
U10
U63
U64
U66
U67
U69
U70
V16
V17
V18
W1 3
W6
W9
Y17
Y19
Y20
Y21

?

A A

Security Classification LC Future Center Secret Data

Issued Date

THIIIS SHEET OF ENGIIINEERING DRAWIIING IIIS THE PROPRIE TARY PR OPERTY OF LC FUTURE C ENTER. A ND CONTAIIINS CONFIDENTIIIAL
AND TRAD E SEC RET IIINFORMATIIION... THIIIS SHEE T MAY NOT BE TRAN SFERED FROM THE CUSTOD Y OF THE COMP ETENT DIVIIISIIION OF R& D
DEPAR TMENT EXCE PT AS AUTHORIZE D BY L C FUTURE CENTER NEIIITHER THIIIS SHEET N OR THE IIINFORMATIIION IIIT CONTAIIINS
MAY BE USED BY OR DISCLO SED TO A NY THIRD PARTY WIIITHOUT PRIO R WR ITTEN CONSEN T OF LC FUTU RE CE NTER.

5 4 3 2 1

2015/08/20 DecipheredDate

2016/08/20

Title

MCP (VSS)

Siiize Document Number

Custom

DG42A

R ev

Sheet 15 of 60Date: S un da y, Ja nu ar y 22, 2017

1.0

5

CPU_CFG0

D D

2

RC1618
1K_0402_5%

@

1

C C

B B

2

RC106
1K_0402_5%

1

2

RC162

49.9_0402_1%

1

Pin Name Strap Descri ption Configuration

A A

CFG[4]

Display Port
Presence s trap

— 1 = eDP Disabled

— 0 = eDP Enabled

5

*

PAD @ TC142
PAD @ TC143
PAD @TC144

PAD @ TC146
PAD @ TC147
PAD @ TC148
PAD @ TC153
PAD @ TC150
PAD @ TC151
PAD @ TC152
PAD @ TC157
PAD @ TC154
PAD @ TC155
PAD @TC156

PAD @TC159
PAD @TC158

PAD @TC161
PAD @TC160

PAD @TC166

PAD @TC186

PAD @TC189
PAD @TC191

PAD @TC171
PAD @TC172

PAD @TC169
PAD @TC170

Default
Value

1

CPU_CFG1

1

CPU_CFG2

1

XDP_CPU_CFG3

1

CPU_CFG4
CPU_CFG5

1

CPU_CFG6

1

CPU_CFG7

1

CPU_CFG8

1

CPU_CFG9

1

CPU_CFG10

1

CPU_CFG11

1

CPU_CFG12

1

CPU_CFG13

1

CPU_CFG14

1

CPU_CFG15

1

CPU_CFG16

1

CPU_CFG17

1

CPU_CFG18

1

CPU_CFG19

1

CFG_RCOMP
XDP_ITP_PMODE

1

1

1
1

1
1

1
1

4

E68

CFG[0]

B67

CFG[1]

D65

CFG[2]

D67

CFG[3]

E70

CFG[4]

C68

CFG[5]

D68

CFG[6]

C67

CFG[7]

F71

CFG[8]

G69

CFG[9]

F70

CFG[10]

G68

CFG[11]

H70

CFG[12]

G71

CFG[13]

H69

CFG[14]

G70

CFG[15]

E63

CFG[16]

F63

CFG[17]

E66

CFG[18]

F66

CFG[19]

E60

CFG_RCOMP

E8

ITP_PMODE

AY2

RSVD_AY2

AY1

RSVD_AY1

D1

RSVD_D1

D3

RSVD_D3

K46

RSVD_K46

K45

RSVD_K45

AL25

RSVD_AL25

AL27

RSVD_AL27

C71

RSVD_C71

B70

RSVD_B70

F60

RSVD_F60

A52

RSVD_A52

BA70

RSVD_TP_BA70

BA68

RSVD_TP_BA68

J71

RSVD_J71

J68

RSVD_J68

F65

VSS_F65

G65

VSS_G65

F61

RSVD_F61

E61

RSVD_E61

SKYLAKE-U_BGA1356

REV = 1
@

4

UC1S

SKL_U LT

RESERVED SIGNALS-1

?

1 OF20

3 2 1

1

TC173 @ PAD
TC174 @PAD

1
1

TC175 @ PAD
TC176 @PAD

1

1

TC183 @ PAD
TC185 @PAD

1
1

TC184 @ PAD
TC181 @PAD

1

1

TC187 @PAD

1

TC182 @PAD

1

TC188 @ PAD
TC193 @PAD

1

1

TC190 @ PAD
TC192 @PAD

1

ZVM# 57

1

TC177 @ PAD

1

TC178 @PAD

1

TC168 @ PAD 1

2

LC Future Center SecretData

+1.8VALW

Cannonlake@

RC1582 2
RC1583 2

Cannonlake@

need to check with Intel

need to check with Intel

For UMA 2+3e

+VCCST_CPU

RSVD_BB2
RSVD_BA3

RSVD_D5
RSVD_D4

RSVD_B2
RSVD_C2

RSVD_B3
RSVD_A3

RSVD_AW1

RSVD_E1
RSVD_E2

RSVD_BA4
RSVD_BB4

RSVD_A4

RSVD_C4

RSVD_A69

RSVD_B69
RSVD_AY3
RSVD_D71

RSVD_C70
RSVD_C54

RSVD_D54

VSS_AY71

ZVM#

MSM#

BB68

BB69

AK13

AK12

BB2

BA3

AU5

TP5

AT5

TP6

D5
D4
B2

C2

B3

A3

AW1

E1

E2
BA4

BB4
A4

C4
BB5

TP4

A69
B69

RSVD_AY3

AY3
D71

C70
C54

D54
AY4

TP1

BB3

TP2

?

AR56

AW71
AW70

AP56
C64

AY71

VSS_AY71

PROC_SELECT#

100K_0402_5% Cannonlake@ R22

RSVD_TP_BB68
RSVD_TP_BB69

RSVD_TP_AK13
RSVD_TP_AK12

RSVD_TP_AW71
RSVD_TP_AW70

PROC_SELECT#

Security Classification

Issued Date

THISII SHEET OF ENGINII EERINII G DRAW INII G ISII THEPROPRIETARYII PROPERTY OF LC FUTURE CENTER. AND CONTAINII S
CONFIDII ENTIALII
AND TRADE SECRET INII FORMATIOII N. THISII SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISIOIIIIII N OF R&D
DEPARTMENT EXCEPT AS AUTHORIZII ED BY LC FUTURE CENTER NEITII HER THISII SHEET NOR THE INII FORMATIOII N ITIICONTAINSII
MAY BE USED BY OR DISCLII OSED TO ANY THIRDII PARTY WITII HOUT PRIOII R WRITTII EN CONSENT OF LC FUTURE CENTER.

3 2

2015/08/20 Deciphered Date

1

0_0402_5%

1

0_0402_5%

2016/08/20

@

@

1

1

RSVD_U12
RSVD_U11

2

RC107
0_0402_5%

2

RC108
0_0402_5%

?

SKL_U LT

UC1T

RSVD_AW69

RSVD_AW68

RSVD_AU56

RSVD_H11

SPARE

1 OF20

RSVD_F6

RSVD_E3
RSVD_C11
RSVD_B11
RSVD_A11
RSVD_D12

RSVD_C12
RSVD_F52

U12
U11

AW69
AW68

AU56

AW48

C7

RSVD_C7
RSVD_U12

H11

RSVD_AW48

RSVD_U11

SKYLAKE-U_BGA1356

REV = 1
@

Title

MCP (CFG,RESERVED)

Siiize Document Number

Custom

Date: Sheet

Sunday, J anuary 22, 2017

DG42A

+VCCST_CPU

F6
E3
C11
B11

A11

D12
C12

RSVD_F52

F52

?

1

1

RC1619
150_0402_5%

@

2

16 of 60

R ev

1.0

5

DDRA_MA0
DDRA_MA1
DDRA_MA2
DDRA_MA3
DDRA_MA4
DDRA_MA5
DDRA_MA6
DDRA_MA7
DDRA_MA8
DDRA_MA9
DDRA_MA10
DDRA_MA11
DDRA_MA12

D D

C C

B B

A A

5 DDRA_MA1 4_WE#
5 DD RA_MA15_C AS#

5 DDRA_MA 16_RAS #

5 D DRA_CLK0#
5 D DRA_CLK0

5 DDRA_CKE 0

+1.2V +1.2V

RD65 1 @ 2 0_0402_5%
RD68 1 @ 2 0_0402_5%

5 D DRA_BS0#
5 D DRA_BS1#

5 D DRA_ACT#
5 D DRA_CS0#

5 DDRA_ ALERT#
5 DDRA_BG0

5 DDRA_ODT0

5 DDRA _PAR

6,18 CPU_D RAMRST#

+1.2V

RD87 1 @ 2 0_0402_5%
RD88 1 @ 2 0_0402_5%

RD96 1 MD@ 2 10K_ 0402_5%

DDRA_MA13

DDRA_MA15 _CAS#
DDRA_MA16 _RAS#

DDRA_CL K0#
DDRA_CL K0

DDRA_CK E0
DDRA _DQS#0

DDRA _DQS0
DDRA _DQS#1
DDRA _DQS1

DDRA_DM1
DDRA_DM0

DDRA_BS 0#
DDRA_BS 1#

DDRA_AC T#
DDRA_CS 0#
DDRA_ALE RT#

DDRA_BG0

DDRA_ODT0

DDRA _PAR

TEN_UD1

CPU_DRA MRST#

@

1

2

CD47

0.1u_0201_10V6K

DDRA_MA0
DDRA_MA1
DDRA_MA2
DDRA_MA3
DDRA_MA4
DDRA_MA5
DDRA_MA6
DDRA_MA7
DDRA_MA8
DDRA_MA9
DDRA_MA10
DDRA_MA11
DDRA_MA12
DDRA_MA13

DDRA_MA15 _CAS#
DDRA_MA16 _RAS#

DDRA_CL K0#
DDRA_CL K0

DDRA_CK E0

DDRA_DQS# 5
DDRA_DQS5
DDRA_DQS# 4

DDRA_DQS4

DDRA_DM4
DDRA_DM5

DDRA_BS 0#
DDRA_BS 1#

DDRA_AC T#
DDRA_CS 0#
DDRA_ALE RT#

DDRA_BG0

DDRA_ODT0

DDRA_PA R

TEN_UD3

CPU_DRA MRST#

@

1

2

0.1u_0201_10V6K

CD107

UD1 @

P3

A0

P7

A1

R3

A2

N7

A3

N3

A4

P8

A5

P2

A6

R8

A7

R2

A8

R7

A9

M3

A10/AP

T2

A11

M7

A12/BC_N

T8

A13

L2

WE_N/A14

M8

CAS_N/A15

L8

RAS_N/A16

K8

CK_C

K7

CK_T

K2

CKE

F3

LDQS_C

G3

LDQS_T

A7

UDQS_C

B7

UDQS_T VDD10

E2

NF/UDM_N/UDBI_N VDDQ1

E7

NF/LDM_N/LDBI_N VDDQ2

N2

BA0

N8

BA1

L3

ACT_N

L7

CS_N

P9

ALERT_N

M2

BG0

K3

ODT

T3

PAR

N9RD94 1 MD@ 2 10K_0402_5%

TEN

P1

RESET_N

F1

VSSQ1

H1

VSSQ2

A2

VSSQ3

D2

VSSQ4

E3

VSSQ5

A8

VSSQ6

D8

VSSQ7

E8

VSSQ8

VSSQ9

C9

H9

VSSQ10

F9

ZQ

12

MD@ RD39 MT40A512M 16HA083 EA_FBGA 96

240_0402_1%

UD3

P3

A0

P7

A1

R3

A2

N7

A3

N3

A4

P8

A5

P2

A6

R8

A7

R2

A8

R7

A9

M3

A10/AP

T2

A11

M7

A12/BC_N

T8

A13

L2

WE_N/A14

M8

CAS_N/A15

L8

RAS_N/A16

K8

CK_C

K7

CK_T

K2

CKE

F3

LDQS_C

G3

LDQS_T

A7

UDQS_C

B7

UDQS_T VDD10

E2

NF/UDM_N/UDBI_NVDDQ1

E7

NF/LDM_N/LDBI_N VDDQ2

N2

BA0

N8

BA1

L3

ACT_N

L7

CS_N

P9

ALERT_N

M2

BG0

K3

ODT

T3

PAR

N9

TEN

P1

RESET_N

F1

VSSQ1

H1

VSSQ2

A2

VSSQ3

D2

VSSQ4

E3

VSSQ5

A8

VSSQ6

D8

VSSQ7

E8

VSSQ8

VSSQ9

C9

H9

VSSQ10

F9

ZQ

12

RD43 MT40A512M16H A083EA _FBGA9 6

MD@

240_0402_1%

VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

VDDQ9

VDDQ10

VREFCA

VDDQ10

VREFCA

C1

DDRA_DQ2 DD RA_DQ18

G2

DQ0

DDRA_DQ3

F7

DDRA_DQ7

DQ1

H3

DQ2

DDRA_DQ1

H7

DDRA_DQ4

DQ3
DQ4

DDRA_DQ0

H8

DDRA_DQ6

DQ5

J3

DQ6

DDRA_DQ5

J7

DDRA_DQ11

DQ7

A3

DQ8

DDRA_DQ8

B8

DDRA_DQ14

DQ9

C3

DDRA_DQ13

DQ10

C7

DQ11

DDRA_DQ15

C2

DDRA_DQ12

DQ12

C8

DQ13

DDRA_DQ10

D3

DDRA_DQ9DDRA_MA14 _WE#

DQ14

D7

DQ15

+1.2V

D1

VDD1

J1

VDD2

L1

VDD3

R1

VDD4

B3

VDD5

G7

VDD6

B9

VDD7

J9

VDD8

VDD9

L9

T9

A1

C1

G1

VDDQ3

F2

VDDQ4

J2

VDDQ5

F8

VDDQ6

J8

VDDQ7

A9

VDDQ8

D9

VDDQ9

G9

B1

VPP1

R9

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8

VDD9

VPP1
VPP2

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7

VSS8
VSS9

VPP2

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7

VSS8
VSS9

@

G1

NC

+VREF_CA _MD

M1
E1

K1

N1
T1
B2
G8
E9
K9

M9

T7

NC

G2

F7
H3
H7
H2
H8
J3
J7
A3
B8
C3

C7

C2

C8

D3

D7

D1

J1

L1

R1

B3

G7

B9
J9
L9

T9

A1

F2
J2
F8
J8
A9
D9

G9

B1

R9

M1

E1

K1
N1
T1
B2
G8
E9
K9

M9

T7

DDRA_DQ43
DDRA_DQ44
DDRA_DQ46
DDRA_DQ40
DDRA_DQ47
DDRA_DQ45
DDRA_DQ42
DDRA_DQ41
DDRA_DQ34
DDRA_DQ37
DDRA_DQ39
DDRA_DQ32
DDRA_DQ35
DDRA_DQ33
DDRA_DQ38

DDRA_DQ36DDRA_MA14 _WE#

+1.2V

MD@

+VREF_CA _MD

MD@

CD115

1

2 2

CD113

1

2

.047U_0201_6.3V6K

.047U_0201_6.3V6K

MD@

4

DDRA_MA0
DDRA_MA1
DDRA_MA2
DDRA_MA3
DDRA_MA4
DDRA_MA5
DDRA_MA6
DDRA_MA7
DDRA_MA8
DDRA_MA9
DDRA_MA10
DDRA_MA11
DDRA_MA12
DDRA_MA13

L2

DDRA_MA15 _CAS#

M8

DDRA_MA16 _RAS#

L8

DDRA_CL K0#
DDRA_CL K0

DDRA_CK E0
DDRA_DQS# 2

DDRA_DQS2
DDRA_DQS# 3
DDRA_DQS3

RD66 1 @ 2 0_0402_5%
RD69 1 @ 2 0_0402_5%

+2.5V _DDR

1 1

MD@ CD@

1

MD@

2 2

1U_0402_6.3V6K

1U_0402_6.3V6K

CD121

CD@

1

2 2

CD150

1U_0402_6.3V6K

+2.5V _DDR

CD123

1

1U_0402_6.3V6K

CD@

CD151

0.1u_0201_10V6K

CD120

1

2

0.1u_0201_10V6K

CD149

+1.2V

RD89 1 @ 2 0_0402_5%
RD90 1 @ 2 0_0402_5%

RD97 1 MD@ 2 10K_0402 _5%

RD95 1 MD@ 2 10K_0 402_5%

DDRA_DM3
DDRA_DM2

DDRA_BS 0#
DDRA_BS 1#

DDRA_AC T#
DDRA_CS 0#
DDRA_ALE RT#

DDRA_BG0

DDRA_ODT0

DDRA_PA R

TEN_UD2

CPU_DRA MRST#

@

1

2

CD48

0.1u_0201_10V6K

12

RD40 MT40A512M16H A083EA _FBGA9 6

MD@

240_0402_1%

DDRA_MA0

P3

DDRA_MA1

P7

DDRA_MA2

R3

DDRA_MA3

N7

DDRA_MA4

N3

DDRA_MA5

P8

DDRA_MA6

P2

DDRA_MA7

R8

DDRA_MA8

R2

DDRA_MA9

R7

DDRA_MA10

M3

DDRA_MA11

T2

DDRA_MA12

M7

DDRA_MA13

T8

L2

DDRA_MA15 _CAS#

WE_N/A14

M8

DDRA_MA16 _RAS#

CAS_N/A15

L8

DDRA_CL K0#

K8

DDRA_CL K0

K7

DDRA_CK E0

K2

DDRA_DQS# 7

F3

DDRA_DQS7

G3

DDRA_DQS# 6

A7

DDRA_DQS6

B7

DDRA_DM6

E2

DDRA_DM7
DDRA_BS 0#

DDRA_BS 1#

DDRA_AC T#
DDRA_CS 0#
DDRA_ALE RT#

DDRA_BG0

DDRA_ODT0

DDRA_PA R

TEN_UD4

CPU_DRA MRST#

@

1

2

0.1u_0201_10V6K

CD108

NF/UDM_N/UDBI_NVDDQ1

E7
N2

N8
L3

L7
P9

M2
K3
T3
N9
P1
F1

H1
A2
D2
E3
A8
D8
E8
C9

H9
F9

12

RD44 MT40A512M16H A083EA _FBGA9 6

MD@

240_0402_1%

UD2 @

P3

A0

P7

A1

R3

A2

N7

A3

N3

A4

P8

A5

P2

A6

R8

A7

R2

A8

R7

A9

M3

A10/AP

T2

A11

M7

A12/BC_N

T8

A13

WE_N/A14

CAS_N/A15

RAS_N/A16

K8

CK_C

K7

CK_T

K2

CKE

F3

LDQS_C

G3

LDQS_T

A7

UDQS_C

B7

UDQS_T VDD10

E2

NF/UDM_N/UDBI_N VDDQ1

E7

NF/LDM_N/LDBI_N VDDQ2

N2

BA0

N8

BA1

L3

ACT_N

L7

CS_N

P9

ALERT_N

M2

BG0

K3

ODT

T3

PAR

N9

TEN

P1

RESET_N

F1

VSSQ1

H1

VSSQ2

A2

VSSQ3

D2

VSSQ4

E3

VSSQ5

A8

VSSQ6

D8

VSSQ7

E8

VSSQ8

VSSQ9

C9

H9

VSSQ10

F9

ZQ

UD4

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC_N

A13

RAS_N/A16

CK_C

CK_T
CKE

LDQS_C
LDQS_T
UDQS_C

UDQS_T VDD10

NF/LDM_N/LDBI_N VDDQ2

BA0

BA1

ACT_N
CS_N

ALERT_N
BG0

ODT
PAR
TEN

RESET_N

VSSQ1

VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8

VSSQ9

VSSQ10
ZQ

VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

VDDQ9

VDDQ10

VREFCA

3

G2

DQ0

DDRA_DQ19

F7

DDRA_DQ16

DQ1

H3

DQ2

DDRA_DQ21

H7

DDRA_DQ22

DQ3
DQ4

DDRA_DQ17

H8

DDRA_DQ23

DQ5

J3

DQ6

DDRA_DQ20

J7

DDRA_DQ30

DQ7

A3

DQ8

DDRA_DQ28

B8

DDRA_DQ26

DQ9

C3

DDRA_DQ25

DQ10

C7

DQ11

DDRA_DQ31

C2

DDRA_DQ29

DQ12

C8

DQ13

DDRA_DQ27

D3

DDRA_DQ24DDRA_MA14 _WE#

DQ14

D7

DQ15

+1.2V

D1

VDD1

J1

VDD2

L1

VDD3

R1

VDD4

B3

VDD5

G7

VDD6

B9

VDD7

J9

VDD8

VDD9

L9

T9

A1

C1

G1

VDDQ3

F2

VDDQ4

J2

VDDQ5

F8

VDDQ6

J8

VDDQ7

A9

VDDQ8

D9

VDDQ9

G9

VDDQ10

B1

VPP1

R9

VPP2

VREFCA

VSS1
VSS2
VSS3

VSS4
VSS5
VSS6
VSS7

VSS8
VSS9

@

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

VDD1

J1

VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8

VDD9

T9

C1

G1

G9

VPP1

R9

VPP2

VSS1
VSS2
VSS3

VSS4
VSS5
VSS6
VSS7

VSS8

M9

VSS9

NC

+VREF_CA _MD

M1

E1
K1
N1
T1
B2
G8
E9
K9

M9

T7

NC

DDRA_DQ59

G2

DDRA_DQ60

F7

DDRA_DQ62

H3

DDRA_DQ56

H7

DDRA_DQ63

H2

DDRA_DQ61

H8

DDRA_DQ58

J3

DDRA_DQ57

J7

DDRA_DQ54

A3

DDRA_DQ52

B8

DDRA_DQ51

C3

DDRA_DQ49

C7

DDRA_DQ50

C2

DDRA_DQ53

C8

DDRA_DQ55

D3

DDRA_DQ48DDRA_MA14 _WE#

D7

+1.2V

D1
L1

R1

B3

G7

B9
J9
L9

A1

F2
J2
F8
J8
A9
D9

B1

M1
E1

K1
N1
T1

B2
G8
E9
K9

T7

MD@

+VREF_CA _MD

MD@

CD116

1

1

MD@

2

2

0.1u_0201_10V6K

.047U_0201_6.3V6K

CD122

CD114

1

1

MD@

2

2

0.1u_0201_10V6K

.047U_0201_6.3V6K

CD153

MD@ MD@

CD124

1 1

2 2

1U_0402_6.3V6K

CD@

CD154

+2.5V _DDR

1 1

2 2

1U_0402_6.3V6K

+2.5V _DDR

MD@

CD155

5 DDR_S A_VREF CA

1U_0402_6.3V6K

CD125

1U_0402_6.3V6K

0.022U_02 01_6.3V6 -K

24.9_0402_ 1% MD@

CD111

2

MD@ MD@

CD119 RD45

0.1u_0201_ 10V6K 1.8K_0 402_1%

RD46 1 2 MD@

2.7_0402_1 %

1

MD@

2

RD48

2 1

+1.2V

1

MD@

2

1U_0402_6.3V6K

CD127

CD126

+1.2V

1

CD@

2

10U_0603_6.3V6M

CD142

+2.5V _DDR

1

MD@

2

10U_0603_6.3V6M

CD152

+0.6V S

1

MD@ MD @

2

1U_0402_6.3V6K

CD158

CD159

+1.2V

1

2

2 1

RD47 MD@

MD@ 1.8K_ 0402_1%

2 1

(1uF_0402_6.3V) *16
Place 4 near each DRAM

1

1

1

MD@ MD @

2

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

CD@

CD128

CD129

(1OuF_0603_6.3V) *5
Place around the DRAMs

1

1

CD@

MD@

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

CD143

CD144

(1OuF_0603_6.3V) *3
Place around the DRAMs

1

1

MD@

CD@

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

CD156

CD147

(1uF_0402_6.3V) *8
Place 2 near each DRAM

1

1

1

CD@ CD@

2

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

CD@

CD161

CD160

DDRA_DQ[0 ..63]

DDRA_DQS# [0..7]

DDRA_DQS[ 0..7]

DDRA_MA[0 ..13]

+VREF_CA _MD

1

CD112

0.1u_0201_ 10V6K

2

1

1

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

CD133

1

2

1U_0402_6.3V6K

CD165

1 1

MD@ MD@ MD@

2 2

1U_0402_6.3V6K

CD134

CD135

+1.2V

+2.5V _DDR

(1OuF_0603_6.3V) *2
Place around the DRAMs

1

1

MD@

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

CD@

CD167

CD166

1

1

CD@

CD@ MD@

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

CD@

CD130

CD132

CD131

1

1

MD@

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

CD@

CD145

CD146

1

1

1

MD@ MD @

2

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

CD@

CD163

CD164

CD162

DDRA_DQ[0 ..63] 5

DDRA_DQS# [0..7] 5

DDRA_DQS[ 0..7] 5

DDRA_CLK 0#
DDRA_CL K0

DDRA_CS 0#
DDRA_ODT0

DDRA_CKE 0
DDRA_MA0

DDRA_MA1
DDRA_MA2
DDRA_MA3

DDRA_MA4
DDRA_MA5
DDRA_MA6
DDRA_MA7

DDRA_MA8
DDRA_MA9
DDRA_MA10
DDRA_MA11

DDRA_MA12
DDRA_MA13
DDRA_MA14 _WE#
DDRA_MA15 _CAS#

DDRA_MA16 _RAS#
DDRA_BG0
DDRA_BS 0#
DDRA_BS 1#

DDRA_AC T#
DDRA_PA R

DDRA_ALE RT#

1

1

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

CD@

CD137

CD136

1 1

CD109 CD110
22P_0402_5 0V8-J 22P_04 02_50V8-J

RF@ R F@

2

1 1

CD157 CD148
22P_0402_5 0V8-J 22P_04 02_50V8-J

RF@ R F@

2

DDRA_MA[0. .13] 5

RD52 1 MD@ 2 34.8_0402 _1%
RD53 1 MD@ 2 34.8_04 02_1%

RD64 1 MD@ 2 34.8_040 2_1%
RD67 1 MD@ 2 34.8_040 2_1%

RD70 1 MD@ 2 34.8_040 2_1%
RD71 1 MD@ 2 34.8_040 2_1%

RD78 1 MD@ 2 34.8_0402_ 1%

1

RD49 1 MD@ 2 36_0402_1%

RD50 1 MD@ 2 36_0402_1%
RD51 1 MD@ 2 34. 8_0402_1%

RD54 1 MD@ 2 34. 8_0402_1%
RD55 1 MD@ 2 34. 8_0402_1%
RD56 1 MD@ 2 34.8_0402_ 1%
RD57 1 MD@ 2 34.8_0402_ 1%

RD58 1 MD@ 2 34. 8_0402_1%
RD59 1 MD@ 2 34. 8_0402_1%
RD60 1 MD@ 2 34.8_0402_ 1%
RD61 1 MD@ 2 34.8_0402_ 1%

RD62 1 MD@ 2 34. 8_0402_1%
RD63 1 MD@ 2 34. 8_0402_1%

RD72 1 MD@ 23 4.8_0402_1%
RD73 1 MD@ 2 34.8_0402_ 1%

RD74 1 MD@ 2 34.8_0402_ 1%
RD75 1 MD@ 2 34. 8_0402_1%
RD76 1 MD@ 2 34.8_0402_ 1%
RD77 1 MD@ 2 34.8_0402_ 1%

RD79 1 MD@ 2 34. 8_0402_1%

RD86 1 MD@ 2 49. 9_0402_1%

1

1

1

MD@

MD@ MD @

2

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

CD@

CD138

CD140

CD139

2

2

+0.6V S

1 1

CD168 CD169

22P_0402_5 0V8-J 22P_04 02_50V8-J

RF@ R F@

2

+0.6V S

+1.2V

1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

CD141

2

SecurrriiitttyClllassiiifffiiicatttion

IIIssued Date 2015///08///20 Deciiiphered Da te 2016///08///20

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THEPROPRIIIETARY PROPERTY OF LC FUTURE CENTER... AND CONTAIIINSCONFIIIDENTIIIAL
AND TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D DEPARTMENT
EXCEPT AS AUTHORIIIZED BY LC FUTURE CENTER NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIITCONTAIIINS

5

4

3

MAYBE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF LC FUTURECENTER.

2

LC Futtture Centtter Secrettt Data

Tiiitttle

DDR4 Memory Down

Siiize Documenttt Number

Custttom

Sunday,,, January 22,,,2017

1

DG42A

Re v

Shee t 17 of 60Dattte:

1.0

5

DDR4 SO-DIMM

+1.2V +1.2V +1.2V +1.2V +1.2V +1.2V +1.2V +1.2V

DDRB_DQ12
DDRB_DQ13
DDRB_DQS#1

DDRB_DQS1

2

1

2

1

RD93
240_0402_1%

DDRB_DQ10
DDRB_DQ14
DDRB_DQ0
DDRB_DQ6

DDRB_DQ7
DDRB_DQ3
DDRB_DQ18
DDRB_DQ16
DDRB_DQS#2

DDRB_DQS2

DDRB_DQ22
DDRB_DQ23
DDRB_DQ27
DDRB_DQ28

DDRB_DQ25
DDRB_DQ30

DDRB_DQS#8
DDRB_DQS8

DDRB_CKE0
DDRB_BG1

DDRB_BG0
DDRB_MA12

DDRB_MA9
DDRB_MA8

DDRB_MA6

1

CD13

0.022U_0201_6.3V6-K

2

12

RD6

24.9_0402_1%

D D

+1.2V

RD92

240_0402_1%

C C

6 DDRB_CKE0
6 DDRB_BG1

6 DDRB_BG0
6 DDRB_MA12

6 DDRB_MA9
6 DDRB_MA8

6 DDRB_MA6

B B

5 DDR_SB_VREFCA

CD117

0.1u_0201_10V6K

RD4 1

2_0402_5%

JDDR1A

1

VSS_1

3

DQ5

5

VSS_3

7

DQ1

9

VSS_5 VSS_6

11

DQS0_C DM0_n/DBIO_n/NC

13

DQS0_t VSS_7

15

VSS_8 DQ6

17

DQ7

19

VSS_10

21

DQ3

23

VSS_12

25

DQ13

27

VSS_14

29

DQ9

31

VSS_16 DQS1_c

33

DM1_n/DBl1_n/NC DQS1_t

35

VSS_17 VSS_18

37

DQ15 DQ14

39

VSS_19

41

DQ10

43

VSS_21

45

DQ21

47

VSS_23

49

DQ17

51

VSS_25 VSS_26

53

DQS2_c DM2_n/DBl2_n/NC

55

DQS2_t VSS_27

57

VSS_28 DQ22

59

DQ23

61

VSS_30

63

DQ19

65

VSS_32

67

DQ29

69

VSS_34

71

DQ25

73

VSS_36 DQS3_c

75

DM3_n/DBl3_n/NC DQS3_t

77

VSS_37 VSS_38

79

DQ30 DQ31

81

VSS_39

83

DQ26

85

VSS_41

87

CB5/NC

89

VSS_43

91

CB1/NC

93

VSS_45 VSS_46

95

DQS8_c DM8_n/DBI8_n/NC

97

DQS8_t VSS_47

99

VSS_48

101

CB2/NC

103

VSS_50

105

CB3/NC

107

VSS_52

109

CKE0

111

VDD_1

113

BG1

115

BG0

117

VDD_3

119

A12

121

A9

123

VDD_5

125

A8

127

A6

129

VDD_7

ARGOS_D4AS0-26001-1P60

ME@

+1.2V

1

1

2

RD3
1K_0402_1%

2

2

1

RD5
1K_0402_1%

2

VSS_2
VSS_4

VSS_9

VSS_11

DQ12

VSS_13

VSS_15

36

VSS_20

DQ11

VSS_22

DQ20

VSS_24

DQ16

VSS_29

DQ18

VSS_31

DQ28

VSS_33

DQ24

VSS_35

78

VSS_40

DQ27
VSS_42
CB4/NC
VSS_44
CB0/NC

98

CB6/NC
VSS_49
CB7/NC
VSS_51

RESET_n

CKE1

VDD_2
ACT_n

ALERT_n

VDD_4

VDD_6

VDD_8

DQ4
DQ0

DQ2

56

A11

4

2
4
6
8
10

12

14

16
18

20
22

24
26

28

DQ8

30
32
34

38
40

42
44

46
48

50
52

54
58

60

62
64

66
68

70

72
74
76

80
82

84

86

88

90

92

94
96

100

102

104

106

108

110
112
114
116
118
120
122

A7

124
126

A5

128

A4

130

Not e:
VREF trace wid th:20 mil s at leas t
Spacin g:20mi ls to other signal/pl anes
Place n ear DIMM scoket

1

CD14

0.1u_0201_10V6K

2

+VREF_CA_DIMM

DDRB_DQ9
DDRB_DQ8

DDRB_DQ11
DDRB_DQ15
DDRB_DQ5
DDRB_DQ4
DDRB_DQS#0

DDRB_DQS0
DDRB_DQ1
DDRB_DQ2
DDRB_DQ20
DDRB_DQ21

DDRB_DQ17
DDRB_DQ19
DDRB_DQ24
DDRB_DQ29
DDRB_DQS#3

DDRB_DQS3
DDRB_DQ26
DDRB_DQ31

CPU_DRAMRST#
DDRB_CKE1

DDRB_ACT#
DDRB_ALERT#

DDRB_MA11
DDRB_MA7

DDRB_MA5
DDRB_MA4

DDRB_CKE1 6
DDRB_ACT# 6

DDRB_ALERT#6
DDRB_MA11 6

DDRB_MA7 6
DDRB_MA5 6

DDRB_MA4 6

DDRB_DQ[0..63]
DDRB_DQS#[0..7]
DDRB_DQS[0..7]

3 2 1

DDRB_DQ[0..63]6

1

CD3

0.1u_0201_10V6K

@

2

+1.2V

DDRB_DQS#[0..7]6
DDRB_DQS[0..7]6

CPU_DRAMRST#6,17

RD1 1 @

+3VS

RD2 1 @ 2

+2.5V_DDR

6 DDRB_MA3
6 DDRB_MA1

6 DDRB_CLK0
6 DDRB_CLK0#

6 DDRB_PAR

6 DDRB_BS1#
6 DDRB_CS0#

6 DDRB_MA14_WE#
6 DDRB_ODT0

6 DDRB_CS1#
6 DDRB_ODT1

7,40 2SMB_CLK_S3

0_0603_5%

2.2U_0402_6.3V6M

0_0603_5%

Layout Note:
Place near DIMM

CD4 CD5

1 1

2

0.1u_0201_10V6K

2

DDRB_MA3
DDRB_MA1

DDRB_CLK0
DDRB_CLK0#

DDRB_PAR

DDRB_BS1#
DDRB_CS0#

DDRB_MA14_W
DDRB_ODT0

DDRB_CS1#

DDRB_ODT1

DDRB_DQ32
DDRB_DQ33
DDRB_DQS#4

DDRB_DQS4
DDRB_DQ39
DDRB_DQ38
DDRB_DQ41
DDRB_DQ40

DDRB_DQ47
DDRB_DQ43
DDRB_DQ53
DDRB_DQ48
DDRB_DQS#6

DDRB_DQS6

DDRB_DQ54
DDRB_DQ50
DDRB_DQ60
DDRB_DQ57

DDRB_DQ59
DDRB_DQ58
SMB_CLK_S3

+VDD_SPD

+VPP

E#

1

2

CD6

1U_0402_6.3V6K

JDDR1B

131

A3

133

A1

135

VDD_9

137

CK0_t

139

CK0_c

141

VDD_11

143

Parity

145

BA1 A10/AP

147

VDD_13 VDD_14

149

CS0_n BA0

151

WE_n/A14 RAS_n/A16

153

VDD_15 VDD_16

155

ODT0 CAS_n/A15

157

CS1_n A13

159

VDD_17 VDD_18
ODT1 C0/CS2_n/NC

161

VDD_19 VREFCA

163

C1/CS3_n/NC SA2

165

VSS_53 VSS_54

167

DQ37 DQ36

169

VSS_55 VSS_56

171

DQ33 DQ32

173

VSS_57 VSS_58

175

DQS4_c DM4_n/DBl4_n/NC

177

DQS4_t VSS_59

179

VSS_60 DQ39

181

DQ38 VSS_61

183

VSS_62 DQ35

185

DQ34 VSS_63
VSS_64 DQ45

187

DQ44 VSS_65

189

VSS_66 DQ41

191

DQ40 VSS_67

193

VSS_68 DQS5_c

195

DM5_n/DBl5_n/NC DQS5_t

197

VSS_69 VSS_70

199

DQ46 DQ47
VSS_71 VSS_72

201

DQ42 DQ43

203

VSS_73 VSS_74

205

DQ52 DQ53

207

VSS_75 VSS_76

209

DQ49 DQ48

211

VSS_77 VSS_78

213

DQS6_c DM6_n/DBl6_n/NC

215

DQS6_t VSS_79
VSS_80 DQ54

217

DQ55 VSS_81

219

VSS_82 DQ50

221

DQ51 VSS_83

223

VSS_84 DQ60

225

DQ61 VSS_85

227

VSS_86 DQ57

229

DQ56 VSS_87

231

VSS_88 DQS7_c
DM7_n/DBl7_n/NC DQS7_t

233

VSS_89 VSS_90

235

DQ62 DQ63

237

VSS_91 VSS_92

239

DQ58 DQ59

241

VSS_93 VSS_94

243

SCL SDA

245

VDDSPD SA0

247

VPP_1 Vtt

249

VPP_2 SA1

251
253

GND_1 GND_2

255
257
259

261

ARGOS_D4AS0-26001-1P60

ME@

@

1

2

1U_0402_6.3V6K

CD7

CD118

A2

EVENT_n

VDD_10

CK1_t

CK1_c

VDD_12

A0

1

1

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

CD8

CD@

+1.2V

12

RD91

240_0402_1%

@

132
134
136
138
140
142
144

146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
210
212
214
216
218
220
222
224
226
228
230
232
234
236
238
240
242
244
246
248
250
252
254
256
258
260

262

+2.5V_DDR+0.6VS

CD@

DDRB_MA2
DDRB_EVENT#

DDRB_CLK1
DDRB_CLK1#

DDRB_MA0

DDRB_MA10
DDRB_BS0#

DDRB_MA16_RAS#
DDRB_MA15_CAS#

DDRB_MA13

+VREF_CA_DIMM
DDRB_SA2

DDRB_DQ36
DDRB_DQ37

DDRB_DQ34
DDRB_DQ35
DDRB_DQ45
DDRB_DQ44
DDRB_DQS#5

DDRB_DQS5
DDRB_DQ46
DDRB_DQ42
DDRB_DQ52
DDRB_DQ49

DDRB_DQ55
DDRB_DQ51
DDRB_DQ56
DDRB_DQ61
DDRB_DQS#7

DDRB_DQS7

DDRB_DQ62
DDRB_DQ63
SMB_DATA_S3

DDRB_SA0

DDRB_SA1

1

2

CD9

1 1

1

2 2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

CD10

CD11

CD@

1U_0402_6.3V6K

SMB_DATA_S3 7,40

+0.6VS

1U_0402_6.3V6K

CD12

DDRB_MA2 6

DDRB_CLK1 6
DDRB_CLK1# 6

DDRB_MA0 6

DDRB_MA10 6
DDRB_BS0# 6

DDRB_MA16_RAS# 6
DDRB_MA15_CAS# 6

DDRB_MA13 6

@

1

2

0.1u_0201_10V6K

CD2

CD1

1

2

2.2U_0402_6.3V6M

1

1

1

2

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

CD21

CD20

CD19

+3VS +3VS +3VS

1

RD7
0_0402_5%

@

2

A A

DDRB_SA0 DDRB_SA1 DDRB_SA2

1

RD10
0_0402_5%

@

2

1

2

1

2

RD8
0_0402_5%

@

RD11
0_0402_5%

@

2

2

1

RD9
0_0402_5%

@

1

RD12
0_0402_5%

@

SPD Address = 2H

5

4

CD@

+1.2V

1

1

EMC_NS@

2

CD15

1

2

2

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

CD16 EMC_NS@

CD17 EMC_NS@

For EMC

Securiiity Clllassiiifiiicatiiion

Issued Date

THIS SHEET OF ENGINEERING DRAWING IIIS THE PROPRIETARY PROPER TY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIIIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMP ETENT DIVIIISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEIIITHER THIS SHEET NOR THE INFORMATION IIIT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WIIITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

3 2

1

1

2

10U_0603_6.3V6M

CD22

1

2

0.1u_0201_10V6K
CD18 EMC_NS@

1

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

CD23

CD24

CD@

RF@

1

2

33P_0402_50V8J

0.1u_0201_10V6K
CD36

Near JDDRL1

2015/08/20 Deciphered Date

1

1

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

RF@

1

2

CD37

10U_0603_6.3V6M

CD25

CD26

33P_0402_50V8J

LC Future Center Secret Data

1

1

2

1U_0402_6.3V6K

CD31

Title

DDR4SO-DIMM

Siiize Document Number

Custom

Date:

1

2

1U_0402_6.3V6K

CD32

Sunday,,, Jan uary 22,,,2017

1

2

CD27

1

1

2

1U_0402_6.3V6K

CD28

1

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

CD29

CD30

CD@

2016/08/20

1

2

2

1U_0402_6.3V6K

CD33

CD@

CD34

DG42A

1U_0402_6.3V6K

Sheet 18 of 60

1

Rev

1.0

1U_0402_6.3V6K

5

4

3

2

1

+3VALW

RA213 1 @ 2 0_ 0402_5%

+3VS

RA216 1@

D D

Analog power for mixers, & IO ports

+5VS +5VA +5VS

RA7 1 @ 2 0_ 0603_5%

+3VALW

+3VS +3VS_CARD

1U_0402 _6.3V6K

1
@

C2062

C C

2

+3VL

To solve the background noise while combojack connecting to an
active speaker and system entry into S3/S4/S5 without analog power.

8 HDA_RS T_AUDIO#

B B

GND

Digital power for HDA link

2

0_0402_5 %

0.1U_0 201_6.3V6-K

1U_0402 _6.3V6K

2 2

CA42 CA20

1 1

Power for card reader controller

RA2031 @ 20_0402 _5%

RA217 1 @ 2 0 _0402_5%

2

1

0_0402_ 5%

RA1

EMC_NS @

RA4 1 2 0_0402_5%

EMC_NS @

RA9 1 @ 2 0_040 2_5%

1

EMC_NS @

2

0_0402_ 5%

RA12

Power supply for full-bri dge left/Right channel

EMC_NS @

1 2

LA25
RA10 1 @ 2 0_0 603_5%

1

@ 20_0402 _5%

RA220

RA219 1 @ 2 0 _0402_5%

Power for combo jack dep op circuit at system

shutdo wn mod e

VDD_STB

GNDA

DVDD_IO

2

1

Close t o Pin7

BLM15 PD600SN1D_2P

CA178

1

2

@1 TC203

CA2

0.1U_0 201_6.3V6-K

+5VD

10U_0805_10V6K

CA18 0. 1U_0201_6.3 V6-K

2

1

+1.8VS +1.8V _AUDIO

RA2251@20_0402_5 %

.8VAL W

+1

RA226

CA19 0. 1U_0201_6.3 V6-K

2

1

MICBIAS B 1

LW 2

USB20_ N5 USB20 _N5_R

1 2

USB20_P5

4

EXC24C H900U_4P

FOR EMI

EMC_NS @

2

1

0_0402_ 5%

@

33 DMIC_DA TA

33 DMIC_CL K
8 HDA _SDOUT_AU DIO
8 HD A_BITCLK_ AUDIO

8 HDA _SDIN0

8 HD A_SYNC_A UDIO

RING2_CONN
RING3_CONN

1

2

2.2K_0 402_5%

RA38

RA37 2 2. 2K_0402_5% 4.7U_0 603_6.3V6K 2 1 CA 4

31 SD_CM D_R
31 SD_D3_R
31 SD_D2_R

44 EC_M UTE#

44 BEEP#

8 PCH_ BEEP

1 2

4 3

3

9 U SB20_N5
9 USB20_P5

+3VS_ CARD

USB20_ P5_R

+3VS

8/29 Add

+1.8VS Ci rcuit for Audio wei

DMIC_DA TA

RA19 1 @ 2 0_0402 _5%

DMIC _CLK

HDA_SD IN0

RA16

PLUG_IN

SD_C MD_R
SD_D3_ R
SD_D 2_R

USB20 _N5

RW 12 1 @ 2 0 _0402_5%

USB20 _P5

RW 13 1 @ 20_0402 _5%

1

CW18

4.7U_0402_6. 3V6M

2

DA1

2

PC_BE EP1

1

3

LBAT54C WT1G_ SOT323-3

DMIC_DA TA_R

RA18 1 @ 2 0_0402_ 5%

CA1 1 2 2. 2U_0402_6. 3V6M

1

RA205
RA204 1

CA41

CW 1
CW 2

RW11 1 2 6. 2K_0402_1% RRE F

RA35 1 @ 20_0402_5 %

DMIC_CL K_R

2 33_0402_5 %

DVDD_IO

1

2

100K_ 0402_1%

2 2 00K_0402_1% JSENSE

1 2

2.2U_0 402_6.3V6M

2

1

1U_0402 _6.3V6K

1

2

1U_0402 _6.3V6K

CARD_3 V3

1

CW19

0.1u_0 201_10V6K

2

DA4

1 2

@

LRB751 V-40T1G_SOD 323-2

1 @ 2

RA211

0_0402_ 5%

2

CA183

1 1

220P_ 0201_25V7-K

CD@ C D@ C D@ CD@

SDATA_ IN

CA184

220P_ 0201_25V7-K

UA1

1

HD-GPIO0/D MIC-DA TA

SPKR_ MUTE#EC_MUTE #

RA43
10K_0 402_5%

2

1

CA40 1

2

0.1U_0 201_6.3V6-K

RA14
10K_0 402_5%

2

1

RA223 CD@ 1 5_0402_5%
RA224 CD@ 1 5_0402_5%
RA32 CD@ 1 5_0402_5%

2

2

CA29

CA30

1 1

220P_ 0201_25V7-K

220P_ 0201_25V7-K

2

HD-BC LK

5

HD-LD O3-CA P

6

HD-SDATA- IN

7

HD-SYNC

9

HD-PC BEEP

10

HD-JD1(H P/LINE1)

11

HD-MIC2-L (RING)

12

HD-MIC2-R( SLEEVE )

13

HD-3V5V- STB

14

HD-MIC2-CA P

15

HD-LINE1- R

16

HD-LINE1- L

17
18 HD-L INE2-R
19 HD-L INE2-L
20 CR-SD-C MD

CR-SD-DAT[3]

21

CR-SD-DAT[2]

22

CR-SD REG

23

CR-TEST1

24

CR-V18-C AP

25

CR-RREF

26

CR-DM

27

CR-DP

28

CR-3V3-IN

29

CR-SD-3 V3

RTS5199 -CG_QFN56 _7X7

PC_BE EP

1 2
1
1
1

HDA_SD OUT_AUDIO 3HD-GPIO1/D MIC-CLK
HDA_BITC LK_AUDIO 4HD-SDATA- OUT

HDA_SY NC_AUDIO 8HD-DVDD-IO

PC_BEEP

VDD_STB
LINE1_R

LINE1_L

USB20 _N5_R
USB20_ P5_R

2

30

CR-GPIO 31SD_CD#

CR-SD-CD

32

CR-SD-WP

33

CR-SD-DAT[1]

34

CR-SD-DAT[0]

35

CR-SD-CLK

36

HD-AVDD1 37LDO1_C AP

HD-LD O1-CA P

38

HD-VR EF

HD-MIC2-V REFO 40LINE1_V REF_L

HD-LINE1- VREFO-L

39

41

HD-HPOUT-L

42

HD-HPOUT-R

43

HD-CP VEE

44

HD-CB N

45

HD-CP VDD

46

HD-CBP

47

HD-LD O2-CA P

48

HD-AVDD2

49

HD-PVDD1

50

HD-SPKOU T-LP

51

HD-SPKOU T-LN

52

HD-SPKOU T-RN53SPK_R +
HD-SPKOU T-RP

54

HD-PVDD2 55SPKR_ MUTE#

HD-PDB

56

HD-DVDD

57

GNDP AD

LINE1_L

LINE1_V REF_L

HPOUT_L
HPOUT_R

LINE1_V REF_L

LINE1_R

SD_ WP
SD_D1_ R
SD_D0_ R
SD_CLK _R

+5VA

MICBIAS B
HPOUT_L

HPOUT_R

HD_LDO2

+5VD
SPK_L +

SPK_L -

SPK_R -

+5VD

CA45 1 2 1 U_0402_6. 3V6K

1

RA41

1

RA42

CA46 1

2 1U_ 0402_6.3V6K

CA43 1 2 2 .2U_0402 _6.3V6M

1

CA44

2

1

CA47

CC1671 2 10U _0402_6.3V6 M

2 4 .7K_0402_ 5%

2 4 .7K_0402_ 5%

SD_CD# 31
SD_ WP 31
SD_D1_ R 31
SD_D0_ R 31
SD_CLK _R 31

2

1U_0402_ 6.3V6K

1U_040 2_6.3V6K

+1.8V _AUDIO

Analog power for DACs, A DCs

+3VS

Digital power for digital I/O circuit

2 2

1U_0402 _6.3V6K

0.1U_0 201_6.3V6-K
CA180 CA 179

1 1

RA21 1 2 51_0402 _1%

2 51_0402_1 %

RA20 1

CA48 1 2 1U_04 02_6.3V6K

@

10U_040 2_6.3V6M

A_HP_ OUTL_R
A_HP_OUTR_R

+1.8V _AUDIO

CC257

2

1

11/8 SIT Vendor suggestion form 47 ohm change to 51om wei

SPK_R+
SPK_R -

2

SPK_L +

2

SPK_L -

2

15_0402 _5%RA33 CD@

1 2

RA222 @ 0_040 2_5%
RA221 @ 0_040 2_5%

1 2

RA30 @ 0_0402_5%

1 2

RA34 @ 0_0402_5%

1 2

11/8 SIT Cost down to 0ohm wei

SPK_R+_CONN
SPK_R -_CONN
SPK_L +_CONN
SPK_L -_CONN

CA31

1 1 1 1

EMC@

2 2 2 2

470P_ 0201_50V7-K

470P_ 0201_50V7-K

470P_ 0201_50V7-K

CA32 E MC@

CA181 EM C@

JSPK1 ME @

1

1

2

2

3

3

4

4

5

470P_ 0201_50V7-K

GND1

6

CA182 EM C@

GND2

ACES_ 88231-04001

8/16 Update Audio Jack P/N SP011509163 wei

Audio Jack

RING2_CO NN

R3124 1

@ 2 C232 1 2

RING3_CONN
RING2_CONN
A_HP_OUTL_R
A_HP_ OUTR_R
PLUG_IN

AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2

1

1

1

C185

EMC_NS @

A A

2

DA5

EMC_NS @

2 1

47P_0 201_25V8-J

2 1

2

2

AZ5123-01F.R7GR_DFN1006P2X2

1

1

DA6

DA7

EMC_NS @

EMC_NS @

2 1

2 1

2

2

AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2

1

DA9

DA8

EMC_NS @

EMC_NS @

2 1

2

1

CA38

2 2

EMC_NS @

100P_0201_25V8J

CA39

DMIC _CLK

DMIC _DATA

1

EMC_NS @

100P_0201_25V8J

CA23

1

2

EMC_NS @

22P_0 201_258J

1

RA27

EMC@

CA24

CA25

1

1

EMC @

2

2

EMC_NS @

22P_0 201_258J

33P_0 201_50V8-J

33P_0 201_50V8-J

2

CA26

1

2

EMC_NS @

27_040 2_5%

HDA_SY NC_AUDIO
HDA_S DOUT_AUDIO

HDA_BITCLK _AUDIO

HDA_SD IN0

For EMI

0_0402_ 5% @ 470 P_0201_50V7-K

2

1 2

1

C184

@

R3123

0_0402_ 5% @ 470 P_0201_50V7-K

A_HP_OUTL_R
PLUG_IN

A_HP_ OUTR_R
RING3_CO NN

1

1

C183

C182

EMC@

EMC@

2

2

100P_ 0201_25V8J

100P_ 0201_25V8J

JHP1

3

G/M

1

L

5

5

6

6

2

R

4

M/G

7

MS

SINGA_2 SJ3095-14 0111F

ME@

8/16 Update Audio Jack P/N DC021608101 w ei

Security Clllassiiifiiication

Issued Date

THISII SHEE T OF ENGINEEII RINGII DRAWINGII ISII THE PROPRIEII TARY PROP ERTY OF LC FUTUR E CENTER... AND CONTAINSII CONFIDEII NTIAL
AND TRADE SE CRET INFOII RMATION... THISII SHEET MAY NOT BE TRANS FERED F ROM THE C USTOD Y OF THE C OMPE TENT DIVISIIII IOII N OF R&D
DEPARTMENT EX CEPT AS AUTHORIZII ED BY LC FUT URE CE NTER NE ITHER THISII SHEET NOR THE INFOII RMATION IT CONTAINSII

5

4

MAY BE USED BY OR DISII CLOSED TO ANY THIRDII PARTY WI THOUT PRIOII R WRITTEN CONSE NT OF LC F UTURE CE NTER.

3

2015/08/20 Deciphered Date

LC Future Center Secret Data

2

2016/08/20

Title

Codec &CR_RTS5199

Size DocumentttNum ber

C

Dattte: Sheet of

DG42A

Sunday, ,, Ja nua ry 22,,, 2017

1

30 60

R ev

1.0

5

D D

4

3 2 1

CARD_3V3

SD / MMC

CW 9

@

CARD_3V3

0.1u_0201_10V6K

1

1

2

2

FOR ESD

1

CW 17

2

SD_D3
SD_CMD

SD_CLK
SD_D0

SD_D1
SD_D2

SD_CD#
SD_WP

JREAD1

1

CD/DAT 3

2

CMD

3
4 VSS1

5 VDD

CLK

6
7 VSS2

8 DAT0

DAT1

9

DAT2

10

CARDDETECT

11

WRITEPROTECT

T-SOL_5-251301001000-6_NR

ME@

SH1
SH2
SH3
SH4

12
13
14
15

8/16 Update Conn. P/N SP07000WG00 wei

DW 1

AZ5123-01F.R7GR_DFN1006P2X2

EMC_NS@

30 SD_D0_R

30 SD_D1_R

C C

B B

30 SD_D2_R

30 SD_D3_R

30 SD_CMD_R

30 SD_CLK_R

SD_D0_R

SD_D1_R

SD_D2_R

SD_D3_R

RW3 1 @ 2 0_0402_5%

RW4 1 @ 2 0_0402_5%

RW5 1 @ 2 0_0402_5%

RW6 1 @ 2 0_0402_5%

RW7 1 @ 2 0_0402_5%

RW8 1 @ 2 0_0402_5%

CW5 1

CW6 1

CW7 1

CW8 1

CW111

CW121

2 5.6P_0402_50V8-D

EMC@

2 5.6P_0402_50V8-D

EMC@

2 5.6P_0402_50V8-D

EMC@

2 5.6P_0402_50V8-D

EMC@

2 5.6P_0402_50V8-D

EMC@

2 5.6P_0402_50V8-D

EMC@

SD_D0

SD_D1

SD_D2

SD_D3

SD_CMDSD_CMD_R

SD_CLKSD_CLK_R

1

2

4.7U_0402_6.3V6M

Close to Connector

30 SD_CD#
30 SD _WP

Close to Connector

A A

Security Classification

IssuedDate

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENT ER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/08/20 Deciphered Date

3 2

LC Future Center SecretData

2016/08/20

Title

Cardreader

Siiize Document Number

Custom

Date: Sheet

Sund ay, January 22,2017

DG42A

1

31 of 60

R ev

1.0

5

4

3 2 1

D D

RTPM1 1 TPM@ 20_0603_5%

1

CTPM4

0.1u_0201_10V6K

TPM@

2

1

CTPM1

10U_0603_6.3V6M

2

TPM@

+3VS_TPM+3VS

1A

1

CTPM3

0.1u_0201_10V6K

TPM@

2

TPM

UTPM1

1 24

NC_1

2

C

RTPM12 1 TPM@2

0_0402_5%

Reserve for Nationz TPM

+3VALW

RTPM11 1

TPM@ 2

0_0603_5%

Add for Nuvoton TPM

B B

NC_2

3

NC_3

7

PP LPCPD#

6

NC_4

9

NC_7

4

GND_1

11

GND_2

18

GND_3

5

NC_5

8

NC_6

12

NC_8

13

NC_9

14

NC_10

Z32H320TC-LPC-T28-LT1_TSSOP28

TPM@

VDD3
VDD1

SERIRQ

LAD0
LAD1

LFRAME#

LAD2
LAD3

GND_4

LCLK

VDD2

CLK_RUN#

LRESET#

10

28

SERIRQ_TPM

27

LPC_AD0_TPM

26

LPC_AD1_TPM

23

LPC_FRAME#_TPM

22

LPC_AD2_TPM

20

LPC_AD3_TPM

17
25

21

19

TPM_CLKRUN#

15
16

RTPM2 1 TPM@ 2 4.7K_0402_5%

RTPM5 1 TPM@ 2 0_0402_5%
RTPM6 1 TPM@

RTPM7 1 TPM@2 0_0402_5%

RTPM8 1 TPM@

RTPM9 1 TPM@2 0_0402_5%

RTPM10 1 TPM@

PLT_RST# 11,20,37,40,44

+3VS_TPM

Reserve for Nationz TPM

2 0_0402_5%
2 0_0402_5%
2 0_0402_5%

1

RTPM13

@

0_0402_5%

Reserve for Nuvoton TPM

1

RTPM4
0_0402_5%

TPM@

2

SERIRQ 7,44

LPC_AD0 7,44

LPC_AD1 7,44

LPC_FRAME# 7,44

LPC_AD2 7,44

LPC_AD3 7,44

CLK_PCI_TPM7

2

+3VS_TPM

PM_CLKRUN# 7

Nationz TPM Nuvoton TPM

RTPM 2 Stuf f NC

RTPM 12 Stu ff NC

RTPM 11 NC Stuf f

C

A A

Security Classification

Issued Date

THISII SHEET OF ENGINII EERINII G DRAW INII G ISII THEPROPRIETARYII PROPERTY OF LC FUTURE CENTER. AND CONTAINII S
CONFIDII ENTIALII
AND TRADE SECRET INII FORMATIOII N. THISII SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISIOIIIIII N OF R&D
DEPARTMENT EXCEPT AS AUTHORIZII ED BY LC FUTURE CENTER NEITII HER THISII SHEET NOR THE INII FORMATIOII N ITIICONTAINSII

5

4

MAY BE USED BY OR DISCLII OSED TO ANY THIRDII PARTY WITII HOUT PRIOII R WRITTII EN CONSENT OF LC FUTURE CENTER.

3 2

2015/08/20 Deciphered Date

LC Future Center SecretData

2016/08/20

Title

TPM

Siiize Document Number

Custom

Date:

Sunday, J anuary 22, 2017

DG42A

Sheet 32 of 60

1

R ev

1.0

5

+3VS

1

C1

0.1u_0201_10V6K

D D

PCH_ENVDD

2

U5 EN PIN VIH MIN 1.5V

V20B+ +LEDVDD

2A 80 mil

LCD POWER CIRCUIT

U5

5

4

EN

SY6288C20AAC_SOT23-5

R17

OUT

IN

GND
OCB

1 @ 2 0_0805_5%

1
2
3

+LCDVDD

R263 1 @ 2

0_0805_5%

2A 80 mil

1

2

C14 CD@

4.7U_0805_25V6-K

4

+LCDVDD_CON

W=60mils

@

1

2

4.7U_0402_6.3V6M

C121

RF_NS@

1

1

2

2

33P_0402_50V8J

0.1u_0201_10V6K

C122

C123

For RF

1

2

C15 EMC@

0.1U_0201_25V6-K

3 2 1

Need short

CMOS Camera

CMOS_ON#

0.01U_0201_25V6-K

EMC_NS@

ForEMI
Close to R5

0.1u_0201_10V6K

R5 1

@

100K_0402_5%

1

C9

2

+3VS +3VS_CMOS_R

LP2301ALT1G_SOT23-3
Q7 3 1 @

1

2

1

C10

0.1u_0201_10V6K

@

2

JUMP_43X39

W=40 mils

2

C5

@

J1 @

1

S

2

1 2

D

@

1

G

2

1

C3

0.1u_0201_10V6K

CD@

2

2

C6

0.01U_0201_10V6K

R3 1 @ 2

0_0603_5%

+3VS_CMOS

W=40mils

1

C4
10U_0603_6.3V6M

@

2

EMI Request

R1

1 @ 2

0_0402_5%

1

2

0_0402_5%R12 1 @ 2

PCH_ENVDD

+3VS

+3VS

2

R10

4.7K_0402_5%

@

1

DISPOFF#

ENBKL

1

R16
100K_0402_5%

2

2

R18
1K_0402_5%

@

1

R20
100K_0402_5%

2

1

INVT_PWM

ENBKL 44

8 PCH_CMOS_ON#

44 EC_CMOS_ON#

DMIC_CLK

R9 R8

100K_0402_1% 100K_0402_1%

@ @

R15 R13

100K_0402_1% 100K_0402_1%

@ @

1 2

R296 0_0402_5%@

R297 1 @ 2 0_0402_5%

EMI request

1

EMC@

2

C11

100P_0201_25V8J

4 PCH_ENVDD

100K_0402_5%

C C

PCH_ENBKL

R11

44 BKOFF#

4 PCH_ENBKL

4 PCH_EDP_PWM

B B

R14 1 @ 2 0_0402_5%

R19 1 @ 2 0_0402_5%

1

2

1

2

DISPOFF#

+3VS

4 CPU_EDP_TX0+

1

2

EDP_AUX
EDP_AUX#

1

2

EMC_NS@ C22

680P_0402_50V7K

CMOS_ON#

INVT_PWM

1

2

EMC_NS@

C12

470P_0201_50V7-K

1

2

EMC_NS@

C13

470P_0201_50V7-K

4 CPU_EDP_TX0­4 CPU_EDP_TX1+

4 CPU_EDP_TX1-

4 CPU_EDP_AUX
4 CPU_EDP_AUX#

+3VS

R21 1

@

0_0402_5%

1

2

CPU_EDP_TX0+
CPU_EDP_TX0-

CPU_EDP_TX1+
CPU_EDP_TX1-

CPU_EDP_AUX
CPU_EDP_AUX#

4 CPU_EDP_HPD

2

W=60mils

30 DMIC_DATA

30 DMIC_CLK

9 USB20_P8
9 USB20_N8

USB20_N8

USB20_P8 USB20_P8_R

+LEDVDD

C19 1 2 0.1u_0201_10V6K

2

1

C16 0.1u_0201_10V6K
C17 1 2 0.1u_0201_10V6K

2

1

C18 0.1u_0201_10V6K
C20 1 2 0.1u_0201_10V6K

2

1

C21 0.1u_0201_10V6K

+LCDVDD_CON

+3VS

1 2

R182 @
R183 1 @

+3VS_CMOS

.047U_0201_6.3V6K

EMC_NS@

EMI request

L12 EMC_NS@

1

1 2

4

4 3

EXC24CH900U_4P

C24

2

3

0_0402_5%

2

0_0402_5%

W=40mils

1

2

USB20_N8_R

EDP_TX0+
EDP_TX0-

EDP_TX1+
EDP_TX1-

EDP_AUX
EDP_AUX#

DISPOFF#
INVT_PWM

USB20_P8_R
USB20_N8_R

For EMI

JEDP1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

27

28

28

29

29

30

30

31

G1

32

G2

DRAPH_FC5AF301-3181H

ME@

Touch Screen

USB20_P6_CONN

USB20_P6

USB20_N6

A A

L15

1

1

4

4

EXC24CH900U_4P

EMC_NS@

For EMI

USB20_P6_CONN

2

2

USB20_N6_CONN

3

3

5

USB20_N6_CONN

+5VS_TS

1

D2

2 1

AZ5725-01F.R7GR_DFN1006P2X2

2

EMC_NS@

For ESD

3

2

D1
AZC199-02S.R7G_SOT23-3

EMC_NS@

1

4

Touch Screen

+5VS_TS+5VS

R26 1 @ 2 0_0402_5%

Securiiity Clllassiiifiiicatiiion

Issued Date

THISII SHEET OF ENGINII EERINII G DRAWINII G ISII THE PROPRIETARII Y PROPERTY OF L C FUTURE CENTER... AND CONTAINII S CONFIDII ENTIALII
AND TRADE SECRE T INII FORMATIONII ... TH ISII SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISIONIIIIIIOF R&D
DEPARTMENT EXCEPT AS AUTHORIZII ED BY LC FUTURE CENTER NEITII HER THISII SHEET NOR THE INII FORMATIONII ITII CONTAINSII
MAY BE USED BY OR DISCII LOSED TO ANY THIRDII PARTY WITII HOUT PRIORII WRITTII EN CONSENT OF LC FUTURE CENTER.

3 2

2015/08/20 Deciphii ered Date

1

C25

0.1u_0201_10V6K

TS@

2

LC Future Center Secret Data

44 EC_TS_ON

9 USB20_N6
9 USB20_P6

R28 1 @ 2 0_0402_5%
R23 1 @

R24 1 @

2016/08/20

2

0_0402_5%

2

0_0402_5%

JTS1 ME@

1

1

2

TS_RS
USB20_N6_CONN

USB20_P6_CONN

2 GND1

3

3

4

4 GND2

5

5

6

6

CVILU_CI1806M2HR0-NH

Tit le

eDP/CMOS/Touch screen

Siiize Document Number

Custom

Date: Sheet

DG42A

Sun day, Jan uary 22, 2017

7
8

enen

R ev

33 of 60

1

1.0

5

4

3 2 1

HDMI_CLK-_C

HDMI_CLK+_C HDMI_CLK+_CON

D D

HDMI_TX0-_C

HDMI_TX0+_C

HDMI_TX1-_C HDMI_TX1-_CON

HDMI_TX1+_C

HDMI_TX2-_C

HDMI_TX2+_C

L2 EMC@

1

1

4

4 3

EXC24CH900U_4P

L3

1

1

4

4 3

EXC24CH900U_4P

L4

1

1

4

4 3

EXC24CH900U_4P

L5

1

1

4

4 3

EXC24CH900U_4P

EMC@

EMC@

EMC@

HDMI_CLK-_CON

2

2

3

HDMI_TX0-_CON

2

2

HDMI_TX0+_CON

3

2

2

HDMI_TX1+_CON

3

HDMI_TX2-_CON

2

2

HDMI_TX2+_CON

3

For EMC

C C

B B

HDMI_CLK-_C
HDMI_CLK+_C
HDMI_TX0-_C
HDMI_TX0+_C
HDMI_TX1-_C
HDMI_TX1+_C

HDMI_TX2-_C
HDMI_TX2+_C

R29 1 2 470_0402_5%
R30 1 2 470_0402_5%

R31 1 2 470_0402_5%
R32 1 2 470_0402_5%
R33 1 2 470_0402_5%
R34 1 2 470_0402_5%
R37 1 2 470_0402_5%
R38 1 2 470_0402_5%

+3VS

2

G

R42 1 @ 2

100K_0402_5%

1 2

C26

1 2

C27

1 2

C28

1 2

C29

1 2

C30

1 2

C31

1 2

C32

1 2

C33

13

D

Q13

2N7002KW_SOT 323-3

S

EMC_NS@

3.3P_0402_5 0V8-C

EMC_NS@

3.3P_0402_5 0V8-C

EMC_NS@

3.3P_0402_5 0V8-C

EMC_NS@

3.3P_0402_5 0V8-C

EMC_NS@

3.3P_0402_5 0V8-C

EMC_NS@

3.3P_0402_5 0V8-C

EMC_NS@

3.3P_0402_5 0V8-C

EMC_NS@

3.3P_0402_5 0V8-C

4 HDMI_HPD

4 DDPB_CLK

4 DDPB_DATA

1M_0402_5%

4 HDMI_TX0+
4 HDMI_TX0­4 HDMI_TX1+
4 HDMI_TX1­4 HDMI_TX2+
4 HDMI_TX2-

4 HDMI_CLK+

4 HDMI_CLK-

+3VS

5

G

Q1B

HDMICLK_R

S

4 3

D

2N7002KDWH_SO T363-6

2

G

Q1A

S

1 6

2N7002KDWH_SO T363-6

+3VS

2

R35

2

Q12

1

3 1

DG S

2N7002KW_SOT 323-3

HDMI_TX0+

C38 2

HDMI_TX0-

C37 2

HDMI_TX1+

C40 2

HDMI_TX1-

C39 2

HDMI_TX2+

C42 2

HDMI_TX2-

C41 2

HDMI_CLK+ HDMI_CLK+_C HDMI_CLK+_CON

C36 2

HDMI_CLK-

C35 2

D

+5VS

D4

3

BAT54S-7-F_SOT23-3

1

D4

R41
20K_0402_5%

1

2

1 0.1u_0201_ 10V6K
1 0.1u_0201_ 10V6K HDMI_TX0-_C R452
1 0.1u_0201_ 10V6K HDMI_TX1+_C R482
1 0.1u_0201_ 10V6K HDMI_TX1-_C R472
1 0.1u_0201_ 10V6K HDMI_TX2+_C R502
1 0.1u_0201_ 10V6K HDMI_TX2-_C R492

1 0.1u_0201_10V6K
1 0.1u_0201_10V6K

2

@

HDMI_DET

HDMI_TX0+_C

HDMI_CLK-_C

HDMIDAT_R

R46 2

R44 2 @

@
@
@
@
@
@

@

46 SUSP

1 0_0402_5%
1 0_0402_5%
1 0_0402_5%
1 0_0402_5%
1 0_0402_5%
1 0_0402_5%

1 0_0402_5%
1 0_0402_5%R43 2

+5VS

+5VS_HDMI

HDMI_TX0+_CON
HDMI_TX0-_CON
HDMI_TX1+_CON
HDMI_TX1-_CON
HDMI_TX2+_CON
HDMI_TX2-_CON

HDMI_CLK-_CON

HDMI_DET
HDMIDAT_R

HDMICLK_R
+5VS_HDMI

For EMC

D5

2

@

3

RB491D_SOT23-3

LP2301ALT1G_ SOT23-3

1 3 Q22

D

S

G

2

JHDMI1

18

+5V_Power

7

TMDS_Data0+

9

TMDS_Data0-

4

TMDS_Data1+

6

TMDS_Data1-

1

TMDS_Data2+

3

TMDS_Data2-

8

TMDS_Data0_Sh ield

5

TMDS_Data1_Sh ield

2

TMDS_Data2_Shield

11

TMDS_Clock_Shield

10

TMDS_Clock+

12

TMDS_Clock-

ALLTO_C128S9- K1935-L

D3

1

1

2

2

4

4

5

5

3

3

8

AZ1045-04F_DFN2 510P10E-10-9

EMC_NS@

1

1 2

0.5A_6V_1206L050YRHF

DDC/CEC_ Ground

F1

0.1u_0201_1 0V6K

ME@

Hot_Plug_Detect

Utili ty

GND1
GND2
GND3
GND4

SDA

SCL

CEC

10

HDMIDAT_R

8

9

HDMICLK_R

7

7

+5VS_HDMI

6

6

+5VS_HDMI+5VS_HDMI_F

1

C34

2

HDMICLK_R

15

HDMIDAT_R

16

13
17

HDMI_DET

19

14

20
21
22
23

2

1

RP1

2.2K_0404_4P2R_5%

4

3

HDMI_DET

9

8/16 Update HDMIConn. P/N DC021608081wei

Close to JHDMI1

D6

1

HDMI_CLK-_CON HDMI_CLK-_CON

A A

1

2

2

4

4

5

5

3

3

8

AZ1045-04F_DFN2 510P10E-10-9

EMC_NS@

HDMI_CLK+_CONHDMI_CLK+_CON

9

10

8

9

HDMI_TX0+_CONHDMI_TX0+_CON

7

7

6

6

For EMC

HDMI_TX1-_CON
HDMI_TX1+_CON
HDMI_TX2-_CON

HDMI_TX2+_CONHDMI_TX0-_CON HDMI_TX0-_CON

D7

1

1

2

2

4

4

5

5

3

3

8

AZ1045-04F_DFN2 510P10E-10-9

EMC_NS@

9

10

8

9

7

7

6

6

HDMI_TX1-_CON
HDMI_TX1+_CON
HDMI_TX2-_CON

HDMI_TX2+_CON

Security Classification LC Future Center Secret Data

Issued Date

THIIIS SHEET OF ENGIIINEERING DRAWIIING IIIS THE PROPRIE TARY PR OPERTY OF LC FUTURE C ENTER. A ND CONTAIIINS CONFIDENTIIIAL
AND TRAD E SEC RET IIINFORMATIIION... THIIIS SHEE T MAY NOT BE TRAN SFERED FROM THE CUSTOD Y OF THE COMP ETENT DIVIIISIIION OF R& D
DEPAR TMENT EXCE PT AS AUTHORIZE D BY L C FUTURE CENTER NEIIITHER THIIIS SHEET N OR THE IIINFORMATIIION IIIT CONTAIIINS
MAY BE USED BY OR DISCLO SED TO A NY THIRD PARTY WIIITHOUT PRIO R WR ITTEN CONSEN T OF LC FUTU RE CE NTER.

5

4

3 2

2015/08/20 DecipheredDate

2016/08/20

Title

HDMI_CONN

Siiize Document Number

Custom

DG42A

R ev

Sheet 34 of 60Date: Su nd ay , J an ua ry 22, 2017

1

1.0

5

4

3 2 1

+3VALW TO +3VALW_LAN

+3VALW_LAN rising t i me ( 10 %~90 %):

+3VALW +3VALW_LAN

D D

44 LAN_PWR_ON#

11,40,44

PCIE_WAKE#

40,44

C C

LAN_WAKE#

+3VS

1

2

ISOLATE#

1

2

RL9
1K_0402_1%

RL11
15K_0402_5%

@

RL2

100K_0402_5%

RL10 1@

+3VALW

@

0_0402_5%

1

2

RL3 1@ 2

LAN_PWR_ON#

2

47K_0402_5%

RL7 1 @ 2 0_0402_5%
RL6 1 @ 2 0_0402_5%

0.1u_0201_10V6K

CL8

1

2

@

Need short

JL1 1

2 @ JUMP_43X79

1 2

LP2301ALT1G_SOT23-3

S

Q14 3 1 @

G

2

+3VALW_LAN

2

RL5
10K_0402_5%

@

1

PCIE_WAKE#_R

11,20,32,40,44 PLT_RST#

9 PCIE_PRX_DTX_N5
9 PCIE_PRX_DTX_P5

D

CL9

@

LAN_PWR_ON#

0.5ms＜s pec＜ 10 0m s

width : 40 mils

CL4

1

2

0.01U_0201_10V6K

Close to Pin11 Close t o Pin32 Close to Pin11

CL5

1

2

@

1

2

@

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

manual change the Codec PN to RTL8111GUL-CG

+3VALW_LAN

2

TL3 @1

PCIE_PRX_C_DTX_N5
PCIE_PRX_C_DTX_P5

RSET
+LAN_VDD10

LAN_XTALO
LAN_XTALI

LAN_DISABLE#
+LAN_REGOUT
+LAN_VDD10

PCIE_WAKE#_R
ISOLATE#

PLT_RST#

RL81

2.49K_0402_1%

@

1

RL12

CL10 1 2 0.1u_0201_10V6K
CL11 1 2 0.1u_0201_10V6K

CL10 close to Pin18
CL11 close to Pin 17

2

0_0402_5% TL4 @ 1

CL6

CL7

1

2

1

2

0.1u_0201_10V6K

0.1u_0201_10V6K

Close to Pin 32

UL1

33

GND

32

AVDD33_2

31

RSET

30

AVDD10

29

CKXTAL2

28

CKXTAL1

27

LED0

26

LED1/GPIO

25

LED2

24

REGOUT

23

VDDREG

22

DVDD10

21

LANWAKEB

20

ISOLATEB

19

PERSTB

18

HSON

17

HSOP

RTL8111GUL-CG QFN 32P

8111GUL@

+3VALW_LAN +LAN_VDDREG

16

REFCLK_N

15

REFCLK_P

14

HSIN

13

HSIP

12

CLKREQB

11

AVDD33_1

10

MDIN3

9

MDIP3

8

AVDD10_2

7

MDIN2

6

MDIP2

5

MDIN1

4

MDIP1

3

AVDD10_1

2

MDIN0

1

MDIP0

RL1 @

1 2

0_0603_5%

CLK_PCIE_LAN#
CLK_PCIE_LAN
PCIE_PTX_C_DRX_N5
PCIE_PTX_C_DRX_P5
LAN_CLKREQ#_R
+3VALW_LAN
LAN_MDI3­LAN_MDI3+
+LAN_VDD10
LAN_MDI2-+LAN_VDDREG
LAN_MDI2+
LAN_MDI1­LAN_MDI1+
+LAN_VDD10
LAN_MDI0­LAN_MDI0+

1

CL1

4.7U_0402_6.3V6M 0.1u_0201_10V6K

2 2

LAN_CLKREQ#_R

CLK_PCIE_LAN#
CLK_PCIE_LAN

PCIE_PTX_C_DRX_N5
PCIE_PTX_C_DRX_P5

LAN_MDI3- 38
LAN_MDI3+ 38

LAN_MDI2- 38
LAN_MDI2+ 38
LAN_MDI1- 38
LAN_MDI1+ 38

LAN_MDI0- 38
LAN_MDI0+ 38

10

10

1

CL2

+3VALW_LAN +3VS

@

RL4

10K_0402_5%

9
9

QL1

1

2

2N7002KW_SOT323-3

RL18 1 @ 2 0_0402_5%

2

G

1 3

D

@

S

LAN_CLKREQ# 10

B B

LAN_XTALO_R

YL1

1

OSC1 GND2

2

GND1 OSC2

1

CL12

12P_0402_50V8-J

A A

25MHZ_10PF_7V25000014

2

5

4
3

1

CL13
15P_0402_50V8J

2

1 2

RL21 1K_0402_5%

4

LAN_XTALI

LAN_XTALO

+LAN_REGOUT

For RTL8111GUL(SWR mode, reserved)

For RTL8111H (LDO mode)

LL1 1 2 8111GUL@

2.2UH_NLC252018T-2R2J-N_5%

RL20 1 2 8111H@ 0_0805_5%

1

CL15

4.7U_0402_6.3V6M

Layout Note: LL1 must be
within 200mil to Pin24,
CL15,CL 16 must be within
200mil to LL1
+LAN_REGOUT: Widt h =60mil

Security Classification

Issued Date

THISII SHEET OF ENGINII EERINII G DRAW INII G ISII THEPROPRIETARYII PROPERTY OF LC FUTURE CENTER. AND CONTAINII S
CONFIDII ENTIALII
AND TRADE SECRET INII FORMATIOII N. THISII SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISIOIIIIII N OF R&D
DEPARTMENT EXCEPT AS AUTHORIZII ED BY LC FUTURE CENTER NEITII HER THISII SHEET NOR THE INII FORMATIOII N ITIICONTAINSII
MAY BE USED BY OR DISCLII OSED TO ANY THIRDII PARTY WITII HOUT PRIOII R WRITTII EN CONSENT OF LC FUTURE CENTER.

2

3 2

+LAN_VDD10

1

CL16

0.1u_0201_10V6K

2

1

CL17

0.1u_0201_10V6K

2

LC Future Center SecretData

2015/08/20 Deciphered Date

1

CL18

0.1u_0201_10V6K

2

Close to Pin3, 8, 22, 30

2016/08/20

1

CL19

0.1u_0201_10V6K

2

1

CL20

0.1u_0201_10V6K

2

Title

LAN_RTL8111H_CG

Siiize Document Number

Custom

Date:

Sunday, J anuary 22, 2017

1

CL21
1U_0402_6.3V6K

2

Close to Pin 22(Reserved)

DG42A

Sheet 37 of 60

1

1

CL22

0.1u_0201_10V6K

2

R ev

1.0

5

4

3 2 1

DL1/DL2

1'S PN:SC300003M00

TL1

D D

LAN_MDI2+
LAN_MDI2-

LAN_MDI3+
LAN_MDI3-

C C

LAN_MDI1­LAN_MDI1+

LAN_MDI0­LAN_MDI0+

DL1

1

LINE1IN LINE1OUT

2 9

LINE2IN LINE2OUT

3 GND1 GND2
4 LINE3IN LINE3OUT

5

LINE4IN LINE4OUT

11 GND3 GND5
12 GND4

AZ3133-08F.R7G_DFN3020P10E10

EMC_NS@

DL2

1

LINE1IN LINE1OUT

2 9

LINE2IN LINE2OUT

3 GND1 GND2
4 LINE3IN LINE3OUT

5 6

LINE4IN LINE4OUT

11

GND3

12

GND4

AZ3133-08F.R7G_DFN3020P10E10

EMC_NS@

10

7

6

10

7

GND5

LAN_MDI2+
LAN_MDI2-

8

13

8

13

LAN_MDI3+
LAN_MDI3-

LAN_MDI1­LAN_MDI1+

LAN_MDI0­LAN_MDI0+

1

2

37 LAN_MDI0+
37 LAN_MDI0-

37 LAN_MDI1+
37 LAN_MDI1-

37 LAN_MDI2+
37 LAN_MDI2-

37 LAN_MDI3+

37 LAN_MDI3-

CL24

0.01U_0201_25V6-K

EMC@

EMC

LAN_MDI0+

LAN_MDI0-

LAN_MDI1+
LAN_MDI1-

LAN_MDI2+
LAN_MDI2-

LAN_MDI3+
LAN_MDI3-

24
23
22
21
20
19
18
17
16

15

14
13

BOTH_GST5009 LF

TCT1

MCT1
MX1+
MX1­MCT2
MX2+
MX2­MCT3
MX3+
MX3­MCT4
MX4+

MX4- TD4-

TD1+

TCT2

TD2+

TCT3

TD3+

TCT4

TD4+

Place Close to TL1

EMC

B B

RL14 1 2

1 2

RL15
RL16

1 2

@

0_0603_5%

@

0_0603_5%

@

0_0603_5%

EMC

CHASSIS1_GND

TD1-

TD2-

TD3-

1
2
3

5
6
7
8
9
10

12

4

11

MCT
LAN_MDO0+

LAN_MDO0-

MCT
LAN_MDO1+

LAN_MDO1-

MCT
LAN_MDO2+

LAN_MDO2-

MCT
LAN_MDO3+

LAN_MDO3-

LAN_MDO0+
LAN_MDO0-

LAN_MDO1+
LAN_MDO2+
LAN_MDO2­LAN_MDO1­LAN_MDO3+
LAN_MDO3-

2 1

1

0.022U_0603_50V7K

CL32

EMC@

JRJ1

1

TX_DA+

2

TX_DA-

3

RX_DB+

4

BI_DC+

5

BI_DC-

6

RX_DB-

7

BI_DD+

8

BI_DD-

ALLTO_C10235-10839-L

2

CHASSIS1_GND

8/16 Update RJ45 P/N DC021608091 wei

EMC@

RL17
20_0603_5%

1

CL25
1000P_1206_2KV7-K

EMC@

2

ME@

GND_4
GND_3
GND_2

GND_1

EMC

12
11
10

9

CHASSIS1_GND

1

DL3

1

PDT5061_DO-214AA

EMC@

2

EMC

2

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

2015/08/20

3 2

LC Future Center Secret Data

Deciphered Date 2016/08/20

Title

LAN_Transformer

Size Document Number

B

Sunday, January 22, 2017

DG42A

Sheet

1

Rev

1.0

38 of 60Date:

5

4

3 2 1

Close to U1

2200P_0201_25V7-K

D D

C44

REMOTE+_R

1

@

REMOTE-_R

2

REMOTE+_R

REMOTE-_R

R176 1 @ 2 0_0402_5% REMOTE2+

R177 1 @ 2 0_0402_5% REMOTE2-

REMOTE+/-_R, REMO TE1+ /-, REMOTE2+/-:
Trace width/space:10/10 mi l

Trace length: <8"

SMSC thermal sensor

+3VS

1

C47

0.1u_0201_10V6K

@

2

+3VS

C C

+5VLP

1

C7

0.1u_0201_10V6K

@

2

B B

REMOTE+_R
REMOTE-_R

1

R51 2@

10K_0402_5%

over temperature threshold :
RSET=3* RTMH
92+/-3 0C

Hysteresis temperature thr esho ld.
RHYST=( RSET*RT ML )/(3*RT ML -RSE T)
56+/ -30C

placed near DIMM

U1 @

1 VDD SCL
2 D+ SDA
3 D- ALERT#
4 T_CRIT# GND

NCT7718W_MSOP8

Address 1001_101xb

HW thermal sensor

U4 @

1

VCC TMSNS1

2

GND RHYST1

3

OT1 TMSNS2

4

OT2 RHYST2

G718TM1U_SOT23-8

8

TMSNS1

7

PHYST1 R6 1@

6

TMSNS2

5

PHYST2 R7 1@

EC_SMB_CK2

8

EC_SMB_DA2

7

6
5

2

2

21.5K_0402_1%

10K_0402_5%

10K_0402_5%

EC_SMB_CK2 7,44
EC_SMB_DA2 7,44

+5VLP +5VLP

2

R252

@

1

2

R253

21.5K_0402_1%

@

1

R196 1 @ 2 0_0402_5%

R197 1 @ 20_0402_5%

NTC_V1

NTC_V2

NTC_V1 44

NTC_V2 44EC_ON44,54,55

REMOTE2+

100P_0201_25V8J

REMOTE2-

NTC_V2

1

C46

2

Q16

B

@

2

+3VALW

1

1 22

Near CPU core

C

MMBT3904WH_SOT323-3

E

@

3 1

Near CPU

R25

13.7K_0402_1%

R288
100K_0402_1%_NCP15WF104F03RC

for layout optimized, change the EC_AGND to GND

+5VS

R52 1 @ 2 0_0603_5%

1

C49

10U_0805_10V6K

2

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENT ER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/08/20 Deciphered Date

3 2

LC Future Center Secret Data

2016/08/20

@

1

2

C50

44 EC_FAN_SPEED
44 EC_FAN_PW M

0.1u_0201_10V6K

Title

Thermal sensor/FAN CONN

Siiize Document Number

Custom

Date:

FAN Conn

+5VS_FAN

Sund ay, Janu ary 22, 2017

DG42A

JFAN1 ME@

1

1

2

2

3

3

4

4

5

GND1

6

GND2

ACES_85205-04001

ONNONN

Sheet 39

1

of 60

R ev

1.0

A B

C D E

Mini-Express Card(WLAN/WiMAX)

49.9K_ 0402_1%

2

1K_04 02_5%

W

R258

+3VS

R259

49.9K_ 0402_1%

2

1

2

1

UART_RX _DEBUG 8

UART_TX_ DEBUG 8

EC_RX 44

SUSCLK 10
PLT_RST# 11,32,37,40,44
PCH_BT_ OFF# 8
PCH_W LAN_OFF# 8

SMB_D ATA_S3 7,18
SMB_C LK_S3 7,18

EC_TX 44

+3VS_W LAN

@

2

2

10 W LAN_C LKREQ#

11,37,44 PCIE_WAKE#

37,44 LA N_W AKE#

+3VS_W LAN+3VS

1

C53

0.1u_0 201_10V6K

@

2

9 USB20_P7
9 U SB20_N7

9 P CIE_PTX_ C_DRX_P6
9 PCIE_P TX_C_DRX _N6

9 PCIE_PRX_DTX_P6
9 P CIE_PRX_ DTX_N6

10 CLK_PCIE _WL AN
10 CLK_PCIE _WLA N#

R61 1 @ 2 0_04 02_5%

1

R262

@ 2 0_0402_5 %

R57 1 @ 2 0_04 02_5%

W LAN_CLKREQ_Q #
PCIE_W AKE#_W LAN

JWLAN1

1

GND1

3

USB _D+

5

USB_D -

7

GND2

9

SDIO _CLK

11

SDIO _CMD

13

SDIO _DAT A0

15

SDIO _DAT A1

17

SDIO _DAT A2

19

SDIO _DAT A3

21

SDIO _WA KE#

23

SDIO_RE SET#

25
27
29
31

33

GND3

35

PETP 0

37

PETN0

39

GND4

41

PER P0

43

PER N0

45

GND5

47

REF CLKP 0

49

REF CLKN0

51

GND6

53

CLK REQ0#

55

PEW AK E0#

57

GND7

59

RSR VD/P ETP1

61

RSRVD/ PETN1

63

GND8

65

RSR VD/P ERP1

67

RER VD/P ERN1

69

GND9

71

RSR VD/RE FCLK P1 UIM_ POW ER_SR C/GPI O1/P EWAKE 1#

73

RSR VD/RE FCLKN 1

75

GND1 0 3 .3VA UX4

77

GND1 5 GND1 4

ARGOS_ NASE0-S6 701-TS40

PCM _CLK/ I2S_S CK

PCM _SYNC /I2S _WS

PCM _IN/ I2S_S D_IN

PCM _OUT/ I2S_ SD_OU T

UAR T_WA KE#

KEY E
PIN24~PIN31 NC PIN

VEN DOR_D EFINE D1
VEN DOR_D EFINE D2
VEN DOR_D EFINE D3

W_ DISA BLE2 #
W_ DISA BLE1 #

UIM_ SWP /PERS T1#

UIM_ POW ER_SN K/CLK REQ1#

ME@

3.3 VAUX 1

3.3 VAUX 2
LED 1#

LED #2

GND1 1

UAR T_RXD

UART_TXD
UART_CTS
UART_RTS

COE X3
COE X2
COE X1

SUS CLK

PER ST0#

I2C_DATA

I2C_ CLK

ALE RT#

RSR VD

3.3 VAUX 3

2
4

6
8
10
12
14

16

18

20
22

24
26
28
30

32

34

36
38
40
42

44

46

48

50

52
54
56

58

60

62

64
66

68

70

72

74

76

1

@ T2

1

@ T3

UART_RX _DEBUG_R

UART_TX_ DEBUG_R

EC_TX _RSVD
EC_R X_RSVD

SUSCL K_R
PLT_RST#
BT_OFF#
WL AN_OFF#

W LAN_SMB_DATA

LAN_S MB_CLK

EC_TX _R

+3VS_W LAN

R256 1 @ 20_0402_ 5%

R257 1 @ 2 0_040 2_5%

R62 1 @ 2 0_ 0402_5%

1

R63

@ 2 0_0402_ 5%

R88 1 @ 20_0402_ 5%

R55 1 @ 20_0402_ 5%

1

R53
R56 1 @ 2 0_040 2_5%

@ 2 0_0402_5 %

R58 1

1

@ 20_0402_ 5%

R59

R89 1 @ 2 0_040 2_5%

R186
100K_ 0402_5%

2

1

Need short

J2

1

1

1 1

2 2

JUMP_43X79

8/16 Update Conn. P /N SP070013 200 wei

Optane Memory

JSSD1 ME@

1

GND_ 1

3

GND_ 2

+3VS +VS_SS D

Need short

1

2

3 3

J14

4 4

@

2

1

JUMP_43X79

22U_0603_6.3V6-M

1

1

C137

2

2

OPTANE@

OPTANE@

A B C D

0.1u_0201_10V6K

22U_0603_6.3V6-M

C207

1

C146

2 2 2 2

OPTANE@

OPTANE@

10K_0 402_5%

9 SS D_DET#

10K_0 402_5%

MAX 1.5A

0.1u_0201_10V6K

0.01U_0201_10V6K

C2048

C2049

1

1

OPTANE@

+VS_SS D

1

8/24 CPU side 10K PU w ei

R3102

@

2

1

@

R3101

2

C2050

1

OPTANE@

SSD_DET#
0--SA TA
1--PCIE

0.01U_0201_10V6K

SSD_DE T#

9 P CIE_PRX_ DTX_N9

9 PCIE_PRX_DTX_P9
9 PCIE_PTX_ C_DRX_N9

9 P CIE_PTX_C _DRX_P9

9 PCIE_PRX _DTX_N10

9 P CIE_PRX_ DTX_P10
9 PCIE_P TX_C_DRX _N10

9 PCIE_P TX_C_DRX_ P10

9 PCIE_PRX _DTX_N11

9 P CIE_PRX_ DTX_P11
9 PCIE_P TX_C_DRX _N11

9 PCIE_P TX_C_DRX_ P11

9 PCIE_PRX _DTX_N12

9 P CIE_PRX_ DTX_P12
9 PCIE_P TX_C_DRX _N12

9 PCIE_P TX_C_DRX_ P12

10 C LK_PCIE_ SSD#
10 CLK _PCIE_SS D

SSD_DE T#

Security Clllassiiifiiication

Issued Date

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPE RTY OF LC F UTURE CENTER... AND CONTAIIINS CONFIIIDENTIAL

AND TRADE SE CRET IIINFORMATION... THIIIS SHEET MAY NOT BE TR ANSFE RED FR OM T HE CU STODY OF T HE CO MPETE NT DIIIVIIISIIION OF R &D
DEPARTMENT EX CEPT AS AUTHORIIIZED BY LC FUT URE CE NTER NEI THER THIIIS SHEET NO R THE IIINFORMATION IT CONTAIIINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WI THOUT PRIIIOR WRITTEN CONS ENT OF LC FUTURE CE NTER.

5

PER N3

7

PER P3

9

GND_ 3

11

PETN 3

13

PETP 3

15

GND_ 4

17

PER N2

19

PER P2

21

GND_ 5

23

PETN 2

25

PETP 2

27

GND_ 6

29

PER N1

31

PER P1

33

GND_ 7

35

PETN 1

37

PETP 1

39

GND_ 8

41

PER N0/S ATA_B +

43

PERP0 /SATA_B-

45

GND_ 9

47

PETN0/S ATA-A-

49

PETP0/ SATA-A+

51

GND_ 10

53

REF CLKN

55

REF CLKP

57

GND_11

59 NC
61 NC
63 NC
65 NC

67

N/C _1

69

PED ET

71

GND_ 12

73

GND_ 13

75

GND_ 14

77

PEG 1

ARGOS_ NASM0-S6 701-TSH4

2015/08/20

DAS /DSS #/LED 1#

CLK REQ#

PEW AK E#

LC Future Center Secret Data

2

3.3 V_1

4

3.3 V_2

6

N/C_2

8

N/C_3

10
12

3.3 V_3

14

3.3 V_4

16

3.3 V_5

18

3.3 V_6

20

N/C_4

22

N/C_5

24

N/C_6

26

N/C_7

28

N/C_8

30

N/C_9

32

N/C _10

34

N/C _11

36

N/C _12

38

DEV SLP

40

N/C _13

42

N/C _14

44

N/C _15

46

N/C _16

48

N/C _17

50

PER ST#

52

54

56

N/C _18

58

N/C_19

NC 60
NC 62
NC 64
NC 66

68

SUS CLK

70

3.3 V_7

72

3.3 V_8

74

3.3 V_9

76

PEG 2

Deciphered Date

1

@

+VS_SS D

PLT_RST#
SSD_CL KREQ_Q#

TP264

+VS_S SD

+VS_SS D

R3099

@

10K_0 402_5%

1

2

R3100

R3098 1 @ 2 0_04 02_5%

2016/08/20

2

1

10K_0 402_5%

OPTANE@

SSD_P CIE_CLKR EQ# 10

Title

NGFF WLAN&SSD

Size Documenttt Number C R ev

Dattte: Sheet 40 of 60

DG42A

Sunday, ,, Ja nua ry 22,,, 2017

E

1.0

A B C D E

+USB_ VCCA

+

C55 1 2

220U_6.3V_M

7 1 2

C111

LEFT SIDE USB3.0 PORTx2

+5VALW + USB_VCCA

1 1

1

C128
1U_0402_ 6.3V6K

2

44 USB_ON #

U2

5

IN OUT

GND

4

ENB OCB

SY6288 D20AAC_SOT23 -5

Low Active 2A

1

2
3

USB_OC 1#

1

C140
1000P_0201_50V7-K

EMC_NS @

2

USB_OC 1# 9

9 USB30_TX_P1
9 USB30_TX_N1 9

USB20_P1

9 USB 20_N1

9 USB3 0_RX_P1

9 USB 30_RX_N1

USB30_TX_P1
USB30_TX_N1

USB20 _N1
USB30_ RX_P1

USB30_ RX_N1

2 0.1u_ 0201_10V6K USB30 _TX_C_P1 R95 1

126

C
C12411

2

0.1u_0 201_10V6K

USB30 _TX_C_N1

@ 20_0402 _5%

1

@ 20_0402_5 %

R96

1

R97

2

@ 0_0 402_5%

R93 @ 0_0 402_5%

1 2
1 2

R94 @ 0_0 402_5%
R98 1 @ 2 0 _0402_5%

USB30_ TX_R_P1
USB30_ TX_R_N1

USB20 _P1_R
USB20 _N1_R

USB30 _RX_R_P1
USB30_ RX_R_N1 G ND_1

2

1

C125

1

2

C127

@

JUSB1

9

StdA_ SSTX+

1

VBU S

8

StdA_ SSTX-

3

D+

7

GND_ DRA IN

2

D-

6

Std A_SS RX+

4

5

Std A_SS RX- GN D_5

ALLTO_C 190AG-109 39-L

47U_080 5_6.3V6-M@

1U_0402_ 10V6K@

1U_0402 _10V6K

ME@

GND_ 2
GND_3
GND_ 4

13

10
11
12

09/05 Update USB Conn. P/N DC0 21609011 wei

L13

USB30_ RX_N1 USB 30_RX_R_N1

USB30_ RX_P1 US B30_RX_ R_P1

USB30_ TX_C_N1 USB30_ TX_R_N1

USB30_ TX_C_P1 USB3 0_TX_R _P1

2 2

3 3

4 4

USB20_P1

USB20_ N1

USB30_ RX_N3 USB3 0_RX_R_N3

USB30_ RX_P3 US B30_RX_R _P3

USB30_ TX_C_N3 USB30_ TX_R_N3

USB30_ TX_C_P3 USB3 0_TX_R_ P3

USB20_P3

USB20_ N3

1

4

1

4

1

4

1

1

4

4 3

EXC24 CH900U_4P

L16

1

1

4

4 3

EXC24 CH900U_4P

L8

1

1

4

4 3

EXC24 CH900U_4P

L30

EMC @

1

4 3

EXC24 CH900U_4P

L29 EMC @

1

4 3

EXC24 CH900U_4P

L17 EMC@

1 2

4 3

EXC24 CH900U_4P

EMC @

2

2

3

EMC@

EMC @

2

2

3

USB20_ P1_R

2

2

USB20 _N1_R

3

+USB_ VCCA

1

2

AZ5725-01F.R7GR_DFN1006P2X2

2 1

EMC@

D11

EMC

2

2

3

2

2

3

9 USB30_TX_P3
9 USB30_TX_N3 9

USB20_P3

9 U SB20_N3

9 U SB30_RX_P 3

9 USB 30_RX_N3

EMC

USB20_ P1_R
USB20 _N1_R

3

2

D13
AZC199 -02S.R7G_S OT23-3

EMC @

1

USB30_TX_P3 C205812 0.1 u_0201_10V6K USB 30_TX_C_P3 R3 119
USB30_TX_N3

USB20 _N3

USB30_ RX_P3

USB30_ RX_N3

C2057

1

2

0.1u_0 201_10V6K

USB30 _TX_C_N3

USB30 _RX_R_N1
USB30 _RX_R_P1
USB30 _TX_R_N1

USB30 _TX_R_P1

1

@ 2 0_0402_5 %

1

@ 20_0402_5 %

R3116

R31031

2

@ 0_0 402_5%

R942 1 @ 20_0402_ 5%

1 2

R3117 @ 0 _0402_5%
R3114 1 @ 2 0_0402 _5%

USB30 _RX_R_N3

D12

9

10

8

9

7

7

6

6

AZ1045 -04F_DFN251 0P10E-10-9

USB30 _TX_R_P3

USB30_ TX_R_N3
USB20 _P3_R

USB20 _N3_R
USB30 _RX_R_P3

EMC@

USB30 _RX_R_N1

1

1

USB30 _RX_R_P1

2

2

USB30 _TX_R_N1

4

4

USB30 _TX_R_P1

5

5

3

3

8

+USB_ VCCA

C2060

C2059

@ 1 U_0402_10V6 K

2

1

1U_0402_ 10V6K@

2

1

JUSB3 M E@

9

Std A_SS TX+

1

VBU S

8

StdA_ SSTX-

3

D+

7

GND_DRAIN

2

D-

6

Std A_SS RX+ GND_ 3

4

GND_1 GND_4

5

Std A_SS RX- GND _5

ALLTO_C 190AG-109 39-L

GND_2

10
11
12
13

09/05 Updat e USBConn. P/ N DC021609011 wei

USB20_ P3_R

2

USB20 _N3_R

3

USB20_ P3_R

USB20 _N3_R

Close to C onnect orFOR ESD

+USB_ VCCA

3

2

D43
AZC199 -02S.R7G_S OT23-3

EMC @

1

1

D34

EMC_NS@

2 1

2

AZ5725-01F.R7GR_DFN1006P2X2

USB30 _RX_R_N3
USB30 _RX_R_P3

USB30 _TX_R_N3
USB30 _TX_R_P3

EMC @

D45

9

10

8

7
6

6

1

9

2

7

4

5

3

8

AZ1045 -04F_DFN251 0P10E-10-9

USB30 _RX_R_N3

1

USB30 _RX_R_P3

2

USB30 _TX_R_N3

4

USB30 _TX_R_P3

5

3

Security Clllassiiifiiication

Issued Date

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPE RTY OF LC F UTURE CENTER... AND CONTAIIINS CONFIIIDENTIAL

AND TRADE SE CRET IIINFORMATION... THIIIS SHEET MAY NOT BE TR ANSFE RED FR OM T HE CU STODY OF T HE CO MPETE NT DIIIVIIISIIION OF R &D
DEPARTMENT EX CEPT AS AUTHORIIIZED BY LC FUT URE CE NTER NEI THER THIIIS SHEET NO R THE IIINFORMATION IT CONTAIIINS

A B C D

MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WI THOUT PRIIIOR WRITTEN CONS ENT OF LC FUTURE CE NTER.

2015/08/20

LC Future Center Secret Data

Deciphered Date

2016/08/20

Title

USB3.0 PORT(LEFT)

Size Documenttt Number C R ev

Dattte: Sheet 41 of 60

DG42A

Sunday, ,, Ja nua ry 22,,, 2017

E

1.0

A

B

C

D E F G

H

SATA HDD Conn.

1 1

+5VS_HDD

9 SATA_PTX_DRX_P0

1

C74 C76
33P_0201_50V8-J

RF@

2

1

33P_0201_50V8-J

RF@

2

1

C75

0.1u_0201_10V6K

2

1

C77
10U_0805_10V6K

2

1

C78
10U_0805_10V6K

@

2

9 SATA_PTX_DRX_N0

9 SATA_PRX_DTX_N0
9 SATA_PRX_DTX_P0

For EMC

2 2

+5VS +5V_ODD

Need Short

J4 @

1

2

1 2

JUMP_43X79

C85

1

1

CD@

2

2

10U_0603_10V6K

0.1u_0201_10V6K

C86

SATA_PTX_DRX_P0
SATA_PTX_DRX_N0

SATA_PRX_DTX_N0
SATA_PRX_DTX_P0

1

2 0.01U_0201_10V6K

C66

2 0.01U_0201_10V6K

1

C67

1

2 0.01U_0201_10V6K

C68

2 0.01U_0201_10V6K

C69

1

+5VS +5VS_HDD

Need short

1

J3

JUMP_43X79

1 2

SATA_PTX_C_DRX_P0
SATA_PTX_C_DRX_N0

SATA_PRX_C_DTX_N0
SATA_PRX_C_DTX_P0

2 @

JHDD1

10

10

9

9

8

8

7

GND2

7

6

6

5

5

4

3

4

GND1

2

3

1

2
1

ELCO_006809610010846

ME@

12

11

FOR 14"

SATA ODD Conn.

3 3

4 4

9 SATA_PTX_DRX_P1
9 SATA_PTX_DRX_N1

9 SATA_PRX_DTX_N1

9 SATA_PRX_DTX_P1

A

SATA_PTX_DRX_P1
SATA_PTX_DRX_N1

SATA_PRX_DTX_N1
SATA_PRX_DTX_P1

14@C70

14@C72

B

1

1

0.01U_0201_10V6K

2
2

0.01U_0201_10V6K14@C71

0.01U_0201_10V6K

2
2

0.01U_0201_10V6K14@C73

1

1

SATA_PTX_C_DRX_P1_14
SATA_PTX_C_DRX_N1_14

SATA_PRX_C_DTX_N1_14
SATA_PRX_C_DTX_P1_14

+5V_ODD

C

JODD1 ME@

1

GND_1

2

RX+

3

RX-

4

GND_2

5

TX-

6
7

TX+

GND_3

8
9

DP

10

+5V_1

11

+5V_2

12

MD GND1

13

GND_4 GND2

GND_5

SUYIN_127382FB013S255ZL

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENT ER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

SATA_PTX_DRX_P1
SATA_PTX_DRX_N1

SATA_PRX_DTX_N1
SATA_PRX_DTX_P1

14
15

15@ C79 1
15@ C80 1 2 0.01U_0201_10V6K

15@ C81 1
15@ C82 1 2 0.01U_0201_10V6K

LC Future Center SecretData

IssuedDate

D E F

2015/08/20 Deciphered Date

2 0.01U_0201_10V6K

2 0.01U_0201_10V6K

2016/08/20

SATA_PTX_C_DRX_P1_15
SATA_PTX_C_DRX_N1_15

SATA_PRX_C_DTX_N1_15
SATA_PRX_C_DTX_P1_15

+5V_ODD

8/16 Update Conn. P/N SP01001YV00 wei

Title

HDD/ODD CONN

Siiize Document Number

Custom

G

FOR 15" 17''

SATA ODD FFC Conn

JODD2

ME@

1

1

2

2

3

3

4

4

5

5

6

6

7

8

7
8

9

10

GND1
GND2

HIGHS_FC5AF081-2931H

Sund ay, Janu ary 22,2017

DG42A

Sheet

R ev

42 of 60Date:

H

1.0

5 4 3 2 1

D D

9 USB30_ TX_N2
9 USB30_TX_ P2

9 USB30 _RX_N2

9 US B30_RX_P2

C C

USB30_ RX_N2

C2068 1

USB30_ RX_P2

USB30_ TX_N2
USB30_ TX_P2

B B

A A

2 0.1U_02 01_6.3V6-K
2 0.1U_0 201_6.3V6- K

C2067 1

2 0.1U_0 201_6.3V6- K

C2065 1

2

1

C2066

+3V_MUX +3V_MUX

2

R3139 R3142
10K_0 402_5% @ 1 0K_0402 _5%

M1 M0

R3144

@ 10K_ 0402_5 %

1 2 1

+3V_MUX

2

R3146

@ 10K_ 0402_5 %

1

VBUS_EN

2

R3141
10K_0402_ 5%

1

+3V_MUX

PH at CPU s ide 09 /06 wei

2

R3147

@ 10K _0402_ 5%

1

TYPE_C_O CP#

2

R3140

@ 10K_ 0402_5 %

1

USB30_ TX_N2

USB30_ TX_P2

USB30_RX_N2

USB30_RX_P2

+3VALW

R1331@20_0402_5%

0.1U_0 201_6.3V6 -K

+3VS

USB30_ RX_N2_M

USB30_ RX_P2_M 5SSRX_1P/ 2N

USB30_ TX_N2_M

USB30_TX_P2_ M

R134 1

TYPE_C_OC P#
VBUS_EN

VMON

M1
M0

6.2K_040 2_1%

@ 2 0_0402_5%

4

6

R3150

1 2

Rp configuration

Rp:1.5A (now)

2

Rp:900mA 0 1

Rp:1.5A 1 0

Rp:3.0A 1 1

R4674
10K_0402_ 5%

1 2 1

For C_VBUS
power switch enable pin

Power switch enable pin

Low Active R3146 mount

High Active R3141 mount

For C_VBUS
power switch OCP pin

Power switch OCP pin

Low Active R3147 mount

High Active R3140 mount

5 4 3 2 1

+3V_MUX +5V_MUX

U26

16

OCP_DET

15

VBUS_EN

17

VMON

SSRX_1N/ 2P

10Gbps 2:1 MUX

SSTX_1 P/2N

7

SSTX_1 N/2P

23

NC

21

RP_SEL _M1

22

RP_SEL _M0

18

REXT

M1 M0 Note

+5VALW

+5VS

C_TX2_ 1P/2N
C_TX2_ 1N/2P

C_RX2_1 P/2N
C_RX2_1 N/2P

C_TX1_ 1P/2N 9 MUX_TX1_ P
C_TX1_ 1N/2P

C_RX1_1 P/2N
C_RX1_1 N/2P

Realtek

RTS5449

RTS5449 -GR_QFN2 4_4X4

R3144/R3142 mount

R3139/R3143 mount

R3139/R3142 mount

R1731@20_0402_5%

@ 2 0_0402_5%

R174 1

2

CC1271

220P_ 0201_25V7-K

1

12

CC1

14

CC2

MUX_TX2_ N

11

MUX_TX2_ P

10

C2075 1

24 A10

1

MUX_TX1_ N

8

C2074 1

2 B10

3

13

VCON_IN

19

5V_IN

20

LDO_3V3

25

E-PAD

Note

Note

2

CC1272

220P_ 0201_25V7-K

1

C2076 1 2 0.1U_02 01_6.3V6-K

2 0.1U_02 01_6.3V6- K

C2073 1 2 0.1U_020 1_6.3V6-K

2 0.1U_02 01_6.3V6-K

+3V_MUX

1

C2064

CC1273

2

4.7U_0 402_6.3V6M

Close Pin 19

9 USB20 _P2

9 US B20_N2

A5

CC1

B5

CC2

C_TX2_ N

C_TX2_ P

C_TX1_ N

C_TX1_ P

+5V_MUX

2

1

0.1u_0 201_10V6K

C_TX2_N

C_TX2_P C_TX 2_P_C

C_RX2_P

C_RX2_N

C_RX2_N
C_RX2_ P

C_RX1_N
C_RX1_ P

C2063

2

1 1

0.1u_0201_10V6K

Close Pin 13

C2077

B3
B2

A11

A3
A2

B11

2

10U_08 05_10V6K

R943 1@2 0_0402_5%

L23

1

1

4

4 3

EXC24C H900U_4P

R91 1@2 0_0402_5%

R944 2@1 0_0402_5%

L24 E MC@

3 4

3 4

2

2 1

EXC24C H900U_4P

R3107 2@1 0_0402_5%

R100 2@1 0_0402_5%

L25 E MC@

3 4

3 4

2

2 1

EXC24C H900U_4P

R101 2@1 0_0402_5%

47U_08 05_6.3V6-M

VBUS_P0

EMC@

2

1

1

U27 @

1

6

+5VALW VBUS_P0

3.3K_ 0402_1% 1 @ 2 R418 5

Iset = 6800 /3.3k=2. 06A

11/16 SIT Reserve Power switch for OPC# flip issue wei

+5VALW1.5A

R3155
200K_0402_1 %

2 1

2

R3149
10K_0402_ 1%

1

2

3

1

1

+

C213

@

2

2

VBUS_EN

VMON

EMC_NS@

C_DP

C_DM

C_TX2_ N_C

C_RX2_ P_C

C_RX2_ N_C

IN OUT

2

ISET GND

VBUS_EN

4

EN/ENB OC B

SY686 1B1ABC_SOT23-6

C1333
150U_B 2_6.3VM_R35M

U6

A1

VIN1

B1

VIN2

C1

VIN3

D3

ON

GND2A2GND1

B2

C2

VBUS_P0

D38

1

1

C918

2

2 1

2

AZ5725 -01F.R7GR_DF N1006P2X2

Securittty Classificiiffii atttionii LC Future Center Secret Data

Issued Da te 2015///08///20 D eciphered Date 2016///08///20

THIIIS SHEET OF ENGINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF LC FUTURE CENTER... AND CONTAIIINS CONFIIIDENTIIIAL
AND TRADE SECRET IIINFORMATION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIIIZED BY LC FUTURE CENTER NEIIITHER THIIIS SHEET NOR THE IIINFORMATION IIIT CONTAIIINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIOR WRIIITTEN CONSENT OF LC FUTURECENTER.

TYPE_C_O CP#

3

A3

VOUT1

B3

VOUT2

C3

VOUT3

D1

OC_FL AGB

ISET

GND3

FPF25 95UCX_W LCSP12

Rset 52 8 Min 18 00mA Type 2 000mA Max 2200 mA Rse t
469 Min 2 025mA Type 2250mA Max 2475mA

1

C919

C922

@

2 1

2

10U_0805_25V6K

4.7U_0805_25V6-K

0.47U_0402_25V6-K

R3135 1@2 0_0402_5%

C_RX1_N

C_RX1_P

R3137 1@2 0_0402_5%

R3136 1@2 0_0402_5%

C_TX1_P C_ TX1_P_C

C_TX1_N C_TX 1_N_C

VBUS_P0

TYPE_C_O CP# D2

2 1

C921

C920

2 1

2 1

0.47U_0402_25V6-K

EMC@

L31

4

4

1

1

EXC24C H900U_4P

L32 E MC@

4 3

4 3

1

1

EXC24C H900U_4P

R3138 1@ 2 0_0402_5%

R604
523_0402_1%

2 1

0.47U_0402_25V6-K

3

3

2

2

2

2

TYPE_C_O CP# 9

C1334

0.47U_0402_25V6-K

C_TX2_ P_C
C_TX2_ N_C

C_RX1_ N_C

C_RX1_ P_C

C_RX1_ N_C

C_RX1_ P_C

D36

9

10

8

9

7

7

6

6

AZ1045 -04F_DFN2510 P10E-10-9

EMC_NS@

C_DM
C_DP

CC2

C_TX2_ N_C

C_TX2_ P_C

1

1

2

2

4

4

5

5

3

3

8

C_RX1_ P_C

C_RX1_ N_C

22

CC1
CC2

C_TX2_ P_C
C_TX2_ N_C

C_RX1_ N_C
C_RX1_ P_C

VBUS_P0

3A

JP1

24

Power_ GND_B12

23

SSRXp1_B11
SSRXn1_B10

21

VBUS_B9

20

SBU2_B8

19

Dn2_B7

18

Dp2_B6

17

CC2_B5

16

VBUS_B4

15

SSTXn2_B3

14

SSTXp2_B2

13

GND_B1

09/02 Update Type-C Conn. DC 021608291 wei

312

D47

EMC_NS@

AZC199 -02S.R7G_SOT 23-3

ForESD

Tiiitle

3DCamera

Size Documenttt Number

Custttom

Dattt e:

28

GND525GND626GND727GND8

SSTXp1_A2
SSTXn1_A3

SSRXn2_ A10
SSRXp2_ A11

GND1031GND1132GND12

GND9

HIGHS_UB1 1246-15A0 C-1H

29

30

D20

C_TX1_ P_C

9

10

C_TX1_ N_C

8

C_RX2_ N_C

7

7

C_RX2_ P_C

6

6

Sunday, January 22,,,2017

GND_A1

VBUS_A4

CC1_A5

Dp1_A6

Dn1_A7
SBU1_A8

VBUS_A9

GND_A12

C_DP

C_DM

9

DG42A

ME@

1
2

3
4
5

6
7

8
9

10

11
12

312

D48

EMC_NS@

AZC199 -02S.R7G_SOT 23-3

1

1

2

2

4

4

5

5

3

3

8

Sheet 43 of 60

C_TX1_ P_C
C_TX1_ N_C

CC1
C_DP

C_DM

C_RX2_ N_C

C_RX2_ P_C

EMC_NS@

C_TX1_ P_C
C_TX1_ N_C

C_RX2_ N_C
C_RX2_ P_C

Re v

1.0

5 4 3 2 1

2

1

For ESD

PLT_RST#

1

CE1

220P_ 0201_25V7-K

EMC@

2

D D

W RST#

+3VL_EC

1

2

DE1

2

1

100K_ 0402_5%

RPE2

3

2

4

1

2.2K_0 404_4P2R_5%

RPE3

4

1

3

2

2.2K_0 404_4P2R_5%

4 H_PE CI

57,59 EC_V R_ON

1

2

@

2 1

100K_ 0402_5%

@

EC_ON

PM_SL P_S3#

10K_0 402_5% BK OFF#

RB751V -40_SOD323- 2

RE8

C C

+3VL_EC

+3VS

B B

+3VL

RE35 1 @ 2 10 K_0402_5% ON/ OFF
RE36

RE38

RE40 1 2 10K_0402_ 5% BKOFF#

For EMI

CLK_P CI_EC

7 KBR ST#

7,32 SE RIRQ

7,32 LPC_ FRAME#

7,32 LPC_A D3
7,32 LPC_A D2
7,32 LPC_A D1
7,32 LPC_A D0

7 CL K_PCI_EC

1

CE12

1U_0402 _6.3V6K

2

45 KSI[0. .7]

45 KSO[ 0..17]

EC_SM B_DA1
EC_SM B_CK1

EC_SM B_CK2
EC_SM B_DA2

RE58 2 @ 1 0_0 402_5%

RE24 1 2 43 _0402_5%

+3VL

DE2 1

@

11,37,40 PCIE_WAKE#

LID_SW #

RE2 1 2 33_ 0402_5%

EMC@

22P_0 402_50V8-J

RE56 2 @ 1 0_040 2_5%
RE59 2 @ 1 0_0402_5 %

RE60
RE61 1 @ 2 0_0402_ 5%

RE62 1 @ 2 0_0402_ 5%
RE63 1 @ 2 0_0 402_5%
RE64 1 @ 2 0_040 2_5%

9 EC_S MI#
40 EC_RX
40 EC_TX

11,32,37,40 PLT_RST#

4 EC_S CI#

KSI[0..7]

KSO[0. .17]

EC_SM B_CK1
EC_SM B_DA1

KSI7
KSI6
WR ST# PAD 1

For factory E C flash

45 ON/OFF

52,53 EC _SMB_CK 1
52,53 EC _SMB_DA 1

37 LAN_ PW R_ON#

7,39 EC_SMB_ CK2
7,39 EC_S MB_DA2

RE27 1 @ 2 0 _0402_5%

41 USB_ON#

11 DPW ROK_E C

11 EC_RSM RST#

11 AC_P RESENT

RE272 @ 0_0 402_5%

2

RB751V -40_SOD323- 2

CE2

EMC@

1

@ 2 0_0402_5 %

PAD 1 @

1

PAD
PAD 1
PAD 1

1

PAD

PAD 1

1

PAD

1 2

1

2

Change RE6 to 0ohm ju mp

LPC_FR AME#_EC 5SER IRQ/G PM6

LPC_A D3_EC LFR AME# /GPM5

LPC_A D2_EC

LPC_AD1 _EC
LPC_AD0 _EC

CLK_P CI_EC
W RST#

EC_RX
EC_TX
PLT_RST#

EC_R TCRST#_ON

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1

IT1

KSO2

@

IT2

KSO3

@

IT3

@

KSO4

IT4

KSO5

@

IT5

KSO6
KSO7
KSO8
KSO9

@

IT6

KSO10

@

IT7

KSO11

@

IT8

KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

ON/OFF
EC_SM B_CK1

EC_SM B_DA1
PECI_E C

EC_SM B_CK2
EC_SM B_DA2

USB_ON#

PCIE_W AKE#

Close EC

2

1

CE3

0.1u_0 201_10V6K

RE6 1 @ 20_0402 _5%

UE1

4

KBR ST#/ GPB6

6
7

LAD 3/GPM 3

8

LAD 2/GPM 2

9

LAD 1/GPM 1

10

LAD 0/GP M0

13

LPC CLK/G PM4

14

WR ST#

15

ECS MI#/ GPD4

16

PW UREQ# /BBO/ SMCLK 2ALT/ GPC7

17

LPC PD#/G PE6

22

LPC RST#/ GPD2

23

ECS CI#/ GPD3

126

GA2 0/GP B5

58

KSI0/S TB#

59

KSI1/A FD#

60

KSI2/IN IT#

61

KSI3/S LIN#

62

KSI 4

63

KSI 5

64

KSI 6

65

KSI7

36

KSO 0/PD 0

37

KSO 1/PD 1

38

KSO 2/PD 2

39

KSO 3/PD 3

40

KSO 4/PD 4

41

KSO 5/PD 5

42

KSO 6/PD 6

43

KSO 7/PD 7

44

KSO 8/AC K#

45

KSO 9/BU SY

46

KSO 10/P E

51

KSO 11/E RR#

52

KSO 12/S LCT

53

KSO 13

54

KSO 14

55

KSO 15

56

KSO 16/S MOSI/ GPC3

57

KSO 17/S MISO/ GPC5

110

PW RSW #

111

XLP _OUT

115

SMC LK1/ GPC1

116

SMD AT1/ GPC2

117

SMC LK2/ PECI/ GPF6

118

SMD AT2/ PECIR QT#/G PF7

94

CRX 1/SIN 1/SM CLK3/ GPH1/ ID1

95

CTX1/SO UT1/GPH2 /SMDAT3 /ID2

112

VSTBY0

125

GPE 4

33

GINT/CTS 0#/GPD5

35

RTS1#/G PE5

93

CLKRUN#/G PH0/ID0

2

CK3 2KE/ GPJ7

128

CK3 2K/GP J6

IT8586E- AX_LQFP 128_14X14

VCORE VCC

3

VBAT

Int.K/B
Matrix

12

VCORE

Clock

RE1

RE3 1 @ 2 0_06 03_5%

+3VS

11

265092

114

121

VCC

VSTBY1

VSTBY2

VSTBY3

VSTBY4

VSTBY5

LPC

IT8586E/AX
LQFP-128L

EXTERNAL SERIAL FLASH

SPI Flash ROM

SM Bus

WAKEUP

GPIO

VSS1

VSS2

VSS3

1

274991

for EC version update to EX, manual modify PN to FX

+3VL

GPG2

A A

GPG2

GPG2

when mirror, GPG2 pull high
when no mirror, GPG2 pull low

2

RE43

@ 1 10K_0 402_5%

2 1

RE44
RE46 2 @ 1 10K _0402_5%

+3VL_EC

SPI_SO

SPI_CLK

SPI_CS 0#

SPI_SI

SPI_CS 0# 7

SPI_SI 7

SPI_SO 7

SPI_CL K 7

NOVO#

10K_0 402_5%

5 4 3 2 1

EC_SP I_CS0#

EC_SP I_SI

EC_SP I_SO

EC_SP I_CLK

2

RE45

@ 10_0402_ 5%

2

RE47 @ 10_0402_ 5%

RE48 2 @ 1 0 _0402_5%

R E49 2 @ 1 0_0402_5 %

0_0603 _5%

+3VL_EC

+3VL_ EC_R

minim um trace wi dth 12 mil

74

127

AVCC

VSTBY(PLL)

PWM

PW M6/SS CK/G PA6
PW M7/RI G1#/ GPA7

ADC

DAC 2/TAC H0B/ GPJ2

DAC 3/TAC H1B/ GPJ3

DAC

DAC 4/DCD 0#/GP J4

PS2 CLK0/ TMB0 /CEC/ GPF0

PS2 DAT0 /TMB1 /GPF 1 87EC_SM B_CK3

PS2

UART

GPIO

DTR1#/S BUSY/GPG1 /ID7

TACH1A/ TMA1/GPD7

L80 HLAT/ BAO/ GPE0

AVSS

VSS4

VSS5

VSS6

75

113

122

EC_AGN D

1

CE48

0.01U_0201_10V6K

EMC_NS @

2

+3VL

+3VALW

All capacitors close to EC

@

1

1

CD@

2

0.1u_0 201_10V6K

CE6

PW M0/G PA0
PW M1/G PA1
PW M2/G PA2
PW M3/G PA3
PW M4/G PA4
PW M5/G PA5

TMRI0/GP C4
TMRI1/GP C6

ADC 0/GP I0
ADC 1/GP I1
ADC 2/GP I2
ADC 3/GP I3

ADC 4/GP I4
ADC 5/DCD 1#/GP I5
ADC 6/DS R1#/GP I6
ADC7/C TS1#/GPI7

DAC 5/RIG0#/ GPJ5

PS2 CLK2/ GPF4 90EC_LID_ OUT#
PS2 DAT2 /GPF5

GPH3/ID 3
GPH4/ID 4
GPH5/ID 5
GPH6/ID 6

LID_SW#

EGA D/GP E1
EGC S#/G PE2
EGC LK/G PE3

SSC E0#/ GPG2
SSC E1#/ GPG0

DSR 0#/GP G6

CRX 0/GP C0

CTX0/TMA 0/GPB2

RI1# /GPD 0
RI2# /GPD 1

TACH2/GP J0

TACH 0A/G PD6
L80 LLAT/G PE7

PECI_E C

BATT_TEMP

ACIN# EMC_ NS@ C E17 1 2 100P_02 01_25V8J

ON/OFF @ CE18 1 2 1U _0402_6.3V6 K

1

1

2

2

2

0.1u_0 201_10V6K

0.1u_0 201_10V6K

CE7

24

25

28

29

30
31
32

34

LAN_W AKE#

120
124

66

67

68

69

70
71

72

73

78
79

80

81

85
86

GPF2

88

GPF3

89

96
97
98
99

101

NC1

102

NC2

103

NC3

105

NC4

108 AC IN#

AC_ IN#

109

82

83

EC_VP P_PW REN

84

77

GPJ 1

100

106

104

107

119
123
18
21
76

48
47
19

20

53,59 VR_HO T#

EMC_NS @ CE15
EMC_NS @ CE16 1 2 100 P_0201_25V8 J

0.1u_0 201_10V6K

CE8

CE9

PWR _LED#

EC_VCC ST_PWR GD
EC_FAN _PWM
EC_VCC ST_EN_R

SUSP#

BATT_TEMP

B+_Trac k

0_0402_ 5% 1 @ 2 RE27 6

H_PROC HOT#_EC

EC_ON_ GPIO

EC_SM B_DA3

1

EC_SP I_CS0#

EC_SP I_SI

EC_SP I_SO
EC_SP I_CLK

LID_ SW#

GPG2

SYSON_R

RE271 1 @ 2 0_040 2_5% SYS ON

BKOFF#

EC_FAN _SPEED

RE34

2

1

47P_0 201_25V8-J

Security Clllassiiifiiication

Issued Date

THISII SHEE T OF ENGINEEII RINGII DRAWINGII ISII THE PROPRIEII TARY PROP ERTY OF LC FUTUR E CENTER... AND CONTAINSII CONFIDEII NTIAL
AND TRADE SE CRET INFOII RMATION... THISII SHEET MAY NOT BE TRANS FERED F ROM THE C USTOD Y OF THE C OMPE TENT DIVISIIII IOII N OF R&D
DEPARTMENT EX CEPT AS AUTHORIZII ED BY LC FUT URE CE NTER NE ITHER THISII SHEET NOR THE INFOII RMATION IT CONTAINSII
MAY BE USED BY OR DISII CLOSED TO ANY THIRDII PARTY WI THOUT PRIOII R WRITTEN CONSE NT OF LC F UTURE CE NTER.

@

1

1

2 2

CE11

CE10

TE1 @

H_PROC HOT#_EC

0.1u_0 201_10V6K

0.1u_0 201_10V6K

PWR _LED# 45
BATT_CHG_ LED# 45
BATT_LOW _LED# 45

EC_VCC ST_PWR GD 11
SYS_PW ROK 11
EC_FAN _PWM 39
BEEP# 30

SUSP# 46

NTC_V1 39

NTC_V2 39
BATT_TEMP 52,53

PM_SL P_SUS# 11

CPU_VR _READY 59

ADP_I 53

SUSW ARN# 11

SUSAC K# 11

ENBKL 33

0_0402_ 5% 1 @ 2 RE57

PBTN_OUT# 11
EC_SM B_CK3 55
EC_SM B_DA3 55

EC_LID_ OUT# 45

CAPS_ LED# 45
PCH_PW R_EN 46,55
EC_BK L_EN 45
PCH_PW ROK 11

LID_ SW# 45

VDDQ_P GOOD 55
EC_VP P_PW REN 55

EC_MUTE # 30

EC_CMO S_ON# 33

BKOFF# 33

PM_SL P_S3# 11,13
PM_SL P_S4# 11
NOVO# 45

EC_TS_O N 33

EC_FAN _SPEED 39

NUM_LE D# 45

1

2

@

0_0402_ 5%

RE267

100_040 2_5%

QE1

2

G

2N7002K W _SOT323-3

RE54 1 @

+3VS

2015/08/20 Deciphered Date

+3VL_EC+3VL_EC

EC_VCCS T_EN

2

0_0402_ 5%

+3VL_EC

PSYS 53,59

1

2 @ 1

0_0402_5 %

RE55

TE3@ 1

1

CE14
47P_0201_25V8-J

EMC_NS @

2

13

1 2

D

S

11 ACIN#

1

CE19

0.1u_0 201_10V6K

2

LC Future Center Secret Data

LE1 1 @ 2 0_060 3_5%

0.1u_0 201_10V6K

LE

2 1 @ 2 0_0603 _5%

RE65
100K_ 0402_5%

2

1

TE2 @

EC_VC CIO_EN

H_PROC HOT# 4,55

ACIN#

CE4

EC_AGN D

EC_VCC ST_EN 13

EC_ON 39,54,55

+3VL

RE42
100K_ 0402_5%

RE262 1 @ 2 0_040 2_5%

1 1

2

D

QE2

2

G

S

2N7002K W _SOT323-3

@

3

2016/08/20

1

2

EC_AGN D

ME_FLA SH 8
SYSON 55

EC_VCC IO_EN 13

+3VL_ EC_R

1

CE5

1000P_0201_50V7-K

2

EC_FAN _SPEED
EC_FAN _PWM

LPC_FRA ME#

ENBKL
CPU_VR _READY

EC_CMOS _ON#
EC_LID_ OUT#

+3VL_EC

LAN_W AKE#

1

RE10

RE11 1 @ 2 10K_0 402_5%

RE7 1 @ 2 10K_0 402_5%
RE9 1 @ 2 100K_ 0402_5%
RE 2701 2 10K_0402 _5%

RE275 1 @ 210K_0 402_5%
RE277 1 @ 210K_0 402_5%

For PMI C

EC_SM B_DA3

EC_SM B_CK3

USB_ON#

SUSP#
SUSP#

SYSON_R
EC_VCCS T_EN
EC_VC CIO_EN

EC_R TCRST#_ON

100K_ 0402_5%

RPE4

1 4

2

2.2K_0 404_4P2R_5%

1

RE15

RE18 1 @ 2 100 K_0402_5%
RE19 1 2 100 K_0402_5%
RE21 1 2 100 K_0402_5%

1

RE269

RE268 1 @ 2100K_ 0402_5%

Add to fix Reset&PWRGD test fail issue

VDDQ_P GOOD

PM_SL P_S4#

PM_SL P_S3#

SYSON CE 13 1 2 EMC_NS@ 10 00P_0201_ 50V7-K

1 2

PM_SL P_S4#

2

G

RE50

@

2

1

ACIN 53

Title

EC ITE8586LQFP

Size DocumentttNum ber

C

Sunday, ,, Ja nua ry 22,,, 2017

Dattte:

V20B+

RE261
470K_ 0402_5%

@

2

1

B+_Track

R260
47K_0 402_5%

@

2

RE5
10K_0 402_5%

2

1

RE273 RE274

0_0402_ 5% @ 0_0 402_5%

3

@ 2 100K_ 0402_5%

2

1

CE51 0. 01U_0201_10 V6K

1 2

CE50

1 2

CE21

1

LAN_W AKE# 37,40

+3VS

2

10K_0 402_5%

+3VALW +3 VL_EC

@

2 12

1

+5VALW

2

100K_ 0402_5%

+3VL_EC

EMC_NS @ 1000 P_0201_50V7-K

EMC_NS @ 1000 P_0201_50V7-K

EMC Request

DE3
RB751V -40_SOD323- 2

@

EC_RTC_ RST# 10

1

D

QE3

S

2N7002 KW_SOT32 3-3

@

3

DG42A

Sheet 44 of 60

R ev

1.0

5

ON/OFF switch Novo button

100K_0402_5%

44 NOVO#

D D

2 @

J5 1

SHORT PADS

J6 1

2 @

SHORTPADS

+3VL

2

R82

1

NOVO#

ON/OFF

R85 1 @ 2 0_0402_5% 3

R119 1 @ 20_0402_5%

+3VALW

2

R83
100K_0402_5%

@

1

R261 1 @ 20_0402_5%

2

D15

BAT54CW_SOT323-3

+3VALW

R111
100K_0402_5%

@

1 2

ON/OFFON/OFFBTN#

4

NOVO_BTN#

1

@

+3VL

R114
100K_0402_5%

1 2

ON/OFF 44

8/16 Del Power Button wei

ON/OFFBTN#

1

D25

2 1

EMC@

2

AZ512 3-01 F.R7GR _DFN10 06P2X 2

3

2

SW2

NTC325-EKJ-A160T_3P

1

3

2

4
5

NOVO_BTN#

1

D24

1

AZ5123-01F.R7GR_DFN1006P2X2

EMC@

2

2

1

8/31 Update the P/N SN 100008W 00 w ei

LID switch

1

C1105

0.01U_0201_10V6K

R264 1 @2

+3VL

0_0402_5%

2

+VCC_LID

2

OUTPUT

VCC

AH9247-W-7_SC59-3

U14

1

GND

1

C1104
100P_0201_25V8J

2

3

LID_SW#

LID_SW#44

K/B Connector

EMC_NS@

PWR_CAPS_LED

1

2

C133

100P_0201_25V8J

EMC@

2

100P_0201_25V8J

C117 1

NUM_LED#_R

C C

1

2 100P_0201_25V8J

C118

15@

EMC_

CAPS_LED# NUM_LED#_R

1

D22
AZ5123-01F.R7GR_DFN1006P2X2

EMC@

2 1

2

1

D23
AZ5123-01F.R7GR_DFN1006P2X2

EMC_15@

2 1

2

Finger Print Connector

+3VS

R3120 1 @ 20_0402_5%

USB20_N4_CONN

B B

USB20_P4_CONN

312

KSI[0..7]

KSI[0..7] 44

KSO[0..17]

KSO[0..17]44

44 NUM_LED#

PWR_LED#

R279 1 15@ 2 0_0402_5%

KSO17 R281 1 15@ 2 0_0402_5%
KSO16 R280 1 15@ 20_0402_5%

R285 1 @ 2 0_0402_5%

8/23 PWR LED fun ction under che ck

PWR_LED#

1

D46
AZ5123-01F.R7GR_DFN1006P2X2

EMC@ 44 CAPS_LED#

2 1

FP_PWR

0.1u _0201 _10V6 K

1

2

C206 1

9 USB20_N4
9 USB20_P4

FP@

2

USB20_N4 USB20_N4_CONN

1 2

R3122 1 @ 2 0_0402_5%

USB20_P4

R3121 @0_0402_5%

For EMC

DT2

FP@

CAPS_LED#

R275 1 @ 2 0_0402_5%

R841

+3VALW

200_0402_1%

To be co nfir m P in d efin e

1

USB20_P4_CONN

2
3
4
5
6
7
8

9

10

HIGHS_FC5AF081-2931H

8/23 Update F G Con n. P/N SP0100 1YV00 w ei

ON/OFFBTN#

NUM_LED#_R

KSO17_R

KSO16_R

KSI1
KSI7
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0

KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15

CAPS_LED#_R

PWR_CAPS_LED

2

JFP1

1
2
3
4
5
6
7
8

GND1
GND2

JKB1

32

32 GND1

31

31GND2

30

30

29

29

28
27

28

26

27

25

26

24

25

23

24

22

23

21

22

20

21

19

20

18
17

19

16

18

15

17

14

16

13

15

12

14

11

13

10

12

9

11

8

10

7

9

6
5

8

4

7

3

6

2

5

1

4
3

CVILU_CF32321D0RONH

2

ME@

1

KB Backlight Connector

33
34

44 EC_BKL_EN

TP/B Connector

TP_I2C_SCL0
TP_I2C_SDA0

EC_BKL_EN

0.1u_0201_10V6K

KBL@

312

1

C1109

2

R141 1 @ 20_0402_5%

DT1

EMC_NS@

10K_0402_5%

+5VS

+5VALW

R265

KBL@

2 1

1 2

100K_0402_5%

KBL@

1

D

2

Q32

G

2N7002KW_SOT323-3

KBL@

S

3

Q31
LP2301ALT1G_SOT23-3

KBL@

D

S

13

G

R266

2

10U_0603_6.3V6M

1

C1108

0.01U_0201_10V6K

KBL@

2

C1106

KBL@

+VCC_KB_LED

1

2

0.1u_0201_10V6K

@

+VCC_KB_LED

1

C1107

0.1u_0201_10V6K

KBL@

2

C1110

1

2

To be co nfir m P in d efin e

JKBL1ME@

1

1

2

2

3 6

3 GND2

4

4 GND1

CVILU_CF50041D0RN-10-NH

5

8/31 Update K BL Co nn. P/N SP0116 0824 1 wei

TP_PWR+3VS

1

44 EC_LID_OUT#

8 PCH_TP_INT#

2

C114

8 TP_I2C_SDA0

0.1u _0201 _10V6 K

8 TP_I2C_SCL0

R4675 1 @ 2 0_0402_5%

1 2

R4676 @ 0_0402_5%

1

2 2

EMC _NS @

C115

C116

100P_0201_25V8J

EC_LID_OUT#_R

TP_INT#

TP_I2C_SDA0
TP_I2C_SCL0

TP_PWR

1

EMC _NS @

100P_0201_25V8J

JTP1ME@

1

1

2

2 GND1

3

3

4
5

4 GND2

6

5
6

ELCO_04-6809-606-110-846-+

7
8

11/16 SIT change t o 6Pin I2C int erface T/P wei

AZC199-02S.R7G_SOT23-3

9/7 Add f or ESD w ei

BATT_LOW_LED#

1

44 BATT_LOW_LED#

44 BATT_CHG_LED#

A A

44 PWR_LED#

1

1

2

BATT_CHG_LED#

1

2 1

PWR_LED#

2

2

LED2

D18
AZ5123-01F.R7GR_DFN1006P2X2

EMC_NS@

D19
AZ5725-01F.R7GR_DFN1006P2X2

EMC_NS@

PWR_LED Chang e to M/ B (31 0->320) 08/17

5

2

L-C192JFCT-LCFC_SUPER_AMBER

2

LED3 1

L-C192WDT-LCFC_WHITE

2

LED41

L-C192WDT-LCFC

R1431 2 470_0402_5%

R1441 2 1.5K_0402_5%

R46721 2 1.5K_0402_5%

+3VALW

+5VALW

+5VALW

PWR_LED#

1

D16
AZ5725-01F.R7GR_DFN1006P2X2

EMC_NS@

2 1

2

4

3

For EMC

Securrritttii y Clllassifffiiicii atttion

IIIssued Date

THISII SHEET OF ENGINEERII INGII DRAWINGII ISII THE PROPRIETII ARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENIITIAL
AND TRADE SEC RET INFORMII ATION.IITHISII SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISIONII OFR&D
DEPARTMENT EXCEPT AS AUTHORIZEDII BY LC F UTURE CENTER NEITII HER THISII SHEET NOR THE INFORMII ATIONII ITII CONTAINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF LC FUTURE CENTER.

AZC199-02S.R7G_SOT23-3

LC Future Center SecretData

2015/08/20 Deciiipherrred Date 2016/08/20

2

Tiiitttle

KBD/ PWR/ IO/L ED/TP Conn.

Size DocumentttNumber

Custttom

Dattte:

Sunday,,, Januarrry 22,,,2017

DG42A

1

onn.onn
.

Sheet 45 of60

Rev

1.0

A

B

C D E

Load Switch
+5VALW To +5VS
+3VALW To +3VS

1

C179

1U_0402_6.3V6K

2

PCH_PW R_EN#

PCH_PW R_EN

100K_0402_5%

3VSON

R162

@

+5VALW

1

C177

2

1

C178
1U_0402_6.3V 6K

2

@

1

R155
100K_0402_5%

@

2

13

D

S

2N7002KW_SOT 323-3

1U_0402_6.3V6K

+3VALW

+5VALW

Q30

2

G

@

1

2

+5VALW

22U_0603_6.3V6-M

R64

1 @ 2 0_0402_ 5%

1 1

2 2

3 3

R27 1 @ 2 0_0402_5%

SUSP# 5VSON

1

C180

1U_0402_6.3V6K

PCH_PW R_EN#_R

44,55 PCH_PW R_EN

R158 1

2

@ 2 100K_0402_5%

+3VS, C173 --> 2.74ms
+5VS, C176 --> 2.03ms

VIN 5V and 3.3V (VBIAS=5V), IMAX(per channel)=6A, Rds=16mohm

5VSON

3VSON

Change the main source to SA000067600 (GMT) 7/16

C1103

U13

1 14

2
3
4
5
6

7

G5016KD1U_T DFN14_2X3

1

@

2

PCH_PW R_EN#_R

OUT1_2

IN1_1

OUT1_1

IN1_2
EN1
VBIAS
EN2

IN2_1
IN2_2

CT1

GND

CT2

OUT2_2
OUT2_1

GPAD

+3VALW +3VALW _PCH

1

R87
100K_0402_5%

@

2

+5VS_LS

13

12 C176 1 2 1000P_0201_50V7-K
11
10 C173 1 2 2200P_0402_25V7-K

+3VS_LS

9
8

15

Need short

J7 @

1

2

1 2

JUMP_43X 79

LP2301ALT1G_ SOT23-3

D

S

Q29 3 1 @

G

2

1

C131

0.1u_0201_10 V6K

@

2

Need Short

J12 @

1

2

1 2

JUMP_43X118

J11 @

1

1 2

JUMP_43X118

Need Short

Id=3.2A

1

C130

0.01U_0201_1 0V6K

@

2

+5VS

0.1u_0201_1 0V6K

2

1

C174

@

2

SUSP R201 1 @ 2 0_0402_5 %

+3VS

1

C175

0.1u_0201_1 0V6K

@

2

+5VALW

1

C2078

0.1u_0201_10 V6K 0.1u_0201_10V6 K 0.1u_0201_10V6K

@ @ @

2 2 2

+1.8VALW +1.8VS

1

0.1u_0201_10 V6K

C201

2

R202

@ 470K_0402_5%

2

1

Q35

S

3

LP2301AL T1G_SOT23-3

G

2

1

2

1

C2080

0.6A

D

1

0.1u_0201_10 V6K

C202

+3VALW

1

1

0.1u_0201_10 V6K

C203

2

1

0.1u_0201_10 V6K

C204

2

8/29 Add +1.8VS Circuit for Audio wei

C2079

1

2

EMC

0.1u_0201_10V6K

C205

+5VLP +5VALW

1

1

2

G

Q10

R157
100K_0402_5%

@

2

13

D

S

2N7002KW_SOT 323-3

08/29: Need double check enable signal and the resistance

R156

100K_0402_5%

2

34 SUSP

44 SUSP#

4 4

SUSP

+0.6VS

1

R159
47_0603_5%

@

1 2

D

Q11

2 SUSP 2 SUSP

G G

S

2N7002KW_SOT 323-3

3

@

Security Classification LC Future Center Secret Data

Issued Date

THIIIS SHEET OF ENGIIINEERING DRAWIIING IIIS THE PROPRIE TARY PR OPERTY OF LC FUTURE C ENTER. A ND CONTAIIINS CONFIDENTIIIAL
AND TRAD E SEC RET IIINFORMATIIION... THIIIS SHEE T MAY NOT BE TRAN SFERED FROM THE CUSTOD Y OF THE COMP ETENT DIVIIISIIION OF R& D
DEPAR TMENT EXCE PT AS AUTHORIZE D BY L C FUTURE CENTER NEIIITHER THIIIS SHEET N OR THE IIINFORMATIIION IIIT CONTAIIINS
MAY BE USED BY OR DISCLO SED TO A NY THIRD PARTY WIIITHOUT PRIO R WR ITTEN CONSEN T OF LC FUTU RE CE NTER.

A

B

C D

For DisCharge

2015/08/20 DecipheredDate

+2.5V_DDR

1

R278
200_0402_5%

@

1 2

D

Q33

S

2N7002KW_SOT 323-3

3

@

2016/08/20

Title

DC V TO VS INTERFACE

Siiize Document Number

Custom

DG42A

CEC
E

46 of 60Date: Su nd ay , J an ua ry 22, 2017

Sheet

E

R ev

1.0

5 4 3 2 1

EMC@

HCB2012KF-121T 50_0805

JDCIN1

1

1

2

GND 1

3

GND 2

4

GND 3

5

GND 4

6

D D

C C

GND 5

7

GND 6

HIGHS_PJ SS0026-8 B01H

ME@

VCCRTC

@

PC105
1U_0402_6.3V6K

1 2

PF101

1

ADPIN

7A_24VDC_F1206HI7000V02 4TM

1

PD101

BAT54CW _SOT323-3

RTC_VCC 2 0MIL
+3VL 20MIL
VCCRTC 20 MIL

2

APDIN_F

2

3

EMC@ PC102

470P_0201_50V7-K

2 1

+3VL

1

1 22

2 PR101 1

1K_0603_5%

PR102

1.5K_0402_1%

PR103

45.3K_0402_1%

1 2

EMC@ PC101

1000P_0201_50V7-K

PL101

1 2

EMC_NS@

HCB2012KF-121T 50_0805

PL102

1 2

RTC_VCC

1

2

3
4

HIGHS_W S33020-S0351-HF

1
2

3
4

HIGHS_W S33020-S0351-HF

JRTC1

1
2
GND 1
GND 2

ME@

JRTC2

1
2
GND 1
GND 2

ME@

VIN

1 2

2 1

1000P_0201_50V7-K

EMC@ PC104

EMC@ PC103

470P_0201_50V7-K

B B

No charge RTC with 35mm cable

RTC Battery for GCM BOM

(2nd source and quoted price )

A A

Security Classification

IssuedDate

THIIIS SHEET OF ENGIIINEERING DRAWIIING IIIS THE PROP RIETARY PROPE RTY OF LC FU TURE C ENTER. AND CONTAIIINS CONFIDENTIIIAL
AND TRAD E SEC RET IIINFORMATIIION... THIIIS SHEE T MAY NOT BE TRAN SFERED FROM THE CUSTOD Y OF THE COMP ETENT DIVIIISIIION OF R& D
DEPAR TMENT EXCE PT AS AUTHORIZE D BY L C FUTURE CENTER NEIIITHER THIIIS SHEET N OR THE IIINFORMATIIION IIIT CONTAIIINS

5 4 3 2

MAY BE USED BY OR DISCLO SED TO A NY THIRD PARTY WIIITHOUT PRIO R W RITTEN CONSEN T OF LC FUTU RE CE NTER.

2015/08/20

LC Future Center Secret Data

Deciphered Date

2016/08/20

Title

PWR-DCIN / RTC charger

Siiize Document Number

Custom

Date: S un da y, J an ua ry 22, 2017 Sheet 51 of 60

erer

DG42A

1

R ev

1.0

5 4 3 2 1

D D

C C

B B

JBATT 1

1
2

9

GND 1 3

10

GND 2 4

5
6
7
8

ME@

SUYIN_125022HB 008M202ZL

VBAT

1
2

EC_SMCA

3

EC_SMDA

4
5

6
7
8

1

1

2

3

BATT_TEMP_IN

PD202

AZ5215-01F_DFN1 006P2E2

EMC_NS@

2

2

AZC199-02S.R7G_ SOT23-3

1

EMC_NS@

PR209

1 2

100K_0402_1%

PR213

1 2

10K_0402_5%

PD201

PR202 1

PR201

2100_0402_1%

1

2

100_0402_1%

+3VALW

BATT_TEMP 44,53

EC_SMB_CK 1 44,53
EC_SMB_DA 1 44,53

1 2

EMC@

HCB2012KF-121T 50_0805

PL201

1 2
1 2

PL202

HCB2012KF-121T 50_0805

EMC@

PC201 PC202

1000P_0201_ 50V7-K

EMC@ EMC@

BATT+

0.01U_0201_25 V6-K

2 1

2S1P polymer battery
voltage level: +6V ~

8.4 V

A A

Security Classification

IssuedDate

THIIIS SHEET OF ENGIIINEERING DRAWIIING IIIS THE PROP RIETARY PROPE RTY OF LC FU TURE C ENTER. AND CONTAIIINS CONFIDENTIIIAL
AND TRAD E SEC RET IIINFORMATIIION... THIIIS SHEE T MAY NOT BE TRAN SFERED FROM THE CUSTOD Y OF THE COMP ETENT DIVIIISIIION OF R& D
DEPAR TMENT EXCE PT AS AUTHORIZE D BY L C FUTURE CENTER NEIIITHER THIIIS SHEET N OR THE IIINFORMATIIION IIIT CONTAIIINS

5 4 3 2

MAY BE USED BY OR DISCLO SED TO A NY THIRD PARTY WIIITHOUT PRIO R W RITTEN CONSEN T OF LC FUTU RE CE NTER.

2015/08/20

LC Future Center Secret Data

Deciphered Date

2016/08/20

Title

PWR-BATTERY CONN/OTP

Siiize Document Number

Custom

Date: S un da y, J an ua ry 22, 2017 Sheet 52 of 60

OTPOTP

DG42A

1

R ev

1.0

5 4 3 2 1

AON6414AL _DFN8-5

PQ311

VIN

D D

PR313 PR 315 :432K a nd 64. 9k

change t o 43k and 7.15k.

vin dete ct volatege level:16.8V

C C

B B

PC309:0. 1u change t o 0.01u
decrease ACDET deas sert time

5

PC301

2 1

470P_0201_50V7-K

44 ADP _I

2 14

2

1

PR302

4.7_06 03_5%

PR310

1
2
3

1

2

4.02K_0603_1%

N1

PR311

4.02K_ 0603_1%

44 ACIN

44,52 EC _SMB_DA 1

44,52 E C_SMB_C K1

1 2

1 2

PC324

100P_0201_25V8J

2 1

7.15K_ 0402_1%

1

PR315

1

0.01U_0402_25V7K

BQ2478 0_VDD

PC325

100P_0201_25V8J

PQ312

AON740 8L_DFN8-5

1
2
3

PC302

0.022U_0402_25V7K

4

N2

PJ301 @

5

JUMP_43X118

1

2

1 2

PC303

1 2

10U_0603_25V6-M

EMC_NS @

1U_0603_ 25V6K

1 2

1

PC307

PR301

0.01_1 206_1%

1

4
3

2

PC304

EMC_NS @

0.1U_0201_2 5V6-K

10U_0603_25V6-M

PC305

2

1

2

2

PC306

0.1U_0 201_25V6-K

1

2 1

2 1

220P_0402_50V7K

EMC @ PC329

2 1

470P_0402_50V7K

EMC @ PC330

680P_0402_50V7K

EMC @ PC331

VIN BATT+

3

2

PD302

BAT54CW_SOT323-3

1U_0603_ 25V6K

2 1

ACDET

EC_SM B_DA1_R

EC_SM B_CK1_R

PR331

PC315

ADP_I_R

ILIM_R

1 2

1

PR314

10_1206 _5%

1 2

780_V CC

ACIN_R

PC328

0.1U_0201_25V6-K

28

11

12

10

13 C MPIN

14 C MPOU T

ILIM 21

PR330
0_0402_ 5%

@

1

2

1

PR333
100K_ 0402_1%

2

ACN

ACP

2

1

ACP

VCC

6

ACD ET

3 26

CMS RC HIDRV

4

ACD RV

5

ACOK
SDA

SCL

7

IADP

8

IDCHG

9

PMO N

PROCHOT#

ILIM

1

14.7K_ 0402_1%
PR332

ACN

BQ2478 0SRUYR_QFN2 4_4X4

PHA SE

PU301

LODR V

BATDRV

BATS RC

TB_STAT#

BATPRES#

16

15

TB_STAT#

2

REG N

BTST

GND

PAD

SRP

SRN

BQ24780_VDD

24

2.2U_0 603_10V6-K P C316

BST_CHG

25

DH_CHG

LX_CHG

27

DL_CHG

23

22

29

BQ2478 0_BATDRV

18

17

SRP_R

20

SRN_R

19

BATT_TEMP 44,52

1 2

PR316 PC318

1 2 2

2.2_06 03_5%

0.047U _0603_16V7K

2
2

PR328

2

PR329

1

PR338 10_0 603_5%

1

1

10_0603 _5%

1

10_0603 _5%

PQ317 4

AON740 8L_DFN8-5

4

1 2

VIN

1

PR313

43K_0 402_1%

2

2

PC309

100K_ 0402_1%

0_0402_5%1 2 PR325 @

0_0402_ 5%1

0_0402_ 5%1 PC321

0_0402_ 5%1 2 PR32 3@

IDCHG

59 Ps ys

PR340

20K_0 402_1%

2 PR324 @1

2

1

+3VALW

2

2

PR339 @120K_0402_1%

2

PR320 @

2

PR322 @

44,59 VR _HOT#

@

1 2

PC1108

100P_0201_25V8J

1 2

316K_ 0402_1%

5

321

5

321

PC327

0.1U_0201_25V6-K

2 1

EMC @ PC332

4700P_0402_50V7-K

PQ316

AON740 8L_DFN8-5

1 2

1

PR321

2.2_08 05_5%

EMC_NS@

1000P _0402_50V7K

2

2 1

2 1

EMC @ PC333

6800P_0402_25V7-K

BQ2478 0_BATDRV

PC313

1 2

1 2

EMC @ PC310

2200P_0201_25V7-K

PL302

1 2 CHG

4.7UH_ PCMB053T-4R 7MS_4A_20%

EMC_NS@

SRP

SRN

EMC @ PC334

0.01U_0201_25V6-K

499K_ 0402_1%

1 2

10U_0805_25V6K

1 2

PR303

V20B+

PC314

10U_0805_25V6K

PR317

0.01_1 206_1%

1
2

PC322

0.1U_0201_25V6-K

V20B+

5

PQ314
AON6324_DFN8-5

4

321

PC308

0.01U_ 0201_25V6-K

1 2

2

1

4

3

1 2

PC323

1 2

0.1U_0201_25V6-K

BATT+

PC319

1 2

PC320

10U_0805_25V6K

10U_0805_25V6K

A A

Security Clllassiiifiiication

Issued Date

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPE RTY OF LC F UTURE CENTER... AND CONTAIIINS CONFIIIDENTIAL

AND TRADE SE CRET IIINFORMATION... THIIIS SHEET MAY NOT BE TR ANSFE RED FR OM T HE CU STODY OF T HE CO MPETE NT DIIIVIIISIIION OF R &D
DEPARTMENT EX CEPT AS AUTHORIIIZED BY LC FUT URE CE NTER NEI THER THIIIS SHEET NO R THE IIINFORMATION IT CONTAIIINS

5 4 3 2

MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WI THOUT PRIIIOR WRITTEN CONS ENT OF LC FUTURE CE NTER.

2015/08/20

LC Future Center Secret Data

Deciphered Date

2016/08/20

Title

PWR-CHARGER

Size Documenttt Number C R ev

Dattte: Sheet 53 of 60

DG42A

Sunday, ,, Ja nua ry 22,,, 2017

1

1.0

5 4 3 2 1

+3VALW

PR407 @

V20B+

@

PJ401

1

2

2 1

JUMP_43X79

D D

PR414 @

EC_ON

39,44,55 EC_ ON

1 2

0_0402_ 5%

2 1

EMC @ PC401

0.01U_0201_25V6-K

+3/5V ALW_EN

+3/5V ALW_EN

2 1

2 1

PC452

PC402

10U_0805_25V6K

10U_0805_25V6K

PR415 @

1 2

0_0402_ 5%

+3V_VIN

@

PC408

2 1

2

0.1U_0201_25V6-K

PU401

+3V_VIN

5
4
3
2

7

8
18
21

+3VALW _EN

12

11
10

15
16

1

PR401

1M_0402_5%

+3VLP +3VL

IN1
IN2
IN3
IN4

GND1
GND2
GND3

EN2
NC1

NC2

GND4

NC3

EN1

@

PJ404

2

2 1

JUMP_43X39

PG
BS

LX1
LX2
LX3

OUT

SY8286BRAC_QFN20_3X3

LDO

1

FF

9

1

+3VBS 1 2

6

19
20 +3VL X

14
13

17

+3V_PW RGD

PC403

0.1U_0603_2 5V7-M

10 0mA

+3VALW _P

+3VALW _FB

+3VLP

2 1

100K_ 0402_5%

1

2

2.2UH_ PCMB053T-2R 2MS_5.5A_20%
PL401

1

2

PR403

2.2_08 05_5%

EMC_NS @

1 2

1

PC410

1000P_0402_50V7K

EMC_NS @

2

PC409

4.7U_0603_6.3V6K
PC411

2

1

1000P _0201_25V7K

2 1

2 1

PC434

PC432

22U_0603_6.3V6-M

PR405

1

1K_04 02_1%

+3VALW _P

2 1

2 1

PC435

PC431

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

2

2

JUMP_43X79

PJ402

+3VALW

@

5A

1

2 1

Vou t=3. 3V± 5%

Vse t=3. 37V± 1.5%
OCP=12A
OVP= (1.1 5~1 .25 )* Vou t
UVP= (0.5 5~0 .65 )* Vou t

Fsw=600Khz

C C

V20B+

+3/5V ALW_EN

B B

A A

@

PJ405

2

1

2 1

JUMP_43X79

PU402

+5V_V IN

5

IN1

4

IN2

3

IN3

2

PC413

2 1

EMC @ PC412

0.01U_0201_25V6-K

@

2 1

PC414

2 1

2 1

10U_0805_25V6K

10U_0805_25V6K

+5V_VIN

PC421

PR412

1M_0402_5%

2 1

0.1U_0201_25V6-K

IN4

7

GND1

8

GND2

18

GND3

21

GND4

12

EN1

11 13

EN2

10

NC1

16

NC2 VCC

SY8288 CRAC_QFN20_ 3X3

ALW _PW RGD

9

PG

1 + 5VBS

BS

6

LX1

19

LX2

20

LX3

14

OUT

FF

15

LDO

17 +5 VVCC

+5VALW _OUT

PC415

0.1U_0 603_25V7-M

2 1

PC416

1U_0603_25V6M

1 2

+5VLX

1 2

0_0402_ 5%

PR410 @

2 1

PC422

4.7U_0603_6.3V6K

+3VALW

2

1

+5VALW _P

+5VLP

10 0mA

PR406 @
100K_ 0402_5%

ALW _PW RGD 55

PL402

1 2

2.2UH_ PCMB063T-2R 2MS_8A_20%

1

PR411

2.2_08 05_5%

EMC_NS @

PC423

1000P_0402_50V7K

2 1 2

EMC_NS @

PC424

2

+5VFB 1

1000P _0201_25V7K

2 1

PR413

1

1K_04 02_1%

PJ406

+5VALW _P

2

2 1

2 1

2 1

2 1

PC418

PC417

22U_0603_6.3V6-M

2

PC420

PC419

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

JUMP_ 43X79

+5VALW

8A

1

@

Vout =5V± 3%
Vset =5.1V ± 1. 5%

OCP=12A
OVP= (1.1 5~1 .25 )*V out

UVP= (0.5 5~0 .65 )* Vou t

Fsw=600Khz

Security Clllassiiifiiication

Issued Date

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPE RTY OF LC F UTURE CENTER... AND CONTAIIINS CONFIIIDENTIAL

AND TRADE SE CRET IIINFORMATION... THIIIS SHEET MAY NOT BE TR ANSFE RED FR OM T HE CU STODY OF T HE CO MPETE NT DIIIVIIISIIION OF R &D
DEPARTMENT EX CEPT AS AUTHORIIIZED BY LC FUT URE CE NTER NEI THER THIIIS SHEET NO R THE IIINFORMATION IT CONTAIIINS

5 4 3 2

MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WI THOUT PRIIIOR WRITTEN CONS ENT OF LC FUTURE CE NTER.

2015/08/20

LC Future Center Secret Data

Deciphered Date

2016/08/20

Title

PWR_3VALW/5VALW

Size Documenttt Number C R ev

Dattte: Sheet 54 of 60

DG42A

Sunday, ,, Ja nua ry 22,,, 2017

1

1.0

5

D D

@

2

EC_VPP_PWREN

PR501 1

0_0402_5%

PR503 1

0_0402_5%

PR504 1

0_0402_5%

PR506 1

0_0402_5%

1M_0402_5%

PR508 1

0_0402_5%

PR507 2

@

2

@

2

@

2

+1.8VALW_B_EN

1

@

+2.5V_DDR_EN

2

0.1u_0201_10V6K

44 SYSON

5 CPU_DRAMPG_C NTL

44,46 PCH_PW R_EN

44 EC_VPP_PWREN

C C

B B

4

PR521 1 2

PMIC_VCC

0_0402_5%

+5V ALW

2

VDDQ_P

PJ508 @ 1

2 1

1

PC510

2 1

22U_0603_6.3V6-M

+2.5V_DDR_VIN

1

21

PR520

1

10_0603_5%

PR505

10_0402_5%

+2.5V_DDR_EN
+1.8VALW_L_EN
+1.0VALW_EN
+1.8VALW_B_EN

+1.0VALW_B_VIN

2 1

PC509

21

PC521

2

10U_0603_10V6K

+1.8VALW_L_VIN

PC523
10U_0603_10V6K

PR502 @

1

10_0603_5%

2

2

VDDQ_EN
VTT_EN

0.1u_0201_10V6K

EMC_NS@

+1.2V_P

PC519

22U_0603_6.3V6-M

1

2

PC500

1

2

2.2U_0603_6.3V6K

PC502

0.1u_0201_10V6K

1 2

PU500

29

EN_LDO1

1

EN_LDO2

11

EN_V1P0A

16

EN_V1P8A

31

EN_VDDQ

36

EN_VTT

7

VIN_V1P0A_7

8

VIN_V1P0A_8

VIN_V1P8A_1919LX_V1P8A_18

38

VIN_VTT

39

VTT

40

VSNS_VTT

30

CS_VDDQ

5

VIN_LDO1

4

VIN_LDO2

PMIC_EN

VSYS_PMIC

28

27941

VCC

GN

D

VSYS

SDA

PMIC_EN

SCL
T_ALERT_B
POK_V1P0A
POK_V1P8A
POK_VDDQ

LX_V1P0A_12
LX_V1P0A_13
LX_V1P0A_14
LX_V1P0A_15

VO_V1P0A

LX_V1P8A_17

LV5028RPC_VQFN40_5X5

VO_V1P8A_20

UGATE_VDDQ

BOOT_VDDQ

PHASE_VDDQ
LGATE_VDDQ

VSNS_VDDQ

LDO1

LDO2

FB_LDO2

VDDQ_EN

VTT_EN

+1.8VALW_L_EN

+1.0VALW_EN

PC506

PC504

@

PC507

1 2

1 2

@

@

0.1u_0201_10V6K

0.1u_0201_10V6K

+5V LP

PC503

PC508

1 2

1 2

1 2

@ @

0.1u_0201_10V6K

0.1u_0201_10V6K

2A

+5V ALW

PJ500 @ 1

2

2 1

JUMP_43X39

PC517 1 2 10U_0603_10V6K

+0.6VS

2A JUMP_43X39 PR515 @

1 2

33K_0402_1%

1A

PJ502 @

2

2 1

+3V ALW

JUMP_43X39

600mA

PJ504 @ 1

2

2 1

+3V ALW

JUMP_43X39

0_0402_5%

1

25
26
24
22
21
23

12

13
14
15

10

17

18

20

33
32

34
35
37

6

3

2

PR517
75K_0402_1%

PR522

2

BST_VDDQ

@

@

PMIC_SMB_DAT1
PMIC_SMB_CLK1

PMIC_ALERT#

+1.0VALW_PG
+1.8VALW_B_PG

VDDQ_PGOOD

LX_1P0

+1.0VALW_FB

UG_VDDQ

LX_VDDQ

LG_VDDQ

+1.2V_P

+2.5V_P

1 2

PC520 22U_0603_6.3V6-M

2

PR516

1

+1.8VALW_L_FB

1 2

3

ALW_PW RGD 54

PR510 1

0_0402_5%

1

PR511

0_0402_5%

2

PR512 1 @ 0_0402_5%

1 PAD @ PTC501
1 PAD @ PTC502

PL500

1

0.47UH_CMMB062D-R47MS_15A_20%

PR1031 PC518

2 2 1

1

0_0603_5% 0.1U_0603_25V7-M

PJ503 @

1

2

2 1 +2. 5V_D DR

JUMP_43X39

+1.8VALW_L_P

2 1

PC522

105K_0402_1%

22U_0603_6.3V6-M

UG_VDDQ

LX_VDDQ

LG_VDDQ

4

EC_ON 39,44,54

2

600mA

PJ505 @

2

JUMP_43X39

4

2

+3VALW

1

PR513

R_0402

100K_0402_5%

2

@

2

EC_SMB_DA3 44

@

2

EC_SMB_CK3 44
H_PROCHOT# 4,44

TDC-6A OCP-10A OVP-135%

PJ501 @

+1.0VALW_FB

2 1

2 1

2 1

2 1

2 1

2 1

2 1

PC513

PC512

22U_0603_6.3V6-M

PR518

2.2_0805_5%

EMC_NS@

PC533

1000P_0402_50V7K

EMC_NS@

PC515

PC514

@

22U_0603_6.3V6-M

22U_0603_6.3V6-M

21

21

EMC@ PC524

0.1U_0201_25V6-K

PL501

1

0.47UH_CMMB062D-R47MS_15A_20%

PC511

22U_0603_6.3V6-M

600mA

1

+1. 8VALW

2 1

5

PQ500
AON7408L_DFN8-5

321

AON7506_DFN

PQ501

3 521

2 1 2 1

JUMP_43X79

2 1

PC516

@

22U_0603_6.3V6-M

22U_0603_6.3V6-M

LX_1P0

1

PR1029

4.7_0603_5%

EMC_NS@

1 2 2

PC1109

1200P_0402_50V7-K

EMC_NS@

2A

PJ506

VDDQ_P

2

2 1

JUMP_43X39

PC525

PC526

2 1

10U_0805_25V6K

10U_0805_25V6K

2

@

@

@

2 1

2 1

2 1

PC528

PC527

PC1113

22U_0603_6.3V6-M

22U_0603_6.3V6-M

VDDQ_PGOOD 44

+1.0VALW

1

V20B+

TDC-6A OCP-10A OVP-120%

PJ507

+1.2V_P

2

1

2 1

JUMP_43X79

2 1

2 1

PC529

22U_0603_6.3V6-M

22U_0603_6.3V6-M

@

2 1

PC530

PC531

PC532

2 1

0.1U_0402_25V6

22U_0603_6.3V6-M

22U_0603_6.3V6-M

EMC_NS@

+1.2V

1

A A

Securityrr Classill fffication

Issued Date 2015///08///20 DecipheredDate 2016///08///20

THISII SHEET OF ENGINEEII RINGII DRAWINGII ISIITHE PROPRIEII TARY PROPERTY OF LC FUTURE CENTER. AND CONTAINSII CONFIDEIINTIALII
AND TRADE SECRET INFII ORMATION.II THISII SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVII ISIIIONII OF R&D DEPARTMENT
EXCEPT AS AUTHORIZEDII BY LC FUTURE CENTER NEITHEII R THISII SHEET NOR THE INFII ORMATIONII ITII CONTAINSII

5

4

3

MAY BE USED BY OR DISCII LOSED TO ANY THIRDII PARTY WITHOUII T PRIORII WRITTIIEN CONSENT OF LC FUTURE CENTER.

2

LC Futtture Centtter Secrettt Data

Tiiitttle

PWR PMIC- DDR4 /1.0 ALW/ 1. ALW

Size Document Number

D

DG42A

1

LW/ 1. ALWL W/1. ALW

Sheet 55 of 60Date: Sunday, January 22, 2017

Rev

1.0

5 4 3 2 1

D D

ZVM# 16

U23E@

U23E@

2 1

7

MODE

3V3

10

2

2 1

VCCOPC _GND

U23E@

5.1_04 02_1%

PC732

U23E@

PR734 PC 737

2.2_06 03_1% 0. 1U_0603_25V 7-M

1 2 2 1

9

BST

+VCCOPC_LX

8

SW

12

VOU T

2

PGN D

11

AGN D

PR701

1

+3VALW

VCCOPC _GND

U23E@

1U_0402_6.3V6K

1

PR717

2.2_08 05_5%

EMC_NS @

PC718

1000P _0402_50V7K

2 1 2

EMC_NS@

U23E@

0.56UH _PH041H-R56M S_5.4A_20%
PL701

1 2

1 2

2.2_06 03_1%
PR736

U23E@

12

PR722

1 2

0_0402_ 5%

U23E@

1

PR723

0_0402_ 5%

U23E@

4.5A

2 1

2 1

PC717 U23E@

PC721 @

PC716 U23E@

22U_060 3_6.3V6-M

22U_060 3_6.3V6-M

22U_060 3_6.3V6-M

VCCOPC _SENSE 12

2

VSSOP C_SENSE 12

PJ706

2

2 1

JUMP_43X79

+VCCOP C_1.0V+VCCOPC_L

1

@

PR710
0_0402_ 5%

U23E@

PR732

100K_0402_1%

1

5

3

4

VIN

EN

C1

C0

U23E@

6 1 2

LP#

NB681G D-Z_QFN13 _2X3

PG

13

U23E@

2

PR718

100K_ 0402_5%

PU703

1

1A

V20B+

PJ705 @

1

2

2 1

JUMP_43X39

PR721

VCCOPC _GND

1 2

0_0402_ 5%

U23E@

1

JUMPER

PJ701

@

2

C C

44,59 EC _VR_ON

PC722

2 1

U23E@

0.1U_0 402_25V6

2

@

.1U_0402_10 V6-K

PR719

2 1

1

@

47K_0 402_5%

PC719

+VCCOP C_VIN

PC750

PC720

2 1

2 1

U23E@

U23E@

10U_0805_25V6K

10U_0805_25V6K

+VCCOP C_EN

+3VS

0_0402_ 5%

PR708

1

2

U23E@

2

1

0_0402_ 5%

PR709

U23E@

B B

A A

Security Clllassiiifiiication

Issued Date

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPE RTY OF LC F UTURE CENTER... AND CONTAIIINS CONFIIIDENTIAL

AND TRADE SE CRET IIINFORMATION... THIIIS SHEET MAY NOT BE TR ANSFE RED FR OM T HE CU STODY OF T HE CO MPETE NT DIIIVIIISIIION OF R &D
DEPARTMENT EX CEPT AS AUTHORIIIZED BY LC FUT URE CE NTER NEI THER THIIIS SHEET NO R THE IIINFORMATION IT CONTAIIINS

5 4 3 2

MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WI THOUT PRIIIOR WRITTEN CONS ENT OF LC FUTURE CE NTER.

2015/08/20

LC Future Center Secret Data

Deciphered Date

2016/08/20

Title

PWR-+VCCOPC

Size Documenttt Number C R ev

Dattte: Sheet 57 of 60

DG42A

Sunday, ,, Ja nua ry 22,,, 2017

1

1.0

5 4 3 2 1

PC918

2 1

PR936

PR937

PR938

Vcore _PH 59,6 0

+CPU_ CORE 12,60

2

13K_0 402_1%

1 PR956 2

2 1

2

3300P _0402_50V7K

PR933

PH904

+VCCST_CPU

2

1

2

45.3_0402_1%

GT_PH1 59,60

GT_PH2 59,60

+VCC_ GT 12,60

GT_PH1 59,60

GT_PH2 59,60

2

@

PR943

PR932

2

1

1

75_0402_1%

100_0402_1%

VR_SV ID_DAT 12

VR_SV ID_ALRT# 12

VR_SV ID_CLK 12

SA_PH 59,60

+VCCS A 13,60

+5VS+5VS

1 2 1 2

PC916

2.2U_0603_10V7K

VR_PV CC

18

PVCC

VCORE P ORTION

VCCGT PORTION

VCCSA PORTION

IOUT_1b

43

SA_Iout

1

2

2

2.2_06 03_5%
PR926

VR_VCC

13

VCC

1

PR958

59K_0 402_1%

V20B+

PR923

2

1

1K_0402_1%

VR_VRM P

12

VRMP

LG3 /ICCM AX_1 b

CSC OMP_ 2ph

NCP812 16MNTXG_Q FN52_6X6

PW M/ICC MAX_1 a

LG2 /ADD R_VBOO T

EPAD

53

12

SCL K

ALE RT#

DRON

BST3

CSP _1a

CSN _1a

CSS UM_2p h

ILIM_2ph

CSR EF_2p h

BST1

LG1 /ROS C

CSP 1_2ph

CSP 2_2ph

CSP _1b
CSN _1b

PC920

0.01U_ 0402_25V7K

36

SDIO

38

37

39

26

25

HG3

24

SW 3

23

33

32

7

6

5

8

14

15

HG1

16

SW 1

17

10

9

40

22

BST2

21

HG2

20

SW 2

19

44
45

VR_SV ID_DAT_1
VR_SV ID_CLK_1
VR_SV ID_ALRT#_1

DRON 60

PR919 PC910

Vcore _BST

1

2.2_06 03_5% 0.22U_0 603_16V7K

11K_0 402_1%

2

1

PR941

GT_CSSU M
GT_CSCOM P

U23E@ 220K_ 0402_5%_TSM0B 224J4702RE

GT_ILIM

2

PR951 16 .9K_0402_1 %

GT_CSR EF

GT_BST1

1

PR925

2.2_06 03_5%

GT_LG1 60

PR954

2

1

14K_0 402_1%

1 2

102K_ 0402_1%

PR927

SA_BS T

1 2

PR989 2.2 _0603_5%

SA_HG 60

14K_0 402_1%

1

PR955

SA_CSP

2 1 2

Vcore _HG 60

Vcore _PH 59,60

Vcore _LG 60

Vcore _CSP

1

PR950

1 2 1

2

GT_HG1 60

2

GT_CSP1

GT_CSP2

1

PC915

1 2

0.22U_ 0603_16V7K

GT_PW M 60

SA_LG 60

PH901

PC989

1 2

2 7 5K_0402_1%

2

GT_PH1 59,60

0.22U_ 0603_16V7K

23.2K_ 0402_1%

1 PR947 2

22K_0 402_1%

PR948 2 1

1

100K_ 0402_1%_TSM0B 104F4251RZ

PC942 3300 P_0402_50V7-K

PC922 2200 P_0402_50V7K

1 2 P R904

137K_ 0402_1%

1 2 PC925

220P_ 0402_50V7K

PC914 330P_ 0402_50V7K

PC917

2 1

0.01U_0402_25V7K

SA_PH 59,60

1U_0402 _6.3V6K

10_040 2_1%

VR_SV ID_DAT_1

VR_SV ID_ALRT#_1

VR_SV ID_CLK_1

PH905

2

1 2

1 2

1 PR949 2

1

0.047U _0402_16V7K
PC926

2 1

180K_ 0402_1%

U23E@

2

PR1018

180K_ 0402_1%

U23E@

10_0402 _1%

1

PC988

0.047U_0402_16V7K

2 1

U23E@

PR1019
2K_04 02_1%

U22@

1

2

+5VS

22K_0 402_1%

1

PC941
PC927 1 2 330 0P_0402_50V7K

2 1

0_0402 _5%

2 1

49.9_0 402_1%

2 1

PR924 2

PR988

10_0402 _1%

1 2

U23E@

1 2

PR953

1.8K_0 402_1%

1

PR952

1.8K_0 402_1%

U23E@

PR957

100K_ 0402_1%_TSM0B 104F4251RZ

1

2

2.2_06 03_5%

PR940

2

Vcore_ COMP

Vcore _ILIM

1

Vcore_ VSP

Vcore_ VSN
Vcore_ IOUT

GT_IOUT

2

GT_DIFF OUT

GT_COMP

2 1 2

PC908

GT_TSENSE

PR912

15.8K_ 0402_1%

1 2

2

1

VR_EN

GT_FB

GT_VSN

SA_COMP

SA_ILIM

2

SA_VS P

SA_VSN

PC9393 30P_0402_50 V7K

PR922

PU901

50

41

42

35

30

31

28

29
34

27

4

51

52

11

47

46

49

48

470P_ 0402_50V7K

1

3

1 2 1

PC912

2.2U_0603_10V7K

PSYS/TS ENSE_1b

EN

VR_RDY

VRHOT#

COM P_1a

ILIM_1a

VSP _1a

VSN _1a

IOUT_1a

TSEN SE_ 1a

IOUT_2ph

DIFF OUT_2 ph/I CCMA X_2ph
COM P_2ph

FB_ 2ph

VSP _2ph

VSN_2ph

TSENS E_2 ph

COM P_1b

ILIM_1b

VSP _1b

VSN _1b

PC929

+VCCST_CPU

D D

2

1

2

2 1 2

1

PR945

2

1

2

1K_0402_1%

2.7K_0 402_1%

1

2 2

PR903

PC901 15P_ 0402_50V8J

330P_ 0402_50V7K PC90 6

1

PR914

49.9_0 402_1%PC907

@

PR944

54.9_0 402_1% @

44,57 EC _VR_ON

44 CPU_VR _READY

44,53 VR_ HOT#

1.58K_ 0402_1%

1

12 VCO RE_VCC_S EN

12 VCORE_ VSS_SEN

C C

PC913
1000P _0402_50V7K

12

PH902

2

2

1

PR942
0_0402_ 5%

@

1

1 2

PR931

2 1

8.25K_0402_1%

PR913

1

PR910 PC 904 1000P _0402_50V7K

1.58K_ 0402_1%

PC924

.1U_04 02_10V6-K

Place close t o MOSFET

100K_0402_1%_TSM0B104F4251RZ

12 VCCGT_V CC_SEN

12 V CCGT_VSS _SEN

B B

12

@

PR960
0_0402_ 5%

13 VCC SA_VCC_ SEN

PC934

PR963

PH903

2

1

2 1

2

1

8.25K_0402_1%

100K_0402_1%_TSM0B104F4251RZ

13 VCCSA _VSS_SEN

.1U_04 02_10V6-K

1 2

PC931

1000P_0402_50V7K

1 2

PR966 1.54K_ 0402_1%

1 2 1 2

PC937 1.5 4K_0402_1% PC9 38 1000P_04 02_50V7K 1 PR970 2

1000P _0402_50V7K P R907

53 Ps ys

@

PR946

1K_0402_1%

PR916

@

2

1

0_0402_ 5%

1500P_0402_50V6-K

1

PC902

1 2

1

2 1

1 2

1K_04 02_1%

1.5K_0 402_1% 0.0 15U_0402_25V 7-K

1

PR965

PC935 15 P_0402_50V8 J

1 2

499_040 2_1%

2

PR911

2

1

470P_ 0402_50V7K

2 1 P C930

1 2

26.1K_ 0402_1% PR 959

470P_ 0402_50V7K

2

PR918

2 2 1

PC936

1 2

1000P _0402_50V7K PC 909

470P_0402_50V7K

2

40.2K_ 0402_1%

154K_ 0402_1%

7.5K_0 402_1%

1000P _0402_50V7K P C940

1

0_0402_ 5%

18K_0 402_1%

2

PR901

1 2

2

1

PC911

1

PR917

Vcore_ TSENSE

PR902 U23E @

1

PR934 220 0P_0402_50V7K

1

1 2

PC932 10P_0 402_50V8J

1.5K_0 402_1%

1 PR964 2

2

1

PC933 330 0P_0402_50V7 -K

1

499_040 2_1%

A A

Security Clllassiiifiiication

Issued Date

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPE RTY OF LC F UTURE CENTER... AND CONTAIIINS CONFIIIDENTIAL

AND TRADE SE CRET IIINFORMATION... THIIIS SHEET MAY NOT BE TR ANSFE RED FR OM T HE CU STODY OF T HE CO MPETE NT DIIIVIIISIIION OF R &D
DEPARTMENT EX CEPT AS AUTHORIIIZED BY LC FUT URE CE NTER NEI THER THIIIS SHEET NO R THE IIINFORMATION IT CONTAIIINS

5 4 3 2

MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WI THOUT PRIIIOR WRITTEN CONS ENT OF LC FUTURE CE NTER.

2015/08/20

LC Future Center Secret Data

Deciphered Date

2016/08/20

Title

PWR_CPU_CORE1

Size Documenttt Number C R ev

Dattte: Sheet 59 of 60

DG42A

Sunday, ,, Ja nua ry 22,,, 2017

1

1.0

5 4 3 2 1

PJ1001

VCCIA_ VIN

2

1

2 1

5

PQ1001
AON6380_DFN8-5

59 Vc ore_HG

59,60 Vcore_PH

D D

59 Vc ore_LG

4

321

5

PQ1002
AON6324_DFN8-5

4

321

+5VS

C C

59 GT_HG 1

59,60 GT_PH1

B B

59 GT_LG 1

1

PR1002

2.2_08 05_5%

EMC_NS @

1 2

PC1026

1000P_0402_50V7K

EMC_NS @

2

4

4

PC1001

0.1U_0201_25V6-K

EMC @

2.2_06 03_5%

1 2

5

321

5

321

2 1

U23E@

PR1014

2 1

2 1

PC1003

PC1002

10U_0805_25V6K

10U_0805_25V6K

0.15UH _PCMB063T-R1 5MS_30A_20%

1

PL1001

2 1

U23E@

PC1034

1U_0402 _10V6K

PQ1005
AON6380_DFN8-5

PQ1006
AON6324_DFN8-5

2

59 GT_PW M

59 DRO N

JUMP_ 43X79

@

+CPU_ CORE 12,59

Vcore _PH 59,6 0

10_0402 _5%

PR1005

U23E@

1

PR1008

2.2_08 05_5%

EMC_NS @

1 2

PC1047

1000P_0402_50V7K

EMC_NS @

2

0_0402_ 5%

1

PR1004

U23E@

1 2

2

1

+

PC1004

68U_25V_M

2

1

+

PC1015

2 3

220U_D2_2VM_R6M

U23E@

PU902
NCP811 51MNTBG_DFN 8_2X2

GT_VCC

4

2 1

2 1

PC1033

10U_0805_25V6K

1

PL1003

VCC BST

2

PW M DR VH

3

EN SW

9 5

FLA G D RVL

2 1

PC1031

10U_0805_25V6K

2

GT_PW M_D

GT_EN

PC1032

0.1U_0201_25V6-K

EMC@

0.15UH _PCMB063T-R1 5MS_30A_20%

+CPU_CORE

1

8

7

6

GND

VCCGT1_V IN

+VCC_ GT 12,59,60

GT_PH1 59,60

V20B+

1

2 1 2

PR1013

2.2_06 03_5% 0.22U_0 603_16V7K

U23E@ U2 3E@

GT_BST2

GT_HG2

GT_PH2

GT_LG2

@

PJ1004

2 1

2 1

JUMP_43X79

1

+

2 3

2 1

2 1

2 1

2 1

PC1008

PC1009

22U_0603_6.3V6-M

@

2 1

PC1017

PC1025

22U_0603_6.3V6-M

@

2 1

PC1085

U23E@

U23E@

10U_080 5_25V6K

22U_0603_6.3V6-M

2 1

PC1018

22U_0603_6.3V6-M

VCCGT2_V IN

+VCC_ GT 12,59,60

GT_PH2 59

PC1013

22U_0603_6.3V6-M

2 1

22U_0603_6.3V6-M

PC1010

22U_0603_6.3V6-M

2 1

PC1024

22U_0603_6.3V6-M

@

PJ1002

2 1

2 1

JUMP_43X79

PC1011

PC1019

22U_0603_6.3V6-M

PC1030

2 1@2 1

2 1

2 1

PC1005

PC1007

PC1006

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

2 1

2 1

2 1@2 1

PC1023

PC1016

PC1022

5

PQ1007
AON6380_DFN8-5

321

5

321

U23E@

PQ1008
AON6324_DFN8-5

U23E@

1 2

1

PR1017

2.2_08 05_5%

EMC_NS @

PC1084

1000P _0402_50V7K

EMC_NS@

2

4

4

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

2 1

2 1

U23E@

PC1083

PC1082

10U_0805_25V6K

0.1U_0201_25V6-K

0.15UH _PCMB063T-R1 5MS_30A_20%

1 2

U23E@

PL1004

V20B+

+VCC_GT

1

+

PC1045

PC1066

2

330U_D2_2V_Y

220U_D2_2VM_R6M

2 1

2 1

PC1052

22U_0603_6.3V6-M

@

2 1

2 1

PC1067

22U_0603_6.3V6-M

2 1

2 1

PC1053

22U_0603_6.3V6-M

2 1

PC1068

22U_0603_6.3V6-M

2 1

2 1

PC1054

22U_0603_6.3V6-M

PC1069

22U_0603_6.3V6-M

2 1

PC1055

22U_0603_6.3V6-M

2 1@2 1

PC1070

22U_0603_6.3V6-M

PC1058

PC1057

PC1056

PC1071

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

@

2 1

2 1

PC1073

PC1072

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

@

+CPU_CORE

2 1

2 1

PC1012

PC1014

22U_0603_6.3V6-M

2 1

22U_0603_6.3V6-M

22U_0603_6.3V6-M

2 1

PC1020

PC1021

22U_0603_6.3V6-M

22U_0603_6.3V6-M

V20B+

+VCC_GT

1

+

PC1086

2 3

U23E@

220U_D2_2VM_R6M

+VCC_GT

2 1

2 1

2 1

2 1

PC1059

22U_0603_6.3V6-M

2 1

2 1

PC1074

22U_0603_6.3V6-M

@

@

2 1

PC1060

PC1061

22U_0603_6.3V6-M

22U_0603_6.3V6-M

2 1

2 1

PC1077

PC1075

PC1076

22U_0603_6.3V6-M

22U_0603_6.3V6-M

2 1

PC1063

PC1062

22U_0603_6.3V6-M

PC1064

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

@

VCCSA _VIN

SA_PH
59,60

234

9

A A

59 SA _HG

59 SA_ LG

1

10

8

AON793 4L_DFN10

765

PQ1003

5 4 3 2

PR1006

2.2_08 05_5%

EMC_NS @

1 2

12

PC1046

1000P_0402_50V7K

EMC_NS @

2 1

PC1027

0.1U_0201_25V6-K

EMC@

0.47UH _PCMB053T-R4 7MS_13A_20%

2 1

2 1

PC1029

PC1028

10U_0805_25V6K

10U_0805_25V6K

PL100 2

1

2

+VCCS A 13,59

SA_PH 59,60

2 1

2 1

PC1115

@

PJ1003

2 1

JUMP_43X79

2 1

47U_0603_4V6-M

@

V20B+

+VCCSA

2 1

PC1038

22U_0603_6.3V6-M

Issued Date

2 1

PC1039

22U_0603_6.3V6-M

2 1

2 1

PC1116

47U_0603_4V6-M

2 1

PC1037

PC1036

22U_0603_6.3V6-M

22U_0603_6.3V6-M

Security Clllassiiifiiication

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPE RTY OF LC F UTURE CENTER... AND CONTAIIINS CONFIIIDENTIAL

AND TRADE SE CRET IIINFORMATION... THIIIS SHEET MAY NOT BE TR ANSFE RED FR OM T HE CU STODY OF T HE CO MPETE NT DIIIVIIISIIION OF R &D
DEPARTMENT EX CEPT AS AUTHORIIIZED BY LC FUT URE CE NTER NEI THER THIIIS SHEET NO R THE IIINFORMATION IT CONTAIIINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WI THOUT PRIIIOR WRITTEN CONS ENT OF LC FUTURE CE NTER.

2 1

2 1

PC1042

PC1041

PC1040

22U_0603_6.3V6-M

22U_0603_6.3V6-M

2015/08/20

22U_0603_6.3V6-M

LC Future Center Secret Data

Deciphered Date

2016/08/20

Title

PWR_CPU_CORE2

Size Documenttt Number C R ev

Dattte: Sheet 60 of 60

DG42A

Sunday, ,, Ja nua ry 22,,, 2017

1

1.0

5

4

3 2 1

CPU Thermal Holex3 GPU Thermal Holex2

H1
HOLEA

D D

1

pad_c6p0d4p0

H2
HOLEA

1

pad_c6p0d4p0

H3
HOLEA

1

pad_c6p0d4p0

Close to RJ45

H6
HOLEA

1

CHASSIS1_GND

pad_ct7p0b8p0d3p0

Close to Audio jack

H7
HOLEA

1

pad_ct7p0b8p0d3p0

PCB Fedical Mark PAD

FD2

FD3

FD4

1

1

1

FD1

1

FD5

FD6

1

1

WLAN Standoff

H10
HOLEA

1

C C

H17

HOLEA

1

pad_o2p6x2p9d2p6x2p9n

SH1

ME@

B B

1

1

SPRING_FINGER_6.2X1.64

SH4

ME@

1

1

SPRING_FINGER_6.2X1.64

pad_ct5p5d2p5

H18
HOLEA

1

PAD_CT7P0D3P0

SH2

ME@

1

1

SPRING_FINGER_6.2X1.64

SH5

ME@

1

1

SPRING_FINGER_6.2X1.64

H19
HOLEA

1

PAD_CT7P0D3P0

1

1

SH3

1

SPRING_FINGER_6.2X1.64

SH6

1

SPRING_FINGER_6.2X1.64

H11
HOLEA

1

pad_ct7p0b6p0d3p3

ME@

ME@

H20

HOLEA

1

pad_c3p3d3p3n

H12
HOLEA

1

pad_ct7p0d3p0

1

1

H13
HOLEA

1

pad_ct7p0d3p0

SH12

ME@

1

SPRING_FINGER_6.2X1.64

SH13

ME@

1

SPRING_FINGER_6.2X1.64

H15
HOLEA

1

pad_ct5p0d2p5

SH7

1

SH9

1

1

USB3.0 Shielding

H16
HOLEA

1

pad_cb5p5d2p5

ME@

1

SHIELDING_SUL-35A2M_9P2X3P3_1P

ME@

SHIELDING_SUL-35A2M_9P2X3P3_1P

DDR4 Shielding

Optane Standoff

H21
HOLEA

1

pad_ct7p0b6p0d3p3

SH8

ME@

1

1

SHIELDING_SUL-35A2M_9P2X3P3_1P

SH10

ME@

1

1

SHIELDING_SUL-35A2M_9P2X3P3_1P

SH14

ME@

1

1

SHIELDING_SUL-35A2M_9P2X3P3_1P

SH11

ME@

1

1

SHIELDING_SUL-35A2M_9P2X3P3_1P

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

2015/08/20

3 2

LC Future Center Secret Data

Deciphered Date 2016/08/20

Title

Hole

Size Document Number

B

Sunday, January 22, 2017

DG42A

Sheet

1

Rev

1.0

49 o f 60Date: