Lenovo B465 Schematics

5

PRELIMINARY

D D

EXTERNAL CLOCK GENERATOR

4

3

GUAM S1G4 SCHEMATIC DESIGN

DDR III, 1333MT/S

HDT

SCAN

16

AMD S1G4 CPU

Channel A

Channel B

2

UNBUFFERED DDR3 NEAR SODIMM

18,19

UNBUFFERED DDR3 FAR SODIMM

18,19

Optional CPU Temperature sensor

16

1

SLG8LP625

20

14,15,16,17

OUT

HyperTransport

IN

LINK0

SB-TSI

16

16x16

LVDS CON

PARK_XT_S3

C C

VGA CON

43

31--40

44

LVDS MUX

CRT MUX

X16 PCIE MUX

RS880M

HyperTransport LINK0 CPU I/F DX10 IGP LVDS/TVOUT/TMDS DISPLAY PORT X2 Side Port Memory

I2C I/F

BOOTSTRAPS ROM(NB)

Ambient Light Sensor

24

52

1 X16 PCIE I/F 1 X4 PCIE I/F WITH SB

GPP PCIE INTERFACE

LAN&CARDREADER JMC261

B B

45

Finger Print Reader

USB#6

45

Bluetooth

USB#7

CAM

USB#5

48

MINIPCIE WIFI

47

USB#4

SIM card socket

USB#1USB#3

45

46

MINIPCIE

USB#8

USB#0

USB 2.0

GPP INTERFACE

USB 2.0

49

USB 2.0

46

6 X1 PCIE I/F

SB820M

USB2.0 (14)+1.1(2) SATA III (6 PORTS) 4 X1 PCIE GEN2 I/F

INT. CLK GEN. GB MAC HW MONITOR PCI/PCI BDGE INT. RTC EC HD AUDIO LPC I/F

21,22,23,24,25

PCIE

X4

26,27,28,29

HD AUDIO I/F

SATA III I/F

HW MONITOR I/F

SPI I/F

SPI ROM

AZALIA CODEC CX20671

HW MONITOR

42

Mobile 2.5" HDD Mobile ODD

41

28

41

CPU Tempreture Sensor

SPI I/F ACPI 1.1

I2C I/F

BOOTSTRAPS ROM (SB)

30

BATTERY CHAGER

A A

SYSTEM MAIN POWER

7

13

5

CPU CORE

1V1DUAL/VLDT/ VCC_NB/+1.1V

CPU MEMORY POWER

8

DISCHARGE CIRCUIT

10

1.5V/1.5VDUAL/

1.8V/3.3V/5V

RESET,FAN & ENABLES

9

11

SCANNED MATRIX KEYBOARD

PS2 TOUCH PAD

55

4

IT8502E EC

4949

3

49

Title

BLOCK DIAGRAM

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Date:

Thursday, August 05, 2010 54

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Bitland Information Techonogy Co.,Ltd.

Bitland Information Techonogy Co.,Ltd. Notebook R&D Division

Notebook R&D Division

BM5016

Sheet of

1

Rev

1.0

5

4

3

2

1

D D

C C

B B

TABLE OF CONTENTS

A A

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TABLE OF CONTENTS

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Date:

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5

4

3

2

Thursday, August 05, 2010 54

Notebook R&D Division

BM5016

Sheet of

1

Rev

1.0

2

1.0

5

BATTERY

11.1V 62WHr

AC ADAPTOR 15-16V 90W

D D

C C

BATTERY CHARGER ISL6251

+VIN

DDR3 PWM LDO VTT TPS51128&RT9199GSP

CPU_VDDIO_SUS +1.5V 4A

CPU_VDDIO_SUS 1.1V_1.0V_PWR

B B

+3.3VDUAL

CPU_VDDIO_SUS

+5VDUAL

+3.3VDUAL

A A

+1.1V DUAL

+3.3VDUAL

5

4

CPU core PWM ISL6265A

+1V~1.2V SW +1.1V SW ISL6228

+1.8V SW MAX8716-2/2

+5V SW +3V SW +5V LDO +3V LDO tps51125

VDDC PWM

TPS51128

SWITCH

2.5V LDO

SWITCH

1.5V LDO

SWITCH

4

CPU_VDD_RUN@38A

CPU_VDDNB_RUN@4A

CPU_VDDIO_SUS@9A

MEM_VTT@1.5A

+1.1VDUAL@10A +VCC_NB_RUN

+1.8V@1.3A

+3.3VALW +5VALW

+3.3VDUAL@8A +5VDUAL@8A

VDDC@15A

MVDDQ

+3VRUN

1.8V_REG 1.5A

+1.5V@1A

+5V

+3.3V

CPU_VDDA_RUN +3.3V

+1.1V

S3,S4,S5

+1.5VDUAL

2.6A

+1.5V

3

+5V

VLDT

+1.1V

+1.8V

+1.1V

+3.3V

+1.8V

+1.1V

+3.3V

+1.1V

+3.3V

+3.3VDUAL

+1.1VDUAL

+1.1V

VDDIO_GBE_S/2

+3.3VDUAL

+1.1VDUAL

PHY_VDDIO_DUAL

+3.3VDUAL

+1.1VDUAL

AZ_VDDIO_DUAL

+1.1VDUAL

+3.3V

+1.1V

+3.3VDUAL

VDDC

MVDDQ

1.1V_1.0V_PWR

1.8V_REG

+3VRUN

3

VLDT

AOZ1024 PWM

+VCC_NB

+3.3V

+1.8V

+1.5V

+3.3V

+1.8V

+3.3V

+1.8V

CPU_VDDA_RUN

CPU_VDD_RUN

CPU_VDDNB_RUN

BEAD

CPU_VDDIO_SUS

VDDR

BEAD BEAD

BEAD BEAD BEAD BEAD BEAD BEAD BEAD BEAD

AMD SB800

BEAD BEAD BEAD BEAD BEAD BEAD

BEAD

BEAD BEAD BEAD BEAD BEAD BEAD

AMD S1G4

VCCA 2.5V

VDD CORE

1.375-1.500V 36A

VDDNB CORE

0.9V 4A

VLDT 1.2V TPDA

VDD MEM TPDA

VDDR 1.5A

RS880M

VDDHTTX 1.2V 0.68A

VDDHTRX+HT 1.1V 0.68A

VDDPCIE 1.1V 1.1A

VDDA18 1.8V 0.64A

VDDC 1.0V-1.1V 7.6A

VDDG33 3.3V 0.06A

VDDG18 1.8V 0.005A

VDD18_MEM 1.8V 0.005A

VDD_MEM 1.8V 0.23A

AVDD 3.3V 0.125A

VDDLT18 0.22A

VDDLT33 0A

PLLs 1.8V 0.1A

PLLs 1.1/1.2V 0.23A

VDDIO_33_PCIGP 3.3V 0.020A

VDDIO_18_FC 1.8V 0.050A

VDDAN_11_PCIE 1.1V 1A

VDDPL_33_PCIE 3.3V 0.030A

VDDAN_11_SATA 1.1V 0.8A

VDDPL_33_SATA 3.3V 0.020A

VDDAN_33_USB_S 3.3V 0.2A

VDDAN_11_USB_S 1.2V 0.2A

VDDCR_11 1.1V 0.5A

VDDAN_11_CLK 1.1V 0.4A

VDDRF_GBE_S

VDDIO_33_GBE_S 3.3V

VDDCR_11_GBE_S 1.1V

VDDIO_GBE_S 3.3V

VDDIO_33_S 3.3V

VDDCR_11_S 1.1V

VDDCD_11_USB 1.1V

VDDIO_AZ_S 3.3V OR 1.5V

VDDCR_11_USB_S 1.1V

VDDPL_33_SYS 3.3V SYS PLL

VDDPL_11_SYS 1.1 V SYS PLL

VDDPL_33_USB_S 3.3 V USB PLL

VDDAN_33_S 3.3V HWM

VDDXL_33_S 3.3V

AMD SB800

PARK_XT_S3

2

CPU_VDDIO_SUS

MEM_VTT

DDRiII SODIMMX2--SYSTEM

VDD MEM 4A

VTT_MEM 0.5A

1

CLOCK GEN

+3.3V

+5V

+3.3V

+3.3VDUAL

+3.3V

BEAD

BEAD BEAD BEAD

+3.3VDUAL

SW

3.3V

HD CODEC

5V

3V

SMSC1100--EC

3.3V 0.5A

LCD PANEL

3.3V 1.5A

AUDIO OP

BACK LIGHT

+VIN

+5VDUAL

+1.5V

+3.3VDUAL

+5V

Title

Size

Size Custom

Custom

Date:

2

Date:

LED_BL

+VDD_MAIN

USB X2 FR

5VDual

MINI PCIE SLOT0,1,2

1.5V (S0, S1) 0.5A each

3.3V (S3, S5) 2.75A each

SATA HD0,1

5V (S3, S5) TBD

SATA ODD

5V (S0, S1) TBD

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POWER DELIVERY CHART

Document Number

Thursday, August 05, 2010 54

Notebook R&D Division

BM5016

Sheet of

1

3

Rev

1.0

Power on Sequence required:

SB800: 1, +3.3VDUAL ramp before +1.1VDUAL 2, +3.3V ramp before +1.8v 3, +1.8V ramp before +1.1v 4, +3.3v ramp before +1.1v 5, +3.3VALW_R ramping down time > 300us 6, 50uS <= All power rails except +3.3VALW_R <= 40mS 7, 100uS <= +3.3VALW_R <= 40mS

RS880: 1, 0 <(+3.3V) - (+1.8v) < 2.1 2, +1.8V ramp before +1.1v

3. +1.1V ramp before VCC_NB

D D

C C

B B

SB OUTPUT

SB INPUT

CPU MEM CTL & DDR3 SODIMM PWRS

CPU_THM/SB/SB_SCL1/2 SB_KB/SPI/LPC ROM PWRS

KBC is ready

KBC is powered by A_VBAT & +3.3VALW

5

CPU_LDT_RST#

(SB TO CPU)

CPU_PWROK

(SB TO CPU)

CPU_CLKP/N running

NB_PWRGD

NB_PWRGD_IN

1)+1.5V SWITCH TO +1.5VDUAL 2)LASSO_PWRON 3)LPCPD# for TPM 4) TO SB&KBCSB_PWRGD

+1.2V_PWRGD

PARK-XT_PGOOD

1.8V_REG

1.1V_1.0V_PWR

PCIE_REFCLKP/N

VDD_CT

VDDC

MVDDQ

VCC_NB

VLDT

+1.1V

VRM_PWRGD

CPU_VDDR

CPU_VDD_RUN

CPU_VDDNB_RUN

VDDA_PWRGD

+2.5V_LDO

(CPU_VDDA_2.5_RUN)

+1.5V

1V8_PWRGD

GROUP A GROUP B

+1.8V

+5V/+3.3V

5V/3.3V_GATE

SLP_S3#

VDRAM_PWRGD

MEM_VTT MEM_VREF

CPU_VDDIO_SUS

SLP_S5#

PWR_BTN#_EC

RSMRST#

V3V5DUAL_PWRGD 1V1DUAL_PWRGD SYSTEM_DUAL_PG_DELAY

DUAL RAILS

VDD_DUAL_EN

Power button pressed

AC_OK (ACIN detect)

+5VALW/+3.3VALW

LDO:5.4V (from DCIN)

+VIN/+12V_HD

A_VBAT

VTT only will be shut down in S3 mode, and VTT for DDR3 SODIMM only.

RC=~ms

RC=0

Power button from EC to SB

20mS delay

+5VDUAL/+3.3VDUAL/+1.5VDUAL/+1.1VDUAL When IMC, always on at all time( always PWR)

Power button pressed

AC not present scenario = LOW AC present= high

Battery inserted/AC IN

4

Req.

>1 mS

>1 mS Req.

running

>1 mS Req.

T3>0

T2>0

T1>=0

RC=~22ms

VCC_NB should not ramp before 1.1v

RC=~4.7ms

VRM_PWRGD AND 1V8_PWRGD

RC=0

VCC_NB(all NB power) valid before NB_PWRGD.

SLP_S3#

1V1DUAL_PWRGD 1V5_PWRGD/DNI

SYS_RST#

+1.2V_PWRGD

KBC_GPIO77/DNI

3

to S3

2

1

A A

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4

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Thursday, August 05, 2010 54D4

1

Notebook R&D Division

POWER SEQUENCE CHART

BM5016

Sheet of

Rev

1.0

5

4

3

2

1

EXTERNAL CLOCK MODE

AMD NORTHBRIDGE

RS880M

A-LINK

GPP_REFCLK

D D

100MHZ

NBLINK_RCLKP/N

A_SODIMM

MEM_MB_CLK1_P/N

MEM_MB_CLK2_P/N

MEM_MA_CLK1_P/N

MEM_MA_CLK2_P/N

AMD

SIG4 CPU

B_SODIMM

CPU_CLKP/N

200MHZ

NB_GFX_REFCLKP/N

EXTERNAL

CLOCK GENERATOR

14.31818MHz

C C

SB_OSC

DNI

NB_OSC

100MHZ

14.318MHZ

GPP REF_CLK

HT_REFCLKP/N

PCIE_REFCLKP/N

100MHZ

CLK_REQ in CLK GEN

PCIE GFX PARK_XT(RS880M, 16 LANES)

EXT_PCIE_PE2_CLKREQ#

PARK_XT

27M Hz

PCIE_PE2_CLKP/N

100MHZ

PCIE_LAN_CLKP/N

100MHZ

MINIPCIE SLOT (SB800, 1 LANE)

EXT_PCIE_PE2_CLKREQ#

PCIE GPP I/F (RS880M, 1 LANE)

EXT_PCIE_LAN_CLKREQ#

PORT2:WLAN

JMC261

25M Hz

NB CLOCK INPUT TABLE

NB CLOCKS

HT_REFCLKP

HT_REFCLKN

REFCLK_P

REFCLK_N

GFX_REFCLK GPP_REFCLK

GPPSB_REFCLK 100M DIFF

* RS880M can be used as clock buffer to output two PCIE referecence clocks By deault, chip will configured as input mode, BIOS can program it to output mode.

RS880M

100M DIFF

14M SE (1.1V)

vref

100M DIFF(IN/OUT)*

NC or 100M DIFF OUTPUT

25M Hz

PCICLK0

25M_X1

25M_X2

PCICLK1

PCICLK2 PCICLK3 PCICLK4

LPCCLK0

LPCCLK1

RTCCLK

AZ_BITCLK

SPI_CLK

GBE_RXCLK GBE_TXCLK

FOR SATA

25M Hz

DNI

SBSRC_CLKP/N

100MHZ

CLK_48M_USB

48MHZ

AMD SB800

EXT CLK MODE

SATA_X1

SATA_X2

PCIE_RCLKP/N

USBCLK

PCI_CLK0

33MHZ

SMSC_CLK

33MHZ

PCI_CLK2 PCI_CLK3 PCI_CLK4

33MHZ

LPC_CLK0

33MHZ

LPC_CLK1

33MHZ

AZ_BIT_CLK

24MHZ

SPI_CLK

xxHZ

NC

FOR DEBUG PORT

STRAPS SETTING, PCIE GEN1/PCIE GEN2

STRAPS SETTING, UNUSED CLOCKS

EC/STRAPS SETTING :EC ENABLE

STRAPS SETTING, CLOCKS ENABLE

HD AUDIO

SPI ROM & HEADER

32.768K Hz

INTERNAL CLOCK MODE

MEM_MA_CLK1_P/N MEM_MA_CLK2_P/N

A_SODIMM

MEM_MB_CLK1_P/N MEM_MB_CLK2_P/N

B_SODIMM

B B

STRAPS SETTING, UNUSED CLOCKS

PCI_CLK0

SMSC_CLK

33MHZ

PCI_CLK2

33MHZ

PCI_CLK3

33MHZ

PCI_CLK4

33MHZ

LPC_CLK0

33MHZ

LPC_CLK1

33MHZ

SPI_CLK

xxHZ

AZ_BIT_CLK

24MHZ

FOR DEBUG PORT

STRAPS SETTING, PCIE GEN1/PCIE GEN2

EC/STRAPS SETTING :EC ENABLE

STRAPS SETTING, CLOCKS ENABLE

SPI ROM & HEADER

HD AUDIO

AMD

SIG4 CPU

CPU_CLKP/N

PCICLK0

PCICLK1

PCICLK2

PCICLK3

PCICLK4

LPCCLK0

LPCCLK1 RTCCLK SPI_CLK

AZ_BITCLK

200MHZ

CPU_HT_CLKP/N

AMD NORTHBRIDGE

RS880M

REFCLKP/N

A-LINK

100MHZ

NB_REFCLK_P/N

SB_NBLINK_RCLKP/N

PCIE_RCLKP/N

NB_DISP_CLKP/N

AMD SB820M

CLOCK GENERATOR

GPP_REFCLK

HT_REFCLKP/N

NB_HT_CLKP/N

100MHZ

SPM_CLK

xxxMHZ

SLT_GFX_CLKP/N

GPP_CLK2P/N

GPP_CLK3P/N

SIDE PORT MEMORY CHIP

PCIE_REFCLKP/N

100MHZ

SB_PCIE_PE2_CLKREQ#

100MHZ

PCIE_LAN_CLKP/N

100MHZ

PCIE GFX PARK_XT(RS880M, 16 LANES)

SB_MXM_CLKREQ#

MINIPCIE SLOT (SB800, 1 LANE)

CLK_REQ2 in SB

PCIE GPP I/F (RS880M, 1 LANE)

CLK_REQ3 in SB

PARK_XT

27M Hz

PORT2:WIFI

JMC261

25M Hz

A A

FOR MASTER FOR RTC FOR SATA

25M Hz

5

4

32.768K Hz

25M Hz

3

DNI

2

Title

CLOCK DISTRIBUTION

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Thursday, August 05, 2010 54

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Bitland Information Techonogy Co.,Ltd.

Bitland Information Techonogy Co.,Ltd. Notebook R&D Division

Notebook R&D Division

BM5016

Sheet of

1

Rev

1.0

5

Thermal Systems

(Emergency Shutdown, Throttling, Fan Control)

4

3

2

1

NON-POP

OVERRIDE#translate

PWM

TACH

4-PIN CPU FAN

NON-POP

KBC

SMSC

W18

F24

M8

P5

J4

G7

T7

Y9

B6 C6

THERMTRIP#

SDA3 SCL3 TALERT#

FANOUT2

SDA0AA18 SCL0

TEMPIN0 TEMP_COMM

PROCHOT#

FANOUT0 FANIN0

TEMPIN3

GEVENT4#

SDA2

ADM 1032

(S5-S0)

(S0)

AMD

SB800

TEMP_COMM

SCL2

Place under DDR

TEMP SENSOR (Q600)

TEMPIN1

TEMPIN2

SMBus Block Diagram

(S5-S0)

A6 C6

DDR 2

SO-DIMM

J401

THERMDC THERMDA

NON-POP

AMD

RS880

mini

PCI Exp x1

MPCIE1

PCI Exp x1

MPCIE2

mini

DDR 2

SO-DIMM

CLK. Gen.

9LRS4880

U800

J402

DUAL_SMB1

NOPOP

POP

SDATA1 SCLK1

SDATA0 SCLK0

CPU Thermal Sensor ADM1032

GPU Thermal Sensor U8

SB800

SDA1

(S5-S0)

SCL1

ASF Only

SDA0

(S0)

SCL0 SDA2

(S5-S0)

SCL2

S1G4

SIC SID

MAX1535 battery charger

U2700

AMD

(master)

(S5-S0)

1.8V

AMD

SDA3 SCL3

BAT_DAT BAT_CLK

(S5-S0)

MAX17009

SVC

CPU Core PWR PWM

SVD

U2800

EC

SMCLK0 SMDAT0

SMCLK1 SMDAT1

U103 (master)

(S5-S0)

(S3-S0)

SVC SVD

J106

translate

POP

3.3V SB-TSI

translate1.5V TSI 3.3V TSI

THERMTRIP_L

D D

MEMHOT_L

ALERT_L

THERMDC THERMDA

SID SIC

AMD

translate

VRM Power

VRM_HOT#

S1G4

PROCHOT_L

translate

ADM

C C

SO-DIMM EVENT

MXM

THERM#

SDA SCL

1032

Thermal disaster prevention is implemented by PROCHOT_L and THERMTRIP_L with hardware

non-system dependant functions. Fan speed control will only be implemented

by SB TSI software based implementation

KBC1100L

B B

Global

System

State

A A

G2

G2/G3

Power State / Voltage Rail Activity Summary

Processor

Sleep State

G0

G1

G2

S5 LOW

G3

Power

State

S0

S1

S3

S4

S5

C0

C1

C2

C3

c4

OFF

5

Running

Sleeping

Description

P-state transitions

under OS control

Stop grant,

caches snoopable

TBD

Powered on suspend

Suspend to RAM

Suspend to diskON

Soft-off

Battery IN

Mechanical off

Halt

RTC ALW DUAL

ON

OFF

SUS RUN

ON

OFF

ON

OFF

Group Name Description

INT: Stuff when use internal clock generator EXT: Stuff when use external clock generator DNI/NC: DO NOT INSTALL KBC: Stuff when use external KBC IMC: Stuff when use internal EC A11:Resistors marked with "A11" is only for SB800A11 ONLY.

OFF

Bitland Information Techonogy Co.,Ltd.

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Title

MISCELLANEOUS TABLES

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Date:

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Bitland Information Techonogy Co.,Ltd. Notebook R&D Division

Notebook R&D Division

BM5016

Sheet of

6

1

6

Rev

1.0

ON

OFF

4

5

VPJ1

VPJ1 DC JACK 5P

DC JACK 5P

PCN1

as BM5910

VPF1

VPF1 7A

7A

1 2

PR175

PR175 10

10

R0402

1 2

PR180

6.98K,1%

R0402

13

6251_DCIN

R0402

1 2

1206

SSM34PT

PC127

PC108

PC130

1 2

PD13

SMA

1uF/10V,X7R

1000pF/50V,X7R

PR186

PR186 10K

10K

R0402

PR40

PR40 NC_31.6K,1%

NC_31.6K,1%

R0402

5A

12

PC22

PC22 1000P_0402_50V7K

1000P_0402_50V7K

ACIN49

1 2

C0603PC127

C0603

1 2

C0603PC108

C0603

5V_internal_LDO

12

PC143

0.1uF/25V,Y5V

C0402

1 2

C0402PC130

C0402

PC146

PC131

PR37

PR37 NC_15.4K,1%

NC_15.4K,1%

1 2

R0402

PR32

PR32 10K

10K

1 2

R0402

1 2

PC132

PC132 NC_0.01uF/25V,X7R

NC_0.01uF/25V,X7R

12

C0402

R0402

15.4K,1%

15.4K,1% PR182

PR182

13

2

1

5

AD+

SHLD2

4

SHLD1

3

12

R0402

NC_100K,1%

NC_100K,1% PR215

PR215

AD-1

AD-2

2

Isense_SYSN

CHGVADJ49

CHG_ON49

SET_I49

PQ6

PQ6 NC_TP0610K-T1-E3_SOT23-3

NC_TP0610K-T1-E3_SOT23-3

2

PR266 NC_100K,1%

PQ5

PQ5 NC_DTC115EUA_SC70-3

NC_DTC115EUA_SC70-3

Isense_SYSP

1 2

D D

C C

B B

AD_6251+

A A

VPFB1

VPFB1 100ohm@100MHz,3A

100ohm@100MHz,3A

fb0805

1 2

VPFB2

VPFB2 100ohm@100MHz,3A

100ohm@100MHz,3A

fb0805

VPFB3

VPFB3 100ohm@100MHz,3A

100ohm@100MHz,3A

fb0805

12

100P_0402_50V8J

PR47

R0402

1 2

12

R0402

4.7

4.7 PR173

PR173

5600pF/50V,Y5V

1 2

0.01uF/25V,X7R

1 2

2.39V_Vref

12

R0402

20K_F

20K_F PR183

PR183

0.1 Vref

12

R0402

10.5K_F

10.5K_F PR185

PR185

SOD323

NC_1N4148WS

NC_1N4148WS PD36

PD36

PD34

PD34 NC_1N4148WS

NC_1N4148WS

SOD323

1 2

PC24

100P_0402_50V8J

100P_0402_50V8J PC21

PC21

1K

VDDP

C0603PC146

C0603

C0402PC131

C0402

PR39

PR39 100K

100K

R0402

1 2

12

AD+

12

PQ49

2N7002

SOT23

PR41

20K

R0402

PU11

15

1

19

20

5

6

11

3

9

8

10

23

ISL6251HAZ

SSOP24_25_150

EC_V3.3AL49

VDDP

VDD

CSIP

CSIN

ICOMP

VCOMP

VADJ

EN

CHLIM

VREF

ACLIM

ACPRN

12

PC23

PC253

PC255

1000P_0402_50V7K

NC_10U_1206_25V6M

3

1

2

PC9

1000pF/50V,X7R

C0402

1 2

ACSET

UGATE

PHASE

LGATE

CELLS

CHG_ON 49

SLP_S3# 9,11,27,40,49,51

12

PC256

NC_10U_1206_25V6M

R0402

12

R0402

DCIN

BOOT

PGND

CSOP

CSON

ICM

GND

PC192

PC192 1000pF/50V,NPO

1000pF/50V,NPO

C0402

PR15

51K

PR48

51K

2

24

17

16

18

14

13

21

22

4

7

12

1 2

PR172

PR172 0R

0R

R0402

12

PC126

0.1uF/25V,Y5V

C0402

12

PC129

PC129 1uF/10V,X7R

1uF/10V,X7R

C0603

12

PC191

PC191 NC_100pF/50V,NPO

NC_100pF/50V,NPO

C0402

PC134

0.01uF/25V,X7R

C0402

12

PC128

0.1uF/25V,Y5V

C0402

6251_DCIN

1 2

PD32

PD32 1N4148WS

1N4148WS

SOD323

1 2

PR184

PR184 100

100

R0402

PR176

PR176 0R

0R

R0402

4

1 2

PR11 8.2K R0402PR11 8.2K R0402

PR142

PR142 51K

51K

R0402

PR132

PR132 51K

51K

R0402

ACOFF#49

Isense_SYSP

12

PC137

0.01uF/25V,X7R

C0402

1 2

PR212

PR212 0R

0R

R0402

12

VDDP

phase

12

PC133

PC133 3300pF/50V,X7R

3300pF/50V,X7R

C0402

1 2

0.01UF/25V,X7R

AD_6251+

PR181

2.2

R0402

设置适配器限流值为

100mV/25m ohm=4.0A.

PR9 20K R0402PR9 20K R0402

PC2

1 2

ALW_EN

0.1uF/25V,X7R

0.1uF/25V,X7R PQ48

PQ48

C0603

AO4419

SO8_50_150

1 2 3

PR131

PC116

100K

R0402

C0402

3

PQ47

PQ47 2N7002

2N7002

SOT23

1

2

PR140

4.7K

R0402

12

PC10

PC117

0.01uF/25V,X7R

100pF/50V,NPO

C0402

5

D

PQ57

4

AO4468

G

PAK1212-8

S

123

12

R0402

10K

10K PR177

PR177

phase

5

D

PQ58

4

AO4468

G

PAK1212-8

S

123

ADC1 49

Layout note: Far away from critical signal trace

Iaclim=1/PR8*(0.05*Vaclim/Vref+0.05)

充电电流

SET_I

0V 0A

0.66V 400mA

3.3V 2A

ICHG=165mV/PR179*(VCHLIM/3.3V)

AD_6251+

1 2

ALW_EN 13

PD7

5A

1 2

8 7 6

SBM54PT

SMA

5

S

D

PD8

G

4

3

2

1 2

PD8

1 2

SBM54PT

SMA

Isense_SYSP

PR133

PR133 51K

51K

R0402

PQ42

2N7002

SOT23

1

1000pF/50V,X7R

12

PC136

PC136 1000pF/50V,NPO

1000pF/50V,NPO

C0402

12

PC148

PC148 1000pF/50V,X7R

1000pF/50V,X7R

C0402

2A 2A 2A

PR49

4.7F

0603

1 2

PC41

PC41 680P_50V_M_B

680P_50V_M_B

0402

1 2

PR36

PR36 NC_0

NC_0

R0402

PR35

PR35 0R

0R

R0402

Isense_SYSN

del BAT_OV#

PC135

C0402

1

SHDN49

1.5A

12

PC144

PC142

10uF/25V,X7R

0.1uF/25V,X7R

C1206

C0603

PL3

PL3 10uH/4A/68mOHM

10uH/4A/68mOHM

1 2

MHCI06030

PL11

PL11 nc_10uH/4A/68m

nc_10uH/4A/68m

LS2_1040

1 2

VDDP

12

PC147

4.7uF/25V,X7R

C1206

CELLS CELLNUMBER CELL PIN 4 VDD CELL PIN 3 GND CELL PIN 2 FLOAT

1 2

PR65

0.015_1W_F

1608

470pF/50V,NPO

Isense_SYSN

1 2

PR179

PR179 50mOHM,1%

50mOHM,1%

R1206

3

1 2

PR10 10 R0402PR10 10 R0402

PQ34

PQ34 AO4419

AO4419

SO8_50_150

4

8A 8A

3 6 2 1

PD4

1 2

PR16

PR16 510K

510K

R0402

BATT+

12

PD4

SSM34PT

PC3

SMA

0.1uF/25V,Y5V

C0402

1 2 3 6

4

1 2

3

1

2

12

PC8

PC8 1000pF/50V,X7R

1000pF/50V,X7R

C0402

12.6V

VBATS1

1

TPC60

NC_TestP

PC145

PC145 10uF/25V,X7R

10uF/25V,X7R

C1206

ADAPT_OUVP=1/9*AD+

Input OVP : 22.3V Input UVP : 17.26V

PC193

C0603

PR14 510K R0402PR14 510K R0402

1 2

3

PQ53

PQ53 2N7002

2N7002

SOT23

PR21

PR21 510K

510K

2

R0402

1 2

12

PC138

PC138 10uF/25V,X7R

10uF/25V,X7R

C1206

5

7 8

12

8 7

5

PQ41

PQ41 AO4419

AO4419

SO8_50_150

PR12

PR12 0R

0R

R0402

PQ33

PQ33 2N7002

2N7002

SOT23

需接到EC之

ADAPT_OUVP49

BATT+

8A

12

PC44

PC18

NC_0.1uF/25V,X7R

NC_2200pF/50V,X7R

C0402

1N4148WS/LMDL914T1G_SOD323-2~D

ADC

1 2

+VIN

12

PC7

PC43

0.01uF/25V,X7R

NC_0.1uF/25V,X7R

C0402

PR56

10K,1%

R0402

LM358DT_SO8

PFB1

PFB1 100ohm@100MHz,3A

100ohm@100MHz,3A

1 2

FB0805

PFB3 100ohm@100MHz,3A

1 2

FB0805

PFB2 100ohm@100MHz,3A

8A 8A

1 2

FB0805

12

PC140

@PC140

@

PC141

@PC141

@

PC25

nc_0.1u_0402_50V7K

nc_2200P_0402_50V7K

1000P_0402_50V7K

1 2

EC_V3.3AL49

PC26

@

nc_0.1U_0402_16V7K

AD+

1

2

8

3

ADPT_OUVP_DET

P

+

2

-

G

4

12

FB0805

PC184

5.6pF/50V,NPO

C0402

PZD2

2

1

BAT54S

sot_23

12

PR206 R0402

PC185

5.6pF/50V,NPO

C0402

3

PR54

PR54 133K,1%

133K,1%

R0402

PR55

PR55 931K,1%

931K,1%

需接到EC之

R0402

BATT_OVP49

PR57

PR57 133K,1%

133K,1%

R0402

100PR205

R0402

SM_BAT_SCL

12

BAT_DAT49

BAT_CLK49

SOD323

D88

PU27A

1

0

ADAPT_OUVP_R

PF2

PF2 7A

7A

FUSE1206

1 2

PF1

PF1 7A

7A

FUSE1206

1 2

100

EC_V3.3AL49

1N4148WS/LMDL914T1G_SOD323-2~D

VCC_358

ADC

PR207

PR207 300K

300K

R0402

EC_V3.3AL49

PR53

1 2

10K,1%

R0402

VMB

SM_BAT_SCL

12

PC27

@

nc_0.1U_0402_16V7K

SM_BAT_SDA

PR208

R0402 1K

R0402

PZD1

2

1

BAT54S

sot_23

1 2

2

VMB

12

@PC149

@

nc_2200P_0402_50V7K

1

3 4 5 6 7

1K

SOD323

D94

PC31

0.01UF/25V,X5R

C0402

7

0

BATT_OVP_R

12

PC150

@PC150

@

PC149

nc_0.1u_0402_50V7K

bat_bp02071-p5651-7f

C10376-10701-B

C10376-10701-B BATCON2

BATCON2

1 22GND 3 4 5 6 7

BAT_INT# 49

3

SM_BAT_SDA

+VIN

1

2

PU27B

PU27B LM358DT_SO8

LM358DT_SO8

8

5

P

+

6

-

G

4

GND1

PBATT_OVP

8

9

BATT+

12

PR50

PR50 133K,1%

133K,1%

R0402

12

PR51

PR51 931K,1%

931K,1%

R0402

12

PR52

PR52 133K,1%

133K,1%

R0402

BATT-OVP=1/9*BATT+ LI-3CELLS:13.5V----BATT-OVP=1.5012V LI-4CELLS :18.0V----BATT-OVP=2.001V

12

PC30

0.01UF/16V,X5R

C0402

1

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Bitland Information Techonogy Co.,Ltd. Notebook R&D Division

Notebook R&D Division

Title

Size

Document Number

Size

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Size

Document Number

Date:

Thursday, August 05, 2010 54D7

5

4

3

2

Thursday, August 05, 2010 54D7

1

Notebook R&D Division

ADP IN/BATTERY CHARGER

BM5016

Sheet of

Rev

1.0

5

Offset &

OFS/VFIXEN

Droop

GND

OX

+3.3V

X

+5VOX

Metal VID Codes

SVC

SVD

0

1

0

1

VRM_PWRGD10,51

R98

1 2

R99

1 2

R104

1 2

R109

1 2

VDDA_PWRGD16,17

VRM_RUN_EC49

R87255 R87255

R8954.9K_1%R8954.9K_1%

100

1 1 0.8

VFIXEN VID Codes

SVC

0 0 1 1

R2500RR250

0R

CPU_PWRGD_SVID_REG16

R2890 0RDNIR2890 0RDNI

C180 4700P

12

1 2

X7R

X7R 16V

16V

12

R881K_1%R881K_1%

C189 1200P

12

1 2

C233

X7R

1 2

16V

180P

X7R

X7R 16V

16V

Close to CPU socket

R1110RR111

0R

12

R112 0RR112 0R

12

Updata on rev:1.1

Close to CPU socket

R113 NC_0RR113 NC_0R

R120 0RR120 0R

SVD

0

0 1

+3.3V

12

R251

R251 10K

10K

12

CPU_SVD16

CPU_SVC16

ISP_0

ISN_0

12

D D

C C

CPU_VDD_RUN

CPU_VDD0_RUN_FB_H16

CPU_VDD0_RUN_FB_L16

B B

CPU_VDD1_RUN_FB_L16

CPU_VDD1_RUN_FB_H16

CPU_VDD_RUN

SVI

O X O

Output

1.10

1.0

0.9

Output

1.4

1.21

1.0

0.8

+5V

12

R47

34.8K_1%

R906.81K_1%R906.81K_1%

C275 1000P

1 2

X7R

X7R 16V

16V

change from 16.2k to 16.5k

R139 NC_10K_1%R139 NC_10K_1%

1 2

12

NC_100K_0402_1%_TH11-4H104FT

Parallel

+1.8V

R170 10K_1%R170 10K_1%

Parallel

VFIX

X

CPU_VDDNB_RUN_FB_H16

+5V

R26710R267

10

1 2

R18610R186

10

1 2

+VIN

R1990RR199

0R

12

R142

100K

1

12

OFS/VFIXEN

2

PGOOD

R2230RR223

0R

12

3

PWROK

R2460RR246

0R

4

12

SVD

R2470RR247

0R

12

5

SVC

R2480RR248

0R

12

6

ENABLE

12

7

RBIAS

R86

8

82.5K_1%

OCSET

9

VDIFF_0

10

FB_0

11

12

R93

4.02K_1%

12

RTN_1

Update on rev:1.1

COMP_0

12

VW_0

2

C276

0.1U

1

X7R

X7R 16V

16V

12

R9116.2K_1%R9116.2K_1%

PH2

R2490RR249

1

C372

C372 1U

1U

2

X7R

X7R 10V

10V

1

C377

0.1U

2

X7R

X7R 25V

25V

49

48

47

VIN

VCC

GND

ISN_0

ISP_013VSEN_0

14

CPU_VDDNB_RUN

0R

12

R144

22K_1%

1

C376

C376 33P

33P

2

X7R

12

25V

46

45

FB_NB

COMP_NB

Pin 49 is GND Pin

ISL6265_QFN_48 6x6

RTN_0

15

16

4A

C375

C375 1200P

1200P

X7R

X7R 25V

25V

R145

44.2K_1%

4

VDD_NB

PJ2

2

112

JUMP_43X118

R25247R252

47

12

R25347R253

47

PC215

12

330U_2.5V_R9mOHM

Updata on rev:1.1

R2700RR270

0R

12

Parallel

1

C374

C374 1000P

1000P

2

X7R

X7R 25V

25V

12

R137

11.5K_1%

42

40

43

44

41

RTN_NB

FSET_NB

VSEN_NB

PGND_NB

OCSET_NB

RTN_1

VSEN_1

VDIFF_119FB_120COMP_1

17

18

21

RTN_1

2

1

C277

C277 4700P

4700P

1

X7R

R128

16V

1K_1%

1 2

R127

R127 255

255

1 2

1

12

+

2

12

CPU_VDDNB_RUN_FB_L 16

38

37

39

LGATE_NB

PHASE_NB

UGATE_NB

VW_122ISP_123ISN_1

24

R266

2

6.81K_1%

6.81K_1% C356

C356 1000P

1000P

1 2

1

X7R

X7R 16V

16V

C344

C344 1200P

1200P

X7R

2

16V

C345

C345 180P

180P

1

X7R

X7R 16V

16V

R129

54.9K_1%

PL8

1 2

2.2UH +-20% 8A 20mo

C73

10U_0805_10V

LGATE_NB

PHASE_NB

UGATE_NB

U2

36

BOOT_NB

35

BOOT_0

34

UGATE_0

33

PHASE_0

32

PGND_0

31

LGATE_0

30

PVCC

29

LGATE_1

28

PGND_1

27

PHASE_1

26

UGATE_1

25

BOOT_1

2

C360

0.1U

1

X7R

X7R 16V

16V

567

8

D

PQ59

PQ59 AO4468

AO4468

SO8_50_150

S

123

PHASE_NB

567

8

D

S

123

1

C371

0.22U

2

X7R

12

25V

R256

2.2

C362

R257

1 2

2.2

0.22U

UGATE_0

X7R

X7R 25V

25V

PHASE_0

+5V

LGATE_0

C61

LGATE_1

2.2uF_X7R

PHASE_1

UGATE_1

C361

R136 2.2R136 2.2

12

0.22U

X7R

X7R 25V

25V

ISN_1

12

R131

4.02K_1%

NC_PH3

R134 NC_10K_5%R134 NC_10K_5%

1 2

12

100K_0402_1%_TH11-4H104FT

ISN_1ISN_1

Fou Uni-plane: G16,G17,R39:Assembly R38:Not Assembly

4

UGATE_NB

G

PQ55

PQ55 AO4468

AO4468

SO8_50_150

4

LGATE_NB

G

UGATE_0

3 5

12

3 5

12

UGATE_1

LGATE_1 LGATE_1

3 5

12

R130 16.2K_1%R130 16.2K_1%

12

C62

PQ31

SIR462DP-T1-GE3

241

PQ35

SIR466DP-T1-GE3

241

3 5

PQ39

SIR466DP-T1-GE3

241

ISP_1

10U_1210_25V

241

12

C64

VIN1

Panasonic ETQP4LR36WFC

LGATE_0

PQ32

SIR462DP-T1-GE3

Panasonic ETQP4LR36WFC

10U_1210_25V

VIN3

VIN2

3 5

1 2

PAD-OPEN 4x4m

1

C378

C378 2200P

2200P

2

X7R

X7R 25V

25V

PQ37

SIR466DP-T1-GE3

241

1

C380

C380 2200P

2200P

2

X7R

X7R 25V

25V

PQ40

SIR466DP-T1-GE3

241

PJP36

PJP34

1 2

PJP35

1 2

1

C379

0.01u

2

X7R

X7R 25V

25V

12

PR2272.2_5%PR2272.2_5%

1

C1931

2

1

2

12

PR228

2.2_5%

1

C1932

2

3

+VIN

12

C68

C69

C66

10U_1210_25V

0.36UH_PCMC104T-R36MN1R17_30A_20%

1 2

PL15

680P_50V8J

ISP_0

ISN_0

12

C77

C74

C75

C381

0.01u

X7R

X7R 25V

25V

C75

10U_1210_25V

0.36UH_PCMC104T-R36MN1R17_30A_20%

10U_1210_25V

1 2

PL16

680P_50V8J

2

CPU_VDD_RUN

1 2

C63

C71

C26

10nF

180P

0.22uF_6.3V

CPU_VDD_RUN

VIN1

CPU_VDD_RUN

C44

22uF_0805_6.3V

2

C338

C389

C340

0.1U

1

X7R

16V

2

C383

C382

0.1U

1

X7R

16V

Updata on rev:1.1 for esd

C384

0.1U

X7R

X7R 16V

16V

2

C385

0.1U

1

X7R

X7R 16V

16V

2

C387

C386

C388

0.1U

1

X7R

16V

LS2_1040

1 2

PC217

1 2

C43

C31

C49

22uF_0805_6.3V

CPU_VDD_RUN

1

+

PC218

2

330U_2.5V_R9mOHM

1

0.7 - 1.3 V 36A

VIN2

LS2_1040

1

+

PC220

2

330U_2.5V_R9mOHM

1 2

CPU_VDD_RUN

1

+

PC221

2

330U_2.5V_R9mOHM

CPU_VDD_RUN

1 2

C50

C52

C45

C48

22uF_0805_6.3V

A A

Bitland Information Techonogy Co.,Ltd.

Bitland Information Techonogy Co.,Ltd. Notebook R&D Division

Notebook R&D Division

CPU CORE PWR

BM5016

Notebook R&D Division

Sheet of

Rev

1.0

Title

Size

Document Number

Size

Document Number

Size

Document Number

Date:

Thursday, August 05, 2010 54D8

5

4

3

2

Thursday, August 05, 2010 54D8

1

5

+3.3VDual

D D

+3.3VDual

PR143

PR143 NC_10K_J

NC_10K_J

0402

PR97

1 2

NC_1K_F

0402

VDDIO_SUS_EN_EC49

SLP_S5#11,27,46,49

C C

1 2 1 2

PR92

PR92 1K_F

1K_F

0402

PC83

0603_X5R

NC_1U_10V_K

12

PC78

0402_NPO

NC_100P_50V_K

PR93

1 2

12

0402

120K_F

PR89

PR89 10K_J

10K_J

0402

1 2

DDR_TRIP DDR_S5 DDR_VFB

DDR_RF

12

PR94

PR96

PR96 10K

10K

0402

PR103

PR103 NC_0_F

NC_0_F

0402

1 2 3 4 5

TPS51218DSCR

null

0402

100K_F

PU3

PGOOD TRIP EN VFB RF

VDRAM_PWRGD 49

11

GND

10

VBST

9

DRVH

8

SW

7

V5IN

6

DRVL

12

PC84

4.7U_10V_K

0805_X5R

4

DDR_BST DDR_DH DDR_LX

DDR_DL

PC77

0.1U_25V_M

0603_X5R

12

PR98

11.5K_F

0402

1 2

PR90

PR90 0R

0R

0603

1 2

+5VDual

12

PR112

PR112 0R0603

0R0603

3

PJ7

+

PC81

330U_2V_7.3x4.3

1 2

jump_gap_open_161x54

PJ8

1 2

jump_gap_open_161x54

PJ9

1 2

jump_gap_open_161x54

12

0402_X5R

PC80

0.1U_6.3V_K

DDR_DCBATOUT

12

PC75

PC74

1206_X5R

0603_X5R

D

PQ29

S

SIR462DP-T1-GE3

5

D

4

G

S

231

SIR466DP-T1-GE3

R2860 200RR2860 200R

0.1U_25V_M

0603_X5R

10U_25V_M

NC_1UH +-20% FDV0630-1R0M=P3 12A

PL9

1 2

PL12

1.0UH_11.5x10.4

1 2

12

PR91

3.3_J

0603

PQ36

12

PC82

PC82 1000P_50V_M

1000P_50V_M

SIR466DP-T1-GE3

0603_X7R

update on rev:1.1

5

4

G

231

5

D

4

G

PQ30

S

231

CPU_VDDIO_SUS_FB_H16

R2853

200R

1206_X5R

Place these CAPS

PC76

close to FETs

10U_25V_M

12

+

DDR_OUT1

PC79

330U_2V_7.3x4.3

12

+VIN

Iocp=19.6A

12A

3A

CPU_VDDIO_SUS

2

1

B B

CPU_VDDIO_SUS

+3.3VDual

PR82

PR82 100K_J

100K_J

0402

1 2

0603_X5R

NC_1U_10V_K

61

D

Q50B

Q50B 2N7002DW-7-F

2N7002DW-7-F

G

2

S

12

4

PR267

PR267 0R

0R

0402

A A

5

SLP_S3#7,11,27,40,49,51

MEM_VTT_EN49

1 2

PR268

1 2

NC_0 0402

PC197

2A

PC199

12

4.7U_6.3V_K

4.7U_6.3V_K R576

0603_X5R

R576

100K_F

0402

12

R577

PC194

0603_X5R

1U_10V_K

100K_F

0402

1 2

34

D

Q50A

Q50A 2N7002DW-7-F

2N7002DW-7-F

G

5

S

PU4

1

VIN

2

GND2

3

REFEN

4

VOUT

RT9199GSP_SO8

12

0402_X5R

PC86

0.1U_6.3V_K

PC87

10U_6.3V_Y

0805_Y5V

10U_6.3V_Y

0805_Y5V

VCNTL

GND1

12

NC1

NC2

NC3

PC88

3

10U_6.3V_Y

0805_Y5V

10U_6.3V_Y

0805_Y5V

6

5

7

8

9

+0_75VRUN

2A

PJ10

1 2

jump_gap_open_161x54

1U_10V_K

PC98

MEM_VTT

12

0603_X5R

+3.3VDual

Bitland Information Techonogy Co.,Ltd.

Bitland Information Techonogy Co.,Ltd. Notebook R&D Division

Notebook R&D Division

1

BM5016

Notebook R&D Division

Sheet of

9

Rev

1.0

Title

CPU MEM PWR

Size

Document Number

Size

Document Number

Size

Document Number

C

Date:

Thursday, August 05, 2010 54

2

Thursday, August 05, 2010 54

5

4

3

2

1

32

C2946

C2946 100nF

100nF

DNI

Q2912

NC_2N7002E

CAP_7343

1

2

FB_VCC_NB-1

R2965

R2965 133K

133K

32

Q2908

1

2N7002E

参数待定

RS880M VCC_NB

When JU2903 is installed with a jumper

+1.1VP

12

+

PC172

PC170

CAP_7343

220UF/6.3V/18M 6R3ME221M

+1.1V

R2981 1kR2981 1k

1

C2144

2

1U_0603_10V4Z

1

+5VDUAL

PJ13

2

JUMP_43X118

R2982

R2982 10k

10k

Q2941

Q2941 MMBT3904

MMBT3904

2 3

112

GPIO Mode Power Shift

PWM

01STRP_DATA

0.95V

N/A

1.1VRS880M VCC_NB

0.95V 1.25V

+1.1VDUAL

+5VDUAL

R2987

R2987 10k

10k

32

Q2909

1

2N7002E

+1.2V_PWRGD 51

PC68

12

1U_0402_6.3V6K

12

4

VCC1

+5VDUAL

R1794

R1794 100K_0402_5%

100K_0402_5%

1 2

61

Q3638A

2

2N7002DW-T/R7_SOT363-6

1U_0402_6.3V6K

2.2_0603_1%

1 2

3

VCC2

0.1U_0402_16V7K

PR88

12

2

VIN2

1 2

+5VDUAL+5VDUAL

PC69

0.1U_0603_25V7K

PR110

10_0603_1%

12

PC73

1000P_0402_50V7K

1

GND_T

FSET2

PGOOD2

OCSET2

PHASE2

UGATE2

21

BST_+1.1V

PC93

PC93 1U_0402_6.3V6K

1U_0402_6.3V6K

12

@PC110

@

PC110

FB2

VO2

EN2

12

1 2

29

28

27

26

25

24

23

22

0_0603_5%

1 2

LG_+1.1V

12

@

NC_10U_0805_16V7K

ISL6228_B+

PR115

18.2K_0402_1%

1 2

+1.1VDUAL_EN

PC89

@PC89

@

nc_0.01U_0402_25V7K

1 2

UG_+1.1V

PR117

12

@

PC112

NC_10U_0805_16V7K

VLDT +1.1V

PC67

1U_0402_6.3V6K

PR87

2.2_0603_1%

+VIN

PJ15

JUMP_43X118

2

112

PJ12

D D

PJ12

JUMP_43X118

2

8.2K_0402_1%

1 2

PR111

112

ISL6228_B+

PC72

1000P_0402_50V7K

35K_0402_1%

12

PR95

PR104

3.3K_0402_5%

1 2

12

PC124

@PC124

@

nc_2200P_0402_50V7K

ISL6228_B++

12

PC104

PC105

1 2

12

4.7U_1206_25V6K

PR102

9.1K_0402_1%

PC105

4.7U_1206_25V6K

8

D36D45D27D1

S3

S2

S1

3

2

1

8

D36D45D27D1

G

S3

S2

S1

3

2

1

PC85

0.033U_0603_50V7K

1 2

VCC_NB

0.95V--1.1V 12A

PJ11

C C

2

JUMP_43X118

112

220U_6.3V_3528

6TPC47MB

VCC_NBP

12

PC34

+

12

+

220U_6.3V_3528

6TPC47MB

PC33

1UH_18A_20%

1 2

680P_0402_50V7K@

PL17

LS2_1040

4.7_1206_5%@

PR113

PC97

DCR 3.3m ohm(max) Cout ESR=15m ohm

+1.05VSP Vo=Vref*((PR80+PR82)/PR80) Ipeak=14.02A, Imax=9.81A Iocp=19A Csen=L/(Rocset*DCR)

0.015U=1U/(Rocset*6m) Rocset=11.111K~11.8K Iocp=(Rocset*10uA)/DCR Iocp=(11K*10uA)/(3.3m ohm*1.3) =15.1A

VCC_NBP

12

B B

A A

NC_0.1U_0402_16V7K

12

@PC95

@

PC95

PC109

@

PC109

@

NC_10U_0805_16V7K

VRM_PWRGD8,51

PC139

@PC139

@

nc_0.1u_0402_50V7K

PR107

60.4K_0402_1%

6228_VCC_NBO1

PQ23

PQ23 SI4172DY-T1-GE3

SI4172DY-T1-GE3

4

G

PQ22

PQ22 SI4168DY-T1-GE3

SI4168DY-T1-GE3

4

PC101

0.1U_0402_16V7K

ISL6228_B++

PR188

0_0402_5%

1 2

+1.2V_PWRGD

1 2

FB_VCC_NB-1FB_VCC_NB

OCSET_VCC_NB

VCC_NB_EN OCSET_+1.1V

LX_VCC_NB

UG_VCC_NB

PR116

0_0603_5%

12

PR178

@PR178

@

10K_0402_5%

1 2

PC71

1000P_0402_50V7K

8

FB1

9

VO1

10

OCSET1

11

EN1

12

PHASE1

13

UGATE1

12

14

BST_VCC_NB

BOOT1

+5VDUAL +5VDUAL

PC100

1U_0402_6.3V6K

LG_VCC_NB

VCC_NB_EN

12

PC103

@PC103

@

0.1U_0402_16V7K

+1.1V_EN

2.2_0603_1%

12

PC70

0.1U_0603_25V7K

PR106

10_0603_1%

12

PR108

22K_0402_1%

1 2

7

PGOOD1

6

FSET1

5

VIN1

Vref=0.6V

PU6

ISL6228HRTZ-T_QFN28_4X4

PVCC115LGATE116PGND117PGND218LGATE219PVCC220BOOT2

1 2

During Power Up 0 < 3.3v - 1.8v < 2.1v

VLDT_PWRGD#

PR189

@PR189

@

1K_0402_5%

1 2

12

R1801

100K_0402_5%

Updated on Rev2.0

NB_VOL_DET: 0: 0.95V / 1.1V 1:0.95V / 1.25V

NB_VOL_DET49

STRP_DATA23

R1822

0_0402_5%

1V1DUAL_PWRGD 49,51

FB_+1.1V-1 FB_+1.1V

6228_+1.1VO2

+5VDUAL

R2954 0RR2954 0R

PQ25

SI4172DY-T1-GE3

S_LX_+1.1V

PQ24

SI4168DY-T1-GE3

PC96

0.1U_0402_16V7K

1 2

+1.1VP

PC113

PJ20

2

112

JUMP_43X118

update on rev:1.1

8

D36D45D27D1

4

G

S3

S2

S1

3

2

1

8

D36D45D27D1

4

G

S3

S2

3

2

1

update on rev:1.1

VRM_PWRGD8,51

1V1_EN_EC49

+VSB

R2953 0R2953 0

PR101

56K_0402_1%

ISL6228_B+

12

S1

DCR 6m ohm(max) Cout ESR=15m ohm Vo=0.6*((PR87+PR83)/PR83)=1.8V

1.8VP Ipeak=11.93A, Imax=8.351A Csen=L/(Rocset*DCR)=1uF/(Rocset*6m ohm)=0.022uF =>Rocset=7.575K, Choose 10K because of thermal factor Iocp=(Rocset*10uA)/DCR=(10K*10uA)/(0.006*1.3)=12.82A

C2147

10U_0805_10V4Z

1 2

12

PC99

4.7U_1206_25V6K

12

PR109

@PR109

@

4.7_1206_5%

12

PC94

@PC94

@

680P_0402_50V7K

1

C2177

2

10U_0805_10V4Z

R1802

R1802 200K_0402_5%

200K_0402_5%

VLDT_PWRGD#

+5V

R3028 NC_33KR3028 NC_33K

R2972

R2972 NC_56K

NC_56K

12

@PC92

@

PC90

nc_2200P_0402_50V7K

4.7U_1206_25V6K

D2910RB751V-40 D2910RB751V-40

1 2

+1.1VDUAL

1

2

12

5

R3020

R3020 NC_4.7K

NC_4.7K

+5V

32

1

R29582KR2958 2K

PR99

3.3K_0402_5%

PR114

51K_0402_1%

1 2

20K_0402_1%

1 2

68nf_0603_50V7K

1 2

PC92

PC123

@PC123

@

nc_0.1u_0402_50V7K

PR105

15K_0402_1%

PL4

PL4 1uH/12A10mOHM

1uH/12A10mOHM

1 2

MHCI06030

+3.3V

R2996

R2996 47K

47K

R29240R DNI R29240R DNI

4

U64

5

7 8

SI4168_SO8

VLDT_GATE

3

Q3638B

Q3638B 2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

4

R3027

R3027 NC_56.2K

NC_56.2K

1

R2966

R2966 47K

47K

Q2917

2N7002E

PC91

1000P_0402_50V7K

12

1 2

PR100

PC102

220UF/6.3V/18M 6R3ME221M

+1.1V_EN

VLDT 1.1V 2A

36 2 1

C2146

10U_0805_10V4Z

1

C2145

0.1U_0603_25V7K

2

Bitland Information Techonogy Co.,Ltd.

Bitland Information Techonogy Co.,Ltd. Notebook R&D Division

Notebook R&D Division

1

Notebook R&D Division

BM5016

Sheet of

Rev

1.0

10

Title

1V1DUAL/VLDT/VCC_NB/+1.1V

Size

Document Number

Size

Document Number

Size

Document Number

Custom

Thursday, August 05, 2010 54

Date:

5

4

3

2

Date:

5

12

PC164

@PC164

@

1U_0402_16V7K

D D

1V8_PWRGD51

1

C2130

C2131

10U_0805_10V4Z

1

+3.3VDUAL

32

+VSB

C2141

10U_0805_10V4Z

R3055

R3055 100K

100K

Q3041

2N7002E

2

10U_0805_10V4Z

R1795

R1795 200K_0402_5%

200K_0402_5%

SUSP

1

C2142

2

10U_0805_10V4Z

C C

B B

SLP_S3#7,9,27,40,49,51

12

R1819

R1811

10K_0402_5%

NC_1K_0402_5%

R2974 0RR2974 0R

R2983 1KR2983 1K

SLP_S3#7,9,27,40,49,51

1U_0402_16V7K

update rev:1.1

+5DUAL TO +5V

+5VDUAL +5V

U61

5

7 8

1

SI4800BDY-T1-E3_SO8

2

12

61

Q31A

2

2N7002DW-T/R7_SOT363-6

+3VDUALTO +3.3V

+3.3VDUAL +3.3V

U63

5

7 8

1

SI4800BDY-T1-E3_SO8

2

SUSP

U2904

7

POK

VOUT1

APL5912

8

EN

GND

12

1

12

R1827

PC189

10K_0402_5%

@

4

36 2

1

C2132

10U_0805_10V4Z

2

5V/3.3V_GATE

1

C2137

NC_0.1U_0603_25V7K

2

update on rev:1.1

4

36 2

1

C2139

10U_0805_10V4Z

2

5V/3.3V_GATE

CPU_VDD_RUN +5V

R3058

R3058 100R

100R

32

Q3040

1

2N7002E

C3013

R3053

100nF

100R

32

Q3030

1

2N7002E

6

VIN

VCNTL

VOUT

FB

vin1

9

update rev:1.1

1

C2133

2

1U_0603_10V4Z

1

C2140

2

1U_0603_10V4Z

R2975 10R2975 10

5

3 4

2

12K_0402_5%

CPU_VDDNB_RUN

1

4

+5VDUAL

+3.3VDUAL

12

PC188

@ <DEVICE>PC188

@ <DEVICE>

22U_1206_6.3V

12

R1810

PC190

1 2

15K_0402_5%

12

R1809

C2135

10U_0805_10V4Z

+VSB

R3040

R3040 100R

100R

32

Q3033

2N7002E

R3059

R3059 100R

100R

32

Q3039

2N7002E

@ <DEVICE>

NC_0.1U_0402_16V7K

22U_1206_6.3V

PC162

1 2

68P_0402_16V7K

@

CPU_VDDIO_SUS

1

C2143

2

10U_0805_10V4Z

12

R1796

R1796 200K_0402_5%

200K_0402_5%

5

1V8_PWRGD#

1V8_PWRGD51

+3.3V MEM_VTT

R3064

R3064 100R

100R

32

Q3032

1

2N7002E

+1.5V

R3060

R3060 100R

100R

32

Q3038

1

2N7002E

+1.8VP

2

12

PC187

@PC187

@

4

U62

5

7 8

SI4800BDY-T1-E3_SO8

+1.5V_GATE

3

Q30B

Q30B 2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

4

100K_0402_5%

1A

+1.8V

PJ25

112

JUMP_43X118

+1.5V

R3061

R3061 100R

100R

R3065

R3065 100R

100R

2

Q3034

2N7002E

Q3031

2N7002E

1

2

C2134

1U_0603_10V4Z

+5VDUAL

1 2

61

R2976 1kR29761k

1

2

R1792

R1792 100K_0402_5%

100K_0402_5%

Q30A

2N7002DW-T/R7_SOT363-6

1

CPU_VDDRVCC_NB VLDT

R3050

R3050 100R

100R

32

1

36 2 1

C2136

10U_0805_10V4Z

1

C2138

0.1U_0603_25V7K

2

1V8_PWRGD#

12

R1797

32

1

+1.8V +1.1V

32

1

Q3029

2N7002E

3

+5VDUAL

R2988

R2988 10k

10k

R2989 0R2989 0

Q3048

2N7002E

1V5_PWRGD 51

+VIN

PR34

PR34 0_0402_5%

0_0402_5%

1

+3.3VDUAL

12

PC121

PC121 NC_10uF/6.3V,X5R_+1.5V

NC_10uF/6.3V,X5R_+1.5V

C0805

1 2

PR151

PR151 NC_10K,5%_+1.5V

NC_10K,5%_+1.5V

R0402

12

PC19

@

0.22U_0402_16V7K

3

C525

C525 NC_0.01uF/10V,X7R_+1.5V

NC_0.01uF/10V,X7R_+1.5V

1 2

C0603

PU10 APL5312-15B_+1.5VPU10 APL5312-15B_+1.5V

VIN1VOUT

SHDN#

V3V5DUAL_PWRGD13,49

1

+5VDUAL

Q2940

Q2940 MMBT3904

MMBT3904

2 3

32

R2977

R2977 10k

10k

1

FOR SB820M 15MA

R3062

R3062 100R

100R

32

Q3037

2N7002E

R3066

R3066 100R

100R

32

Q3042

1

2N7002E

PR29

100K_0402_1%

PR31

22K_0402_1%

1 2

32

Q3049

2N7002E

Updata on rev:1.3

BP

GND

2

DEL +1.5V

2

12

5

4

C518

C518 NC_0.01uF/10V,X7R+1.5V

NC_0.01uF/10V,X7R+1.5V

1 2

C0603

12

PC16

@

nc_0.22U_1206_25V7K

PJ17

12

PC122

PC122 NC_1UF/16V,X7R_+1.5V

NC_1UF/16V,X7R_+1.5V

C0402

与

PQ3

TP0610K-T1-E3_SOT23-3

2

112

JUMP_43X118

LDO

之间的切换

13

+1.5VDUAL

21

D47

D47 NC_1N5819

NC_1N5819

SOD123

1

PJ14

2

JUMP_43X118

R3063 0RR3063 0R

+VSB

112

CPU_VDDIO_SUS+5VDUAL

R3057

R3057 100R

100R

R3056

R3056 100K

100K

32

Q3036

1

2N7002E

32

Q3035

1

2N7002E

C3011

C3011 100nF

100nF

+VSBP

12

PC17

@

nc_0.1U_0603_25V7K

SLP_S5#9,27,46,49

A A

Bitland Information Techonogy Co.,Ltd.

Bitland Information Techonogy Co.,Ltd. Notebook R&D Division

Notebook R&D Division

Title

1.5V/1.5VDUAL/1.8V/3.3V/5V

Size

Document Number

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Document Number

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Document Number

Custom

Date:

Thursday, August 05, 2010 54

5

4

3

2

Thursday, August 05, 2010 54

Notebook R&D Division

Rev

1.0

BM5016

Sheet of

1

1.0

11

5

D D

C C

4

3

2

1

B B

A A

Bitland Information Techonogy Co.,Ltd.

Bitland Information Techonogy Co.,Ltd. Notebook R&D Division

Notebook R&D Division

1

BM5016

Notebook R&D Division

Sheet of

12

Rev

1.0

Title

//

Size

Document Number

Size

Document Number

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Document Number

C

Date:

Thursday, August 05, 2010 54

5

4

3

2

Thursday, August 05, 2010 54

5

4

3

2

1

+3.3VALW

D D

参数设定：

ADD RESISTOR TO GET -5% LOWER FOR +3.3V(3.1626V)

VDC_TPS51125

12

PC125

PC125 10uF/25V,X7R

10uF/25V,X7R

C1206

C C

C1206

Iocp=10.8A

PL1

+3VALWP +5VALWP+3.3VDUAL

PJ4

2

112

JUMP_43X118

PC156

PC156 220UF/6.3V/18M 6R3ME221M

220UF/6.3V/18M 6R3ME221M

CAP_7343

B B

12

+

共

C730

0.1uF/25V,X5R

C0402

.

+3VALWP

Lay

+3VALWP

PL1

1 2

4.7uH/5.5A/15mOHM

MHCI06030

C367

0.1uF/25V,X5R

C0402

.

PJ26

112

JUMP_43X118

C691

0.1uF/25V,X5R

C0402

.

PR42

4.7F

0603

PC39

PC39 680P_50V_M_B

680P_50V_M_B

0402

C364

0.1uF/25V,X5R

C0402

.

+VIN

2

C663

C663 1000PF/50V,NPO

1000PF/50V,NPO

C0402

.

8

PQ50

PQ50 AO4468

AO4468

SO8_50_150

123

8

PD16

PD16 NC_1N4148WS

NC_1N4148WS

SOD323

1 2

1

1 2

C365

0.1uF/25V,X5R

C0402

.

123

Vo1=5.01V ;Vo2=3.3V

R526

NC_110K,1%

R0402

+3.3VALW

567

D

4

G

S

R541

10K

R0402

567

D

4

G

S

PQ38

PQ38 AO4468

AO4468

SO8_50_150

C729

0.1uF/25V,X5R

C0402

.

+3VALWP

R543

R543 13K,1%

13K,1%

R0402

R518

R518 20K,1%

20K,1%

R0402

R1813

R1813 0R

0R

R0402

C659

4.7uF/10V,Y5V

C0805

C657

0.1uF/25V,X7R

C0603

PR44

PR44 0R

0R

0603

C731

C731 220pF/50V,X7R

220pF/50V,X7R

C0402

PR24

取值，

7

8

9

12

10

11

12

R522

NC_620K

R0402

EN V3AL

PR24

PR24 147K

147K

R0402

EN_V3AL_TPS51125

VO2

VREG3

VBST2

DRVH2

LLS

DRVL2

的网络名

REF

R538

R538 NC_0

NC_0

R0402

6

R5050RR505 0R

REF

R539

R539 0R

0R

R0402

C186

C186 1uF/25V,X5R

1uF/25V,X5R

C0805

C0805 .

.

REF

3

4

5

VFB2

ENTRIP2

UP6182AQAG/TPS51125

EN013SKIPSEL14GND15VIN16VREG517VCLK

R521

R521 NC_10K

NC_10K

R0402

2

VFB1

VREF

TONSEL

U31

C185

C185 1uF/25V,X5R

1uF/25V,X5R

C0805

C0805 .

.

+VIN

改变

PR25

1

ENTRIP1

18

+5VALW

PR26

PR26 147K

147K

R0402

C656

C656 220pF/50V,X7R

220pF/50V,X7R

C0402

取值，

EN V5AL

EN_V5AL_TPS51125

GND1

VO1

PGOOD

VBST1

DRVH1

LL1

DRVL1

C187

C187 10uF/25V,X5R

10uF/25V,X5R

C0805

C0805 .

.

32

567

S

567

S

NC_10K ,5%

R0402

1

8

123

8

123

NOTE: H---> 5v L---> 4.65V

R527

C2979

C2979 NC_100nF

NC_100nF

C366

C366 1000PF/50V,NPO

1000PF/50V,NPO

.

. C0402

C0402

PQ51

PQ51 AO4468

AO4468

SO8_50_150

PD14

PD14 NC_1N4148WS

NC_1N4148WS

1

SOD323

+5VALWP

R525

R540

30.1K,1%

R0402

VFB1VFB2

的网络名改变

R520

20K,1%

R0402

25

24

23

22

21

20

19

1 2

PR45

PR45 0F

0F

0603

R504

R504 100K

100K

R0402

.

NC_220K,1%

R0402

Q2931

NC_2N7002E

V3V5DUAL_PWRGD 11,49

C184

0.1uF/25V,X7R

C0603

4

R542

R542 10K

10K

R0402

4

PQ52

PQ52 AO4468

AO4468

SO8_50_150

R525

D

G

D

G

Update on rev:1.1

C363

0.1uF/25V,X5R

.

. C0402

C0402

PL2

4.7uH/5.5A/15mOHM

1 2

MHCI06030

PR43

4.7,1%

0603

1 2

PC37

PC37 680P_50V_NPO

680P_50V_NPO

0402

1 2

C370

0.1uF/25V,X5R

C0402

.

R3024NC_0R R3024NC_0R

VDC_TPS51125+3.3VDUAL

SMARTVOLT2 27

12

PC111

PC111 10uF/25V,X7R

10uF/25V,X7R

C1206

C368

0.1uF/25V,X5R

C0402

.

Iocp=9.7A

PJ3

2

112

JUMP_43X118

12

+

PC157

PC157 220UF/6.3V/18M 6R3ME221M

220UF/6.3V/18M 6R3ME221M

CAP_7343

共

Lay

C369

0.1uF/25V,X5R

C0402

C761

0.1uF/25V,X5R

C0402

.

+5VDUAL

+5VALWP

C665

0.1uF/25V,X5R

C0402

.

+5VALW

PR30

PQ56

PQ56 100k

100k

3

2N7002

R0402

SOT23

2N7002

1

2

3

2

PC20

PC20 NC

NC

C0402

PD9 1N4148WS

1

VDD_DUAL_EN49

ALW_EN7

A A

1

SOD323

PD10 1N4148WS

1

SOD323

12

PJ1

JOPEN

JOPEN RESISTOR_1

RESISTOR_1 ns

ns

PR46

R0402

10

EN_V5AL EN_V3AL

PR33

PR33 100K

100K

R0402

PC29

PC29 1000pF/50V,X7R

1000pF/50V,X7R

C0402

PQ60

SOT23

EN_V5AL EN_V3AL

EN_V3AL_TPS51125EN_V5AL_TPS51125

PQ62

PQ62 2N7002

2N7002

SOT23

PC28

PC28 NC

NC

C0402

+5VALW

PR38

PR38 100k

3

2

100k

R0402

1

PQ63

3

2N7002

SOT23

1

2

Add Enable/OCP Circuit 090918

Bitland Information Techonogy Co.,Ltd.

Bitland Information Techonogy Co.,Ltd. Notebook R&D Division

Notebook R&D Division

1

BM5016

Notebook R&D Division

Sheet of

13

Rev

1.0

Title

SYSTEM PWR

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Document Number

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Date:

Thursday, August 05, 2010 54

5

4

3

2

Thursday, August 05, 2010 54

5

4

3

2

1

D D

HT_NB_CPU_CAD_H021 HT_NB_CPU_CAD_L021 HT_NB_CPU_CAD_H121 HT_NB_CPU_CAD_L121 HT_NB_CPU_CAD_H221 HT_NB_CPU_CAD_L221 HT_NB_CPU_CAD_H321 HT_NB_CPU_CAD_L321 HT_NB_CPU_CAD_H421 HT_NB_CPU_CAD_L421 HT_NB_CPU_CAD_H521 HT_NB_CPU_CAD_L521 HT_NB_CPU_CAD_H621 HT_NB_CPU_CAD_L621 HT_NB_CPU_CAD_H721 HT_NB_CPU_CAD_L721 HT_NB_CPU_CAD_H821 HT_NB_CPU_CAD_L821 HT_NB_CPU_CAD_H921 HT_NB_CPU_CAD_L921 HT_NB_CPU_CAD_H1021

C C

HT_NB_CPU_CAD_L1021 HT_NB_CPU_CAD_H1121 HT_NB_CPU_CAD_L1121 HT_NB_CPU_CAD_H1221 HT_NB_CPU_CAD_L1221 HT_NB_CPU_CAD_H1321 HT_NB_CPU_CAD_L1321 HT_NB_CPU_CAD_H1421 HT_NB_CPU_CAD_L1421 HT_NB_CPU_CAD_H1521 HT_NB_CPU_CAD_L1521

HT_NB_CPU_CLK_H021 HT_NB_CPU_CLK_L021 HT_NB_CPU_CLK_H121 HT_NB_CPU_CLK_L121

HT_NB_CPU_CTL_H021 HT_NB_CPU_CTL_L021 HT_NB_CPU_CTL_H121 HT_NB_CPU_CTL_L121

CPU_VLDT

CPU_VLDT 1.1V 1.5A

U100A

D1 D2 D3 D4

E3 E2 E1

F1 G3 G2 G1

H1

J1 K1 L3 L2 L1

M1

N3 N2 E5 F5 F3 F4

G5

H5 H3 H4 K3 K4 L5

M5 M3 M4

N5 P5

J3

J2

J5 K5

N1 P1 P3 P4

HT LINK

VLDT_A0 VLDT_A1 VLDT_A2 VLDT_A3

L0_CADIN_H0 L0_CADIN_L0 L0_CADIN_H1 L0_CADIN_L1 L0_CADIN_H2 L0_CADIN_L2 L0_CADIN_H3 L0_CADIN_L3 L0_CADIN_H4 L0_CADIN_L4 L0_CADIN_H5 L0_CADIN_L5 L0_CADIN_H6 L0_CADIN_L6 L0_CADIN_H7 L0_CADIN_L7 L0_CADIN_H8 L0_CADIN_L8 L0_CADIN_H9 L0_CADIN_L9 L0_CADIN_H10 L0_CADIN_L10 L0_CADIN_H11 L0_CADIN_L11 L0_CADIN_H12 L0_CADIN_L12 L0_CADIN_H13 L0_CADIN_L13 L0_CADIN_H14 L0_CADIN_L14 L0_CADIN_H15 L0_CADIN_L15

L0_CLKIN_H0 L0_CLKIN_L0 L0_CLKIN_H1 L0_CLKIN_L1

L0_CTLIN_H0 L0_CTLIN_L0 L0_CTLIN_H1 L0_CTLIN_L1

SOCKET_638_PIN

VLDT_B0 VLDT_B1 VLDT_B2 VLDT_B3

L0_CADOUT_H0

L0_CADOUT_L0

L0_CADOUT_H1

L0_CADOUT_L1

L0_CADOUT_H2

L0_CADOUT_L2

L0_CADOUT_H3

L0_CADOUT_L3

L0_CADOUT_H4

L0_CADOUT_L4

L0_CADOUT_H5

L0_CADOUT_L5

L0_CADOUT_H6

L0_CADOUT_L6

L0_CADOUT_H7

L0_CADOUT_L7

L0_CADOUT_H8

L0_CADOUT_L8

L0_CADOUT_H9

L0_CADOUT_L9 L0_CADOUT_H10 L0_CADOUT_L10 L0_CADOUT_H11 L0_CADOUT_L11 L0_CADOUT_H12 L0_CADOUT_L12 L0_CADOUT_H13 L0_CADOUT_L13 L0_CADOUT_H14 L0_CADOUT_L14 L0_CADOUT_H15 L0_CADOUT_L15

L0_CLKOUT_H0

L0_CLKOUT_L0

L0_CLKOUT_H1

L0_CLKOUT_L1

L0_CTLOUT_H0

L0_CTLOUT_L0

L0_CTLOUT_H1

L0_CTLOUT_L1

AE2 AE3 AE4 AE5

AD1 AC1 AC2 AC3 AB1 AA1 AA2 AA3 W2 W3 V1 U1 U2 U3 T1 R1 AD4 AD3 AD5 AC5 AB4 AB3 AB5 AA5 Y5 W5 V4 V3 V5 U5 T4 T3

Y1 W1 Y4 Y3

R2 R3 T5 R5

CPU_VLDT

HT_CPU_NB_CAD_H0 21 HT_CPU_NB_CAD_L0 21 HT_CPU_NB_CAD_H1 21 HT_CPU_NB_CAD_L1 21 HT_CPU_NB_CAD_H2 21 HT_CPU_NB_CAD_L2 21 HT_CPU_NB_CAD_H3 21 HT_CPU_NB_CAD_L3 21 HT_CPU_NB_CAD_H4 21 HT_CPU_NB_CAD_L4 21 HT_CPU_NB_CAD_H5 21 HT_CPU_NB_CAD_L5 21 HT_CPU_NB_CAD_H6 21 HT_CPU_NB_CAD_L6 21 HT_CPU_NB_CAD_H7 21 HT_CPU_NB_CAD_L7 21 HT_CPU_NB_CAD_H8 21 HT_CPU_NB_CAD_L8 21 HT_CPU_NB_CAD_H9 21

HT_CPU_NB_CAD_L9 21 HT_CPU_NB_CAD_H10 21 HT_CPU_NB_CAD_L10 21 HT_CPU_NB_CAD_H11 21 HT_CPU_NB_CAD_L11 21 HT_CPU_NB_CAD_H12 21 HT_CPU_NB_CAD_L12 21 HT_CPU_NB_CAD_H13 21 HT_CPU_NB_CAD_L13 21 HT_CPU_NB_CAD_H14 21 HT_CPU_NB_CAD_L14 21 HT_CPU_NB_CAD_H15 21 HT_CPU_NB_CAD_L15 21

HT_CPU_NB_CLK_H0 21 HT_CPU_NB_CLK_L0 21 HT_CPU_NB_CLK_H1 21 HT_CPU_NB_CLK_L1 21

HT_CPU_NB_CTL_H0 21 HT_CPU_NB_CTL_L0 21 HT_CPU_NB_CTL_H1 21 HT_CPU_NB_CTL_L1 21

DEL HTPA Soft-Touch Duo Connectors

B B

VLDT CPU_VLDT

R183

0.001R_1W

C335

C335 10uF

10uF

C101

4.7uF

C102

C102 22uF

22uF

C103

C103 220nF

220nF

C104

C104 220nF

220nF

Place close to socket

* If VLDT is connected only on one side, one 4.7uF cap should be added to

A A

the island side

5

C105

C105 180pF

180pF

C106

C106 180pF

180pF

T26

P26

E26

D26

B25

D25

C25

E25

D24

B24

E24

A24

C24

B23

D23

A23

E23

C23

B22

D22

C22

A22

E22

C21

B21

D21

A21

E21

B20

D20

E20

A20

C20

B19

D19

C19

A19

E19

C18

B18

A18

D18

E18

E17

B17

C17

A17

D17

B16B3H16

E16

D16

A16

C16

B15

D15

E15

A15

C15

B14

C14

A14

D14

E14

D13

C13

E13

A13

B13

D12

B12

A12

C12

E12

A11

B11 AB11

E11

D11

C11

B10

A10

E10

D10

C10

A9

E9

B9

D9

C9

B8

E8

D8

A8

C8

C7

E7

B7

D7

A7

E6

C6

D6

A6

B6

E5

D5

C5

A5

B5

E4

B4

A4

C4

D4

E3

C3

A3

E2

C2

D2

D1

C1

E1

A1

4

W26

K26

R26

G26

V26

J26

L26

U26

F26

M26C26

N26

H26

T25

J25

W25

M25

H25

U25

P25

F25

G25

V25

K25

N25

L25

R25

T24

J24

K24

M24

H24

U24

F24

N24

G24

P24

W24

L24

R24

V24

F23

J23

H23

M23

U23

L23

R23

V23P23

G23

N23

W23

T23

K23

G22

F22

M22

U22

T22

W22

H22

V22

N22

R22

J22

K22

L22

P22

G21

M21

U21

W21

V21

T21

P21

H21

J21

N21

R21

F21

K21

L21

H20

L20

M20

T20

U20

V20

K20

P20

F20

N20

R20

J20

L19

H19

F19

K19

U19N19

V19J19 P19

R19

M19

K18

T18

M18

H18

L18

P18

R18

V18

U18

N18

F18

G18

W18

J18

V17

H17

M17

T17

P17

R17

F17

U17

N17

K17

W17

G17

L17

J17

P16

M16

T16

F16

K16

R16

V16

L16

N16

G16

W16

U16

J16

G15

F15

U15

T15

W15

V15

L15

K15

H14

W14

T14

L14

K14

V14

G14

J14

U14

F14

J13

K13

T13

W13

H13

L13

U13

F13

G13

V13

U12

W12

L12

H12

T12

F12

J12

K12

G12

V12

W11

R11

N11

P11

F11

T11

G11 AD11

K11

U11

M11

J11

H11

L11 AE11

V11

V10

P10 AA10

R10

T10 AE10

J10

G10

W10

N10

F10

U10

L10

K10

H10

M10

H9

F9

L9

G9

K9

U9W8W9

N9 P9

V9

R9

T9

M9

J9

L8

K8

F8

U8N8

M8

R8

T8

H8

V8

P8

J8

R7

V7R6AA7

J7

T7

K7

M7

W7

L7

U7

N7

F7

P7

H7

P6

L6

F6

T6

V6

M6

N6

K6

W6

G6

J6

H6

U6

N5K3F5

L5

H5

T5

M5

V5

W5

K5

P5

J5

G5

R5

U5

J4

F4

K4

T4

R4

U4

W4

H4

V4

N4

P4G4

L4

M4

P3

N3

G3

L3

J3 W3

F3

T3

M3

V3D3

H3

U3

R3

P2

F2

N2

K2

J2

L2

W2

M2

H2

U2

R2 V2

G2

T2

U1

R1

H1

J1

K1

L1

M1

T1

V1

P1

F1

N1

G1

W1

BGA638_50_26SQ_S1G3_OEM

AD26

AC26

Y26

AA26

AB26

AE25

AD25

AB25

AC25

AA25

Y25

AA24

AB24

AF24

AD24

AC24

AE24

Y24

AF23

AD23

AA23

AC23

AE23

AB23

Y23

AA22

AB22

Y22

AF22

AD22

AC22

AE22

AB21

AF21

Y21

AC21

AD21

AA21

AE21

Y20

AF20

AD20

AA20

AE20

AB20

AC20

AC19

AE19

AF19T19

Y19

AB19

AA19

AD19

AE18

AC18

AB18

AD18

AA18

AF18

Y18

AE17

AB17

AD17

AA17

AF17

Y17

AC17

Y16

AB16

AD16

AF16

AA16

AC16

AE16

AD15

AC15

AF15

AA15

AE15H15

Y15

AB15J15

AB14

AF14

AC14

AA14

AE14

AD14

Y14

AB13

AD13

AA13

AE13

Y13

AC13

AF13

AB12

AC12

AA12

Y12

AD12

AF12

AE12

AA11

AC11

Y11

AF11

AC10

Y10

AD10

AB10

AF10

AA9

Y9

AB9

AC9

AE9

AD9

AF9

AC8

AE8

AD8

AF8

AA8

AB8

AB7

AD7

AF7

AE7

AC7

Y6

AB6

AD6

AF6

AE6

AA6

AC6

AF5

AB5

AD5

AE5

AA5

AC5

Y5

Y4

AB4

AF4

AA4

AC4

AE4

AD4

AB3

Y3

AE3

AD3

AA3

AC3

AD2

AC2

Y2

AA2

AB2

AE2

AD1

AB1

AC1

AA1

Y1

Title

S1G4 HT I/F

Size

Document Number

Size

Document Number

Size

Document Number

Custom

Date:

Thursday, August 05, 2010 54

3

2

Thursday, August 05, 2010 54

Bitland Information Techonogy Co.,Ltd.

Bitland Information Techonogy Co.,Ltd. Notebook R&D Division

Notebook R&D Division

BM5016

Sheet of

14

1

Rev

1.0

A

B

C

D

E

Processor Memory Interface

U100C

MEM:DATA

MEM_MB_DATA[0..63]18

4 4

PLACE THEM CLOSE TO CPU WITHIN 1"

CPU_VDDIO_SUS

R100 0RR100 0R

C190

10uF

DNI

Updated on Rev2.0

3 3

2 2

R105 39.2RR105 39.2R R106 39.2RR106 39.2R

MEM_MA_RST#18

MEM_MA0_ODT018 MEM_MA0_ODT118

MEM_MA0_CS#018 MEM_MA0_CS#118

MEM_MA_CKE018 MEM_MA_CKE118

MEM_MA_CLK1_P18 MEM_MA_CLK1_N18

MEM_MA_CLK2_P18 MEM_MA_CLK2_N18

MEM_MA_ADD[0..15]18

MEM_MA_BANK[0..2]18 MEM_MB_BANK[0..2] 18

MEM_MA_RAS#18 MEM_MA_CAS#18 MEM_MA_WE#18

TP46TP46 TP47TP47

MEM_MA1_ODT0 MEM_MA1_ODT1

MEM_MA_ADD0 MEM_MA_ADD1 MEM_MA_ADD2 MEM_MA_ADD3 MEM_MA_ADD4 MEM_MA_ADD5 MEM_MA_ADD6 MEM_MA_ADD7 MEM_MA_ADD8 MEM_MA_ADD9 MEM_MA_ADD10 MEM_MA_ADD11 MEM_MA_ADD12 MEM_MA_ADD13 MEM_MA_ADD14 MEM_MA_ADD15

MEM_MA_BANK0 MEM_MA_BANK1 MEM_MA_BANK2

DEL ACE (margining tool) header

VDDR 1.05V 1.75A

D10

VDDR1

C10

VDDR2

B10

VDDR3

AD10

VDDR4

AF10

TP48TP48 TP49TP49

TP50TP50 TP51TP51 TP52TP52 TP53TP53

M_ZP M_ZN

AE10

H16

T19 V22 U21 V19

T20 U19 U20 V20

J22 J20

N19 N20 E16 F16 Y16

AA16

P19 P20

N21 M20 N22 M19 M22

L20

M24

L21

L19 K22 R21

L22 K20 V24 K24 K19

R20 R23

J21

R19 T22 T24

CPU_VDDIO_SUS

R107

1.00K

R108

1.00K

MEMZP MEMZN

MA_RESET_L

MA0_ODT0 MA0_ODT1 MA1_ODT0 MA1_ODT1

MA0_CS_L0 MA0_CS_L1 MA1_CS_L0 MA1_CS_L1

MA_CKE0 MA_CKE1

MA_CLK_H5 MA_CLK_L5 MA_CLK_H1 MA_CLK_L1 MA_CLK_H7 MA_CLK_L7 MA_CLK_H4 MA_CLK_L4

MA_ADD0 MA_ADD1 MA_ADD2 MA_ADD3 MA_ADD4 MA_ADD5 MA_ADD6 MA_ADD7 MA_ADD8 MA_ADD9 MA_ADD10 MA_ADD11 MA_ADD12 MA_ADD13 MA_ADD14 MA_ADD15

MA_BANK0 MA_BANK1 MA_BANK2

MA_RAS_L MA_CAS_L MA_WE_L

SOCKET_638_PIN

C109

C109 470nF_6.3V

470nF_6.3V

U100B

MEM:CMD/CTRL/CLK

VDDR_SENSE

MB_RESET_L

MB0_ODT0 MB0_ODT1 MB1_ODT0

MB0_CS_L0 MB0_CS_L1 MB1_CS_L0

MB_CLK_H5

MB_CLK_L5

MB_CLK_H1

MB_CLK_L1

MB_CLK_H7

MB_CLK_L7

MB_CLK_H4

MB_CLK_L4

MB_ADD10 MB_ADD11 MB_ADD12 MB_ADD13 MB_ADD14 MB_ADD15

MB_BANK0 MB_BANK1 MB_BANK2

CPU_M_VREF_SUS

C111

C111 10nF

10nF

W10

VDDR5

AC10

VDDR6

AB10

VDDR7

AA10

VDDR8

A10

VDDR9

Y10

W17

MEMVREF

B18

W26 W23 Y26

MEM_MB1_ODT0

V26 W25 U22

J25

MB_CKE0

H26

MB_CKE1

P22 R22 A17 A18 AF18 AF17 R26 R25

P24

MB_ADD0 MB_ADD1 MB_ADD2 MB_ADD3 MB_ADD4 MB_ADD5 MB_ADD6 MB_ADD7 MB_ADD8 MB_ADD9

MB_RAS_L MB_CAS_L

MB_WE_L

C112

C112 1nF

1nF

PLACE CLOSE TO CPU

MEM_MB_ADD0

N24

MEM_MB_ADD1

P26

MEM_MB_ADD2

N23

MEM_MB_ADD3

N26

MEM_MB_ADD4

L23

MEM_MB_ADD5

N25

MEM_MB_ADD6

L24

MEM_MB_ADD7

M26

MEM_MB_ADD8

K26

MEM_MB_ADD9

T26

MEM_MB_ADD10

L26

MEM_MB_ADD11

L25

MEM_MB_ADD12

W24

MEM_MB_ADD13

J23

MEM_MB_ADD14

J24

MEM_MB_ADD15

R24

MEM_MB_BANK0

U26

MEM_MB_BANK1

J26

MEM_MB_BANK2

U25 U24 U23

sensing point for op-amp feedback routed near CPU

CPU_VDDRCPU_VDDR

CPU_VDDR_SENSE 17

TP13TP13

TP14TP14 TP15TP15 TP16TP16 TP45TP45

MEM_MB_RST# 18

MEM_MB0_ODT0 18 MEM_MB0_ODT1 18

TP7TP7

MEM_MB0_CS#0 18 MEM_MB0_CS#1 18

MEM_MB_CKE0 18 MEM_MB_CKE1 18

MEM_MB_CLK1_P 18 MEM_MB_CLK1_N 18

MEM_MB_CLK2_P 18 MEM_MB_CLK2_N 18

MEM_MB_ADD[0..15] 18

MEM_MB_RAS# 18 MEM_MB_CAS# 18 MEM_MB_WE# 18

CPU_M_VREF_SUS

To reverse SODIMM socket

MEM_MB_DM[0..7]18

MEM_MB_DQS0_P18 MEM_MB_DQS0_N18 MEM_MB_DQS1_P18 MEM_MB_DQS1_N18 MEM_MB_DQS2_P18 MEM_MB_DQS2_N18 MEM_MB_DQS3_P18 MEM_MB_DQS3_N18 MEM_MB_DQS4_P18 MEM_MB_DQS4_N18 MEM_MB_DQS5_P18 MEM_MB_DQS5_N18 MEM_MB_DQS6_P18 MEM_MB_DQS6_N18 MEM_MB_DQS7_P18 MEM_MB_DQS7_N18

MEM_MB_DATA0 MEM_MB_DATA1 MEM_MB_DATA2 MEM_MB_DATA3 MEM_MB_DATA4 MEM_MB_DATA5 MEM_MB_DATA6 MEM_MB_DATA7 MEM_MB_DATA8 MEM_MB_DATA9 MEM_MB_DATA10 MEM_MB_DATA11 MEM_MB_DATA12 MEM_MB_DATA13 MEM_MB_DATA14 MEM_MB_DATA15 MEM_MB_DATA16 MEM_MB_DATA17 MEM_MB_DATA18 MEM_MB_DATA19 MEM_MB_DATA20 MEM_MB_DATA21 MEM_MB_DATA22 MEM_MB_DATA23 MEM_MB_DATA24 MEM_MB_DATA25 MEM_MB_DATA26 MEM_MB_DATA27 MEM_MB_DATA28 MEM_MB_DATA29 MEM_MB_DATA30 MEM_MB_DATA31 MEM_MB_DATA32 MEM_MB_DATA33 MEM_MB_DATA34 MEM_MB_DATA35 MEM_MB_DATA36 MEM_MB_DATA37 MEM_MB_DATA38 MEM_MB_DATA39 MEM_MB_DATA40 MEM_MB_DATA41 MEM_MB_DATA42 MEM_MB_DATA43 MEM_MB_DATA44 MEM_MB_DATA45 MEM_MB_DATA46 MEM_MB_DATA47 MEM_MB_DATA48 MEM_MB_DATA49 MEM_MB_DATA50 MEM_MB_DATA51 MEM_MB_DATA52 MEM_MB_DATA53 MEM_MB_DATA54 MEM_MB_DATA55 MEM_MB_DATA56 MEM_MB_DATA57 MEM_MB_DATA58 MEM_MB_DATA59 MEM_MB_DATA60 MEM_MB_DATA61 MEM_MB_DATA62 MEM_MB_DATA63

MEM_MB_DM0 MEM_MB_DM1 MEM_MB_DM2 MEM_MB_DM3 MEM_MB_DM4 MEM_MB_DM5 MEM_MB_DM6 MEM_MB_DM7

AA24 AA23 AD24 AE24 AA26 AA25 AD26 AE25 AC22 AD22 AE20 AF20 AF24 AF23 AC20 AD20 AD18 AE18 AC14 AD14 AF19 AC18 AF16 AF15 AF13 AC12 AB11

AE14 AF14 AF11 AD11

AB26 AE22 AC16 AD12

AC25 AC26 AF21 AF22 AE16 AD16 AF12 AE12

C11 A11 A14 B14

G11

E11 D12 A13 A15 A16 A19 A20 C14 D14 C18 D18 D20 A21 D24 C25 B20 C20 B24 C24 E23

E24 G25 G26

C26

D26 G23 G24

Y11

A12

B16

A22

E25

C12

B12

D16

C16

A24

A23

F26

E26

MB_DATA0 MB_DATA1 MB_DATA2 MB_DATA3 MB_DATA4 MB_DATA5 MB_DATA6 MB_DATA7 MB_DATA8 MB_DATA9 MB_DATA10 MB_DATA11 MB_DATA12 MB_DATA13 MB_DATA14 MB_DATA15 MB_DATA16 MB_DATA17 MB_DATA18 MB_DATA19 MB_DATA20 MB_DATA21 MB_DATA22 MB_DATA23 MB_DATA24 MB_DATA25 MB_DATA26 MB_DATA27 MB_DATA28 MB_DATA29 MB_DATA30 MB_DATA31 MB_DATA32 MB_DATA33 MB_DATA34 MB_DATA35 MB_DATA36 MB_DATA37 MB_DATA38 MB_DATA39 MB_DATA40 MB_DATA41 MB_DATA42 MB_DATA43 MB_DATA44 MB_DATA45 MB_DATA46 MB_DATA47 MB_DATA48 MB_DATA49 MB_DATA50 MB_DATA51 MB_DATA52 MB_DATA53 MB_DATA54 MB_DATA55 MB_DATA56 MB_DATA57 MB_DATA58 MB_DATA59 MB_DATA60 MB_DATA61 MB_DATA62 MB_DATA63

MB_DM0 MB_DM1 MB_DM2 MB_DM3 MB_DM4 MB_DM5 MB_DM6 MB_DM7

MB_DQS_H0 MB_DQS_L0 MB_DQS_H1 MB_DQS_L1 MB_DQS_H2 MB_DQS_L2 MB_DQS_H3 MB_DQS_L3 MB_DQS_H4 MB_DQS_L4 MB_DQS_H5 MB_DQS_L5 MB_DQS_H6 MB_DQS_L6 MB_DQS_H7 MB_DQS_L7

SOCKET_638_PIN

MEM:DATA

MA_DATA0 MA_DATA1 MA_DATA2 MA_DATA3 MA_DATA4 MA_DATA5 MA_DATA6 MA_DATA7 MA_DATA8

MA_DATA9 MA_DATA10 MA_DATA11 MA_DATA12 MA_DATA13 MA_DATA14 MA_DATA15 MA_DATA16 MA_DATA17 MA_DATA18 MA_DATA19 MA_DATA20 MA_DATA21 MA_DATA22 MA_DATA23 MA_DATA24 MA_DATA25 MA_DATA26 MA_DATA27 MA_DATA28 MA_DATA29 MA_DATA30 MA_DATA31 MA_DATA32 MA_DATA33 MA_DATA34 MA_DATA35 MA_DATA36 MA_DATA37 MA_DATA38 MA_DATA39 MA_DATA40 MA_DATA41 MA_DATA42 MA_DATA43 MA_DATA44 MA_DATA45 MA_DATA46 MA_DATA47 MA_DATA48 MA_DATA49 MA_DATA50 MA_DATA51 MA_DATA52 MA_DATA53 MA_DATA54 MA_DATA55 MA_DATA56 MA_DATA57 MA_DATA58 MA_DATA59 MA_DATA60 MA_DATA61 MA_DATA62 MA_DATA63

MA_DM0 MA_DM1 MA_DM2 MA_DM3 MA_DM4 MA_DM5 MA_DM6 MA_DM7

MA_DQS_H0 MA_DQS_L0 MA_DQS_H1 MA_DQS_L1 MA_DQS_H2 MA_DQS_L2 MA_DQS_H3 MA_DQS_L3 MA_DQS_H4 MA_DQS_L4 MA_DQS_H5 MA_DQS_L5 MA_DQS_H6 MA_DQS_L6 MA_DQS_H7 MA_DQS_L7

G12 F12 H14 G14 H11 H12 C13 E13 H15 E15 E17 H17 E14 F14 C17 G17 G18 C19 D22 E20 E18 F18 B22 C23 F20 F22 H24 J19 E21 E22 H20 H22 Y24 AB24 AB22 AA21 W22 W21 Y22 AA22 Y20 AA20 AA18 AB18 AB21 AD21 AD19 Y18 AD17 W16 W14 Y14 Y17 AB17 AB15 AD15 AB13 AD13 Y12 W11 AB14 AA14 AB12 AA12

E12 C15 E19 F24 AC24 Y19 AB16 Y13

G13 H13 G16 G15 C22 C21 G22 G21 AD23 AC23 AB19 AB20 Y15 W15 W12 W13

MEM_MA_DATA0 MEM_MA_DATA1 MEM_MA_DATA2 MEM_MA_DATA3 MEM_MA_DATA4 MEM_MA_DATA5 MEM_MA_DATA6 MEM_MA_DATA7 MEM_MA_DATA8 MEM_MA_DATA9 MEM_MA_DATA10 MEM_MA_DATA11 MEM_MA_DATA12 MEM_MA_DATA13 MEM_MA_DATA14 MEM_MA_DATA15 MEM_MA_DATA16 MEM_MA_DATA17 MEM_MA_DATA18 MEM_MA_DATA19 MEM_MA_DATA20 MEM_MA_DATA21 MEM_MA_DATA22 MEM_MA_DATA23 MEM_MA_DATA24 MEM_MA_DATA25 MEM_MA_DATA26 MEM_MA_DATA27 MEM_MA_DATA28 MEM_MA_DATA29 MEM_MA_DATA30 MEM_MA_DATA31 MEM_MA_DATA32 MEM_MA_DATA33 MEM_MA_DATA34 MEM_MA_DATA35 MEM_MA_DATA36 MEM_MA_DATA37 MEM_MA_DATA38 MEM_MA_DATA39 MEM_MA_DATA40 MEM_MA_DATA41 MEM_MA_DATA42 MEM_MA_DATA43 MEM_MA_DATA44 MEM_MA_DATA45 MEM_MA_DATA46 MEM_MA_DATA47 MEM_MA_DATA48 MEM_MA_DATA49 MEM_MA_DATA50 MEM_MA_DATA51 MEM_MA_DATA52 MEM_MA_DATA53 MEM_MA_DATA54 MEM_MA_DATA55 MEM_MA_DATA56 MEM_MA_DATA57 MEM_MA_DATA58 MEM_MA_DATA59 MEM_MA_DATA60 MEM_MA_DATA61 MEM_MA_DATA62 MEM_MA_DATA63

MEM_MA_DM0 MEM_MA_DM1 MEM_MA_DM2 MEM_MA_DM3 MEM_MA_DM4 MEM_MA_DM5 MEM_MA_DM6 MEM_MA_DM7

MEM_MA_DATA[0..63] 18

To normal SODIMM socket

MEM_MA_DM[0..7] 18

MEM_MA_DQS0_P 18 MEM_MA_DQS0_N 18 MEM_MA_DQS1_P 18 MEM_MA_DQS1_N 18 MEM_MA_DQS2_P 18 MEM_MA_DQS2_N 18 MEM_MA_DQS3_P 18 MEM_MA_DQS3_N 18 MEM_MA_DQS4_P 18 MEM_MA_DQS4_N 18 MEM_MA_DQS5_P 18 MEM_MA_DQS5_N 18 MEM_MA_DQS6_P 18 MEM_MA_DQS6_N 18 MEM_MA_DQS7_P 18 MEM_MA_DQS7_N 18

CPU_VDDR

C113

4.7uF

1 1

A

4.7uF

C114

4.7uF

C115

4.7uF

C116

4.7uF

C117

C117 220nF

220nF

Place close to socket

C119

C118

C118 220nF

220nF

C120

C120 220nF

220nF

B

C121

C121 1nF

1nF

C122

C122 1nF

1nF

C123

C123 1nF

1nF

C124

C124 1nF

1nF

C125

C125 180pF

180pF

C126

C126 180pF

180pF

C127

C127 180pF

180pF

C128

C128 180pF

180pF

Bitland Information Techonogy Co.,Ltd.

Bitland Information Techonogy Co.,Ltd. Notebook R&D Division

Notebook R&D Division

E

BM5016

Notebook R&D Division

15

Sheet of

Rev

1.0

Title

S1G4 DDRIII MEMORY I/F

Size

Document Number

Size

Document Number

Size

Document Number

Custom

Thursday, August 05, 2010 54

Date:

C

D

Date:

5

+5VDUAL

CPU_PWRGD26

CPU_LDT_STOP#23,26

3.3V

1U_0402_16V7K

U2911

2

EN

3

VIN

5

NC

SCLK249

SDATA249

SMBALERT#49

R2990 10R2990 10

+3.3V

12

C130

@C130

@

R1830

R1830 1K_0402_5%

1K_0402_5%

1 2

4

R1829

NC_10K_0402_5%

1 2

1

POK

VCNTL

UP7717ASU8_PSOP_8

6

VOUT

GND

8

+1.5V

800MA

22K_0402_5%

7

FB

GND1

9

10K_0402_5%

1 2

12

1 2

R1824

Keep net PWRGD, LDT_STOP#, LDT_RST# no stub

R187

R187 300R

300R

PWRGD

C337

C337 180pF

180pF

DNI

R191

R191 300R

300R

LDT_STOP#

RB501V-40

U103 is not used; CPU thermal control is based on TSI by default.

R2930R R2930R

R1825

PC168

27P_0402_16V7K

@

CPU_LDT_RST#26

C110

DNI

220pF

1

RB501V-40

TSI_CLK 49

TSI_DAT 49

R1320R DNI R1320R DNI

R1330R DNI R1330R DNI

VDDA_PWRGD 8,17

CPU_VDDIO_SUS

R221

2.2K

C179

DNI

220pF

Q118

23

MMBT3904

D107

21

D106

SCLK8VDD

7

SDATA

6

ALERT

5

GND

1

NC_ADM1032ARMZ

D D

PR238

+3.3V

12

@<DEVICE> PC207

@<DEVICE>

12

NC_100_J

PR237

12

100_J

DEL SB-TSI HEADER

VDDA_EN_EC49

PC207

22U_1206_6.3V

C C

B B

DEL SCAN Connector

A A

5

+1.5V

R193 300R

300R

R220

2.2K

C336

DNI

220pF

Q119

23

MMBT3904

1

21

U103

D+

D-

THERM

4

CPU_VDDA_2.5_RUN

+2.5V_LDO

12

AEP Head

+

100u

PC106

LDT_RST#

C176

C176 180pF

180pF

DNI

R268

2.2K

R298, R295's value is TBD.

R327NC_0R R327NC_0R R309NC_0R R309NC_0R

Q117

23

MMBT3904

+3.3VDUAL

R161

R161 0R

0R

DNI

1

C139 NC_100nFC139 NC_100nF

2

H_THRMDA

3

H_THRMDC

4

C182

2.2nF_50V

DNI

4

LAYOUT: ROUTE VDDA TRACE APPROX. 50 mils WIDE (USE 2x25 mil TRACES TO

FB26 26R_600mAFB26 26R_600mA

C183

C132

180pF

4.7UF

+1.8V

U4503

1

NC

5

VCC

2

INA

3

4

CPU_LDT_RST_HTPA#

GND

OUT Y

NC_TC7SZ07F

Update on rev:1.1

CPU_VDDIO_SUS

SCLK3 27

SDATA3 27

R2981KR298

R2951KR295

1K

R2940R R2940R

R3010R R3010R

R3140R R3140R

HDT pin24 can be VDDIO Level if only Purple Possum is used. For old HDT tool, 3.3v level shift is required. However, Purple Possum can tolerance 3.3v.

CPU_VDDIO_SUS

TP84TP84

CPU_DBREQ#

TP32TP32

CPU_DBRDY

TP59TP59 TP60TP60

CPU_TCK CPU_TMS

TP76TP76

CPU_TDI

TP77TP77

CPU_TRST#

TP81TP81

CPU_TDO

TP82TP82

TP83TP83

CPU_LDT_RST_HTPA#

TP85TP85

C133

C133 220nF

220nF

C138 NC_100nFC138 NC_100nF

supports AC couple & DC bias

R3251KR325 1K

CPU_SIC

CPU_SID

CPU_ALERT

C134

3.3NF

PLL bypass debug option

EXIT BALL FIELD) AND 500 mils LONG.

CPU_CLKP20

CPU_CLKN20

+3.3V

R126

R126 NC_4.7K

NC_4.7K

DEL

1.5V

DEL SB-TSI HEADER

Note. LDTREQ_L may be left unconnected as its function is not supported by the s1g4

place them to CPU within 1.5"

HDT Connector

C135 3.9NFC135 3.9NF

C136 3.9NFC136 3.9NF

CPU_VLDT

CPU_VDDIO_SUS

TP22TP22

3

CPU_VDDA_RUN

Keep trace from resisor to CPU within 0.6" keep trace from caps to CPU within 1.2"

CPU_CLKIN_SC_P CPU_CLKIN_SC_N

R173

R173 169R

169R

LDT_RST# PWRGD LDT_STOP# CPU_LDT_REQ#_CPU

CPU_SIC CPU_SID CPU_ALERT

R115 44.2RR115 44.2R R116 44.2RR116 44.2R

R258

R258 510R

510R

R254

R254 510R

510R

R1380RR138 0R

TP20TP20

CPU_VDD0_RUN_FB_H8 CPU_VDD0_RUN_FB_L8

CPU_VDD1_RUN_FB_H8 CPU_VDD1_RUN_FB_L8

CPU_DBRDY CPU_TMS CPU_TCK CPU_TRST# CPU_TDI

TP4TP4

CPU_TEST23_TSTUPD

CPU_TEST18_PLLTEST1

TP17TP17

CPU_TEST19_PLLTEST0

TP19TP19

CPU_TEST25_H_BYPASSCLK_H

CPU_TEST25_L_BYPASSCLK_L

CPU_TEST21_SCANEN

TP21TP21

CPU_TEST20_SCANCLK2

TP11TP11

TP9TP9

CPU_TEST24_SCANCLK1 CPU_TEST22_SCANSHIFTEN

TP10TP10

CPU_TEST12_SCANSHIFTENB

TP12TP12

CPU_TEST27_SINGLECHAIN

TP18TP18

CPU_TEST9_ANALOGIN CPU_TEST6_DIECRACKMON

CPU_HTREF0 CPU_HTREF1

DEL AEP HEAD

3

SB_PROCHOT#28

EC_PROCHOT#49

U100D

F8

VDDA1

F9

VDDA2

A9

TP33TP33

CLKIN_H

A8

TP34TP34

CLKIN_L

B7

TP41TP41

RESET_L

A7

TP42TP42

PWROK

F10

TP43TP43

LDTSTOP_L

THERMTRIP_L

C6

TP87TP87

TP39TP39 TP40TP40R193

TP35TP35 TP36TP36

PROCHOT_L

LDTREQ_L

AF4

SIC

AF5

SID

AE6

ALERT_L

R6

HT_REF0

P6

HT_REF1

F6

VDD0_FB_H

VDDIO_FB_H

E6

VDD0_FB_L

VDDIO_FB_L

Y6

VDD1_FB_H

VDDNB_FB_H

AB6

VDD1_FB_L

VDDNB_FB_L

G10

DBRDY

AA9

TMS

AC9

TCK

AD9

TRST_L

AF9

TDI

AD7

TEST23

H10

TEST18

G9

TEST19

E9

TEST25_H

E8

TEST25_L

AB8

TEST21

AF7

TEST20

AE7

TEST24

AE8

TEST22

AC8

TEST12

AF8

TEST27

C2

TEST9

AA6

TEST6

A3

RSVD1

A5

RSVD2

B3

RSVD3

B5

RSVD4

C1

RSVD5

SOCKET_638_PIN

CPU_SVC_R CPU_SVD_R PWRGD

Note: To override VID, Remove R192, R194, R196, install R165 set VID via SW100

BOOT VOLTAGE(VDD)

SVC

SVD

(CPUVRM_PRO# = VCC/GND)

0 0 1.1 1.1 0 1 1.0 1.2 1 0 0.9 1.0 1 1 0.8 0.8

VID OVERIDE TABLE (VDD)

Updata on rev:1.2

CPU_PROCHOT#_VDDIOCPU_PROCHOT#_VDDIOCPU_PROCHOT#_VDDIOCPU_PROCHOT#_VDDIO

R146NC_0R R146NC_0R

R1690R R1690R

Update on rev:1.1

R142 and Q110 is DNI, S1G4 does not support MEMHOT_L

M11

RSVD11

MEMHOT_L

THERMDC THERMDA

DBREQ_L

TEST28_H

TEST28_L

TEST17 TEST16 TEST15 TEST14

TEST10

TEST29_H

TEST29_L

RSVD10

TEST7

TEST8

RSVD9 RSVD8 RSVD7 RSVD6

VSS

SVC SVD

TDO

(CPUVRM_PRO# = OPEN)

W18

A6 A4

AF6 AC7 AA8

W7 W8

W9 Y9

H6 G6

E10

AE9

J7 H8

D7 E7 F7 C7

C3 K8

C4

C9 C8

H18 H19 AA7 D5 C5

CPU_VDDIO_SUS

CPU_SVC_R CPU_SVD_R

R1401KR140

1K

CPU_THERMTRIP#_VDDIO CPU_PROCHOT#_VDDIO

CPU_THERMDC CPU_THERMDA

TP44TP44 TP55TP55

TP54TP54 TP56TP56

CPU_DBREQ#

CPU_TDO

CPU_TEST28_H_PLLCHRZ_P CPU_TEST28_L_PLLCHRZ_N

CPU_TEST17_BP3 CPU_TEST16_BP2 CPU_TEST15_BP1 CPU_TEST14_BP0

CPU_TEST7_ANALOG_T CPU_TEST10_ANALOGOUT

CPU_TEST8_DIG_T

CPU_TEST29_H_FBCLKOUT_P

CPU_TEST29_L_FBCLKOUT_N

R184's value is TBD.

R157

R158

1K

DNI

VID Override Circuit

R141

300R

CPU_VDDIO_SUS_FB_H 9

CPU_VDDNB_RUN_FB_H 8 CPU_VDDNB_RUN_FB_L 8

route as differential as short as possible testpoint under package

TP6TP6 TP8TP8

TP61TP61 TP62TP62 TP63TP63 TP64TP64

TP25TP25 TP26TP26

TP27TP27

R184

80.6R

Route as 80ohm, diff

R1940R R1940R R1960R R1960R R1920R R1920R

2

CPU_VDDIO_SUS

R143

R143 10K

10K

1

Q108

Q108 MMBT3904

MMBT3904

2 3

H_THRMDC

R171NC_0R R171NC_0R

H_THRMDA

R172NC_0R R172NC_0R

Thermdc and Thermda should be routed away to VRM, crystal, etc. Customer should follow the MBDG. However, Guam is using TSI so this does not applies to Guam.

CPU_DBREQ# CPU_TEST27_SINGLECHAIN

TP23TP23

TP24TP24

CPU_TEST21_SCANEN CPU_TEST20_SCANCLK2 CPU_TEST24_SCANCLK1 CPU_TEST22_SCANSHIFTEN CPU_TEST12_SCANSHIFTENB CPU_TEST15_BP1 CPU_TEST14_BP0

CPU_TEST18_PLLTEST1 CPU_TEST19_PLLTEST0 CPU_TEST23_TSTUPD CPU_DBRDY

CPU_TEST10_ANALOGOUT

R147, R152 is installed ONLY when SCAN is enabled R215, R185 internal ONLY R162 is TBD

+1.5V

1K

R1601KR160

R1591KR159

R163 2.2KR163 2.2K

N$325218

N$325219

R197NC_220RR197NC_220R

R164NC_220RR164NC_220R

R165 220RDNIR165 220RDNI

Tek differential probing point

for normal operation open all switches

2

place them under CPU

TP37TP37

CPU_THERMTRIP# 27 CPU_PROCHOT#_VDDIO 26

DEL SB_CPU_THRMDA/ SB_CPU_THRMDC

CPU_VDDIO_SUS

R198 300RR198 300R R147 NC_1KR147 NC_1K

R185 300RDNIR185 300RDNI

R148 1KR148 1K R149 1KR149 1K R150 1KR150 1K R151 1KR151 1K R152 NC_1KR152 NC_1K R153 300RDNIR153 300RDNI R154 300RDNIR154 300RDNI

R155 1KR155 1K R156 1KR156 1K R162 1KDNIR162 1KDNI R166 300RDNIR166 300RDNI

R215 300RDNIR215 300RDNI

CPU_VLDT

TP31TP31

TP28TP28

CPU_SVC 8 CPU_SVD 8 CPU_PWRGD_SVID_REG 8

TP29TP29

TP30TP30

Update on rev:1.1

1

Title

S1G4 CTRL & DEBUG

Size

Document Number

Size

Document Number

Size

Document Number

Date:

Thursday, August 05, 2010 54D16

1

Bitland Information Techonogy Co.,Ltd.

Bitland Information Techonogy Co.,Ltd. Notebook R&D Division

Notebook R&D Division

BM5016

Sheet of

Rev

1.0

5

4

3

CPU_VDD_RUN

BOTTOM SIDE DECOUPLING

C143

C140

C140 22uF

22uF

C141

C141 22uF

22uF

C142

C142 22uF

22uF

C143 22uF

22uF

C144

C144 220nF

220nF

C145

C145 10nF

10nF

C146

C146 180pF

180pF

2

1

C334

0.22uF

CPU_VDD_RUN

C152

C157

C157 22uF

22uF

C151

C151 220nF

220nF

C158

C158 220nF

220nF

C152 10nF

10nF

C159

C159 220nF

220nF

C153

C153 180pF

180pF

C160

C160 180pF

180pF

C147

C147 22uF

22uF

CPU_VDDNB_RUN

C175

C154

22uF

C148

C149

22uF

CPU_VDDIO_SUS

C155

C155 22uF

22uF

C156

C156 22uF

22uF

C150

C150 22uF

22uF

DECOUPLING BETWEEN PROCESSOR AND DIMMs PLACE CLOSE TO PROCESSOR AS POSSIBLE

CPU_VDDIO_SUS

C168

C162

C177

4.7uF

0.22uF

VDDA_PWRGD8,16

VDDR_1.2_EN26

VDDR_1.2_EN: 1 : VDDR =1.05V 1.75A 0: VDDR = 0.9V 1.25 A (Default)

C163

4.7uF

R529 0RR529 0R

C526

2.2nF

DNI

C164

4.7uF

C165

C166

4.7uF

220nF

CPU_VDDIO_SUS

12

PC201

@ <DEVICE>PC201

@ <DEVICE>

22U_1206_6.3V

+3.3V

1U_0402_16V7K

C532 100nFC532 100nF

R536

R536 NC_10k

NC_10k

C167

C167 220nF

220nF

C168 220nF

220nF

12

@PC152

@

U2910

2

EN

3

VIN

5

NC

R534 33RR534 33R

PC152

4

VCNTL

VOUT

GND

8

10K_0402_5%

C531

C531 150PF

150PF

C169

C169 220nF

220nF

1

POK

UP7717ASU8_PSOP_8

6

7

FB

GND1

9

R1805

C170

C170 100nF

100nF

R2980 10R2980 10

12

C171

C171 10nF

10nF

R1807

1 2

1

32

+5VDUAL

R535

6.81K

C172

C172 180pF

180pF

10K_0402_5%

R1806

1 2

PC151

1 2

27P_0402_16V7K

@

Q501

Q501 2N7002E

2N7002E

C161

C4505

180pF

100nF

Note.. VDDR must be 1.05v nominal to support ddr3-1333. VDDR can be droped to 0.9v for DDR3-800 and DDR3-1066 to reduce power consumption

VDDR_1.2_EN: 1 : VDDR =1.05V 1.75A 0: VDDR = 0.9V 1.25 A (Default)

12

+

PC153

@PC153

PC154

@

100u

R532

R532 100R

100R

NC_0.1U_0402_16V7K

1.27K_0402_5%

CPU_VDDRP

2

PJ18

112

JUMP_43X118

Updata on rev:1.1

R5310R R5310R

CPU_VDDR

CPU_VDDR_SENSE 15

D D

U100F

AA4

VSS1

AA11

VSS2

AA13

VSS3

AA15

VSS4

AA17

VSS5

AA19

VSS6

AB2

VSS7

AB7

VSS8

AB9

VSS9

AB23

VSS10

U100E

G4 H2

J9 J11 J13 J15

K6

K10 K12 K14

L4

L7

L9

L11 L13 L15

M2 M6 M8

M10

N7 N9

N11

K16 M16 P16 T16 V16

H25

J17

K18 K21 K23 K25 L17 M18 M21 M23 M25 N17

U100E

VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 VDD_10 VDD_11 VDD_12 VDD_13 VDD_14 VDD_15 VDD_16 VDD_17 VDD_18 VDD_19 VDD_20 VDD_21 VDD_22 VDD_23

VDDNB_1 VDDNB_2 VDDNB_3 VDDNB_4 VDDNB_5

VDDIO1 VDDIO2 VDDIO3 VDDIO4 VDDIO5 VDDIO6 VDDIO7 VDDIO8 VDDIO9 VDDIO10 VDDIO11 VDDIO12

SOCKET_638_PIN

CPU_VDD_RUN

C C

CPU_VDDNB_RUN

CPU_VDDNB_RUN 4A

CPU_VDDIO_SUS

VDD_24 VDD_25 VDD_26 VDD_27 VDD_28 VDD_29 VDD_30 VDD_31 VDD_32 VDD_33 VDD_34 VDD_35 VDD_36 VDD_37 VDD_38 VDD_39 VDD_40 VDD_41 VDD_42 VDD_43 VDD_44 VDD_45 VDD_46 VDD_47 VDD_48 VDD_49

VDDIO27 VDDIO26 VDDIO25 VDDIO24 VDDIO23 VDDIO22 VDDIO21 VDDIO20 VDDIO19 VDDIO18 VDDIO17 VDDIO16 VDDIO15 VDDIO14 VDDIO13

P8 P10 R4 R7 R9 R11 T2 T6 T8 T10 T12 T14 U7 U9 U11 U13 U15 V6 V8 V10 V12 V14 W4 Y2 AC4 AD2

Y25 V25 V23 V21 V18 U17 T25 T23 T21 T18 R17 P25 P23 P21 P18

CPU_VDD_RUN

CPU_VDDIO_SUS

cpu_vddio_sus 3A

B B

AB25 AC11 AC13 AC15 AC17 AC19 AC21

AD25 AE11 AE13 AE15 AE17 AE19 AE21 AE23

AD6 AD8

B4 B6 B8

B9 B11 B13 B15 B17 B19 B21 B23 B25

D6 D8

D9 D11 D13 D15 D17 D19 D21 D23 D25

E4

F2 F11 F13 F15 F17 F19 F21 F23 F25

H7

H9 H21 H23

J4

VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65

SOCKET_638_PIN

VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98

VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129

J6 J8 J10 J12 J14 J16 J18 K2 K7 K9 K11 K13 K15 K17 L6 L8 L10 L12 L14 L16 L18 M7 M9 AC6 M17 N4 N8 N10 N16 N18 P2 P7 P9 P11 P17 R8 R10 R16 R18 T7 T9 T11 T13 T15 T17 U4 U6 U8 U10 U12 U14 U16 U18 V2 V7 V9 V11 V13 V15 V17 W6 Y21 Y23 N6

IF VDDIO plane is split, add two 0.22uf caps

A A

Bitland Information Techonogy Co.,Ltd.

Bitland Information Techonogy Co.,Ltd. Notebook R&D Division

Notebook R&D Division

1

BM5016

Notebook R&D Division

Sheet of

17

Rev

1.0

Title

S1G4 PWR & GND

Size

Document Number

Size

Document Number

Size

Document Number

C

Date:

Thursday, August 05, 2010 54

5

4

3

2

Thursday, August 05, 2010 54

Lenovo B465 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual