Lenovo 3000 G230 DDR3 Schematics

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SYSTEM DC/DC

Project code: 91.4K101.001 ZY LZ2

LZ2 Block Diagram

91.4J301.001 XR LX2 PCB P/N : 07260-SB Revision : SA

4 4

CLK GEN.

3

HOST BUS

DDR3 socket

15

DDR3 socket

3 3

INT MIC

SPR x2

MIC In

2 2

HP

RJ11

16

Codec

ALC269

(include AMP)

MODEM

MDC Card

800/1066MHz

AZALIA

25

24

Mobile CPU

Penryn SV 35W

800/1066MHz@1.05V

Cantiga

AGTL+ CPU I/F DDR Memory I/F

INTEGRATED GRAHPICS

LVDS, CRT I/F

8,9,10,11,12,13,14

X4 DMI 400MHz

C-Link0

ICH9M

6 PCIe ports PCI/PCI BRIDGE ACPI 1.1 4 SATA 12 USB

High Definition Audio LPC I/F Serial Peripheral I/F

19,20,21,22,23

4, 5

EMC2102

USB

PCIe

PCIe/ USB

LPC BUS

07

R.G.B

LVDS

Realtek RTS5158E

Cardreader

LAN

Boardcom 5906M

Mini Card

28

a/b/g/n

26

CRT

12"W LCD

31

18

17

SD/MMC/MS

RJ45

3 in 1

27

PCB 8-LAYER STACKUP

TOP

GND

S

PWR

S

GND

BOTTOM

28

TPS51120

INPUTS

DCBATOUT

5V_S5 3D3V_S5

SYSTEM DC/DC

TPS51124

INPUTS OUTPUTS

DCBATOUT

TPS51100

1D5V_S3

1D5V_S3 1D5V_S0

CHARGER

BQ24740

DCBATOUT

CPU DC/DC

INPUTS

DCBATOUT

1D05V_S0 1D5V_S3

DDR_VREF_S0 (1.5A)

DDR_VREF_S3

OUTPUTSINPUTS CHG_PWR

18V

UP+5V

5V 100mA

ADP3208

OUTPUTS

VCC_CORE

36

OUTPUTS

37

38

33

39

35

Finger Print

New card

31

PCI Express / USB

SATA

USB

32

BlueTooth

17

24

G-sensor

30

1 1

Power switch

31

SATA-HDD

24

SATA-ODD

24

CAMERA

USB 3 Port

32

KBC

Winbond

WPC776

Touch Pad

34 34

INT. KB

29

SPI I/F

BIOS

2M byte

34

LPC

DEBUG CONN.

24

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

BLOCK DIAGRAM

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet of

Date: Sheet

BLOCK DIAGRAM

LZ2

141Friday, April 11, 2008

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ICH9M Functional Strap Definitions

4 4

3 3

Signal

HDA_SDOUT

HDA_SYNC

GNT2#/ GPIO53

GPIO20

GNT1#/ GPIO51

GNT3#/ GPIO55

GNT0#: SPI_CS1#/ GPIO58

SPI_MOSI

GPIO49

SATALED#

SPKR

TP3

GPIO33/ HDA_DOCK _EN#

Usage/When Sampled Comment

XOR Chain Entrance/ PCIE Port Config1 bit1, Rising Edge of PWROK

PCIE config1 bit0, Rising Edge of PWROK.

PCIE config2 bit2, Rising Edge of PWROK.

Reserved Rising Edge of PWROK.

ESI Strap(Server Only) Rising edge of PWROK

Top-Block Swap Override. Rising Edge of PWROK.

Boot BIOS Destination Selection 0:1. Rising Edge of PWROK.

Integrated TPM Enable, Rising Edge of CLPWROK

DMI Termination Voltage, Rising Edge of PWROK.

PCI Express Lane Reversal. Rising Edge of PWROK.

No Reboot. Rising Edge of PWROK.

XOR Chain Entrance. Rising Edge of PWROK.

Flash Descriptor Security Override Strap Rising Edge of PWROK

Allows entrance to XOR Chain testing when TP3 pulled low.When TP3 not pulled low at rising edge of PWROK,sets bit1 of RPC.PC(Config Registers: offset 224h). This signal has weak internal pull-down

This signal has a weak internal pull-down. Sets bit0 of RPC.PC(Config Registers:Offset 224h)

This signal has a weak internal pull-up. Sets bit2 of RPC.PC2(Config Registers:Offset 0224h) This signal has a weak internal pull-down. Note:This signal should not be pulled high.

Tying this strap low configures DMI for SIcompatible operation. This signal has a weak internal pull-up. NOTE: ESI compatible mode is for server latforms only. This signal should not be pulled low for desktop and mobile.

Sampled low:Top-Block Swap mode(inverts A16 for all cycles targeting FWH BIOS space). Note: Software will not be able to clear the Top-Swap bit until the system is rebooted without GNT3# being pulled down.

Controllable via Boot BIOS Destination bit (Config Registers:Offset 3410h:bit 11:10). GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC.

Sample low: the Integrated TPM will be disabled. Sample high: the MCH TPM enable strap is sampled low and the TPM Disable bit is clear, the Integrated TPM will be enable.

The signal is required to be low for desktop applications and required to be high for mobile applications.

Signal has weak internal pull-up. Sets bit 27 of MPC.LR(Device 28:Function 0:Offset D8)

If sampled high, the system is strapped to the "No Reboot" mode(ICH9 will disable the TCO Timer system reboot feature). The status is readable via the NO REBOOT bit.

This signal should not be pull low unless using XOR Chain testing.

Sampled low:the Flash Descriptor Security will be overridden. If high,the security measures will be in effect.This should only be enabled in manufacturing environments using an external pull-up resister.

ICH9 EDS 642879 Rev.1.5

ICH9M Integrated Pull-up and Pull-down Resistors

SIGNAL Resistor Type/Value

CL_CLK[1:0] CL_DATA[1:0] CL_RST0# DPRSLPVR/GPIO16 ENERGY_DETECT HDA_BIT_CLK HDA_DOCK_EN#/GPIO33 HDA_RST# HDA_SDIN[3:0] HDA_SDOUT HDA_SYNC GLAN_DOCK#

GNT[3:0]#/GPIO[55,53,51]

GPIO[20] GPIO[49] LDA[3:0]#/FHW[3:0]# LAN_RXD[2:0] LDRQ[0] LDRQ[1]/GPIO23 PME# PWRBTN# SATALED#

SPI_CS1#/GPIO58/CLGPIO6

SPI_MOSI SPI_MISO SPKR TACH_[3:0] TP[3] USB[11:0][P,N]

The pull-up or pull-down active when configured for native GLAN_DOCK# functionality and determined by LAN controller

ICH9 EDS 642879 Rev.1.5

PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-DOWN 20K PULL-UP 20K PULL-DOWN 20K PULL-UP 20K PULL-DOWN 20K PULL-DOWN 20K PULL-DOWN 20K PULL-DOWN 20K

PULL-UP 20K PULL-DOWN 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 15K PULL-UP 20K PULL-DOWN 20K PULL-UP 20K PULL-DOWN 20K PULL-UP 20K PULL-UP 20K PULL-DOWN 15K

Cantiga chipset and ICH9M I/O controller Hub strapping configuration

Pin Name

CFG[2:0]

CFG[4:3] CFG8 CFG11 CFG[15:14] CFG[18:17]

CFG5 CFG6

CFG7

CFG9

CFG10 PCIE Loopback enable

CFG[13:12]

CFG16

CFG19

CFG20

SDVO_CTRLDATA

L_DDC_DATA

NOTE:

1. All strap signals are sampled with respect to the leading edge of the (G)MCH Power OK (PWROK) signal.

2. iTPM can be disabled by a 'Soft-Strap' option in the Flash-decriptor section of the Firmware. This 'Soft-Strap' is activated only after enabling iTPM via CFG6. Only one of the CFG10/CFG/12/CFG13 straps can be enabled at any time.

FSB Frequency Select

Reserved

DMI x2 Select iTPM Host

Interface

Intel Management engine Crypto strap

PCIE Graphics Lane

FSB Dynamic ODT

DMI Lane Reversal

Digital Display Port (SDVO/DP/iHDMI) Concurrent with PCIe

Montevina Platform Design guide 22339 0.5

Strap Description

XOR/ALL

SDVO Present

Local Flat Panel (LFP) Present

Configuration

000 = FSB1067 011 = FSB667 010 = FSB800 others = Reserved

0 = DMI x2

1 = DMI x4

0= The iTPM Host Interface is enabled(Note2)

1= The iTPM Host Interface is disalbed(default)

0 = Transport Layer Security (TLS) cipher suite with no confidentiality

1 = TLS cipher suite with confidentiality (default)

0 = Reverse Lanes,15->0,14->1 ect..

1= Normal operation(Default):Lane Numbered in order

0 = Enable (Note 3)

1= Disabled (default)

00 = Reserve 10 = XOR mode Enabled 01 = ALLZ mode Enabled (Note 3)

11 = Disabled (default)

0 = Dynamic ODT Disabled

1 = Dynamic ODT Enabled (Default) 0 = Normal operation(Default):

Lane Numbered in Order

1 = Reverse Lanes DMI x4 mode[MCH -> ICH]:(3->0,2->1,1->2and0->3) DMI x2 mode[MCH -> ICH]:(3->0,2->1)

0 = Only Digital Display Port or PCIE is operational (Default)

1 =Digital display Port and PCIe are operting simulataneously via the PEG port

0 = No SDVO Card Present (Default)

1 = SDVO Card Present

0 = LFP Disabled (Default)

1= LFP Card Present; PCIE disabled

(Default)

page 218

DCBATOUT17,33,35,36,37,39,41

2 2

SMBus

PCIE Routing

LANE1 BroadCom LAN LANE2 MiniCard WLAN LANE4 NewCard

History:

LAB: 2008/01/02

USB Table

USB

Pair

Device

0

JACK0

1

NC

2

JACK2

3

NC 4 BLUETOOTH 5

JACK1

Fringer Print6 7

Mini Card 8

CAMERA 9 NEW CARD 10 CARDREADER

NC11

ICH9M

KBC

SMBC_G792

THER_SCL

BAT_SCL

SMB_CLK

G7921

AV Panel

BATTERY

Mini Card

New Card

3D3V_AUX_S57,19,29,34,36,39,40

5V_AUX_S57,31,33,36,39

3D3V_S517,20,21,22,23,24,26,29,30,31,33,34,36,37,41

5V_S522,32,33,36,37,38,41

1D5V_S310,12,13,15,16,33,37,38,41

0D75V_S315,16,38

1D8V_S013,33,38

3D3V_S03,7,10,11,13,15,16,17,18,19,20,21,22,23,24,25,26,28,29,31,32,33,34,35,36,37,38,41

5V_S07,13,17,18,22,23,24,25,33,34,35,41

1D05V_S04,5,6,8,10,11,12,13,19,22,33,37

1D5V_S03,5,13,19,20,22,31,33

DCBATOUT

3D3V_AUX_S5

5V_AUX_S5

3D3V_S5

5V_S5

1D5V_S3

0D75V_S3

1D8V_S0

3D3V_S0

5V_S0

1D05V_S0

1D5V_S0

1 1

SMBC_ICH

CLK GEN

DDR II

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Reference

Size Document Number Rev

Size Document Number Rev C

C

C Date: Sheet

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

LZ2

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4 4

3 3

2 2

1 1

3D3V_S0

L16

BLM11A121S-GP

1 2

12

C332

SC1U10V3KX-3GP

Design Note:

1. All of Input pin didn't have internal pull up resistor.

2. Clock Request (CR) function are enable by registers.

3. CY28548 integrated serial resistor of differential clock, so put 0 ohm serial resistor in the schematic.

3D3V_S0_CK505

12

R198

R198 10KR2J-3-GP

10KR2J-3-GP

PCI2_TME

12

R197

R197 10KR2J-3-GP

10KR2J-3-GP

DY

3D3V_S0_CK505

12

R193

R193 10KR2J-3-GP

10KR2J-3-GP

12

R194

R194 10KR2J-3-GP

10KR2J-3-GP

DY

12

ITP_EN

C329

12

C321

C301

SCD1U16V2ZY-2GP

CLK_SATA_OE#21 CLKREQ_MCH#10

PCLK_FWH24

TP128 TPAD30TP128 TPAD30

PCLK_KBC29 CLK_PCI_ICH20

CLK_ICH1421

SCD1U16V2ZY-2GP

SC10U10V5ZY-1GP

PCI2_TME Output

0 Normal mode 1 Trusted mode

0 =overclocking enable 1 =overclocking unable

ITP_EN Output

0 SRC8 1 CPU_ITP

12

C333

SCD1U16V2ZY-2GP

A

C336

SCD1U16V2ZY-2GP

PCLK_PCM

12

C337

DY

3D3V_S0_CK505

12

SCD1U16V2ZY-2GP

12

C353SC4D7P50V2CN-1GPDYC353SC4D7P50V2CN-1GP

B

C327

SCD1U16V2ZY-2GP

12

C340SC4D7P50V2CN-1GP C340SC4D7P50V2CN-1GP

C338SC4D7P50V2CN-1GP C338SC4D7P50V2CN-1GP

SC33P50V2JN-3GP

12

C343

CLK48_ICH21

CLK_48M_R511828

R181 475R2F-L1-GPR181 475R2F-L1-GP

1 2

R196 475R2F-L1-GPR196 475R2F-L1-GP

1 2

R199 33R2J-2-GPR199 33R2J-2-GP

1 2

R200 33R2J-2-GPR200 33R2J-2-GP

1 2

R184 33R2J-2-GPR184 33R2J-2-GP

1 2

R185 33R2J-2-GPR185 33R2J-2-GP

1 2

R180 33R2J-2-GPR180 33R2J-2-GP

1 2

12

C352SC4D7P50V2CN-1GP C352SC4D7P50V2CN-1GP

CPU_BSEL24 CPU_BSEL14 CPU_BSEL04

C330 SC4D7P50V2CN-1GPC330 SC4D7P50V2CN-1GP

1 2

H_STP_PCI#21 H_STP_CPU#21

ICH_SMBCLK15,16,23

ICH_SMBDATA15,16,23

CK_PWRGD21

C342

R172

R172 R176 22R2J-2-GPR176 22R2J-2-GP

12

X3

X3 X-14D31818M-30GP

X-14D31818M-30GP

12

SC33P50V2JN-3GP

CLK_XTAL_IN

FSB FSC

ICS9LPRS355BKLFT-GP

71.09355.B03

3 2

17

45 44

7 6

63

8 10 11 12 13 14

64

5 55

CLK_XTAL_OUT

22R2J-2-GP

FSA

1 2 1 2

CLK_SATAREQ_OE# CLKREQ_MCH_R# PCI2_TME PCLK_PCM_R 27_SEL ITP_EN

MAIN SOURCE:71.09355.B03 SECOND SOURCE:71.00875.A03

Cypress Setting

FS_C FS_B FS_A CPU

1 0 1 100M 0 0 1 133M 0 1 0 200M 0 1 1 166M 0 0 0 266M

1 2

R179 10KR2J-3-GPR179 10KR2J-3-GP

1 2

R175 0R2J-2-GPR175 0R2J-2-GP

1 2

R165 2K2R2J-2-GPR165 2K2R2J-2-GP

R166 1KR2J-1-GPR166 1KR2J-1-GP

1 2

R167 1KR2J-1-GPR167 1KR2J-1-GP

1 2

R195 1KR2J-1-GPR195 1KR2J-1-GP

1 2

C

3D3V_S0_CK505

U33

4

X1 X2

USB_48MHZ/FSLA

PCI_STOP# CPU_STOP#

SCLK SDATA

CK_PWRGD/PD#

PCI0/CR#_A PCI1/CR#_B PCI2/TME PCI3 PCI4/27_SELECT PCI_F5/ITP_EN

FSLB/TEST_MODE REF0/FSLC/TEST_SEL

NC#55

18

default

16

VDDREF

GND48

15

VDD48

GNDPCI

9

VDDPCI

GNDREF

1

46

62

23

VDDSRC

VDDCPU

VDDPLL3

GND

GNDSRC

22

30

36

FSC FSB FSA

MCH_CLKSEL0 10 MCH_CLKSEL1 10 MCH_CLKSEL2 10

19

43

52

27

VDD96_IO

VDDSRC_IO

VDDPLL3_IO

27MHZ_NONSS/SRCT1/SE1

GND

GNDSRC

GNDCPU

26

49

59

33

56

VDDSRC_IO

VDDCPU_IO

CPUT2_ITP/SRCT8

CPUC2_ITP/SRCC8

SRCT7/CR#_F

SRCC7/CR#_E

SRCT11/CR#_H SRCC11/CR#_G

SRCT3/CR#_C SRCC3/CR#_D

SRCT2/SATAT

SRCC2/SATAC

27MHZ_SS/SRCC1/SE2

SRCT0/DOTT_96

SRCC0/DOTC_96

GND

65

C297

SC10U10V5ZY-1GP

CPUT0 CPUC0

CPUT1_F CPUC1_F

SRCT6 SRCC6

SRCT10 SRCC10

SRCT9 SRCC9

SRCT4 SRCC4

3D3V_S0_CK505

12

R183

R183 10KR2J-3-GP

10KR2J-3-GP

12

R182

R182 10KR2J-3-GP

10KR2J-3-GP

1D5V_S0_CK505

12

C316

SCD1U16V2ZY-2GP

CLKGEN_CPUT0

61

CLKGEN_CPUC0

60

CLKGEN_CPUT1

58

CLKGEN_CPUC1

57 54

53

51 50

CLKGEN_SRCT6

48

CLKGEN_SRCC6

47

CLKGEN_SRCT10

41

CLKGEN_SRCC10

42 40

39

CLKGEN_SRCT9

37

CLKGEN_SRCC9

38

CLKGEN_SRCT4

34

CLKGEN_SRCC4

35

CLKGEN_SRCT3

31

CLKGEN_SRCC3

32

CLKGEN_SRCT2

28

CLKGEN_SRCC2

29

CLKGEN_SRCT1

24

CLKGEN_SRCC1

25

CLKGEN_SRCT0

20

CLKGEN_SRCC0

21

DY

27_SEL

12

C326

C300

SCD1U16V2ZY-2GP

RN21 SRN0J-6-GPRN21 SRN0J-6-GP

RN19 SRN0J-6-GPRN19 SRN0J-6-GP

RN15 SRN10J-7-GPRN15 SRN10J-7-GP

RN12 SRN10J-7-GPRN12 SRN10J-7-GP

RN13 SRN10J-7-GPRN13 SRN10J-7-GP

RN14 SRN0J-6-GPRN14 SRN0J-6-GP

RN16 SRN0J-6-GPRN16 SRN0J-6-GP

RN17 SRN0J-6-GPRN17 SRN0J-6-GP

RN18 SRN0J-6-GPRN18 SRN0J-6-GP

RN20 SRN0J-6-GPRN20 SRN0J-6-GP

12

C317

SCD1U16V2ZY-2GP

1 2 3

SB

1 2 3

2 3 1

BLM11A121S-GP

12

C302

C312

SCD1U16V2ZY-2GP

SC10U10V5ZY-1GP

4

R142 10KR2J-3-GPR142 10KR2J-3-GP

1 2

R143 10KR2J-3-GPR143 10KR2J-3-GP

1 2

4

1 2

12

27_SEL PIN 20 PIN 21 PIN 24 PIN 25

0 DOT96T DOT96C SRCT1/LCDT_100 SRCT1/LCDT_100 1 SRCT0 SRCC0 27M_NSS 27M_SS

Title

Clock Generator

Size Document Number Rev

Date: Sheet

D

Date: Sheet

1D5V_S0

L14

12

C298

SC1U10V3KX-3GP

CLK_CPU_BCLK 4 CLK_CPU_BCLK# 4

CLK_MCH_BCLK 8 CLK_MCH_BCLK# 8

CLK_PCIE_MINI 31 CLK_PCIE_MINI# 31

CLK_PCIE_NEW 31 CLK_PCIE_NEW# 31

3D3V_S0

NEWCARD_CLKREQ# 31 LAN_CLKREQ# 26

3D3V_S0

CLK_PCIE_LAN 26 CLK_PCIE_LAN# 26

CLK_MCH_3GPLL 10 CLK_MCH_3GPLL# 10

CLK_PCIE_ICH 20 CLK_PCIE_ICH# 20

CLK_PCIE_SATA 19 CLK_PCIE_SATA# 19

DREFCLKSS_100M 10 DREFCLKSS_100M# 10

DREFCLK_96M 10 DREFCLK_96M# 10

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

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341Wednesday, April 16, 2008

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341Wednesday, April 16, 2008

A

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D

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CPU_BSEL03 CPU_BSEL13 CPU_BSEL23

H_DSTBN#0 H_DSTBP#0 H_DINV#0

H_DSTBN#1 H_DSTBP#1 H_DINV#1

GTLREF CPU_TEST1 CPU_TEST2

CPU_TEST1 CPU_TEST2

H_D#[63..0]8 H_DSTBN#[3..0]8 H_DSTBP#[3..0]8 H_DINV#[3..0]8

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15

H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31

U55B

E22

D[0]#

F24

D[1]#

E26

D[2]#

G22

D[3]#

F23

D[4]#

G25

D[5]#

E25

D[6]#

E23

D[7]#

K24

D[8]#

G24

D[9]#

J24

D[10]#

J23

D[11]#

H22

D[12]#

F26

D[13]#

K22

D[14]#

H23

D[15]#

J26

DSTBN[0]#

H26

DSTBP[0]#

H25

DINV[0]#

N22

D[16]#

K25

D[17]#

P26

D[18]#

R23

D[19]#

L23

D[20]#

M24

D[21]#

L22

D[22]#

M23

D[23]#

P25

D[24]#

P23

D[25]#

P22

D[26]#

T24

D[27]#

R24

D[28]#

L25

D[29]#

T25

D[30]#

N25

D[31]#

L26

DSTBN[1]#

M26

DSTBP[1]#

N24

DINV[1]#

AD26

GTLREF

C23

TEST1

D25

TEST2

C24

TEST3

AF26

TEST4

AF1

TEST5

A26

TEST6

C3

TEST7

B22

BSEL[0]

B23

BSEL[1]

C21

BSEL[2]

BGA479-SKT6-GPU6

DATA GRP 0

DATA GRP 1

MISC

D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]#

DATA GRP 2DATA GRP 3

D[42]# D[43]# D[44]# D[45]# D[46]#

D[47]# DSTBN[2]# DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]# DSTBN[3]# DSTBP[3]#

DINV[3]# COMP[0]

COMP[1] COMP[2] COMP[3]

DPRSTP#

DPSLP# DPWR#

PWRGOOD

SLP#

PSI#

Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22

AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20

R26 U26 AA1 Y1

E5 B5 D24 D6 D7 AE6

H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_DSTBN#2 H_DSTBP#2 H_DINV#2

H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DSTBN#3 H_DSTBP#3 H_DINV#3

COMP0

R338 27D4R2F-L1-GPR338 27D4R2F-L1-GP

1 2

COMP1

R340 54D9R2F-L1-GPR340 54D9R2F-L1-GP

1 2

COMP2

R122 27D4R2F-L1-GPR122 27D4R2F-L1-GP

1 2

COMP3

R115 54D9R2F-L1-GPR115 54D9R2F-L1-GP

1 2

H_DPRSTP# 10,19,35 H_DPSLP# 19

H_DPWR# 8

CPU_PWRGD 19

H_CPUSLP# 8

PSI# 35

Place each resistor within 0.5" of each pin

H_A#[3..35]8

H_ADSTB#08

3 3

2 2

H_REQ#[4..0]8

H_ADSTB#18

H_A20M#19

H_FERR#19

H_IGNNE#19 H_STPCLK#19

INTR19 NMI19 H_SMI#19

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

U55A

J4

A[3]#

L5

A[4]#

L4

A[5]#

K5

A[6]#

M3

A[7]#

N2

A[8]#

J1

A[9]#

N3

A[10]#

P5

A[11]#

P2

A[12]#

L2

A[13]#

P4

A[14]#

P1

A[15]#

R1

A[16]#

M1

ADSTB[0]#

K3

REQ[0]#

H2

REQ[1]#

K2

REQ[2]#

J3

REQ[3]#

L1

REQ[4]#

Y2

A[17]#

U5

A[18]#

R3

A[19]#

W6

A[20]#

U4

A[21]#

Y5

A[22]#

U1

A[23]#

R4

A[24]#

T5

A[25]#

T3

A[26]#

W2

A[27]#

W5

A[28]#

Y4

A[29]#

U2

A[30]#

V4

A[31]#

W3

A[32]#

AA4

A[33]#

AB2

A[34]#

AA3

A[35]#

V1

ADSTB[1]#

A6

A20M#

A5

FERR#

C4

IGNNE#

D5

STPCLK#

C6

LINT0

B4

LINT1

A3

SMI#

M4

RSVD[01]

N5

RSVD[02]

T2

RSVD[03]

V3

RSVD[04]

B2

RSVD[05]

D2

RSVD[06]

D22

RSVD[07]

D3

RSVD[08]

F6

RSVD[09]

BGA479-SKT6-GPU6

ADDR GROUP_0

ADDR GROUP_1

XDP/ITP SIGNALS

THERMAL

PROCHOT#

THERMDA THERMDC

ICH

THERMTRIP#

H CLK

RESERVED

ADS# BNR# BPRI#

DEFER#

DRDY# DBSY#

BR0#

IERR#

INIT#

LOCK#

CONTROL

RESET#

RS[0]# RS[1]# RS[2]#

TRDY#

HIT#

HITM#

BPM[0]# BPM[1]# BPM[2]# BPM[3]#

PRDY# PREQ#

TCK

TDI TDO TMS

TRST#

DBR#

BCLK[0] BCLK[1]

H1 E2 G5

H5 F21 E1

F1 D20

B3 H4 C1

F3 F4 G3 G2

G6 E4

AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20

D21 A24 B25

CPU_THERMTRIP#

C7

A22 A21

DY

H_RS#0 H_RS#1 H_RS#2

XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 ITP_PRDY# ITP_PREQ#

XDP_DBRESET#

12

C145

C145 SC100P50V2JN-3GP

SC100P50V2JN-3GP

H_ADS# 8 H_BNR# 8

H_BPRI# 8 H_DEFER# 8

H_DRDY# 8 H_DBSY# 8

H_BR0# 8

H_IERR#

H_INIT# 19

H_LOCK# 8

H_RESET# 8

H_TRDY# 8

H_HIT# 8 H_HITM# 8

XDP_TCK 6 XDP_TDI 6 XDP_TDO 6 XDP_TMS 6 XDP_TRST# 6

1 2

R83

R83 0R0402-PAD

0R0402-PAD

CLK_CPU_BCLK 3 CLK_CPU_BCLK# 3

H_THERMDA

H_THERMDC

H_RS#[0..2] 8

1D05V_S0

H_THERMTRIP# 10,19

12

R82

R82 56R2J-4-GP

56R2J-4-GP

12

R81

R81 68R2-GP

68R2-GP

H_THERMDA 7 H_THERMDC 7

XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 ITP_PRDY# ITP_PREQ# XDP_DBRESET#

CPU_PROCHOT# 35

1D05V_S0

12

R351

R351 1KR2F-3-GP

1KR2F-3-GP

Trace should be less than 0.5 inch

12

R352

R352 2KR2F-3-GP

2KR2F-3-GP

DY

R80 1KR2J-1-GP

1 2

R332 1KR2J-1-GP

1 2

DY

TP113TPAD30 TP113TPAD30 TP115TPAD30 TP115TPAD30 TP114TPAD30 TP114TPAD30 TP109TPAD30 TP109TPAD30 TP107TPAD30 TP107TPAD30 TP108TPAD30 TP108TPAD30 TP42TPAD30 TP42TPAD30

12

C816

C816 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SB

This capacitor must near CPU

1 1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

C

A

B

C

D

C

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Penryn CPU(1/2)

LZ2

441Wednesday, April 16, 2008

E

SB

of

5

www.kythuatvitinh.com

SC10U6D3V5MX-3GP

12

VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067]

C518

SC10U6D3V5MX-3GP

12

VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100]

VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16]

VCCA[01] VCCA[02]

VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]

VCCSENSE

VSSSENSE

C203

SC10U6D3V5MX-3GP

12

C291

VCC_CORE

AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20

G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21

B26 C26

AD6 AF5 AE5 AF4 AE3 AF3 AE2

AF7

AE7

.

CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6

C235

SC10U6D3V5MX-3GP

12

C263

D D

VCC_CORE

U55C

A7

A9 A10 A12 A13 A15 A17 A18 A20

B7

B9 B10 B12 B14

C C

B B

A A

B15 B17 B18 B20

C9

C10 C12 C13 C15 C17 C18

D9

D10 D12 D14 D15 D17 D18

E7

E9 E10 E12 E13 E15 E17 E18 E20

F7

F9 F10 F12 F14 F15 F17 F18 F20

AA7

AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20

AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18

BGA479-SKT6-GPU6

5

4

SC10U6D3V5MX-3GP

12

C200

DY

12

C210

SCD1U10V2KX-5GP

CPU_VID[0..6] 35

4

3

VCC_COREVCC_CORE

SC10U6D3V5MX-3GP

12

C223

12

C144

SC10U6D3V5MX-3GP

12

C290

12

C517

1D05V_S0

VCC_CORE

12

SC10U6D3V5MX-3GP

C246

SC10U6D3V5MX-3GP

C261

12

SC10U6D3V5MX-3GP

C141

12

DY

12

C262

C294

SC10U6D3V5MX-3GP

VCC_CORE

SC10U6D3V5MX-3GP

12

C530

SC10U6D3V5MX-3GP

C201

SC10U6D3V5MX-3GP

C529

SC10U6D3V5MX-3GP

C528

12

SC10U6D3V5MX-3GP

12

C531

12

DY

SC10U6D3V5MX-3GP

C516

12

SC10U6D3V5MX-3GP

12

C202

10UF 6.3V X5R 2125 1/16W X16 PCS

12

C236

SCD1U10V2KX-5GP

C211

12

C237

SCD1U10V2KX-5GP

PLACE 0.01uF NEAR VCCA PIN.B26

SB

12

SC10U6D3V5MX-3GP

C509

12

C506

SCD01U16V2KX-3GP

12

C226

12

C264

SCD1U10V2KX-5GP

TC10

TC10 ST220U2VBM-3GP

ST220U2VBM-3GP

77.C2271.26L

77.C2271.26L CT3528H83

CT3528H83

1D5V_S0

VCC_CORE

12

R133

R133 100R2F-L1-GP-U

100R2F-L1-GP-U

12

R134

R134 100R2F-L1-GP-U

100R2F-L1-GP-U

3

VCORE_VCCSENCE 35

VCORE_VSSSENCE 35

12

C103

2

SC10U6D3V5MX-3GP

C289

C293

12

SC10U6D3V5MX-3GP

C519

C143

SCD1U16V2ZY-2GP

C519

12

SC10U6D3V5MX-3GP

12

C260

VCC_CORE

12

C88

C114

SCD1U16V2ZY-2GP

CPU power EMI

2

1

U55D

A4

VSS[001]

A8

VSS[002]

A11

VSS[003]

SC10U6D3V5MX-3GP

C224

12

SC10U6D3V5MX-3GP

C199

12

SC10U6D3V5MX-3GP

12

C292

DY

12

C95

C109

SCD1U16V2ZY-2GP

SC10U6D3V5MX-3GP

C258

12

SC10U6D3V5MX-3GP

12

C259

DY

SCD1U16V2ZY-2GP

Title

Size Document Number Rev

A3

Date: Sheet of

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

A23

VSS[007]

AF2

VSS[008]

B6

VSS[009]

B8

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

C5

VSS[017]

C8

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

C2

VSS[023]

C22

VSS[024]

C25

VSS[025]

D1

VSS[026]

D4

VSS[027]

D8

VSS[028]

D11

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

E3

VSS[035]

E6

VSS[036]

E8

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

F5

VSS[044]

F8

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

F2

VSS[050]

F22

VSS[051]

F25

VSS[052]

G4

VSS[053]

G1

VSS[054]

G23

VSS[055]

G26

VSS[056]

H3

VSS[057]

H6

VSS[058]

H21

VSS[059]

H24

VSS[060]

J2

VSS[061]

J5

VSS[062]

J22

VSS[063]

J25

VSS[064]

K1

VSS[065]

K4

VSS[066]

K23

VSS[067]

K26

VSS[068]

L3

VSS[069]

L6

VSS[070]

L21

VSS[071]

L24

VSS[072]

M2

VSS[073]

M5

VSS[074]

M22

VSS[075]

M25

VSS[076]

N1

VSS[077]

N4

VSS[078]

N23

VSS[079]

N26

VSS[080] VSS[081]P3VSS[162]

B1

VSS

BGA479-SKT6-GPU6

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Penryn CPU(2/2)

LZ2

1

VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161]

VSS[163]

541Wednesday, April 16, 2008

P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25

.

SB

5

www.kythuatvitinh.com

D D

OK

XDP_TDI4

OK

XDP_TMS4

OK

XDP_TRST#4

C C

OK

XDP_TDO4

OK

XDP_TCK4

4

1D05V_S0

3

R136

R138

12

R137

TP98 TPAD30TP98 TPAD30 TP102 TPAD30TP102 TPAD30

54D9R2F-L1-GP

12

R135

TP101 TPAD30TP101 TPAD30

TP103 TPAD30TP103 TPAD30

TP106 TPAD30TP106 TPAD30

12

2

1

54D9R2F-L1-GP

B B

A A

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

C

5

4

3

2

C

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

ITP CONN

LZ2

1

SB

641Wednesday, April 16, 2008

SB

of

5

www.kythuatvitinh.com

Layout notice : Both H_THERMDA and THERMDC routing 10 mil trace width and 10 mil spacing

12

EMC2102_VDD_3D3

12

C809

3D3V_S0

12

SCD1U16V2ZY-2GP

C808

C808 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

3D3V_S0

Layout notice : Both H_THERMDA_1 and THERMDC_1 routing 10 mil trace width and 10 mil spacing

D D

Layout notice : Both DN3 and DP3 routing 10 mil trace width and 10 mil spacing

Layout notice : C809, C811, C812 close to chip side;

H_THERMDC4

CPU0

C C

SYSTEM

Q38

MMBT3904-3-GP

Q37

MMBT3904-3-GP

H_THERMDA4

E

B

C

E

C

12

C813

B

C813 SC470P50V3JN-2GP

SC470P50V3JN-2GP

DY

SC4D7U10V5ZY-3GP

3D3V_S0

EMC2102_DN2

EMC2102_DP2

EMC2102_DN3

EMC2102_DP3

1 2

C812

5V_S0

C807

R805

49D9R2F-GP

12

SC470P50V3JN-2GP

12

C811

SC470P50V3JN-2GP

12

SC470P50V3JN-2GP

This cap should close to thermal diode.

GND = Fan is OFF OPEN = Fan is at 60% full-scale +3.3V = Fan is at 75% full-scale

B B

3D3V_S0

C806

4

R804

1 2

10KR2J-3-GP

1 2 3 4 5 6 7

EMC2102-DZK-GP

74.02102.A73

R810

1 2

DY

R815

1 2

DY

R811

1 2

DY

10KR2J-3-GP

R809

1 2

10KR2J-3-GP

29

GND

VDD_3V DN1 DP1 DN2 DP2 DN3 DP3

EMC2102_SHDN

10KR2J-3-GP

EMC2102_FAN_mode

EMC2102_FAN_TACH

EMC2102_FAN_DRIVE

SC22U6D3V5MX-2GP

28

26

27

FANb25FANa

TACH

VDD_5Va

EMC2102

SHDN_SEL9FAN_MODE10TRIP_SET11SYS_SHDN#12THERMTRIP#13POWER_OK#

NC#8

8

24

VDD_5Vb

23

D34

SSM14PT-GP-U

C810

SMBC_THERM_1

SMBD_THERM_1

22

SMCLK

SMDATA

CLK_SEL

14

EMC2102_PWROK# EMC2102_THTRIP#

KA

12

R819 0R0402-PADR819 0R0402-PAD

1 2 1 2

R820 0R0402-PADR820 0R0402-PAD

U93

21

NC#21

20

GND

19

ALERT#

18

CLK_IN

17 16

RESET#

15

NC#15

HW_THRM_SHDN#

V_DEGREE

EMC2102_FAN_DRIVE

SC

ALERT#

0R2J-2-GP

G7921_CLK EMC2102_CLK_SEL

THRM_RESET#

RN67

1 2 3

SRN10KJ-5-GP

5V_S0

R806

R806 10KR2J-3-GP

10KR2J-3-GP

1 2

KA

D35

D35 SSM14PT-GP-U

SSM14PT-GP-U

SMBC_THERM SMBD_THERM

3D3V_S0

4

3

EMC2102_FAN_TACH_1

*Layout* 15 mil

3D3V_S0

12

R807

8K2R2J-3-GP

DY

12

R497

G7921_CLK 21

3D3V_S0

C814

C815

12

EMC2102_FAN_TACH_1 41

R808

R808 10KR2J-3-GP

10KR2J-3-GP

1 2

R812

R812 10KR2J-3-GP

10KR2J-3-GP

1 2

SCD1U16V2ZY-2GP

12

R813

R813 5K62R2F-GP

5K62R2F-GP

CN15

5 3 2

1

4

ACES-CON3-GP-U1

THRM# 21

TRIP_SET Pin Voltage V_DEGREE =(((Degree-75)/21)

2

3D3V_S0

4

RN46

SRN4K7J-8-GP

1

2 3

SMBC_THERM

R639

1 2

DY

SMBD_THERM

THER_SCL29,34,41

GND = Internal Oscillator Selected +3.3V = External 32.768kHz Clock Selected

3 4 2 1

R640

1 2

DY

0R2J-2-GP

U73

5 6

2N7002DW-7F-GP

0R2J-2-GP

1

3D3V_S03D3V_S0

THER_SDA 29,34,41

SC

SCD1U16V2ZY-2GP

U96

5

PM_PWROK21

4

NC7SZ08P5-GP

73.7SZ08.AAH

Dummy when G792 enhanced T8 function

HW thermal shut down tempature setting 95 degree . Put Near CPU .

A A

R95

DY

CPU_THSET

1 2

18KR2F-GP

Rset=0.0012*T^2-0.9308*T+96.147

U28

1

SET

2

GND OUT#3HYST

G709T1UF-GP

5

DY

1

A

VCC

THRM_RESET#

2

B

GND3Y

220ms delay time after Power-on

5V_AUX_S5

12

DY

R111

150R2J-L1-GP-U

12

DY

C249

SCD01U16V2KX-3GP

G709T_VCC

5

VCC

CPU_TH_HYSTT8_HW_SHUT#

4

5V_AUX_S5

12

PM_SLP_S3_1# 29,33

DY

R112

R112 0R2J-2-GP

0R2J-2-GP

DY

R104

R104 0R2J-2-GP

0R2J-2-GP

3D3V_AUX_S5 3D3V_AUX_S5

12

R272

R272 10KR2F-2-GP

1 2

10KR2F-2-GP

D16

1

2

D23

D23 BAT54-4-GP

BAT54-4-GP

3

BAW56W-7-F-GP

HW_THRM_SHDN#33

HW_THRM_SHDN#

T8_HW_SHUT#

3D3V_AUX_S5

4

R271 10KR2F-2-GPR271 10KR2F-2-GP

S5_ENABLE29

SCD1U16V2ZY-2GP

12

R360

R360 100KR2J-1-GP

100KR2J-1-GP

3

SC1U10V3ZY-6GP

1

2

C555

12

PWR_S5_EN 33

DY

BOM1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Thermal/Fan Controllor EMC2102

Size Document Number Rev

Size Document Number Rev Custom

Custom

Custom Date: Sheet

Date: Sheet

2

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

LZ2 SB

1

of

741Wednesday, April 16, 2008

A

www.kythuatvitinh.com

4 4

H_A#[3..35]4

H_D#[63..0]4 H_DSTBN#[3..0]4 H_DSTBP#[3..0]4

H_DINV#[3..0]4

3 3

2 2

1 1

H_REQ#[4..0]4

H_RS#[0..2]4

H_RCOMP trace should be 10 mil wide / 20 mil spacing

1D05V_S0

12

R330

R330 1KR2F-3-GP

1KR2F-3-GP

R331

R331 2KR2F-3-GP

2KR2F-3-GP

A

1D05V_S0

12

B

R89

R89 221R2F-2-GP

221R2F-2-GP

R88

R88 100R2F-L1-GP-U

100R2F-L1-GP-U

R87

R87 24D9R2F-L-GP

24D9R2F-L-GP

12

C508

C508 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

B

H_SWING

12

C168

C168 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

1 2

U56A

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

H_RCOMP

H_RESET#4

H_CPUSLP#4

H_A/DVREF

Short both H_AVREF and H_DVREF pins below (G)MCH package and connect them to termination.

F2

H_D#_0

G8

H_D#_1

F8

H_D#_2

E6

H_D#_3

G2

H_D#_4

H6

H_D#_5

H2

H_D#_6

F6

H_D#_7

D4

H_D#_8

H3

H_D#_9

M9

H_D#_10

M11

H_D#_11

J1

H_D#_12

J2

H_D#_13

N12

H_D#_14

J6

H_D#_15

P2

H_D#_16

L2

H_D#_17

R2

H_D#_18

N9

H_D#_19

L6

H_D#_20

M5

H_D#_21

J3

H_D#_22

N2

H_D#_23

R1

H_D#_24

N5

H_D#_25

N6

H_D#_26

P13

H_D#_27

N8

H_D#_28

L7

H_D#_29

N10

H_D#_30

M3

H_D#_31

Y3

H_D#_32

AD14

H_D#_33

Y6

H_D#_34

Y10

H_D#_35

Y12

H_D#_36

Y14

H_D#_37

Y7

H_D#_38

W2

H_D#_39

AA8

H_D#_40

Y9

H_D#_41

AA13

H_D#_42

AA9

H_D#_43

AA11

H_D#_44

AD11

H_D#_45

AD10

H_D#_46

AD13

H_D#_47

AE12

H_D#_48

AE9

H_D#_49

AA2

H_D#_50

AD8

H_D#_51

AA3

H_D#_52

AD3

H_D#_53

AD7

H_D#_54

AE14

H_D#_55

AF3

H_D#_56

AC1

H_D#_57

AE3

H_D#_58

AC3

H_D#_59

AE11

H_D#_60

AE8

H_D#_61

AG2

H_D#_62

AD6

H_D#_63

C5

H_SWING

E3

H_RCOMP

C12

H_CPURST#

E11

H_CPUSLP#

A11

H_AVREF

B11

H_DVREF

CANTIGA-GM-GP-U-NF

C

1 OF 10

H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8

H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35

H_ADS# H_ADSTB#_0 H_ADSTB#_1

H_BNR#

H_BPRI#

H_BREQ#

H_DEFER#

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

HOST

C

H_DRDY#

H_HIT#

H_HITM# H_LOCK# H_TRDY#

H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3

H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3

H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3

H_REQ#_0 H_REQ#_1

H_REQ#_2 H_REQ#_3

H_REQ#_4

H_RS#_0

H_RS#_1

H_RS#_2

A14 C15 F16 H13 C18 M16 J13 P16 R16 N17 M13 E17 P17 F17 G20 B19 J16 E20 H16 J20 L17 A17 B17 L16 C21 J17 H20 B18 K17 B20 F21 K21 L20

H12 B16 G17 A9 F11 G12 E9 B10 AH7 AH6 J11 F9 H9 E12 H11 C9

J8 L3 Y13 Y1

L10 M7 AA5 AE6

L9 M8 AA6 AE5

B15 K13 F13 B13 B14

B6 F12 C8

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3

H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3

H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_RS#0 H_RS#1 H_RS#2

D

H_ADS# 4 H_ADSTB#0 4 H_ADSTB#1 4 H_BNR# 4 H_BPRI# 4 H_BR0# 4 H_DEFER# 4 H_DBSY# 4

CLK_MCH_BCLK 3 CLK_MCH_BCLK# 3

H_DPWR# 4 H_DRDY# 4 H_HIT# 4 H_HITM# 4

H_LOCK# 4

H_TRDY# 4

E

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Cantiga(1/7):HOST I/F

LZ2

841Wednesday, April 16, 2008

E

SB

A

www.kythuatvitinh.com

B

C

D

E

M_A_DQ[63..0]15

M_A_DM[7..0]15

4 4

3 3

2 2

M_A_DQS#[7..0]15

M_A_DQS[7..0]15

M_A_A[14..0]15

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21

M_A_DQ22

M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

U56D

AJ38

SA_DQ_0

AJ41

SA_DQ_1

AN38

SA_DQ_2

AM38

SA_DQ_3

AJ36

SA_DQ_4

AJ40

SA_DQ_5

AM44

SA_DQ_6

AM42

SA_DQ_7

AN43

SA_DQ_8

AN44

SA_DQ_9

AU40

SA_DQ_10

AT38

SA_DQ_11

AN41

SA_DQ_12

AN39

SA_DQ_13

AU44

SA_DQ_14

AU42

SA_DQ_15

AV39

SA_DQ_16

AY44

SA_DQ_17

BA40

SA_DQ_18

BD43

SA_DQ_19

AV41

SA_DQ_20

AY43

SA_DQ_21

BB41

SA_DQ_22

BC40

SA_DQ_23

AY37

SA_DQ_24

BD38

SA_DQ_25

AV37

SA_DQ_26

AT36

SA_DQ_27

AY38

SA_DQ_28

BB38

SA_DQ_29

AV36

SA_DQ_30

AW36

SA_DQ_31

BD13

SA_DQ_32

AU11

SA_DQ_33

BC11

SA_DQ_34

BA12

SA_DQ_35

AU13

SA_DQ_36

AV13

SA_DQ_37

BD12

SA_DQ_38

BC12

SA_DQ_39

BB9

SA_DQ_40

BA9

SA_DQ_41

AU10

SA_DQ_42

AV9

SA_DQ_43

BA11

SA_DQ_44

BD9

SA_DQ_45

AY8

SA_DQ_46

BA6

SA_DQ_47

AV5

SA_DQ_48

AV7

SA_DQ_49

AT9

SA_DQ_50

AN8

SA_DQ_51

AU5

SA_DQ_52

AU6

SA_DQ_53

AT5

SA_DQ_54

AN10

SA_DQ_55

AM11

SA_DQ_56

AM5

SA_DQ_57

AJ9

SA_DQ_58

AJ8

SA_DQ_59

AN12

SA_DQ_60

AM13

SA_DQ_61

AJ11

SA_DQ_62

AJ12

SA_DQ_63

CANTIGA-GM-GP-U-NF

4 OF 10

BD21

SA_BS_0

BG18

SA_BS_1

AT25

SA_BS_2

BB20

SA_RAS#

BD20

SA_CAS#

AY20

SA_WE#

M_A_DM0

AM37

SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7

SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6

SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7

SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8

SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14

DDR SYSTEM MEMORY A

AT41 AY41 AU39 BB12 AY6 AT7 AJ5

AJ44 AT44 BA43 BC37 AW12 BC8 AU8 AM7 AJ43 AT43 BA44 BD37 AY12 BD8 AU9 AM8

BA21 BC24 BG24 BH24 BG25 BA24 BD24 BG27 BF25 AW24 BC21 BG26 BH26 BH17 AY25

M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14

M_A_BS0 15 M_A_BS1 15 M_A_BS2 15

DDR_A_RAS# 15 DDR_A_CAS# 15

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

M_B_DQ[63..0]16

M_B_DM[7..0]16

M_B_DQS[7..0]16

M_B_DQS#[7..0]16

M_B_A[14..0]16

U56E

AK47

SB_DQ_0

AH46

SB_DQ_1

AP47

SB_DQ_2

AP46

SB_DQ_3

AJ46

SB_DQ_4

AJ48

SB_DQ_5

AM48

SB_DQ_6

AP48

SB_DQ_7

AU47

SB_DQ_8

AU46

SB_DQ_9

BA48

SB_DQ_10

AY48

SB_DQ_11

AT47

SB_DQ_12

AR47

SB_DQ_13

BA47

SB_DQ_14

BC47

SB_DQ_15

BC46

SB_DQ_16

BC44

SB_DQ_17

BG43

SB_DQ_18

BF43

SB_DQ_19

BE45

SB_DQ_20

BC41

SB_DQ_21

BF40

SB_DQ_22

BF41

SB_DQ_23

BG38

SB_DQ_24

BF38

SB_DQ_25

BH35

SB_DQ_26

BG35

SB_DQ_27

BH40

SB_DQ_28

BG39

SB_DQ_29

BG34

SB_DQ_30

BH34

SB_DQ_31

BH14

SB_DQ_32

BG12

SB_DQ_33

BH11

SB_DQ_34

BG8

SB_DQ_35

BH12

SB_DQ_36

BF11

SB_DQ_37

BF8

SB_DQ_38

BG7

SB_DQ_39

BC5

SB_DQ_40

BC6

SB_DQ_41

AY3

SB_DQ_42

AY1

SB_DQ_43

BF6

SB_DQ_44

BF5

SB_DQ_45

BA1

SB_DQ_46

BD3

SB_DQ_47

AV2

SB_DQ_48

AU3

SB_DQ_49

AR3

SB_DQ_50

AN2

SB_DQ_51

AY2

SB_DQ_52

AV1

SB_DQ_53

AP3

SB_DQ_54

AR1

SB_DQ_55

AL1

SB_DQ_56

AL2

SB_DQ_57

AJ1

SB_DQ_58

AH1

SB_DQ_59

AM2

SB_DQ_60

AM3

SB_DQ_61

AH3

SB_DQ_62

AJ3

SB_DQ_63

CANTIGA-GM-GP-U-NF

5 OF 10

SB_BS_0 SB_BS_1 SB_BS_2

SB_RAS# SB_CAS#

SB_WE#

SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7

SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6

SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7

SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8

SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14

DDR SYSTEM MEMORY B

BC16 BB17 BB33

AU17 BG16 BF14

AM47 AY47 BD40 BF35 BG11 BA3 AP1 AK2

AL47 AV48 BG41 BG37 BH9 BB2 AU1 AN6 AL46 AV47 BH41 BH37 BG9 BC2 AT2 AN5

AV17 BA25 BC25 AU25 AW25 BB28 AU28 AW28 AT33 BD33 BB16 AW33 AY33 BH15 AU33

M_B_BS0 M_B_BS1 M_B_BS2

M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14

M_B_BS0 16 M_B_BS1 16 M_B_BS2 16

DDR_B_RAS# 16 DDR_B_CAS# 16DDR_A_WE# 15 DDR_B_WE# 16

1 1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A

B

C

D

Size Document Number Rev

Date: Sheet

Cantiga(2/7):DDR3

C

Taipei Hsien 221, Taiwan, R.O.C.

LZ2

941Wednesday, April 16, 2008

E

SB

of

A

www.kythuatvitinh.com

ME DEBUG PORT PIN OUT TABLE RESERVED#AL34 ME_JTAG_TCK RESERVED#AK34 ME_JTAG_TDI RESERVED#AN35 ME_JTAG_TDO RESERVED#AM35 ME_JTAG_TMS

4 4

TP82 TPAD30TP82 TPAD30 TP84 TPAD30TP84 TPAD30 TP91 TPAD30TP91 TPAD30 TP97 TPAD30TP97 TPAD30

CFG5 : DMIx2 CFG6 : iTPM CFG7 : ME Crypto CFG9: PCIE STD& REV CFG16 : FSB Dynamic ODT CFG19 : DMI Lane reversal

3 3

2 2

1 1

10KR2J-3-GP

VGATE_PWRG#21,35

R109

3D3V_S0

12

VR_PWRG35

12

R118

R118 10KR2J-3-GP

10KR2J-3-GP

PM_EXTTS#0 PM_EXTTS#1

R125 0R2J-2-GP

1 2

DY

CFG20 : DP concurrent CFG[17:3]:internal pullup CFG[20:18]:internal pulldown

MCH_CLKSEL03 MCH_CLKSEL13 MCH_CLKSEL23

PLT_RST#20,24,26,29,31

VR_PWRG

PM_SYNC#21

H_DPRSTP#4,19,35

PM_EXTTS#015 PM_EXTTS#116

H_THERMTRIP#4,19

PM_DPRSLPVR21,35

TP50 TPAD30TP50 TPAD30 TP60 TPAD30TP60 TPAD30 TP67 TPAD30TP67 TPAD30 TP63 TPAD30TP63 TPAD30 TP64 TPAD30TP64 TPAD30 TP54 TPAD30TP54 TPAD30 TP59 TPAD30TP59 TPAD30 TP61 TPAD30TP61 TPAD30 TP58 TPAD30TP58 TPAD30 TP52 TPAD30TP52 TPAD30 TP53 TPAD30TP53 TPAD30 TP51 TPAD30TP51 TPAD30 TP57 TPAD30TP57 TPAD30 TP56 TPAD30TP56 TPAD30 TP55 TPAD30TP55 TPAD30 TP68 TPAD30TP68 TPAD30 TP69 TPAD30TP69 TPAD30 TP62 TPAD30TP62 TPAD30

R90 100R2J-2-GPR90 100R2J-2-GP

1 2

A

GMCH_AL34 GMCH_AK34 GMCH_AN35 GMCH_AM35

GMCH_CFG3 GMCH_CFG4 GMCH_CFG5 GMCH_CFG6 GMCH_CFG7 GMCH_CFG8 GMCH_CFG9 GMCH_CFG10 GMCH_CFG11 GMCH_CFG12 GMCH_CFG13 GMCH_CFG14 GMCH_CFG15 GMCH_CFG16 GMCH_CFG17 GMCH_CFG18 GMCH_CFG19 GMCH_CFG20

VR_PWRG GMCH_RSTIN#

B

U56B

M36

RESERVED#M36

N36

RESERVED#N36

R33

RESERVED#R33

T33

RESERVED#T33

AH9

RESERVED#AH9

AH10

RESERVED#AH10

AH12

RESERVED#AH12

AH13

RESERVED#AH13

K12

RESERVED#K12

AL34

RESERVED#AL34

AK34

RESERVED#AK34

AN35

RESERVED#AN35

AM35

RESERVED#AM35

T24

RESERVED#T24

B31

RESERVED#B31

B2

RESERVED#B2

M1

RESERVED#M1

AY21

RESERVED#AY21

BG23

RESERVED#BG23

BF23

RESERVED#BF23

BH18

RESERVED#BH18

BF18

RESERVED#BF18

T25

CFG_0

R25

CFG_1

P25

CFG_2

P20

CFG_3

P24

CFG_4

C25

CFG_5

N24

CFG_6

M24

CFG_7

E21

CFG_8

C23

CFG_9

C24

CFG_10

N21

CFG_11

P21

CFG_12

T21

CFG_13

R20

CFG_14

M20

CFG_15

L21

CFG_16

H21

CFG_17

P29

CFG_18

R28

CFG_19

T28

CFG_20

R29

PM_SYNC#

B7

PM_DPRSTP#

N33

PM_EXT_TS#_0

P32

PM_EXT_TS#_1

AT40

PWROK

AT11

RSTIN#

T20

THERMTRIP#

R32

DPRSLPVR

BG48

NC#BG48

BF48

NC#BF48

BD48

NC#BD48

BC48

NC#BC48

BH47

NC#BH47

BG47

NC#BG47

BE47

NC#BE47

BH46

NC#BH46

BF46

NC#BF46

BG45

NC#BG45

BH44

NC#BH44

BH43

NC#BH43

BH6

NC#BH6

BH5

NC#BH5

BG4

NC#BG4

BH3

NC#BH3

BF3

NC#BF3

BH2

NC#BH2

BG2

NC#BG2

BE2

NC#BE2

BG1

NC#BG1

BF1

NC#BF1

BD1

NC#BD1

BC1

NC#BC1

F1

NC#F1

A47

NC#A47

CANTIGA-GM-GP-U-NF

C

2 OF 10

AP24

SA_CK_0

AT21

SA_CK_1

AV24

SB_CK_0

AU20

SB_CK_1

AR24

SA_CK#_0

AR21

SA_CK#_1

AU24

SB_CK#_0

AV20

SB_CK#_1

BC28

SA_CKE_0

AY28

SA_CKE_1

AY36

SB_CKE_0

RSVD

SM_RCOMP_VOH SM_RCOMP_VOL

SM_DRAMRST# DPLL_REF_CLK

DDR CLK/ CONTROL/COMPENSATION

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

CLK

DMI

CFG

PM

GRAPHICS VID

MEHDA

DDPC_CTRLCLK

DDPC_CTRLDATA

NC

SDVO_CTRLCLK

SDVO_CTRLDATA

MISC

SB_CKE_1 SA_CS#_0

SA_CS#_1 SB_CS#_0 SB_CS#_1

SA_ODT_0 SA_ODT_1 SB_ODT_0 SB_ODT_1

SM_RCOMP

SM_RCOMP#

SM_VREF

SM_PWROK

SM_REXT

PEG_CLK

PEG_CLK#

DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3

DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3

DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3

DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3

GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4

GFX_VR_EN

CL_CLK

CL_DATA

CL_PWROK

CL_RST# CL_VREF

CLKREQ#

ICH_SYNC#

TSATN#

HDA_BCLK

HDA_RST#

HDA_SDI

HDA_SDO

HDA_SYNC

BB36 BA17

AY16 AV16 AR13

BD17 AY17 BF15 AY13

BG22 BH21

BF28 BH28

AV42 AR36 BF17 BC36

B38 A38 E41 F41

F43 E43

AE41 AE37 AE47 AH39

AE40 AE38 AE48 AH40

AE35 AE43 AE46 AH42

AD35 AE44 AF46 AH43

B33 B32 G33 F33 E33

C34

AH37 AH36 AN36 AJ35 AH34

DDPC_CTRLCLK

N28

DDPC_CTRLDATA

M28

SDVO_CTRLCLK

G36

SDVO_CTRLDATA

E36 K36 H36

B12

B28 B30 B29 C29 A28

M_RCOMPP

R335 80D6R2F-L-GPR335 80D6R2F-L-GP

M_RCOMPN

R334 80D6R2F-L-GPR334 80D6R2F-L-GP

SM_RCOMP_VOH SM_RCOMP_VOL

SMPWRG

SM_REXT

DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3

DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3

DMI_RXN0DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3

DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3

GFXVID0 GFXVID1 GFXVID2 GFXVID3 GFXVID4

GFX_VR_EN

CL_CLK_MCH 21

CL_DATA_MCH 21 CL_PWROK 21 CL_RST_MCH# 21

GMCH_TSATN#

C

1 2 1 2

DMI_TXN0 20 DMI_TXN1 20 DMI_TXN2 20 DMI_TXN3 20

DMI_TXP0 20 DMI_TXP1 20 DMI_TXP2 20 DMI_TXP3 20

DMI_RXN0 20 DMI_RXN1 20 DMI_RXN2 20 DMI_RXN3 20

DMI_RXP0 20 DMI_RXP1 20 DMI_RXP2 20 DMI_RXP3 20

R333 56R2F-1-GPR333 56R2F-1-GP

DDRCLK0_533M 15 DDRCLK1_533M 15 DDRCLK2_533M 16 DDRCLK3_533M 16

DDRCLK0_533M# 15 DDRCLK1_533M# 15 DDRCLK2_533M# 16 DDRCLK3_533M# 16

DDR_CKE0_DIMMA 15 DDR_CKE1_DIMMA 15 DDR_CKE2_DIMMB 16 DDR_CKE3_DIMMB 16

DDR_CS0_DIMMA# 15 DDR_CS1_DIMMA# 15 DDR_CS2_DIMMB# 16 DDR_CS3_DIMMB# 16

M_ODT0 15 M_ODT1 15 M_ODT2 16 M_ODT3 16

R93 499R2F-2-GPR93 499R2F-2-GP

1 2

DRAMRST# 15,16

DREFCLK_96M 3 DREFCLK_96M# 3 DREFCLKSS_100M 3 DREFCLKSS_100M# 3

CLK_MCH_3GPLL 3 CLK_MCH_3GPLL# 3

TP81TPAD30 TP81TPAD30 TP70TPAD30 TP70TPAD30 TP79TPAD30 TP79TPAD30 TP90TPAD30 TP90TPAD30 TP80TPAD30 TP80TPAD30

TP88TPAD30 TP88TPAD30

TP66TPAD30 TP66TPAD30 TP65TPAD30 TP65TPAD30 TP95TPAD30 TP95TPAD30 TP94TPAD30 TP94TPAD30

1 2

1D5V_S3

SM_REXT:Constant circuit reference for clocks.

1D05V_CL_VREF

SCD1U10V2KX-4GP

CLKREQ_MCH# 3 MCH_ICH_SYNC# 21

1D05V_S0

DDR_SM_VREF

12

C265

SCD1U10V2KX-4GP

SMPWRG

R105 1KR2F-3-GPR105 1KR2F-3-GP

1 2

12

R113

R113 499R2F-2-GP

499R2F-2-GP

12

R824

R824 10KR2J-3-GP

10KR2J-3-GP

1 2

1D05V_S0

INTEL Suggest use 511

D

12

R822

0R2J-2-GP

D

C278

SCD1U10V2KX-4GP

12

C270

DDR_VREF_S3

R131

1 2

0R0603-PAD

M_PWROK 37

E

1D5V_S3

R341

R341 1KR2F-3-GP

1KR2F-3-GP

SM_RCOMP_VOH

SM_RCOMP_VOL

Title

Size Document Number Rev

C

Date: Sheet

12

C527

SCD01U16V2KX-3GP

12

C522

SCD01U16V2KX-3GP

CLKREQ_MCH#

Cantiga(3/7):DMI/PM/CFG/GF

1 2

12

C532

12

C523

R337

R337 3K01R2F-3-GP

3K01R2F-3-GP

SC2D2U6D3V3MX-1-GP

R336

R336 1KR2F-3-GP

1KR2F-3-GP

1 2

SC2D2U6D3V3MX-1-GP

3D3V_S0

R119

R119 10KR2J-3-GP

10KR2J-3-GP

1 2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

LZ2

10 41Wednesday, April 16, 2008

E

of

SB

5

www.kythuatvitinh.com

3D3V_S0

R116

R117

12

D D

LBKLT_CTL17 BLON_IN29

LDDC_CLK17 LDDC_DATA17

LCDVDD_EN17

C C

2K2R2J-2-GP

GMCH_TXAOUT0-17 GMCH_TXAOUT1-17 GMCH_TXAOUT2-17

GMCH_TXAOUT0+17 GMCH_TXAOUT1+17 GMCH_TXAOUT2+17

ZO=37.5 OHMZO=50 OHM

BLUE_GMCH18 GREEN_GMCH18 RED_GMCH18

B B

12

R99

R100

150R2F-1-GP

2K2R2J-2-GP

2K4R2F-GP

150R2F-1-GP

R120

12

R130

1 2 1 2 1 2

12

R101

4

R108

12

10KR2J-3-GP

LCD_CTRL_CLK LCD_CTRL_DATA

1 2

GMCH_TXACLK-17 GMCH_TXACLK+17

150R2F-1-GP

TP112

TPAD30

R9675R2J-1-GP R9675R2J-1-GP R9775R2J-1-GP R9775R2J-1-GP R9875R2J-1-GP R9875R2J-1-GP

R110

1 2

100KR2J-1-GP

10KR2J-3-GP

LIBG

LVDS_VBG

TVA_DAC TVB_DAC TVC_DAC

CRT_IREF

12

L32 G32 M32

M33 K33

J33

M29 C44 B43 E37 E38 C41 C40 B37 A37

H47 E46 G40 A40

H48 D45 F40 B40

A41 H38 G37

J37

B42 G38 F37 K37

F25 H25 K25

H24

C31 E32

E28 G28

J28 G29 H32

J32

J29 E29 L29

R102

R102 1K02R2D-GP

1K02R2D-GP

U56C

L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK

L_CTRL_DATA L_DDC_CLK L_DDC_DATA

L_VDD_EN LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK

LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2 LVDSA_DATA#_3

LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2 LVDSA_DATA_3

LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2 LVDSB_DATA#_3

LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2 LVDSB_DATA_3

TVA_DAC TVB_DAC TVC_DAC

TV_RTN

TV_DCONSEL_0 TV_DCONSEL_1

CRT_BLUE CRT_GREEN CRT_RED CRT_IRTN CRT_DDC_CLK

CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF CRT_VSYNC

CANTIGA-GM-GP-U-NF

3

1D05V_S0

3 OF 10

T37

PEG_COMPI

T36

PEG_COMPO

H44

PEG_RX#_0

J46

PEG_RX#_1

L44

PEG_RX#_2

L40

PEG_RX#_3

N41

PEG_RX#_4

P48

PEG_RX#_5

N44

PEG_RX#_6

T43

PEG_RX#_7

U43

PEG_RX#_8

Y43

PEG_RX#_9

Y48

PEG_RX#_10

Y36

PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15

PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8

PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15

PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9

PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15

PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8

PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15

AA43 AD37 AC47 AD39

H43 J44 L43 L41 N40 P47 N43 T42 U42 Y42 W47 Y37 AA42 AD36 AC48 AD40

J41 M46 M47 M40 M42 R48 N38 T40 U37 U40 Y40 AA46 AA37 AA40 AD43 AC46

J42 L46 M48 M39 M43 R47 N37 T39 U36 U39 Y39 Y46 AA36 AA39 AD42 AD46

LVDS

TV VGA

PCI-EXPRESS GRAPHICS

12

PEG_COMP

R114

R114 49D9R2F-GP

49D9R2F-GP

2

1

GMCH_DDC_CLK18

GMCH_DDC_DATA18

HSYNC_GMCH18 VSYNC_GMCH18

A A

R106 30D1R2F-L-GPR106 30D1R2F-L-GP

1 2

R107 30D1R2F-L-GPR107 30D1R2F-L-GP

1 2

5

HSYNC_R

VSYNC_R

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CANTIGA(5/7)-VGA/LVDS

Size Document Number Rev

Size Document Number Rev C

C

C Date: Sheet

Date: Sheet

4

3

2

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

LZ2

1

SB

41Wednesday, April 16, 2008

of

11

A

www.kythuatvitinh.com

4 4

U56G

12

C233

R91

R91 0R0402-PAD

0R0402-PAD

AP33 AN33 BH32 BG32

BF32 BD32 BC32 BB32 BA32 AY32

AW32

AV32 AU32 AT32 AR32 AP32 AN32 BH31 BG31

BF31 BG30 BH29 BG29

BF29 BD29 BC29 BB29 BA29 AY29

AW29

AV29 AU29 AT29 AR29 AP29

BA36 BB24 BD16 BB21

AW16 AW13

AT13

Y26 AE25 AB25 AA25 AE24 AC24 AA24

Y24 AE23 AC23 AB23 AA23

AJ21 AG21 AE21 AC21 AA21

Y21

AH20

AF20 AE20 AC20 AB20 AA20

T17 T16

AM15

AL15 AE15

AJ15 AH15 AG15

AF15 AB15 AA15

Y15 V15 U15

AN14 AM14

U14

T14

AJ14

AH14

CANTIGA-GM-GP-U-NF

1D5V_S3

12

C238

SCD1U10V2KX-4GP

12

C243

DY

SC1U10V2KX-1GP

3 3

2 2

12

C253

C244

SCD1U10V2KX-4GP

12

C250

C242

DY

SC1U10V2KX-1GP

SCD22U10V2KX-1GP

12

1

C252

C251

2

SC22U6D3V5MX-2GP

SA

12

TC13

TC13 ST220U2VBM-3GP

ST220U2VBM-3GP

77.C2271.26L

SC

SC22U6D3V5MX-2GP

VCC_SM_36 VCC_SM_37 VCC_SM_38

VCC_SM_39 VCC_SM_40

1 2

1D05V_AXG_SENSE

SCD22U10V2KX-1GP

12

C255

1D05V_S0

SCD47U6D3V2KX-GP

VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM

VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC

VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG

VCC_AXG_SENSE VSS_AXG_SENSE

B

VCC SMVCC GFX

VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF

POWER

VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF

VCC GFX NCTF

VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF

VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF

VCC SM LF

7 OF 10

W28 V28 W26 V26 W25 V25 W24 V24 W23 V23 AM21 AL21 AK21 W21 V21 U21 AM20 AK20 W20 U20 AM19 AL19 AK19 AJ19 AH19 AG19 AF19 AE19 AB19 AA19 Y19 W19 V19 U19 AM17 AK17 AH17 AG17 AF17 AE17 AC17 AB17 Y17 W17 V17 AM16 AL16 AK16 AJ16 AH16 AG16 AF16 AE16 AC16 AB16 AA16 Y16 W16 V16 U16

AV44 BA37 AM40 AV21 AY5 AM10 BB13

12

C138

SC22U6D3V5MX-2GP

C225

SC10U6D3V3MX-GP

GM_VCC_SM_LF_1 GM_VCC_SM_LF_2 GM_VCC_SM_LF_3 GM_VCC_SM_LF_4 GM_VCC_SM_LF_5 GM_VCC_SM_LF_6 GM_VCC_SM_LF_7

SCD47U6D3V2KX-GP

C248

12

1

2

SC10U6D3V3MX-GP

C217

SC1U10V2KX-1GP

12

C

1D05V_S0

C176

12

C257

SC10U6D3V3MX-GP

C254

C156

C502

12

SCD1U10V2KX-4GP

C175

12

SCD1U10V2KX-4GP

C221

C170

C160

12

SCD1U10V2KX-4GP

C247

12

C204

C218

SCD1U10V2KX-4GP

SA

12

TC15

TC15 ST220U2VBM-3GP

ST220U2VBM-3GP

77.C2271.26L

VCC_SM_36

VCC_SM_37

VCC_SM_38

VCC_SM_39

VCC_SM_40

C269

C267

C280

12

1

2

12

C227

SCD22U10V2KX-1GP

DY

C266 SCD1U10V2KX-4GP

1 2

DY

C222 SCD1U10V2KX-4GP

1 2

DY

C215 SCD1U10V2KX-4GP

1 2

DY

C214 SCD1U10V2KX-4GP

1 2

DY

C178 SCD1U10V2KX-4GP

1 2

D

U56F

AG34

VCC

AC34

VCC

AB34

VCC

12

C232

C212

SC22U6D3V5MX-2GP

SCD22U10V2KX-1GP

AA34

12

C256

AM33 AK33

AJ33

SCD01U16V2KX-3GP

AG33

AF33

AE33 AC33 AA33

W33

AH28

AF28 AC28 AA28

AJ26 AG26 AE26 AC26 AH25 AG25

AF25 AG24

AJ23 AH23

AF23

VCC

Y34

VCC

V34

VCC

U34

VCC VCC VCC VCC VCC VCC

VCC VCC VCC

Y33

VCC VCC

V33

VCC

U33

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

T32

VCC

CANTIGA-GM-GP-U-NF

VCC CORE

POWER

VCC NCTF

6 OF 10

VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF

AM32 AL32 AK32 AJ32 AH32 AG32 AE32 AC32 AA32 Y32 W32 U32 AM30 AL30 AK30 AH30 AG30 AF30 AE30 AC30 AB30 AA30 Y30 W30 V30 U30 AL29 AK29 AJ29 AH29 AG29 AE29 AC29 AA29 Y29 W29 V29 AL28 AK28 AL26 AK26 AK25 AK24 AK23

E

1D05V_S0

1 1

SCD1U10V2KX-4GP

SCD22U6D3V2KX-1GP

A

B

C

SC1U10V2KX-1GP

SCD47U6D3V2KX-GP

SCD22U6D3V2KX-1GP

D

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

C

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Cantiga(5/7):VCC

LZ2

E

12 41Friday, April 11, 2008

of

SB

A

www.kythuatvitinh.com

B

C

D

E

5V_S0

1D05V_S0

IND-10UH-72-GP

1 2

L12

4 4

1D05V_S0

1 2

12

C179

C179 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

3 3

2 2

1D05V_S0 1D05V_VCCA_PLL

R144

1 2

0R0603-PAD

1 1

L12 L13

L13

L8

1 2

BLM15EG121SN1D-GP

L9

BLM15EG121SN1D-GP

12

1R2F-GP

1R2F-GP R145

R145

1D05V_VCCA_PLL_1

12

SC10U6D3V5MX-3GP

1 2

IND-10UH-72-GP

C305

12

C147

C501

SCD1U10V2KX-4GP

SC4D7U10V5KX-1GP

1D05V_S0

NOTE:47UF shared with VCCA_SM and VCCA_SM_CK

12

C275

SC22U6D3V5MX-2GP

12

R79

R79 D51R3F-2-GP

D51R3F-2-GP

VCCA_MPLL_1

12

C142

C142 SC2D2U6D3V3KX-GP

SC2D2U6D3V3KX-GP

1 2

12

TC11

TC11 SC47U6D3V6MX-1GP

SC47U6D3V6MX-1GP

1D5V_S0

12

SCD1U10V2KX-4GP

SB

R94

0R0603-PAD

C288

12

C500

C500 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

C281

SC22U6D3V5MX-2GP

1D05_VCCA_SM_CK

SC22U6D3V5MX-2GP

1D5V_S0

1 2

L10

L10 BLM18PG181SN-3GP

BLM18PG181SN-3GP

12

SCD1U10V2KX-4GP

C230

C284

12

C216

SC22U6D3V5MX-2GP

1

2

SC2D2U6D3V2MX-GP

R346

1 2

0R0603-PAD

3D3V_DAC

12

L29

VCCA_DAC

BLM18PG181SN-3GP

12

C525

SCD01U16V2KX-3GP

1D05_VCCA_SM_CK

12

C220

SC1U10V2KX-1GP

SC4D7U6D3V3KX-GP

12

DY

C231

C241

SCD1U10V2KX-4GP

12

C538

12

C240

SCD022U16V2KX-3GP

SCD1U10V2KX-4GP

12

SB

TC31

TC31 SC47U6D3V6MX-1GP

SC47U6D3V6MX-1GP

VCCA_CRT

R267

1 2

0R0603-PAD

SB

VCCA_DAC

12

C526

C521

SCD1U10V2KX-4GP

VCCA_DPLLA VCCA_DPLLB VCCA_HPLL VCCA_MPLL

SC1KP50V2KX-1GP

1D05_VCCA_SM_CK

12

C537

1 2

1D05V_VCCA_PLL

SCD1U10V2KX-4GP

SCD01U16V2KX-3GP

1D05V_S0

12

SCD1U10V2KX-4GP

12

C213

SCD1U10V2KX-4GP

C245 SCD1U10V2KX-4GPC245 SCD1U10V2KX-4GP

1D05V_VCCA_PLL

12

C239

C534

1D8V_TXLVDS_S0

C282

12

SCD01U16V2KX-3GP

VCC_HDA

C296

SCD1U10V2KX-4GP

12

SCD1U10V2KX-4GP

1D5V_S0

12

C285

VCCA_DAC

C520

VCCA_DAC

VCCD_QDAC_MCH

1D8V_S0

12

C198

SC1U10V2KX-1GP

NOTE:shared by VCCA_TV_DAC, VCCA_DAC_BG,VCCA_CRT_DAC

12

C533

SCD01U16V2KX-3GP

C286

SCD1U10V2KX-4GP

12

C268

C268 SC1U10V2KX-1GP

SC1U10V2KX-1GP

12

C510

U56H

B27

VCCA_CRT_DAC

A26

VCCA_CRT_DAC

A25

VCCA_DAC_BG

B25

VSSA_DAC_BG

F47

VCCA_DPLLA

L48

VCCA_DPLLB

AD1

VCCA_HPLL

AE1

VCCA_MPLL

J48

VCCA_LVDS

J47

VSSA_LVDS

AD48

VCCA_PEG_BG

AA48

VCCA_PEG_PLL

AR20

VCCA_SM

AP20

VCCA_SM

AN20

VCCA_SM

AR17

VCCA_SM

AP17

VCCA_SM

AN17

VCCA_SM

AT16

VCCA_SM

AR16

VCCA_SM

AP16

VCCA_SM

AP28

VCCA_SM_CK

AN28

VCCA_SM_CK

AP25

VCCA_SM_CK

AN25

VCCA_SM_CK

AN24

VCCA_SM_CK

AM28

VCCA_SM_CK_NCTF

AM26

VCCA_SM_CK_NCTF

AM25

VCCA_SM_CK_NCTF

AL25

VCCA_SM_CK_NCTF

AM24

VCCA_SM_CK_NCTF

AL24

VCCA_SM_CK_NCTF

AM23

VCCA_SM_CK_NCTF

AL23

VCCA_SM_CK_NCTF

B24

VCCA_TV_DAC

A24

VCCA_TV_DAC

A32

VCC_HDA

M25

VCCD_TVDAC

L28

VCCD_QDAC

AF1

VCCD_HPLL

AA47

VCCD_PEG_PLL

M38

VCCD_LVDS

L37

VCCD_LVDS

CANTIGA-GM-GP-U-NF

U54

VOUT

3

VIN

GND

APL5308-33AC-TRL-GP-U

2 1

CRTPLLA PEGA SM

A LVDS

POWER

A CK

TV

HDA

D TV/CRT

LVDS

12

C524

SC22U6D3V5MX-2GP

Near VCCA_CRT_DAC,VCCA_DAC_BG

8 OF 10

VTT

VCC_AXF VCC_AXF VCC_AXF

AXF

VCC_SM_CK VCC_SM_CK VCC_SM_CK VCC_SM_CK

SM CK

VCC_TX_LVDS

VCC_HV VCC_HV VCC_HV

HV

VCC_PEG VCC_PEG VCC_PEG VCC_PEG VCC_PEG

PEG

VCC_DMI VCC_DMI VCC_DMI VCC_DMI

DMI

VTTLF

A

B

C

R339

1 2

0R3-0-U-GP

VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT

VTTLF VTTLF VTTLF

U13 T13 U12 T12 U11 T11 U10 T10 U9 T9 U8 T8 U7 T7 U6 T6 U5 T5 V3 U3 V2 U2 T2 V1 U1

B22 B21 A21

BF21 BH20 BG20 BF20

K47 C35

B35 A35

V48 U48 V47 U47 U46

AH48 AF48 AH47 AG47

A8 L1 AB2

SB

3D3V_S03D3V_DAC

VTTLF1 VTTLF2 VTTLF3

VCC_AXF_MCH

12

SC10U6D3V5MX-3GP

SB

3D3V_VCC_HV

12

SC4D7U6D3V3KX-GP

VCC_DMIPEG_MCH

1

C163

2

SCD47U6D3V2KX-GP

SC4D7U6D3V3KX-GP

C512

C279

1

2

12

C154

C169

SC1U10V2KX-1GP

12

C228

SC4D7U6D3V3KX-GP

L27

1 2

IND-D1UH-10-GP

12

C515

1D8V_TXLVDS_S0

For VCC_PEG

12

C277

SC22U6D3V6KX-1GP

SCD1U10V2KX-4GP

1

C507

2

SCD47U6D3V2KX-GP

D

C283

12

C276

12

SC2D2U6D3V3MX-1-GP

SCD1U10V2KX-4GP

C177

1D05V_S0

1D5V_SM_CK

12

C513

SC1KP50V2KX-1GP

12

C544

SCD1U10V2KX-4GP

12

TC9

ST100U6D3VBM-5GP

12

R92

R92 1R2F-GP

1R2F-GP

1D5V_SM_CK_1

12

C207

SC10U6D3V5MX-3GP

R348

1 2

0R0603-PAD

L11

1 2

IND-91NH-1-GP

TC16

TC16 SC47U6D3V6MX-1GP

SC47U6D3V6MX-1GP

1D05V_S0

SCD1U10V2KX-4GP

12

C174

1D5V_S3

L28

1 2

COIL-1UH-31-GP

1D8V_TXLVDS_S0 1D8V_S0

L15

1 2

IND-D1UH-10-GP

12

C303

C303 SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

3D3V_S0

1D05V_S0

R349

1 2

10R2J-2-GP

3D3_1D05_HV

D21

2 1

CH521S-30-GP-U1

83.00521.01F

1D05V_S0

SC

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Cantiga(6/7):VCC

Size Document Number Rev

C

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

LZ2

13 41Friday, April 11, 2008

E

SB

of