LENEAD LTC2290 User Manual

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Page 1

查询LTC2290供应商

FEATURES

■

Integrated Dual 12-Bit ADCs

■

Sample Rate: 10Msps

■

Single 3V Supply (2.7V to 3.4V)

■

Low Power: 120mW

■

71.3dB SNR

■

90dB SFDR

■

110dB Channel Isolation

■

Multiplexed or Separate Data Bus

■

Flexible Input: 1V

■

575MHz Full Power Bandwidth S/H

■

Clock Duty Cycle Stabilizer

■

Shutdown and Nap Modes

■

Pin Compatible Family

P-P

to 2V

P-P

Range

80Msps: LTC2294 (12-Bit), LTC2299 (14-Bit) 65Msps: LTC2293 (12-Bit), LTC2298 (14-Bit) 40Msps: LTC2292 (12-Bit), LTC2297 (14-Bit) 25Msps: LTC2291 (12-Bit), LTC2296 (14-Bit) 10Msps: LTC2290 (12-Bit), LTC2295 (14-Bit)

■

64-Pin (9mm × 9mm) QFN Package

APPLICATIO S

LTC2290

Dual 12-Bit, 10Msps

Low Power 3V ADC

DESCRIPTIO

The LTC®2290 is a 12-bit 10Msps, low power dual 3V A/D converter designed for digitizing high frequency, wide dynamic range signals. The LTC2290 is perfect for demanding imaging and communications applications with AC performance that includes 71.3dB SNR and 90dB SFDR for signals well beyond the Nyquist frequency.

DC specs include ±0.3LSB INL (typ), ±0.15LSB DNL (typ) and no missing codes over temperature. The transition noise is a low 0.25LSB

A single 3V supply allows low power operation. A separate output supply allows the outputs to drive 0.5V to 3.3V logic. An optional multiplexer allows both channels to share a digital output bus.

A single-ended CLK input controls converter operation. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles.

, LTC and LT are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

RMS

■

Wireless and Wired Broadband Communication

■

Imaging Systems

■

Spectral Analysis

■

Portable Instrumentation

TYPICAL APPLICATIO

ANALOG INPUT A

CLK A

CLK B

ANALOG INPUT B

INPUT

S/H

–

CLOCK/DUTY CYCLE

CONTROL

CLOCK/DUTY CYCLE

CONTROL

INPUT

S/H

–

12-BIT PIPELINED ADC CORE

OUTPUT

DRIVERS

OUTPUT

DRIVERS

2290 TA01

D11A

•

D0A

OGND

MUX

D11B

•

D0B

OGND

Typical INL, 2V Range

1.0

0.8

0.6

0.4

0.2

–0.2

INL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

1024

2048

CODE

3072

4096

2290 TA01

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LTC2290

ABSOLUTE AXI U RATI GS

OVDD = VDD (Notes 1, 2)

Supply Voltage (VDD) ................................................. 4V

Digital Output Ground Voltage (OGND) ....... –0.3V to 1V

Analog Input Voltage (Note 3) ..... –0.3V to (V

Digital Input Voltage .................... –0.3V to (V

Digital Output Voltage ................– 0.3V to (OV

Power Dissipation............................................ 1500mW

Operating Temperature Range

LTC2290C ............................................... 0°C to 70°C

LTC2290I............................................. –40°C to 85°C

Storage Temperature Range ..................–65°C to 125°C

Lead Temperature (Soldering, 10 sec).................. 300°C

+ 0.3V)

UUW

PACKAGE/ORDER I FOR ATIO

TOP VIEW

64 GND

63 VDD62 SENSEA

61 VCMA

60 MODE

59 SHDNA

58 OEA

57 OFA

56 DA11

55 DA10

54 DA9

53 DA8

52 DA7

51 DA6

50 OGND

49 OV

INA+

–

INA

REFHA 3 REFHA 4 REFLA 5 REFLA 6

CLKA

8 CLKB 9 V

REFLB 11 REFLB 12 REFHB 13 REFHB 14

–

INB

GND

SENSEB

64-LEAD (9mm × 9mm) PLASTIC QFN

EXPOSED PAD (PIN 65) IS GND AND MUST BE SOLDERED TO PCB

NC 24

OEB 23

MUX 21

VCMB

SHDNB 22

UP PACKAGE

= 125°C, θJA = 20°C/W

JMAX

NC 25

DB0 26

DB1 27

DB2 28

ORDER PART

NUMBER

DB3 29

48 DA5 47 DA4 46 DA3 45 DA2 44 DA1 43 DA0 42 NC 41 NC 40 OFB 39 DB11 38 DB10 37 DB9 36 DB8 35 DB7 34 DB6 33 DB5

DB4 30

OGND 31

QFN PART*

MARKING

LTC2290CUP

LTC2290UP

LTC2290IUP

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

CO VERTER CHARACTERISTICS

temperature range, otherwise specifications are at TA = 25°C. (Note 4)

PARAMETER CONDITIONS MIN TYP MAX UNITS

Resolution (No Missing Codes) ● 12 Bits Integral Linearity Error Differential Analog Input (Note 5) ● –1.3 ±0.3 1.3 LSB Differential Linearity Error Differential Analog Input ● –0.7 ±0.15 0.7 LSB Offset Error (Note 6) ● –12 ±212 mV Gain Error External Reference ● –2.5 ±0.5 2.5 %FS Offset Drift ±10 µV/°C Full-Scale Drift Internal Reference ±30 ppm/°C

External Reference ±15 ppm/°C Gain Matching External Reference ±0.3 %FS Offset Matching ±2mV Transition Noise SENSE = 1V 0.25 LSB

The ● denotes the specifications which apply over the full operating

RMS

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LTC2290

A ALOG I PUT

specifications are at TA = 25°C. (Note 4)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

IN,CM

SENSE

MODE

JITTER

CMRR Analog Input Common Mode Rejection Ratio 80 dB

Analog Input Range (A

Analog Input Common Mode Differential Input (Note 7) ● 1 1.5 1.9 V

Analog Input Leakage Current 0V < A

SENSEA, SENSEB Input Leakage 0V < SENSEA, SENSEB < 1V ● –3 3 µA

MODE Input Leakage Current 0V < MODE < V

Sample-and-Hold Acquisition Delay Time 0 ns

Sample-and-Hold Acquisition Delay Time Jitter 0.2 ps

Full Power Bandwidth Figure 8 Test Circuit 575 MHz

DY A IC ACCURACY

otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

SNR Signal-to-Noise Ratio 5MHz Input ● 69.6 71.3 dB

SFDR Spurious Free Dynamic Range 5MHz Input ● 74 90 dB

2nd or 3rd Harmonic

SFDR Spurious Free Dynamic Range 5MHz Input ● 80 90 dB

4th Harmonic or Higher

S/(N+D) Signal-to-Noise Plus Distortion Ratio 5MHz Input ● 69 71.3 dB

Intermodulation Distortion fIN = 4.3MHz, 4.6MHz 90 dB

Crosstalk fIN = 5MHz –110 dB

The ● denotes the specifications which apply over the full operating temperature range, otherwise

–

–A

) 2.7V < V

< 3.4V (Note 7) ● 1V to 2V V

–

, A

< V

● –1 1 µA

● –3 3 µA

RMS

The ● denotes the specifications which apply over the full operating temperature range,

70MHz Input 70.7 dB

70MHz Input 85 dB

70MHz Input 90 dB

70MHz Input 70.4 dB

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LTC2290

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I TER AL REFERE CE CHARACTERISTICS

PARAMETER CONDITIONS MIN TYP MAX UNITS

VCM Output Voltage I

VCM Output Tempco ±30 ppm/°C

VCM Line Regulation 2.7V < VDD < 3.3V 3 mV/V

VCM Output Resistance –1mA < I

= 0 1.475 1.500 1.525 V

OUT

(Note 4)

< 1mA 4 Ω

OUT

DIGITAL I PUTS A D DIGITAL OUTPUTS

full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

LOGIC INPUTS (CLK, OE, SHDN, MUX)

LOGIC OUTPUTS

OVDD = 3V

SOURCE

SINK

= 2.5V

OVDD = 1.8V

High Level Input Voltage VDD = 3V ● 2V

Low Level Input Voltage VDD = 3V ● 0.8 V

Input Current VIN = 0V to V

Input Capacitance (Note 7) 3 pF

Hi-Z Output Capacitance OE = High (Note 7) 3 pF

Output Source Current V

Output Sink Current V

High Level Output Voltage IO = –10µA 2.995 V

Low Level Output Voltage IO = 10µA 0.005 V

High Level Output Voltage IO = –200µA 2.49 V

Low Level Output Voltage IO = 1.6mA 0.09 V

High Level Output Voltage IO = –200µA 1.79 V

Low Level Output Voltage IO = 1.6mA 0.09 V

= 0V 50 mA

OUT

= 3V 50 mA

OUT

= –200µA ● 2.7 2.99 V

= 1.6mA ● 0.09 0.4 V

The ● denotes the specifications which apply over the

● –10 10 µA

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LTC2290

POWER REQUIRE E TS

range, otherwise specifications are at T

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

DISS

SHDN

NAP

Analog Supply Voltage (Note 9) ● 2.7 3 3.4 V

Output Supply Voltage (Note 9) ● 0.5 3 3.6 V

Supply Current Both ADCs at f

Power Dissipation Both ADCs at f

Shutdown Power (Each Channel) SHDN = H, OE = H, No CLK 2 mW

Nap Mode Power (Each Channel) SHDN = H, OE = L, No CLK 15 mW

= 25°C. (Note 8)

The ● denotes the specifications which apply over the full operating temperature

S(MAX)

● 40 46 mA

● 120 138 mW

TI I G CHARACTERISTICS

range, otherwise specifications are at TA = 25°C. (Note 4)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Pipeline Latency 6 Cycles

Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired.

Note 2: All voltage values are with respect to ground with GND and OGND wired together (unless otherwise noted).

Note 3: When these pin voltages are taken below GND or above V will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup.

Note 4: VDD = 3V, f drive, unless otherwise noted.

Sampling Frequency (Note 9) ● 1 10 MHz

CLK Low Time Duty Cycle Stabilizer Off ● 40 50 500 ns

CLK High Time Duty Cycle Stabilizer Off ● 40 50 500 ns

Sample-and-Hold Aperture Delay 0 nS

CLK to DATA Delay CL = 5pF (Note 7) ● 1.4 2.7 5.4 ns

MUX to DATA Delay CL = 5pF (Note 7) ● 1.4 2.7 5.4 ns

Data Access Time After OE↓ CL = 5pF (Note 7) ● 4.3 10 ns

BUS Relinquish Time (Note 7) ● 3.3 8.5 ns

= 10MHz, input range = 2V

SAMPLE

The ● denotes the specifications which apply over the full operating temperature

● 5 50 500 ns

= 10MHz, input range = 1V

P-P

with differential

P-P

Duty Cycle Stabilizer On (Note 7)

Note 5: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band.

Note 6: Offset error is the offset voltage measured from –0.5 LSB when

, they

the output code flickers between 0000 0000 0000 and 1111 1111 1111.

Note 7: Guaranteed by design, not subject to test. Note 8: V

drive. The supply current and power dissipation are the sum total for both channels with both channels active.

Note 9: Recommended operating conditions.

= 3V, f

SAMPLE

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LTC2290

INPUT FREQUENCY (MHz)

100

30 50

2290 G09

10 20

40 60 70

SFDR (dBFS)

TYPICAL PERFOR A CE CHARACTERISTICS

Crosstalk vs Input Frequency

–100

–105

–110

–115

CROSSTALK (dB)

–120

–125

–130

20 40 60 80

INPUT FREQUENCY (MHz)

8192 Point FFT, f

–1dB, 2V Range

–10

–20

–30

–40

–50

–60

–70

AMPLITUDE (dB)

–80

–90

–100

–110

–120

FREQUENCY (MHz)

= 5.1MHz,

2290 G01

2290 G04

100

Typical INL, 2V Range Typical DNL, 2V Range

1.0

0.8

0.6

0.4

0.2

–0.2

INL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

1024

2048

CODE

8192 Point FFT, fIN = 70.1MHz, –1dB, 2V Range

–10

–20

–30

–40

–50

–60

–70

AMPLITUDE (dB)

–80

–90

–100

–110

–120

FREQUENCY (MHz)

3072

4096

2290 G02

2290 G05

1.0

0.8

0.6

0.4

0.2

–0.2

DNL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

1024

8192 Point 2-Tone FFT, fIN = 4.3MHz and 4.6MHz, –1dB, 2V Range

–10

–20

–30

–40

–50

–60

–70

AMPLITUDE (dB)

–80

–90

–100

–110

–120

FREQUENCY (MHz)

2048

CODE

3072

4096

2290 G03

2290 G06

Grounded Input Histogram

70000

60000

50000

40000

COUNT

30000

20000

10000

2155

2048

61758

2049

CODE

1607

2050

2290 G07

SNR vs Input Frequency, –1dB, 2V Range

SNR (dBFS)

INPUT FREQUENCY (MHz)

SFDR vs Input Frequency, –1dB, 2V Range

2290 G08

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TYPICAL PERFOR A CE CHARACTERISTICS

LTC2290

SNR and SFDR vs Sample Rate, 2V Range, f

100

SNR AND SFDR (dBFS)

2468

= 5MHz, –1dB

SAMPLE RATE (Msps)

vs Sample Rate,

VDD

10 12 14

5MHz Sine Wave Input, –1dB

(mA)

VDD

02468

SAMPLE RATE (Msps)

2V RANGE

1V RANGE

2290 G10

10 12 14

SNR vs Input Level, fIN = 5MHz, 2V Range

SNR (dBc AND dBFS)

–0

–60 –50 –30

–70

2290 G13

dBFS

dBc

–40

INPUT LEVEL (dBFS)

–20 –10 0

2290 G11

2.0

1.8

1.6

1.4

1.2

(mA)

1.0

OVDD

0.8

0.6

0.4

0.2

SFDR vs Input Level, fIN = 5MHz, 2V Range

120

110

100

SFDR (dBc AND dBFS)

–70

vs Sample Rate, 5MHz Sine

OVDD

Wave Input, –1dB, O

SAMPLE RATE (Msps)

–50

–60

VDD

dBFS

dBc

90dBc SFDR

REFERENCE LINE

–30

–40

INPUT LEVEL (dBFS)

= 1.8V

2290 G14

–20

–10

2290 G12

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LTC2290

PI FU CTIO S

(Pin 1): Channel A Positive Differential Analog

INA

Input.

–

(Pin 2): Channel A Negative Differential Analog

INA

Input.

REFHA (Pins 3, 4): Channel A High Reference. Short together and bypass to Pins 5, 6 with a 0.1µF ceramic chip capacitor as close to the pin as possible. Also bypass to Pins 5, 6 with an additional 2.2µF ceramic chip capacitor and to ground with a 1µF ceramic chip capacitor.

REFLA (Pins 5, 6): Channel A Low Reference. Short together and bypass to Pins 3, 4 with a 0.1µF ceramic chip capacitor as close to the pin as possible. Also bypass to Pins 3, 4 with an additional 2.2µF ceramic chip capacitor and to ground with a 1µF ceramic chip capacitor.

VDD (Pins 7, 10, 18, 63): Analog 3V Supply. Bypass to GND with 0.1µF ceramic chip capacitors.

CLKA (Pin 8): Channel A Clock Input. The input sample starts on the positive edge.

CLKB (Pin 9): Channel B Clock Input. The input sample starts on the positive edge.

REFLB (Pins 11, 12): Channel B Low Reference. Short together and bypass to Pins 13, 14 with a 0.1µF ceramic chip capacitor as close to the pin as possible. Also bypass to Pins 13, 14 with an additional 2.2µF ceramic chip ca- pacitor and to ground with a 1µF ceramic chip capacitor.

REFHB (Pins 13, 14): Channel B High Reference. Short together and bypass to Pins 11, 12 with a 0.1µF ceramic chip capacitor as close to the pin as possible. Also bypass to Pins 11, 12 with an additional 2.2µF ceramic chip ca- pacitor and to ground with a 1µF ceramic chip capacitor.

–

(Pin 15): Channel B Negative Differential Analog

INB

Input.

(Pin 16): Channel B Positive Differential Analog

INB

Input.

and a ±1V input range. An external reference greater than

0.5V and less than 1V applied to SENSEB selects an input range of ±V

(Pin 20): Channel B 1.5V Output and Input Common

CMB

Mode Bias. Bypass to ground with 2.2µF ceramic chip capacitor. Do not connect to V

MUX (Pin 21): Digital Output Multiplexer Control. If MUX is High, Channel A comes out on DA0-DA13, OFA; Channel B comes out on DB0-DB13, OFB. If MUX is Low, the output busses are swapped and Channel A comes out on DB0DB13, OFB; Channel B comes out on DA0-DA13, OFA. To multiplex both channels onto a single output bus, connect MUX, CLKA and CLKB together.

SHDNB (Pin 22): Channel B Shutdown Mode Selection Pin. Connecting SHDNB to GND and OEB to GND results in normal operation with the outputs enabled. Connecting SHDNB to GND and OEB to V tion with the outputs at high impedance. Connecting SHDNB to VDD and OEB to GND results in nap mode with the outputs at high impedance. Connecting SHDNB to V and OEB to VDD results in sleep mode with the outputs at high impedance.

OEB (Pin 23): Channel B Output Enable Pin. Refer to SHDNB pin function.

NC (Pins 24, 25, 41, 42): Do Not Connect These Pins.

DB0 – DB11 (Pins 26 to 30, 33 to 39): Channel B Digital

Outputs. DB11 is the MSB.

OGND (Pins 31, 50): Output Driver Ground.

OVDD (Pins 32, 49): Positive Supply for the Output Driv-

ers. Bypass to ground with 0.1µF ceramic chip capacitor.

OFB (Pin 40): Channel B Overflow/Underflow Output. High when an overflow or underflow has occurred.

DA0 – DA11 (Pins 43 to 48, 51 to 56): Channel A Digital Outputs. DA11 is the MSB.

. ±1V is the largest valid input range.

SENSEB

CMA

results in normal opera-

GND (Pins 17, 64): ADC Power Ground.

SENSEB (Pin 19): Channel B Reference Programming Pin.

Connecting SENSEB to V and a ±0.5V input range. VDD selects the internal reference

selects the internal reference

CMB

OFA (Pin 57): Channel A Overflow/Underflow Output. High when an overflow or underflow has occurred.

OEA (Pin 58): Channel A Output Enable Pin. Refer to SHDNA Pin Function.

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LTC2290

PI FU CTIO S

SHDNA (Pin 59): Channel A Shutdown Mode Selection Pin. Connecting SHDNA to GND and OEA to GND results in normal operation with the outputs enabled. Connecting SHDNA to GND and OEA to VDD results in normal operation with the outputs at high impedance. Connecting SHDNA to V the outputs at high impedance. Connecting SHDNA to V

and OEA to GND results in nap mode with

and OEA to VDD results in sleep mode with the outputs at high impedance.

MODE (Pin 60): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Note that MODE controls both channels. Connecting MODE to GND selects straight binary output format and turns the clock duty cycle stabilizer off. 1/3 VDD selects straight binary output format and turns the clock duty cycle stabilizer on. 2/3 VDD selects 2’s complement output format and turns the clock duty cycle

FUNCTIONAL BLOCK DIAGRA

stabilizer on. VDD selects 2’s complement output format and turns the clock duty cycle stabilizer off.

(Pin 61): Channel A 1.5V Output and Input Common

CMA

Mode Bias. Bypass to ground with 2.2µF ceramic chip capacitor. Do not connect to V

CMB

SENSEA (Pin 62): Channel A Reference Programming Pin. Connecting SENSEA to V and a ±0.5V input range. V

selects the internal reference

CMA

selects the internal reference

and a ±1V input range. An external reference greater than

0.5V and less than 1V applied to SENSEA selects an input range of ±V

SENSEA

. ±1V is the largest valid input range.

GND (Exposed Pad) (Pin 65): ADC Power Ground. The Exposed Pad on the bottom of the package needs to be soldered to ground.

2.2µF

SENSE

INPUT

S/H

–

1.5V

REFERENCE

RANGE SELECT

FIRST PIPELINED

ADC STAGE

REF

BUF

SECOND PIPELINED

ADC STAGE

DIFF REF

AMP

REFH

THIRD PIPELINED

0.1µF

2.2µF

ADC STAGE

INTERNAL CLOCK SIGNALSREFH REFL

REFL

FOURTH PIPELINED

CLOCK/DUTY

CYCLE

CONTROL

CLK

ADC STAGE

FIFTH PIPELINED

CONTROL

LOGIC

SHDN

ADC STAGE

OEMODE

SIXTH PIPELINED

ADC STAGE

SHIFT REGISTER

AND CORRECTION

OUTPUT

DRIVERS

OGND

2290 F01

D11

•

1µF1µF

Figure 1. Functional Block Diagram (Only One Channel is Shown)

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LTC2290

WUW

TI I G DIAGRA S

ANALOG

INPUT

CLK

D0-D11, OF

ANALOG INPUT A

ANALOG INPUT B

N – 6

Dual Digital Output Bus Timing

(Only One Channel is Shown)

N + 2

N + 1

N – 5 N – 4 N – 3 N – 2

N + 3

N + 4

N + 5

N – 1

2290 TD01

Multiplexed Digital Output Bus Timing

APA

APB

A + 1

B + 1

A + 2

A + 3

B + 2

B + 3

A + 4

B + 4

CLKA = CLKB = MUX

D0A-D11A, OFA

D0B-D11B, OFB

A – 6

B – 6

A – 6

A – 5

B – 5

A – 5

A – 4

B – 4

A – 4

A – 3

B – 3

A – 3

A – 2

B – 2

2290 TD02

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WUUU

APPLICATIO S I FOR ATIO

LTC2290

DYNAMIC PERFORMANCE

Signal-to-Noise Plus Distortion Ratio

The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency.

Signal-to-Noise Ratio

The signal-to-noise ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components except the first five harmonics and DC.

Total Harmonic Distortion

Total harmonic distortion is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as:

2fb + fa, 2fa – fb and 2fb – fa. The intermodulation distortion is defined as the ratio of the RMS value of either input tone to the RMS value of the largest 3rd order intermodulation product.

Spurious Free Dynamic Range (SFDR)

Spurious free dynamic range is the peak harmonic or spurious noise that is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full scale input signal.

Input Bandwidth

The input bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full scale input signal.

Aperture Delay Time

The time from when CLK reaches midsupply to the instant that the input signal is held by the sample and hold circuit.

Aperture Delay Jitter

THD = 20Log √(V22 + V32 + V42 + . . . Vn2)/V1

where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through nth harmonics. The THD calculated in this data sheet uses all the harmonics up to the fifth.

Intermodulation Distortion

If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency.

If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. The 3rd order intermodulation products are 2fa + fb,

The variation in the aperture delay time from conversion to conversion. This random variation will result in noise when sampling an AC input. The signal to noise ratio due to the jitter alone will be:

SNR

Crosstalk

Crosstalk is the coupling from one channel (being driven by a full-scale signal) onto the other channel (being driven by a –1dBFS signal).

CONVERTER OPERATION

As shown in Figure 1, the LTC2290 is a dual CMOS pipelined multistep converter. The converter has six pipelined ADC stages; a sampled analog input will result in a digitized value six cycles later (see the Timing Diagram section). For optimal AC performance the analog inputs should be driven differentially. For cost sensitive

= –20log (2π) • fIN • t

JITTER

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LTC2290

WUU

APPLICATIO S I FOR ATIO

applications, the analog inputs can be driven single-ended with slightly worse harmonic distortion. The CLK input is single-ended. The LTC2290 has two phases of operation, determined by the state of the CLK input pin.

Each pipelined stage shown in Figure 1 contains an ADC, a reconstruction DAC and an interstage residue amplifier. In operation, the ADC quantizes the input to the stage and the quantized value is subtracted from the input by the DAC to produce a residue. The residue is amplified and output by the residue amplifier. Successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and vice versa.

When CLK is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the “Input S/H” shown in the block diagram. At the instant that CLK transitions from low to high, the sampled input is held. While CLK is high, the held input voltage is buffered by the S/H amplifier which drives the first pipelined ADC stage. The first stage acquires the output of the S/H during this high phase of CLK. When CLK goes back low, the first stage produces its residue which is acquired by the second stage. At the same time, the input S/H goes back to acquiring the analog input. When CLK goes back high, the second stage produces its residue which is acquired by the third stage. An identical process is repeated for the

third, fourth and fifth stages, resulting in a fifth stage residue that is sent to the sixth stage ADC for final evaluation.

Each ADC stage following the first has additional range to accommodate flash and amplifier offset errors. Results from all of the ADC stages are digitally synchronized such that the results can be properly combined in the correction logic before being sent to the output buffer.

SAMPLE/HOLD OPERATION AND INPUT DRIVE

Sample/Hold Operation

Figure 2 shows an equivalent circuit for the LTC2290 CMOS differential sample-and-hold. The analog inputs are connected to the sampling capacitors (C

SAMPLE

) through NMOS transistors. The capacitors shown attached to each input (C

PARASITIC

) are the summation of all other capaci-

tance associated with each input.

During the sample phase when CLK is low, the transistors connect the analog inputs to the sampling capacitors and they charge to and track the differential input voltage. When CLK transitions from low to high, the sampled input voltage is held on the sampling capacitors. During the hold phase when CLK is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the ADC core for processing. As CLK transitions from

CLK

LTC2290

15Ω

–

Figure 2. Equivalent Input Circuit

PARASITIC

1pF

PARASITIC

1pF

SAMPLE

4pF

SAMPLE

4pF

2290 F02

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APPLICATIO S I FOR ATIO

LTC2290

high to low, the inputs are reconnected to the sampling capacitors to acquire a new sample. Since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. If the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. If the input change is large, such as the change seen with input frequencies near Nyquist, then a larger charging glitch will be seen.

Single-Ended Input

For cost sensitive applications, the analog inputs can be driven single-ended. With a single-ended input the harmonic distortion and INL will degrade, but the SNR and DNL will remain unchanged. For a single-ended input, A should be driven with the input signal and A

–

should be

connected to 1.5V or VCM.

Common Mode Bias

For optimal performance the analog inputs should be driven differentially. Each input should swing ±0.5V for the 2V range or ±0.25V for the 1V range, around a common mode voltage of 1.5V. The VCM output pin may be used to provide the common mode bias level. VCM can be tied directly to the center tap of a transformer to set the DC input level or as a reference level to an op amp differential driver circuit. The VCM pin must be bypassed to ground close to the ADC with a 2.2µF or greater capacitor.

Input Drive Impedance

As with all high performance, high speed ADCs, the dynamic performance of the LTC2290 can be influenced by the input drive circuitry, particularly the second and third harmonics. Source impedance and reactance can influence SFDR. At the falling edge of CLK, the sampleand-hold circuit will connect the 4pF sampling capacitor to the input pin and start the sampling period. The sampling period ends when CLK rises, holding the sampled input on the sampling capacitor. Ideally the input circuitry should

be fast enough to fully charge the sampling capacitor during the sampling period 1/(2F

ENCODE

); however, this is not always possible and the incomplete settling may degrade the SFDR. The sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling.

For the best performance, it is recommended to have a source impedance of 100Ω or less for each input. The source impedance should be matched for the differential inputs. Poor matching will result in higher even order harmonics, especially the second.

Input Drive Circuits

Figure 3 shows the LTC2290 being driven by an RF transformer with a center tapped secondary. The secondary center tap is DC biased with VCM, setting the ADC input signal at its optimum DC level. Terminating on the transformer secondary is desirable, as this provides a common mode path for charging glitches caused by the sample and hold. Figure 3 shows a 1:1 turns ratio transformer. Other turns ratios can be used if the source impedance seen by the ADC does not exceed 100Ω for each ADC input. A disadvantage of using a transformer is the loss of low frequency response. Most small RF transformers have poor performance at frequencies below 1MHz.

2.2µF

0.1µFT1

ANALOG

INPUT

Figure 3. Single-Ended to Differential Conversion Using a Transformer

1:1

T1 = MA/COM ETC1-1T RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE

25Ω

0.1µF

25Ω

12pF

LTC2290

–

2290 F03

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LTC2290

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APPLICATIO S I FOR ATIO

Figure 4 demonstrates the use of a differential amplifier to convert a single ended input signal into a differential input signal. The advantage of this method is that it provides low frequency input response; however, the limited gain bandwidth of most op amps will limit the SFDR at high input frequencies.

2.2µF

12pF

LTC2290

–

2290 F04

ANALOG

INPUT

HIGH SPEED

DIFFERENTIAL

AMPLIFIER

–

25Ω

Figure 4. Differential Drive with an Amplifier

Figure 5 shows a single-ended input circuit. The impedance seen by the analog inputs should be matched. This circuit is not recommended if low distortion is required.

Reference Operation

Figure 6 shows the LTC2290 reference circuitry consisting of a 1.5V bandgap reference, a difference amplifier and switching and control circuit. The internal voltage reference can be configured for two pin selectable input ranges of 2V (±1V differential) or 1V (±0.5V differential). Tying the SENSE pin to VDD selects the 2V range; tying the SENSE pin to V

selects the 1V range.

The 1.5V bandgap reference serves two functions: its output provides a DC bias point for setting the common mode voltage of any external input circuitry; additionally, the reference is used with a difference amplifier to generate the differential reference levels needed by the internal ADC circuitry. An external bypass capacitor is required for the 1.5V reference output, VCM. This provides a high frequency low impedance path to ground for internal and external circuitry.

LTC2290

4Ω

1.5V

2.2µF

1.5V BANDGAP REFERENCE

0.5V

2.2µF

12pF

LTC2290

–

2290 F05

ANALOG

INPUT

0.1µF

25Ω

0.1µF

Figure 5. Single-Ended Drive

The 25Ω resistors and 12pF capacitor on the analog inputs serve two purposes: isolating the drive circuitry from the sample-and-hold charging glitches and limiting the wideband noise at the converter input.

TIE TO V

RANGE = 2 • V

0.5V < V

RANGE

DETECT

AND

FOR 2V RANGE;

FOR 1V RANGE;

SENSE

1µF

2.2µF

1µF

FOR

< 1V

SENSE

CONTROL

REFH

0.1µF

REFL

Figure 6. Equivalent Reference Circuit

INTERNAL ADC HIGH REFERENCE

DIFF AMP

INTERNAL ADC LOW REFERENCE

BUFFER

2290 F06

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APPLICATIO S I FOR ATIO

LTC2290

The difference amplifier generates the high and low reference for the ADC. High speed switching circuits are connected to these outputs and they must be externally bypassed. Each output has two pins. The multiple output pins are needed to reduce package inductance. Bypass capacitors must be connected as shown in Figure 6. Each ADC channel has an independent reference with its own bypass capacitors. The two channels can be used with the same or different input ranges.

Other voltage ranges between the pin selectable ranges can be programmed with two external resistors as shown in Figure 7. An external reference can be used by applying its output directly or through a resistor divider to SENSE. It is not recommended to drive the SENSE pin with a logic device. The SENSE pin should be tied to the appropriate level as close to the converter as possible. If the SENSE pin is driven externally, it should be bypassed to ground as close to the device as possible with a 1µF ceramic capacitor. For the best channel matching, connect an external reference to SENSEA and SENSEB.

1.5V

12k

0.75V

12k

2.2µF

SENSE

1µF

LTC2290

2290 F07

Driving the Clock Input

The CLK inputs can be driven directly with a CMOS or TTL level signal. A sinusoidal clock can also be used along with a low jitter squaring circuit before the CLK pin (Figure 8).

CLEAN

FERRITE

BEAD

0.1µF

CLK

SUPPLY

LTC2290

2290 F08

4.7µF

NC7SVU04

SINUSOIDAL

CLOCK

INPUT

Figure 8. Sinusoidal Single-Ended CLK Drive

0.1µF

50Ω

The noise performance of the LTC2290 can depend on the clock signal quality as much as on the analog input. Any noise present on the clock signal will result in additional aperture jitter that will be RMS summed with the inherent ADC aperture jitter.

In applications where jitter is critical, such as when digitizing high input frequencies, use as large an amplitude as possible. Also, if the ADC is clocked with a sinusoidal signal, filter the CLK signal to reduce wideband noise and distortion products generated by the source.

Figure 7. 1.5V Range ADC

Input Range

The input range can be set based on the application. The 2V input range will provide the best signal-to-noise performance while maintaining excellent SFDR. The 1V input range will have better SFDR performance, but the SNR will degrade by 3.8dB. See the Typical Performance Characteristics section.

It is recommended that CLKA and CLKB are shorted together and driven by the same clock source. If a small time delay is desired between when the two channels sample the analog inputs, CLKA and CLKB can be driven by two different signals. If this delay exceeds 1ns, the performance of the part may degrade. CLKA and CLKB should not be driven by asynchronous signals.

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LTC2290

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APPLICATIO S I FOR ATIO

Maximum and Minimum Conversion Rates

The maximum conversion rate for the LTC2290 is 10Msps. For the ADC to operate properly, the CLK signal should have a 50% (±10%) duty cycle. Each half cycle must have at least 40ns for the ADC internal circuitry to have enough settling time for proper operation.

An optional clock duty cycle stabilizer circuit can be used if the input clock has a non 50% duty cycle. This circuit uses the rising edge of the CLK pin to sample the analog input. The falling edge of CLK is ignored and the internal falling edge is generated by a phase-locked loop. The input clock duty cycle can vary and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. If the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require a hundred clock cycles for the PLL to lock onto the input clock. To use the clock duty cycle stabilizer, the MODE pin should be connected to 1/3VDD or 2/3VDD using external resistors. The MODE pin controls both Channel A and Channel B—the duty cycle stabilizer is either on or off for both channels.

DIGITAL OUTPUTS

Digital Output Buffers

Figure 9 shows an equivalent circuit for a single output buffer. Each buffer is powered by OVDD and OGND, isolated from the ADC power and ground. The additional N-channel transistor in the output driver allows operation down to low voltages. The internal resistor in series with the output makes the output appear as 50Ω to external circuitry and may eliminate the need for external damping resistors.

LTC2290

DATA

FROM

LATCH

PREDRIVER

LOGIC

43Ω

OGND

0.5V TO V

0.1µF

TYPICAL DATA OUTPUT

The lower limit of the LTC2290 sample rate is determined by droop of the sample-and-hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specified minimum operating frequency for the LTC2290 is 1Msps.

2290 F09

Figure 9. Digital Output Buffer

As with all high speed/high resolution converters, the digital output loading can affect the performance. The digital outputs of the LTC2290 should drive a minimal capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. The output should be buffered with a device such as an ALVCH16373 CMOS latch. For full speed operation the capacitive load should be kept under 10pF.

Lower OVDD voltages will also help reduce interference from the digital outputs.

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APPLICATIO S I FOR ATIO

Data Format

Using the MODE pin, the LTC2290 parallel digital output can be selected for offset binary or 2’s complement format. Note that MODE controls both Channel A and Channel B. Connecting MODE to GND or 1/3VDD selects straight binary output format. Connecting MODE to 2/3VDD or VDD selects 2’s complement output format. An external resistor divider can be used to set the 1/3VDD or 2/3V MODE pin.

Table 1. MODE Pin Function

MODE Pin Output Format Cycle Stabilizer

0 Straight Binary Off

1/3V

2/3V

Overflow Bit

When OF outputs a logic high the converter is either overranged or underranged.

Output Driver Power

Separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. The power supply for the digital output buffers, OVDD, should be tied to the same power supply as for the logic being driven. For example, if the converter is driving a DSP powered by a 1.8V supply, then OVDD should be tied to that same 1.8V supply.

logic values. Table 1 shows the logic states for the

Clock Duty

Straight Binary On

2’s Complement On

2’s Complement Off

OVDD can be powered with any voltage from 500mV up to

3.6V. OGND can be powered with any voltage from GND up to 1V and must be less than OV swing between OGND and OV

. The logic outputs will

Output Enable

The outputs may be disabled with the output enable pin, OE. OE high disables all data outputs including OF. Channels A and B have independent output enable pins (OEA, OEB).

Sleep and Nap Modes

The converter may be placed in shutdown or nap modes to conserve power. Connecting SHDN to GND results in normal operation. Connecting SHDN to VDD and OE to V

results in sleep mode, which powers down all circuitry including the reference and typically dissipates 1mW. When exiting sleep mode it will take milliseconds for the output data to become valid because the reference capacitors have to recharge and stabilize. Connecting SHDN to VDD and OE to GND results in nap mode, which typically dissipates 30mW. In nap mode, the on-chip reference circuit is kept on, so that recovery from nap mode is faster than that from sleep mode, typically taking 100 clock cycles. In both sleep and nap modes, all digital outputs are disabled and enter the Hi-Z state.

Channels A and B have independent SHDN pins (SHDNA, SHDNB). Channel A is controlled by SHDNA and OEA, and Channel B is controlled by SHDNB and OEB. The nap, sleep and output enable modes of the two channels are completely independent, so it is possible to have one channel operating while the other channel is in nap or sleep mode.

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LTC2290

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APPLICATIO S I FOR ATIO

Digital Output Mulitplexer

The digital outputs of the LTC2290 can be multiplexed onto a single data bus. The MUX pin is a digital input that swaps the two data busses. If MUX is High, Channel A comes out on DA0-DA11, OFA; Channel B comes out on DB0-DB11, OFB. If MUX is Low, the output busses are swapped and Channel A comes out on DB0-DB11, OFB; Channel B comes out on DA0-DA11, OFA. To multiplex both channels onto a single output bus, connect MUX, CLKA and CLKB together (see the Timing Diagram for the multiplexed mode). The multiplexed data is available on either data bus—the unused data bus can be disabled with its OE pin.

Grounding and Bypassing

The LTC2290 requires a printed circuit board with a clean, unbroken ground plane. A multilayer board with an internal ground plane is recommended. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC.

High quality ceramic bypass capacitors should be used at the V capacitors must be located as close to the pins as possible. Of particular importance is the 0.1µF capacitor between REFH and REFL. This capacitor should be placed as close to the device as possible (1.5mm or less). A size 0402 ceramic capacitor is recommended. The large 2.2µF capacitor between REFH and REFL can be somewhat further away. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible.

The LTC2290 differential inputs should run parallel and close to each other. The input traces should be as short as possible to minimize capacitance and to minimize noise pickup.

Heat Transfer

Most of the heat generated by the LTC2290 is transferred from the die through the bottom-side exposed pad and package leads onto the printed circuit board. For good electrical and thermal performance, the exposed pad should be soldered to a large grounded pad on the PC board. It is critical that all ground pins are connected to a ground plane of sufficient area.

, OVDD, VCM, REFH, and REFL pins. Bypass

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Page 19

LTC2290

C21

0.1µF

C27

0.1µF

CMB

C20

2.2µF

C18 1µF

C23 1µF

C34

0.1µF

C31

12pF

C17

0.1µF

C14

0.1µF

C25

0.1µF

C30

18pF

47nH

R28

Ω

C32

18pF

C28

2.2µF

C35

0.1µF

C24

0.1µF

C36

4.7µF

PWR

GND

228876 AI01

0.1µF

R16

33Ω

R10

R14

49.9Ω

R20

24.9Ω

R18

24.9Ω

R24

24.9Ω

R17

OPT

R22

24.9Ω

R23

ETC1-1T

C29

0.1µF

C33

0.1µF

CLOCK

INPUT

NC7SVU04

NC7SV86P5X

NC7SVU04

C13

0.1µF

C15

0.1µF

C12

4.7µF

6.3V

BEAD

C19

0.1µF

C11

0.1µF

2.2µF

C10

2.2µF

C9 1µF

C13 1µF

R15

ANALOG

INPUT B

••

CMB

0.1µF

12pF

C44

0.1µF

24.9Ω

OPT

24.9Ω

ETC1-1T

0.1µF

ANALOG

INPUT A

••

CMA

2/3V

1/3V

GND

JP1 MODE

C16 0.1µF

3201S-40G1

R13

10k

R11

10k

R12

10k

R30

Ω

N1D

33Ω

N1C

33Ω

N1B

33Ω

N1A

33Ω

N2D

33Ω

N2C

33Ω

N2B

33Ω

N2A

33Ω

N3D

33Ω

N3C

33Ω

N3B

33Ω

N3A

33Ω

N4D

33Ω

N4C

33Ω

N4B

33Ω

C39

1µF

C38

0.01µF

BYP

GND

ADJ

OUT

SHDN

GND

LT1763

GND

R26

100k

R25

105k

C37

10µF

6.3V

GND

C40

0.1µF

C41

0.1µF

INA

–

REFHA

REFLA

CLKA

CLKB

REFLB

REFHB

INB

–

INB

DA5

DA4

DA3

DA2

DA1

DA0

OFB

DB11

DB10

DB9

DB8

DB7

DB6

DB5

GND

SENSEA

VCMA

MODE

SHDNA

OEA

OFA

DA11

DA10

DA9

DA8

DA7

DA6

OGND

GND

SENSEB

VCMB

MUX

SHDNB

OEB

DB0

DB1

DB2

DB3

DB4

OGND

EXT

REF B

CMB

EXT REF

JP3 SENSE

EXT

REF A

EXT REF

JP2 SENSE A

0.1µF

C26

0.1µF

74VCX245BQX

T/R

GND

74VCX245BQX

T/R

GND

SCL

SDA

R29

Ω

47nH

C43

8.2pF

47nH

C42

8.2pF

24LC025

R31

TBD

R27

TBD

U10

NC7SV86P5X

R32

22Ω

LTC2290

WUU

APPLICATIO S I FOR ATIO

2290f

Page 20

LTC2290

WUU

APPLICATIO S I FOR ATIO

Silkscreen Top

Top Side

2290f

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LTC2290

WUU

APPLICATIO S I FOR ATIO

Inner Layer 2 GND

Inner Layer 3 Power

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LTC2290

WUU

APPLICATIO S I FOR ATIO

Bottom Side

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Page 23

PACKAGE DESCRIPTIO

LTC2290

UP Package

64-Lead Plastic QFN (9mm × 9mm)

(Reference LTC DWG # 05-08-1705)

0.70 ±0.05

0.25 ±0.05

0.50 BSC

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

9 .00 ± 0.10

(4 SIDES)

PIN 1 TOP MARK (SEE NOTE 5)

7.15 ±0.05 (4 SIDES)

8.10 ±0.05 9.50 ±0.05

PACKAGE OUTLINE

0.75 ± 0.05

7.15 ± 0.10 (4-SIDES)

R = 0.115

TYP

PIN 1

CHAMFER

6463

0.40 ± 0.10

1 2

0.200 REF

NOTE:

1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-5

2. ALL DIMENSIONS ARE IN MILLIMETERS

3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT

4. EXPOSED PAD SHALL BE SOLDER PLATED

5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

6. DRAWING NOT TO SCALE

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

0.00 – 0.05

BOTTOM VIEW—EXPOSED PAD

0.25 ± 0.05

0.50 BSC

(UP64) QFN 1003

2290f

Page 24

LTC2290

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS

LTC2220 12-Bit, 170Msps ADC 890mW, 67.5dB SNR, 9mm × 9mm QFN Package

LTC2221 12-Bit, 135Msps ADC 630mW, 67.5dB SNR, 9mm × 9mm QFN Package

LTC2222 12-Bit, 105Msps ADC 475mW, 67.9dB SNR, 7mm × 7mm QFN Package

LTC2223 12-Bit, 80Msps ADC 366mW, 68dB SNR, 7mm × 7mm QFN Package

LTC2224 12-Bit, 135Msps ADC 630mW, 67.5dB SNR, 7mm × 7mm QFN Package

LTC2225 12-Bit, 10Msps ADC 60mW, 71.4dB SNR, 5mm × 5mm QFN Package

LTC2226 12-Bit, 25Msps ADC 75mW, 71.4dB SNR, 5mm × 5mm QFN Package

LTC2227 12-Bit, 40Msps ADC 120mW, 71.4dB SNR, 5mm × 5mm QFN Package

LTC2228 12-Bit, 65Msps ADC 205mW, 71.3dB SNR, 5mm × 5mm QFN Package

LTC2230 10-Bit, 170Msps ADC 890mW, 67.5dB SNR, 9mm × 9mm QFN Package

LTC2231 10-Bit, 135Msps ADC 630mW, 67.5dB SNR, 9mm × 9mm QFN Package

LTC2232 10-Bit, 105Msps ADC 475mW, 61.3dB SNR, 7mm × 7mm QFN Package

LTC2233 10-Bit, 80Msps ADC 366mW, 61.3dB SNR, 7mm × 7mm QFN Package

LTC2245 14-Bit, 10Msps ADC 60mW, 74.4dB SNR, 5mm × 5mm QFN Package

LTC2246 14-Bit, 25Msps ADC 75mW, 74.5dB SNR, 5mm × 5mm QFN Package

LTC2247 14-Bit, 40Msps ADC 120mW, 74.4dB SNR, 5mm × 5mm QFN Package

LTC2248 14-Bit, 65Msps ADC 205mW, 74.3dB SNR, 5mm × 5mm QFN Package

LTC2249 14-Bit, 80Msps ADC 222mW, 73dB SNR, 5mm × 5mm QFN Package

LTC2291 12-Bit, Dual, 25Msps ADC 150mW, 74.5dB SNR, 9mm × 9mm QFN Package

LTC2292 12-Bit, Dual, 40Msps ADC 235mW, 74.4dB SNR, 9mm × 9mm QFN Package

LTC2293 12-Bit, Dual, 65Msps ADC 400mW, 74.3dB SNR, 9mm × 9mm QFN Package

LTC2295 14-Bit, Dual, 10Msps ADC 120mW, 74.4dB SNR, 9mm × 9mm QFN Package

LTC2296 14-Bit, Dual, 25Msps ADC 150mW, 74.5dB SNR, 9mm × 9mm QFN Package

LTC2297 14-Bit, Dual, 40Msps ADC 235mW, 74.4dB SNR, 9mm × 9mm QFN Package

LTC2298 14-Bit, Dual, 65Msps ADC 400mW, 74.3dB SNR, 9mm × 9mm QFN Package

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507

●

www.linear.com

2290f

LT/TP 1204 1K • PRINTED IN USA