LeCroy WaveRunner 6000, WaveRunner 6030, WaveRunner 6050, WaveRunner 6100, WaveRunner 6051 Service manual

LeCroy Color Digital Oscilloscopes
WaveRunner 6000 Series
Service Manual

Version B- August 2004

WAVERUNNER-SM-E ECO B

LeCroy Corporate Headquarters

700 Chestnut Ridge Road
Chestnut Ridge, NY 10977-6499
USA

Tel : [phone]
http://www.lecroy.com

LeCroy European Service
LeCroy SA

4, Rue Moïse Marcinhes
Case postale 341
1217 Meyrin 1
Geneva

Tel : [phone]

LeCroy Japan Service

LeCroy Japan Corporation
Sasazuka Center Bldg. – 6th floor,
1-6, 2-Chome, Sasazuka, Shibuya-ku
Tokyo Japan 151-0073

Tel. [phone]

© 2003 by LeCroy Corporation. All rights reserved.

LeCroy, ActiveDSO, ProBus, SMART Trigger, WavePro, and Waverunner are registered
trademarks of LeCroy Corporation. JitterTrack, WaveMaster, and X-Stream are trademarks
of LeCroy Corporation. Information in this publication supersedes all earlier versions.
Specifications subject to change without notice.

Table of Contents i

Read this first

Warranty 1-1

1. Warranty and Product Support 1-1

1.2 Product Assistance 1-1

1.3 Maintenance Agreements 1-1

1.4 Staying Up to Date 1-2

1.5 Service and Repair 1-2

1.6 How to return a Product 1-2

1.7 What Comes with Your Scope 1-2

General Information 2-1

2.1 Product Assistance 2-1

2.2 Installation for Safe and Efficient Operation 2-1
Operating Environment 2-1
Safety Symbols 2-1
Power Requirements 2-3
Cleaning and Maintenance 2-3
Power On 2-3

Specifications 3-1

3.1 Vertical System 3-1

3.2 Horizontal System 3-1

3.3 Acquisition System 3-2

3.4 Acquisition Processing 3-2

3.5 Triggering System 3-2

3.6 Basic Triggers 3-3

3.7 SMART Triggers® 3-3

3.8 SMART Triggers with Exclusion Technology 3-3

3.9 Probes 3-3

3.10 Color Waveform Display 3-3

3.11 Analog Persistence Display 3-4

3.12 Zoom Expansion Traces 3-4

3.13 CPU 3-4

3.14 Internal Waveform Memory 3-4

3.15 Setup Storage 3-4

3.16 Interface 3-4

3.17 Auxiliary Input 3-4

3.18 General 3-4

3.19 Environmental 3-5

3.20 Physical Dimensions 3-5

3.21 Certifications 3-5

3.22 Warranty and Service 3-5

ii Table of Contents

Theory of Operation

System Block Diagram 4-1

4.2 Computer 4-2

4.2.1 Operating System 4-2

4.2.2 Memory 4-2

4.2.3 Interfaces 4-2

4.2.4 Storage Devices 4-2

4.2.5 CMOS Settings 4-2

4.3 PCI Card 4-3

4.4 USB Hub 4-3

4.5 Display and Touch Screen 4-4

4.5.1 Color LCD Module 4-4

4.5.2 Inverter 4-4

4.5.3 Touch Screen 4-4

4.6 Acquisition System 4-5

4.6.1 Main Card 4-6

4.6.1.1 JTAG Chains 4-7

4.6.1.2 Serial chains 4-7

4.6.1.3 Controller FPGA 4-8

4.6.1.4 MicroController 4-8

4.6.1.5 Timebase & Trigger 4-9

4.6.1.5.1 HTB645 4-9

4.6.1.5.1.1 Trigger Bandwidth 4-9

4.6.1.5.1.2 Trigger Signal I/O 4-10

4.6.1.5.1.3 TDC 4-10

4.6.1.5.1.4 Timebase 4-10

4.6.1.5.1.5 Miscellaneous clocks 4-10

4.6.1.5.2 MST429A – Smart Trigger IC 4-10

4.6.1.5.2.1 Signal I/O 4-10

4.6.1.5.2.2 Trigger Functions 4-10

4.6.1.5.2.3 Main trigger delay 4-10

4.6.1.5.2.4 Qualifier selection 4-10

4.6.1.5.2.5 Polarity 4-10

4.6.1.5.2.6 Analog Time Measure 4-10

4.6.1.5.2.7 Digital Time Measure 4-10

4.6.1.5.2.8 Trigger Frequency 4-11

4.6.2 ADC & Memory 4-11

4.6.2.1 HAD639 4-11

4.6.2.1.1 Signal I/O 4-11

4.6.2.1.2 ADC’s 4-11

4.6.2.1.3 Calibration 4-11

4.6.2.1.4 Control 4-11

4.6.2.2 MAM439 4-12

4.6.2.2.1 Signal I/O 4-12

4.6.2.2.2 Control 4-12

4.6.2.2.3 Decimation 4-12

4.6.2.3 8b/10b Bus 4-12

4.6.3 Front End 4-13

4.6.3.1 Input Coupling 4-13

4.6.3.2 50Ω Path 4-13

4.6.3.3 1MΩ Path 4-14

4.6.3.4 HFE653 4-14

4.6.3.5 Amplifier Signal Path 4-15

4.6.3.5.1 Power Off State 4-15

4.6.3.5.2 50Ω /1 Path 4-16

4.6.3.5.3 50Ω /10 Path 4-16

4.6.3.5.4 1MΩ /1 Path DC Coupled 4-17

4.6.3.5.5 1MΩ /10 Path DC Coupled 4-17

4.6.3.5.6 1MΩ /100 Path DC Coupled 4-18

4.6.3.5.7 1MΩ /1 Path AC Coupled 4-18

4.6.4 Other Sub Systems 4-19

4.6.4.1 Power Supply 4-19

4.6.4.2 NCO (Numerically Controlled Osc.) 4-19

4.6.4.3 10GHz Clock 4-19

Theory of Operation - List of Figures

Figure 4-1 WaveRunner 6000 Block Diagram 4-1
Figure 4-2 Device Manage 4-3
Figure 4-3 Acquisition Main Board Block Diagram 4-5
Figure 4-4 JTGA Device Chains 4-7
Figure 4-5 Serial Bus Device Chains 4-8
Figure 4-6 Trigger and Timebase Block Diagram 4-9
Figure 4-7 ADC and Memory Block Diagram 4-11
Figure 4-8 8b/10b Path 4-12
Figure 4-9 Front End Card Block Diagram 4-13
Figure 4-11 Front End Power Off State Block Diagram 4-15
Figure 4-10: HFE653 Block Diagram 4-15
Figure 4-12 50Ω /1 Path Block Diagram 4-16
Figure 4-13 50Ω /10 Path Block Diagram 4-16
Figure 4-14 1MΩ /1 Path DC Coupled Block Diagram 4-17
Figure 4-15 1MΩ /20 Path DC Coupled Block Diagram 4-17
Figure 4-16 1MΩ /20 Path DC Coupled Block Diagram 4-18
Figure 4-17 1MΩ /1 Path AC Coupled Block Diagram 4-18
Figure 4-18 Cal Clock Block Diagram 4-19

Table of Contents iii

iv Table of Contents

Performance Verification

5.1 Introduction 5-1

5.1.1 List of Tested Characteristics 5-1

5.1.2 Calibration Cycle 5-1

5.2 Test Equipment Required 5-2

5.2.1 Test Records 5-2

5.3 Turn On 5-2

5.4 Input Impedance 5-3

5.4.1 Channel Input Impedance 5-3

5.4.2 External Trigger Input Impedance 5-6

5.5 Leakage Current 5-7

5.5.1 Channel Leakage Current 5-7

5.5.2 External Trigger Leakage Current 5-10

5.6 Peak-Peak Noise Level 5-12

5.6.1 5 GS/s 50 Ohm 5-12

5.6.2. 10 GS/s Channel Mode (WR6100 & WR6200 only) 5-14

5.7 DC Accuracy 5-17

5.7.1 Positive 50Ω DC Accuracy 5-17

5.7.2 Negative 50Ω DC Accuracy 5-20

5.7.1 Positive 1MΩ DC Accuracy 5-21

5.7.2 Negative 1MΩ DC Accuracy 5-23

5.8 Offset Accuracy 5-25

5.8.1 Positive 50Ω Offset Accuracy 5-25

5.8.2 Negative 50Ω Offset Accuracy 5-27

5.8.3 Positive 1MΩ Offset Accuracy 5-28

5.8.4 Negative 1MΩ Offset Accuracy 5-30

5.9 Bandwidth 5-31

5.9.1 Description 5-31

5.10 Trigger Level 5-36

5.10.1 Description 5-36

5.10.2 Channel Trigger at 0 Division Threshold 5-36

5.10.3 Channel Trigger at +2.5 Divisions Threshold 5-38

5.10.4 Channel Trigger at −2.5 Divisions Threshold 5-39

5.11 Time Base Accuracy 5-41

5.11.1 Description 5-41

5.11.2 10 GHz Clock Verification Procedure 5-41

Maintenance

6. Maintenance 6-1

6.1 Introduction 6-1

6.1.1 Safety Precautions 6-1

6.1.2 Anti-static Precautions 6-1

6.2 Disassembly and Assembly Procedure 6-2

6.2.1 Disassembly Procedure 6-2
a. Removal of the Upper Cover Assembly 6-2
b. Opening of the Front Bezel 6-2
c. Removal of the Acquisition System Assembly 6-3
d. Removal of the PCI Board 6-4
e. Removal of the AGP-DVO Interface Board 6-4
f. Removal of the Processor Board 6-4
g. Removal of the Hard Disk Drive 6-5
h. Removal of the CD ROM Drive 6-5
i. Removal of the Power Supply 6-6
j. Removal of the Front Frame Assembly 6-6
k. Removal of the Front Panel Encoder Board 6-7
l. Removal of the USB Hub Board 6-7
m. Removal of the Display Inverter Board 6-8
n. Removal of the Display and Touchscreen 6-8
o. Replacing the Battery 6-9

Assembly Procedure 6-10

6.2.2 Installing Hardware Options 6-11

6.3 Software Update Procedure 6-11

6.3.1 Installing New X-Stream DSO Application Software 6-11

6.3.2 Software End User License Agreement 6-12

6.3.3 Installing Device Drivers 6-17

6.3.4 Upgrading Microcode 6-18

6.3.5 Verifying Microcode 6-19

6.3.6 Restoring the Operating System 6-19

6.3.7 Software Options 6-21

6.3.7.1 Changing Software Option Key 6-21
a. Scope ID, Scope Serial Number 6-21
b. Entering Option Key in the DSO 6-21

6.4 Board Exchange Procedure 6-22

6.4.1 Processor Board Exchange Procedure 6-22

6.4.2 Hard Drive Replacement Procedure 6-22

6.5 Equipment and Spare Parts Recommended for Service 6-23

6.5.1 Test Equipment Required 6-23

6.5.2 WaveRunner Spare Parts 6-23

6.6 Service Menu 6-24

6.6.1 Accessing Service Menu 6-24

6.6.2 Mainframe Tests 6-25

6.6.2.1 Front Panel Test 6-25

6.6.2.2 Critical File Backup 6-27

6.6.3 Acquisition System Tests 6-28

6.6.3.1 Critical Acquisition System Component Temperatures 6-28

Table of Contents v

vi Table of Contents

6.6.3.2 Automatic Calibrations 6-29

6.7 Calibration Procedures 6-30

6.7.1 System Power Supply Calibration Procedure 6-30

6.7.2 Touch Screen Calibration Procedure 6-34

6.8 Troubleshooting and Flow Charts 6-37

6.8.1 Introduction 6-37

6.8.2 Repair Level 6-37

6.8.3 Initial Troubleshooting 6-38

6.8.4 Power Supply Problem 6-40

6.8.5 No Display (Internal or External) 6-43

6.8.6 Internal Display Problem 6-44

6.8.7 Boot Up Sequence 6-45

6.8.8 Front Panel Controls Do not Operate 6-46

6.8.9 Touch Screen Problems 6-47

6.8.10 Timebase Problem 6-49

6.8.11 Remote Control Problem 6-50

6.8.12 CD-ROM Problem 6-51

6.8.13 Vertical Accuracy Problem 6-52

Replaceable Parts

7.1 900888-00: WR6020 2 GHz, 5GS/s 4 Ch Acq Board 2

7.2 900890-00: PCI Interface 9

7.3 900894-00: Processor Assy 10

7.4 900896-00: 4 Channel Encoder Board 10

7.5 901949-00: AGP/DVO Interface 11

7.6 901593-00: 4 channel front frame 12

7.7 901594-00: 2 channel front frame 13

7.8 901697-00: CD R/W Assy 14

7.9 901740-00: 2 Channel Encoder Board 14

7.10 901754-00: Chassis Mechanical 15

7.11 901761-00: Top Cover Assy 15

7.12 901763-00: WR 6051 500 MHz 5 GS/s 2 Ch Acq bd 16

7.13 901764-00: WR 6050 500 MHz 5 GS/s 4 Ch Acq bd 23

7.14 901765-00: WR 6100 1 GHz 5 GS/s 4 Ch Acq bd 30

7.15 901768-00: Accessories 37

7.16 901806-00: WR 6030 350 MHz 2.5 GS/s 4 Ch Acq bd 37

7.17 901851-00: USB Hub 44

7.18 901853-00: CD R Assy 45

Table of Contents vii

viii Table of Contents

Mechanical Parts

Figure 8-1: WaveRunner Top Cover Removal 8-1
Figure 8-2 Cable Interconnections 8-2
Figure 8-3 Cable Interconnections 8-3
Figure 8-4 Bezel Open & Acquisition Board Installation 8-4
Figure 8-5 Front Frame Installation 8-5
Figure 8-6 Power Supply Installation 8-6
Figure 8-7 Processor Assembly Installation 8-7
Figure 8-8 Processor Tray Assembly 8-8
Figure 8-9 CD ROM Drive Assembly Installation 8-9
Figure 8-10 CD ROM Assembly 8-10
Figure 8-11 Two and Four Channel Front Panel Assembly 8-11
Figure 8-12 Two and Four Channel Front Panel Encoders 8-12
Figure 8-13 Two Channel Keypad Installation 8-13
Figure 8-14 Four Channel Keypad Installation 8-14
Figure 8-15 TFT Installation 8-15
Figure 8-16 USB Hub and TFT Inverter Installation 8-16
Figure 8-17 Top Cover Assembly 8-17
Figure 8-18 Graphics Printer Cover Assembly 8-18
Figure 8-19 Dimensions 8-19
Figure 8-20 Packing 8-20

Schematics, Layouts, Parts List

Schematics, Layouts & Parts List 9-1
900890-00 PCI Schematic 9-3
900890-00 PCI Layout 9-4
900890-00 PCI Parts List 9-5
900896-00 4 channel front panel Schematic 9-9
900896-00 4 channel front panel Layout 9-10
900896-00 4 channel front panel Parts List 9-12
901504-00 CD ROM Adapter Schematic 9-15
901504-00 CD ROM Adapter Layout 9-16
901504-00 CD ROM Adapter Parts List 9-17
901558-00 Video Schematic 9-18
901558-00 Video Layout 9-20
901558-00 Video Parts List 9-21
901586-00 2 Ghz 4 channel Main Board Schematic 9-25
901586-00 2 Ghz 4 channel Main Board Layout 9-70
901586-00 2 Ghz 4 channel Main Board Parts List 9-92
901740-00 2 channel front panel Schematic 9-149
901740-00 2 channel front panel Layout 9-150
901740-00 2 channel front panel Parts List 9-152
901851-00 Hub Schematic 9-155
901851-00 Hub Layout 9-157
901851-00 Hub Parts List 9-158

Read this First 1-1

1. Warranty and Product Support

It is recommended that you thoroughly inspect the contents of the oscilloscope
packaging immediately upon receipt. Check all contents against the packing
list/invoice copy shipped with the instrument. Unless LeCroy is notified promptly of any
missing or damaged item, responsibility for its replacement cannot be accepted.
Contact your nearest LeCroy Customer Service Center or national distributor
immediately (see chapter 2 for cont act num ber s ).

1.1 Warranty

LeCroy warrants its oscilloscope products for normal use and operation within
specifications for a period of t hree years f rom the dat e of shipment. Calibrat ion each
year is recommended to ensure in-spec. performance. Spares, replacement parts and
repairs are warranted for 90 days. The instr ument's firmware has been thoroughly
tested and is thought to be f unctional, but is supplied without warranty of any kind
covering detailed performance. Products not made by LeCroy are covered solely by
the warranty of the original equipm ent manufacturer.

Under the LeCroy warranty, LeCroy will repair or, at its option, replace any product
returned within the warranty period to a LeCroy authorized service center. However,
this will be done only if the product is determined aft er examination by LeCroy to be
defective due to workmanship or materials, and not to have been caused by misuse,
neglect or accident, or by abnormal conditions or oper at ion.

1.2 Product Assistance

Help on installation, calibration, and the use of LeCroy equipment is available from the
LeCroy Customer Service Center in your country.

1.3 Maintenance Agreements

LeCroy provides a variety of customer support services under Maintenance Agreements.
Such agreements give extended warranty and allow clients to budget maintenance costs
after the initial three-year warranty has expired. Other services such as installation,
training, enhancements, on-site repairs and calibrations are available through special
supplemental support agreements.

Note:

Note:Note:

Note: This warranty replaces all other warranties, expressed or implied, including but

not limited to any implied warranty of merchantability, fitness, or adequacy for any
particular purpose or use. LeCroy shall not be liable for any special, incidental, or
consequential damages, whether in con tract or otherwise. The clien t will be responsible
for the transportation and insurance charges for the return of products to the service
facility. LeCroy will return all products under warranty with transport prepaid.

1-2 Read this First

1.4 Staying U p to Date

LeCroy is dedicated to offering state-of -the-art instruments, by continually refining and
improving the performance of LeCroy products. Because of the speed with which physical
modifications may be implemented, this manual and related documentation may not
agree in every detail with the products they describe. For example, there might be small
discrepancies in the values of components affecting pulse shape, timing or offset, and —
infrequently — minor logic changes. However, be assured the scope it self is in f ull order
and incorporates the most up-to-date circuitry. LeCroy frequently updates firmware and
software during servicing to improve scope performance, free of charge during
warranty. You will be kept informed of such changes, through new or revised manuals
and other publications.

Nevertheless, you should retain this, the original manual, for future reference
to your scope’s hardware specifications.

1.5 Service and Repair

Please return products requiring maintenance to the Customer Service Department in
your country or to an authorized service facility. The customer is responsible for
transportation charges to the factory, whereas all in-warranty products will be returned to
you with transportation prepaid. Outside the warranty period, you will need to provide us
with a purchase order number before we can repair your LeCroy product. You will be
billed for parts and labor related to the repair work, and for shipping.

1.6 How to return a Product

Contact the nearest LeCroy Service Center or office to find out where to return the product.
All returned products should be identified by model and serial number. You should
describe the defect or failure, and provide your name and contact number. In the case of a
product returned to the factory, a Return Authorization Number (RAN) should be used.

Return shipments should be made prepaid. We cannot accept COD (Cash On
Delivery) or Collect Return shipments. We recommend air-freighting.

It is important that the RAN be clear ly shown on the outside of t he shipping pack age
for prompt redirection to the appropriate LeCroy department.

1.7 What Comes with Your Scope

Refer to chapter 10 for a list of the items that ships standard with the different
configurations of t his oscilloscope.

Note:

Note:Note:

Note: Wherever possible, please use the original shipping carton. If a substitute

carton is used, it should be rigid and packed so that that the product is surrounded
by a minimum of four inches or 10 cm of shock-absorbent material.

General Information 2-1

2. General Information

2.1 Product Assistance

Help on installation, calibration, and the use of LeCroy equipment is available from your
local LeCroy office, or from LeCroy’s

• Customer Care Center, 700 Chestnut Ridge Road, Chestnut Ridge,

New York 10977–6499, U.S.A., tel. [phone]

• European Service Center,

4, Rue Moïse Marcinhes, Case postale 341, 1217 Meyrin 1,

Geneva Switzerland, tel. [phone].

• LeCroy Japan Corporation, Sasazuka Center Bldg – 6

th

floor, 1-6, 2-Chome,

Sasazuka, Shibuya-ku, Tokyo Japan 151-0073, tel. [phone]

2.2 Installation for Safe and Efficient Operation

Operating Environment

The oscilloscope will operate to its specifications if the environment is maintained within
the following parameters:

Temperature................5 to 4 0 °C (41 to 104 °F) rated.

Humidity.......................Maximum relative humidity 80 % RH (non-condensing) for

temperatures up to 31 °C decreasing linearly to 50 % relative humidity
at 40 °C

Altitude.........................2000 m (6560 ft)

The oscilloscope has been qualified to the following EN61010-1 category:

Installation (Ov e rv ol tage) C ate gory...............................II

Pollution De gree............................ 2

Safety Symbols

Where these symbols or indications appear on the front or rear panels, and in this

manual, they have the following meanings

:

2-2 General Information

..............................CAUTION: Refer to accompanying documents (for Safety-related

information). See elsewhere in this manual wherever t he sym bol is
present,as indicated in the Table of Contents.

..............................CAUTION: Risk of electric shock

...............................On (Supply)

❘ Off (Supply)

..............................Earth (Ground) Terminal

............................Protective Conductor Terminal

................................Earth (Ground) Terminal on BNC Connectors

WARNING....................Denotes a hazard. If a WARNING is indicated on th e instrument, do

not proceed until its conditions are understood and met.

WARNING

WARNINGWARNING

WARNING

Any use of this instrument in a
manner not specified by the
manufacturer may impair the
instrument’s safety protection.

The oscilloscope has not been designed to m ake direct measurement s on the human
body. Users who connect a LeCroy oscilloscope dir ectly to a person do so at their own
risk.

General Information 2-3

Power Requirements

The oscilloscope operates from a 115 V (90 to 132 V) or 220 V (180 to 250 V) AC

power source at 45 Hz to 66 Hz. No voltage selection is required, since the instrument

automatically adapts to the line voltage present.
The power supply of the oscilloscope is protected against short-circuit and

overload by means of a 10. 0 A/ 250 V AC, “T” rated fuses (size: 5 X 20 mm),
located above the mains plug . Disconnect the power cord before inspecting or
replacing a fuse. Open the fuse box by inserting a small screwdriver into the
slot and tur ning counter clockwise.

For continued fire protection at all line voltages, replace only with fuse of the
specified type and rating (T 10.0 A/250 V).

Maintain the ground line to avoid an electric shock.
None of the cur rent- carr ying conductors may exceed 250 V rms with respect to ground

potential. The oscilloscope is provided with a three-wire electrical cord containing a
three-terminal polarized plug for mains voltage and safety ground connection.

The plug's ground t erminal is connected directly to the f rame of the unit. For adequate
protection against electrical hazard, this plug must be inserted into a mating outlet
containing a safety ground contact.

Cleaning And Maintenance

Maintenance and repairs should be carried out exclusively by a LeCroy technician

Cleaning should be limited to the exterior of the instrument only, using a damp, soft

cloth. Do not use chemicals or abrasive elements. Under no circumstances should

moisture be allowed to penetrate the oscilloscope. To avoid electric shocks, disconnect

the instrument from the power supply before cleaning.

CAUTION

CAUTIONCAUTION

CAUTION

Risk of electrical shock:
No user serviceable parts
inside. Leave repair to
qualified personnel.

2-4 General Information

This page intentionally left blank

Specifications 3-1

3. Specifications

3.1 Vertical System

WaveRunner WaveRunner WaveRunner WaveRunner WaveRunner
6030(A) 6050(A) 6051(A) 6100(A) 6200(A)

Nominal Analog Bandwidth @
50 Ω (-3 dB)

350 MHz 500 MHz 500 MHz 1 GHz 2 GHz

Rise Time (Typical) 1 ns 750 ps 750 ps 400 ps 225 ps
Input Channels 4 4 2 4 4
Bandwidth Limiters 20 MHz; 200 MHz
Input Impedance 1MΩ//<20pF (10 MΩ // 9.5pF using PP007 probe)
Input Coupling 50 Ω: DC, 1MΩ: AC, DC, GND
Maximum Input Voltage, 50Ω 50 Ω: 5 Vrms, 1 MΩ: 250 V max (Peak AC: ≤ 10 kHz + DC)
Channel to Channel Isolation >40dB @ <100MHz (>30dB @ full bandwidth)
Vertical Resolution 8 bits; up to 11 with enhanced resolution (ERES)
Sensitivity 50 Ω: 2 mV/div - 1 V/div fully variable; 1 MΩ: 2 mV - 10 V/div fully variable
DC Gain Accuracy ±1.0% of full scale (typical); ±1.5% of full scale ≥ 10mV/div (warranted)
Offset Range 50 Ω: ± 400 mV @ 2-4.99 mV/div
± 1 V @ 5-100 mV/div
± 10 V @ 102 mV/div - 1V/div
1 MΩ: ± 500 mV @ 2-4.99 mV/div
± 1 V @ 5-100 mV/div
± 10 V @ 102 mV/div - 1V/div
± 100 V @ 1.02V/div - 10V/div

Offset Accuracy

±(1.5% + 0.5% of offset value + 1 mV) all fixed gain < 2V/div

±(1.5% + 1.0% of offset value + 1 mV) all variable and V/div settings ≥ 2V/div

Probing System BNC or Probus®

3.2 Horizontal System

Timebases

Internal timebase common to all input channels; an external clock may be

applied at the auxiliary input
Time/Division Range 20 ps/div - 10 s/div
Math & Zoom Traces 4 independent zoom and 4 math/zoom traces standard
Clock Accuracy ≤ 5 ppm @ 25° C (≤ 10ppm @ 5-40° C)
Time Interval Accuracy Clock Accuracy + Jitter Noise Floor
Sample Rate & Delay Time Accuracy Equal to Clock Accuracy
Trigger & Interpolator Jitter (RMS) ≤ 3 ps rms (typical)

Channel to Channel Deskew Range ±9 x T/div setting, 100ms max, each channel

External Sample Clock

DC to 1 GHz; 50 Ω (limited BW in 1MΩ), BNC input, limited to 2 Ch

operation (1 Ch in WR6051), (minimum rise time and amplitude

requirements apply at low frequencies)

Roll Mode User selectable, Available at lower time/div settings

3.3 Acquisition System

WaveRunner WaveRunner WaveRunner WaveRunner WaveRunner
6030(A) 6050(A) 6051(A) 6100(A) 6200(A)
Single-Shot Sample

Rate/Ch

2.5 GS/s 5 GS/s 5 GS/s 5 GS/s 5 GS/s

Interleaved Sample Rate
(2 Ch)

5 GS/s N/A N/A 10 GS/s 10 GS/s

Random Interleaved
Sampling (RIS)

200 GS/s

Trigger Rate 125,000 waveforms/second

Sequence Time Stamp
Resolution

1 ns

Minimum time Between
Sequential Segments

8 µs

Acquisition Memory

Max. Acquisition Points (4ch/2ch; 2ch/1ch in

6051)

Segments (Sequence

Mode)
Standard 1M / 2M 500
Option S (Std for A

models)

2M / 4M 500

Option M 4M / 8M 1,000
Option L 8M/16M 5,000
Option VL 12M/24M 10,000

3.4 Acquisition Processing

WaveRunner WaveRunner WaveRunner WaveRunner WaveRunner
6030(A) 6050(A) 6051(A) 6100(A) 6200(A)

Time Resolution (min,
Single-shot)

200 ps (5 GS/s) 100 ps (10 GS/s)

Averaging Summed and continuous averaging to 1 million sweeps
ERES From 8.5 to 11 bits vertical resolution
Envelope (Extrema) Envelope, floor, and roof for up to 1 million sweeps
Interpolation Linear, Sinx/x

3.5 Triggering System

Trigger Modes Normal, Auto, Single, Stop

Sources

Any input channel, External, Ext/10, or Line; slope and level unique to

each source

Trigger Coupling DC50 Ω, GND, DC1MΩ, AC1MΩ
Pre-trigger delay 0-100% of memory size (adjustable in 1% increments, or 100 ns)
Post-trigger delay The smaller of 0 to 10,000 divisions or 86,400 seconds
Hold-off 2 ns to 20 s or 1 to 99,999,999 events
Internal trigger level range ±5 div from center (typical)

3-2 Specifications

Specifications 3-3

WaveRunner WaveRunner WaveRunner WaveRunner WaveRunner
6030(A) 6050(A) 6051(A) 6100(A) 6200(A)
Trig Sensitivity

(Edge Trigger)

2 div@350 MHz 2 div@500 MHz 2 div@500 MHz 2 div@1 GHz 2 div@2 GHz

CH 1-4 + ext 1 div@250 MHz 1 div@350 MHz 1 div@350 MHz 1 div@750 MHz 1 div@1.8 GHz
Max Trig Freq

with SMART
Trigger®

350 MHz 500 MHz 500 MHz 750 MHz 750 MHz

CH 1-4 + ext @ ≥ 10mV @ ≥ 10mV @ ≥ 10mV @ ≥ 10mV @ ≥ 10mV
Trigger Level DC

Accuracy

±4% full scale ±2mV (typical)

External trigger range EXT/10 ±4V; EXT ±400mV

3.6 Basic Triggers

Edge/Slope/Line

Triggers when signal meets slope (positive or negative) and level

condition

3.7 SMART Triggers®

State or Edge Qualified

Triggers on any input source only if a defined state or edge occurred

on another input source .

Delay between sources is selectable by time or events.

Dropout

Triggers if signal drops out for longer than selected time between 2 ns

and 20 s.

Pattern

Logic combination (AND, NAND, OR, NOR) of 5 inputs (4 channels

and external trigger input - 2ch+EXT on 6051). Each source can be

high, low, or don't care.

The high and low level can be selected independently. Triggers at start

or end of the pattern.

3.8 SMART Triggers® with Exclusion Technology

Glitch & Pulse Width

Triggers on positive or negative glitches with widths selectable from 600 ps
to 20 s or on intermittent faults. (Subject to bandwidth limit of oscilloscope).

Signal or Pattern Width

Triggers on positive or negative pulse widths selectable from 600 ps to 20 s

or on intermittent faults. (Subject to bandwidth limit of oscilloscope).

Signal or Pattern Interval Triggers on intervals selectable between 2 ns and 20 s.

Timeout (State/Edge
Qualified)

Triggers on any source if a given state (or transition edge) has occurred on

another source.

Delay between sources is 10ns to 20 s, or 1 to 99,999,999 events.
Exclusion Triggering Trigger on intermittent faults by specifying the normal width or period.
Automatic Setup
Auto Setup Automatically sets timebase, trigger, and sensitivity to display a wide range

Vertical Find Scale

Automatically sets the vertical sensitivity and offset for the selected channels

to display

3.9 Probes

Probes

One PP007 per channel standard; Optional passive and active probes

available
Probe System; Probus Automatically detects and supports a variety of compatible probes
Scale Factors Automatically or manually selected, depending on probe used

3.10 Color Waveform Display

Type Color 8.4" flat-panel TFT-LCD with high resolution touch screen
Resolution SVGA; 800 x 600 pixels

Real Time Clock

Dates, hours, minutes, seconds displayed with waveform. Accurate to

±50ppm. SNTP support to synchronize to precision internet clocks.

Number of Traces

Display a maximum of 8 traces. Simultaneously display channel, zoom,

memory, and math traces.
Grid Styles Auto, Single, Dual, Quad, Octal, XY, Single + XY, Dual + XY
Waveform Styles Sample dots joined or dots only

3.11 Analog Persistence Display

Analog & Color-Graded
Persistence

Variable saturation levels; stores each trace's persistence data in

memory.

Persistence Selections Select analog, color, or three-dimensional.
Trace Selection Activate persistence on all or any combination of traces.
Persistence Aging Time Select from 500 ms to infinity.
Sweeps Displayed All accumulated, or all accumulated with last trace highlighted.

3.12 Zoom Expansion Traces

Zoom Expansion Traces Display up to 4 Math/Zoom traces;

3.13 CPU

Processor Intel Celeron® 2 GHz or better.
Processing Memory 256 MB on Std & M option; 512 MB with L option & VL option
Operating System

Microsoft Windows® 2000 Professional (XP Professional “A” model)

3.14 Internal Waveform Memory

M1, M2, M3, M4 Internal Waveform Memory (store full-length

waveform with 16 bits/data point) or store to any number of files limited

only by data storage media

3.15 Setup Storage

Front Panel and Instrument
Status

Store to the internal hard drive, over the network, or to a USB-

connected peripheral device.

3.16 Interface

Remote Control Via Windows Automation, or via LeCroy Remote Command Set
GPIB Port (Optional) Supports IEEE - 488.2
Ethernet Port 10/100Base-T Ethernet interface (RJ-45 connector)

USB Ports

5 USB ports (one on front of instrument) supports Windows-compatible

devices

External Monitor Port

Standard 15-pin D-Type SVGA-compatible DB-15; connect a second

monitor to use dual-monitor display mode.
Parallel Port Standard DB-25
Serial Port DB-9 RS232 port (not for remote oscilloscope control)

3-4 Specifications

Specifications 3-5

3.17 Auxiliary Input

Signal Types Selected from External Trigger or External Clock input on front panel
Coupling 50 Ω: DC, 1MΩ: AC, DC, GND
Maximum Input Voltage 50 Ω: 5Vrms, 1MΩ: 250 Vmax (Peak AC; ≤ 10 Khz + DC)

3.18 Auxiliary Output

Signal Types Trigger Enabled, Trigger Output, Pass/Fail, or Off
Output Level TTL, ~3.3 V
Connector Types BNC, located on rear panel

3.19 General

Auto Calibration

Ensures specified DC and timing accuracy is maintained for 1 year

minimum

Power

100-240 Vrms (±10%) at 50/60 Hz; 100-120 Vrms (±10%) at 400 Hz

Automatic AC Voltage Selection

Installation Category: 300V CAT II; Max. Power Consumption: 425

VA/425 W

3.20 Environmental

Temperature: Operating +5°C to 40°C
Temperature: Non-Operating -20°C to +60°C

Humidity: Operating

5% to 80% RH (non-condensing) up to 30°C, Upper limit derates

linearly to 50% RH (non-condensing) at 40°C

Humidity: Non-Operating 5% to 95% RH (non-condensing) as tested per MIL-PRF-28800F
Altitude: Operating 3,048m (10,000 ft) max at ≤ 25°C
Altitude: Non-Operating 12,190m (40,000 ft)

3.21 Physical Dimensions

Dimensions (HWD) 211mm x 355mm x 363mm (excluding feet) 8.3" x 13.8" x 14.3"
Net Weight 10 kg (22 lb), excluding printer
Shipping Weight less than 13.6 kg (30 lb)

3.22 Certifications

CE Approved, UL and cUL listed; Conforms to EN 61326-1, EN 61010-

1, UL 3111-1, and CSA C22.2 No. 1010.1

3.23 Warranty and Service

3-year warranty; calibration recommended annually. Optional service

programs include extended warranty, upgrades, calibration, and

customization services

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3-6 Specifications

Theory of Operation 4-1

4. Theory of Operation

4.1 System Block Diagram

Acquisition System

Power Supply

PC Motherboard

PCI

Card

Touch Screen

1 to 4

USB Hub

TFT

TFT

Inverter

Front Panel

Keypad /

Encoder

CD/
ROM
Drive

Hard
Disk

Drive

AGP -

DVI
Intf.

Power Switch

Optional

Graphics

Printer

USB

USB

USB

Video

LVDS

Figure 4-1 WaveRunner 6000 Block Diagram

4-2 Theory of Operation

4.2 Computer – The WaveRunner 6000 processor is a 1.7 GHz or 2.0 GHz Intel

Celeron motherboard or better. This assembly will change more often than other
assemblies due to the volatility of PC motherboards.

4.2.1 Operating System – The system uses Microsoft Windows 2000 as the

operating system. The operating system license can be found on the rear
panel of the instrument.

4.2.2 Memory – The standard memory configuration for a WaveRunner 6000 is

256MB, consisting of 1 piece of 32M x72 Bit PC2100 SDRAM DIMM. If option
L or VL is installed into the acquisition system then the processor RAM needs
to be 512MB.

4.2.3 Interfaces – The standard interfaces provided by the PC Motherboard are

SVGA, Audio, Ethernet, RS-232, Centronics and USB. .

4.2.4 Storage Devices – The system has an internal hard drive of at least 40 GB in

size. 5 GB is allocated for LeCroy use, the balance is in a user partition for the
saving of panel setups, waveform memory, hard copies, application programs,
user data, etc. The system also includes a CD-ROM drive. The CD-ROM drive
requires an adapter PCA to provide the interconnection to the ribbon cable
which makes connection to the motherboard.

4.2.5 CMOS Settings – The BIOS version is locked so that the System recovery CD

will only work on WaveRunner 6000 scope. Changes can still be made to BIOS
settings if needed, the lock is only relevant to the use of the System Recovery
CD.

4.3 PCI Card - The PCI card is the interface between the PCI bus on the processor card

and the acquisition system. It has the following interfaces:

– PCI card acts as a transaction repeater
– LVDS link between PCI card and Acquisition system
– PCI card also contains buzzer and unique chip ID.
– All digital functions (PCI and LVDS interface) contained in a Xilinx Spartan

IIe

– Two Beeps at powerup indicates link is good
– PCI card can also be detected with device manager

4.4 USB Hub – The USB Hub is a 1 to 4 USB 1.1 Interface. Only three USB are actually

created however the HUB interface chip is capable of making four USB ports. One
of the ports connects to the Touch Screen Controller, one port is available for an
internal graphics printer and the third port is for the front panel processor. The USB
Hub is recognized by Windows as a Generic USB Hub.

Figure 4-2 Device Manager

Theory of Operation 4-3

4-4 Theory of Operation

4.5 Display and Touch Screen

4.5.1 Color LCD Module – The display module is an NEC TFT (thin film transistor)

active matrix color liquid crystal display (LCD) module comprising amorphous
silicon TFT attached to each signal electrode, a driving circuit and a backlight.
The 22cm diagonal display area contains 800x600 pixels (SVGA) and can
display 262144 colors simultaneously.

4.5.2 Inverter – The inverter which supplies power to the TFT is supplied with +12V

from the DVI card DVO/DVI processor, it then converts this to 1000-2000V AC
to drive the TFT. The intensity control is kept at a constant 100%, dimming is
not possible.

4.5.3 Touch Screen – The touch screen is a 4 wire resistive touch screen. It must

be calibrated so that software can determine where a touch corresponds to a
position on the screen. This calibration is done at five points and can be
invoked through the Utilities menu.

4.6 Acquisition System –

PCI FPGACPU

PCI

Mainboard

Power

MAM

MAM

MAM

Front-End

Front-End

Front-End

Front-End

Front-End

ATC
HTB
MST

Controller FPGA

HAD

MAM

MAM

MAM

8b/10b

8b/10b

8b/10b

8b/10b

8b/10b

8b/10b

adc data

adc dat a

adc dat a

adc data

adc dat a

adc dat a

Ch 1

Ch 2

Ext

Ch 3

Ch 4

Cal Out

Ext Clk

Cal Gen

Delay

Cal

10GHz

Clk

HAD

LVDS

LVDS

SDRAM

SRAM & Flash

Micro Controller

JTAG, SPI,

misc

Analog Mux

Voltage Monitors

BW comp

BW comp

BW comp

BW comp

I2C, RS-232

To All

FEs

\

Figure 4-3 Acquisition Main Board Block Diagram

Theory of Operation 4-5

4-6 Theory of Operation

4.6.1 Main Card –

 Receives +12V, -12V, +3.3V, -3.3V, +5V, -5V, and “line sync” from Bulk AC power

supply.

 Other I/O:

– BNC Channel and External inputs
– Probus
– Trigger out/pass fail BNC (rear panel)
– USB (pass thru)
– Power Switch (pass thru)
– Arm and Trigger LED (to front panel)
– Calibrator Output (front panel probe hook)
– External Clock Input through External BNC

 Sub systems

– FE (50 Ohm, 1M Ohm)
– ADC and Acquisition Memory
– Timebase and Trigger
– 10GHz clock
– Controller FPGA
– uP Controller
– Power Supply
– NCO
– Probus

 Communication with devices

– SPI

– Slow Serial interface (2MHz). Used for communication with DACs,

HFEs and FE control, NCO.

– JTAG

– Serial Interface for communicating with HTB, ADCs, and MAMs.

– 8B/10B Gigabit Ethernet

– Acqusition memory (MAM) readout

– I2C

– Probus

– Parallel Interface

– uC to Controller FPGA

– GPIO

– 16 bit general purpose I/O

4.6.1.1 JTAG Chains

Control
FPGA

EN
B

MAM2

TDI TDO

MAM1

TDO TDI

MAD

TDO TDI

MAM3

TDI TDO

TCK TM STCK TM S

TRSTTRST

TCK TMS TCK TMS

TRST TRST

Channel 1-2

Channel 3-4

MAD

TDI TDO

MAM1

TDI TDO

TCK TMSTCK TMS

TRSTTRST

MAM3

TDO TDI

MAM2

TDO TDI

TCK TMS TCK TMS

TRST TR ST

ATC

(MTT)

TDO TDI

TCK TMS

EN
B

EN
B

JTAG

Control

EN
B

EN
B

EN
B

TDI

_TB

TMS
_TB

TCK
_TB

TDI

_CH

TMS
_CH

TCK
_CH

TDO_CH

TDO_TB

Dashed arrows show "NORES" c onnections when

Channels 3 & 4 are unpo pulated

TRST

_CH

8 bit IR

18bit DR

3 bit IR

21 bit DR

3 bit IR

21 bit DR

3 bit IR

21 bit DR

5(8) bit IR

18(15-145) bit DR

Figure 4-4 JTGA Device Chains

The software detects the devices on JTAG chain at startup

4.6.1.2 Serial chains

Control

FPGA

SPI Interface:

MFE Relay Reg

SCAN SCLK LD

Channel 1

Ext Trig

LD SCLK

8 bit16 bit

MFE Relay Reg

8 bit16 bit

Dual DAC

32 bit

LD SCLK

SCLK LD

NCO

40 bit

SCLK LD

Octal DAC

16 bit

SCLK LD

SCAN SCLK LD

MFE Relay Reg

SCAN SCLK LD LD SCLK

8 bit16 bit

Dual DAC

32 bit

SCLK LD

Channel 2

MFE Relay Reg

SCAN SCLK LD

Channel 3

LD SCLK

8 bit16 bit

Dual DAC

32 bit

SCLK LD

MFE Relay Reg

SCAN SCLK LD LD SCLK

8 bit16 bit

Dual DAC

32 bit

SCLK LD

Channel 4

Dashed arrows

show "NO RES"

connections when

Channels 3 & 4

are unpopulated

Figure 4-5 Serial Bus Device Chains

Theory of Operation 4-7

4-8 Theory of Operation

4.6.1.3 Controller FPGA

 Handles Communication to PCI card thru LVDS Link
 uC Interface
 GPIO Interface Controller
 JTAG Interface Controller
 SPI Interface Controller
 Time Stamp SDRAM Controller

4.6.1.4 MicroController

 Handles programming of Xilinx FPGAs on Acquisition Board (to Spartan IIe devices)
 Provides Scanning ADC for Monitoring:

• Chip temperatures of ADC, MAMs, FE, HTB

• System temperature

• Bulk power supplies

• Probus ring voltages

• Channel overload protection

 Probus Communication via I2C
 RS232 Interface for programming FLASH (internal use only)

4.6.1.5 Timebase & Trigger

 Comprised of ATC FPGA, HTB645, MST429, SDRAM
 Trigger Threshold
 Generates many system clocks (125MHZ, 500MHz from 10GHz)
 Handles Starting and Stopping of ADCs and Memory
 Counters for pre and post trigger
 TDC for waveform trigger position
 Fanout for External Clock
 Smart Trigger
 Sequence Mode (Time stamp stored in SDRAM)

MST429A

HTB645

External Controls

(DACs, Digital Level Translator)

To & From ATC-uC

Control BUS

Analog controls

(DACs)

Control Bits

Analog controls

(DACs)

Analog Trigger

lines from FE

External CLKs

Digital Trigger

lines from HTB

comparators

Valid

smart trigger

ADC 's

StartStop (1-4)

MACQ (1- 8)

MAMClk (1-4)

Ref

Clk

Clocks

Figure 4-6 Trigger and Timebase Block Diagram

4.6.1.5.1 HTB645 – Hybrid Timebase Trigger IC which performs all

standard triggers and control of individual acquisitions by the
ADC and Memory system.

4.6.1.5.1.1 Trigger Bandwidth – The trigger bandwidth of

the system using standard triggers is 5 GHz.

4.6.1.5.1.2 Trigger Signal I/O – There are five differential

trigger inputs, five differential trigger
comparator outputs to be used by an external
Smart Trigger IC, five analog trigger level
threshold control lines, five analog trigger
hysteresis control lines (they are all connected
together in this implementation), five trigger
selection lines and a validate trigger input from
the smart trigger.

Theory of Operation 4-9

4-10 Theory of Operation

4.6.1.5.1.3 TDC – The HTB645 has an internal TDC and

the ability to drive an external TDC. The TDC
resolution is ≈1.4ps.

4.6.1.5.1.4 Timebase – Provides control of starting and

stopping individual acquisition segments.

4.6.1.5.1.5 Miscellaneous clocks – provides 125MHz

clock for the NCO and the probe cal generator.

4.6.1.5.2 MST429A – Smart Trigger IC

4.6.1.5.2.1 Signal I/O – there are 6 differential ECL trigger

inputs, 6 differential ECL validate inputs and 2
single ended ECL inputs

4.6.1.5.2.2 Trigger Functions

• edge trigger

• timeout trigger

• pulse width trigger

• interval width trigger

• setup and hold time violation trigger

4.6.1.5.2.3 Main trigger delay or holdoff selection

• trigger delayed by time

• trigger holdoff by time

• trigger delayed by events

• trigger delayed by events and time

• trigger holdoff by events and time

• trigger delayed by time and events

4.6.1.5.2.4 Qualifier selection

• gate qualifier

• state qualifier

• edge qualifier

• number of events qualifier

• state with specified delay qualifier

• edge with restartable delay qualifier

• edge with not restartable delay qualifier

• pulse width qualifier

• interval width qualifier

4.6.1.5.2.5 Polarity – Polarity selection for trigger and

qualifier (positive, negative or either)

4.6.1.5.2.6 Analog Time Measure – Analog time measure

system used for specific trigger and qualifier
from 500ps to 10ns with 250ps resolution, and
from 10ns to 100ns with 500ps resolution

4.6.1.5.2.7 Digital Time Measure – Digital time measure

system used for specific trigger and qualifier

from 100ns to about 70s with 2ns resolution
(clock reference at 500 MHz)

4.6.1.5.2.8 Trigger Frequency – Main trigger frequency

up to 750 MHz, Qualifier frequency up to 500
MHz

4.6.2 ADC & Memory - The ADC function is performed by a two dual channel 5

GS/s, 8 Bit ADC hybrids (HAD639) with 24 Megabytes of DRAM. They have an
8b/10b data link to transfer data to an off board processor. For each pair of
channels (1&2 and 3&4) there is an 8 Bit Hybrid ADC and three 8 Megabyte
DRAM IC’s (MAM439). The ADC can be used either as a dual acquisition
channel, or it may be used as part or a two channel system to interleave data to

achieve a 10GS/s sampling rate

 Controlled via JTAG
 ADCs sample at 5GS/s for 4CH and 10GS/s when Interleaved to 2CH
 Digitized Data Decimated to achieve other sample rates
 Digitized data stored in MAMs and read out over 8b/10b bus
 Gain, Offset and Delay Dacs
 PRBS Generator

10 GHz

Clock Input

MAM

X
Y

RX

TX

MAM

X
Y

RX

TX

MAM

X
Y

RX

TX

2GHz CLK_Input

ADC

Output Port 1
Output Port 4

Output Port 2
Output Port 5

Output Port 3
Output Port 6

9 bit Digital Output Data

1.67GS/s

Differential LVDS Signal

From:
Control FPGA

TTL 8B/10B Data

EXT or

Unused

CH2 or CH4

CH1 or CH3

To:
Control FPGA (2 ch unit)
Ch 3 & 4 MAM (4 ch unit)

Figure 4-7 ADC and Memory Block Diagram

4.6.2.1 HAD639 – 10 GS/s, 8 Bit ADC

4.6.2.1.1 Signal I/O – The HAD639 has three differential analog inputs

and six output ports that each have nine differential output
signals and two differential quadrature clock outputs.

4.6.2.1.2 ADC’s – There are six 8 bit ADC’s in this device. Each ADC

operates at a clock speed of 1.667 GHz.

4.6.2.1.3 Calibration – There are several DAC’s built into the HAD639

to calibrate its ADC’s. For each ADC there are five internal
DAC’s, one for gain, one for offset, one for delay, one for
output delay and one for sample delay.

Theory of Operation 4-11

4-12 Theory of Operation

4.6.2.1.4 Control – The operating mode of the ADC is controlled

through JTAG, the control of each acquisition, start, stop etc
is controlled by the HTB.

4.6.2.2 MAM439 - 8 Megabytes DRAM

4.6.2.2.1 Signal I/O – The MAM439 has two, nine bit differential

inputs, each with two differential quadrature clock inputs.
Output is through an 8B/10B Ethernet transceiver.

4.6.2.2.2 Control – The state of MAM is controlled through JTAG and

through the Gigabit Ethernet link, the control of each
acquisition, clock, reset, stop etc is controlled by the HTB.

4.6.2.2.3 Decimation – When the sample rate is below 10GS/s, the

MAM439 ignores or decimates the correct amount of
samples so that the desired sample rate is achieved. The
ADC always digitizes at 10 GSs.

4.6.2.3 8b/10b Bus

ADC

MAM

MAM MAM

Control

FPGA

MTB

MST

ADC

MAM

MAMMAM

Buffer

Resistor

Jumper

8B 10B Bus

ATC

Figure 4-8 8b/10b Path

4.6.3 Front End – the front ends contain the attenuators, calibration signals and

offset generation, and signal conditioning of the input signal. It outputs are
differential analog signals used by the ADC’s and trigger circuitry.

+

-

HFE653

A

B

C

To trigger

20 db

RL1

RL4

RL2

RL8

÷10

÷10

AC / DC

Isolation Relay

Used during Cal

HF Cal Signal

50

50

50 Ohm Of fset

Var Gain

1 MOhm Offset

DAC

Relay

Control

1 MOhm Offset

50 Ohm Offset

Var Gain

6

Channel Input

Serial Bus

To ADC

To ADC

RL6

RL3

3 db

50 Ohm / Hi-Z

Therm al

Link

Therm al

Reference

Overload

- 5V

+ 5V

Hi-Z

buffer

buffer

RL1

÷10

boost

cap

U15

Q11

Q2 &

Q1

Figure 4-9 Front End Card Block Diagram

4.6.3.1 Input Coupling – There are two paths through the front end card.

One is the high bandwidth (350 MHz to 2 GHz) 50Ω path , the other is
the lower bandwidth (350 or 500 MHz) high impedance path which can
be either DC or AC coupled. The path is determined by relay RL7.

4.6.3.2 50Ω Path – The 50Ω path has a 3db attenuator right after the input to

limit the current into the front end from overload and then there are
clamp diodes to protect the HFE653. There is a thermal link from the
3db attenuator to a diode which is used to sense an overloaded input
by the heat dissipated by the 3db attenuator There is a switch able
20db attenuator (RL3) which is used for range settings of greater than
100mv/div. The input signal passes through the input to the HFE and is
terminated with a 50Ω resistor on the front end card.

Theory of Operation 4-13

4-14 Theory of Operation

4.6.3.3 1MΩ Path – The Hi-Z path has a switchable 20db attenuator (RL8)

which is used at input range settings of ≥ 102 mV/div. There are two
adjustable capacitors C4 & C25 in this attenuator circuit, C25 is used
to adjust the pulse shape when the 20db attenuator is switched in and
C4 is used to adjust the input capacitance of the channel so that it is
the same when the 20db attenuator is not switched in. After the /10
attenuator there is a second /10 attenuator which is additionally
switched in at input range settings of ≥1.02 V/div. C59 is used to adjust
the pulse shape when this attenuator is switched in. The signal then
passes through RL6 which is used to terminate the input to the Hi-Z
amplifier when 50Ω coupling is selected. Next the input signal splits
and follows two paths, DC and high frequency. In the block diagram
above, the upper path in the high impedance amplifier is the high
frequency stage and lower path is the DC stage. The DC stage is
preceded by RL4 which selects DC or AC coupling. R38 is used to
match the transfer functions of the high frequency and low frequency
path so that a square pulse shape can be obtained. The adjustable
cap C85 is used to provide additional drive for the high-Z buffer and
increase the bandwidth. The output of the buffer is then fed to the
HFE653 and this input is also terminated with a 50Ω resistor on the
front end card.

4.6.3.4 HFE653 – The HFE653 monolithic amplifier is the primary component

comprising the high bandwidth 50Ohm amplifier. The HFE provides the
following functions:

4.6.3.4.1 Gain control on inputs based on the sensitivity settings of
the DSO, so as to provide a 500mVpp differential signal at
the output of the amplifier.

4.6.3.4.2 Provide the capability to choose from three input channels.

4.6.3.4.3 Using a serial chain control to

 Select one of the three input channels

 Choose either BW limit filter path or the full BW path

 Turn ON and OFF any output amplifiers

 Provide a read back capability to read the latch states

and the device revision code.

Buffer

Var gain

Full BW

200 MHzBuffer

Buffer 20 MHz

3

2

1

D

out

Overload

Differential

outputs

HF cal input

Input from 50 Ohm path

Input from 1MOhm path

Var Gain

Digital Interface

D

in

2

3

DC Loop In

DC Loop Out

Figure 4-10: HFE653 Block Diagram

4.6.3.5 Amplifier Signal Path – The following diagrams illustrate the signal

path taken during the various different scope input coupling and input
attenuation modes:

4.6.3.5.1 Power Off State –

+

-

HFE653

A

B

C

To trigger

20 db

RL1

RL4

RL2

RL8

÷10

÷10

AC / DC

Isolation Relay

Used during Cal

HF Cal Signal

50

50

50 Ohm Offset

Var Gain

1 MOhm Offset

DAC

Relay

Control

1 MOhm Offset

50 Ohm Offset

Var Gain

6

Channel Input

Serial Bus

To ADC

To ADC

RL6

RL3

3 db

50 Ohm / Hi-Z

Thermal

Link

Thermal

Reference

Overload

- 5V

+ 5V

Hi-Z

buffer

buffer

RL1

÷10

boost

cap

U15

Q11

Q2 &

Q1

Figure 4-11 Front End Power Off State Block Diagram

Theory of Operation 4-15

4-16 Theory of Operation

4.6.3.5.2 50Ω /1 Path –

+

-

HFE653

A

B

C

To trigger

20 db

RL4

RL2

RL8

÷10

÷10

AC / DC

Isolation Relay

HF Cal Signal

50

50

50 Ohm Offset

Var Gain

1 MOhm Offset

DAC

Relay

Control

1 MOhm Offset

50 Ohm Offset

Var Gain

6

Channel Input

Serial Bus

To ADC

To ADC

RL6

RL3

3 db

50 Ohm / Hi-Z

Thermal

Link

Thermal

Reference

Overload

- 5V

+ 5V

Hi-Z

buffer

buffer

RL1

÷10

boost

cap

U15

Q11

Q2 &

Q1

Figure 4-12 50Ω /1 Path Block Diagram

4.6.3.5.3 50Ω /10 Path –

+

-

HFE653

A

B

C

To trigger

20 db

RL4

RL2

RL8

÷10

÷10

AC / DC

Isolation Relay

HF Cal Signal

50

50

50 Ohm Offset

Var Gain

1 MOhm Offset

DAC

Relay

Control

1 MOhm Offset

50 Ohm Offset

Var Gain

6

Channel Input

Serial Bus

To ADC

To ADC

RL6

RL3

3 db

50 Ohm / Hi-Z

Thermal

Link

Thermal

Reference

Overload

- 5V

+ 5V

Hi-Z

buffer

buffer

RL1

÷10

boost

cap

U15

Q11

Q2 &

Q1

Figure 4-13 50Ω /10 Path Block Diagram

4.6.3.5.4 1 MΩ /1 Path DC Coupled –

+

-

HFE653

A

B

C

To trigger

20 db

RL4

RL2

RL8

÷10

÷10

AC / DC

Isolation Relay

HF Cal Signal

50

50

50 Ohm Offset

Var Gain

1 MOhm Offset

DAC

Relay

Control

1 MOhm Offset

50 Ohm Offset

Var Gain

6

Channel Input

Serial Bus

To ADC

To ADC

RL6

RL3

3 db

50 Ohm / Hi-Z

Thermal

Link

Thermal

Reference

Overload

- 5V

+ 5V

Hi-Z

buffer

buffer

RL1

÷10

boost

cap

U15

Q11

Q2 &

Q1

Figure 4-14 1MΩ /1 Path DC Coupled Block Diagram

4.6.3.5.5 1 MΩ /10 Path DC Coupled –

+

-

HFE653

A

B

C

To trigger

20 db

RL4

RL2

RL8

÷10

AC / DC

Isolation Relay

HF Cal Signal

50

50

50 Ohm Offset

Var Gain

1 MOhm Offset

DAC

Relay

Control

1 MOhm Offset

50 Ohm Offset

Var Gain

6

Channel Input

Serial Bus

To ADC

To ADC

RL6

RL3

3 db

50 Ohm / Hi-Z

Thermal

Link

Thermal

Reference

Overload

- 5V

+ 5V

Hi-Z

buffer

buffer

RL1

÷10

boost

cap

U15

Q11

Q2 &

Q1

÷10

Figure 4-15 1MΩ /20 Path DC Coupled Block Diagram

Theory of Operation 4-17

4-18 Theory of Operation

4.6.3.5.6 1 MΩ /100 Path DC Coupled –

+

-

HFE653

A

B

C

To trigger

20 db

RL4

RL2

RL8

÷10

AC / DC

Isolation Relay

HF Cal Signal

50

50

50 Ohm Offset

Var Gain

1 MOhm Offset

DAC

Relay
Control

1 MOhm Offset

50 Ohm Offset

Var Gain

6

Channel Input

Serial Bus

To ADC

To ADC

RL6

RL3

3 db

50 Ohm / Hi-Z

Thermal

Link

Thermal

Reference

Overload

- 5V

+ 5V

Hi-Z

buffer

buffer

RL1

÷10

boost

cap

U15

Q11

Q2 &

Q1

÷10

Figure 4-16 1MΩ /20 Path DC Coupled Block Diagram

4.6.3.5.7 1 MΩ /1 Path AC Coupled –

+

-

HFE653

A

B

C

To trigger

20 db

RL4

RL2

RL8

÷10

÷10

AC / DC

Isolation Relay

HF Cal Signal

50

50

50 Ohm Offset

Var Gain

1 MOhm Offset

DAC

Relay

Control

1 MOhm Offset

50 Ohm Offset

Var Gain

6

Channel Input

Serial Bus

To ADC

To ADC

RL6

RL3

3 db

50 Ohm / Hi-Z

Thermal

Link

Thermal

Reference

Overload

- 5V

+ 5V

Hi-Z

buffer

buffer

RL1

÷10

boost

cap

U15

Q11

Q2 &

Q1

Figure 4-17 1MΩ /1 Path AC Coupled Block Diagram

4.6.4 Other Sub Systems

4.6.4.1 Power Supply

 Filtered and Linear regulated supplies

4.6.4.2 NCO (Numerically Controlled Osc.)

 Provides calibration signal to FEs for ADC calibration and External

clock calibration

125 MHz

3.3 to 5V

Translator

Control

3.3 to 5 V

Translator

From HTB645

Synchronous

with 10GHz

Digital control

From AAC

Digital Direct

Synthesizer

fout = Fin*(N/M)

Filter centered at 32MHz

Output

On / Off

RF CAL CH1

RF CAL CH2

RF CAL CH3

RF CAL CH4

RF CAL Ext

Figure 4-18 Cal Clock Block Diagram

4.6.4.3 10GHz Clock

 Generates 10GHz system clock from 10MHz oscillator. 10GHz piped

thru system using semi-flex (ADCs and HTB)

Theory of Operation 4-19

4-20 Theory of Operation

This page intentionally left blank

5. Performance Verification

5.1 Introduction

This chapter contains procedures suitable for determining if the WaveRunner 6000
Series,VBA6050, VBA6100 and LSA1225 Digital Storage Oscilloscope performs
correctly and as warranted. They check all the characteristics listed in subsection

5.1.1.
In the absence of the computer automated calibration system based on LeCroy

Calibration Software (Calsoft), this manual performance verification procedure can
be followed to establish a traceable calibration. It is the calibrating entities’
responsibility to ensure that all laboratory standards used to perform this procedure
are operating within their specifications and traceable to required standards if a
traceable calibration certificate is to be issued for the WaveRunner 6000 Digital
Storage Oscilloscope.

5.1.1 List of Tested Characteristics

This subsection lists the characteristics that are tested in terms of quantifiable
performance limits.

• Input Impedance

• Leakage Current

• Peak to Peak noise level

• Positive and Negative DC accuracy

• Positive and Negative Offset

• Bandwidth

• Trigger Accuracy

• Time Base Accuracy

5.1.2 Calibration Cycle

The WaveRunner 6000 Digital Storage Oscilloscope requires periodic verification of
performance. Under normal use (2,000 hours of use per year) and environmental
conditions, this instruments calibration cycle is 12 months.

WR6K Rev.D Performance Verification 5-1

5-2 Performance Verification WR6K Rev. D

5.2 Test Equipment Required

These procedures use external, traceable signal generators, DC precision power
supply and digital multi-meter, to directly check specifications.

Instrument Specifications Recommended
Signal Generator

Radio Frequency

Frequency : .5 MHz to 3 GHz
Frequency Accuracy : 1 PPM

HP8648B/C, Fluke 9500 or

equivalent
Signal Generator
Audio Frequency

Frequency : 0 to 5 kHz
Amplitude : 8 V peak to peak

HP33120A or equivalent
Voltage Generator

DC Power Supply

Range of 0 to 20 V, in
steps of no more than 15 mV

HP6633A or equivalent
Power Meter +

Sensor

Accuracy ±1 %

HP437B + 8482A or

equivalent
Digital Multimeter
Volt & Ohm

Voltmeter Accuracy : 0.1 %
Ohmmeter Accuracy : 0.1 %

Keithley 2000 or equivalent
Coaxial Cable, 5 ns

50Ω, BNC, length 100 cm,

Coaxial Cable, 5 ns

50Ω, SMA, length 100 cm,

2 Attenuators, 20 dB

50Ω, BNC, 1 % accuracy

T adapter

50Ω, BNC T adapter

Table 5-1 : Test Equipment

5.2.1 Test Records

The last pages of this document contain WaveRunner 6000 series test records in the
format tables. Keep them as masters and use a photocopy for each calibration.

5.3 Turn On

If you are not familiar with operating the WaveRunner 6K series, refer to the

operator's manual.
 Switch on the power using the power switch.
 Wait for about 20 minutes for the scope to reach a stable operating

temperature:

 Insert the CD with panel setups

5.4 Input Impedance

Specifications

DC 50Ω ±1.5 %
EXT DC 50Ω ±1.5 %
DC 1MΩ ±1.25%

The impedance values for 50Ω coupling are measured with a high precision digital
multimeter. The DMM is connected to the DSO in 4 wire configuration (input and sense),
allowing for accurate measurements. Check that the DMM used is measuring the 1 MΩ

inputs in at least a 3 MΩ range. If tested in a lower range some readings may not be
within specifications.

5.4.1 Channel Input Impedance

a. DC 50Ω

 Recall Input Impedance - 50 ohm x1.lss or configure the DSO :

Panel Setups : Recall FROM DEFAULT SETUP
Channels Trace ON Channel 1, Channel 2, Channel 3 & Channel 4
Input Coupling : DC 50Ω on all 4 Channels
Input gain : 20 mV/div. on all 4 Channels
Time base : 50 ηsec/div.
Trigger mode : Auto

WR6K Rev.D Performance Verification 5-3

5-4 Performance Verification WR6K Rev. D

 Set the DMM with Ohms and Ohms sense to provide a 4 wire measurement.
 Connect it to Channel 1.

 Measure the input impedance, reverse the meter leads and measure the input

impedance.

 Average these two numbers and record it in Table 2, and compare it to the limits.
 Repeat the above test for all input channels.
 Recall Input Impedance - 50 ohm x10.lss or Set Input gain to 200 mV/div. on all

4 Channels
 Repeat the test for all input channels.
 Record the measurements in Table 2, and compare the test results to the

limits in the test record.

b. DC 1MΩ

 Recall Input Impedance - 1 Mohm DC x1.lss or configure the DSO :

Panel Setups : Recall FROM DEFAULT SETUP
Channels Trace ON Channel 1, Channel 2, Channel 3 & Channel 4
Input Coupling : DC 1 MΩ on all 4 Channels
Input gain : 20 mV/div. on all 4 Channels
Time base : 50 ηsec/div.
Trigger mode : Auto

 Set the DMM with Ohms and Ohms sense to provide a 4 wire measurement.
 Connect it to Channel 1.

 Measure the input impedance, reverse the meter leads and measure the input

impedance.

 Average these two numbers and record it in Table 2, and compare it to the limits.
 Repeat the above test for all input channels.
 Recall Input Impedance - 1 Mohm DC x10.lss or Set Input gain to 200 mV/div.

on all 4 Channels
 Repeat the test for all input channels.
 Record the measurements in Table 2, and compare the test results to the

limits in the test record.
 Recall Input Impedance - 1 Mohm DC x100.lsss or Set Input gain to 2 V/div. on

all 4 Channels
 Repeat the test for all input channels.
 Record the measurements in Table 2, and compare the test results to the

limits in the test record.

WR6K Rev.D Performance Verification 5-5

5-6 Performance Verification WR6K Rev. D

5.4.2 External Trigger Input Impedance

a. DC 50Ω

 Recall Input Impedance - 50 ohm ext x1.lss or configure the DSO :
Select Setup trigger
Trigger on : EXT
Impedance : DC 50Ω

 Connect the DMM to External, and measure the input impedance, reverse the

meter leads and measure the input impedance.

 Average these two numbers and record the input impedance in Table 2, and

compare the result to the limit in the test record.

b. Ext DC 1MΩ Input Impedance

 Recall Input Impedance - 1 Mohm DC Ext x1.lss or configure the DSO :
Select Setup trigger

Trigger on : EXT
Impedance : DC 1MΩ

 Connect the DMM to External, and measure the input impedance, reverse the

meter leads and measure the input impedance.

 Average these two numbers and record the input impedance in Table 2, and

compare the result to the limit in the test record.

5.5 Leakage Current

Specifications

DC 50Ω, EXT DC 50Ω : ±2 mV

The leakage current is tested by measuring the voltage across the input channel.

5.5.1 Channel Leakage Current

a. DC 50Ω

 Recall Leakage - 50 ohm x1.lss or configure the DSO :

Panel Setups : Recall FROM DEFAULT SETUP
Channels Trace ON Channel 1, Channel 2, Channel 3 & Channel 4
Input Coupling : DC 50Ω on all 4 Channels

Input gain : 20 mV/div. on all 4 Channels
Trigger mode : Auto

Time base : 50 nsec/div.

WR6K Rev.D Performance Verification 5-7

5-8 Performance Verification WR6K Rev. D

 Set the DMM to measure Volts, and connect it to Channel 1.

 Measure the voltage and enter it in Table 3. Compare it to the limits.
 Repeat the test for all input channels.
 Recall Leakage - 50 ohm x10.lss or set Input gain to 200 mV/div. on all 4

Channels

 Repeat the test for all input channels. Record the measurements in Table 3,
and compare the results to the limits in the test record.

b. DC 1MΩ

 Recall Leakage - 1 Mohm x1.lss or configure the DSO :

Panel Setups : Recall FROM DEFAULT SETUP

Channels Trace ON Channel 1, Channel 2, Channel 3 & Channel 4
Input Coupling :

DC 1MΩ on all 4 Channels

Input gain : 20 mV/div. on all 4 Channels
Trigger mode : Auto
Time base : 50 nsec/div.

 Set the DMM to measure Volts, and connect it to Channel 1.

 Measure the voltage and enter it in Table 3. Compare it to the limits.

 Repeat the test for all input channels.
 Recall Leakage - 1 Mohm x10.lss or set Input gain to 200 mV/div. on all 4

Channels

 Repeat the test for all input channels. Record the measurements in Table 3,
and compare the results to the limits in the test record.

 Recall Leakage - 1 Mohm x100.lss or set Input gain to 2 V/div. on all 4

Channels

 Repeat the test for all input channels. Record the measurements in Table 3,
and compare the results to the limits in the test record.

WR6K Rev.D Performance Verification 5-9

5-10 Performance Verification WR6K Rev. D

5.5.2 External Trigger Leakage Current

a. DC 50Ω

 Recall Leakage - 50 ohm ext x1.lss or configure the DSO as shown in 5.5.1 and

make the following changes:

Select Setup trigger
Set Trigger on : EXT

Impedance : DC 50Ω

 Connect the DMM to External.

 Measure the voltage and enter it in Table 3. Compare it to the limits.

b. DC 1MΩ

 Recall Leakage - 1 Mohm ext x1.lss or configure the DSO as shown in 5.5.1
and make the following changes:

Select Setup trigger
Set Trigger on : EXT

Impedance : DC 1MΩ

 Connect the DMM to External.

 Measure the voltage and enter it in Table 3. Compare it to the limits.

WR6K Rev.D Performance Verification 5-11

5-12 Performance Verification WR6K Rev. D

5.6 Peak-Peak Noise Level

Description

Noise tests with open inputs are executed on all channels with 0 mV offset, at a gain

setting of 10 mV/div. The scope parameters functions are used to measure the Peak to

Peak amplitude of the noise.

Specifications

7.5 mV Peak-Peak at 10 mV/div.

5.6.1 5 GS/s 50 Ohm

With no signal connected to the inputs

 Recall Noise - 10mv.lss or configure the DSO :
Panel Setups : Recall FROM DEFAULT SETUP

Channels Trace ON Channel 1, Channel 2, Channel 3 & Channel 4
Input Coupling : DC 50Ω on all 4 Channels
Input gain : 10 mV/div. on all 4 Channels
Input offset : 0.0 mV on all 4 Channels
Trigger setup : Edge
Trigger on : C1
Trigger Mode : Auto

Time base : 1 µsec/div.
Channel use : Automatic
Press : Measure, Measure Setup,
Statistics : On
Add parameters
P1 : Measure pkpk of Ch1
P2 : Measure pkpk of Ch2
P3 : Measure pkpk of Ch3
P4 : Measure pkpk of Ch4

 Press Clear Sweeps.
 Measure for at least 50 sweeps, and then press Stop to halt the acquisition.
 Record the four max pk-pk parameter values in Table 4, and compare the test

results to the limits in the test record.
 Repeat the test for Time base : 1 msec/div.
 Record the measurements (high pk-pk of 1,2,3,4) in Table 4, and compare the

results to the limits in the test record.

WR6K Rev.D Performance Verification 5-13

5-14 Performance Verification WR6K Rev. D

5.6.2. 10 GS/s Channel Mode (WR6100 & WR6200 only)

a) Channel 1 & Channel 3
 Recall Noise 10GS Ch1 & Ch3.lss or configure the DSO as shown in 5.6.1 and

make the following changes :
Input Coupling : DC 50Ω on all 4 Channels
Input gain : 10 mV/div. On all 4 Channels
Channels Trace ON Channel 1, Channel 3

Channels Trace OFF Channel 2, Channel 4
Time base : 500 ηsec/div.

Select Time base Setup
Channel use : Automatic
Press : Measure

Change parameters

P1 : Measure pkpk of Ch1
P2 : Turn Off
P3 : Measure pkpk of Ch3
P4 : Turn Off

 Check that the Sampling rate is 10 GS/s
 Press Clear Sweeps.
 Measure for at least 50 sweeps, then press Stop to halt the acquisition.
 Record the two max pkpk of Ch1 & Ch3 in Table 4, and compare the test results

to the limits in the test record.

b) Channel 2 & Channel 4

 Recall Noise 10GS Ch2 & Ch4.lss or configure the DSO as shown in 5.6.1.a.

and make the following changes :
Input Coupling : DC 50Ω on all 4 Channels
Input gain : 10 mV/div. On all 4 Channels
Channels Trace ON Channel 2, Channel 4

Channels Trace OFF Channel 1, Channel 3
Time base : 500 ηsec/div.

Select Time base Setup
Channel use : Automatic
Press : Measure

Change parameters

P1 : Turn Off
P2 : Measure pkpk of Ch4
P3 : Turn Off
P4 : Measure pkpk of Ch4

WR6K Rev.D Performance Verification 5-15

5-16 Performance Verification WR6K Rev. D

 Check that the Sampling rate is 10 GS/s
 Press Clear Sweeps.
 Measure for at least 50 sweeps, then press Stop to halt the acquisition.
 Record the two max pkpk of Ch2 & Ch4 in Table 4, and compare the test results

to the limits in the test record.

5.7 DC Accuracy

Specification

≤ ±2 % of full scale + 2mv, with 0 mV offset.

Note: This limit applies to a single point measurement (absolute DC accuracy, as
measured by this procedure), for measurements of gain accuracy (difference of two
points) the specification is: ≤ ±1.0 % of full scale

Description

This test measures the DC Accuracy within the gain range specified.
It requires a DC source with a voltage range of 0 V to 6 V adjustable in steps of no
more than 15 mV, and a calibrated DMM that can measure voltage to 0.1 %.

Measurements are made using voltage values applied by the external voltage

reference source, measured by the DMM, and in the oscilloscope using the

parameters Mean. For each known input voltage, the deviation is checked against

the tolerance.

5.7.1 Positive 50Ω DC Accuracy
Procedure

 Recall DC accuracy - 50 ohm 2mv.lss or configure the DSO :
Panel Setups : Recall FROM DEFAULT SETUP

Channels Trace ON Channel 1, Channel 2, Channel 3 & Channel 4
Input Coupling : DC 50Ω on all 4 Channels
Input offset : 0.0 mV on all 4 Channels
Input gain : from 2mV/div to 1 V/div. (see Table 5) on all 4 Ch

C1 Averaging : 5 sweeps
C2 Averaging : 5 sweeps
C3 Averaging : 5 sweeps
C4 Averaging : 5 sweeps

Trigger setup : Edge
Trigger on : Line
Mode : Auto
Time base : 1 µsec/div.
Channel use : 4

Change parameters
P1 : Measure mean of C1
P2 : Measure mean of C2
P3 : Measure mean of C3
P4 : Measure mean of C4

WR6K Rev.D Performance Verification 5-17

5-18 Performance Verification WR6K Rev. D

 For the low sensitivities: 2 mV through 20 mV/div., connect the test

equipment as shown in Figure 5-1.

DC Power SupplyDMM

20DB20

DB

Figure 5-1 : DC 50Ω Accuracy Equipment Setup for 2 mV - 20 mV/div

 For the sensitivities: 50 mV and 100 mV/div, connect the test equipment as
shown in Figure 5-2.

DC Power SupplyDMM

20

DB

Figure 5-2 : DC 50Ω Accuracy Equipment Setup for 50 mV and 100 mV/div

 For the range 200 mV, 500 mV and 1 V/div no attenuator is required, connect the

test equipment as shown in Figure 5-3.

DC Power SupplyDMM

Figure 5-3 : DC 50Ω Accuracy Equipment Setup for 200 mV, 500 mV and 1 V/div.

 For each DSO Volts/div, set the output of the external DC voltage reference

source as shown in Table 6, column PS output.

1) Connect the DMM and record the voltage reading in Table 5, column DMM.

2) Disconnect the DMM from the BNC T connector.

3) Press Clear Sweeps

4) After 100 sweeps, read off the DSO mean parameter, and record the
measurement in Table 5, column Mean.

 For each DC voltage applied to the DSO input, repeat parts 1), 2), 3) and 4).
 Calculate the Difference ( ∆ ) by subtracting the DMM voltage reading from the

DSO mean voltage reading. Record the test result in Table 5, and
compare the Difference ( ∆ ) to the corresponding limit in the test record.

 Repeat step 5.7.1.a. for the other channels, substituting channel controls and

Input connector.

WR6K Rev.D Performance Verification 5-19

5-20 Performance Verification WR6K Rev. D

5.7.2 Negative 50Ω DC Accuracy

 Recall DC accuracy - 50 ohm 2mv.lss or configure the DSO as shown in 5.7.1.
 Connect the test equipment as shown in either Figure 5-1 or 5-2 or 5-3.

 For each DSO Volts/div, set the output of the external DC voltage reference
source as shown in Table 6, column PS output. (if a banana-BNC adapter is

being used it can simply be turned to get the opposite polarity)

1) Connect the DMM and record the voltage reading in Table 6, column DMM.

2) Disconnect the DMM from the BNC T connector.

3) Press Clear Sweeps

4) After 100 sweeps, read off the DSO mean parameter, and record the
measurement in Table 6, column Mean.

 For each DC voltage applied to the DSO input, repeat parts 1), 2), 3) and 4).
 Calculate the Difference ( ∆ ) by subtracting the DMM voltage reading from the

DSO mean voltage reading. Record the test result in Table 6, and
compare the Difference ( ∆ ) to the corresponding limit in the test record.

 Repeat step 5.7.2. for the other channels, substituting channel controls and
input connector.

5.7.1 Positive 1MΩ DC Accuracy
Procedure

 Recall DC accuracy - 1 Mohm 2mv.lss or configure the DSO :
Panel Setups : Recall FROM DEFAULT SETUP

Channels Trace ON Channel 1, Channel 2, Channel 3 & Channel 4
Input Coupling : DC

1MΩ on all 4 Channels

Input offset : 0.0 mV on all 4 Channels
Input gain : from 2mV/div to 2 V/div. (see Table 6) on all 4 Ch

C1 Averaging : 5 sweeps
C2 Averaging : 5 sweeps
C3 Averaging : 5 sweeps
C4 Averaging : 5 sweeps

Trigger setup : Edge
Trigger on : Line
Mode : Auto
Time base : 1 µsec/div.
Channel use : 4
Change parameters

P1 : Measure mean of C1
P2 : Measure mean of C2
P3 : Measure mean of C3
P4 : Measure mean of C4

 For the low sensitivities: 2 mV through 20 mV/div., connect the test
equipment as shown in Figure 5-4.

DC Power SupplyDMM

20DB20

DB

50

Figure 5-4 : DC 1MΩ Accuracy Equipment Setup for 2 mV - 20 mV/div

 For the sensitivities: 50 mV and 100 mV/div, connect the test equipment as
shown in Figure 5-5.

WR6K Rev.D Performance Verification 5-21

5-22 Performance Verification WR6K Rev. D

DC Power SupplyDMM

20

DB

50

Figure 5-5 : DC 1MΩ Accuracy Equipment Setup for 50 mV and 100 mV/div

 For the range 200 mV, - 2 V/div no attenuator is required, connect the test

equipment as shown in Figure 5-6.

DC Power SupplyDMM

50

Figure 5-6 : DC 1MΩ Accuracy Equipment Setup for 200 mV, 500 mV and 1 V/div.

 For each DSO Volts/div, set the output of the external DC voltage reference
source as shown in Table 7, column PS output.

1) Connect the DMM and record the voltage reading in Table 7, column DMM.

2) Disconnect the DMM from the BNC T connector.

3) Press Clear Sweeps

4) After 100 sweeps, read off the DSO mean parameter, and record the
measurement in Table 7, column Mean.

 For each DC voltage applied to the DSO input, repeat parts 1), 2), 3) and 4).
 Calculate the Difference ( ∆ ) by subtracting the DMM voltage reading from the

DSO mean voltage reading. Record the test result in Table 7, and
compare the Difference ( ∆ ) to the corresponding limit in the test record.

 Repeat step 5.7.1.a. for the other channels, substituting channel controls and

Input connector.

5.7.2 Negative 1MΩ DC Accuracy

 Recall DC accuracy - 1 Mohm 2mv.lss or configure the DSO as shown in 5.7.1.
 Connect the test equipment as shown in either Figure 5-4 or 5-5 or 5-6.

 For each DSO Volts/div, set the output of the external DC voltage reference
source as shown in Table 8, column PS output. (if a banana-BNC adapter is

being used it can simply be turned to get the opposite polarity)

WR6K Rev.D Performance Verification 5-23

5-24 Performance Verification WR6K Rev. D

1) Connect the DMM and record the voltage reading in Table 8, column DMM.

2) Disconnect the DMM from the BNC T connector.

3) Press Clear Sweeps

4) After 100 sweeps, read off the DSO mean parameter, and record the
measurement in Table 8, column Mean.

 For each DC voltage applied to the DSO input, repeat parts 1), 2), 3) and 4).
 Calculate the Difference ( ∆ ) by subtracting the DMM voltage reading from the

DSO mean voltage reading. Record the test result in Table 8, and
compare the Difference ( ∆ ) to the corresponding limit in the test record.

 Repeat step 5.7.2. for the other channels, substituting channel controls and
input connector.

5.8 Offset Accuracy

Specifications
±(1.5% of offset + .5% of FS + 1mv)

Description

The offset test is done at 50 mV/div, with a signal of ±0.750 Volt cancelled by an
offset of the opposite polarity.

5.8.1 Positive 50Ω Offset Accuracy

Procedure

 Recall Offset - 50 ohm Positive.lss or configure the DSO:
Panel Setups : Recall FROM DEFAULT SETUP

Channels Trace ON Channel 1, Channel 2, Channel 3 & Channel 4
Input Coupling : DC 50Ω on all 4 Channels
Input gain : 50mV/div on all 4 Channels
Input offset : +0.750 Volt on all 4 Channels

C1 Averaging : 5 sweeps
C2 Averaging : 5 sweeps
C3 Averaging : 5 sweeps
C4 Averaging : 5 sweeps

Trigger setup : Edge
Trigger on : Line
Mode : Auto
Time base : 50 ηsec/div.
Channel use : 4
Statistics : on
Change parameters
P1 : Measure mean of C1
P2 : Measure mean of C2
P3 : Measure mean of C3
P4 : Measure mean of C4

 Connect the test equipment as shown in Figure 5-7.

DC Power SupplyDMM

20

DB

Figure 5-7 : Offset Accuracy Equipment Setup

 Set the output of the external DC voltage reference source until the DVM

measures −0.750 Volt.

WR6K Rev.D Performance Verification 5-25

5-26 Performance Verification WR6K Rev. D

1) Verify that the displayed trace A : Average (1) is on the screen, near the center

horizontal graticule line. If the trace is not visible, modify the DC voltage

reference source output until the trace is within ± 2 divisions of center.

2) Connect the DMM and record the voltage reading in Table 9, column DMM.

3) Disconnect the DMM from the BNC T connector.

4) Press Clear Sweeps

5) After 100 sweeps, Read off the DSO Mean parameter voltage, and record the

measurement in Table 9, column Mean.

 Repeat the test for the other channels, substituting channel controls and input
connector. Record the measurements in Table 9.

 Calculate the Difference ( ∆ ) by subtracting the DMM voltage reading from the

DSO mean voltage reading.

 Record the test result in Table 9, and compare the Difference ( ∆ ) to the

corresponding limit in the test record.

5.8.2 Negative 50Ω Offset Accuracy

Procedure

 Recall Offset - 50 ohm Negative.lss or configure the DSO as shown in 5.8.1

and for each channel make the following change :

Input offset : −0.750 Volt on all 4 Channels

 Connect the test equipment as shown in Figure 5-7.
 Set the output of the external DC voltage reference source until the DMM

measures +0.750 Volt.

1) Verify that the displayed trace A : Average (1) is on the screen, near the center

horizontal graticule line. If the trace is not visible, modify the DC voltage

reference source output until the trace is within ± 2 divisions of center.

2) Connect the DMM and record the voltage reading in Table 10, column DMM.

3) Disconnect the DMM from the BNC T connector.

4) Press Clear Sweeps

5) After 100 sweeps, Read off the DSO Mean parameter voltage, and record the

measurement in Table 10, column Mean.

 Repeat the test for the other channels, substituting channel controls and input
connector. Record the measurements in Table 10.

 Calculate the Difference ( ∆ ) by subtracting the DMM voltage reading from the
DSO mean voltage reading. Record the test result in Table 10, and
compare the Difference ( ∆ ) to the corresponding limit in the test record.

WR6K Rev.D Performance Verification 5-27

5-28 Performance Verification WR6K Rev. D

5.8.3 Positive 1MΩ Offset Accuracy

Procedure

 Recall Offset - 1 Mohm Positive.lss or configure the DSO:
Panel Setups : Recall FROM DEFAULT SETUP

Channels Trace ON Channel 1, Channel 2, Channel 3 & Channel 4
Input Coupling : DC 1MΩ on all 4 Channels
Input gain : 50mV/div on all 4 Channels
Input offset : +0.750 Volt on all 4 Channels

C1 Averaging : 5 sweeps
C2 Averaging : 5 sweeps
C3 Averaging : 5 sweeps
C4 Averaging : 5 sweeps

Trigger setup : Edge
Trigger on : Line
Mode : Auto
Time base : 50 ηsec/div.
Channel use : 4
Statistics : on

Change parameters
P1 : Measure mean of C1
P2 : Measure mean of C2
P3 : Measure mean of C3
P4 : Measure mean of C4

 Connect the test equipment as shown in Figure 5-7.
 Set the output of the external DC voltage reference source until the DVM

measures −0.750 Volt.

1) Verify that the displayed trace A : Average (1) is on the screen, near the center
horizontal graticule line. If the trace is not visible, modify the DC voltage

reference source output until the trace is within ± 2 divisions of center.

2) Connect the DMM and record the voltage reading in Table 11, column DMM.

3) Disconnect the DMM from the BNC T connector.

4) Press Clear Sweeps

5) After 100 sweeps, Read off the DSO Mean parameter voltage, and record the
measurement in Table 11, column Mean.

 Repeat the test for the other channels, substituting channel controls and input
connector. Record the measurements in Table 11.

 Calculate the Difference ( ∆ ) by subtracting the DMM voltage reading from the

DSO mean voltage reading.

 Record the test result in Table 11, and compare the Difference ( ∆ ) to the

corresponding limit in the test record.

WR6K Rev.D Performance Verification 5-29

5-30 Performance Verification WR6K Rev. D

5.8.4 Negative 1MΩ Offset Accuracy

Procedure

 Recall Offset - 1 Mohm Negative.lss or configure the DSO as shown in 5.8.1

and for each channel make the following change :

Input offset : −0.750 Volt on all 4 Channels

 Connect the test equipment as shown in Figure 5-7.
 Set the output of the external DC voltage reference source until the DMM

measures +0.750 Volt.

1) Verify that the displayed trace A : Average (1) is on the screen, near the center
horizontal graticule line. If the trace is not visible, modify the DC voltage

reference source output until the trace is within ± 2 divisions of center.

2) Connect the DMM and record the voltage reading in Table 12, column DMM.

3) Disconnect the DMM from the BNC T connector.

4) Press Clear Sweeps

5) After 100 sweeps, Read off the DSO Mean parameter voltage, and record the
measurement in Table 12, column Mean.

 Repeat the test for the other channels, substituting channel controls and input
connector. Record the measurements in Table 12.

 Calculate the Difference ( ∆ ) by subtracting the DMM voltage reading from the
DSO mean voltage reading. Record the test result in Table 12, and
compare the Difference ( ∆ ) to the corresponding limit in the test record.

5.9 Bandwidth

5.9.1 Description

The purpose of this test is to ensure that the entire system has a bandwidth of at
least 2 GHz for a WaveRunner 6200, 1 GHz for a WaveRunner 6100, 500 MHz for a
WaveRunner 6050 or 6051 and 350 MHz for a WaveRunner 6030. An external
source is used as the reference to provide a signal where amplitude and frequency
are well controlled. The HP8648B may be used when testing the lower bandwidth
scopes.
The amplitude of the generator and cable as a function of frequency and power is
calibrated using an HP8482A sensor on an HP437B power meter or equivalent.
Note: If a leveled generator is used then the corrections needed by using the power
meter may not be necessary.

Specifications

WaveRunner 6200, LSA1225

50Ω : DC to at least 2 GHz (-3 dB)

WaveRunner 6100, VBA6100

50Ω : DC to at least 1 GHz (-3 dB)

WaveRunner 6050, 6051 or VBA6050

50Ω : DC to at least 500 MHz (-3 dB)

WaveRunner 6030

50Ω : DC to at least 350 MHz (-3 dB)

WR6K Rev.D Performance Verification 5-31

5-32 Performance Verification WR6K Rev. D

 Recall Bandwidth - CH1 10mv.lss or configure the DSO:

Panel Setups : Recall FROM DEFAULT SETUP
Channels Trace ON Channel 1, Channel 2, Channel 3 & Channel 4
Input Coupling : DC 50Ω on all 4 Channels
Input gain : 10 mV/div on all 4 Channels
Input offset : 0 mV on all 4 Channels
Trigger setup : Edge
Trigger on : Line
Slope line : Pos
Mode : Auto
Time base : 50 ηsec/div.
Channel use : Automatic
Change parameters
P1 : Sdev of C1
P2 : Freq of C1

 Connect the HP8482A power sensor to the power meter.

 Zero and calibrate the HP8482A power sensor using the power meter Power
Ref output.

 Connect a BNC adapter to the HP8482A power sensor.

 Connect a 50Ω SMA cable to the RF output of the HP8648B/C

generator and then through the necessary adapters to the power sensor. It is
very important that the same cable/generator be used throughout this BW
procedure and that the SMA connectors are torqued at all their mating locations.

Power Sensor

Power Meter

Power Ref

Output

Sensor Input

Sine Wave

Generator

Figure 5-8 : Power Meter Equipment Setup

 Set the generator frequency to 10 MHz

 Set the generator amplitude to measure 8 µW on the power meter.

 Read the displayed generator output amplitude, and record it in the fourth
column of Table 8.

 Repeat the above measurement for the apropiate scope model, 350.1 MHz,

500.1 MHz, 1000,1 & 2000.1 MHz. Record the generator output amplitude

readout in the fourth column of Table 8.

 Disconnect the RF output of the HP8648B/C generator from the power
sensor.

 Connect the RF output of the HP8648B/C generator through the same cable that

was calibrated in the previous step into Channel 1 and connect any attenuators
as listed in the table.

Sine Wave

Generator

Figure 5-9 : 50Ω Bandwidth Equipment Setup

 Set the generator frequency to 10 MHz.
 From the generator, apply the recorded generator signal amplitude to

Channel 1.

 Measure the value of Sdev(1) in Table 8.

WR6K Rev.D Performance Verification 5-33

5-34 Performance Verification WR6K Rev. D

 Increase the frequency of the generator to the maximum input frequency for that

model, adjusting the amplitude so that the power remains constant and measure
the value of Sdev. Record in Table 13.

 Repeat the above 3 steps for Channel 2, (Bandwidth – CH2 10mv.lss) 3

(Bandwidth – CH3 10mv.lss) & 4 (Bandwidth – CH4 10mv.lss) substituting
channel controls and input connector. Record the measurements in Table 13.

 Calculate the ratio to 10 MHz for each channel, sdev

2000.1/ sdev10 (for

WaveRunner 6200)

, sdev1000.1/ sdev10 (for WaveRunner 6100), sdev500.1/sdev 10

(for WaveRunner 6050 or 6051), sdev350.1/ sdev10 (for WaveRunner 6030) and
compare the results to the limits in the test record.

 Repeat the above steps for V/div setting of 50 mV, 100 mV, and 500mV, using

the appropriate Bandwidth - CHx yymv.lss (where x is channel and yy is V/div
setting) panel setup and recording your results in Tables 14 through 16. Use the
power setting and attenuators as shown in the tables.

WR6K Rev.D Performance Verification 5-35

5-36 Performance Verification WR6K Rev. D

5.10 Trigger Level

5.10.1 Description

The trigger capabilities are tested for several cases of the standard edge trigger:

 Channel (internal), and External Trigger sources
 Three DC levels: −2.5, 0, +2.5 major screen divisions
 Positive and negative slopes

5.10.2 Channel Trigger at 0 Division Threshold

Recall Trigger - CH1 0 div neg slope.lss or configure the DSO:

Panel Setups : Recall FROM DEFAULT SETUP
Channels Trace ON Channel 1, Channel 2, Channel 3 & Channel 4
Input Coupling : DC 50Ω on all 4 Channels
Input gain : 100 mV/div. on all 4 Channels
Input offset : 0 mV on all 4 Channels (use show status to verify)

Trigger setup : Edge
Trigger on : C1
Slope 1 : Pos
Mode : Auto
Set Trigger level : DC 0.0 mV
Pre-Trigger Delay : 50 %

Time base : 1 µsec/div.
C1 Pre-Processing: Averaging 10 sweeps
C2 Pre-Processing: Averaging 10 sweeps
C3 Pre-Processing: Averaging 10 sweeps
C4 Pre-Processing: Averaging 10 sweeps

 Set the output of the sine wave generator to 100 KHz.
 Connect the output of the generator to Channel 1 through a 50 Ohm coaxial cable

as shown in Figure 5-10 and adjust the sine wave output amplitude to get 90% of

full scale.

Sine Wave

Generator

Figure 5-10 Channel Trigger Equipment Setup

 Select Measure: Cursors, Horizontal Abs

 Use the "cursor position" knob, to move the Time marker at 0.0 ηs

 Press Clear Sweeps,

 Acquire 10 sweeps and record in Table 15 the level readout displayed below
100 mV in the icon 1, at top left.

 Compare the test results to the corresponding limit in the test record.
 Set Trigger Slope 1 : Neg

WR6K Rev.D Performance Verification 5-37

5-38 Performance Verification WR6K Rev. D

 Acquire 10 sweeps and record in Table 15 the level readout displayed below

100 mV in the icon 1, at top left.

 Set trigger to channels 2, 3 and 4 and for both POS and NEG slope, move input

signal to appropriate channel and compare the test results to the corresponding
limit in the test record.

5.10.3 Channel Trigger at +2.5 Divisions Threshold

 Recall Trigger - CH1 +2.5 div pos slope.lss or configure the DSO as shown in

5.10.2 and for each Channel make the following change :
Set Trigger level : DC +250 mV

 Connect the output of the generator to Channel 1 through a 50 Ohm coaxial
cable.

 Press Clear Sweeps,
 Acquire 10 sweeps and record in Table 15 the level readout displayed below

100 mV in the icon 1, at top left.
 Compare the test results to the corresponding limit in the test record.

 Set Trigger Slope 1 : Neg

 Acquire 10 sweeps and record in Table 15 the level readout displayed below 100

mV in the icon 1, at top left.

 Set trigger to channels 2, 3 and 4 and for both POS and NEG slope move input

signal to appropriate channel and compare the test results to the corresponding
limit in the test record.

5.10.4 Channel Trigger at −2.5 Divisions Threshold

 Recall Trigger - CH1 -2.5 div pos slope.lss or configure the DSO as shown in

5.10.2 and for each channel make the following change :

Set Trigger level : DC −250 mV

 Connect the output of the generator to Channel 1 through a 50 Ohm coaxial
cable.

 Press Clear Sweeps,
 Acquire 10 sweeps and record in Table 15 the level readout displayed below

100 mV in the icon 1, at top left.

WR6K Rev.D Performance Verification 5-39

5-40 Performance Verification WR6K Rev. D

 Compare the test results to the corresponding limit in the test record.
 Set Trigger Slope 1 : Neg
 Acquire 10 sweeps and record in Table 17 the level readout displayed below 100

mV in the icon 1, at top left.

 Set trigger to channels 2, 3 and 4 and for both POS and NEG slope move input

signal to appropriate channel and compare the test results to the corresponding
limit in the test record.

5.11 Time Base Accuracy

5.11.1 Description

An external sine wave generator of 10.0 MHz with frequency accuracy better than 1
PPM is used.

Specifications

10 GHz clock : accuracy : ≤ ±0.0005 % or ≤ ±5 PPM

5.11.2 10 GHz Clock Verification Procedure

 Recall Timebase Accuracy.lss or configure the DSO

Panel Setups : Recall FROM DEFAULT SETUP

Channels trace ON Channel 1
Input gain : .1 V/div.
Input offset : 0 mV
Trigger setup : Edge
Trigger on : C1
Slope 1 : Pos

Level 1 : 100 mV
Trigger mode : Norm

Delay : 0 %
Time base : 500 msec/div.
Channel use : 4

Measure : Parameters
P1 : Amplitude of C1

P2 : Frequency of C1

 Connect the RF output of the signal generator through a 50 Ohm
coaxial cable into Channel 1.

 Set the generator frequency to 10.0 MHz.
 Adjust the generator output amplitude to get 6 divisions peak to peak.

 Read of the frequency parameter (to 2 decimal places) and record the value in

Table 18.

 Verify that the error is less than 50 Hz.

WR6K Rev.D Performance Verification 5-41

5-42 Performance Verification WR6K Rev. D

5-42 Performance Verification WR6K Rev. D

WaveRunner 6000 Test Record

LeCroy Digital Storage Oscilloscope

Performance Certificate

WaveRunner 6K Manual Performance Test Procedure Version D – Feb. 2007

Model Serial Number Customer

Software Version
Inspection Date Next Due
Temperature Humidity %
Tested By Report Number
Place of Inspection
Condition found Condition Left

Approved By

Test Equipment Used

Instrument Model S/N Cal Due Date
Signal Generator

Radio Frequency
Signal Generator

Audio Frequency
Voltage Generator

DC Power Supply
Digital Multimeter

Voltmeter, Ohmmeter
Traceable to

Table 1: WaveRunner Test Report

Rev. D 1 of 12

This page intentionally left blank

Rev. D 2 of 12

WaveRunner 6000 Test Record

Coupling Volts/div. Measured

Channel 1

Impedance

Ω, MΩ

Measured

Channel 2

Impedance

Ω, MΩ

Measured

Channel 3

Impedance

Ω, MΩ

Measured
Channel 4

Impedance

Ω, MΩ

Measured

External

Impedance

Ω, MΩ

Lower

Limit

Ω, MΩ

Upper

Limit

Ω, MΩ

DC 1MΩ

20 mV/div

0.9875 MΩ 1.0125 MΩ

DC 1MΩ

200 mV/div

0.9875 MΩ 1.0125 MΩ

DC 1MΩ

2 V/div

0.9875 MΩ 1.0125 MΩ

DC 50Ω

20 mV/div

49.25 Ω 50.75 Ω

DC 50Ω

200 mV/div

49.25 Ω 50.75 Ω

DC 50Ω

49.25 Ω 50.75 Ω

DC 1MΩ

0.9875 MΩ 1.0125 MΩ

Table 2: Impedance Test Record

Coupling Volts/div. Measured

Channel 1

Leakage

mV

Measured
Channel 2

Leakage

mV

Measured

Channel 3

Leakage

mV

Measured
Channel 4

Leakage

mV

Measured

External

Leakage

mV

Lower

Limit

mV

Upper

Limit

mV

DC 1MΩ

20 mV/div

−2

+2

DC 1MΩ

200 mV/div

-2 +2

DC 1MΩ

2 V/div

−2

+2

DC 50Ω

20 mV/div

−2

+2

DC 50Ω

200 mV/div

−2

+2

DC 50Ω

−2

+2

DC 1MΩ

−2

+2

Table 3: Leakage Voltage Test Record

Rev. D 3 of 12

WaveRunner 6000 Test Record

Coupling Time/Div. Measured

Pkpk Channel

1

mV

Measured

Pkpk Channel

2

mV

Measured

Pkpk Channel

3

mV

Measured

Pkpk Channel

4

mV

Limits

pk-pk

mV

DC 50Ω

1 µs

7.5

DC 50Ω

1 ms 7.5

DC 50Ω : 2 Channel Mode 0.5 µs

7.5

Table 4: Peak to Peak Noise Test Record

Rev. D 4 of 12

WaveRunner 6000 Test Record

Volts

/div.

Attenuator P S

Output

Measured Channel 1

V & mV

Measured Channel 2

V & mV

Measured Channel 3

V & mV

Measured Channel 4

V & mV

Limits

DMM

1

Mean

(A)

∆ 1

Mean−

DMM

DMM

2

Mean

(B)

∆ 2

Mean−

DMM

DMM

3

Mean

(C)

∆ 3

Mean−

DMM

DMM

4

Mean

(D)

∆ 4

Mean−

DMM

mV

2 mV X 100 +0.6 V ±2.3
5 mV X 100 +1.5 V ±2.8

10 mV X 100 +3.0 V ±3.6

.1 V X 10 +3.0 V ±18

1 V X 1 +3.0 V ±162

Table 5: DC 50Ω, Positive DC Accuracy Test Record

Volts

/div.

Attenuator P S

Output

Measured Channel 1

V & mV

Measured Channel 2

V & mV

Measured Channel 3

V & mV

Measured Channel 4

V & mV

Limits

DMM

1

Mean

(A)

∆ 1

Mean−

DMM

DMM

2

Mean

(B)

∆ 2

Mean−

DMM

DMM

3

Mean

(C)

∆ 3

Mean−

DMM

DMM

4

Mean

(D)

∆ 4

Mean−

DMM

mV

2 mV X 100 +0.6 V ±2.3
5 mV X 100 +1.5 V ±2.8

10 mV X 100 +3.0 V ±3.6

.1 V X 10 +3.0 V ±18

1 V X 1 +3.0 V ±162

Table 6: DC 50Ω, Negative DC Accuracy Test Record

Rev. D 5 of 12

WaveRunner 6000 Test Record

Volts

/div.

Attenuator P S

Output

Measured Channel 1

V & mV

Measured Channel 2

V & mV

Measured Channel 3

V & mV

Measured Channel 4

V & mV

Limits

DMM Mean

1 (A)

∆ 1

Mean−

DMM

DMM

2

Mean

(B)

∆ 2

Mean−

DMM

DMM

3

Mean

(C)

∆ 3

Mean−

DMM

DMM

4

Mean

(D)

∆ 4

Mean−

DMM

mV

2 mV X 100 +0.6 V ±2.3
5 mV X 100 +1.5 V ±2.8

10 mV X 100 +3.0 V ±3.6

200 mV X 10 +6.0 V ±34

2 V X 1 +6.0 V ±322

Table 7: DC 1MΩ, Positive DC Accuracy Test Record

Volts

/div.

Attenuator P S

Output

Measured Channel 1

V & mV

Measured Channel 2

V & mV

Measured Channel 3

V & mV

Measured Channel 4

V & mV

Limits

DMM Mean

1 (A)

∆ 1

Mean−

DMM

DMM

2

Mean

(B)

∆ 2

Mean−

DMM

DMM

3

Mean

(C)

∆ 3

Mean−

DMM

DMM

4

Mean

(D)

∆ 4

Mean−

DMM

mV

2 mV X 100 +0.6 V ±2.3
5 mV X 100 +1.5 V ±2.8

10 mV X 100 +3.0 V ±3.6

200 mV X 10 +6.0 V ±34

2 V X 1 +6.0 V ±322

Table 8: DC 1MΩ, Negative DC Accuracy Test Record

Rev. D 6 of 12

WaveRunner 6000 Test Record

Measured Channel 1

V & mV

Measured Channel 2

V & mV

Measured Channel 3

V & mV

Measured Channel 4

V & mV

Limits

Volt
/div.

Coupling

DC

DSO

Offset

V

P S

Output

V

DMM

1

Mean

(A)

∆ 1

Mean−

DMM

DMM

2

Mean

(B)

∆ 2

Mean−

DMM

DMM

3

Mean

(C)

∆ 3

Mean−

DMM

DMM

4

Mean

(D)

∆ 4

Mean−

DMM

mV

50mV

50 Ω

+.750

−.750

±14.2

Table 9: Positive 50Ω Offset Test Record

Measured Channel 1

V & mV

Measured Channel 2

V & mV

Measured Channel 3

V & mV

Measured Channel 4

V & mV

Limits

Volt
/div.

Couplin

g

DC

DSO

Offset

V

P S

Output

V

DMM

1

Mean

(A)

∆ 1

Mean−

DMM

DMM

2

Mean

(B)

∆ 2

Mean−

DMM

DMM

3

Mean

(C)

∆ 3

Mean−

DMM

DMM

4

Mean

(D)

∆ 4

Mean−

DMM

mV

50mV

50 Ω

+.750

−.750

±14.2

Table 10: Negative 50Ω Offset Test Record

Measured Channel 1

V & mV

Measured Channel 2

V & mV

Measured Channel 3

V & mV

Measured Channel 4

V & mV

Limits Volt

/div.

Coupling

DC

DSO

Offset

V

P S

Output

V

DMM

1

Mean

(A)

∆ 1

Mean−

DMM

DMM

2

Mean

(B)

∆ 2

Mean−

DMM

DMM

3

Mean

(C)

∆ 3

Mean−

DMM

DMM

4

Mean

(D)

∆ 4

Mean−

DMM

mV

50mV

1 MΩ

+.750

−.750

±14.2

Table 11: Positive 1MΩ Offset Test Record

Rev. D 7 of 12

WaveRunner 6000 Test Record

Measured Channel 1

V & mV

Measured Channel 2

V & mV

Measured Channel 3

V & mV

Measured Channel 4

V & mV

Limits

Volt
/div.

Couplin

g

DC

DSO

Offset

V

P S

Output

V

DMM

1

Mean

(A)

∆ 1

Mean−

DMM

DMM

2

Mean

(B)

∆ 2

Mean−

DMM

DMM

3

Mean

(C)

∆ 3

Mean−

DMM

DMM

4

Mean

(D)

∆ 4

Mean−

DMM

mV

50mV

1 MΩ

+.750

−.750

±14.2

Table 12: Negative 1MΩ Offset Test Record

Frequency Measured

Power

Generator
Amplitude

Measured

Channel 1

Measured

Channel 2

Measured
Channel 3

Measured

Channel 4

Lower

Limit

MHz

µW

mV

Sdev(1)

mV

Ratio(1)

to 10

Sdev(2)

mV

Ratio(2)

to 10

Sdev(3)

mV

Ratio(3)

to 10

Sdev(4)

mV

Ratio(4)

to 10

10

8.0

N/A

N/A

N/A

N/A N/A

350.1

(WR 6030)

8.0 0.707

500.1

(WR 6050,

6051)

8.0 0.707

1000.1

(WR 6100)

8.0 0.707

2000.1

(WR 6200)

8.0 0.707

Table 13: DC 50Ω, 10 mV/div. Bandwidth Test Record

Rev. D 8 of 12

WaveRunner 6000 Test Record

Frequency Measured

Power

Generator
Amplitude

Measured
Channel 1

Measured

Channel 2

Measured
Channel 3

Measured

Channel 4

Lower

Limit

MHz

mW

mV

Sdev(1)

mV

Ratio(1)

to 10

Sdev(2)

mV

Ratio(2)

to 10

Sdev(3)

mV

Ratio(3)

to 10

Sdev(4)

mV

Ratio(4)

to 10

10

0.22

N/A

N/A

N/A

N/A N/A

350.1

(WR 6030)

0.22 0.707

500.1

(WR 6050,

6051)

0.22 0.707

1000.1

(WR 6100)

0.22 0.707

2000.1

(WR 6200)

0.22 0.707

Table 14: DC 50Ω, 50 mV/div. Bandwidth Test Record

Rev. D 9 of 12

WaveRunner 6000 Test Record

Frequency Measured

Power

Generator
Amplitude

Measured
Channel 1

Measured

Channel 2

Measured
Channel 3

Measured

Channel 4

Lower

Limit

MHz

mW

mV

Sdev(1)

mV

Ratio(1)

to 10

Sdev(2)

mV

Ratio(2)

to 10

Sdev(3)

mV

Ratio(3)

to 10

Sdev(4)

mV

Ratio(4)

to 10

10

0.8

N/A

N/A

N/A

N/A N/A

350.1

(WR 6030)

0.8 0.707

500.1

(WR 6050,

6051)

0.8 0.707

1000.1

(WR 6100)

0.8 0.707

2000.1

(WR 6200)

0.8 0.707

Table 15: DC 50Ω, 100 mV/div. Bandwidth Test Record

Rev. D 10 of 12

WaveRunner 6000 Test Record

Frequency Measured

Power

Generator
Amplitude

Measured
Channel 1

Measured

Channel 2

Measured
Channel 3

Measured

Channel 4

Lower

Limit

MHz

mW

mV

Sdev(1)

mV

Ratio(1)

to 10

Sdev(2)

mV

Ratio(2)

to 10

Sdev(3)

mV

Ratio(3)

to 10

Sdev(4)

mV

Ratio(4)

to 10

10

22.0

N/A

N/A

N/A

N/A N/A

350.1

(WR 6030)

22.0 0.707

500.1

(WR 6050,

6051)

22.0 0.707

1000.1

(WR 6100)

22.0 0.707

2000.1

(WR 6200)

22.0 0.707

Table 16: DC 50Ω, 500mV/div. Bandwidth Test Record

Rev. D 11 of 12

WaveRunner 6000 Test Record

Trigger

Level

Trigger

Slope

Channel 1 Channel 2 Channel 3 Channel 4 Lower

Limit

Upper

Limit

mV

Measured

DC

Trigger

Level (1)

mV

Measured

DC

Trigger

Level (2)

mV

Measured

DC

Trigger

Level (3)

mV

Measured

DC

Trigger

Level (4)

mV

mV

mV

0 Pos

−44

+44

0 Neg

−44

+44
+250 Pos +218 +282
+250 Neg +218 +282

−250

Pos -282 -218

−250

Neg -282 -218

Table 17: Channel DC Trigger Test Record

Generator
Frequency

MHz

Freq.(1)

(Hz)

Lower

Limit

Upper

Limit

10.0 -50 +50

Table 20: Time Base Test Record

Rev. D 12 of 12

Maintenance 6-1

6. Maintenance

6.1 Introduction

This section contains information necessary to disassemble, assemble, maintain,
calibrate and troubleshoot the LeCroy WaveRunner6000.

6.1.1 Safety Precautions

The

symbol used in this manual indicates dangers that could result in

personal injury.

The

symbol used in this manual identifies conditions or practices that could

damage the instrument.

The following servicing instructions are for use by qualified personnel only.
Do not perform any servicing other than contained in service instructions. Refer to
procedures prior to performing any service.

Exercise extreme safety when testing high energy power circuits. Always turn
the power OFF, disconnect the power cord and discharge all capacitors before
disassembling the instrument.

6.1.2 Anti-static Precautions

Any static charge that builds on your person or clothing may be sufficient to

destroy CMOS components, integrated circuits, Gate array’s..........etc.

In order to avoid possible damage, the usual precautions against static electricity are
required.

• Handle the boards in anti-static boxes or containers with foam specially designed

to prevent static build-up.

• Ground yourself with a suitable wrist strap.

• Disassemble the instrument at a properly grounded work station equipped with

anti-static mat.

• When handling the boards, do not touch the pins.

• Stock the boards in anti-static bags.

6-2 Maintenance

6.2 Disassembly and Assembly Procedure

The disassembly and assembly procedures detailed below refer to the views of
figures shown in section 8.

6.2.1 Disassembly Procedure

Please study the figures in section 8 before attempting disassembly. Before
removing any parts from the LeCroy WaveRunner, be sure to read carefully the
instructions referring to those parts, noting any precautions needed to avoid
problems.

Note: Power is always present on the CPU motherboard and inside the Power
Supply whenever the power cord is plugged into a power source. Remove the
power cord from the instrument before removing or inserting any connectors to the
CPU motherboard. Extreme caution should be taken in protecting the LCD face
from damage (e.g. scratch marks, etc.) when handling, in particular when inserting
or removing from the instrument.

a. Removal of the Upper Cover Assembly

The upper cover disassembly procedure refers to the view of figure 8-1.

Tools Needed:

• T15 Torx driver

• #2 Philips screwdriver

Procedure:

• Remove the front bezel (see procedure 6.2.1.a)

• Remove the twelve 6-32 x ¼” screws (five on right side, three on left side and four

in the rear).

• Remove the two 6-32 x ½” screws that secure the two upper feet to the upper

cover and rear panel.

• Carefully slide the upper cover off the unit. If the unit has an optional internal

printer disconnect printer power cable and data cable.

b. Opening of the Front Bezel

The front bezel disassembly procedure refers to the view of figure 8-2.

Tools Needed:

• T10 Torx driver

• #1 Philips screwdriver

Procedure:

• Remove four 6-32 x 5/16” screws underneath the plastic bezel.

• Remove two 6-32 x ¼” screws (one on each side of the front frame near the

bottom)

• The Front Frame can now be pivoted up to allow access for further instrument

disassembly. Pay close attention to the power switch and spring as these will fall
off once the front frame is pivoted away from chassis.

c. Removal of the Acquisition System Assembly

The Acquisition System removal procedure refers to the view of figure 8-1 & 8-4.

Tools Needed:

• #2 Philips screwdriver

Procedure:

• Remove the upper cover assembly (6.2.1.a)

• Open the front bezel (6.2.1.b)

• Disconnect the power connectors at J23, J19 and J15.

• Disconnect the USB cable at J26

• Disconnect the power switch cable at J24

• Disconnect the two ribbon cables from the PCI card at the acquisition board

connectors J11 and J10.

• Remove the nine 6-32 x 5/16” screws through the bottom of the chassis.

• Gently slide the Acquisition board forward and disconnect the fan cable at J4 and

the Triggered/Ready LED cable at J9000.

The acquisition system can now be removed from the oscilloscope.

Maintenance 6-3

6-4 Maintenance

d. Removal of the PCI Board

The PCI board removal procedure refers to the views of figure 8-5 and figure 8-9

Tools Needed:

• Diagonal cutting pliers

Procedure:

• Remove the upper cover assembly (6.2.1.a)

• Disconnect the two ribbon cables at J1 and J2 of the PCI card.

• Cut the cable clamp which secures the PCI card to the motherboard.

• Unplug the PCI card from the processor board.

e. Removal of the AGP-DVO Interface Board

The AGP-DVO removal procedure refers to the views of figure 8-5 and figure 8-9

Tools Needed:

• none

Procedure:

• Remove the upper cover assembly (6.2.1.a)

• Disconnect the video cable at J1 of the DVO Card.

• Disconnect the inverter power cable at J2.

• Bend the spring clamp on the AGP connector on the processor card slightly to

disengage the lock to the AGP/DVO card.

• Unplug the AGP/DVO card from the processor board.

f. Removal of the Processor Board

The processor board disassembly procedure refers to the views of figure 8-7 and
figure 8-9.

Tools Needed:

• #1 Philips screwdriver

Procedure:

• Remove the upper cover assembly (6.2.1.a)

• Remove the PCI card (6.2.1.d)

• Remove the AGP/DVI Interface (6.2.1.e).

• Disconnect the following cables on the processor board:

Processor Connector Connects to

Primary IDE Hard Drive

Secondary IDE CD ROM drive

Main Power Power supply harness

Supplemental Processor Power Power supply harness

Front Panel USB USB Hub & Acq Board

Front Panel Header Power Switch – Acq Board