CONDITIONS FOR
CE CONFORMITYSince this product is a subassembly, it is the responsibility of the end
user, acting as the system integrator, to ensure that the overall system is
CE compliant. This product was demonstrated to meet CE conformity
using a CE compliant crate housed in an EMI/RFI shielded enclosure. It
is strongly recommended that the system integrator establish these
same conditions.
3
CAUTION
GENERALCrate power should be turned off during insertion and removal of unit to
avoid possible damage caused by momentary misalignment of contacts.
See pocket in back of manual for schematics, parts list and additional
addenda with any changes to manual.
5
General Information
Purpose9
Unpacking and Inspection9
Warranty9
Product Assistance9
Maintenance Agreements9
Documentation Discrepancies10
Software Licensing Agreement10
Service Procedure10
Front-Panel Diagram11
1. Product Description
1.1General13
1.2Specifications13
1.3Analog Inputs 14
1.4Clear Function14
1.5External Gate Input (GATE) 15
1.6ADC Pedestals 15
1.7Test Function15
1.8Pedestal Memory16
1.9Status Register16
1.10 ECL Port Output18
1.11 ECL Port Readout Handshake19
1.12 Halt of Readout on the ECL Port 20
1.13 CAMAC Readout20
1.14 LAM Handling21
1.15 FERA System Connections21
1.16 Packaging and Power Requirements 22
TABLE OF CONTENTS
2.0 Operating Instructions
2.1General31
2.2CLEAR and GATE Functions32
2.3Charge to Time Converters 32
2.4Test Circuit33
2.5Digital Interpolators 33
2.6Real Time Counters 33
2.7Clock Generators 34
2.8Pedestal Memory 34
2.9Data Compression and Readout Logic 34
2.10 ECL Port Readout Circuit36
2.11 CAMAC Readout Circuit36
2.12 CAMAC Functions Decoder36
2.13 ADC Resolution Adjustment36
3.0 List of Figures and Tables
1.1Readout Timing Diagram23
1.2ECL Port Timing Diagram24
1.3FERA System Connections25
1.4Model 4301 FERA Driver Block Diagram26
1.5Localization of Removable Resistors & VGND-GND Jumper27
1,1a Table: Status Register Format28
7
1.1b Table: Readout Format29
2.1Model 4300B Block Diagram38
2.2Charge-to-Time Converter Block Diagram39
2.3Time-to-Digital Converter Blcok Diagram and Timing40
4.0 Appendix
4.1ECL Differntial I/O Levels41
4.2ECL Single-Ended I/O Levels42
8
GENERAL INFORMATION
PURPOSEThis manual is intended to provide instruction regarding the setup and
operation of the covered instruments. In addition, it describes the theory
of operation and presents other information regarding its functioning and
application.
UNPACKING AND
INSPECTIONIt is recommended that the shipment be thoroughly inspected immedi-
ately upon delivery. All material in the container should be checked
against the enclosed Packing List and shortages reported promptly.
If the shipment is damaged in any way, please notify the Customer
Service Department or the local field service office. If the damage is
due to mishandling during shipment, you may be requested to assist in
contacting the carrier in filing a damage claim.
WARRANTYLeCroy warrants its instrument products to operate within specifications
under normal use and service for a period of one year from the date of
shipment. Component products, replacement parts, and repairs are
warranted for 90 days. This warranty extends only to the originalpurchaser. Software is thoroughly tested, but is supplied "as is" with no
warranty of any kind covering detailed performance. Accessory products
not manufactured by LeCroy are covered by the original equipment
manufacturers' warranty only.
In exercising this warranty, LeCroy will repair or, at its option, replace any
product returned to the Customer Service Department or an
authorized service facility within the warranty period, provided that the
warrantor's examination discloses that the product is defective due to
workmanship or materials and has not been caused by misuse, neglect,
accident or abnormal conditions or operations.
The purchaser is responsible for the transportation and insurance
charges arising from the return of products to the servicing facility.
LeCroy will return all in-warranty products with transportation prepaid.
This warranty is in lieu of all other warranties, express or implied, including but not limited to any implied warranty of merchantability, fitness, or
adequacy for any particular purpose or use. LeCroy shall not be liable
for any special, incidental, or consequential damages, whether incontract, or otherwise.
PRODUCT ASSISTANCEAnswers to questions concerning installation, calibration, and use of
LeCroy equipment are available from the Customer Service Department,
700 Chestnut Ridge Road, Chestnut Ridge, New York, 10977-6499,
(914) 578-6030.
MAINTENANCE
AGREEMENTSLeCroy offers a selection of customer support services. For example,
Maintenance Agreements provide extended warranty that allows the
customer to budget maintenance costs after the initial warranty has
expired. Other services such as installation, training, on-site repair, and
addition of engineering improvements are available through specific
Supplemental Support Agreements. Please contact the Customer
Service Department for more information.
9
DOCUMENTATION
DISCREPANCIESLeCroy is committed to providing state-of-the-art instrumentation and is
continually refining and improving the performance of its products. While
physical modifications can be implemented quite rapidly, the corrected
documentation frequently requires more time to produce. Consequently,
this manual may not agree in every detail with the accompanying product
and the schematics in the Service Documentation. There may be small
discrepancies in the values of components for the purposes of pulse
shape, timing, offset, etc., and, occasionally, minor logic changes.
Where any such inconsistencies exist, please be assured that the unit is
correct and incorporates the most up-to-date circuitry.
SOFTWARE LICENSING
AGREEMENTSoftware products are licensed for a single machine. Under this license
you may:
■Copy the software for backup or modification purposes in support of
your use of the software on a single machine.
■Modify the software and/or merge it into another program for your
use on a single machine.
■Transfer the software and the license to another party if the other
party accepts the terms of this agreement and you relinquish all
copies, whether in printed or machine readable form, including all
modified or merged versions.
SERVICE PROCEDUREProducts requiring maintenance should be returned to the Customer
Service Department or authorized service facility. If under warranty,
LeCroy will repair or replace the product at no charge. The purchaser is
only responsible for the transportation charges arising from return of the
goods to the service facility. For all LeCroy products in need of repair
after the warranty period, the customer must provide a Purchase Order
Number before any inoperative equipment can be repaired or replaced.
The customer will be billed for the parts and labor for the repair as well
as for shipping. All products returned for repair should be identified by
the model and serial numbers and include a description of the defect or
failure, name and phone number of the user. In the case of products
returned, a Return Authorization Number is required and may be
obtained by contacting the Customer Service Department at (914) 578-
6030.
10
Pull Down ON (LED
indicator) indicates
that pull down and
input resistors are
mounted on Command
bus (Sec. 1.15)
Pull Down on (LED
Indicator) indicates
that pull down
resistors are mounted
on the ECL output
Port (Sec. 1.15)
Common Virtual Ground
(Sec. 1.3)
Ground (Sec 1.3)
ECL output port
(Sec 1.10)
Last 2 pins not
connected
11
PRODUCT DESCRIPTION
1.1 GeneralThe LeCroy Model 4300B FERA contains 16 independent charge-todigital converters with common GATE and common CLEAR.
Four basic factory options are available:
a. 8 or 9 bits with 100 ohm impedance
b. 8 or 9 bits with 50 ohm input impedance
c. 10 or 11 bits with 100 ohm input impedance
d. 10 or 11 bits with 50 ohm input impedance.
The options a, b and c are only produced for large quantities. The
resolution on each of the above versions may be adjusted via jumpers
and an internal potentiometer (see Section 2.13 for details).
An 8-bit register (Status Register) and a memory (Pedestal Memory),
containing the individual pedestal (or offset) values to be subtracted from
each ADC, allow different readout modes of the 16 digitized ADC values.
Both the Status Register and Pedestal Memory must be previously
loaded via CAMAC. Data may be read out either via the CAMAC
dataway or the ECL port. The state of the Status Register determines the
readout modes. The ECL port output, located on the front-panel, is first
activated and delivers ADC data sequentially in words of 16 bits (8 to 11
bits of data plus 4 subaddress) at differential ECL levels. When data are
ready to be read at the ECL port, the REQ output is activated.
In CAMAC mode, data are also read out in 16-bit words in either random
access or sequential CAMAC readout (Q stop mode). The CAMAC
readout can only be carried out after completion of ECL port readout.
When data are ready for readout via CAMAC dataway, a LAM may be
generated and there is a Q response to the readout function F(2). The
data read out mode via these two ports may be independently selected
and programmed to be in one of three states: 1) raw; 2) with the pedestal subtracted; or 3) compacted, i.e., all data < 1 are eliminated (Zero
suppression).
A system for testing the 16 ADCs is incorporated in the Model 4300B.
The test is initiated by the CAMAC command F(25) A(0). This command
opens the ADC GATEs and applies, at the input of each one, a charge
proportional to the continuous voltage that must be given on the front
panel TRV input.
13
The Model 4300B will be in one of two states: “ready” or “busy”; depending on the GATE and CLEAR signals sent via either the front-panel or
CAMAC command. After a CLEAR, the module is in the “ready” state,
i.e., ready to receive a GATE (front-panel or test): the logic and the ADCs
are permanently cleared. It is only in the “ready” state that the Status
Register and the Pedestal Memory may be loaded or read via CAMAC.
After a GATE (front panel or test): the module changes to the “busy”
state and no other GATE signal will be accepted. The GATE disables the
reset, opens the ADCs and initiates the charge digitization logic. At the
end of the conversation time, data readout is enabled. At this time,
depending on the state of the Status Register and the ADC data values
to be read, one of four conditions may be present:
a. Data readout via ECL port and CAMAC. In this case, the ECL port
must be read first and only upon its completion can CAMAC readout
take place.
b. Data readout via ECL port only. In this case, only the ECL port is
enabled.
c. Data readout via CAMAC only. Here, the ECL port readout is not
enabled; CAMAC readout is enabled immediately at the end of
conversation.
d. No data to be read. In this case, no data readout is enabled.
To eliminate unwanted data or accept further GATE after data read out, a
CLEAR must be applied to the 4300B unit (see Figure 1.1).
1.3 Analog InputsThe 16 analog inputs are designed for negative signals with respect to a
floating common signal ground (Common Virtual Ground) which is
coupled to the module ground via capacitors. Input impedance is 50 or
100 ohm with respect to the Common Virtual Ground. All 16 inputs are
protected against positive signals by diodes connected to the module
ground, and against too high amplitude negative signals by diodes
connected to a -3 V potential. The Common Virtual Ground is also
protected against large swings of voltage by two diodes connected to the
module ground.
If the user wishes to connect the Common Virtual Ground to the module
ground, the 16 upper right hands pin (VGND, Common Virtual Ground)
may be connected to the lower 2 pins (GND, module ground), of the
input connector. Another option is to solder a jumper between the two
points designed for this function located on the printed circuit board (see
Figure 1.5).
1.4 Clear FunctionA clear is initiated by a front-panel CLEAR input and by CAMAC functions Z, C or F(9) A(0) strobed by S2. Front-panel CLEAR and F(9) A(0)
have priority over the GATE signal and care must be taken not to generate any gate in coincidence with them. As a result, the GATE signal
duration would be modified.
14
These commands set a latch maintaining the clear level (“ready” state of
module) until the next GATE signal. The front ends of the ADCs require
at least 2 µs after a clear to guarantee a ± 1 count precision. They are
automatically cleared at the end of conversation after digitized charges
have been memorized. Thus, a 2 µs delay before a new GATE is only
necessary when the CLEAR command is used during conversation. After
power-on, a clear function must be applied for the module to be in the
“ready” state.
1.5 External Gate
Input (GATE)A GATE command is effective only if the module is in the “ready” state
and if the CLEAR command is released. The GATE input is inhibited
when the I (CAMAC Inhibit) line is ON. A 100 ns integrator is placed on
the I line.
A valid GATE signal commands the following functions:
a. Releases the clear on the ADC front ends.
b. Opens ADC gate for its entire duration.
c. Enables ADC pedestal injection circuit.
d. The end of the GATE starts conversation, switches the module to the
“busy” state and inhibits the GATE input.
The GATE signal must precede analog input signals by a minimum of
20 ns and its length may vary from 50 ns to 500 ns. Use of a GATE
longer than 500 ns is possible, but it may require adjustment of ADC
pedestals (see Sections 1.6 and 2.3).
1.6 ADC PedestalsThe 16 ADC pedestals are generated by the injection of a small charge
at the leading edge of the GATE. The pedestal value may be adjusted via
an internal potentiometer, 0 adjustment. A common circuit compensates,
to a large degree, the variations of the pedestals with respect to GATE
width.
The Model 4300B is adjusted so that the pedestals remain between 1
and 13 pC for GATE durations of 50 ns to 500 ns. For a GATE larger
than 500 ns, some ADCs channels may have pedestals below 0 pC. The
charge injected by the O adjustment potentiometer must be increased to
obtain at least 1 pC.
The pedestals may be subtracted from the ADC value during ECL port or
CAMAC readout, independently.
1.7 Test FunctionThe test function is initiated by the CAMAC command F(25) A(0) strobed
by S2, when accepted, Q response is given. This function is accepted
only when the module is in the “ready” state; no Q response will be given
if the command is not accepted.
The test function controls the following operations:
a. Releases the clear on the front end of the ADCs.
b. Opens the GATE for a duration of 550 ns, during which time no
signal is allowed on any of the analog inputs, although the cable may
remain connected. The gate input may, but need not, be blocked by
the CAMAC command I.
15
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