LDIC LC25TR00-20 Datasheet
LC25TR00-20
Communication Section
LSI Communication 2.5Gb/S Ethernet Tranceiver
LSI Communication 2.12Gb/S Fiber Channel Tranceiver
2.12/1.06 Gbit/Sec. Fiber Channel Transceiver
2.5/1.25 Gbits/Sec. Ethernet Transceiver
Advance optional PRML data and clock recovery
Auto detectable/ switchable full or half speed
Maximum serial data output Random Jitter (RMS) 4.0 p.S
Maximum Serial data output deterministic jitter (p-p) 25.0 p.S
Maximum data output total jitter (p-p) in loop back mode 1.8 n.S
Data Acquisition lock time at 2.5Gb/S is 1000 Bit Clock
Lowest power consumption at 2.5Gb/S, 550mW max
Fully compliant with 802.3z Ethernet Specification
Fully scalable technology path toward 10Gb/S Ethernet
Total Power dissipation at 2.5Gb/S is 2.0W
Advance 0.18microm CMOS technology
80-pin or 100-pin EDQUAD package
FEATURES
GENERAL
LC25TR00-20
Comma
Detect
Logic
Frequency
Synthesizer
PLL Clock
Multiply (x20)
Frame
Logic
Serial
to
Parallel
Pipeline
Clock
Recovery
EWRAP
R0:19
20
2:1
RXRATE
Data
Received
PRML
RBC
RBCN
COMMA_DETECTED
COMMA_DETECT_ENABLE
T0:19
TBC
REF
TXRATE
BCMN
20
125 MHz
Retimed
Data
Recovered
Clock
125 MHz
2.5 Gb/s
Serial Data
2.5 GHz
Synthesized
Clock
DECODER
RX-
RX+
TX-
TX+
Loop Back
2:1
2:1
2.5 Gb/s
Synchronized
Decoder
Data
In
Parallel
to
Serial
ENCODER
20
Recoverd Bus
Disparity Calculator
Data Encoder
Command Encoder
Merged Phase Block
Word Alignment
State Machine
Synchronizer
RX-Reset
TX-Reset
LDIC 1.25/2.5 Gb/s Ethernet Tranceiver
LDIC 1.06/2.12 Gb/s Fiber Channel Tranceiver
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