LCFC V530 schematics

1 1

2 2

V330/V530/EX3

DIS M/B Schematics Document

Intel Kabylake RU Processor with DDR4

AMD R17M

2017-06-15

3 3

LA-F481P

R E V

4 4

0 . 2

：

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

Date: Sheet of

Cover Page

Document Number Re v

Document Number Rev

LA-D562P

1 66Thursday, June 15, 2017

0.1

www.schematic-x.blogspot.com

Channel A

DDR4 2133/2400MHz (1.2V , 2.5V)

AMD Radeon 530M

1 1

VRAM GDDR5 x2

P21

eDP Conn.

FHD

P28

HDMI Conn. (HDMI 1.4)

RJ45 Conn.

2 2

LAN

RTL8111H-CG 100/1000

M.2 SSD

P29

P36

PCIe X4 / SATA X1

(TYPE M)

P32

PCIe X1 for WLAN

WLAN / BT

USB2.0 x1 for BT

P31

2nd Battery / USB2.0 conn. (Reserve)

P46

Card Reader

Realtek

3 3

LED

RTS5146

Finger Print

DC to DC

Touch Pad

APS

4 4

P37

P33

P46

PCIe X4

eDP X1 (2 Lanes)

DDI X1

PCIe X1

USB2.0 x1

SMBUS

TPM/TCM

Opt i on

Intel KBL-RU 15W/28W

I2C

ENE KB9022

P27 P45

Int. KBD

SOC

1356pin BGA

SPILPC

SPI ROM

16MB

P33

Channel B

DDR4 2133/2400MHz (1.2V , 2.5V)

DDR4 support 2133/2400MHz on KBL-RU DDR4 support 2133MHz on SKL and KBL-U

USB3.0 x1 USB2.0 x1

USB3.0 x1

TypeC

RTS5448

CC+MUX

USB3.0 x1

DDI X1

DP MUX

PS8338B

P38

USB2.0 x1

SATA X1

HDA

Int. MIC Conn. Int. Speaker Conn.

P08

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

P28

Compal Secret Data

Deciphered Date

On board DDR4 X 4

DDR4 SO DIMM X1

Right USB3.0 x1

Left USB3.0 x1

With AOU

USB3.0 x1 USB2.0 x1

P42 P43

TypeC

RTL5455

PD+DP+MUX

CRT converter

RTD2166

Int. Camera

HDD Conn.

P28

P30

Audio Codec

CONEXANT CX11802

P35

P18

P19

P34

TypeC (CC)

USB3.0 x1 USB2.0 x1

P40 P41

P39

TypeC (CC+PD+DP)

CRT Conn.

Opt i on

Audio Combo Jack

P35

HP & MIC

P35

Compal Electronics, Inc.

Title

Size

Document Number Rev

Date: Sheet of

Block Diagram

LA-D562P

2 66Thursday, June 15, 2017

P39

1.0

Voltage Rails

power

A A

B B

S5 and S4/Battery only

S5 and S4/AC&Battery don't exist(Only RTC )

plane

State

S5 and S4/AC

+RTCBATT

+5VL

+3VL

+5VALW

+3VALW

+1.8VALW

+1VALW

EC SM Bus1 address

Device

Smart Battery

Address

0001 011x

PCH SM Bus address

Device

DDR_JDIMM1 GPU RTS5455 RTD2166

C C

APS

Address

1010 000x A0h 1000 001x A0h

010 1100 A0h

1 1100 100 A0h 1111 0100 A0h

+1.0V_VCCST

+2.5V

+1.2V

O O

+5VS +3VS +3VGS +1.8VGS +1.0VS_VCCIO +PCIE_VGS +VGA_CORE +1.35VS_VRAM +0.6VS +VCCCORE +VCCGT +VCCSA

XXX

CPU

2+2

2+3

USB 2.0 Port Table

Port

1 2 3 4 5 6 7 8 9 10

3 External USB Port

USB 3.0 Port (AOU)

USB 3.0 Port

TYPE-C USB 3.0 Port TYPE-C USB 3.0 Port(FULL) Camera

M.2 BT

Card Reader

Finger Print

2nd Battery

USB 3.0 Port Table

USB 3.0 Port (AOU)

USB 3.0 Port

TYPE-C USB 3.0 Port

TYPE-C USB 3.0 Port(FULL)

5 6

SATA Port Table

Port

HDD

M.2 SATA SSD

SKL-U

UC1

CPU1@ SA000092P60

UC1

CPU5@ SA00009E620

i7-6500U

i7-6567U

UC1

CPU2@

i5-6300U

SA000092T40

UC1

CPU4@

i3-6006U

SA0000ACN10

UC1

CPU6@

i5-6267U

SA00009E530

UC1

CPU3@

i5-6200U

SA000092O70

KBL-U

UC1

CPU7@

i3-7100U

SA0000A38H0

UC1

CPU10@

i5-7300U

SA0000ADO20

UC1

CPU13@

i7-7567U

SA0000AW620

BOM Structure Table

PCIE Port Table

Port

Lane

4 5 6 7 8 9 10 11 12

i5-7200U

3865U

i5-7267U

UC1

CPU9@

i7-7500U

SA0000A34F0

UC1

CPU12@

4415U

SA0000ADV40

UC1

CPU8@ SA0000A37B0

UC1

CPU11@ SA0000ADL30

UC1

CPU14@ SA0000AKR20

GPU

LAN

M.2 WLAN+BT

M.2 PCIE*4 SSD

KBL-RU

UC1

CPU15@

KBL-R QN5D

SA0000AR010

UC1

CPU17@

KBL-R QNEF

SA0000AWB00

SKL only SKL@ For 2+2 U22@ For 2+3 For 4+2 For DIS

EMI Un-pop ESD pop ESD Un-pop

Finger Print Keyboard backlight KBL@

NONAOU NONAOU@

APS NOAPS 2nd Battery USB BATT2@ NO 2nd Battery USB

Onboard RAM MICRON Onboard RAM SAMSUNG VRAM HYNIX VRAM MICRON VRAM SAMSUNG CardReader RTS5146 CardReader GL835 TPM T TCM TCM@ NO TPM/TCM NOTPM@

4+2

UC1

CPU16@

KBL-R QN5C

SA0000AQZ10

UC1

CPU18@

KBL-R QNBF

SA0000AWC00

BOM StructureItem

U23@ U42@ DIS@ UMA@For UMA CMOS@Camera EMI@EMI pop @EMI@ ESD@ @ESD@ RF@RF pop @RF@RF unpop 8M@For SPI 8M 16M@For SPI 16M FP@

AOU@AOU

TYPEC@TYPEC FULL NONTYPEC@NONTYPEC APS@ NOAPS@

NOBATT2@ X76DDRH@Onboard RAM HYNIX X76DDRM@ X76DDRS@ X76H2G@ X76M4G@ X76S2G@ X76RT@ X76GL@

PM@

ME@Connector

SMBUS Control Table

ZZZ

SOURCE

SMB_EC_CK1 SMB_EC_DA1 SMB_EC_CK2 SMB_EC_DA2 PCH_SMBCLK PCH_SMBDATA PCH_SML0CLK PCH_SML0DATA SML1CLK SML1DATA

D D

STATE

Full

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

EC KB9022

+3VALW

EC KB9022

+3VS

PCH

+3VALW

PCH

+3VALW

PCH

+3VALW

SIGNAL

GPU

+3VALW

+3VGS

SLP_S1#

LOW

HIGH HIGH HIGH

LOW

LOW LOW LOW

LOWLOW

SODIMMNECP388BATT

VX X

X X

+3VS

SLP_S4#SLP_S3# +V(RAM)+VALWSLP_S5# Clock+VS

HIGHHIGHHIGH

HIGH

LOWLOW

SOC

+3VALW

3VS

X76DDR4H@

2G HYNIX

X7675138L01

On Board RAM

ZZZ

X76RT@

RTS5146

X7675138L61

OFF

ONON

LOW

OFF

CardReader

ZZZ

X4E@

X4E

X4EA8X38L01

ZZZ

X76DDR4M@

2G MICRON

X7675138L02

ZZZ

X76GL@

GL835

X7675138L62

ZZZ

X76DDR4S@

2G SAMSUNG

X7675138L03

UV1

GPU1@

VGA

SA000098VB0

ZZZ

PCB

DA8001CE000

GPU

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/24 2012/07/12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Notes List

Size

Document Number Rev

Date: Sheet of

LA-D562P

3 66Thursday, June 15, 2017

0.1

[BIWB6/B7/E7/E8-PWR Sequence_SKL-U22_DDR3L_Volume_NON CS]

G3->S0 S0->S3 ->S0

+3VL_RTC

SOC_RTCRST#

B+

D D

+3VLP

EC_ON

+5VALW / +3VALW

CH01_Min : 9 ms

tPCH04_Min : 9 ms

Pull-up to DSW well if not implemented.

/DS3 DS3S3/

S0->S5

+3VL_RTC

SOC_RTCRST#

+19VB

+3VLP/+5VLP

EC_ON

+5VALW/+3VALW/+3 VALW_DSW PM_BATLOW#

PCH_PWR_EN (SLP_SUS#)

+3V_PRIM

+1.8VALW

.0VALW

tPCH06_Min : 200 us

PCH_DPWROK

EC_RSMRST#

AC_PRESENT(VCIN1_AC_IN)

tPCH34_Max : 20 ms

tPCH02_Min : 10 ms

CH03_Min : 10 ms

tPLT02_Min : 0 ms Max : 90 ms

ON/OFF#

TN_OUT#

C C

PM_SLP_S5#

nimum duration of PWRBTN# assertion = 16mS. PWRBTN# can assert before or after RSMRST#

PM_SLP_S4#

SYSON

+1.0V_VCCST

+1.2V

PM_SLP_S3#

SUSP#

+1.0VS_VCCIO

+5VS / +3VS / +1.05VS

EC_VCCST_PG(VCCST_PWRGD)

VR_ON

DDR_VTT_PG_CTRL

B B

+0.675VS

tCPU04 Min : 100 ns

T4 = Min : 20ms Max : 30ms(EC Control)

tCPU19 Max : 100 ns

tCPU18 Max : 35 us

+VCCSA

tCPU10 Min : 1 ms

tCPU09 Min : 1 ms

+VCCCORE

+VCCGT

_PWRGD

PCH_PWROK

tCPU16 Min : 0 ns

H_CPUPWRGD

SYS_PWROK

SOC_PLTRST#(PCIRST#)

+1.8V_PRIM

+1.0V_PRIM

SUSACK#

PCH_DPWROK

EC_RSMRST#

AC_PRESENT

ON/OFF

TN_OUT#

PM_SLP_S5#

PM_SLP_S4#

SYSON

+1.0V_VCCST/+1.0V_VCCSFR

+1.35V_VDDQ/+1.35V_VCCSFR_OC

PM_SLP_S3#

SUSP#

.0VS_VCCIO

+5VS/+3VS/+1.5VS/+1.05VS

EC_VCCST_PG

VR_ON

SM_PG_CTRL

.675VS_VTT

C_SA

CC_CORE

+VCC_GT

_PWRGD

PCH_PWROK

H_CPUPWRGD

SYS_PWROK

SOC_PLTRST#

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

2015/01/29 2016/01/29

Deciphered Date

Compal Electronics, Inc.

Title

tle

Power Sequence

Size

Date: Sheet

Power Sequence

Document Number Re

Document Number Rev

LA-D561P

4 66Thursday, June 15, 2017

0.1

M1-30 VRAM STRAP

Vendor

UV3, UV4, UV5, UV6

D D

X76H2G@

X7667538L03

X76M2G@

X7667538L04

X76S2G@

X7667538L05

HYNIX 4096Mbits SA000076P80 TEMP 256MX16 K4W4G1646E-BC1A TEMP

Micron 4096Mbits SA00009HF00 TEMP 256Mx16 MT41J256M16LY-091G:N TEMP

SAMSUNG 4096Mbits SA00008DN00 TEMP 256MX16 H5TC4G63CFR-N0C TEMP

2GBytes

0 0

_3[ 2 ]PS_3[ 3 ]

PS_3[ 1 ]PS

10 0

00 1

001 4.99K4.53K

X76@X76@

R_pu

RV22 RV27

NC 4.75K

8.45K 2K

4.53K 2K

R_pd

Power-Up/Down Sequence

"M1" has the following requirements with regards to power-supply sequencing to avoid damaging the ASIC:

All the ASIC supplies must reach their respective nominal voltages within 20ms

‧

of the start of the ramp-up sequence, though a shorter ramp-up duration is preferred. The maximum slew rate on all rails is 50 mV/μ s.

It is recommended that the 3.3-V rail ramp up frist.

‧

It is recommended that the 0.95-V rail reach at least 90% of its nominal value no later

‧

than 2ms from the start of VDDC ramping up.

‧

The power rails that are shared with other components on the system should be gated for the dGPU so that when dGPU is powered down (for example AMD PowerXpressTM idle state), all the power rails are removed from the dGPU. The gate circuits must meet the slew rate requirement (such as 50mV/us)

VDDC and VDD_CT should not ramp up simultaneously. For example, VDDC

‧

should reach 90% before VDD_CT starts to ramp up (or vice versa).

For power down, reversing the ramp-up sequence is recommended.

‧

≦

5 11 0 3.24K 5.62K

6 10K3.4K011

ZZZ

C C

X76H2G@

2G HYNIX

X7675138L04

ZZZ

X76M2G@

2G MICRON

X7675138L05

ZZZ

X76S2G@

2G SAMSUNG

X7675138L06

VDDR3(+3VGS)

PCIE_VDDC(+0.95VGS)

VDD_CT(+1.8VGS)

VDDR1(+1.35VGS)

VDDC/VDDCI(+VGA_CORE)

DGPU_PWROK

PERSTb

REFCLK

Straps Reset

B B

Straps Valid

Global ASIC Reset

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/01/07 2016/01/07

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

Date: Sheet

Compal Electronics, Inc.

VGA Notes List

Document Number Rev

Document Number R ev

VGA Notes List LA-D562P

LA-D562P

5 66Thursday, June 15, 2017

0.1

1 1

DDI

SPLAY SIDEBANDS

SKL-U

1 OF 20

EDP

Rev_1.0

EDP_TXN[0]

EDP_TXP[0]

EDP_TXN[1]

EDP_TXP[1]

EDP_TXN[2]

EDP_TXP[2]

EDP_TXN[3]

EDP_TXP[3]

EDP_AUXN EDP_AUXP

EDP_DISP_UTIL

DDI1_AUXN DDI1_AUXP DDI2_AUXN DDI2_AUXP

RSVD RSVD

GPP_E13/DDPB_HPD0 GPP_E14/DDPC_HPD1 GPP_E15/DDPD_HPD2 GPP_E16/DDPE_HPD3

GPP_E17/EDP_HPD

EDP_BKLTEN

EDP_BKLTCTL

EDP_VDDEN

C47 C46 D46 C45 A45 B45 A47 B47

E45 F45

B52 G50

F50 E48 F48 G46 F46

L9 L7 L6 N9 L10

R12 R11 U13

EDP_TXN0 [28] EDP_TXP0 [28] EDP_TXN1 [28] EDP_TXP1 [28]

EDP_AUXN [28] EDP_AUXP [28]

DDIP2_AUXN [38] DDIP2_AUXP [38]

TMDS_B_HPD [29] DDIP2_HPD [38]

EC_SCI# [10,45] EDP_HPD [28]

ENBKL [45] INVPWM [28] PCH_ENVDD [28]

From HDMI From DP

From eDP

<eDP>

UC1A

HDMI_TX2-_CK[29] HDMI_TX2+_CK[29] HDMI_TX1-_CK[29]

HDMI

DP MUX (Type-C/VGA)

HDMI DDC

DP MUX DDC

2 2

+1.0VS_VCCIO

     ! "

EDP_COMP

1 2

RC1 24.9_0402_1%

HDMI_TX1+_CK[29] HDMI_TX0-_CK[29] HDMI_TX0+_CK[29] HDMI_CLK-_CK[29] HDMI_CLK+_CK[29]

DDI2_TX0-_CK[38] DDI2_TX0+_CK[38] DDI2_TX1-_CK[38] DDI2_TX1+_CK[38] DDI2_TX2-_CK[38] DDI2_TX2+_CK[38] DDI2_TX3-_CK[38] DDI2_TX3+_CK[38]

HDMICLK_NB[29] HDMIDAT_NB[29]

DDIP2_CTRLCLK[38] DDIP2_CTRLDATA[38]

EDP_COMP

E55

DDI1_TXN[0]

F55

DDI1_TXP[0]

E58

DDI1_TXN[1]

F58

DDI1_TXP[1]

F53

DDI1_TXN[2]

G53

DDI1_TXP[2]

F56

DDI1_TXN[3]

G56

DDI1_TXP[3]

C50

DDI2_TXN[0]

D50

DDI2_TXP[0]

C52

DDI2_TXN[1]

D52

DDI2_TXP[1]

A50

DDI2_TXN[2]

B50

DDI2_TXP[2]

D51

DDI2_TXN[3]

C51

DDI2_TXP[3]

L13

GPP_E18/DDPB_CTRLCLK

L12

GPP_E19/DDPB_CTRLDATA

GPP_E20/DDPC_CTRLCLK

GPP_E21/DDPC_CTRLDATA

N11

GPP_E22

N12

GPP_E23

E52

EDP_RCOMP

SKL-U_BGA1356

 

+1.0VS_VCCIO

RC2 1K_0402_5%

H_PROCHOT#_R

H_PROCHOT#[45]

3 3

1 2

RC3 499_0402_1%

+1.0V_VCCST

1 2

RC7 1K_0402_5%

H_THERMTRIP#

H_PECI[45]

RC10 49.9_0402_1% RC11 49.9_0402_1% RC12 49.9_0402_1% RC14 49.9_0402_1%

H_PECI H_PROCHOT#_R H_THERMTRIP#

12 12 12 12

T1 TP@

T2 TP@ T3 TP@

T4 TP@ T5 TP@ T6 TP@

T7 TP@

T8 TP@

SOC_CATERR#

SOC_OCC# XDP_BPM#0

XDP_BPM#1 XDP_BPM#2 XDP_BPM#3

SOC_GPIOE3

SOC_GPIOB4

CPU_POPIRCOMP PCH_OPIRCOMP EDRAM_OPIO_RCOMP EOPIO_RCOMP

AT16 AU16

D63 A54 C65 C63 A65

C55 D55 B54 C56

A7 BA5 AY5

H66 H65

UC1D

SKL-U_BGA1356

CATERR# PECI PROCHOT# THERMTRIP# SKTOCC#

BPM#[0] BPM#[1] BPM#[2] BPM#[3]

GPP_E3/CPU_GP0 GPP_E7/CPU_GP1 GPP_B3/CPU_GP2 GPP_B4/CPU_GP3

PROC_POPIRCOMP PCH_OPIRCOMP OPCE_RCOMP OPC_RCOMP

CPU MISC

SKL-U

4 OF 20

JTAG

PROC_TCK

PROC_TDI PROC_TDO PROC_TMS

PROC_TRST#

PCH_JTAG_TCK

PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS

PCH_TRST#

Rev_1.0

JTAGX

B61 D60 A61 C60 B59

B56 D59 A56 C59 C61 A59

CPU_XDP_TCK0 SOC_XDP_TDI SOC_XDP_TDO SOC_XDP_TMS SOC_XDP_TRST#

PCH_JTAG_TCK1 SOC_XDP_TDI

SOC_XDP_TDO SOC_XDP_TMS PCH_XDP_TRST# CPU_XDP_TCK0

T9 TP@

#!$!%&"

SOC_XDP_TMS SOC_XDP_TDI SOC_XDP_TDO

CPU_XDP_TCK0 PCH_JTAG_TCK1

SOC_XDP_TRST#

RC4 51_0402_5%@ RC5 51_0402_5%@ RC6 51_0402_5%@

RC8 51_0402_5%@ RC9 51_0402_5%@

RC13 51_0402_5%

+1.0VS_VCCIO

1 2 1 2 1 2

1 2 1 2

1 2

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/05/19 2015/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

Date: Sheet

Compal Electronics, Inc.

SKL-U(1/12)DDI,EDP,MISC,CMC

Document Number Re

Custom

LA-D562P

6 66Thursday, June 15, 2017

0.1

'()

D D

DDR_A_D[0..15][18]

DDR_A_D[16..31][18]

C C

DDR_A_D[32..47][18]

DDR_A_D[48..63][18]

B B

UC1B

DDR_A_D0

AL71

DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15

DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

DDR0_DQ[0]

AL68

DDR0_DQ[1]

AN68

DDR0_DQ[2]

AN69

DDR0_DQ[3]

AL70

DDR0_DQ[4]

AL69

DDR0_DQ[5]

AN70

DDR0_DQ[6]

AN71

DDR0_DQ[7]

AR70

DDR0_DQ[8]

AR68

DDR0_DQ[9]

AU71

DDR0_DQ[10]

AU68

DDR0_DQ[11]

AR71

DDR0_DQ[12]

AR69

DDR0_DQ[13]

AU70

DDR0_DQ[14]

AU69

DDR0_DQ[15]

Interleave / Non-Interleaved

BB65

DDR0_DQ[16]/DDR0_DQ[32]

AW65

DDR0_DQ[17]/DDR0_DQ[33]

AW63

DDR0_DQ[18]/DDR0_DQ[34]

AY63

DDR0_DQ[19]/DDR0_DQ[35]

BA65

DDR0_DQ[20]/DDR0_DQ[36]

AY65

DDR0_DQ[21]/DDR0_DQ[37]

BA63

DDR0_DQ[22]/DDR0_DQ[38]

BB63

DDR0_DQ[23]/DDR0_DQ[39]

BA61

DDR0_DQ[24]/DDR0_DQ[40]

AW61

DDR0_DQ[25]/DDR0_DQ[41]

BB59

DDR0_DQ[26]/DDR0_DQ[42]

AW59

DDR0_DQ[27]/DDR0_DQ[43]

BB61

DDR0_DQ[28]/DDR0_DQ[44]

AY61

DDR0_DQ[29]/DDR0_DQ[45]

BA59

DDR0_DQ[30]/DDR0_DQ[46]

AY59

DDR0_DQ[31]/DDR0_DQ[47]

AY39

DDR0_DQ[32]/DDR1_DQ[0]

AW39

DDR0_DQ[33]/DDR1_DQ[1]

AY37

DDR0_DQ[34]/DDR1_DQ[2]

AW37

DDR0_DQ[35]/DDR1_DQ[3]

BB39

DDR0_DQ[36]/DDR1_DQ[4]

BA39

DDR0_DQ[37]/DDR1_DQ[5]

BA37

DDR0_DQ[38]/DDR1_DQ[6]

BB37

DDR0_DQ[39]/DDR1_DQ[7]

AY35

DDR0_DQ[40]/DDR1_DQ[8]

AW35

DDR0_DQ[41]/DDR1_DQ[9]

AY33

DDR0_DQ[42]/DDR1_DQ[10]

AW33

DDR0_DQ[43]/DDR1_DQ[11]

BB35

DDR0_DQ[44]/DDR1_DQ[12]

BA35

DDR0_DQ[45]/DDR1_DQ[13]

BA33

DDR0_DQ[46]/DDR1_DQ[14]

BB33

DDR0_DQ[47]/DDR1_DQ[15]

AY31

DDR0_DQ[48]/DDR1_DQ[32]

AW31

DDR0_DQ[49]/DDR1_DQ[33]

AY29

DDR0_DQ[50]/DDR1_DQ[34]

AW29

DDR0_DQ[51]/DDR1_DQ[35]

BB31

DDR0_DQ[52]/DDR1_DQ[36]

BA31

DDR0_DQ[53]/DDR1_DQ[37]

BA29

DDR0_DQ[54]/DDR1_DQ[38]

BB29

DDR0_DQ[55]/DDR1_DQ[39]

AY27

DDR0_DQ[56]/DDR1_DQ[40]

AW27

DDR0_DQ[57]/DDR1_DQ[41]

AY25

DDR0_DQ[58]/DDR1_DQ[42]

AW25

DDR0_DQ[59]/DDR1_DQ[43]

BB27

DDR0_DQ[60]/DDR1_DQ[44]

BA27

DDR0_DQ[61]/DDR1_DQ[45]

BA25

DDR0_DQ[62]/DDR1_DQ[46]

BB25

DDR0_DQ[63]/DDR1_DQ[47]

SKL-U_BGA1356

 *!+,"

DDR_VTT_CNTL to DDR

TT supplied ramped

V <35u S (tCPU 18)

DDR_PG_CTRL

NC1VCC

GND

74AUP1G07GW_TSSOP5

SA00007WE00

SKL-U

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]

DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]

DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]

DDR0_DQSN[2]/DDR0_DQSN[4]

DDR0_DQSP[2]/DDR0_DQSP[4]

DDR0_DQSN[3]/DDR0_DQSN[5]

DDR0_DQSP[3]/DDR0_DQSP[5]

DDR0_DQSN[4]/DDR1_DQSN[0]

DDR0_DQSP[4]/DDR1_DQSP[0]

DDR0_DQSN[5]/DDR1_DQSN[1]

DDR0_DQSP[5]/DDR1_DQSP[1]

DDR0_DQSN[6]/DDR1_DQSN[4]

DDR0_DQSP[6]/DDR1_DQSP[4]

DDR0_DQSN[7]/DDR1_DQSN[5]

DDR0_DQSP[7]/DDR1_DQSP[5]

DDR CH - A

2 OF 20

CC1

0.1U_0201_10V6K

UC8

DDR0_CKN[0] DDR0_CKP[0] DDR0_CKN[1] DDR0_CKP[1]

DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3]

DDR0_CS#[0] DDR0_CS#[1] DDR0_ODT[0] DDR0_ODT[1]

DDR3L / LPDDR3 / DDR4

DDR0_MA[3]

DDR0_MA[4] DDR0_DQSN[0] DDR0_DQSP[0] DDR0_DQSN[1] DDR0_DQSP[1]

Interleave / Non-Interleaved

DDR0_ALERT#

DDR0_PAR

DDR_VREF_CA

DDR0_VREF_DQ DDR1_VREF_DQ

DDR_VTT_CNTL

+3VS+1.2V +3VALW

CRB ORB

RC19

220K_0402_5%

ev_1.0

RC20 100K_0402_5%

AU53 AT53 AU55 AT55

BA56 BB56 AW56 AY56

AU45 AU43 AT45 AT43

BA51 BB54 BA52 AY52 AW52 AY55 AW54 BA54 BA55 AY54 AU46 AU48 AT46 AU50 AU52 AY51 AT48 AT50 BB50 AY50

BA50 BB52 AM70 AM69 AT69 AT70

BA64 AY64 AY60 BA60 BA38 AY38 AY34 BA34 BA30 AY30 AY26 BA26

AW50 AT52

AY67 AY68 BA67

AW67

DDR_A_CLK#0 DDR_A_CLK0 DDR_A_CLK#1 DDR_A_CLK1

DDR_A_CKE0 DDR_A_CKE1

DDR_A_CS#0 DDR_A_CS#1 DDR_A_ODT0 DDR_A_ODT1

DDR_A_MA5 DDR_A_MA9 DDR_A_MA6 DDR_A_MA8 DDR_A_MA7 DDR_A_BG0 DDR_A_MA12 DDR_A_MA11 M_A_ACT# DDR_A_BG1 DDR_A_MA13 DDR_A_MA15 DDR_A_MA14 DDR_A_MA16 DDR_A_BA0 DDR_A_MA2 DDR_A_BA1 DDR_A_MA10 DDR_A_MA1 DDR_A_MA0

DDR_A_MA3 DDR_A_MA4 DDR_A_DQS#0 DDR_A_DQS0 DDR_A_DQS#1 DDR_A_DQS1

DDR_A_DQS#2 DDR_A_DQS2 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_DQS#4 DDR_A_DQS4 DDR_A_DQS#5 DDR_A_DQS5 DDR_A_DQS#6 DDR_A_DQS6 DDR_A_DQS#7 DDR_A_DQS7

+0.6V_VREFCA +0.6V_B_VREFDQ DDR_PG_CTRL

DDR_VTT_PG_CTRL [54]

DDR_A_CLK#0 [18] DDR_A_CLK0 [18]

T10@ T13@

DDR_A_CKE0 [18,20]

T11@

DDR_A_CS#0 [18,20]

T14@

DDR_A_ODT0 [18,20]

T12@

DDR_A_MA5 [18,20] DDR_A_MA9 [18,20] DDR_A_MA6 [18,20] DDR_A_MA8 [18,20] DDR_A_MA7 [18,20] DDR_A_BG0 [18,20] DDR_A_MA12 [18,20] DDR_A_MA11 [18,20] M_A_ACT# [18,20] DDR_A_BG1 [18] DDR_A_MA13 [18,20] DDR_A_MA15 [18,20] DDR_A_MA14 [18,20] DDR_A_MA16 [18,20] DDR_A_BA0 [18,20] DDR_A_MA2 [18,20] DDR_A_BA1 [18,20] DDR_A_MA10 [18,20] DDR_A_MA1 [18,20] DDR_A_MA0 [18,20]

DDR_A_MA3 [18,20] DDR_A_MA4 [18,20] DDR_A_DQS#0 [18] DDR_A_DQS0 [18] DDR_A_DQS#1 [18] DDR_A_DQS1 [18]

DDR_A_DQS#2 [18] DDR_A_DQS2 [18] DDR_A_DQS#3 [18] DDR_A_DQS3 [18] DDR_A_DQS#4 [18] DDR_A_DQS4 [18] DDR_A_DQS#5 [18] DDR_A_DQS5 [18] DDR_A_DQS#6 [18] DDR_A_DQS6 [18] DDR_A_DQS#7 [18] DDR_A_DQS7 [18]

DDR_A_ALERT# [18] DDR_A_PARITY [18,20]

+0.6V_VREFCA [18]

T16@

+0.6V_B_VREFDQ [19]

DDR_B_D[0..15][19]

DDR_B_D[16..31][19]

DDR_B_D[32..47][19]

DDR_B_D[48..63][19]

Trace width/Spacing >= 20mils Place componment near SODIMM

#543016 PDG0.9 P.163 RC place near SODIMM

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47

DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

UC1C

Interleave / Non-Interleaved

AF65

DDR1_DQ[0]/DDR0_DQ[16]

AF64

DDR1_DQ[1]/DDR0_DQ[17]

AK65

DDR1_DQ[2]/DDR0_DQ[18]

AK64

DDR1_DQ[3]/DDR0_DQ[19]

AF66

DDR1_DQ[4]/DDR0_DQ[20]

AF67

DDR1_DQ[5]/DDR0_DQ[21]

AK67

DDR1_DQ[6]/DDR0_DQ[22]

AK66

DDR1_DQ[7]/DDR0_DQ[23]

AF70

DDR1_DQ[8]/DDR0_DQ[24]

AF68

DDR1_DQ[9]/DDR0_DQ[25]

AH71

DDR1_DQ[10]/DDR0_DQ[26]

AH68

DDR1_DQ[11]/DDR0_DQ[27]

AF71

DDR1_DQ[12]/DDR0_DQ[28]

AF69

DDR1_DQ[13]/DDR0_DQ[29]

AH70

DDR1_DQ[14]/DDR0_DQ[30]

AH69

DDR1_DQ[15]/DDR0_DQ[31]

AT66

DDR1_DQ[16]/DDR0_DQ[48]

AU66

DDR1_DQ[17]/DDR0_DQ[49]

AP65

DDR1_DQ[18]/DDR0_DQ[50]

AN65

DDR1_DQ[19]/DDR0_DQ[51]

AN66

DDR1_DQ[20]/DDR0_DQ[52]

AP66

DDR1_DQ[21]/DDR0_DQ[53]

AT65

DDR1_DQ[22]/DDR0_DQ[54]

AU65

DDR1_DQ[23]/DDR0_DQ[55]

AT61

DDR1_DQ[24]/DDR0_DQ[56]

AU61

DDR1_DQ[25]/DDR0_DQ[57]

AP60

DDR1_DQ[26]/DDR0_DQ[58]

AN60

DDR1_DQ[27]/DDR0_DQ[59]

AN61

DDR1_DQ[28]/DDR0_DQ[60]

AP61

DDR1_DQ[29]/DDR0_DQ[61]

AT60

DDR1_DQ[30]/DDR0_DQ[62]

AU60

DDR1_DQ[31]/DDR0_DQ[63]

AU40

DDR1_DQ[32]/DDR1_DQ[16]

AT40

DDR1_DQ[33]/DDR1_DQ[17]

AT37

DDR1_DQ[34]/DDR1_DQ[18]

AU37

DDR1_DQ[35]/DDR1_DQ[19]

AR40

DDR1_DQ[36]/DDR1_DQ[20]

AP40

DDR1_DQ[37]/DDR1_DQ[21]

AP37

DDR1_DQ[38]/DDR1_DQ[22]

AR37

DDR1_DQ[39]/DDR1_DQ[23]

AT33

DDR1_DQ[40]/DDR1_DQ[24]

AU33

DDR1_DQ[41]/DDR1_DQ[25]

AU30

DDR1_DQ[42]/DDR1_DQ[26]

AT30

DDR1_DQ[43]/DDR1_DQ[27]

AR33

DDR1_DQ[44]/DDR1_DQ[28]

AP33

DDR1_DQ[45]/DDR1_DQ[29]

AR30

DDR1_DQ[46]/DDR1_DQ[30]

AP30

DDR1_DQ[47]/DDR1_DQ[31]

AU27

DDR1_DQ[48]

AT27

DDR1_DQ[49]

AT25

DDR1_DQ[50]

AU25

DDR1_DQ[51]

AP27

DDR1_DQ[52]

AN27

DDR1_DQ[53]

AN25

DDR1_DQ[54]

AP25

DDR1_DQ[55]

AT22

DDR1_DQ[56]

AU22

DDR1_DQ[57]

AU21

DDR1_DQ[58]

AT21

DDR1_DQ[59]

AN22

DDR1_DQ[60]

AP22

DDR1_DQ[61]

AP21

DDR1_DQ[62]

AN21

DDR1_DQ[63]

SKL-U_BGA1356

SKL-U

DDR3L / LPDDR3 / DDR4

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]

DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]

DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]

DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]

Interleave / Non-Interleaved

DDR1_DQSN[0]/DDR0_DQSN[2] DDR1_DQSP[0]/DDR0_DQSP[2] DDR1_DQSN[1]/DDR0_DQSN[3] DDR1_DQSP[1]/DDR0_DQSP[3] DDR1_DQSN[2]/DDR0_DQSN[6] DDR1_DQSP[2]/DDR0_DQSP[6] DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQSP[3]/DDR0_DQSP[7] DDR1_DQSN[4]/DDR1_DQSN[2] DDR1_DQSP[4]/DDR1_DQSP[2] DDR1_DQSN[5]/DDR1_DQSN[3] DDR1_DQSP[5]/DDR1_DQSP[3]

DDR CH - B

3 OF 20

DDR1_CKN[0] DDR1_CKN[1] DDR1_CKP[0] DDR1_CKP[1]

DDR1_CKE[0] DDR1_CKE[1] DDR1_CKE[2] DDR1_CKE[3]

DDR1_CS#[0]

DDR1_CS#[1] DDR1_ODT[0] DDR1_ODT[1]

DDR1_MA[3] DDR1_MA[4]

DDR1_DQSN[6] DDR1_DQSP[6] DDR1_DQSN[7] DDR1_DQSP[7]

DDR1_ALERT#

DDR1_PAR DRAM_RESET# DDR_RCOMP[0] DDR_RCOMP[1] DDR_RCOMP[2]

ev_1.0

AN45 AN46 AP45 AP46

AN56 AP55 AN55 AP53

BB42 AY42 BA42 AW42

AY48 AP50 BA48 BB48 AP48 AP52 AN50 AN48 AN53 AN52 BA43 AY43 AY44 AW44 BB44 AY47 BA44 AW46 AY46 BA46

BB46 BA47

AH66 AH65 AG69 AG70 AR66 AR65 AR61 AR60 AT38 AR38 AT32 AR32

AR25 AR27 AR22 AR21 AN43 AP43 AT13 AR18 AT18 AU18

DDR_B_CLK#0 DDR_B_CLK#1 DDR_B_CLK0 DDR_B_CLK1

DDR_B_CKE0 DDR_B_CKE1

DDR_B_CS#0 DDR_B_CS#1 DDR_B_ODT0 DDR_B_ODT1

DDR_B_MA5 DDR_B_MA9 DDR_B_MA6 DDR_B_MA8 DDR_B_MA7 DDR_B_BG0 DDR_B_MA12 DDR_B_MA11 M_B_ACT# DDR_B_BG1 DDR_B_MA13 DDR_B_MA15 DDR_B_MA14 DDR_B_MA16 DDR_B_BA0 DDR_B_MA2 DDR_B_BA1 DDR_B_MA10 DDR_B_MA1 DDR_B_MA0

DDR_B_MA3 DDR_B_MA4

DDR_B_DQS#0 DDR_B_DQS0 DDR_B_DQS#1 DDR_B_DQS1 DDR_B_DQS#2 DDR_B_DQS2 DDR_B_DQS#3 DDR_B_DQS3 DDR_B_DQS#4 DDR_B_DQS4 DDR_B_DQS#5 DDR_B_DQS5

DDR_B_DQS#6 DDR_B_DQS6 DDR_B_DQS#7 DDR_B_DQS7 DDR_B_ALERT# DDR_B_PARITY DDR_DRAMRST#

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

#543016 PDG0.9 P.117 W=12-15 Space= 20/25 L=500mil

DDR_DRAMRST#

RC15 200_0402_1% RC16 80.6_0402_1% RC17 100_0402_1%

+1.2V

DDR_B_CLK#0 [19] DDR_B_CLK#1 [19] DDR_B_CLK0 [19] DDR_B_CLK1 [19]

DDR_B_CKE0 [19] DDR_B_CKE1 [19]

DDR_B_CS#0 [19] DDR_B_CS#1 [19] DDR_B_ODT0 [19] DDR_B_ODT1 [19]

DDR_B_MA5 [19] DDR_B_MA9 [19] DDR_B_MA6 [19] DDR_B_MA8 [19] DDR_B_MA7 [19] DDR_B_BG0 [19] DDR_B_MA12 [19] DDR_B_MA11 [19] M_B_ACT# [19] DDR_B_BG1 [19] DDR_B_MA13 [19] DDR_B_MA15 [19] DDR_B_MA14 [19] DDR_B_MA16 [19] DDR_B_BA0 [19] DDR_B_MA2 [19] DDR_B_BA1 [19] DDR_B_MA10 [19] DDR_B_MA1 [19] DDR_B_MA0 [19]

DDR_B_MA3 [19] DDR_B_MA4 [19]

DDR_B_DQS#0 [19] DDR_B_DQS0 [19] DDR_B_DQS#1 [19] DDR_B_DQS1 [19] DDR_B_DQS#2 [19] DDR_B_DQS2 [19] DDR_B_DQS#3 [19] DDR_B_DQS3 [19] DDR_B_DQS#4 [19] DDR_B_DQS4 [19] DDR_B_DQS#5 [19] DDR_B_DQS5 [19]

DDR_B_DQS#6 [19] DDR_B_DQS6 [19] DDR_B_DQS#7 [19] DDR_B_DQS7 [19] DDR_B_ALERT# [19] DDR_B_PARITY [19] DDR_DRAMRST# [18,19]

X76@

12 1 2 1 2

RC18 470_0402_5%

0606 : RC15 add X76@

!!!

- .  .

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/01/29 2016/01/29

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

SKL-U(2/12)DDR4

Size

Document Number R

Custom

Date: Sheet

Thursday, June 15, 2017

LA-D562P

0.1

SMBALERT# (Internal Pull Down): 0 = Disable Intel ME TLS function ==> Default 1 = Enable Intel ME TLS function

SKL-U

LPC

5 OF 20

'-*01"

UC9

/CS

DO(IO1)

/WP(IO2)

GND

W25Q64FVSSIQ_SO8

/HOLD(IO3)

UC9

16M@

16M ROM

SA00005VV20

8M@

VCC CLK

DI(IO0)

SMBUS, SMLINK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

GPP_B23/SML1ALERT#/PCHHOT#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

8 7 6 5

GPP_C7/SML1DATA

GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A10/CLKOUT_LPC1

+3VALW

CC2 0.1U_0201_10V6K

SOC_SPI_IO3_0_RSOC_SPI_SO_0_R SOC_SPI_CLK_0_R SOC_SPI_SI_0_R

Rev_1.0

GPP_C0/SMBCLK

GPP_C3/SML0CLK

GPP_C6/SML1CLK

GPP_A8/CLKRUN#

1 2

CC3 10P_0603_50V8-J

@EMI@

R7 R8 R10

R9 W2 W1

W3 V3 AM7

AY13 BA13 BB13 AY12 BA12 BA11

AW9 AY9 AW11

SOC_SMBCLK SOC_SMBDATA SOC_SMBALERT#

SOC_SML0CLK SOC_SML0DATA

SOC_SML0ALERT#

SOC_SML1CLK SOC_SML1DATA

SOC_SML1ALERT#

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

LPC_FRAME#

LPC_CLK0

RC24 22_0402_1%EMI@

LPC_CLK1

RC102 22_0402_1%EMI@

@RF@

CC95 33P_0402_50V8J

SOC_SMBCLK [19] SOC_SMBDATA [19]

T17TP@

T18TP@

SOC_SML1CLK [22,39,45,46] SOC_SML1DATA [22,39,45,46]

LPC_AD0 [27,45] LPC_AD1 [27,45] LPC_AD2 [27,45] LPC_AD3 [27,45]

LPC_FRAME# [27,45]

1 2 1 2

CLKRUN#

SOC_SML1ALERT#

SOC_SML0CLK SOC_SML0DATA

SOC_SMBCLK SOC_SMBDATA SOC_SML1DATA SOC_SML1CLK

CLKRUN#

RC26 150K_0402_5%@ RC27 499_0402_1% RC28 499_0402_1%

RC30 8.2K_0402_5%

Follow 543016_SKL_U_Y_PDG_0_9

AV2 AW3 AV3 AW2 AU4 AU3 AU2 AU1

AW13

AY11

M2 M3

J4 V1 V2

G3 G2 G1

UC1E

SKL-U_BGA1356

SPI - FLASH

SPI0_CLK SPI0_MISO SPI0_MOSI SPI0_IO2 SPI0_IO3 SPI0_CS0# SPI0_CS1# SPI0_CS2#

SPI - TOUCH

GPP_D1/SPI1_CLK GPP_D2/SPI1_MISO GPP_D3/SPI1_MOSI GPP_D21/SPI1_IO2 GPP_D22/SPI1_IO3 GPP_D0/SPI1_CS#

LINK

CL_CLK CL_DATA CL_RST#

GPP_A0/RCIN# GPP_A6/SERIRQ

D D

C C

+3VALW

1 2

RC21 10K_0402_5%

1 2

RC22 1K_0402_5%@

1 2

RC23 1K_0402_5%@

+1.8VS_3VS_PGPPA

1 2

RC25 8.2K_0402_5%

KB_RST#

SOC_SPI_IO2

SOC_SPI_IO3

SERIRQ

SOC_SPI_CLK SOC_SPI_SO SOC_SPI_SI SOC_SPI_IO2 SOC_SPI_IO3 SOC_SPI_CS#0

KB_RST#[45] SERIRQ[27,45]

KB_RST# SERIRQ

RPC1, RPC3 and RC30 are close to UC3

RPC1

SOC_SPI_IO2 SOC_SPI_SO SOC_SPI_SI



B B

EC_SPI_CS0#[45]

/

EC_SPI_MOSI[45] EC_SPI_CLK[45]

EC_SPI_MISO[45]

SOC_SPI_IO3

EC_SPI_CS0# SOC_SPI_CS#0 EC_SPI_MOSI SOC_SPI_SI_0_R EC_SPI_CLK SOC_SPI_CLK_0_R

+3VALW

RC110

1 8 2 7 3 6 4 5

33_0804_8P4R_5%

1 2

RC29 33_0402_5%EMI@

RPC3

1 8 2 7 3 6 4 5

33_0804_8P4R_5%

1 2

10K_0402_5%

EMI@

SOC_SPI_IO2_0_R SOC_SPI_SO_0_R SOC_SPI_SI_0_R SOC_SPI_IO3_0_R

SOC_SPI_CLK_0_RSOC_SPI_CLK

EMI@

SOC_SPI_SO_0_REC_SPI_MISO

SOC_SPI_CS#0

SOC_SPI_CS#0 SOC_SPI_IO2_0_R

SML0ALERT# (Internal Pull Down): eSPI or LPC 0 = LPC is selected for EC ==> Default 1 = eSPI is selected for EC

SMB

(Link to DDR)

SML1

(Link to EC,DGPU,CRT,APS,RTS5455)

CK_LPC_KBC [45] CK_LPC_TPM [27] CLKRUN# [45]

+3VS

12 1 2 1 2

RPC2

1 8 2 7 3 6 4 5

1K_0804_8P4R_5%

+1.8VS_3VS_PGPPA

1 2

For ENE auto load search code V12

A A

Security Classification

2014/05/19 2015/12/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/05/19 2015/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

Custom

Date: Sheet

Compal Electronics, Inc.

SKL-U(3/12)SPI,SMB,LPC,ESPI

Document Number Re

LA-D562P

8 66Thursday, June 15, 2017

0.1

2!3!'*"

RPC4

EMI@

HDA_BITCLK_AUDIO[35] HDA_SYNC_AUDIO[35] HDA_SDOUT_AUDIO[35]

D D

C C

HDA_RST_AUDIO#[35]

+3VS

RC32 2.2K_0402_5%

1 2

1 8 2 7 3 6 4 5

HDA_SPKR

SPKR (Internal Pull Down): TOP Swap Override

B B

0 = Disable TOP Swap mode. ==> Default 1 = Enable TOP Swap Mode.

HDA_BIT_CLK HDA_SYNC ME_EN HDA_RST#

33_0804_8P4R_5%

/%/*("

UC1G

HDA_SYNC[44] HDA_BIT_CLK[44]

ME_EN[44,45]

HDA_SDIN0[35]

HDA_RST#[44]

DDI_PRIORITY[38]

HDA_SPKR[35]

HDA_SYNC HDA_BIT_CLK ME_EN

HDA_RST#

DDI_PRIORITY

HDA_SPKR

BA22 AY22 BB22 BA21 AY21

AW22

AY20

AW20

AK7 AK6 AK9

AK10

AW5

A36 B36 C38 D38 C36 D36 A38 B38

C31 D31 C33 D33 A31 B31 A33 B33

A29 B29 C28 D28 A27 B27 C27 D27

H5 D7

D8 C8

AUDIO

HDA_SYNC/I2S0_SFRM HDA_BLK/I2S0_SCLK HDA_SDO/I2S0_TXD HDA_SDI0/I2S0_RXD HDA_SDI1/I2S1_RXD HDA_RST#/I2S1_SCLK GPP_D23/I2S_MCLK I2S1_SFRM I2S1_TXD

GPP_F1/I2S2_SFRM GPP_F0/I2S2_SCLK GPP_F2/I2S2_TXD GPP_F3/I2S2_RXD

GPP_D19/DMIC_CLK0 GPP_D20/DMIC_DATA0

GPP_D17/DMIC_CLK1 GPP_D18/DMIC_DATA1

GPP_B14/SPKR

SKL-U_BGA1356

UC1I

CSI-2

CSI2_DN0 CSI2_DP0 CSI2_DN1 CSI2_DP1 CSI2_DN2 CSI2_DP2 CSI2_DN3 CSI2_DP3

CSI2_DN4 CSI2_DP4 CSI2_DN5 CSI2_DP5 CSI2_DN6 CSI2_DP6 CSI2_DN7 CSI2_DP7

CSI2_DN8 CSI2_DP8 CSI2_DN9 CSI2_DP9 CSI2_DN10 CSI2_DP10 CSI2_DN11 CSI2_DP11

SKL-U_BGA1356

SKL-U

9 OF 20

GPP_A17/SD_PWR_EN#/ISH_GP7

7 OF 20

Rev_1.0

CSI2_CLKN0 CSI2_CLKP0 CSI2_CLKN1 CSI2_CLKP1 CSI2_CLKN2 CSI2_CLKP2 CSI2_CLKN3 CSI2_CLKP3

CSI2_COMP

GPP_D4/FLASHTRIG

EMMC

GPP_F13/EMMC_DATA0 GPP_F14/EMMC_DATA1 GPP_F15/EMMC_DATA2 GPP_F16/EMMC_DATA3 GPP_F17/EMMC_DATA4 GPP_F18/EMMC_DATA5 GPP_F19/EMMC_DATA6 GPP_F20/EMMC_DATA7

GPP_F21/EMMC_RCLK

GPP_F22/EMMC_CLK

GPP_F12/EMMC_CMD

EMMC_RCOMP

SDIO / SDXC

GPP_G0/SD_CMD GPP_G1/SD_DATA0 GPP_G2/SD_DATA1 GPP_G3/SD_DATA2 GPP_G4/SD_DATA3

GPP_G5/SD_CD# GPP_G6/SD_CLK

GPP_G7/SD_WP

GPP_A16/SD_1P8_SEL

C37 D37 C32 D32 C29 D29 B26 A26

E13

RC33 100_0402_1%@

AP2 AP1 AP3 AN3 AN1 AN2 AM4 AM1

AM2 AM3 AP4

AT1

RC34 200_0402_1%@

Rev_1.0

SD_RCOMP

GPP_F23

AB11 AB13 AB12 W12 W11 W10 W8 W7

BA9 BB9

AB7

AF13

RC31 200_0402_1%@

A A

Security Classification

2014/05/19 2015/12/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/05/19 2015/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

Custom

Date: Sheet

Compal Electronics, Inc.

SKL-U(4/12)HDA,EMMC,SDIO,CSI2

Document Number R

Thursday, June 15, 2017

LA-D562P

0.1

+3VS

RPC5

EC_SCI#

WLANCLK_REQ#

M2CLK_REQ#

LANCLK_REQ#

D D

RC36 10K_0402_5%UMA@

RC37 10K_0402_5%

+3VL_RTC

C C

+3VALW

10K_0804_8P4R_5%

1 2 1 2

GPUCLK_REQ#

DIS@

1 2

RC40 20K_0201_5%

1 2

CC6 1U_0402_6.3V6K

1 2

RC41 20K_0402_5%

1 2

CC7 1U_0402_6.3V6K

1 2

CLRP1 SHORT PADS

1 2

RC44 1M_0402_5%

RPC6

PCH_PWROK

EC_RSMRST#

LAN_WAKE#

SYS_RESET#

10K_0804_8P4R_5%

EC_SCI# [6,45]

SOC_SRTCRST#

SOC_RTCRST#

CLR CMOS

SM_INTRUDER#

RC42

1 2

0_0402_5%

/!

1 2

ESD@

CC11 100P_0402_50V8J

1 2

ESD@

CC12 100P_0402_50V8J

1 2

ESD@

CC13 100P_0402_50V8J

B B

1 2

RC107 10K_0402_5%

+3VALW

1 2

RC49 1K_0402_5%

SYS_RESET# EC_RSMRST# SYS_PWROK

SYS_PWROK

WAKE#

EC_RSMRST# PCH_DPWROK

Only For Power Sequence Debug

DGPU

LAN

NGFF WL+BT(KEY E)

M.2 PCIE SSD

EC_CLEAR_CMOS# [45]

1 2

RC47 0_0402_5%

0606 change

UC1J

CLK_PCIE_GPU#[21] CLK_PCIE_GPU[21]

GPUCLK_REQ#[22] CLK_PCIE_LAN#[36]

CLK_PCIE_LAN[36] LANCLK_REQ#[36]

CLK_PCIE_WLAN#[31] CLK_PCIE_WLAN[31] WLANCLK_REQ#[31]

CLK_PCIE_M2#[32] CLK_PCIE_M2[32] M2CLK_REQ#[32]

GPUCLK_REQ#

LANCLK_REQ#

WLANCLK_REQ#

M2CLK_REQ#

2 4-5&$ $  "

SOC_PLTRST# SYS_RESET#

EC_RSMRST#[45]

PCH_PWROK[45]

T21 TP@

SYS_PWROK[45]

T24 TP@

EC_RSMRST# H_CPUPWRGD

EC_VCCST_PG SYS_PWROK

PCH_PWROK PCH_DPWROK

SUSWARN#

WAKE# LAN_WAKE#

D42 C42

AR10

B42 A42 AT7

D41 C41 AT8

D40 C40

AT10

B40 A40 AU8

E40 E38 AU7

SOC_PLTRST#

TC7SH08FUF_SSOP5

UC1K

AN10

GPP_B13/PLTRST#

SYS_RESET#

AY17

RSMRST#

A68

PROCPWRGD

B65

VCCST_PWRGD

SYS_PWROK

BA20

PCH_PWROK

BB20

DSW_PWROK

AR13

GPP_A13/SUSWARN#/SUSPWRDNACK

AP11

GPP_A15/SUSACK#

BB15

WAKE#

AM15

GPD2/LAN_WAKE#

AW17

GPD11/LANPHYPC

AT15

GPD7/RSVD

SKL-U_BGA1356

CLKOUT_PCIE_N0 CLKOUT_PCIE_P0 GPP_B5/SRCCLKREQ0#

CLKOUT_PCIE_N1 CLKOUT_PCIE_P1 GPP_B6/SRCCLKREQ1#

CLKOUT_PCIE_N2 CLKOUT_PCIE_P2 GPP_B7/SRCCLKREQ2#

CLKOUT_PCIE_N3 CLKOUT_PCIE_P3 GPP_B8/SRCCLKREQ3#

CLKOUT_PCIE_N4 CLKOUT_PCIE_P4 GPP_B9/SRCCLKREQ4#

CLKOUT_PCIE_N5 CLKOUT_PCIE_P5 GPP_B10/SRCCLKREQ5#

SKL-U_BGA1356

RC43

1 2

0_0402_5%

+3VS

UC11

SYSTEM POWER MANAGEMENT

SKL-U

CLOCK SIGNALS

10 OF 20

RC46

100K_0402_5%

SKL-U

11 OF 20

PCIRST# [21,27,31,32,36,45]

CC8 100P_0402_50V8J

ESD@

GPP_B11/EXT_PWR_GATE#

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

GPD8/SUSCLK

XTAL24_IN

XTAL24_OUT

XCLK_BIASREF

RTCX1 RTCX2

SRTCRST#

RTCRST#

Rev_1.0

GPP_B12/SLP_S0#

GPD4/SLP_S3# GPD5/SLP_S4#

GPD10/SLP_S5#

SLP_SUS#

SLP_LAN#

GPD9/SLP_WLAN#

GPD6/SLP_A#

GPD3/PWRBTN#

GPD1/ACPRESENT

GPD0/BATLOW#

GPP_A11/PME#

INTRUDER#

GPP_B2/VRALERT#

Rev_1.0

AT11 AP15 BA16 AY16

AN15 AW15 BB17 AN16

BA15 AY15 AU13

AU11 AP16

AM10 AM11

F43 E43

BA17 E37

E35 E42 AM18

AM20 AN18

AM16

SOC_XTAL24_IN

SOC_XTAL24_OUT

SUSCLK SOC_XTAL24_IN

SOC_XTAL24_OUT XCLK_BIASREF SOC_RTCX1

SOC_RTCX2 SOC_SRTCRST#

SOC_RTCRST#

PM_SLP_S0# PM_SLP_S3# PM_SLP_S4# PM_SLP_S5#

SLP_WLAN# PM_SLP_A#

PBTN_OUT# AC_PRESENT PM_BATLOW#

SM_INTRUDER#

SOC_VRALERT#

1 2

RC101 33_0201_1%

EMI@

1 2

RC100 33_0201_1%

EMI@

24MHZ_18PF_XRCGB24M000F2P51R0

SUSCLK [31]

T19TP@

PM_SLP_S3# [45] PM_SLP_S4# [45,54]

T20TP@

T22TP@

T23TP@

1 2

RC48 0_0402_5%

YC1

U23@

SJ10000UJ00

CC4

27P_0402_50V8J

U23@

SE071270J80

SOC_XTAL24_IN_R

SOC_XTAL24_OUT_R

YC1 24MHZ_18PF_XRCGB24M000F2P51R0

CC4

27P_0402_50V8J

U22@

YC1 need to be replaced by

38.4MHz (30ohm ESR) XTAL for Cannonlake-U

XCLK_BIASREF

U22@

1 2

RC35 1M_0402_5%

SJ10000UJ00U22@

1 2 1 2

RC38 2.7K_0402_1% RC39 60.4_0402_1%

RC35 1M_0402_5%

U23@ SD028100480

CC5

27P_0402_50V8J

U22@

+1.0V_CLK5_F24NS

Follow 546765_2014WW48_Skylake_MOW_Rev_1_0 Stuff 2.7k ohm(RC35) PU for Skylake-U Stuff 60.4 ohm(RC110) PD for Cannonlake-U

SOC_RTCX2

SOC_RTCX1

PBTN_OUT# [45]

AC_PRESENT_R [45]

PM_BATLOW#

SOC_VRALERT#

1 2

RC45 10M_0402_5%

YC2

1 2

32.768KHZ 9PF 20PPM 9H03280012

CC9

4.7P_0402_50V8B

1 2

RC50 8.2K_0402_5%

1 2

RC51 10K_0402_5%

CC10

4.7P_0402_50V8B

+3VALW

CC5 27P_0402_50V8J

U23@ SE071270J80

/6*0!7

A A

VCCST_PWRGD[45]

+1.0V_VCCST

RC52 1K_0402_5%

1 2

RC53 60.4_0402_1%

EC_VCCST_PG

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/05/19 2015/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

SKL-U(5/12)CLK,PM,GPIO

Size

Document Number Re

Custom

Date: Sheet

LA-D562P

10 66Thursday, June 15, 2017

0.1





 

RC55 10K_0402_5%

X76@

RC57 10K_0402_5%

X76@

OBRAM_ID2 OBRAM_ID0 OBRAM_ID1 GSPI0_MOSI

GSPI1_MOSI

WLBT_OFF# UART_2_CRXD_DTXDUART_2_CRXD_DTXD

UART_2_CTXD_DRXD

I2C1_SDA_TP I2C1_SCL_TP

*5-39'!





AM5 AN7 AP5 AN5

AB1 AB2

AB3 AD1

AD2 AD3 AD4

AH9

AH10 AH11

AH12 AF11

AF12

RC54 10K_0402_5%

X76@

RC56 10K_0402_5%

X76@

UC1F

AN8

GPP_B15/GSPI0_CS#

AP7

GPP_B16/GSPI0_CLK

AP8

GPP_B17/GSPI0_MISO

AR7

GPP_B18/GSPI0_MOSI GPP_B19/GSPI1_CS#

GPP_B20/GSPI1_CLK GPP_B21/GSPI1_MISO GPP_B22/GSPI1_MOSI

GPP_C8/UART0_RXD GPP_C9/UART0_TXD

GPP_C10/UART0_RTS# GPP_C11/UART0_CTS#

GPP_C20/UART2_RXD GPP_C21/UART2_TXD GPP_C22/UART2_RTS# GPP_C23/UART2_CTS#

GPP_C16/I2C0_SDA

GPP_C17/I2C0_SCL

GPP_C18/I2C1_SDA

GPP_C19/I2C1_SCL GPP_F4/I2C2_SDA

GPP_F5/I2C2_SCL GPP_F6/I2C3_SDA

GPP_F7/I2C3_SCL GPP_F8/I2C4_SDA

GPP_F9/I2C4_SCL

SKL-U_BGA1356

LPSS ISH

SKL-U

GPP_F10/I2C5_SDA/ISH_I2C2_SDA

GPP_F11/I2C5_SCL/ISH_I2C2_SCL

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_C15/UART1_CTS#/ISH_UART1_CTS#

Sx_EXIT_HOLDOFF# / GPP_A12 / BM_BUSY# / ISH_GP6

6 OF 20

GPP_D15/ISH_UART0_RTS#

Rev_1.0

GPP_D9 GPP_D10 GPP_D11 GPP_D12

GPP_D5/ISH_I2C0_SDA GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA GPP_D8/ISH_I2C1_SCL

GPP_A18/ISH_GP0 GPP_A19/ISH_GP1 GPP_A20/ISH_GP2 GPP_A21/ISH_GP3 GPP_A22/ISH_GP4 GPP_A23/ISH_GP5

P2 P3 P4 P1

M4 N3

N1 N2

AD11 AD12

U1 U2 U3 U4

DGPU_PWR_EN

AC1

DGPU_HOLD_RST#

AC2

DGPU_PWROK

AC3

DGPU_PRSNT#

AB4

AOU_STRAP

AY8

TPM_STRAP

BA8

TPM_STRAP2

BB7

APS_STRAP

BA7

PD_STRAP

AY7

ULTBY_STRAP

AW7 AP13

DGPU_PWR_EN [23,45,57,58] DGPU_HOLD_RST# [21] DGPU_PWROK [57,58]

RPC7

DGPU_HOLD_RST# DGPU_PWR_EN DGPU_PWROK DGPU_PRSNT#

DIS@ 1 8 2 7 3 6 4 5

10K_0804_8P4R_5%

DGPU_PRSNT# PD for DIS SKU

&  

3

!'

+3VS

RC62 10K_0402_5%UMA@

9





1 2

+3VS

DGPU_PRSNT#

-3(

2)







&

*5-39'!

*5-39'!

  



D D

GSPI0_MOSI (Internal Pull Down): No Reboot 0 = Disable No Reboot mode. ==> Default 1 = Enable No Reboot Mode. (PCH will disable the TCO

Timer system reboot feature). This function is useful when running ITP/XDP.

GSPI1_MOSI (Internal Pull Down):

Boot BIOS Strap Bit

= SPI Mode ==> Default

+3VS

C C

+3VS

0 1 = LPC Mode

1 2

RC58 2.2K_0402_5%

1 2

RC59 2.2K_0402_5%

1 2

RC103 10K_0402_5%

1 2

RC106 10K_0402_5%

1 2

RC60 49.9K_0402_1%

1 2

RC61 49.9K_0402_1%

1 2

R469 2.2K_0201_5%

1 2

R470 2.2K_0201_5%

UART_2_CTXD_DRXD

GSPI0_MOSI GSPI1_MOSI

WLBT_OFF#

DMIC_DET#

I2C1_SDA_TP I2C1_SCL_TP

+3VS +3VS +3VS

-(

RC105 10K_0402_5%

X76@

OBRAM_ID2 OBRAM_ID1 OBRAM_ID0

RC104 10K_0402_5%

X76@

TP_INT#[33]

DMIC_DET#[28]

WLBT_OFF#[31]

UART_2_CRXD_DTXD[31] UART_2_CTXD_DRXD[31]

I2C1_SDA_TP[33] I2C1_SCL_TP[33]

B B

&  

8931

3* 

:*:3*

AOU_STRAP

&  

4-353? 

:*4-353?

ULTBY_STRAP PD_STRAP

A A



893>



RC11210K_0402_5% AOU@

RC11110K_0402_5% NONAOU@

+3VS +3VS

RC11410K_0402_5% BATT2@

RC11310K_0402_5% NOBATT2@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

&  

3 

:*3

APS_STRAP

&  

!

:*!

93

+3VS+3VS



TPM_STRAP

TPM_STRAP2

893

RC10810K_0402_5% APS@

RC10910K_0402_5% NOAPS@





RC11610K_0402_5% TYPEC@

RC11510K_0402_5% NONTYPEC@

Compal Secret Data

2014/05/19 2015/12/31

Compal Secret Data

Deciphered Date

R3163

TCM@

10K_0402_5%

SD028100280

NOTPM@

TPM@

TCM@

NOTPM@

+3VS

R316310K_0402_5%

R316410K_0402_5%

+3VS

R3165

12 12

Title

Size

Custom

Date: Sheet

TPM@

10K_0402_5%

R316510K_0402_5%

SD028100280

R316610K_0402_5%

Compal Electronics, Inc.

SKL-U(6/12)GPIO,I2C,GSPI

Document Number R

&  

:*





LA-D562P

29;8 38 3<=

93-



93-









11 66Thursday, June 15, 2017

0.1

UC1H

D D

PCIE_CRX_GTX_N1[21] PCIE_CRX_GTX_P1[21]

PCIE_CTX_C_GRX_N1[21] PCIE_CTX_C_GRX_P1[21]

PCIE_CRX_GTX_N2[21]

PCIE_CRX_GTX_P2[21]

PCIE_CTX_C_GRX_N2[21]

dGPU

LAN

C C

M.2 WLAN

HDD

M.2 SATA/PCIE*4

B B

When PCIE8/SATA1A is used as SATA Port 1 (ODD), then PCIE11/SATA1B (M.2 SSD) cannot be used as SATA Port 1.

PCIE_CTX_C_GRX_P2[21] PCIE_CRX_GTX_N3[21]

PCIE_CRX_GTX_P3[21]

PCIE_CTX_C_GRX_N3[21]

PCIE_CTX_C_GRX_P3[21] PCIE_CRX_GTX_N4[21]

PCIE_CRX_GTX_P4[21]

PCIE_CTX_C_GRX_N4[21] PCIE_CTX_C_GRX_P4[21]

PCIE_CRX_DTX_N5[36] PCIE_CRX_DTX_P5[36]

PCIE_CTX_C_DRX_N5[36]

PCIE_CTX_C_DRX_P5[36]

PCIE_CRX_DTX_N6[31]

PCIE_CRX_DTX_P6[31] PCIE_CTX_DRX_N6[31] PCIE_CTX_DRX_P6[31]

SATA_CRX_DTX_N0[30] SATA_CRX_DTX_P0[30] SATA_CTX_DRX_N0[30] SATA_CTX_DRX_P0[30]

PCIE_CRX_DTX_N9[32] PCIE_CRX_DTX_P9[32] PCIE_CTX_DRX_N9[32] PCIE_CTX_DRX_P9[32]

PCIE_CRX_DTX_N10[32] PCIE_CRX_DTX_P10[32] PCIE_CTX_DRX_N10[32] PCIE_CTX_DRX_P10[32]

PCIE_CRX_DTX_N11[32]

PCIE_CRX_DTX_P11[32] PCIE_CTX_DRX_N11[32] PCIE_CTX_DRX_P11[32]

PCIE_CRX_DTX_N12[32]

PCIE_CRX_DTX_P12[32] PCIE_CTX_DRX_N12[32] PCIE_CTX_DRX_P12[32]

0222 change net name

1 2

CC18 0.22U_0402_6.3V6KDIS@

1 2

CC19 0.22U_0402_6.3V6KDIS@

1 2

CC14 0.22U_0402_6.3V6KDIS@

1 2

CC15 0.22U_0402_6.3V6KDIS@

1 2

CC16 0.22U_0402_6.3V6KDIS@

1 2

CC17 0.22U_0402_6.3V6KDIS@

1 2

CC20 0.22U_0402_6.3V6KDIS@

1 2

CC21 0.22U_0402_6.3V6KDIS@

1 2

CC22 0.1U_0201_10V6K

1 2

CC23 0.1U_0201_10V6K

1 2

RC66 100_0402_1%

T25 TP@ T26 TP@

PCIE_CRX_GTX_N1 PCIE_CRX_GTX_P1 PCIE_CTX_GRX_N1 PCIE_CTX_GRX_P1

PCIE_CRX_GTX_N2 PCIE_CRX_GTX_P2 PCIE_CTX_GRX_N2 PCIE_CTX_GRX_P2

PCIE_CRX_GTX_N3 PCIE_CRX_GTX_P3 PCIE_CTX_GRX_N3 PCIE_CTX_GRX_P3

PCIE_CRX_GTX_N4 PCIE_CRX_GTX_P4 PCIE_CTX_GRX_N4 PCIE_CTX_GRX_P4

PCIE_CRX_DTX_N5 PCIE_CRX_DTX_P5 PCIE_CTX_DRX_N5 PCIE_CTX_DRX_P5

PCIE_CRX_DTX_N6 PCIE_CRX_DTX_P6 PCIE_CTX_DRX_N6 PCIE_CTX_DRX_P6

PCIE_RCOMPN PCIE_RCOMPP

XDP_PRDY# XDP_PREQ#

PCIE / USB3 / SATA

H13

PCIE1_RXN/USB3_5_RXN

G13

PCIE1_RXP/USB3_5_RXP

B17

PCIE1_TXN/USB3_5_TXN

A17

PCIE1_TXP/USB3_5_TXP

G11

PCIE2_RXN/USB3_6_RXN

F11

PCIE2_RXP/USB3_6_RXP

D16

PCIE2_TXN/USB3_6_TXN

C16

PCIE2_TXP/USB3_6_TXP

H16

PCIE3_RXN

G16

PCIE3_RXP

D17

PCIE3_TXN

C17

PCIE3_TXP

G15

PCIE4_RXN

F15

PCIE4_RXP

B19

PCIE4_TXN

A19

PCIE4_TXP

F16

PCIE5_RXN

E16

PCIE5_RXP

C19

PCIE5_TXN

D19

PCIE5_TXP

G18

PCIE6_RXN

F18

PCIE6_RXP

D20

PCIE6_TXN

C20

PCIE6_TXP

F20

PCIE7_RXN/SATA0_RXN

E20

PCIE7_RXP/SATA0_RXP

B21

PCIE7_TXN/SATA0_TXN

A21

PCIE7_TXP/SATA0_TXP

G21

PCIE8_RXN/SATA1A_RXN

F21

PCIE8_RXP/SATA1A_RXP

D21

PCIE8_TXN/SATA1A_TXN

C21

PCIE8_TXP/SATA1A_TXP

E22

PCIE9_RXN

E23

PCIE9_RXP

B23

PCIE9_TXN

A23

PCIE9_TXP

F25

PCIE10_RXN

E25

PCIE10_RXP

D23

PCIE10_TXN

C23

PCIE10_TXP

PCIE_RCOMPN

PCIE_RCOMPP

D56

PROC_PRDY#

D61

PROC_PREQ#

BB11

GPP_A7/PIRQA#

E28

PCIE11_RXN/SATA1B_RXN

E27

PCIE11_RXP/SATA1B_RXP

D24

PCIE11_TXN/SATA1B_TXN

C24

PCIE11_TXP/SATA1B_TXP

E30

PCIE12_RXN/SATA2_RXN

F30

PCIE12_RXP/SATA2_RXP

A25

PCIE12_TXN/SATA2_TXN

B25

PCIE12_TXP/SATA2_TXP

SKL-U_BGA1356

SKL-U

8 OF 20

SSIC / USB3

USB3_2_RXN / SSIC_RXN USB3_2_RXP / SSIC_RXP

USB3_2_TXN / SSIC_TXN USB3_2_TXP / SSIC_TXP

USB2

USB2_VBUSSENSE

GPP_E9/USB2_OC0# GPP_E10/USB2_OC1# GPP_E11/USB2_OC2# GPP_E12/USB2_OC3#

GPP_E4/DEVSLP0 GPP_E5/DEVSLP1 GPP_E6/DEVSLP2

GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2

GPP_E8/SATALED#

Rev_1.0

USB3_1_RXN USB3_1_RXP USB3_1_TXN USB3_1_TXP

USB3_3_RXN USB3_3_RXP USB3_3_TXN USB3_3_TXP

USB3_4_RXN USB3_4_RXP USB3_4_TXN USB3_4_TXP

USB2N_1

USB2P_1

USB2N_2

USB2P_2

USB2N_3

USB2P_3

USB2N_4

USB2P_4

USB2N_5

USB2P_5

USB2N_6

USB2P_6

USB2N_7

USB2P_7

USB2N_8

USB2P_8

USB2N_9

USB2P_9

USB2N_10 USB2P_10

USB2_COMP

USB2_ID

H8 G8 C13 D13

J6 H6 B13 A13

J10 H10 B15 A15

E10 F10 C15 D15

USB20_N1

AB9

USB20_P1

AB10

USB20_N2

AD6

USB20_P2

AD7

USB20_N3

AH3

USB20_P3

AJ3

USB20_N4

AD9

USB20_P4

AD10

USB20_N5

AJ1

USB20_P5

AJ2

USB20_N6

AF6

USB20_P6

AF7

USB20_N7

AH1

USB20_P7

AH2

USB20_N8

AF8

USB20_P8

AF9

USB20_N9

AG1

USB20_P9

AG2 AH7

AH8

USB2_COMP

AB6

USB2_ID

AG3

USB2_VBUSSENSE

AG4

USB_OC0#

USB_OC1#

USB_OC2#

USB_OC3#

B9 J1

J2 J3

H2 H3 G4

PCH_SATALED#

USB3_RX_N1 [34]

USB3_RX_P1 [34]

USB3_TX_N1 [34]

USB3_TX_P1 [34]

USB3_RX_N2 [34]

USB3_RX_P2 [34]

USB3_TX_N2 [34]

USB3_TX_P2 [34]

USB3_RX_N3 [42]

USB3_RX_P3 [42]

USB3_TX_N3 [42]

USB3_TX_P3 [42]

USB3_RX_N4 [40]

USB3_RX_P4 [40]

USB3_TX_N4 [40]

USB3_TX_P4 [40]

USB20_N1 [34] USB20_P1 [34]

USB20_N2 [34] USB20_P2 [34]

USB20_N3 [43] USB20_P3 [43]

USB20_N4 [41] USB20_P4 [41]

USB20_N5 [28] USB20_P5 [28]

USB20_N6 [31] USB20_P6 [31]

USB20_N7 [37] USB20_P7 [37]

USB20_N8 [33] USB20_P8 [33]

USB20_N9 [46] USB20_P9 [46]

1 2

RC64 113_0402_1%

1 2

RC65 1K_0402_5%

1 2

RC67 1K_0402_5%

USB_OC0# [34] USB_OC1# [34] USB_OC2# [46]

EC_WL_OFF# [31]

PCH_SATALED# [33]

USB3(AOU)

USB3(Type-A)

USB3(Type-C)

USB3(Type-C Full)

USB2(AOU)

USB2(Type-A) USB2(Type-C)

USB2(Type-C Full) Camera M.2 BT Card Reader Finger Print 2nd Battery

USB_OC2# USB_OC1# USB_OC0# USB_OC3#

+3VS

R235 10K_0402_5%

RPC8

10K_0804_8P4R_5%

SATA_GP2 [32]

+3VALW

18 27 36 45

+3VS

A A

Security Classification

2014/05/19 2015/12/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/05/19 2015/12/31

Compal Secret Data

Deciphered Date

Title

SKL-U(7/12)PCIE,USB,SATA

Size

Document Number Re

Document Number R

Custom

Date: Sheet

PCH_SATALED#

Compal Electronics, Inc.

1 2

RC68 10K_0402_5%

LA-D562P

0.1

12 66Thursday, June 15, 2017

+1.0VALW TO +1.0V_VCCST

D D

+5VALW +1.0V_VCCST+1.0VALW

RC69

SYSON[44,45,54]

C C

1 2

47K_0402_5%

EN_1.0V_VCCSTU

0.1U_0402_25V6 CC29

1U_0402_6.3V6K

CC24

CC25

I(Max) : 0.16 A(+1.0V_VCCST) RON(Max) : 25 mohm V drop : 0.004 V

UC12

VOUT

VIN

VOUT

VIN

1U_0402_6.3V6K

TPS22967DSGR_SON8_2X2

VBIAS

GND GND

Follow 543977_SKL_PDDG_Rev0_91 CC24 10PF ->22us(Spec:<= 65us)

+1.0VS_VCCIO

+1.0V_VCCST

7 8

5 9

10P_0402_50V8J

CC27

0.1U_0201_10V6K

CC26

+1.2V

AU23 AU28 AU35 AU42 BB23 BB32 BB41 BB47 BB51

AM40

A18 A22

AL23

K20 K21

SKL-U

UC1N

VDDQ_AU23 VDDQ_AU28 VDDQ_AU35 VDDQ_AU42 VDDQ_BB23 VDDQ_BB32 VDDQ_BB41 VDDQ_BB47 VDDQ_BB51

VDDQC VCCST VCCSTG_A22 VCCPLL_OC VCCPLL_K20

VCCPLL_K21

SKL-U_BGA1356

+1.0VS_VCCIO

CPU POWER 3 OF 4

14 OF 20

Rev_1.0

VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO

VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA

VCCIO_SENSE

VSSIO_SENSE

VSSSA_SENSE VCCSA_SENSE

AK28 AK30 AL30 AL42 AM28 AM30 AM42

AK23 AK25 G23 G25 G27 G28 J22 J23 J27 K23 K25 K27 K28 K30

AM23 AM22

H21 H20

VSSSA_SENSE VCCSA_SENSE

Trace Length Match < 25 mils

+VCCSA

VSSSA_SENSE [59] VCCSA_SENSE [59]

+1.0VALW TO +1.0VS_VCCIO

+5VALW

SUSP#[44,45,54,63]

B B

A A

SUSP#

1 2

RC72 0_0402_5%

+1.0VALW

0.1U_0201_10V6K

CC33

1U_0402_6.3V6K

CC34

+1.0VS_VCCIO

I(Max) : 3.04 A(+1.0VS_VCCIO) RON(Max) : 6.2 mohm V drop : 0.019 V

UC13

VIN1

VIN2

VIN thermal

VBIAS

CC39

10U_0603_6.3V6M

CC40

TPS22961DNYR_WSON8

1U_0402_6.3V6K

CC42

CC41

0.1U_0402_25V6

10P_0402_25V8J

VOUT

GND

CC96

RF@

+1.0VS_VCCIO_STG

+1.0VS_VCCIO

RC71

1 2

0_0805_5%

PSC SideBSC Side BSC SidePSC Side

1U_0402_6.3V6K

CC43

1U_0402_6.3V6K

CC44

CC46

CC45

Close to CPUUnderneath CPU

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

CC38

0.1U_0201_10V6K

+1.2V

BSC Side

1U_0402_6.3V6K

10U_0603_6.3V6M

CC47

22U_0603_6.3V6M

CC48

CC49

Close to CPUClose to AM40 Underneath CPUClose to AL23

Compal Secret Data

2014/05/19 2015/12/31

Compal Secret Data

Deciphered Date

+1.0V_VCCST

+1.0VS_VCCIO

BSC SidePSC Side

1U_0402_6.3V6K

CC35

CC36

1U_0402_6.3V6K

CC37

Close to A18 Close to K20 Close to A22

1U_0402_6.3V6K

22U_0603_6.3V6M

CC50

10U_0603_6.3V6M

CC51

10U_0603_6.3V6M

CC52

CC53

Title

Size

Custom

Date: Sheet

1U_0402_6.3V6K

CC54

Document Number R

CC55

Compal Electronics, Inc.

SKL-U(8/12)Power

LA-D562P

0.1

13 66Thursday, June 15, 2017

D D

C C

B B

Follow 543016_SKL_U_Y_PDG_1_0

+1.0VALW

LC1

MURATA BLM15EG221SN1D

1 2

SM01000HC00

RF@

R_0402

Follow 543016_SKL_U_Y_PDG_1_0

RC75

1 2

0_0603_5%

Follow 543016_SKL_U_Y_PDG_1_0

RC76

1 2

0_0603_5%

Follow 543016_SKL_U_Y_PDG_1_0

RC78

1 2

0_0603_5%

Follow 543016_SKL_U_Y_PDG_1_0

RC82

1 2

0_0603_5%

+1.0V_APLL

CC59

0.1U_0201_10V K X5R

RF@

+1.0V_AMPHYPLL

1U_0402_6.3V6K

22U_0603_6.3V6M

CC62

+1.0V_CLK5_F24NS

22U_0603_6.3V6M

+1.0V_CLK4_F100OC

22U_0603_6.3V6M

+1.0V_CLK6_24TBT

22U_0603_6.3V6M

1U_0402_6.3V6K

CC74

+1.0VALW

RC73

1 2

0_0805_5%

'BCD3

RC74

1 2

0_0805_5%

+3VALW

'B>C3

RC77

RF@

MURATA BLM15EG221SN1D

1 2

SM01000HC00

R_0402

LPC 3.3V

RC80

1 2

0_0402_5%

CC63

CC67

CC72

+1.0V_PRIM_CORE

+3.3V_HDA

0.1U_0201_10V K X5R

+3V_1.8V_PGPPA

+1.8VS_3VS_PGPPA

1U_0402_6.3V6K

CC60

+1.0V_MPHYGT

1U_0402_6.3V6K

22U_0603_6.3V6M

CC66

CC65

HD Audio : 3.3V or 1.5V

CC68

RF@

I2S : 1.8V or 3.3V

+3VALW

CC69

Close to AJ21

+1.0VALW

CC70

1U_0402_6.3V6K

Close to AF20 Close to N18

1 2

CC58 1U_0402_6.3V6K

+1.0V_PRIM_CORE

1 2

CC56 1U_0402_6.3V6K

1 2

CC57 1U_0402_6.3V6K

Close to K17

+1.0V_MPHYGT

+1.0V_AMPHYPLL

+1.0V_APLL

+3VALW

+3.3V_HDA

+3VALW

CC71

1U_0402_6.3V6K

Follow 543016_SKL_U_Y_PDG_1_0

CC75

+3VS

LPC 3.3V

RC84

1 2

0_0402_5%

+1.0VALW +3VALW +1.8VALW

22U_0603_6.3V6M

CC76

22U_0603_6.3V6M

CC77

22U_0603_6.3V6M

CC78

CC79

22U_0603_6.3V6M

CC80

+1.0VALW

1U_0402_6.3V6K

22U_0603_6.3V6M

CC81

DCPDSW

UC1O

AB19

VCCPRIM_1P0

AB20

VCCPRIM_1P0

P18

VCCPRIM_1P0

AF18

VCCPRIM_CORE

AF19

VCCPRIM_CORE

V20

VCCPRIM_CORE

V21

VCCPRIM_CORE

AL1

DCPDSW_1P0

K17

VCCMPHYAON_1P0

N15

VCCMPHYGT_1P0_N15

N16

VCCMPHYGT_1P0_N16

N17

VCCMPHYGT_1P0_N17

P15

VCCMPHYGT_1P0_P15

P16

VCCMPHYGT_1P0_P16

K15

VCCAMPHYPLL_1P0

L15

VCCAMPHYPLL_1P0

V15

VCCAPLL_1P0

AB17

VCCPRIM_1P0_AB17

Y18

VCCPRIM_1P0_Y18

AD17

VCCDSW_3P3_AD17

AD18

VCCDSW_3P3_AD18

AJ17

VCCDSW_3P3_AJ17

AJ19

VCCHDA

AJ16

VCCSPI

AF20

VCCSRAM_1P0

AF21

VCCSRAM_1P0

T19

VCCSRAM_1P0

T20

VCCSRAM_1P0

AJ21

VCCPRIM_3P3_AJ21

AK20

VCCPRIM_1P0_AK20

N18

VCCAPLLEBB_1P0

SKL-U_BGA1356

+3VALW

!DD D1$!!-)&$)

1U_0402_6.3V6K

CC82

SKL-U

CPU POWER 4 OF 4

15 OF 20

VCCPGPPA VCCPGPPB VCCPGPPC VCCPGPPD VCCPGPPE

VCCPGPPF

VCCPGPPG

VCCPRIM_3P3_V19

VCCPRIM_1P0_T1

VCCATS_1P8

VCCRTCPRIM_3P3

VCCRTC_AK19 VCCRTC_BB14

GPP_B0/CORE_VID0 GPP_B1/CORE_VID1

1U_0402_6.3V6K

CC83

Rev_1.0

DCPRTC VCCCLK1 VCCCLK2 VCCCLK3 VCCCLK4 VCCCLK5 VCCCLK6

0.1U_0201_10V6K

+1.8VALW

+3VALW

AK15 AG15 Y16 Y15 T16 AF16 AD15

V19 T1 AA1 AK17 AK19

BB14 BB10 A14 K19 L21 N20 L19 A10 AN11

AN13

DCPRTC

+3V_1.8V_PGPPA

VCCPGPPF support 1.8V only

+1.0VALW

1 2

CC61 1U_0402_6.3V6K

+3VL_RTC

1 2

CC64 0.1U_0201_10V6K

+1.0V_CLK6_24TBT

+1.0V_APLL +1.0V_CLK4_F100OC +1.0V_CLK5_F24NS +1.0V_CLK6_24TBT

- 5  )

+3VL_RTC +RTCBATT

W=20mils

1 2

RC81 0_0402_5%

CC73 1U_0402_6.3V6K

$ ) &    ( //   @  A- 

CC84

3@DE?E 38

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/05/19 2015/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

SKL-U(9/12)Power

Size

Document Number Re

Custom

Date: Sheet

LA-D562P

14 66Thursday, June 15, 2017

0.1

VCCGT_SENSE VSSGT_SENSE

+VCCGT +VCCGT+VCCCORE +VCCCORE

AA63 AA64 AA66 AA67 AA69 AA70 AA71 AC64 AC65 AC66 AC67 AC68 AC69 AC70 AC71

M62 N63 N64 N66 N67 N69

A48 A53 A58 A62 A66

J43 J45 J46 J48 J50 J52 J53 J55 J56 J58 J60 K48 K50 K52 K53 K55 K56 K58 K60 L62 L63 L64 L65 L66 L67 L68 L69 L70 L71

J70 J69

UC1M

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

VCCGT_SENSE VSSGT_SENSE

SKL-U_BGA1356

SKL-U

CPU POWER 2 OF 4

13 OF 20

Rev_1.0

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

VCCGTX_AK42 VCCGTX_AK43 VCCGTX_AK45 VCCGTX_AK46 VCCGTX_AK48 VCCGTX_AK50 VCCGTX_AK52 VCCGTX_AK53 VCCGTX_AK55 VCCGTX_AK56 VCCGTX_AK58 VCCGTX_AK60 VCCGTX_AK70

VCCGTX_AL43 VCCGTX_AL46 VCCGTX_AL50 VCCGTX_AL53 VCCGTX_AL56

VCCGTX_AL60 VCCGTX_AM48 VCCGTX_AM50 VCCGTX_AM52 VCCGTX_AM53 VCCGTX_AM56 VCCGTX_AM58 VCCGTX_AU58 VCCGTX_AU63 VCCGTX_BB57 VCCGTX_BB66

VCCGTX_SENSE VSSGTX_SENSE

N70 N71 R63 R64 R65 R66 R67 R68 R69 R70 R71 T62 U65 U68 U71 W63 W64 W65 W66 W67 W68 W69 W70 W71 Y62

AK42 AK43 AK45 AK46 AK48 AK50 AK52 AK53 AK55 AK56 AK58 AK60 AK70 AL43 AL46 AL50 AL53 AL56 AL60 AM48 AM50 AM52 AM53 AM56 AM58 AU58 AU63 BB57 BB66

AK62 AL61

1 2

SKL@

RC86 0_0402_5%

VCCGTX_SENSE VSSGTX_SENSE

For GT3 SKU

T29 TP@ T30 TP@

+VCCGT

UC1L

A30

VCC_A30

A34

VCC_A34

D D

+1.0VS_VCCOPC

+1.8VALW

U23@

VCCOPC_SENSE VSSOPC_SENSE

+1.8V_VCCOPC

1 2

For GT3 SKU

C C

RC85 0_0402_5%

VCCOPC_SENSE[63] VSSOPC_SENSE[63]

SVID ALERT

B B

A39

A44 AK33 AK35 AK37 AK38 AK40 AL33 AL37 AL40

AM32 AM33 AM35 AM37 AM38

G30

K32

AK32

AB62

P62

V62

H63

G61

AC63 AE63

AE62

AG62

AL63 AJ62

+1.0V_VCCST

RC88 56_0402_5%

VCC_A39 VCC_A44 VCC_AK33 VCC_AK35 VCC_AK37 VCC_AK38 VCC_AK40 VCC_AL33 VCC_AL37 VCC_AL40 VCC_AM32 VCC_AM33 VCC_AM35 VCC_AM37 VCC_AM38 VCC_G30

RSVD RSVD VCCOPC_AB62

VCCOPC_P62 VCCOPC_V62

VCC_OPC_1P8_H63 VCC_OPC_1P8_G61 VCCOPC_SENSE

VSSOPC_SENSE VCCEOPIO

VCCEOPIO VCCEOPIO_SENSE

VSSEOPIO_SENSE

SKL-U_BGA1356

Place the PU resistors close to CPU

SKL-U

CPU POWER 1 OF 4

12 OF 20

Rev_1.0

VCC_G32 VCC_G33 VCC_G35 VCC_G37 VCC_G38 VCC_G40 VCC_G42 VCC_J30 VCC_J33 VCC_J37 VCC_J40 VCC_K33 VCC_K35 VCC_K37 VCC_K38 VCC_K40 VCC_K42 VCC_K43

VCC_SENSE VSS_SENSE

VIDALERT#

VIDSCK

VIDSOUT

VCCSTG_G20

G32 G33 G35 G37 G38 G40 G42 J30 J33 J37 J40 K33 K35 K37 K38 K40 K42 K43

E32 E33

B63 A63 D64

G20

Trace Length Match < 25 mils

VCCCORE_SENSE [59]

SOC_SVID_ALERT# VR_SVID_CLK VR_SVID_DATA

VSSCORE_SENSE [59]

VR_SVID_CLK [59]

ALERT signal must be routed between CLK and DATA signals

+1.0VS_VCCIO

0309 K52 and AK52 KEEP NC 563377_KBL_MOW_WW09_March_2017

------------------------SLK will connection add structure

VCCGT_SENSE[59] VSSGT_SENSE[59]

Trace Length Match < 25 mils

+VCC_GT_+VCC_CORE +VCC_GT_+VCC_CORE

+VCCGT

1 2

RC87 0_0402_5%SKL@

SOC_SVID_ALERT#

SVID DATA

VR_SVID_DATA

A A

1 2

RC89 220_0402_5%

+1.0V_VCCST

RC90 100_0402_5%

VR_ALERT# [59]

Place the PU resistors close to CPU

VR_SVID_DATA [59]

(To VR)

For CPU GT3 SKU

+1.0VS_VCCOPC

BSC Side BSC Side

10U_0603_6.3V6M

CC85

U23@

(To VR)

Close to AE62,AG62 Close to AB62,P62,V62

Security Classification

2014/05/19 2015/12/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/05/19 2015/12/31

Compal Secret Data

Deciphered Date

1U_0402_6.3V6K

10U_0603_6.3V6M

CC86

U23@

1U_0402_6.3V6K

10U_0603_6.3V6M

CC88

CC87

U23@

1U_0402_6.3V6K

CC89

U23@

Title

Size

Custom

Date: Sheet

CC91

CC90

U23@

Compal Electronics, Inc.

SKL-U(10/12)Power,SVID

Document Number R

LA-D562P

0.1

15 66Thursday, June 15, 2017

D D

C C

B B

A67 A70 AA2

AA4 AA65 AA68 AB15 AB16 AB18 AB21

AB8 AD13 AD16 AD19 AD20 AD21 AD62

AD8 AE64 AE65 AE66 AE67 AE68 AE69

AF1 AF10 AF15 AF17

AF2

AF4 AF63 AG16 AG17 AG18 AG19 AG20 AG21 AG71 AH13

AH6 AH63 AH64 AH67

AJ15 AJ18 AJ20

AK11 AK16 AK18 AK21 AK22 AK27 AK63 AK68 AK69

AK8

AL2

AL28 AL32 AL35 AL38

AL4

AL45 AL48 AL52 AL55 AL58 AL64

AJ4

UC1P

SKL-U_BGA1356

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SKL-U

GND 1 OF 3

16 OF 20

Rev_1.0

AL65 AL66 AM13 AM21 AM25 AM27 AM43 AM45 AM46 AM55 AM60 AM61 AM68 AM71 AM8 AN20 AN23 AN28 AN30 AN32 AN33 AN35 AN37 AN38 AN40 AN42 AN58 AN63 AP10 AP18 AP20 AP23 AP28 AP32 AP35 AP38 AP42 AP58 AP63 AP68 AP70 AR11 AR15 AR16 AR20 AR23 AR28 AR35 AR42 AR43 AR45 AR46 AR48 AR5 AR50 AR52 AR53 AR55 AR58 AR63 AR8 AT2 AT20 AT23 AT28 AT35 AT4 AT42 AT56 AT58

AT63 AT68

AT71 AU10 AU15 AU20 AU32 AU38

AV1 AV68 AV69 AV70 AV71

AW10 AW12 AW14 AW16 AW18 AW21 AW23 AW26 AW28 AW30 AW32 AW34 AW36 AW38 AW41 AW43 AW45 AW47 AW49 AW51 AW53 AW55 AW57

AW6 AW60 AW62 AW64 AW66

AW8

AY66

B10 B14 B18 B22 B30 B34 B39 B44 B48 B53 B58 B62 B66 B71

BA1 BA10 BA14 BA18

BA2 BA23 BA28 BA32 BA36

BA45

F68

UC1Q

SKL-U_BGA1356

SKL-U

GND 2 OF 3

17 OF 20

Rev_1.0

BA49 BA53 BA57 BA6 BA62 BA66 BA71 BB18 BB26 BB30 BB34 BB38 BB43 BB55 BB6 BB60 BB64 BB67 BB70 C1 C25 C5 D10 D11 D14 D18 D22 D25 D26 D30 D34 D39 D44 D45 D47 D48 D53 D58 D6 D62 D66 D69 E11 E15 E18 E21 E46 E50 E53 E56 E6 E65 E71 F1 F13 F2 F22 F23 F27 F28 F32 F33 F35 F37 F38 F4 F40 F42 BA41

UC1R

VSS

G10

VSS

G22

VSS

G43

VSS

G45

VSS

G48

VSS

G52

VSS

G55

VSS

G58

VSS

G60

VSS

G63

VSS

G66

VSS

H15

VSS

H18

VSS

H71

VSS

J11

VSS

J13

VSS

J25

VSS

J28

VSS

J32

VSS

J35

VSS

J38

VSS

J42

VSS

K16

VSS

K18

VSS

K22

VSS

K61

VSS

K63

VSS

K64

VSS

K65

VSS

K66

VSS

K67

VSS

K68

VSS

K70

VSS

K71

VSS

L11

VSS

L16

VSS

L17

VSS

SKL-U_BGA1356

SKL-U

GND 3 OF 3

18 OF 20

Rev_1.0

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

L18 L2 L20 L4 L8 N10 N13 N19 N21 N6 N65 N68 P17 P19 P20 P21 R13 R6 T15 T17 T18 T2 T21 T4 U10 U63 U64 U66 U67 U69 U70 V16 V17 V18 W13 W6 W9 Y17 Y19 Y20 Y21

A A

Security Classification

2014/05/19 2015/12/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/05/19 2015/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

Custom

Date: Sheet

SKL-U(11/12)GND

Document Number Re

LA-D562P

16 66Thursday, June 15, 2017

0.1

D D

T33 TP@ T34 TP@ T35 TP@ T36 TP@ T37 TP@ T38 TP@ T31 TP@ T39 TP@ T32 TP@ T40 TP@ T41 TP@ T42 TP@ T43 TP@ T44 TP@ T45 TP@ T46 TP@

T47 TP@ T48 TP@

T49 TP@

C C

B B

1 2

RC98 49.9_0402_1%

1 2

RC99 1K_0402_5%

CFG_RCOMP

T50 TP@

T51 TP@

CFG4

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15

CFG16 CFG17

CFG18 CFG19

CFG_RCOMP XDP_ITP_PMODE

Display Port Presence Strap

1 : Disabled; No Physical Display Port attached to Embedded Display Port

CFG4

A A

0 : Enabled; An external Display Port device is connected to the Embedded Display Port

E68 B67 D65 D67 E70 C68 D68 C67

G69 G68

H70 G71 H69 G70

E63

E66

E60

AY2 AY1

K46 K45

AL25 AL27

C71 B70

A52

BA70 BA68

G65

E61

F71 F70

F63

F66

D1 D3

F60

J71 J68

F65

F61

UC1S

CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15]

CFG[16] CFG[17]

CFG[18] CFG[19]

CFG_RCOMP ITP_PMODE RSVD_AY2

RSVD_AY1 RSVD_D1

RSVD_D3 RSVD_K46

RSVD_K45 RSVD_AL25

RSVD_AL27 RSVD_C71

RSVD_B70 RSVD_F60 RSVD_A52 RSVD_TP_BA70

RSVD_TP_BA68 RSVD_J71

RSVD_J68 VSS_F65

VSS_G65 RSVD_F61

RSVD_E61

SKL-U_BGA1356

SKL-U

RESERVED SIGNALS-1

19 OF 20

Rev_1.0

RSVD_TP_BB68 RSVD_TP_BB69

RSVD_TP_AK13 RSVD_TP_AK12

RSVD_BB2 RSVD_BA3

TP5 TP6

RSVD_D5 RSVD_D4

RSVD_B2

RSVD_C2

RSVD_B3 RSVD_A3

RSVD_AW1

RSVD_E1 RSVD_E2

RSVD_BA4 RSVD_BB4

RSVD_A4

RSVD_C4

TP4

RSVD_A69 RSVD_B69

RSVD_AY3 RSVD_D71

RSVD_C70 RSVD_C54

RSVD_D54

TP1 TP2

VSS_AY71

ZVM#

RSVD_TP RSVD_TP

MSM#

PROC_SELECT#

UC1T

RSVD_U12 RSVD_U11

AW69

RSVD_AW69

AW68

RSVD_AW68

AU56

RSVD_AU56

AW48

RSVD_AW48

RSVD_C7

U12

RSVD_U12

U11

RSVD_U11

H11

RSVD_H11

SKL-U_BGA1356

+1.0V_VCCST

BB68 BB69

AK13 AK12

BB2 BA3

AU5 AT5

D5 D4 B2 C2

B3 A3

AW1 E1

E2 BA4

BB4 A4

C4 BB5 A69

B69 AY3 D71

C70 C54

D54 AY4

BB3 AY71

AR56 AW71

AW70 AP56

C64

LPM_ZVM#

PM_MSM# SKL_CNL#

T52 TP@

RC97 100K_0402_5%

42E_SOC_XTAL24_OUT_R

LPM_ZVM# [63]

1 2

Follow 544669_SKL_U_DDR3L_RVP7_schematic_rev1.0 Stuff 100k(RC97) for Cannonlake. Un-stuff 100k(RC97) for Skylake

SKL-U

SPARE

20 OF 20

42E_SOC_XTAL24_IN_R

42E_SOC_XTAL24_OUT_R

Rev_1.0

RSVD_F6

RSVD_E3 RSVD_C11 RSVD_B11 RSVD_A11 RSVD_D12 RSVD_C12 RSVD_F52

LPM_ZVM#

F>&  

49G,H

9H

RC94 33_0201_1%EMI@

RC95 33_0201_1%EMI@

42E_SOC_XTAL24_IN_R

E3 C11 B11 A11 D12 C12 F52

RSVD_U12 RSVD_U11

1 2

U23@

RC93 10K_0402_5%

1 2

42E_SOC_XTAL24_IN

42E_SOC_XTAL24_OUT

1 2

RC91 0_0402_5%@

1 2

RC92 0_0402_5%@

+3VS

1 2

RC96 1M_0402_5%U42@

YC3 24MHZ_18PF_XRCGB24M000F2P51R0

CC93

27P_0402_50V8J

U42@

1U_0402_6.3V6K

SJ10000UJ00U42@

CC92

+1.8VALW

CC94

27P_0402_50V8J

U42@

Security Classification

2014/05/19 2015/12/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/05/19 2015/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

Custom

Date: Sheet

Compal Electronics, Inc.

SKL-U(12/12)CFG,RSVD

Document Number R

LA-D562P

17 66Thursday, June 15, 2017

0.1

+DDR_VREF_CA

DDR_A_MA0

DDR_A_MA1 DDR_A_MA2

CD1

DDR_A_MA3 DDR_A_MA4 DDR_A_MA5

0.047U_0402_25V7K

DDR_A_MA6 DDR_A_MA7

D D

DDR_A_BA0[7,18,20] DDR_A_BA1[7,18,20]

DDR_A_CLK0[7,18] DDR_A_CLK#0[7,18] DDR_A_CKE0[7,18,20]

DDR_A_ODT0[7,20]

DDR_A_CS#0[7,18,20]

C C

DDR_A_ALERT#[7]

DDR_A_PARITY[7,20]

DDR_A_MA[0..16][7,20] DDR_A_DQS#[0..7][7] DDR_A_DQS[0..7][7] DDR_A_D[0..63][7]

B B

DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14

DDR_A_BA0 DDR_A_BA1 DDR_A_BA1

+1.2V

DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CKE0

DDR_A_ODT0 DDR_A_CS#0 DDR_A_MA16 DDR_A_MA15

DDR_A_DQS#1 DDR_A_DQS1 DDR_A_DQS#0 DDR_A_DQS0

MEMRST#

1 2

240_0402_1%

M_A_ACT#

M_A_ACT#[7,20]

DDR_A_BG0

DDR_A_BG0[7,20]

DDR_A_ALERT# DDR_A_PARITY

+2.5V

VREFCA

A10/AP

A11

A12/BC

A13

A14/WE

BA0

BA1

DMU/DBIU

DML/DBIL

CK_t

CK_c

CKE

ODT

RAS

CAS

DQSU_c

DQSU_t

DQSL_c

DQSL_t

RESET

RD23

ACT

BG0

TEN

ALERT

PAR

VPP

96-BALL

SDRAM DDR4

K4A8G165WB-BCPB_FBGA96

X76@

CLOCK TERMINATION

DDR_DRAMRST#[7,19]

DDR_A_CLK0 DDR_A_CLK#0

RD18 36_0402_1% RD19 36_0402_1%

DDR_A_ALERT#

RD2 49.9_0402_1%

DDR_DRAMRST#

1 2 1 2

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS

DDR_A_D5

DDR_A_D6

DDR_A_D1

DDR_A_D2

DDR_A_D4

DDR_A_D7

DDR_A_D0

DDR_A_D3

DDR_A_D13

DDR_A_D14

DDR_A_D9

DDR_A_D15

DDR_A_D8

DDR_A_D10

DDR_A_D12

DDR_A_D11

B3 B9 D1 G7 J1 J9 L1 L9 R1 T9

A1 A9 C1 D9 F2 F8 G1 G9 J2 J8

B2 E1 E9 G8 K1 K9 M9 N1 T1

A2 A8 C9 D2 D8 E3 E8 F1 H1 H9

+1.2V

DDR_A_BG1_R DDR_A_BG1_R DDR_A_BG1_R

X76@

RD29 0_0402_5%

+1.2V

INTEL suggest 50ohm 1%

RD3

1 2

0_0402_5%

MEMRST#

CD5

0.1U_0201_10V6K

+DDR_VREF_CA

RD22

VREFCA

A10/AP

A11

A12/BC

A13

A14/WE

BA0

BA1

DMU/DBIU

DML/DBIL

CK_t

CK_c

CKE

ODT

RAS

CAS

DQSU_c

DQSU_t

DQSL_c

DQSL_t

RESET

ACT

BG0

TEN

ALERT

PAR

VPP

96-BALL

SDRAM DDR4

K4A8G165WB-BCPB_FBGA96

X76@

DDR_A_BG1[7]

DDR_A_MA0

DDR_A_MA1 DDR_A_MA2

CD2

DDR_A_MA3 DDR_A_MA4 DDR_A_MA5

0.047U_0402_25V7K

DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14

DDR_A_BA0[7,18,20] DDR_A_BA1[7,18,20]

DDR_A_CLK0[7,18] DDR_A_CLK#0[7,18] DDR_A_CKE0[7,18,20]

DDR_A_CS#0[7,18,20] DDR_A_CS#0[7,18,20]

X76@

RD35 0_0402_5%

DDR_A_BA0

+1.2V +1.2V

DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CKE0

DDR_A_ODT0 DDR_A_CS#0 DDR_A_MA16 DDR_A_MA15

DDR_A_DQS#2 DDR_A_DQS2 DDR_A_DQS#3 DDR_A_DQS3

MEMRST# MEMRST#

1 2

240_0402_1%

M_A_ACT# DDR_A_BG0

DDR_A_ALERT# DDR_A_PARITY

+2.5V

+0.6VS

DDR_A_D25

DQL0

DDR_A_D29

DQL1

DDR_A_D27

DQL2

DDR_A_D26

DQL3

DDR_A_D24

DQL4

DDR_A_D31

DQL5

DDR_A_D28

DQL6

DDR_A_D30

DQL7

DDR_A_D16

DQU0

DDR_A_D18

DQU1

DDR_A_D17

DQU2

DDR_A_D23

DQU3

DDR_A_D20

DQU4

DDR_A_D22

DQU5

DDR_A_D21

DQU6

DDR_A_D19

DQU7

VDD

VDDQ

VSS

VSSQ

0606 add

X76@

DDR_A_BG1 DDR_A_BG1_R

1 2

RD33

0_0402_5%

+1.2V

+DDR_VREF_CA

RD21



VREFCA

A10/AP

A11

A12/BC

A13

A14/WE

BA0

BA1

DMU/DBIU

DML/DBIL

CK_t

CK_c

CKE

ODT

RAS

CAS

DQSU_c

DQSU_t

DQSL_c

DQSL_t

RESET

ACT

BG0

TEN

ALERT

PAR

VPP

96-BALL

SDRAM DDR4

K4A8G165WB-BCPB_FBGA96

X76@

!!

:3 :3 :3 :3

3

3



I>9.

>9.

I I>9. I>9.

DDR_A_MA0

DDR_A_MA1 DDR_A_MA2

CD3

DDR_A_MA3 DDR_A_MA4 DDR_A_MA5

0.047U_0402_25V7K

DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14

+2.5V

DDR_A_BG1_R [20]

54/

3

DDR_A_BA0 DDR_A_BA1

DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CKE0

DDR_A_ODT0 DDR_A_CS#0 DDR_A_MA16 DDR_A_MA15

DDR_A_DQS#4 DDR_A_DQS4 DDR_A_DQS#5 DDR_A_DQS5

1 2

240_0402_1%

M_A_ACT# DDR_A_BG0

DDR_A_ALERT# DDR_A_PARITY

DDR_A_BA0[7,18,20] DDR_A_BA1[7,18,20] DDR_A_BA0[7,18,20]

DDR_A_CLK0[7,18] DDR_A_CLK#0[7,18] DDR_A_CLK0[7,18] DDR_A_CKE0[7,18,20]

X76@

RD30

RD36

0_0402_5%

!

3

-!<

3

-!>

3

-!>

3

-!>

-!>>

-!>I

9.

-!>

9.

-!>D

9.

-!>1

DQL0

DQL1

DQL2

DQL3

DQL4

DQL5

DQL6

DQL7

DQU0

DQU1

DQU2

DQU3

DQU4

DQU5

DQU6

DQU7

VDD

VDDQ

VSS

VSSQ

Data mapping

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

DDR_A_D40 DDR_A_D43 DDR_A_D44 DDR_A_D42 DDR_A_D41 DDR_A_D46 DDR_A_D45 DDR_A_D47

DDR_A_D37 DDR_A_D39 DDR_A_D32 DDR_A_D35 DDR_A_D34 DDR_A_D33 DDR_A_D36 DDR_A_D38

D3 D1 D2 D0 D

7 D5 D6 D4

D10

D11

D14 D13 D15 D12

+DDR_VREF_CA

RD20

VREFCA

A10/AP

A11

A12/BC

A13

A14/WE

BA0

BA1

DMU/DBIU

DML/DBIL

CK_t

CK_c

CKE

ODT

RAS

CAS

DQSU_c

DQSU_t

DQSL_c

DQSL_t

RESET

ACT

BG0

TEN

ALERT

PAR

VPP

96-BALL

SDRAM DDR4

K4A8G165WB-BCPB_FBGA96

X76@

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

D51 D49 D50 D48 D55 D53 D54 D52 D58 D56 D59 D57 D62 D61 D63 D60

DDR_A_MA0

DDR_A_MA1 DDR_A_MA2

CD4

DDR_A_MA3 DDR_A_MA4 DDR_A_MA5

0.047U_0402_25V7K

DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14

+1.2V

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQ DQU3 DQU4 DQU5 DQU6 DQU7

X76@

RD31 0_0402_5%

DDR_A_CLK#0[7,18] DDR_A_CKE0[7,18,20]

X76@

RD37 0_0402_5%

D19 D17 D18 D16 D23 D21 D22 D20 D26 D24 D27 D25 D30 D29 D31 D28

DDR_A_BA1[7,18,20]

DDR_A_CS#0[7,18,20]

DDR_A_BA0 DDR_A_BA1

+1.2V

DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CKE0

DDR_A_ODT0 DDR_A_CS#0 DDR_A_MA16 DDR_A_MA15

DDR_A_DQS#6 DDR_A_DQS6 DDR_A_DQS#7 DDR_A_DQS7

MEMRST#

1 2

M_A_ACT# DDR_A_BG0

+2.5V

U4 U5

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0

DQ DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

240_0402_1%

DDR_A_ALERT# DDR_A_PARITY

D35 D33 D34 D32 D39 D37 D38 D36 D42 D40 D43 D41 D46 D45 D47 D44

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

DDR_A_D56

DDR_A_D58

DDR_A_D57

DDR_A_D59

DDR_A_D61

DDR_A_D62

DDR_A_D60

DDR_A_D63

DDR_A_D52

DDR_A_D55

DDR_A_D53

DDR_A_D54

DDR_A_D49

DDR_A_D50

DDR_A_D48

DDR_A_D51

VDD

A1 A9 C1 D9 F2 F8 G1 G9 J2 J8

VSS

A2 A8 C9 D2 D8 E3 E8 F1 H1 H9

+1.2V

DDR_A_BG1_R

X76@

RD32

0_0402_5%

X76@

RD38 0_0402_5%

+1.2V

RD4

1.8K_0402_1%

1 2

RD7

1.8K_0402_1%

1 2

+DDR_VREF_CA

RD5

2.7_0402_1%

A A

+0.6V_VREFCA[7]

CD6

0.022U_0402_16V7K

RD6

24.9_0402_1%

4*8'

LA-D301P

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/02/14 2015/02/14

Compal Secret Data

Deciphered Date

Title

DDR4 ON BOARD CHIPS

Size

Document Number Re

Custom

Custom Date: Sheet of

Date: Sheet of

18 66Thursday, June 15, 2017

0.1

DDR_B_DQS#[0..7][7]

DDR_B_D[0..63][7]

DDR_B_DQS[0..7][7]

DDR_B_MA[0..16][7]

DDR_B_BA0[7]

DDR_B_BA1[7]

DDR_B_BG0[7] DDR_B_BG1[7]

DDR_B_CLK0[7]

1 1

Layout Note: Place near JDIMM1

+1.2V

2 2

+1.2V

DDR_B_CLK#0[7] DDR_B_CLK1[7]

DDR_B_CLK#1[7]

DDR_B_CKE0[7]

DDR_B_CKE1[7]

DDR_B_CS#0[7]

DDR_B_CS#1[7]

SOC_SMBDATA[8] SOC_SMBCLK[8]

DDR_B_ODT0[7] DDR_B_ODT1[7]

1U_0402_6.3V6K

CD8

CD9

4 as near side of the DIMM close to VDD pins

10U_0603_6.3V6M

CD18

CD17

DDR_B_BA0 DDR_B_BA1 DDR_B_BG0 DDR_B_BG1

DDR_B_CLK0 DDR_B_CLK#0 DDR_B_CLK1 DDR_B_CLK#1

DDR_B_CKE0 DDR_B_CKE1 DDR_B_CS#0 DDR_B_CS#1

SOC_SMBDATA SOC_SMBCLK

DDR_B_ODT0 DDR_B_ODT1

Note: Check voltage tolerance of VREF_DQ at the DIMM socket

1U_0402_6.3V6K

CD10

10U_0603_6.3V6M

CD19

CD20

CD11

CD12

10U_0603_6.3V6M

CD23

CD22

CD21

1U_0402_6.3V6K

10U_0603_6.3V6M

1U_0402_6.3V6K

CD13

CD15

CD14

CD24

+1.2V

DDR_B_D14 DDR_B_D15 DDR_B_DQS#1

DDR_B_DQS1 DDR_B_D13 DDR_B_D12 DDR_B_D1 DDR_B_D5

DDR_B_D2 DDR_B_D3 DDR_B_D21 DDR_B_D16 DDR_B_D17 DDR_B_DQS#2

DDR_B_DQS2 DDR_B_D23 DDR_B_D22 DDR_B_D29 DDR_B_D25

DDR_B_D30 DDR_B_D26

@ 1 2 1 2

RD25 240_0402_1% RD24 240_0402_1%@

DDR_B_CKE0

DDR_B_BG1

DDR_B_BG0

DDR_B_MA12

DDR_B_MA9

DDR_B_MA8

DDR_B_MA6

DDR_B_MA3

DDR_B_MA1

DDR_B_CLK0

DDR_B_PARITY[7]

DDR_B_CLK#0

1 3 5 7

9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99

101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143

JDIMM2 ME@

VSS1 DQ5 VSS3 DQ1 VSS5 DQS0_c DQS0_t VSS8 DQ7 VSS10 DQ3 VSS12 DQ13 VSS14 DQ9 VSS16 DM1_n/DBI_n VSS17 DQ15 VSS19 DQ10 VSS21 DQ21 VSS23 DQ17 VSS25 DQS2_c DQS2_t VSS28 DQ23 VSS30 DQ19 VSS32 DQ29 VSS34 DQ25 VSS36 DM3_n/DBI3_n VSS37 DQ30 VSS39 DQ26 VSS41 CB5/NC VSS43 CB1/NC VSS45 DQS8_c DQS8_t VSS48 CB2/NC VSS50 CB3/NC VSS52 CKE0 VDD1 BG1 BG0 VDD3 A12 A9 VDD5 A8 A6 VDD7 A3 A1 VDD9 CK0_t CK0_c VDD11 PARITY

DM0_n/DBI0_n

VSS11 VSS13

VSS15 DQS1_c DQS1_t

VSS18

VSS20

VSS22

VSS24

VSS26

DM2_n/DBI2_n

VSS27

VSS29

VSS31

VSS33

VSS35 DQS3_c DQS3_t

VSS38

VSS40

VSS42 CB4/NC

VSS44 CB0/NC

VSS46

DM8_n/DBI_n/NC

VSS47 CB6/NC

VSS49 CB7/NC

VSS51

RESET_n

ACT_n

ALERT_n

EVENT_n/NF

VDD10

CK1_t/NF

CK1_c/NF

VDD12

VSS2

DQ4

VSS4

DQ0

VSS6 VSS7

DQ6

VSS9

DQ2

DQ12

DQ8

DQ14 DQ11 DQ20 DQ16

DQ22 DQ18 DQ28 DQ24

DQ31 DQ27

CKE1 VDD2

VDD4

VDD6

VDD8

+1.2V

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120

A11

122

124 126

128

130 132

134 136 138 140 142 144

DDR_B_D11 DDR_B_D10

DDR_B_D8 DDR_B_D9 DDR_B_D4 DDR_B_D0 DDR_B_DQS#0

DDR_B_DQS0 DDR_B_D6 DDR_B_D7 DDR_B_D20

DDR_B_D19 DDR_B_D18 DDR_B_D28 DDR_B_D24 DDR_B_DQS#3

DDR_B_DQS3 DDR_B_D31 DDR_B_D27

DDR_B_CKE1

DDR_B_MA11 DDR_B_MA7

DDR_B_MA5 DDR_B_MA4

DDR_B_MA2

DDR_B_CLK1 DDR_B_CLK#1

DDR_B_MA0

DDR_DRAMRST#_R

M_B_ACT# [7]

DDR_B_ALERT# [7]

CD80

0.1U_0201_10V6K

+0.6V_B_VREFDQ[7]

Reverse Type

2-3A to 1 DIMMs/channel



CD7

0.022U_0402_16V7K

RD10

24.9_0402_1%

RD9 2_0402_1%

+1.2V

+DIMM_VREF_DQ

RD8 1K_0402_1%

1 2

RD11 1K_0402_1%

1 2

DDR_B_BA1 DDR_B_CS#0

DDR_B_MA14 DDR_B_ODT0

DDR_B_CS#1 DDR_B_ODT1

Place these caps on the VTT plane close to DIMM

+0.6VS

10U_0603_6.3V6M

CD29

10P_0402_25V8J

CD25

1U_0402_6.3V6K

3 3

4 4

10U_0603_6.3V6M

CD26

1U_0402_6.3V6K

+2.5V

CD28

CD27

1U_0402_6.3V6K

CD55

CD32

CD30

1U_0402_6.3V6K

CD81

@RF@

10P_0402_25V8J

CD82

@RF@

+3VS

CD54

2.2U_0402_6.3V6M

CD31

0.1U_0201_10V6K

close to DIMM

DDR_B_D37 DDR_B_D33 DDR_B_DQS#4

DDR_B_DQS4 DDR_B_D38 DDR_B_D34 DDR_B_D41 DDR_B_D40

DDR_B_D43 DDR_B_D42 DDR_B_D52 DDR_B_D49 DDR_B_DQS#6

DDR_B_DQS6 DDR_B_D55 DDR_B_D50 DDR_B_D61 DDR_B_D56

DDR_B_D59 DDR_B_D58 SOC_SMBCLK

145

BA1

147

VDD13

149

CS0_n

151

WE_n/A14

153

VDD15

155

ODT0

157

CS1_n

159

VDD17

161

ODT1

163

VDD19

165

C1, CS3_n,NC

167

VSS53

169

DQ37

171

VSS55

173

DQ33

175

VSS57

177

DQS4_c

179

DQS4_t

181

VSS60

183

DQ38

185

VSS62

187

DQ34

189

VSS64

191

DQ44

193

VSS66

195

DQ40

197

VSS68

199

DM5_n/DBI5_n

201

VSS69

203

DQ46

205

VSS71

207

DQ42

209

VSS73

211

DQ52

213

VSS75

215

DQ49

217

VSS77

219

DQS6_c

221

DQS6_t

223

VSS80

225

DQ55

227

VSS82

229

DQ51

231

VSS84

233

DQ61

235

VSS86

237

DQ56

239

VSS88

241

DM7_n/DBI7_n

243

VSS89

245

DQ62

247

VSS91

249

DQ58

251

VSS93

253

SCL

255

VDDSPD

257

VPP1

259

VPP2

DEREN_40-42272-26001RHF

JDIMM Connector PN SP07001GK00

C0/CS2_n/NC

DM4_n/DBI4_n

DM6_n/DBI6_n

RAS_n/A16 CAS_n/A15

A10/AP

VDD14

VDD16

VDD18

VREFCA

VSS54

VSS56

VSS58

VSS59

VSS61

VSS63

VSS65

VSS67 DQS5_c DQS5_t

VSS70

VSS72

VSS74

VSS76

VSS78

VSS79

VSS81

VSS83

VSS85

VSS87 DQS7_c DQS7_t

VSS90

VSS92

VSS94

DQ36 DQ32

DQ39 DQ35 DQ45 DQ41

DQ47 DQ43 DQ53 DQ48

DQ54 DQ50 DQ60 DQ57

DQ63 DQ59

GND1 GND2

146 148 150

BA0

152 154 156 158

A13

160 162 164 166

SA2

168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232 234 236 238 240 242 244 246 248 250 252 254

SDA

256

SA0

258

VTT

260

SA1

261 262

DDR_B_MA10 DDR_B_BA0

DDR_B_MA16 DDR_B_MA15

DDR_B_MA13

DDR_B_D36 DDR_B_D32

DDR_B_D39 DDR_B_D35 DDR_B_D44 DDR_B_D45 DDR_B_DQS#5

DDR_B_DQS5 DDR_B_D47 DDR_B_D46 DDR_B_D53 DDR_B_D48

DDR_B_D54 DDR_B_D51 DDR_B_D60 DDR_B_D57 DDR_B_DQS#7

DDR_B_DQS7 DDR_B_D63 DDR_B_D62 SOC_SMBDATA

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+DIMM_VREF_DQ

RD27

10K_0402_5%

RD26

0_0402_5%

Compal Secret Data

+3VS

1 2 12

Deciphered Date

+0.6VS+2.5V

2014/11/10 2016/11/10

DDR_DRAMRST#_R

RD15

1 2

0_0402_5%

0309 change 0ohm

Compal Electronics, Inc.

Title

Size

Date: Sheet

DDR4_DIMM

Document Number Rev

Custom

LA-D562P

DDR_DRAMRST# [7,18]

19 66Thursday, June 15, 2017

0.1

DDR_A_MA[0..16][7,18]

D D

+1.2V

CD56

CD58

CD57

1U_0402_6.3V6K

CD60

CD59

1U_0402_6.3V6K

CD61

1U_0402_6.3V6K

3

10U_0603_6.3V6M

C C

+2.5V +0.6VS

CD64

10U_0603_6.3V6M

CD42

CD43

CD66

CD65

1U_0402_6.3V6K

2 as near each on board RAM device as possible

10U_0603_6.3V6M

CD44

CD67

1U_0402_6.3V6K

CD46

CD45

CD63 330U_D2_2V_Y

SGA00009S00

330U 9mohm POLY

CD68

CD70

CD69

1U_0402_6.3V6K

CD36

CD62

1U_0402_6.3V6K

CD35

CD34

CD33

CD37

1U_0402_6.3V6K

4 as near each on board RAM device as possible

2V H1.9

CD71

1U_0402_6.3V6K

CD38

1U_0402_6.3V6K

CD40

CD39

1U_0402_6.3V6K

CD41

1U_0402_6.3V6K

CD78

CD79

1U_0402_6.3V6K

CD76

CD77

1U_0402_6.3V6K

CD74

CD75

1U_0402_6.3V6K

CD72

CD73

1U_0402_6.3V6K

2 as near each on board RAM device as possible

+0.6VS

RP1

DDR_A_MA1

1 8

DDR_A_MA5

2 7

DDR_A_MA7

3 6

DDR_A_MA9

4 5

36_0804_8P4R_5%

RP2

DDR_A_MA13

1 8

DDR_A_MA8

2 7

DDR_A_PARITY

DDR_A_PARITY[7,18]

DDR_A_CKE0[7,18]

DDR_A_ODT0[7,18]

M_A_ACT#[7,18]

DDR_A_BG1_R[18]

DDR_A_BG0[7,18]

DDR_A_BA1[7,18]

DDR_A_CS#0[7,18]

DDR_A_BA0[7,18]

DDR_A_MA11

DDR_A_CKE0 DDR_A_MA16 DDR_A_ODT0 M_A_ACT#

DDR_A_MA2

DDR_A_BG1_R

DDR_A_BG0 DDR_A_MA10 DDR_A_MA3 DDR_A_BA1

DDR_A_MA14 DDR_A_CS#0 DDR_A_MA15 DDR_A_MA12

DDR_A_MA4 DDR_A_BA0 DDR_A_MA0 DDR_A_MA6

3 6 4 5

36_0804_8P4R_5%

RP3

1 8 2 7 3 6 4 5

36_0804_8P4R_5%

1 2

RD28 36_0201_1%

1 2

RD34 36_0201_1%X76@

RP5

1 8 2 7 3 6 4 5

36_0804_8P4R_5%

RP6

1 8 2 7 3 6 4 5

36_0804_8P4R_5%

RP7

1 8 2 7 3 6 4 5

36_0804_8P4R_5%

10U_0603_6.3V6M

CD47

10U_0402_6.3V6M

CD48

10U_0402_6.3V6M

B B

A A

10U_0603_6.3V6M

CD49

CD51

CD50

10U_0603_6.3V6M

CD52

CD53

LA-D301P

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/02/14 2015/02/14

Compal Secret Data

Deciphered Date

Title

DDR4 ON BOARD CHIPS

Size

Document Number Re

Custom

Custom Date: Sheet of

Date: Sheet of

20 66Thursday, June 15, 2017

0.1

+ 46 hidden pages

LCFC V530 schematics

Specifications and Main Features

Frequently Asked Questions

User Manual