LCFC S145AST Schematic

A

Vinafix.com

1 1

B

C

D

E

LCFC Confidential

S145AST M/B Schematics Document

2 2

REV:0.2

AMD FT4 Stoney SOC with DDRIV

AMD R17M-M1-70

3 3

4 4

A

2018-10

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

C

2017/03/14

2017/03/14

2017/03/14

LC Future Center Secr et Data

LC Future Center Secr et Data

LC Future Center Secr et Data

Deciphered Date

Deciphered Date

Deciphered Date

2017/03/14

2017/03/14

2017/03/14

D

Title

Cover Page

Cover Page

Cover Page

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Thursday, October 25, 2018

Thursday, October 25, 2018

Date: Sheet of

Date: Sheet of

Date: Sheet of

Thursday, October 25, 2018

S145AST

S145AST

S145AST

E

1 50

1 50

1 50

0.2

0.2

0.2

A

Vinafix.com

LCFC confidential

File Name : German

B

C

D

E

AMD: R17M-M1-70
Package: S3

WĂŐĞϭϱΕϭϵ

1 1

VRAM: 256*32
GDDR5*2: 2GB

WĂŐĞϮϬΕϮϭ

PCIe Port 1~4

HDMI Conn.

WĂŐĞϮϰ

Touch Screen

USB 2.0 Port

eDP Conn

Int. Camera

2 2

USB2.0 Port2

Int. MIC Conn.

WĂŐĞϮϯ

WĂŐĞϮϯ

SATA HDD

WĂŐĞϯϰ

NGFF SSD

WĂŐĞϮϵ

PCI-Express

4x Gen3

HDMI x4 Lane Port1

USB 2.0 1x

eDP x2 Lane

USB2.0 1x

SATA Gen3

SATA Port0

PCI-Express 2x Gen3

AMD FT4 APU

Stoney 15W

(Integrated FCH)

BGA-769
24mm*24mm

Memory BUS (DDR4)
Single Channel B

1.2V DDR4 2133 MT/s
1866 MT/s

USB3.0 x1
USB2.0 x1

USB3.0 Left Conn

USB3.0 Port0
USB2.0 Port4

USB2.0 Left Conn

USB2.0 x1

USB3.0 x1
USB2.0 x1

USB 2.0 1x

PCIe 1x

SPI BUS

USB2.0 Port3

USB3.0 Left Conn

USB3.0 Port1
USB2.0 Port5

NGFF Card
WLAN&BT
Key E

WĂŐĞϯϭ

SPI ROM
8MB

PCIe Por t2
USB2.0 Port1

WĂŐĞϬϴ

DDR4-SO-DIMM X1

Page 12

UP TO 8G

WĂŐĞϮϱ

WĂŐĞϮϱ

WĂŐĞϮϱ

TPM (Reserved)

SD/MMC Conn.

3 3

SPK Conn.

Codec & C/R

Realtek RTS5119

USB2.0 x1

HD Audio

WĂŐĞϰΕϭϭ

HP&Mic Combo Conn.

LPC BUS

SMBUS

SMBUS

IO Board

USB2.0 Port0

EC
ITE IT8586E-LQFP

WĂŐĞϯϱ

ST33HTPH2E32AHB4

WĂŐĞϮϲ

Touch Pad

WĂŐĞϯϲ

Bat tery

WĂŐĞϰϯ

4 4

A

B

Int.KBD

WĂŐĞϯϲ

Thermistor

WĂŐĞϯϬ

Charger

Hall sensor

AH9247

WĂŐĞϯϲ

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEI THER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEI THER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEI THER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

C

2017/03/14

2017/03/14

2017/03/14

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Decipher ed Date

Decipher ed Date

Decipher ed Date

Thermal Sensor
F75303M

WĂŐĞϯϬ

D

WĂŐĞϰϰ

reserve

2017/03/14

2017/03/14

2017/03/14

Title

Title

Title

Block Diagram

Block Diagram

Block Diagram

Size Docu me nt Nu mb er Rev

Size Docu me nt Nu mb er Rev

Size Docu me nt Nu mb er Rev

Cus to m

Cus to m

Cus to m

Thursday, October 25, 2018

Thursday, October 25, 2018

Thursday, October 25, 2018

Dat e: Sheet of

Dat e: Sheet of

Dat e: Sheet of

S145AST

S145AST

S145AST

E

2 50

2 50

2 50

0.2

0.2

0.2

A

Vinafix.com

Voltage Rails

1 1

State

S0

S3

2 2

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery
don't exist

( O --> Means ON , X --> Means OFF )

power
plane

B+
(+20VSB)

+3VL

+5VLP

O

O

O

O

X

+5VALW

+3VALW
(+3VALW_APU)

+1.8VALW

+0.95VALW

+0.775VALW

O

O

O

X

X X X

+2.5V

+1.2V
(+VSYSMEM_APU)

SMBUS Control Table

SOURCE

EC_SMB_CK1

EC_SMB_DA1

3 3

EC_SMB_CK3

EC_SMB_DA3

APU_SMB_CLK
APU_SMB_DATA

EC_SMB_CK2

EC_SMB_DA2

TP_I2C0_SCL_R
TP_I2C0_SDA_R

IT8586E

+3VL_EC

IT8586E

+3VS

APU

+3VS

IT8586E

+3VL_EC

APU

+1.8VS

EC SM Bus1 address

Device

Battery

Ch ar ger

4 4

A d d r e s s

0X16 1001_100xb(reserve)

0001 0010 b

APU SM Bus1 address

Device A d d r e s s

Touch pad

GPU BATT SODIMM WLAN Thermal

X

X

V

+3VS_VGA

X X X X

X

X

V V

X X X X X X XXV

X X X X X X X X

EC SM Bus2 address

A

0x15

Device

PMI C

A P U S M B u s 2

No use

A d d r e s s

0X34

APU SM Bus3 address

Device A d d r e s s

DDR DIMM

WLAN

B

+5VS

+3VS

+1.8VS

+1.5VS

+0.95VS

+0.6VS

+APU_CORE

+APU_CORE_NB

+APU_GFX

+VGA_CORE

+3VGS

+1.8VGS

+1.35VGS

+0.95VGS

O

X X

X

Sensor

XV

X

V

X

Device

Therm al Sensor

GPU

APU SB-TSI

0xA0h

RSVD

B

STATE

S0 (Full ON)

S1 (Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

USB Port Table for Stoney FT4

OO

EHCI

X

xHCI 2

X

APUIT8586E

Charger

PMIC

V

X

V

APU_SIC
APU_SID

1.8VS for AST

X

X

X

X

EC SM Bus3 address

A d d r e s s

0x41(default)

releate to F3x1E4[SbiAddr] or
Address Select Pins setting

APU SM Bus4

No use

C

SIGNAL

SLP_S3# SLP_S5# +VALW +V +VS Clock

HIGH HIGH

LOW

LOW LOW

USB 3.0USB 2.0 Port

HIGHHIGH

HIGHLOW

LOW

Port device

0

Card Reader

1

Blue Tooth

2

Camera

3

LEFT USB (2.0)

4

LEFT USB (3.0) Lower

5

LEFT USB (3.0) upper

6

Touch screen

7

ON

ON

ON

ON

ON

ONONON ON

ON

OFF

OFF

ON

OFF

OFF

OFF

D

LOW

OFF

OFF

OFF

BOM Structure Table

@
ME@
Debug@
NODebug@
EMC@
EMC_NS@
EMC_PX@
EMC_PXNS@
RF_NS@
RF_PXNS@
UMA@
PX@
EXO@
TOPAZ@
TPM@
AOAC@
HDT@
TS@
NOTS@
S4GX4@
M4GX4@

Touch
Pad

X

PCIE PORT LIST

Port Device

0

SSD

1

GPP

2

WL AN

3

N/A

0
1

GFX

DIS GPU

2
3

H4GX4@

X

S2GX4@
M2GX4@
H2GX4@

X

VRAM

X

S2G@
M2G@
H2G@
S1G@
M1G@
H1G@
SIVCD@

2017/03/14

2017/03/14

2017/03/14

HDMI@
STN@

V

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEE RING DRAWING IS THE PROPRIETARY P ROPERTY OF LC FUTURE CENTER. AND CONT AINS CONFIDENTIAL

THIS SHEET OF ENGINEE RING DRAWING IS THE PROPRIETARY P ROPERTY OF LC FUTURE CENTER. AND CONT AINS CONFIDENTIAL

THIS SHEET OF ENGINEE RING DRAWING IS THE PROPRIETARY P ROPERTY OF LC FUTURE CENTER. AND CONT AINS CONFIDENTIAL
AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R& D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R& D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R& D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

C

2017/03/14

2017/03/14

2017/03/14

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

E

BOARD

BOARD_ID1

Config.

0: Dis

1: UMA

BOARD

BOARD_ID0 BOARD_ID3

Config.
14''

15''

17''

BOARD_ID2 reserve

0

0 1

1 0

0: No KBL

1: KBL

0

BTO ItemBOM Structure

Not stuff

Connector

For USB debug part

For USB no debug part

EMC Part

EMC reserve Part

EMC GPU part

EMC GPU reserve part

RF reserve Part

RF GPU reserve part

UMA SKU ID part

Discrete GPU SKU part

EXO GPU Part

TOPAZ GPU Part

TPM part

AOAC support part

HDT Debug part

Touch screen part

No Touch screen part

X76 SAMSUNG 2G

X76 MICRON 2G

X76 HYNIX 2G

X76 SAMSUNG 1G

X76 MICRON 1G

X76 HYNIX 1G

SAMSUNG 2G

MICRON 2G

HYNIX 2G

SAMSUNG 1G

MICRON 1G

HYNIX 1G

SIV COST down material

HDMI Logo

Stoney part

Title

Title

Title

Notes List

Notes List

Notes List

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Thursday, October 25, 2018

Thursday, October 25, 2018

Thursday, October 25, 2018

Date: Sheet of

Date: Sheet of

Date: Sheet of

S145AST

S145AST

S145AST

E

3 50

3 50

3 50

0.2

0.2

0.2

5

Vinafix.com

D D

PCIE_CRX_DTX_P029

M.2 SSD1

WLAN WLAN

C C

GPU

+0.95VS

PCIE_CRX_DTX_N029

PCIE_CRX_DTX_P129
PCIE_CRX_DTX_N129

PCIE_PRX_DTX_P131
PCIE_PRX_DTX_N131

PCIE_CRX_GTX_P015
PCIE_CRX_GTX_N015

PCIE_CRX_GTX_P115
PCIE_CRX_GTX_N115

PCIE_CRX_GTX_P215
PCIE_CRX_GTX_N215

PCIE_CRX_GTX_P315
PCIE_CRX_GTX_N315

1 2

with BOM strcture control, RC1 change to 196_0402_1% for Stoney and Carrizo

CarrizoL not support GFX4-GFX7

4

UC2B

PCIE

PCIE_CRX_DTX_P0
PCIE_CRX_DTX_N0

PCIE_CRX_DTX_P1 PCIE_CTX_DRX_P1
PCIE_CRX_DTX_N1

PCIE_PRX_DTX_P1
PCIE_PRX_DTX_N1

PCIE_CRX_GTX_P0
PCIE_CRX_GTX_N0

PCIE_CRX_GTX_P1
PCIE_CRX_GTX_N1

PCIE_CRX_GTX_P2
PCIE_CRX_GTX_N2

PCIE_CRX_GTX_P3
PCIE_CRX_GTX_N3

P_TX_ZVDD

RC1196_0402_1% STN@

U4
U5

R8

R10

R5
R4

N4
N5

L5
L4

J5
J4

G5
G4

D7
E7

U8

P_GPP_RXP0
P_GPP_RXN0

P_GPP_RXP1
P_GPP_RXN1

P_GPP_RXP2
P_GPP_RXN2

P_GPP_RXP3
P_GPP_RXN3

P_GFX_RXP0
P_GFX_RXN0

P_GFX_RXP1
P_GFX_RXN1

P_GFX_RXP2
P_GFX_RXN2

P_GFX_RXP3
P_GFX_RXN3

P_ZVDDP

@

P_GPP_TXP0

P_GPP_TXN0

P_GPP_TXP1

P_GPP_TXN1

P_GPP_TXP2

P_GPP_TXN2

P_GPP_TXP3

P_GPP_TXN3

P_GFX_TXP0
P_GFX_TXN0

P_GFX_TXP1
P_GFX_TXN1

P_GFX_TXP2
P_GFX_TXN2

P_GFX_TXP3
P_GFX_TXN3

FT4 REV 0.93

AMD-STONEY-FT4_BGA769

P_ZVSS

3

D2
D1

C2
C1

B2
B1

A3
B3

A4
B4

A5
B5

A6
B6

A7
B7

W8

P_RX_ZVDD

PCIE_CTX_DRX_P0
PCIE_CTX_DRX_N0

PCIE_CTX_DRX_N1

PCIE_PTX_DRX_P1
PCIE_PTX_DRX_N1

PCIE_CTX_GRX_P0
PCIE_CTX_GRX_N0

PCIE_CTX_GRX_P1
PCIE_CTX_GRX_N1

PCIE_CTX_GRX_P2
PCIE_CTX_GRX_N2

PCIE_CTX_GRX_P3
PCIE_CTX_GRX_N3

1 2

CC3 0.22U_0201_6.3V6-K

1 2

CC4 0.22U_0201_6.3V6-K

1 2

CC13 0.22U_6.3V_K_X5R_0201

1 2

CC14 0.22U_6.3V_K_X5R_0201

1 2

CC1 0.1U_0201_6.3V6-K

1 2

CC2 0.1U_0201_6.3V6-K

1

CC5 0.22U_0201_6.3V6-KPX@
CC6 0.22U_0201_6.3V6-KPX@

CC7 0.22U_0201_6.3V6-KPX@
CC8 0.22U_0201_6.3V6-KPX@

CC9 0.22U_0201_6.3V6-KPX@
CC10 0.22U_0201_6.3V6-KPX@

CC11 0.22U_0201_6.3V6-KPX@
CC12 0.22U_0201_6.3V6-KPX@

1

1
1

1
1

1
1

1 2

2
2

2
2

2
2

2
2

RC3196_0402_1% STN@

2

PCIE_CTX_C_DRX_P0
PCIE_CTX_C_DRX_N0

PCIE_CTX_C_DRX_P1
PCIE_CTX_C_DRX_N1

PCIE_PTX_C_DRX_P1
PCIE_PTX_C_DRX_N1

PCIE_CTX_C_GRX_P0
PCIE_CTX_C_GRX_N0

PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_N1

PCIE_CTX_C_GRX_P2
PCIE_CTX_C_GRX_N2

PCIE_CTX_C_GRX_P3
PCIE_CTX_C_GRX_N3

PCIE_CTX_C_DRX_P0 29
PCIE_CTX_C_DRX_N0 29

PCIE_CTX_C_DRX_P1 29
PCIE_CTX_C_DRX_N1 29

PCIE_PTX_C_DRX_P1 31
PCIE_PTX_C_DRX_N1 31

PCIE_CTX_C_GRX_P0 15
PCIE_CTX_C_GRX_N0 15

PCIE_CTX_C_GRX_P1 15
PCIE_CTX_C_GRX_N1 15

PCIE_CTX_C_GRX_P2 15
PCIE_CTX_C_GRX_N2 15

PCIE_CTX_C_GRX_P3 15
PCIE_CTX_C_GRX_N3 15

1

GPU

B B

A A

5

Title

Title

Security Cl assificat ion

Security Cl assificat ion

Security Cl assificat ion

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2017/03/14

2017/03/14

2017/03/14

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2017/03/14

2017/03/14

2017/03/14

2

Title

FT4 (PCIE I/F)

FT4 (PCIE I/F)

FT4 (PCIE I/F)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet o f

Date: Sheet of

Date: Sheet of

Thursday, October 25, 2018

Thursday, October 25, 2018

Thursday, October 25, 2018

S145AST

S145AST

S145AST

1

4 50

4 50

4 50

0.2

0.2

0.2

5

Vinafix.com

D D

C C

MEM_MB_RST#12

B B

4

DDRB_MA[13..0]12

DDRB_BG112
DDRB_ACT#12

DDRB_BA012
DDRB_BA112
DDRB_BG012

DDRB_DM[7..0]12

DDRB_CLK012
DDRB_CLK0#12
DDRB_CLK112
DDRB_CLK1#12

1 2

RC240 10_0402_5%

MEM_MB_EVENT#12

DDRB_CKE012
DDRB_CKE112

DDRB_ODT012
DDRB_ODT112

DDRB_CS0#12
DDRB_CS1#12

DDRB_MA16_RAS#12
DDRB_MA15_CAS#12
DDRB_MA14_WE#12

TC8 6 @
TC7 0 @

1
1

DDRB_MA0
DDRB_MA1
DDRB_MA2
DDRB_MA3
DDRB_MA4
DDRB_MA5
DDRB_MA6
DDRB_MA7
DDRB_MA8
DDRB_MA9
DDRB_MA10
DDRB_MA11
DDRB_MA12
DDRB_MA13
DDRB_BG1
DDRB_ACT#

DDRB_BA0
DDRB_BA1
DDRB_BG0

DDRB_DM0
DDRB_DM1
DDRB_DM2
DDRB_DM3
DDRB_DM4
DDRB_DM5
DDRB_DM6
DDRB_DM7

DDRB_DQS0
DDRB_DQS#0
DDRB_DQS1
DDRB_DQS#1
DDRB_DQS2
DDRB_DQS#2
DDRB_DQS3
DDRB_DQS#3
DDRB_DQS4
DDRB_DQS#4
DDRB_DQS5
DDRB_DQS#5
DDRB_DQS6
DDRB_DQS#6
DDRB_DQS7
DDRB_DQS#7

DDRB_CLK0
DDRB_CLK0#
DDRB_CLK1
DDRB_CLK1#

MEM_MB_RST#_R
MEM_MB_EVENT#

DDRB_CKE0
DDRB_CKE1

DDRB_ODT0
DDRB_ODT1

DDRB_CS0#
DDRB_CS1#

DDRB_MA16_RAS#
DDRB_MA15_CAS#
DDRB_MA14_WE#

+MEM_VREF
APU_M_VREFDQ

AG3 8

M_ A D D 0

W35

M_ A D D 1

W38

M_ A D D 2

W34

M_ A D D 3

U38

M_ A D D 4

U37

M_ A D D 5

U34

M_ A D D 6

R35

M_ A D D 7

R38

M_ A D D 8

N38

M_ A D D 9

AG3 4

M_ A D D 1 0

R34

M_ A D D 1 1

N37

M_ A D D 1 2

AN35

M_ A D D 1 3

L38

M_ADD14/M_BG1

L35

M_ADD15/M_ACT_L

AJ3 8

M_BANK0

AG3 5

M_ B A N K 1

N34

M_BANK2/M_BG0

B35

M_ D M 0

D40

M_ D M 1

K40

M_ D M 2

T41

M_ D M 3

AE41

M_ D M 4

AL40

M_ D M 5

AU40

M_ D M 6

BA37

M_ D M 7

B36

M_DQS_H0

A36

M_DQS_L0

E40

M_DQS_H1

D41

M_DQS_L1

L40

M_DQS_H2

K41

M_DQS_L2

U41

M_DQS_H3

U40

M_DQS_L3

AF4 1

M_DQS_H4

AE40

M_DQS_L4

AM40

M_DQS_H5

AM41

M_DQS_L5

AV40

M_DQS_H6

AV41

M_DQS_L6

BA36

M_DQS_H7

AY36

M_DQS_L7

AC35

M_CLK_H0

AC34

M_CLK_L0

AA34

M_CLK_H1

AA32

M_CLK_L1

AE38

M_CLK_H2

AE37

M_CLK_L2

AA37

M_CLK_H3

AA38

M_CLK_L3

G38

M_RESET_L

AA41

M_EVENT_L

J38

M0_CKE0

J34

M0_CKE1

L34

M1_CKE0

J37

M1_CKE1

AN37

M0_ODT0

AU38

M0_ODT1

AL34

M1_ODT0

AN34

M1_ODT1

AL35

M0_CS_L0

AR37

M0_CS_L1

AJ3 4

M1_CS_L0

AR38

M1_CS_L1

AJ3 7

M_RAS_L/M_RAS_L_ADD16

AN38

M_CAS_L/M_CAS_L_ADD15

AL38

M_WE_L/M_WE_L_ADD14

AA40

M_VREF

Y41

M_VREFDQ

@

UC2A

MEMO RY

M_ZVDDIO_MEM_S3

FT4 REV 0.93

AMD-STONEY-FT4_BGA769

3

M_ D A T A 0
M_ D A T A 1
M_ D A T A 2
M_ D A T A 3
M_ D A T A 4
M_ D A T A 5
M_ D A T A 6
M_ D A T A 7

M_ D A T A 8

M_ D A T A 9
M_DATA10
M_DATA11
M_DATA12
M_DATA13
M_DATA14
M_DATA15

M_DATA16
M_DATA17
M_DATA18
M_DATA19
M_DATA20
M_DATA21
M_DATA22
M_DATA23

M_DATA24
M_DATA25
M_DATA26
M_DATA27
M_DATA28
M_DATA29
M_DATA30
M_DATA31

M_DATA32
M_DATA33
M_DATA34
M_DATA35
M_DATA36
M_DATA37
M_DATA38
M_DATA39

M_DATA40
M_DATA41
M_DATA42
M_DATA43
M_DATA44
M_DATA45
M_DATA46
M_DATA47

M_DATA48
M_DATA49
M_DATA50
M_DATA51
M_DATA52
M_DATA53
M_DATA54
M_DATA55

M_DATA56
M_DATA57
M_DATA58
M_DATA59
M_DATA60
M_DATA61
M_DATA62
M_DATA63

A34
B34
A38
B38
A33
B33
A37
B37

B41
C40
F41
G40
A40
B40
E41
F40

J40
J41
N40
N41
H40
H41
M4 0
M4 1

R40
T40
W40
Y40
P40
P41
V40
V41

AD41
AD40
AH41
AH40
AB40
AC40
AF4 0
AG4 0

AK41
AK40
AP41
AP40
AJ4 1
AJ4 0
AN41
AN40

AT4 0
AU41
AY40
BA40
AR40
AT4 1
AW 40
AY41

BA38
AY37
BA34
BA33
AY39
AY38
AY35
AY34

AB41

DDRB_DQ0
DDRB_DQ1
DDRB_DQ2
DDRB_DQ3
DDRB_DQ4
DDRB_DQ5
DDRB_DQ6
DDRB_DQ7

DDRB_DQ8
DDRB_DQ9
DDRB_DQ10
DDRB_DQ11
DDRB_DQ12
DDRB_DQ13
DDRB_DQ14
DDRB_DQ15

DDRB_DQ16
DDRB_DQ17
DDRB_DQ22
DDRB_DQ23
DDRB_DQ20
DDRB_DQ21
DDRB_DQ19
DDRB_DQ18

DDRB_DQ24
DDRB_DQ25
DDRB_DQ26
DDRB_DQ27
DDRB_DQ29
DDRB_DQ28
DDRB_DQ30
DDRB_DQ31

DDRB_DQ36
DDRB_DQ32
DDRB_DQ39
DDRB_DQ35
DDRB_DQ33
DDRB_DQ37
DDRB_DQ34
DDRB_DQ38

DDRB_DQ41
DDRB_DQ44
DDRB_DQ43
DDRB_DQ47
DDRB_DQ45
DDRB_DQ40
DDRB_DQ46
DDRB_DQ42

DDRB_DQ54
DDRB_DQ53
DDRB_DQ50
DDRB_DQ52
DDRB_DQ49
DDRB_DQ48
DDRB_DQ51
DDRB_DQ55

DDRB_DQ60
DDRB_DQ57
DDRB_DQ58
DDRB_DQ59
DDRB_DQ61
DDRB_DQ56
DDRB_DQ63
DDRB_DQ62

MB_ZVDDIO

DDRB_DQ[63..0] 12

1 2

RC10 39.2_0402_1%

2

DDRB_DQS[0..7]12

DDRB_DQS#[0..7]12

DDRB_DQS[0..7]

DDRB_DQS#[0..7]

1

DATA16--DATA23 Byte internal swap

DATA24--DATA31 Byte internal swap

DATA32--DATA39 Byte internal swap

DATA40--DATA47 Byte internal swap

DATA48--DATA55 Byte internal swap

DATA56--DATA63 Byte internal swap

+1.2V

A A

5

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2017/03/14

2017/03/14

2017/03/14

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered D ate

Deciphered D ate

Deciphered D ate

2

2017/03/14

2017/03/14

2017/03/14

Title

FT4 (MEM)

FT4 (MEM)

FT4 (MEM)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

S145AST

S145AST

S145AST

Thursday, October 25, 2018

Thursday, October 25, 2018

Thursday, October 25, 2018

5 50

5 50

1

5 50

0.2

0.2

0.2

1 4

Vinafix.com

2 3

5

1

CC1286

2

@

0.01U_0201_25V6-K

APU_PWROK

RPC 10
1K_0404_4P2R_5%

STN@

1

1

CC1287

2

@

@

0.01U_0201_25V6-K

1

2

2

G1

D16S1

QC6A
PJT7838_SOT363-6

STN@

1

CC1288

2

0.01U_0201_25V6-K

CC1276

0.01U_0201_25V6-K

EMC_NS@

+1.8VS+1.8VS

5

G2

4

D23S2

QC6B
PJT7838_SOT363-6

STN@

APU_SVT49
AP U _ S VC49
AP U _ S VD49

H_P RO CH OT #35,46

1000P_0402_25V7-K

+3VALW_APU

EC_SMB_CK3

EC_SMB_DA3

RC249 0_0402_5%
RC213 22_0402_5%
RC215 22_0402_5%

RC31 0_0402_5%

AP U _ S VT _ L

12

CC21 0

@

1 2
1 2
1 2

1 2

APU_PWROK49

EC_SMB_CK3 16,30,35

EC_SMB_DA3 16,30,35

AP U _ S VT

AP U _ S VC

AP U _ S VD

+1.8VS

12

RC18
300_0402_5%

D D

C C

B B

AP U _ R S T #

PLACE CC16 CAPS CLOSE TO APU,CRB reserve 27pf

1

CC16
56P_0402_50V8-J

2

@

+1.8VS

12

RC19
300_0402_5%

AP U _ P W R O K

PLACE CC17 CAPS CLOSE TO APU,CRB reserve 27pf

1

CC17
56P_0402_50V8-J

2

@

AP U _ S I C

AP U _ S I D

With HDT+ Header

+1.8VS

RC7
1K_0402_5%

1 2

AP U _ T R S T #

A A

RC76 33_0402_5%HD T@

2

CC84

0.01U_6.3V_K_X7R_0201

1

1 2

5

1 8

2 7

3 6

4 5

APU_TRST#_R

RPC 17
10K_0804_8P4R_5%

HDT@

JHDT1

@

1

1

3

3

5

5

7

7

9

9

10

11

11

12

13

13

14

15

15

16

17

17

18

19

19

20

SAMTE_ASP-136446-07-B

2

4

6

8

2

4

6

8

10

12

14

16

RC27 3 33_0402_5%HD T@

18

20

AP U _ S VT _ L
APU_SVC_L
APU_SVD_L

12

RC23 9100K_0402_5% @

AP U _ T C K

AP U _ T M S

AP U _ T D I

AP U _ T D O

APU_PWROK_BUF

APU_RST#_BUF

APU_DBRDY

1 2

APU_TEST19_PLLTEST0

APU_TEST18_PLLTEST1

4

AP U _ S I C
AP U _ S I D
AL E R T #
APU_PROCHOT#_R

APU_PWROK
AP U _ R S T #

AP U _ T D I
AP U _ T D O
AP U _ T C K
AP U _ T M S
APU_TRST#
APU_DBRDY
APU_DBREQ#

Cor e_ ty p e

APU_DBREQ#

4

AE34
AM15
AM17
AM19

AP13
AP15
AP17
AR13
AR15
AR17

AU13
AU15
AU17

AV11
AV13
AV15
AV17

H27
E27
D27

B30
B29
A30
A31

G25

D29

B25
A27
B27
B26
A29
A26
A25

D9
D11
D13

E4
E31
H11
H13
L11

AN8

AU4

AV7
AV9

AY3
AY7

DISPLAY/SVI2/JTAG/TEST

SVT
SVC
SVD

SIC
SID
ALERT_L
PROCHOT_L

PWROK
RESET_L

TD I
TD O
TC K
TM S
TRST_L
DBRDY
DBREQ_L

RSVD_1
RSVD_2
RSVD_3
RSVD_4
RSVD_5
RSVD_6
RSVD_7
RSVD_8
RSVD_9
RSVD_10
RSVD_11
RSVD_12
RSVD_13
RSVD_14
RSVD_15
RSVD_16
RSVD_17
RSVD_18
RSVD_19
RSVD_20
RSVD_21
RSVD_22
RSVD_23
RSVD_24
RSVD_25
RSVD_26
RSVD_27
RSVD_28
RSVD_29
RSVD_30
RSVD_31

@

RPC 5

1K_0804_8P4R_5%

2

CC21 3

HDT@

0.01U_6.3V_K_X7R_0201

1

UC2C

DP_VARY_BL

DP_AUX_ZVSS

DP_STEREOSYNC/TEST36

VDDCR_CPU_SENSE

VDDCR_NB_SENSE

VDDIO_MEM_S3_SENSE

VDDP_SENSE

VSS_SENSE_A

FT4 REV 0.93

VSS_SENSE_B

AMD-STONEY-FT4_BGA769

+1.8VS+1.8VS

18
27
36
45

AP U _ P W R O K

AP U _ R S T #

APU_TDIAP U _ D B R E Q #

DP_BLON

DP_DIGON

DP_ZVSS

DP0_AUXP
DP0_AUXN

DP0_HPD

DP1_AUXP
DP1_AUXN

DP1_HPD

DP2_AUXP
DP2_AUXN

DP2_HPD

DP0_TXP0
DP0_TXN0
DP0_TXP1
DP0_TXN1
DP0_TXP2
DP0_TXN2
DP0_TXP3
DP0_TXN3

DP1_TXP0
DP1_TXN0
DP1_TXP1
DP1_TXN1
DP1_TXP2
DP1_TXN2
DP1_TXP3
DP1_TXN3

DP2_TXP0
DP2_TXN0
DP2_TXP1
DP2_TXN1
DP2_TXP2
DP2_TXN2
DP2_TXP3
DP2_TXN3

TE S T 4
TE S T 5
TE S T 6

TE S T 9
TE S T 1 0
TE S T 1 4
TE S T 1 5
TE S T 1 6
TE S T 1 7
TE S T 1 8
TE S T 1 9

TEST28_H

TEST28_L

TE S T 3 1

TE S T 4 1

0.1U_0201_6.3V6-K

B23
B24
A24

D21
B18

G15
H15
D15

G17
H17
D17

G19
H19
D19

A9
B9
A10
B10
A11
B11
A12
B12

A14
B14
A15
B15
A16
B16
A17
B17

A19
B19
A20
B20
A21
B21
A22
B22

H29
G29
H25
R32
N32
G21
H21
D23
E23
A28
B28
N8
N10
H31
D25
B31

D31
E33
D35
AM21

D33
AM23

UC6

3

2A

2

GND

1

1A

2

1

HDT@

CC21 2

0.01U_0201_10V6K

@

DP_ENBKL
DP_ENVDD
DP_EDP_PWM

DP_150_ZVSS
DP_2K_ZVSS

APU_EDP_AUX
APU_EDP_AUX#
APU_EDP_HPD

APU_DDC_CLK
APU_DDC_DATA
APU_HDMI_HPD

APU_EDP_TX0+
APU_EDP_TX0­APU_EDP_TX1+
APU_EDP_TX1-

APU_HDMI_TX2+
APU_HDMI_TX2­APU_HDMI_TX1+
APU_HDMI_TX1­APU_HDMI_TX0+
APU_HDMI_TX0­APU_HDMI_CLK+
APU_HDMI_CLK-

TES T 5

TES T 9
TES T 1 0
APU_TEST14_BP0
APU_TEST15_BP1
APU_TEST16_BP2
APU_TEST17_BP3
APU_TEST18_PLLTEST1
APU_TEST19_PLLTEST0
APU_TEST28_H_PLLCHARZ
APU_TEST28_L_PLLCHARZ
APU_TEST31_MEM_TEST
APU_TEST36_STEREOSYNC
TES T 4 1

APU_VDDCORE_SEN_H
APU_VDDNB_SEN_H
VDDIO_MEM_S3_SENSE
VDD_095_FB_H

APU_VSS_SEN_L
VSS_SENSE_B

1

CC25

2

2Y

VCC

1Y

SN74LVC2G07YZPR_WCSP6HD T@

3

1 2

RC12 150_0402_1%
RC55 2K_0402_1%

1 2

APU_EDP_AUX 23
APU_EDP_AUX# 23
APU_EDP_HPD 23

APU_DDC_CLK 24
APU_DDC_DATA 24
APU_HDMI_HPD 24

AP U _ E D P _ T X 0 + 23

APU_EDP_TX0- 23

AP U _ E D P _ T X 1 + 23

APU_EDP_TX1- 23

APU_HDMI_TX2+ 24

APU_HDMI_TX2- 24

APU_HDMI_TX1+ 24

APU_HDMI_TX1- 24

APU_HDMI_TX0+ 24

APU_HDMI_TX0- 24
APU_HDMI_CLK+ 24
APU_HDMI_CLK- 24

TC1 4 @

1

TC8 0@

1
1

TC8 1@

RC21 1K_0402_5%@

1 2

TC1 8@

1

1 2

RC23 1K_0402_5%@
RC24 1K_0402_5%@

1 2

TC2 1@

1
1

TC2 3@
TC2 5@

1

TC7 8@

1

APU_VDDCORE_SEN_H 49
APU_VDDNB_SEN_H 49

1

@
@

1

TC7 6
TC2 6

1 2

RC23 6 0_0402_5%

TC7 7@

1

+1.8VS+1.8VS

12

RC32
300_0402_5%

HDT@

4

5

6

3

12

RC36
300_0402_5%

HDT@

APU_RST#_BUF

APU_PWROK_BUF

2

APU_DDC_CLK
APU_DDC_DATA

APU_EDP_HPD

eDP

AL E R T #
APU_PROCHOT#_R

HDMI

To EDP panel

eDP

+3VALW_APU

HDMI

DP_EDP_PWM

RPC 14 1K_0404_4P2R_5%

14
23

RC28 1K_0402_5%

1 2
1 2

RC27 1K_0402_5%

@

AP U _ V D D _ S E N _ L 49

APU_VDDNB_SEN_H

APU_VDDCORE_SEN_H

APU_VDD_SEN_L

APU_TEST31_MEM_TEST

1

1

1

+1.8VS

TC2 7@

TC2 8@

TC2 9@

@

@

1 2

1 2

RC27 4

39.2_0402_1%

RC27 5

39.2_0402_1%

+1.8VS

DP_ EN VDD

DP_ENBKL

Reserve follow CRB

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.

2017/03/14

2017/03/14

2017/03/14

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2

RC11
100K_0402_5%

RC13
100K_0402_5%

@

2

G1

+3VALW_APU

G1

12

12

LCD Power IC can change for PCH_ENVDD for cost down

+3VALW_APU

2

RC14
100K_0402_5%

@

G1

12

PCH_ENBKL con EC 1.8V level GPI pin cost down

2017/03/14

2017/03/14

2017/03/14

+3VS_APU

RC71
10K_0402_5%

1 2

5

G2

6

D1

QC8A
PJT7838_SOT363-6

S1

1

RC20 5 0_0402_5%@

1 2

+3VS_APU

RC73
10K_0402_5%

@

1 2

5

G2

6

D1

QC9A
PJT7838_SOT363-6

@

S1

1

1 2

RC20 6 0_0402_5%

+3VS_APU

1 2

RC75
10K_0402_5%

@

3

1 2

5

G2

6

4

D1

QC10A
PJT7838_SOT363-6

@

S1

1

RC20 7 0_0402_5%

1 2

1

RPC 18

1 4
2 3

2.2K_0404_4P2R_5%

RC35 100K_0402_5%

1 2

RPC 11

23
14

1K_0404_4P2R_5%

12

RC70

4.7K_0402_5%

3

D2

QC8B
PJT7838_SOT363- 6

S2

4

12

RC74

4.7K_0402_5%

@

3

D2

QC9B
PJT7838_SOT363- 6

@

S2

4

RC77

2.2K_0402_5%

@

D2

QC10B
PJT7838_SOT363-6

@

S2

Title

Title

Title

FT4 (DISPLAY/CLK/MISC)

FT4 (DISPLAY/CLK/MISC)

FT4 (DISPLAY/CLK/MISC)

Size Documen t Number Rev

Size Documen t Number Rev

Size Documen t Number Rev

Cus t om

Cus t om

Cus t om

Date: Sheet of

Date: Sheet of

Date: Sheet of

+3VS_APU

PCH_EDP_PWM 23

PCH_ENVDD 23

PCH_ENBKL 2 3

S145AST

S145AST

S145AST

Thursday, October 25, 2018

Thursday, October 25, 2018

Thursday, October 25, 2018

1

+1.8VS

6 50

6 50

6 50

0.2

0.2

0.2

5

Vinafix.com

PLT_RST#15,26,29,31,35

D D

EC_RSMRST#35

12

RC66
100K_0402_5%@

12

RC43
100K_0402_5%@

LRB751V-40T1G_SOD323-2

RC38 33_0402_5%

1

CC19
150P_25V_J_NPO_0402

2

1 2

RC247 0_0402_5%

DC1

1 2

@

1 2

with QC16,QC17, EC must set EC_RSMRST# and EC_SYS_PWRGD reversed compare to DC1 and DC2

C C

EC_SYS_PWRGD35

PCIE_WAKE#_RA

RC88 0_0402_5%@

AGPIO5

SDM10U45LP-7_DFN1006-2-2

+3VALW_APU

RC84

B B

2.2K_0402_5%

@

1 2

RC195
15K_0402_5%

1 2

1 2

2

@

0_0402_5%

2 1

@

1 2

1 2

12

RC82
100K_0402_5%@

1

RC92

DC3

RC85
1K_0402_5%

@

RC196
15K_0402_5%

1 2

RC95 0_0402_5%

DC2

1 2

LRB751V-40T1G_SOD323-2

PCIE_WAKE# 31,35

RC20

2.2K_0402_5%

@

1 2

TEST0
TEST1
TEST2

RC197
15K_0402_5%

1 2

@

PCIE_RST#_R

+1.8VALW

Connected to 10-ms RC-delay circuit on VDD_18_S5 power rail.
(CRB PWR Dealy: 22K/0.1uF)

12

RC53
10K_0402_5%

RSMRST#_R

+3VS_APU

12

1

CC21

0.1U_0201_6.3V6-K

2

RC72
10K_0402_5%

@

SYS_PWRGD_R

1

CC22

0.1U_0201_6.3V6-K

2

PBTN_OUT#35

PM_SLP_S3#35
PM_SLP_S5#35

Add USB_OC3# for USB2.0 port3

Connect TouchPad to I2C port0 following CRB 10/28

DC4

SYS_PWRGD_RSYS_RESET#

1 2

LRB751V-40T1G_SOD323-2

1

CC38

0.1U_0201_6.3V6-K

2

@

PXS_PWREN_R/PXS_RST#_R/VR_VGA_PWRGD internal pull up 40k

+3VS_APU

5

PXS_PWREN_R

VR_VGA_PWRGD

PXS_PWREN_R

VR_VGA_PWRGD

@

HDA_RST# HDA_RST_AUDIO#
HDA_SYNC

HDA_SDOUT

For EMI

1

CC4222
2P_25V_NPO_0201

2

Close to PCH

1 8
2 7
3 6
4 5

1 2

RC98 10K_0402_5%PX@

1 2

RC100 10K _0402_5%@

1 2

RC101 100K _0402_5%@

1 2

RC104 2K _0402_5%UMA @

A A

VR_VGA_PWRGD

1

CC4223

0.1U_0201_6.3V6-K

2

@

4

RC191 0_0402_5%

SYS_RESET#11

PM_SLP_S3#

RC193 0_0402_5%

PM_SLP_S5#

RC194 0_0402_5%

APU_S5_MUX_CTRL9

AC_PRESENT35

SSD_1_CLKREQ#29
PCH_WLAN_OFF#31

WLAN_CLKREQ#31

PCH_BT_OFF#31

GPU_CLKREQ#16

USB_OC1#25
USB_OC2#25
USB_OC3#25

HDA_SDIN036

RC201 0_0402_5%

TP_I2C0_SCL_R36

TP_I2C0_SDA_R36

Max ESR < 65K ohm !!

RPC21

1K_0804_8P4R_5%

For EMI For EMI

HDA_BITCLK HDA _SYNC HDA_SDOUTHDA_SDIN0_R

1

CC4220
56P_50V_J_NPO_0201

2

EMC@

Close to PCH

4

RC40

RC39

10K_0402_5%

10K_0402_5%

UMA@

TS @

1 2

BOARD_ID0
BOARD_ID1
BOARD_ID2
BOARD_ID3

1 2

1 2
1 2

TC 9 0 @

1 2

1 2

RC47

RC48

2K_0402_5%

2K_0402_5%

NOTS@

PCIE_RST#_R

RSMRST#_R

PWRBTN#_RPBTN_OUT#
SYS_PWRGD_R
SYS_RESET#
PCIE_WAKE#_RA

PM_SLP_S3#_R
PM_SLP_S5#_R
AGPIO10

TEST0
TEST1
TEST2

AC_PRESENT
BOARD_ID0
BOARD_ID1
BOARD_ID3
ODD_E N

SSD_1_CLKREQ#
PCH_WLAN_OFF#
WLAN_CLKREQ#
PCH_BT_OFF#
GPU_CLKREQ#

BOARD_ID2
USB_OC1#
USB_OC2#
USB_OC3#

HDA_BITCLK
HDA_SDIN0_R
HDA_SDIN1
HDA_SDIN2
HDA_RST#
HDA_SYNC
HDA_SDOUT

TP_I2C0_SCL_R
TP_I2C0_SDA_R

I2C1SCL
I2C1SDA

1

CC24

2

1

1 2

32K_X1

32K_X2

20P_0402_50V8

PX@

1 2

APU_S5_MUX_CTRL

1

RPC3

1 4
2 3

10K_0404_4P2R_5%

RC102

1 2

20M_0402_5%

YC1

1 2

32.768KHZ_12.5PF_202740-PG14

1

CC23

2

20P_0402_50V8

TC 8 7 @

HDA_SYNC_AUDIO36
HDA_SDOUT_AUDIO36
HDA_BITCLK_AUDIO36

1

CC4221

@

2P_25V_NPO_0201

2

Close to PCH Close to PCH

+3VALW_APU

AE4

AG1

AD2
AE2
AF1
AE7

AC2
AG4
AB1
AA7

AF2
AE1
AC8

AH2
AA4
AG8
AL5
AE8

AY32
AY31
AV29
AP31
AV35

AB2
AG2
AJ1
AH1

AY6
BA6
AY5
BA5
AY4
BA3
BA4

AY22
BA22
AU19
AV19

BA2

AY2

3

RC41

RC1660

10K_0402_5%

10K_0402_5%

BD15@

RC49
2K_0402_5%

BD14@

For EMI

1

CC4219
2P_25V_NPO_0201

2

3

1 2

1 2

@

RC1659
2K_0402_5%

@

ACPI/SD/AZ/GPIO/RTC/MISC

HDA_RST#
HDA_SYNC
HDA_SDOUT
HDA_BITCLK

1 2

1 2

PCIE_RST_L/EGPIO26

RSMRST_L

PWR_BTN_L/AGPIO0
PWR_GOOD
SYS_RESET_L/AGPIO1
WAKE_L/AGPIO2

SLP_S3_L
SLP_S5_L
S0A3_GPIO/AGPIO10
S5_MUX_CTRL/EGPIO42

TEST0
TEST1/TMS
TEST2

AC_PRES/USB_OC4_L/IR_RX0/AGPI O23
IR_TX0/USB_OC5_L/AGPIO13
IR_TX1/USB_OC6_L/AGPIO14
IR_RX1/AGPIO15
IR_LED_L/LLB_L/AGPIO12

CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/AGPIO92
CLK_REQ1_L/AGPIO115
CLK_REQ2_L/AGPIO116
CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/EGPIO131
CLK_REQG_L/OSCIN/EGPIO132

USB_OC0_L/TRST_L/AGPIO16
USB_OC1_L/TDI/AGPIO17
USB_OC2_L/TCK/AGPIO18
USB_OC3_L/TDO/AGPIO24

AZ_BITCLK/I2S_BCLK_MIC
AZ_SDIN0/I2S_DATA_MIC 0
AZ_SDIN1/I2S_LR_PLAYBACK
AZ_SDIN2/I2S_DATA_PLAYBACK
AZ_RST_L/I2S_LR_MIC
AZ_SYNC/I2S_BCLK_PLAYBACK
AZ_SDOUT/I2S_DATA_MIC 1

I2C0_SCL/EGPIO145
I2C0_SDA/EGPIO146
I2C1_SCL/EGPIO147
I2C1_SDA/EGPIO148

X32K_X1

X32K_X2

@

RPC4

1 8
2 7
3 6
4 5

33_0804_8P4R_5%

@

2

1

0

1

AGPIO3
AGPIO4
AGPIO5

AGPIO8
AGPIO9

AGPIO40

HVBEN_L

RTCCLK

BOARD

BOARD_ID1

Config.

DIS

UMA 1

BA28
AY29
AY13
BA14
AY15
BA29

AY14
BA13
BA16
AY16

AY33
BA32

AC5
AC4

AJ7
AK2
AK1
AL4
AJ2
AJ4
AG5
AD1

AJ8
AR29
AP29
AU35

AV33
AU33

AP23
AP25
AR25
AV25
AU23

AP21
AV21
AP19
AV23
AR21

AP27

AN4

0

1 2

RC1667 0_0402_5%PX@

EGPIO101
SD_PWR_CNTL

1

ODD_DETECT#

1
1
1

SD_LED

1 2

RC1670 0_0402_5%@

SD_DATA0_R

1 2

RC1673 0_0402_5%

SD_DATA1_R

1

SD_DATA2_R

1

SD_DATA3_R

1

APU_SMB_CLK
APU_SMB_DATA

RPC2

1 4

SCL1

2 3

SDA1

@

10K_0404_4P2R_5%

AGPIO5

PCH_TP_INT#_L
AGPIO8

PCH_PWRBT#

BLINK
VR_VGA_PWRGD

PXS_PWREN_R
PCH_TP_INT#_R PCH_TP_INT#

APU_UART0_CTS#
APU_UART0_RXD
APU_UART0_RTS#
APU_UART0_TXD

RC109 1K _0402_5%PX@

RC1662

PXS_RST# change from AGPIO76 to EGPIO101

TC 4 4@
TC 8 9@
TC 4 5@
TC 5 9@

SSD_SATA_PCIE_DET1#

APU_SSD_RST#

TC 6 3@
TC 6 4@

add APU_SSD_RST#

TC 6 5@

APU_SMB_CLK 12,31
APU_SMB_DATA 12,31

AGPIO3 11

1

TC 8 3@

USBDEBUG 25

1 2

RC1663 0_0402_5%

1

TC 9 2@

PCH_PWRBT# 35

VR_VGA_PWRGD 15,48

PCH_BEEP 36

GATEA2 0 35

1 2

1

2

@

0_0402_5%

reserve UART0 for BIOS debug

PCH_SPI_PIRQ# 26

delete APU_SHUTDOWN# signal for Stoney FT4

HVB_EN

APU_S5_MUX_CTRL 100K pull high follow CRB

BLINK isn't strap pin, don't need pull high

HVB_EN 11,35

SUSCLK 11,29,31

PXS_RST# 8,15

add USBDEBUG

BOARD

BOARD_ID0

Config.

TS

NOTS 0

BOARD

BOARD_ID3

Config.
14'

15'

UC2D

SD_WP/EGPIO101

SD_PWR_CTRL/AGPIO102

SD_CD/AGPIO25

SD_CLK/EGPIO95

SD_CMD/EGPI O96

SD_LED/EGPIO93

SD_DATA0/EGPIO97
SD_DATA1/EGPIO98
SD_DATA2/EGPIO99

SD_DATA3/EGPIO100

SCL0/I2C2_SCL/EGPIO113
SDA0/I2C2_SDA/EGPIO114

SCL1/I2C3_SCL/AGPIO19

SDA1/I2C3_SDA/AGPIO20

AGPIO6/LDT_RST_L

AGPIO7/LDT_PWROK

BLINK/USB_OC7_L/AGPIO11

GENINT2_L/AGPIO90

SPKR/AGPIO91

GA20IN/AGPIO126

FANIN0/AGPIO84

FANOUT0/AGPIO85

UART0_CTS_L/EGPIO135

UART0_RXD/EGPIO136

UART0_RTS_L/EGPIO137

UART0_TXD/EGPIO138

UART0_INTR/AGPIO139

UART1_CTS_L/BT_I2S_BCLK/EGPIO140

UART1_RXD/BT_I2S_SDI/ EGPIO141

UART1_RTS_L/EGPIO142

UART1_TXD/BT_I2S_SDO/EGPIO143

UART1_INTR/BT_I2S_LRC LK/AGPIO144

FT4 REV 0.93

AMD-STONEY-FT4_BGA769

follow Checklist, HDA_BITCLK PD reserve

CRB: CARRIZO NEED 10K PD ON UNUSED SDIN
DG: 10K PD

Securi ty Cl assific ation

Securi ty Cl assific ation

Securi ty Cl assific ation

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2017/03/14

2017/03/14

2017/03/14

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciph ered Date

Deciph ered Date

Deciph ered Date

2

SSD_SATA_PCIE_DET1# 29

APU_SSD_RST# 29

PCH_TP_INT# 36

PXS_PWREN 47,48

2017/03/14

2017/03/14

2017/03/14

1

+3VS_APU

PCH_TP_INT#

APU_SSD_RST#

APU_SMB_CLK
APU_SMB_DATA

SSD_1_CLKREQ#
WLAN_CLKREQ#
PCH_BT_OFF#
PCH_WLAN_OFF#

PCH_PWRBT#

GPU_CLKREQ#

GATEA 20

PXS_RST#

TP_I2C0_SCL_R

TP_I2C0_SDA_R

APU_UART0_CTS#
APU_UART0_RXD
APU_UART0_RTS#
APU_UART0_TXD

PCIE_WAKE#_RA
AC_PRESENT

PBTN_ OUT#

USB_OC1#
USB_OC2#
USB_OC3#

PM_SLP_S3#
PM_SLP_S5#

APU_S5_MUX_CTRL

BLINK

APU_SSD_RST#

PCH_TP_INT#

SD_LED

AGPIO10

GPU_CLKREQ#

HDA_BITCLK

HDA_SDIN0_R

RSMRST#_R
SYS_PWRGD_R

HDA_SDIN2
HDA_SDIN1

Title

Title

Title

FT4 (GEVENT/GPIO/SD/AZ)

FT4 (GEVENT/GPIO/SD/AZ)

FT4 (GEVENT/GPIO/SD/AZ)

Size Docum ent Number Rev

Size Docum ent Number Rev

Size Docum ent Number Rev

Custom

Custom

Custom

Thursday, October 25, 2018

Thursday, October 25, 2018

Thursday, October 25, 2018

Date: Sheet of

Date: Sheet of

Date: Sheet of

1 2

RC1655 10K_0402_5%

1 2

RC1671 10K_0402_5%

RPC9

23
14

2.2K_0404_4P2R_5%
RPC6

18
27
36
45

10K_0804_8P4R_5%

1 2

RC287 10K_0402_5%@

1 2

RC64 10K_0402_5%UMA@

1 2

RC276 10K_0402_5%

2

1

RC280 10K_0402_5%@

2

1

RC281 10K_0402_5%PX@

RPC19

1 4
2 3

2.2K_0404_4P2R_5%

2
2
2
2

RPC15

1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

RPC22

1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

1 2
1 2

1 2

STN@

1 2

1 2

1 2

1 2

1 2

1 2

1 2
1 2

RPC24

1 4
2 3

1/16W_100K_5%_4P2R_0404
RPC23

1 4
2 3

10K_0404_4P2R_5%

S145AST

S145AST

S145AST

1

1
1
1
1

7 50

7 50

7 50

RC3136 1K_0402_1%@
RC3137 1K_0402_1%@
RC3138 1K_0402_1%@
RC3139 1K_0402_1%@

RC203 2.2K_0402_5%@
RC208 2.2K_0402_5%@

RC248 100K_0402_5%

RC277 10K_0402_5%@

RC1672 10K_0402_5%@

RC1661 10K_0402_5%@

RC97 10K_0402_5%@

RC80 10K_0402_5%@

RC65 2K_0402_5%PX@

RC1675 10K_0402_5%@
RC91 10K_0402_5%@

+1.8VS

+3VALW_APU

0.2

0.2

0.2

5

Vinafix.com

SATA_PTX_DRX_P034

RPC13

23
14

D D

C C

B B

10K_0404_4P2R_5%

STN@

1 2

RC147 10K_0402_5%

Add 0ohm for LPC DAT, cause
LPC data signal overshoot/undershoot issue

APU_LPC_RST#35

1 2

RC140 1M_0402_5%

YC2

1

OSC 1

1

2

NC12OSC 2

48MHZ 10PF X1E000021083400
CC28
12P_0402_50V8-J

NC2

SATA0_DEVSLP_R
EGPIO70

APU_TS_ON#

CLK_PCIE_GPU15

CLK_PCIE_GPU#15

CLK_PCIE_SSD29

CLK_PCIE_SSD#2 9

CLK_PCIE_WLAN31

CLK_PCIE_WLAN#31

RC149 10K_0402_5%

48M_X1

48M_X2

4

3

1

2

HDD

+0.95VS

CLK_PCI_EC11,35
LPC_CLK111

1 2

1 2

RC46 33_0402_5%

1

CC20
150P_25V_J_NPO_0402

2

CC29
12P_0402_50V8-J

SATA_PTX_DRX_N034

SATA_PRX_DTX_N034
SATA_PRX_DTX_P034

RC113 1K_0402_1%
RC114 1K_0402_1%

CLK_PCIE_GPU#

CLK_PCIE_SSD# CLK_PCIE_SSD#_R

CLK_PCIE_WLAN#

RC126 0_0402_5%
RC127 0_0402_5%

LPC_FRAME#11, 35

LPC_AD035
LPC_AD135
LPC_AD235
LPC_AD335

LPC_RST#_R

8M ROM

with BOM strcture control, UC3 change to 1.8V SPI ROM for CZ

4

SATA_PTX_DRX_P0
SATA_PTX_DRX_N0

SATA_PRX_DTX_N0
SATA_PRX_DTX_P0

X14M_25M_48M_OSC

1 2
1 2
1 2
1 2
1 2

1

UC3

1

/CS

2

DO( I O1 )

3

/WP(IO2)

4

GND

W25Q64FWSSIQ_SO 8

SATA_CALRN
SATA_CALRP

APU_TS_ON#
SATA0_DEVSLP_R
EGPIO70

CLK_PCIE_GPU_RCLK_PCIE_GPU
CLK_PCIE_GPU#_R

CLK_PCIE_SSD_RCLK_PCIE_SSD

CLK_PCIE_WLAN_RCLK_PCIE_WLAN
CLK_PCIE_WLAN#_R

48M_X1

48M_X2

LPCCLK0
LPCCLK1

LPC_RST#_R

AGPIO21

ODD_DA#

/HOLDor/RESET(IO3)

1 2
1 2

1 2

RC117 0_0402_5%

1 2

RC118 0_0402_5%

1 2

RC1665 0_0402_5%

1 2

RC1664 0_0402_5%

1 2

RC119 0_0402_5%

1 2

RC120 0_0402_5%

1

TC53 @

1 2
1 2

RC3144 0_0402_5%
RC3140 0_0402_5%
RC3141 0_0402_5%
RC3142 0_0402_5%
RC3143 0_0402_5%

EC_SCI#35

TC91 @

SERIRQ35

SPI_CS0#
SPI_SO SPI_HOLD#

FRAME#
LAD0
LAD1
LAD2
LAD3

VCC

CLK

DI (I O0 )

BA10

SATA_TX0P

AY10

SATA_TX0N

AY12

SATA_RX0N

BA12

SATA_RX0P

AY9

SATA_TX1P

BA9

SATA_TX1N

BA8

SATA_RX1N

AY8

SATA_RX1P

AU11

SATA_ZVSS

AP11

SATA_ZVDDP

AY30

SATA_ACT_L/AGPIO130

AV31

DEVSLP0/EGPIO67

AU31

DEVSLP1/EGPIO70

H2

GFX _CLK P

H1

GFX _CLK N

M2

GPP _CLK 0P

M1

GPP _CLK 0N

L2

GPP _CLK 1P

L1

GPP _CLK 1N

K2

GPP _CLK 2P

K1

GPP _CLK 2N

J2

GPP _CLK 3P

J1

GPP _CLK 3N

F2

X48M_X1

F1

X48M_X2

AU27

X25M_48M_OSC

BA25

LPCCLK0/EGPIO74

BA24

LPCCLK1/EGPIO75

AY24

LFRAME_L

BA26

LAD0

AY28

LAD1

AY25

LAD2

AY23

LAD3

AY27

LPC_RST_L

AY26

LPC_CLKRUN_L/AGPIO88

AC1

LPC_PD_L/AGPIO21

AA8

LPC_PME_L/AGPIO22

BA27

LPC_SMI_L/AGPIO86

AV27

SERIRQ/AGPIO87

@

8
7

SPI_CLKSPI_WP#

6

SPI_SI

5

+VCC_SPI

3

UC2E

CLK/SATA/USB/SPI/LPC

USBCLK/25M_48M_OSC

SPI_CLK/ESPI_CLK/EGPIO117

SPI_DO/ESPI_DAT0/EGPIO121

SPI_DI/ESPI_DAT1/EGPIO120

SPI_HOLD_L/ESPI_DAT3/E GPIO133

SPI_WP_L/ESPI_DAT2/EGPIO122

SPI_TPM_CS_L/AGPIO76

ESPI_ALERT_L/LDRQ0_L

ESPI_RESET_L/KBRST_L/AGPIO129

SPI_CS2_L/ESPI_CS_L/EGPIO119

FT4 REV 0.93

AMD-STONEY-FT4_BGA769

1

CC27

0.1U_0201_6.3V6-K

2

USB_ZVSS

USB_HSD0P
USB_HSD0N

USB_HSD1P
USB_HSD1N

USB_HSD2P
USB_HSD2N

USB_HSD3P
USB_HSD3N

USB_HSD4P
USB_HSD4N

USB_HSD5P
USB_HSD5N

USB_HSD6P
USB_HSD6N

USB_HSD7P
USB_HSD7N

USB_SS_ZVSS

USB_SS_ZVDDP

USB_SS_0TXP
USB_SS_0TXN

USB_SS_0RXP
USB_SS_0RXN

USB_SS_1TXP
USB_SS_1TXN

USB_SS_1RXP
USB_SS_1RXN

USB_SS_2TXP
USB_SS_2TXN

USB_SS_2RXP
USB_SS_2RXN

SPI_CS1_L/EGPIO118

+VCC_SPI

SPI_WP#
SPI_HOLD#

SPI_CS0#

CLK_USB48M

AL8

USB_RCOMP

AN7

AW1
AW2

AV1
AV2

AU1
AU2

AT1
AT2

AR1
AR2

AP1
AP2

AN1
AN2

AM1
AM2

W4
W5

T1
T2

V2
V1

R1
R2

W2
W1

P1
P2

Y2
Y1

AY17
AY20
BA17
BA18
BA20
AY21
BA21

AY18
BA30
AY19

+VCC_SPI

RC138 10K_0402_5%

RC112 11.8K_0402_1%

USB20_P0
USB20_N0

USB20_P1
USB20_N1

USB20_P2
USB20_N2

USB20_P3
USB20_N3

USB20_P4
USB20_N4

USB20_P5
USB20_N5

USB20_P6
USB20_N6

USBSS_CALRN
USBSS_CALRP

USB30_TX_P0
USB30_TX_N0

USB30_RX_P0
USB30_RX_N0

USB30_TX_P1
USB30_TX_N1

USB30_RX_P1
USB30_RX_N1

SPI_CLK_R
SPI_SI_R
SPI_SO_R
SPI_HOLD#_R
SPI_WP#_R
SPI_CS0#_R
SPI_TPM_CS_R

1

EGPIO119

RC135 0_0402_5%@

RC192 0_0402_5%

RPC8

1 4
2 3

10K_0404_4P2R_5%

1 2

2

1

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

KBRST#

TC69@

Card Reader

Blue Tooth

Camera

LEFT USB (2.0)

LEFT USB (3.0) lower

LEFT USB (3.0) upper

Touch Screen

@

KBRST# 35

1 2

USB20_P0 36
USB20_N0 36

USB20_P1 31
USB20_N1 31

USB20_P2 23
USB20_N2 23

USB20_P3 25
USB20_N3 25

USB20_P4 25
USB20_N4 25

USB20_P5 25
USB20_N5 25

USB20_P6 23
USB20_N6 23

1 2

RC123 1K_0402_1%

1 2

RC124 1K_0402_1%

USB30_TX_P0 25
USB30_TX_N0 25

USB30_RX_P0 25
USB30_RX_N0 25

USB30_TX_P1 25
USB30_TX_N1 25

USB30_RX_P1 25
USB30_RX_N1 25

RC209 0_0402_5%
RC198 0_0402_5%
RC199 0_0402_5%
RC133 0_0402_5%
RC132 0_0402_5%
RC202 0_0402_5%
RC243 0_0402_5%TPM@
RC1674 0_0402_5%

TC54@

KBRST#

1 2

1 2

+VCC_SPI

1

USB3.0 port0 must map to USB2.0 port4,
USB3.0 port1 must map to USB2.0 port5,
USB3.0 port2 must map to USB2.0 port6

+0.95VALW

Connect the four USB 3.0 ports to onboard devices first
starting from the lower ports and then the remaining
ports can be used for routing to USB 3.0 connectors.
Less than four USB 3.0 ports can be utilized provided
the unused ports are higher-numbered consecutive

LEFT USB (3.0) lower

ports.
None of the four USB 3.0 ports can be configured
as USB 2.0 external ports.

LEFT USB (3.0) upper

SPI_CLK
SPI_SI
SPI_SO
SPI_HOLD#
SPI_WP#
SPI_CS0#

SPI_CS#_TPM

PXS_RST# 7,15

1 2

RC279 10K_0402_5%

+3VALW_APU

+1.8VS

2

SPI_CLK

SPI_CLK 26

SPI_SI 26
SPI_SO 26

SPI_CS#_TPM 26

1

RC14410K_0402_5% STN@

+3VS_APU

RC139
10_0402_5%

EMC_NS@

1 2

2

CC26
10P_0402_50V8J

EMC_NS@

1

EMC

KBRST#

EMC_NS@

1 2

CC1274

1000P_0402_25V7-K

A A

5

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEE RING DRAWING IS THE PROPRIETARY P ROPERTY OF LC FUTURE CENTER. AND CONT AINS CONFIDENTIAL

THIS SHEET OF ENGINEE RING DRAWING IS THE PROPRIETARY P ROPERTY OF LC FUTURE CENTER. AND CONT AINS CONFIDENTIAL

THIS SHEET OF ENGINEE RING DRAWING IS THE PROPRIETARY P ROPERTY OF LC FUTURE CENTER. AND CONT AINS CONFIDENTIAL
AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R& D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R& D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R& D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2017/03/14

2017/03/14

2017/03/14

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2017/03/14

2017/03/14

2017/03/14

Title

FT4 (SATA/USB/LPC/SPI)

FT4 (SATA/USB/LPC/SPI)

FT4 (SATA/USB/LPC/SPI)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

S145AST

S145AST

S145AST

Thursday, October 25, 2018

Thursday, October 25, 2018

Thursday, October 25, 2018

8 5 0

8 5 0

8 5 0

1

0.2

0.2

0.2

5

Vinafix.com

4

3

2

1

+1.2V

1

1

+1.2V

1

1

D D

SIVCD@

+0.95VS

1

CC222

CC221

2

SIVCD@

22UC_6.3VC_MC_X5RC_0603

C C

VCCRTC

RC231 10K_0402_5%

B B

+1.2V

CC168

A A

1

CC42

CC55

CC54

2

22UC_6.3VC_MC_X5RC_0603

1

1

CC223

2

2

SIVCD@

22UC_6.3VC_MC_X5RC_0603

1 2

1

1

CC169

2

2

0.22U_0201_6.3V6-K

SIVCD@

DECOUPLING BETWEEN PROCESSOR AND DIMMs
ACROSS VDDIO AND VSS SPLIT

CC56

2

2

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

1

1

CC174

CC224

CC225

2

2

SIVCD@

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

1

CC37

AP2138N-1.5TRG1_SOT23-3

2

1U_0402_6.3V6K

1

1

CC170

CC172

2

2

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

SIVCD@

5

1

1

1

CC58

CC57

CC59

2

2

2

SIVCD@

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

1

1

CC227

CC226

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

SIVCD@

UC5

1

Vi n

3

Vo u t

2

GND

1

1

CC176

CC179

2

2

SIVCD@

180P_50V_J_NPO_0402

1

1

CC60

2

2

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

1

1

CC228

2

2

1000P_16V_K_X7R_0402

1000P_16V_K_X7R_0402

RC6

+1.8VS

RC212 0_0402_5%

+RTCBATT

1

CC194

2

1U_0402_6.3V6K

180P_0402_50V8-J

1

CC53

2

SIVCD@

1

CC229

2

1 2

1K_0402_5%

1 2

1000P_16V_K_X7R_0402

CC258

22UC_6.3VC_MC_X5RC_0603

1

1

CC230

CC203

2

2

1000P_16V_K_X7R_0402

180P_50V_J_NPO_0402

CD@

+RTCBATT_APU+RTCBATT

CC192

+VDDIO_AZ_APU

12

JCMOS1
SHORT PADS

@

L2N7002KWT1G_SOT323-3

1

CC185

2

2

1U_0402_6.3V6K

CD@

1

CC220
47P_0402_50V8J

RF_NS@

2

0.1A

1

2

1U_0402_6.3V6K

0.2A

12

RC8
470_0603_5%

13

D

S

@

+APU_CORE_NB

1

CC207
10U_0603_6.3V6M

2

SDVCD@

1U_0402_6.3V6K

CC236

QC7

CC214

2

1

2

1U_0402_6.3V6K

@

EC_RTCRST#_ON

2

G

+0.775VALW

1

2

SDVCD@

4

CC165

1U_0402_6.3V6K

+APU_CORE

+0.95VALW

CC182

1

CC235

CC234

2

SIVCD@

1000P_16V_K_X7R_0402

CC208
10U_0603_6.3V6M

1

2

180P_50V_J_NPO_0402

1

CC215

2

1U_0402_6.3V6K

1

2

10U_0603_6.3V6M

1 2

1000P_0402_25V7-K

12

RC15
100K_0402_5%

@

+5VALW

CC209

SDVCD@

22A

1

CC216

2

SIVCD@

0.79A

1

CC219

2

1U_0402_6.3V6K

EC_RTCRST#_ON 35

1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

CC231

SIVCD@

1

CC137

2

180P_50V_J_NPO_0402

1 2

1000P_0402_25V7-K

UC7

1

2

3

G5018RD1U_TDFN8_3X3

STN@

+1.2V

+VDDCR_FCH_S5

+0.95VS

6.9A

VO U T _ 1

VI N 1 _ 1

VI N 1 _ 2

VO U T _ 2

VI N 2

VC C4EN

0.4A

GND

J35

3A

VDDIO_MEM_S3_1

L32

VDDIO_MEM_S3_2

L37

VDDIO_MEM_S3_3

N35

VDDIO_MEM_S3_4

R37

VDDIO_MEM_S3_5

U32

VDDIO_MEM_S3_6

U35

VDDIO_MEM_S3_7

W32

VDDIO_MEM_S3_8

W37

VDDIO_MEM_S3_9

AA 3 5

VDDIO_MEM_S3_10

AC 3 2

VDDIO_MEM_S3_11

AC 3 7

VDDIO_MEM_S3_12

AE 3 2

VDDIO_MEM_S3_13

AE 3 5

VDDIO_MEM_S3_14

AG 3 2

VDDIO_MEM_S3_15

AG 3 7

VDDIO_MEM_S3_16

AJ 3 2

VDDIO_MEM_S3_17

AJ 3 5

VDDIO_MEM_S3_18

AL 3 2

VDDIO_MEM_S3_19

AL 3 7

VDDIO_MEM_S3_20

A

R35

VDDIO_MEM_S3_21

K21

VD D C R _ C P U _ 1

K23

VD D C R _ C P U _ 2

K25

VD D C R _ C P U _ 3

K27

VD D C R _ C P U _ 4

K29

VD D C R _ C P U _ 5

K31

VD D C R _ C P U _ 6

N21

VD D C R _ C P U _ 7

N23

VD D C R _ C P U _ 8

N25

VD D C R _ C P U _ 9

N27

VDDCR_CPU_10

N29

VDDCR_CPU_11

N31

VDDCR_CPU_12

U23

VDDCR_CPU_13

U25

VDDCR_CPU_14

U27

VDDCR_CPU_15

U29

VDDCR_CPU_16

U31

VDDCR_CPU_17

AA 2 5

VDDCR_CPU_18

AA 2 7

VDDCR_CPU_19

AA 2 9

VDDCR_CPU_20

AA 3 1

VDDCR_CPU_21

AR 4

VD D C R _ F C H _ S 5 _ 1

AR 5

VD D C R _ F C H _ S 5 _ 2

AR 7

VD D C R _ F C H _ S 5 _ 3

AU 7

VD D C R _ F C H _ S 5 _ 4

AJ 1 1

VDDP_S5_1

AL 1 1

VDDP_S5_2

AL 1 3

VDDP_S5_3

AJ 2 1

VD D P _ 1

AJ 2 3

VD D P _ 2

AJ 2 5

VD D P _ 3

AJ 2 7

VD D P _ 4

AL 2 3

VD D P _ 5

AL 2 5

VD D P _ 6

AL 2 7

VD D P _ 7

AL 2 9

VD D P _ 8

AM 1 1

VDDBT_RTC_G

AM 1 3

VDDIO_AUDIO

@

8

7

APU_S5_MUX_CTRL

6

SEL

5

9

+0.95VALW

2.2U_0402_6.3V6M

+VDDCR_FCH_S5

UC2F

POWER

VDDCR_NB_1
VDDCR_NB_2
VDDCR_NB_3
VDDCR_NB_4
VDDCR_NB_5
VDDCR_NB_6
VDDCR_NB_7
VDDCR_NB_8

VDDCR_NB_9
VDDCR_NB_10
VDDCR_NB_11
VDDCR_NB_12
VDDCR_NB_13
VDDCR_NB_14
VDDCR_NB_15
VDDCR_NB_16
VDDCR_NB_17
VDDCR_NB_18
VDDCR_NB_19
VDDCR_NB_20
VDDCR_NB_21
VDDCR_NB_22
VDDCR_NB_23
VDDCR_NB_24
VDDCR_NB_25
VDDCR_NB_26
VDDCR_NB_27
VDDCR_NB_28
VDDCR_NB_29
VDDCR_NB_30
VDDCR_NB_31
VDDCR_NB_32
VDDCR_NB_33
VDDCR_NB_34
VDDCR_NB_35
VDDCR_NB_36
VDDCR_NB_37
VDDCR_NB_38
VDDCR_NB_39
VDDCR_NB_40
VDDCR_NB_41
VDDCR_NB_42
VDDCR_NB_43
VDDCR_NB_44
VDDCR_NB_45
VDDCR_NB_46
VDDCR_NB_47
VDDCR_NB_48
VDDCR_NB_49
VDDCR_NB_50

VDD_18_1
VDD_18_2

VDD_18_S5_1

VDD_18_S5_2

VDD_33_1
VDD_33_2

VDD_33_S5_1

VDD_33_S5_2

FT4 REV 0.93

AMD-STONEY-FT4_BGA769

2

2

CC1280

CC1281

1

1

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

EMC_NS@

EMC_NS@

EMC_NS@

APU_S5_MUX_CTRL 7

3

+APU_CORE_NB

18A

E9
E11
E13
E15
E17
E19
G7
J7
K11
K13
K15
K17
K19

ϮϯϳϮϯϴ^ƚƵĨĨĨŽƌ

L7

DƚĞƐƚĨĂŝůϭϬϭϲ

L10
L15
L17
N7
N11
N13
N15
N17
N19
R7
U7
U11
U13
U15
U17
U19
U21
W7
AA 1 1
AA 1 3
AA 1 5
AA 1 7
AA 1 9
AA 2 1
AA 2 3
AE 1 1
AE 1 3
AE 1 5
AE 1 7
AE 1 9
AE 2 1
AE 2 3
AE 2 5
AE 2 7
AE 2 9
AE 3 1

+1.8VS

AJ 1 5

1.5A

AL 1 7

AJ 1 3

0.5A

AL 1 5

AJ 1 9

0.2A

AL 2 1

+3VALW_A PU

AJ 1 7

0.2A

AL 1 9

2

2

CC1282

1

2.2U_0402_6.3V6M

EMC_NS@

2

2

CC1284

CC1283

1

1

1

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

EMC_NS@

EMC_NS@

1

1

CC162

CC217

2

2

10U_0603_6.3V6M

STN@

STN@

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRA WING IS THE PROPRIETARY PROP ERTY OF LC FUTURE CENTER. A ND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRA WING IS THE PROPRIETARY PROP ERTY OF LC FUTURE CENTER. A ND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRA WING IS THE PROPRIETARY PROP ERTY OF LC FUTURE CENTER. A ND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

+1.8VALW

CC1285

1U_0402_6.3V6K

CC218

SIVCD@

1

2

CC232

1U_0402_6.3V6K

SIVCD@

+APU_CORE_NB

EMC_PX@

1

CC252

2

CC233

1 2

1000P_0402_25V7-K

STN@

2017/03/14

2017/03/14

2017/03/14

1

1

CC237

CC238

2

2

EMC@

1000P_16V_K_X7R_0402

OK

+1.8VS

1

1

CC246

CC247

2

2

10U_0603_6.3V6M

1

CC253

2

1U_0402_6.3V6K

10U_0603_6.3V6M

1

2

1000P_16V_K_X7R_0402

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

1

1

CC240

CC241

CC239

2

2

CD@

1000P_16V_K_X7R_0402

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

CC245

1 2

1U_0402_6.3V6K

1000P_0402_25V7-K

SIVCD@

RC214 0_0402_5%

1 2

CC251

1 2

1000P_0402_25V7-K

SIVCD@

VDDCR_CPU

VDDCR_NB

VDDCR_GFX

VDDIO_MEM_S3

VDDCR_FCH_S5

VDDP

VDDP_GFX

VDDP_S5

VDD_18

VDD_18_S5

VDD_33

VDD_33_S5

VDDIO_AUDIO

VDDBT_RTC_G

Deciphered Date

Deciphered Date

Deciphered Date

2

1

CC242

2

SIVCD@

22UC_6.3VC_MC_X5RC_0603

+1.8VALW

1

CC249

2

10U_0603_6.3V6M

Design Guide CRBG FT4

7*22uf 0603
2*1uf 0402
1*180pf 0402
11*22uf 0603
1*1uf 0402
1*180pf 0402

9*22uf 0603
3*1uf 0402
3*180pf 0402
1*10uf 0402
2*1uf 0402
2*1000pf 0402
5*22uf 0603 2*10uf 0603 5*22uf 0603 2*10uf 0603
4*1000pf 0402
1*180pf 0402

1*10uf 0402
1*1uf 0402
1*1000pf 0402
1*10uf 0402
1*1uf 0402
1*1000pf 0402
1*10uf 0402
1*1uf 0402
1*1000pf 0402
1*10uf 0402
1*1uf 0402
1*1000pf 0402
1*10uf 0402
1*1uf 0402
1*1000pf 0402
1*10uf 0402
2*1000pf 0402

1*1000pf 0402

1

1

1

CC244

CC243

2

2

2

1U_0402_6.3V6K

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

1

CC248

CC250

1 2

2

1U_0402_6.3V6K

1000P_0402_25V7-K

SIVCD@

+3VS+3VS_APU

2017/03/14

2017/03/14

2017/03/14

1

1

1

CC145

2

1

CC199

2

2

@

@

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

CC254

1 2

1000P_0402_25V7-K

SIVCD@

Wednesday, October 31, 2018

Wednesday, October 31, 2018

Wednesday, October 31, 2018

1

CC200

2

0.22U_0201_6.3V6-K

11*22uf 0603
1*1uf 0402
1*180pf 0402
15*22uf 0603
8*0.22uf 0402 split *5
1*180pf 0402

9*22uf 0603 2*1uf 0402
split*4 0.22uf 0402
1*180pf 0402 split*2
2*10uf 0603
1*0.22uf 0402

4*10uf 0603
1*0.22uf 0402
1*180pf 0402

1*10uf 0603
1*0.22uf 0402

1*22uf 0603
1*10uf 0603

1*10uf 0603
1*0.22uf 0402

1*10uf 0603

1*10uf 0603
1*0.22uf 0402

3*1uf 0402

1*0.22uf 0402

S145AST

S145AST

S145AST

1

CC195

CC196

2

@

@

0.22U_0201_6.3V6-K

180P_50V_J_NPO_0402

follow CRB reserve

+3VALW_APU

1

1

CC256

CC255

2

2

1U_0402_6.3V6K

10U_0603_6.3V6M

11*22uf 0805
2*1uf 0402
1*180pf 0402
11*22uf 0603
1*1uf 0402
1*180pf 0402

9*22uf 0603 2*1uf 0402
split*4 0.22uf 0402
1*180pf 0402 split*2
1*10uf 0402
2*1uf 0402
2*1000pf 0402

4*1000pf 0402
1*180pf 0402

1*10uf 0402
1*1uf 0402
1*1000pf 0402
1*10uf 0402
1*1uf 0402
1*1000pf 0402
1*10uf 0402
1*1uf 0402
1*1000pf 0402
1*10uf 0402
1*1uf 0402
1*1000pf 0402
1*10uf 0402
1*1uf 0402
1*1000pf 0402
1*10uf 0402
2*1000pf 0402

1*1000pf 0402

Title

Title

Title

FT4 (POWER&DECOUPLING)

FT4 (POWER&DECOUPLING)

FT4 (POWER&DECOUPLING)

Size Docu ment Number Rev

Size Docu ment Number Rev

Size Docu ment Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

9 50

9 50

9 50

0.2

0.2

0.2

5

Vinafix.com

4

3

2

1

VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181

FT4 REV 0.93

UC2H

GND

AMD-STONEY-FT4_BGA 769

VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212

AU39
AW3
AW5
AW7
AW9
AW11
AW13
AW15
AW17
AW19
AW21
AW23
AW25
AW27
AW29
AW31
AW33
AW35
AW37
AW39
AW41
AY1
AY11
BA7
BA11
BA15
BA19
BA23
BA31
BA35
BA39

UC2G

VSS_215
VSS_214
VSS_213
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58

@

GND

VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98

VSS_99
VSS_10 0
VSS_10 1
VSS_10 2
VSS_10 3
VSS_10 4
VSS_10 5
VSS_10 6
VSS_10 7
VSS_10 8
VSS_10 9
VSS_11 0
VSS_11 1
VSS_11 2
VSS_11 3
VSS_11 4
VSS_11 5
VSS_11 6
VSS_11 7
VSS_11 8
VSS_11 9

FT4 REV 0.93

AMD-STONEY-FT4_BGA 769

L13
L19
L21
L23
L25
L27
L29
L31
L39
L41
N1
N2
N3
N39
R3
R11
R13
R15
R17
R21
R23
R25
R27
R29
R31
R39
R41
U1
U2
U3
U10
U39
W3
W10
W11
W13
W15
W17
W19
W21
W23
W25
W27
W29
W31
W39
W41
AA1
AA2
AA3
AA5
AA10
AA39
AC3
AC7
AC10
AC11
AC13
AC15
AC17
AC19

D D

C C

B B

AJ31

R19
H23

A13
A18
A23
A32
A35
A39

B13
B32
B39

C11
C13
C15
C17
C19
C21
C23
C25
C27
C29
C31
C33
C35
C37
C39
C41

E21
E25
E29
E35
E38
E39

G11
G13
G23
G27
G31
G35
G37
G39
G41

J39

A2
A8

B8

C3
C5
C7
C9

E1
E2
E3

G1
G2
G3

J3
J8

L3
L8

AC21
AC23
AC25
AC27
AC29
AC31
AC38
AC39
AC41

AE3

AE5
AE10
AE39

AG3

AG7
AG10
AG11
AG13
AG15
AG17
AG19
AG21
AG23
AG25
AG27
AG29
AG31
AG39
AG41

AJ3

AJ5
AJ10
AJ29
AJ39

AL1

AL2

AL3

AL7
AL10
AL31
AL39
AL41

AM25
AM27
AM29
AM31

AN3
AN5

AN39

AR3
AR11
AR19
AR23
AR27
AR31
AR39
AR41

AU3

AU9
AU21
AU25
AU29

@

A A

5

Security Clas sification

Security Clas sification

Security Clas sification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORI ZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFO RMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORI ZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFO RMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORI ZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFO RMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

2017/03/14

2017/03/14

2017/03/14

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

3

2017/03/14

2017/03/14

2017/03/14

2

Title

Title

Title

FT4 (VSS)

FT4 (VSS)

FT4 (VSS)

Size Docum ent Number Rev

Size Docum ent Number Rev

Size Docum ent Number Rev

Custo m

Custo m

Custo m

Thursday, October 25, 2018

Thursday, October 25, 2018

Date : Sheet of

Date : Sheet of

Date : Sheet of

Thursday, October 25, 2018

S145AST

S145AST

S145AST

10 50

10 50

10 50

1

0.2

0.2

0.2

5

Vinafix.com

D D

LPC_FRAME#8,35

LPC_CLK18

CLK_PCI_EC8,35

AGPIO37

SYS_RESET#7

SUSCLK7,29,31

4

+3VS +3VS +3VS +3VALW_APU +3VALW_APU +3VALW_APU+3VALW_APU+3VALW_APU +3VALW_APU +3VS_APU

12

RC152
10K_0402_5%

12

RC169
10K_0402_5%

@

3

12

RC153
10K_0402_5%

12

RC200
10K_0402_5%

@

12

RC154
10K_0402_5%

@

12

RC173
10K_0402_5%

@

2

12

RC155
10K_0402_5%

12

RC156
10K_0402_5%

12

RC157
10K_0402_5%

1

1 2

RC81
10K_0402_5%

@

HVB_EN7,35

C C

12

RC159
2K_0402_5%

@

12

RC160
2K_0402_5%

@

12

RC161
2K_0402_1%

12

@

RC162
2K_0402_5%

12

RC163
2K_0402_5%

@

12

RC164
2K_0402_5%

@

12

RC79

0_0402_5%

@

STRAP PINS

LFRAME_L LPCCLK1 LPCCLK0 AGPIO3SYS_RESET_LRTCCLK

Signal

Int pull-upInt pull-upInt pull-up

Type II II I

SPI ROMIIInt ern al

B B

PULL
HIGH

PULL
LOW

LPC ROM

CLK Gen

DefaultDefault

Reserved

Boot Fail Timer
Enabled

Boot Fail Timer
Disabled

Default

I

RTC Coin Battery is
implemented

Default

RTC Coin Battery is
not implemented

Normal Power Up
&Reset Timing

Default

Reserved

I

Enhanced reset
logic (for quicker
S5 resume)

Default

traditional
reset logic

Type I straps become valid immediately after capture with the rising edge of RSMRST_L,they are captured only once when power is first applied to the processor

Type II straps become valid after PWR_GOOD is asserted,straps are captured every time the systems powers up from the S5 state. A transition from S3 to S0 does not trigger capture.
Type II straps should be pulled up to S0 power rail to prevent leakage when the signal is connected to a device in S0 power domain.

If the LPC bus is connected to devices that are on S0 power rail, then a pull-up resistor to VDD_33 is implemented.

All Strap pins must be configured with either external pull-up or pull-down resistors.

Platforms that are designed for AOAC complaint are recommended to use the Alternate Reset by strapping this pin to ‘1’ for CZ
AGPIO3

A A

HVB_EN

floating

Disable HVB
on FT4 platforms

Default

connected to VSS

Enable HVB
on FT4 platforms

5

Titl e

Titl e

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER N EITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER N EITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER N EITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2017/03/14

2017/03/14

2017/03/14

3

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2017/03/14

2017/03/14

2017/03/14

2

Titl e

FT4 (STRAPS)

FT4 (STRAPS)

FT4 (STRAPS)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Thursday, October 25, 2018

Thursday, October 25, 2018

Thursday, October 25, 2018

Date: Sheet of

Date: Sheet of

Date: Sheet of

S145AST

S145AST

S145AST

1

11 50

11 50

11 50

0.2

0.2

0.2

5

Vinafix.com

DDR4 SO-DIMM A

JDDR1A

D D

C C

+1.2V

DDRB_CKE05

DDRB_BG15
DDRB_BG05

B B

+3VS +3VS

12

RD26

10K_0402_5%

@

RD268

A A

0_0402_5%

1 2

DDRB_DQ0

DDRB_DQ1

DDRB_DQS#0
DDRB_DQS0

DDRB_DQ3

DDRB_DQ6

DDRB_DQ9

DDRB_DQ13

DDRB_DM1

DDRB_DQ10

DDRB_DQ14

DDRB_DQS#2
DDRB_DQS2

DDRB_DQ22

DDRB_DQ23

DDRB_DQ28

DDRB_DQ29

DDRB_DM3

DDRB_DQ31 DDRB_DQ26

DDRB_DQ30 DDRB_DQ27

1 2

RD273 240_0402_1%@

1 2

RD274 240_0402_1%@

DDRB_CKE0

DDRB_BG1
DDRB_BG0

DDRB_MA12
DDRB_MA9

DDRB_MA8
DDRB_MA6 DDRB_MA4

+1.2V

12

RD258
1K_0402_1%

DDR4_ALERT

+3VS

12

RD269

10K_0402_5%

1 2

@

RD28
0_0402_5%

DDRB0_SA0 DDRB0_SA1 DDRB0_SA2

1

VS S _1

3

DQ5

5

VS S _3

7

DQ1

9

VS S _5

11

DQS0_C

DM0_n/DBIO_n/NC

13

DQS0_t

15

VS S _8

17

DQ7

19

VS S _1 0

21

DQ3

23

VS S _1 2

25

DQ13

27

VS S _1 4

29

DQ9

31

VS S _1 6

33

DM1_n/DBl1_n/NC

35

VS S _1 7

37

DQ15

39

VS S _1 9

41

DQ10

43

VS S _2 1

45

DQ21

47

VS S _2 3

49

DQ17

51

VS S _2 5

53

DQS2_c

DM2_n/DBl2_n/NC

55

DQS2_t

57

VS S _2 8

59

DQ23

61

VS S _3 0

63

DQ19

65

VS S _3 2

67

DQ29

69

VS S _3 4

71

DQ25

73

VS S _3 6

75

DM3_n/DBl3_n/NC

77

VS S _3 7

79

DQ30

81

VS S _3 9

83

DQ26

85

VS S _4 1

87

CB5/NC

89

VS S _4 3

+1.2V +1.2V

91

CB1/NC

93

VS S _4 5

95

DQS8_c

DM8_n/DBI8_n/NC

97

DQS8_t

99

VS S _4 8

101

CB2/NC

103

VS S _5 0

105

CB3/NC

107

VS S _5 2

109

CKE0

111

VD D _ 1

113

BG1

115

BG0

117

VD D _ 3

119

A12

121

A9

123

VD D _ 5

125

A8

127

A6

129

VD D _ 7

ARGOS_D4AR0-26001-1P40

ME@

+1.2V

12

RD11

1K_0402_1%

1 2

12

RD270

10K_0402_5%

@

RD29
0_0402_5%

1 2

VS S _1 1

VS S _1 3

VS S _1 5

DQS1_c

DQS1_t
VS S _1 8

VS S _2 0

VS S _2 2

VS S _2 4

VS S _2 6

VS S _2 7

VS S _2 9

VS S _3 1

VS S _3 3

VS S _3 5

DQS3_c

DQS3_t
VS S _3 8

VS S _4 0

VS S _4 2
CB4/NC
VS S _4 4
CB0/NC
VS S _4 6

VS S _4 7
CB6/NC
VS S _4 9
CB7/NC
VS S _5 1

RESET_n

VD D _ 2

ALERT_n

VD D _ 4

VD D _ 6

VD D _ 8

RD10
1K_0402_1%

ϭϱŵŝů

1

2

CD262

VS S _2

VS S _4

VS S _6

VS S _7

VS S _9

DQ12

DQ14

DQ11

DQ20

DQ16

DQ22

DQ18

DQ28

DQ24

DQ31

DQ27

CKE1

ACT_n

0.1U_0201_6.3V6-K

2
4

DQ4

6
8

DQ0

10
12
14
16

DQ6

18
20

DQ2

22
24
26
28

DQ8

30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120

A11

122

A7

124
126

A5

128

A4

130

+VREF_CA

1

2

CD116

0.1U_0201_6.3V6-K

SPD Address = A0H

5

CD117

1

2

4

DDRB_DQ5

DDRB_DQ4

DDRB_DM0

DDRB_DQ7

DDRB_DQ2

DDRB_DQ12

DDRB_DQ8

DDRB_DQS#1
DDRB_DQS1

DDRB_DQ11

DDRB_DQ15

DDRB_DQ21DDRB_DQ16

DDRB_DQ20DDRB_DQ17

DDRB_DM2

DDRB_DQ18

DDRB_DQ19

DDRB_DQ25

DDRB_DQ24

DDRB_DQS#3
DDRB_DQS3

MEM_MB_RST#
DDRB_CKE1

DDRB_ACT#
DDR4_ALERT

DDRB_MA11
DDRB_MA7

DDRB_MA5

1000P 25V K X7R 0201

ĨŽƌDDͺDͺZ^dηŽǀĞƌƐŚŽŽƚŝƐƐƵĞ

DDRB_CKE1 5

DDRB_ACT# 5

+3VS +VDDSPD

RD271 0_0402_5%

+2.5VS

RD272 0_0402_5%@

4

+1.2V

MEM_MB_EVENT#

+VDDSPD

1U_0402_6.3V6K

CD28

1 2

1 2

1 2

RC9 1K_0402_5%

MEM_MB_RST# 5

1

CD120

2

@

0.1U_0201_6.3V6-K

>ĂLJŽƵƚEŽƚĞWůĂĐĞŶĞĂƌ:Zϭ

+0.6VS

ĨŽůůŽǁZϭƉĐƐϰϳƵĨнϭƉĐƐϬϭƵĨ

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

1

1

CD251

CD249

CD122

@

2

+2.5V

1

2

CD250

@

2

ĨŽůůŽǁZϭƉĐƐϭƵĨнϮƉĐƐϬϭƵĨнϭƉĐƐϭϴϬƉĨ

0.1U_0201_6.3V6-K

1U_0402_6.3V6K

1

CD123

CD124

2

4.7U_0402_6.3V6M

0.1U_0201_6.3V6-K

1

1

CD248

2

2

180P_50V_J_NPO_0402

0.1U_0201_6.3V6-K

1

1

CC206

2

2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

+1.2V

DDRB_MA3
DDRB_MA1

DDRB_CLK05
DDRB_CLK0#5

RD259 0_0402_5%

DDRB_BA15

DDRB_CS0#5

DDRB_MA14_WE#5

DDRB_ODT05

DDRB_CS1#5

DDRB_ODT15

APU_SMB_CLK7,31 APU_SMB_DATA 7,31

1

1

CD29

0.1U_0201_6.3V6-K

2

2

+1.2V

1

CD16

2

+1.2V

1

CD261

2

3

DDRB_CLK0 DDRB_CLK1
DDRB_CLK0#

1 2

DDRB_BA1

DDRB_CS0#
DDRB_MA14_WE#

DDRB_ODT0
DDRB_CS1#

DDRB_ODT1

DDRB_DQ37

DDRB_DQ33 DDRB_DQ36

DDRB_DQS#4
DDRB_DQS4

DDRB_DQ38

DDRB_DQ35

DDRB_DQ44

DDRB_DQ41

DDRB_DM5

DDRB_DQ47

DDRB_DQ43

DDRB_DQ53

DDRB_DQ54

DDRB_DQS#6
DDRB_DQS6

DDRB_DQ52

DDRB_DQ50

DDRB_DQ61

DDRB_DQ56

DDRB_DM7

DDRB_DQ58

DDRB_DQ59 DDRB_DQ62

APU_SMB_CLK APU_SMB_DATA

+2.5V

1

CD121

22P_0402_50V8-J

RF_NS@

RF

2

ĨŽůůŽǁZϴƉĐƐϬϭƵĨ

0.1U_0201_6.3V6-K

CD17

CD63

10U_0603_6.3V6M

2017/03/14

2017/03/14

2017/03/14

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

1

1

CD18

CD20

2

2

1

1

CD66

2

2

10U_0603_6.3V6M

CD@

SITCD@

22UC_6.3VC_MC_X5RC_0603

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

CD67

JDDR1B

131

A3

133

A1

135

VD D _ 9

137

CK0_t

139

CK0_c

141

VD D _ 1 1

143

Pa r it y

145

BA1

147

VD D _ 1 3

149

CS0_n

151

WE_n/A14

153

VD D _ 1 5

155

ODT0

157

CS1_n

159

VD D _ 1 7

161

ODT1

163

VD D _ 1 9

165

C1/CS3_n/NC

167

VS S _5 3

169

DQ37

171

VS S _5 5

173

DQ33

175

VS S _5 7

177

DQS4_c

179

DQS4_t

181

VS S _6 0

183

DQ38

185

VS S _6 2

187

DQ34

189

VS S _6 4

191

DQ44

193

VS S _6 6

195

DQ40

197

VS S _6 8

199

DM5_n/DBl5_n/NC

201

VS S _6 9

203

DQ46

205

VS S _7 1

207

DQ42

209

VS S _7 3

211

DQ52

213

VS S _7 5

215

DQ49

217

VS S _7 7

219

DQS6_c

221

DQS6_t

223

VS S _8 0

225

DQ55

227

VS S _8 2

229

DQ51

231

VS S _8 4

233

DQ61

235

VS S _8 6

237

DQ56

239

VS S _8 8

241

DM7_n/DBl7_n/NC

243

VS S _8 9

245

DQ62

247

VS S _9 1

249

DQ58

251

VS S _9 3

253

SCL

255

VD D S PD

257

VPP_1

259

VPP_2

261

GND_1

ARGOS_D4AR0-26001-1P40

ME@

0.1U_0201_6.3V6-K

1

CD21

2

1

2

22UC_6.3VC_MC_X5RC_0603

2

DM4_n/DBl4_n/NC

DM6_n/DBl6_n/NC

0.1U_0201_6.3V6-K

1

2

1

CD19
22P_0402_50V8-J

RF_NS@

2

2

EVENT_n

VDD_10

VDD_12

VDD_14

RAS_n/A16

VDD_16

CAS_n/A15

VDD_18

C0/CS2_n/NC

VR E F C A

DQS5_c

DQS7_c

CD22

2017/03/14

2017/03/14

2017/03/14

CK1_t

CK1_c

A10/AP

VS S _5 4

DQ36

VS S _5 6

DQ32

VS S _5 8

VS S _5 9

DQ39

VS S _6 1

DQ35

VS S _6 3

DQ45

VS S _6 5

DQ41

VS S _6 7

DQS5_t
VS S _7 0

DQ47

VS S _7 2

DQ43

VS S _7 4

DQ53

VS S _7 6

DQ48

VS S _7 8

VS S _7 9

DQ54

VS S _8 1

DQ50

VS S _8 3

DQ60

VS S _8 5

DQ57

VS S _8 7

DQS7_t
VS S _9 0

DQ63

VS S _9 2

DQ59

VS S _9 4

GND_2

0.1U_0201_6.3V6-K

1

2

A2

A0

BA0

A13

SA2

SDA

SA0
VTT
SA1

CD23

1

2

DDRB_DQ[0..63]

DDRB_DQS[0..7]

DDRB_DQS#[0..7]

DDRB_MA[0..13]

DDRB_DM[0..7]

+1.2V

DDRB_MA2

132

MEM_MB_EVENT#

134
136
138

DDRB_CLK1#

140
142

DDRB_MA0

144

DDRB_MA10

146
148

DDRB_BA0

150

DDRB_MA16_RAS#

152
154

DDRB_MA15_CAS#

156

DDRB_MA13

158
160
162
164

DDRB0_SA2

166
168

DDRB_DQ32

170
172
174
176

DDRB_DM4

178
180

DDRB_DQ39

182
184

DDRB_DQ34

186
188

DDRB_DQ45

190
192

DDRB_DQ40

194
196

DDRB_DQS#5

198

DDRB_DQS5

200
202

DDRB_DQ42

204
206

DDRB_DQ46

208
210

DDRB_DQ49

212
214

DDRB_DQ48

216
218

DDRB_DM6

220
222

DDRB_DQ55

224
226

DDRB_DQ51

228
230

DDRB_DQ57

232
234

DDRB_DQ60

236
238

DDRB_DQS#7

240

DDRB_DQS7

242
244

DDRB_DQ63

246
248
250
252
254

DDRB0_SA0

256
258

DDRB0_SA1

260

262

QD1

LP2301ALT1G_SOT23-3

SUSP24,37

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

1

1

CD58

CD59

@

2

2

1

CD260
22P_0402_50V8-J

RF_NS@

CD12
22P_0402_50V8-J

RF_NS@

2

Title

Title

Title

DDRIII SO-DIMM A

DDRIII SO-DIMM A

DDRIII SO-DIMM A

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

MEM_MB_EVENT# 5

DDRB_CLK1 5
DDRB_CLK1# 5

DDRB_BA0 5

DDRB_MA16_RAS# 5

DDRB_MA15_CAS# 5

+VREF_CA

+0.6VS

D

S

13

G

2

@

0.1U_6.3V_K_X5R_0201

0.1U_0201_6.3V6-K

1

1

CD60

@

2

2

RF

Thursday, October 25, 2018

Thursday, October 25, 2018

Thursday, October 25, 2018

1

DDRB_DQ[0..63] 5

DDRB_DQS[0..7] 5

DDRB_DQS#[0..7] 5

DDRB_MA[0..13] 5

DDRB_DM[0..7] 5

+2.5VS+2.5V

0.1U_0201_6.3V6-K

1

CD61

CD62

@

@

2

S145AST

S145AST

S145AST

1

0.1U_0201_6.3V6-K

1

CC211

2

12 50

12 50

12 50

180P_50V_J_NPO_0402

1

2

0.2

0.2

0.2

5

Vinafix.com

D D

C C

4

3

2

1

B B

A A

5

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2

2017/03/14

2017/03/14

2017/03/14

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2017/03/14

2017/03/14

2017/03/14

Title

DDRIII SO-DIMM B

DDRIII SO-DIMM B

DDRIII SO-DIMM B

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

D

D

D

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

Thursday, October 25, 2018

Thursday, October 25, 2018

Thursday, October 25, 2018

S145AST

S145AST

S145AST

13 50

13 50

13 50

0.2

0.2

0.2

5

Vinafix.com

4

3

2

1

Power-Up/Down Sequence

"Topaz" has the following requirements with regards to power-supply sequencing to

D D

C C

avoid damaging the ASIC:

All the ASIC supplies must reach their respective nominal voltages within 20 ms
of the start of the ramp-up sequence, though a shorter ramp-up duration is
preferred. The maximum slew rate on all rails is 50 mV/ȝs.
It is recommended that the 3.3-V rail ramp up first.
The 3.3-V, 1.8-V, and 0.95-V rails must reach their ready state at least 10 ȝs
before VDDC, VDDCI, and VMEMIO start to ramp up.
The power rails that are shared with other components on the system should be
gated for the dGPU so that when the dGPU is powered down (for example
AMD PowerXpress idle state), all the power rails are removed from the dGPU.
The gate circuits must meet the slew rate requirement (such as  50 mV/ȝs).
For power down, reversing the ramp-up sequence is recommended.

ϬΕϮϬŵƐ

VDDR3(+3VGS)

ϬΕϮϬŵƐ

VRAM ID config

Memory Type

Hynix

H5GC8H24AJR-R0C 6.0Gbps@1.35V

256Mx32

Micron

MT51J256M32HF-70:B 6.0Gbps@1.35V

Samsung

K4G80325FB-HC28 6.0Gbps@1.35V

VRAM ID PU resistor PD resistor

PS_3[3:1]

100

111

110

RV63 RV70

4.53K

4.75K

3.4K

4.99K

NC

10K

VDD_CT(+1.8VGS)

PCIE_VDDC(+0.95VGS)

VDDR1(+1.35VGS)

ϭϬƵƐŵŝŶ

VDDC/VDDCI(+VGA_CORE)

PERSTb(GPU_RST#)

ϭϬϬŵƐŵŝŶ

ϭϬϬƵƐŵŝŶ

REFCLK(CLK_PCIE_VGA)

B B

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2017/03/14

2017/03/14

2017/03/14

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered D ate

Deciphered D ate

Deciphered D ate

2

2017/03/14

2017/03/14

2017/03/14

Title

VGA Notes List

VGA Notes List

VGA Notes List

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Thursday, October 25, 2018

Thursday, October 25, 2018

Thursday, October 25, 2018

Date: Sheet of

Date: Sheet of

Date: Sheet of

S145AST

S145AST

S145AST

1

14 50

14 50

14 50

0.2

0.2

0.2

5

Vinafix.com

PCIE_CTX_C_GRX_P[0..3]4

PCIE_CTX_C_GRX_N[0..3]4

PCIE_CTX_C_GRX_P[0..3]

PCIE_CTX_C_GRX_N[0..3]

4

UV1A

3

PCIE_CRX_GTX_P[0..3]

PCIE_CRX_GTX_N[0..3]

2

PCIE_CRX_GTX_P[0..3] 4

PCIE_CRX_GTX_N[0..3] 4

1

PCIE_CTX_C_GRX_P0 PCIE_CRX_C_GTX_P0 PCIE_CRX_GTX_P0
PCIE_CTX_C_GRX_N0

D D

C C

PXS_RST#GPU_RST#

@

1

2

B B

0.1U_0201_6.3V6-K

CV669

PX@

1

2

0.1U_0201_6.3V6-K

CV632

PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_N1

PCIE_CTX_C_GRX_P2
PCIE_CTX_C_GRX_N2

PCIE_CTX_C_GRX_P3
PCIE_CTX_C_GRX_N3

AF 3 0
AE 3 1

AE 2 9
AD 2 8

AD 3 0
AC 3 1

A
AB 2 8

AB 3 0
AA31

AA29

W31

W29

C29

Y2 8

Y3 0

V28

V30
U31

U29

T2 8

T3 0
R31

R29
P28

P30
N31

N29
M2 8

M3 0

L31

L29

K30

PCIE_RX0P
PCIE_RX0N

PCIE_RX1P
PCIE_RX1N

PCIE_RX2P
PCIE_RX2N

PCIE_RX3P
PCIE_RX3N

PCIE_RX4P
PCIE_RX4N

PCIE_RX5P
PCIE_RX5N

PCIE_RX6P
PCIE_RX6N

PCIE_RX7P
PCIE_RX7N

NC#V30
NC#U31

NC#U29
NC#T28

NC#T30
NC#R31

NC#R29
NC#P28

NC#P30
NC#N31

NC#N29
NC#M28

NC#M30
NC#L31

NC#L29
NC#K30

AH 3 0

PCIE_TX0P

PCIE_TX0N

PCIE_TX1P

PCIE_TX1N

PCIE_TX2P

PCIE_TX2N

PCIE_TX3P

PCIE_TX3N

PCIE_TX4P

PCIE_TX4N

PCIE_TX5P

PCIE_TX5N

PCIE_TX6P

PCIE_TX6N

PCIE_TX7P

PCIE_TX7N

NC#W24
NC#W23

NC#V27

PCI EXPRESS INTERFACE

NC#U26

NC#U24
NC#U23

NC#T26
NC#T27

NC#T24
NC#T23

NC#P27
NC#P26

NC#P24
NC#P23

NC#M27

NC#N26

PCIE_CRX_C_GTX_N0

AG 3 1

PCIE_CRX_C_GTX_P1

AG 2 9

PCIE_CRX_C_GTX_N1

AF 2 8

PCIE_CRX_C_GTX_P2

AF 2 7

PCIE_CRX_C_GTX_N2 PCIE_CRX_GTX_N2

AF 2 6

PCIE_CRX_C_GTX_P3

AD 2 7

PCIE_CRX_C_GTX_N3 PCIE_CRX_GTX_N3

AD 2 6

AC 2 5
AB 2 5

Y2 3
Y2 4

AB 2 7
AB 2 6

Y2 7
Y2 6

W24
W23

V27
U26

U24
U23

T2 6
T2 7

T2 4
T2 3

P27
P26

P24
P23

M2 7
N26

change the GPU PN to AMD(EXO-S3 PRO), symbol check ok

11/4 change to PC sample SA000074V10

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

CV10.22U_0201_6.3V6-K P X@

PCIE_CRX_GTX_N0

CV20.22U_0201_6.3V6-K P X@

PCIE_CRX_GTX_P1

CV30.22U_0201_6.3V6-K P X@

PCIE_CRX_GTX_N1

CV40.22U_0201_6.3V6-K P X@

PCIE_CRX_GTX_P2

CV50.22U_0201_6.3V6-K P X@
CV60.22U_0201_6.3V6-K P X@

PCIE_CRX_GTX_P3

CV70.22U_0201_6.3V6-K P X@
CV80.22U_0201_6.3V6-K P X@

with BOM strcture control, CV1--CV8 change to 0.22uf for CZ

+3VALW

+3VGS

1 2

RV1430 0_0402_5%PX@

1 2

RV1429 0_0402_5%@

UV2 power change to +3VALW to solve GPU_RST# glitch

RV7 0_0402_5%@

A A

PXS_RST#7,8

PLT_RST#7,26,29,31,35

1

2

5

+3V_GATE

1 2

+3V_GATE

5

UV2

VCC

IN 1

OUT

IN 2

GND

MC74VHC1G08DFT2G_SC70-5

3

PX@

CL O C K

AK 3 0

PCIE_REFCLKP

AK 3 2

PCIE_REFCLKN

CALIBRATION

N10

TEST_PG

AL27

PERSTB

@

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

PCIE_CALR_TX

PCIE_CALR_RX

Y2 2

AA 2 2

2017/03/14

2017/03/14

2017/03/14

3

1 2

RV3 1.69K_0402_1%PX@

1 2

RV5 1K_0402_1%PX@

VR_VGA_PWRGD7,48

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

+0.95VGS

2017/03/14

2017/03/14

2017/03/14

GPU_RST#

VR_VGA_PWRGD

2

DV3

2

3

LBAT54AWT1G SOT323

PX@

Title

Title

Title

ATI_EXO-PRO_PCIE

ATI_EXO-PRO_PCIE

ATI_EXO-PRO_PCIE

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet o f

Date: Sheet of

Date: Sheet of

VGA_PWROK

1

Friday, October 26, 2018

Friday, October 26, 2018

Friday, October 26, 2018

S145AST

S145AST

S145AST

VGA_PWROK 48

15 50

15 50

15 50

1

0.2

0.2

0.2

1 2

GPU_RST#

CLK_PCIE_GPU
CLK_PCIE_GPU#

RV41K_0402_1% PX@

12

RV6
100K_0402_5%

PX@

4

CLK_PCIE_GPU8
CLK_PCIE_GPU#8

GPU_RST#16

GPU_RST#

4

5

Vinafix.com

D D

+3VGS

1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2

1 2

RV810K_0402_5% @

RV910K_0402_5% @
RV1210K_0402_5% @
RV1310K_0402_5% @
RV1410K_0402_5% @
RV2510K_0402_5% @
RV9610K_0402_5% @
RV3410K_0402_5% @
RV8110K_0402_5% @
RV9710K_0402_5% @
RV9810K_0402_5% @
RV9910K_0402_5% @
RV10610K_0402_5% @

RV101110K_0402_5% @

RV10395.11K_0402_1% @

GPU_GPIO5

GPU_GPIO0
GPU_GPIO8
GPU_GPIO9
GPU_GPIO10
GPU_GPIO11
GPU_GPIO12
GPU_GPIO13
GPU_GPIO22
GPU_VID1
GPU_GPIO21
GPU_VID5
GPU_VID2

GPU_GPIO17

TESTEN

+1.8VGS

RV93

1 2

10K_0402_5%

1 2

RV95

10K_0402_5%

Reserve

+VGA_CORE

RB751V-40_SOD323-2

GPU_VR_HOT#

GPU_SVD

GPU_SVC

GPU_VR_HOT#

+1.8VGS

DV1

RV104 0_0402_5%PX@

10K_0402_5%

RV64

+VGA_CORE

LV3

(1.8V@20mA TSVDD)

VGA_AC_DET35

+VGA_CORE

C C

+3VGS

1 2
1 2
1 2

1 2

1 2

2016/09/02: Pull-down GPU_CLKREQ# at GPU side

1 2

CV25

PX@

10P_0201_50V8-D

YV1

PX@

B B

CV32

PX@

1 2

10P_0201_50V8-D

$%!!&'(&')'(

+3VGS

RV7210K_0402_5% @
RV7510K_0402_5% @
RV7810K_0402_5% @

RV4010K_0402_5% @

RV1040470_0402_5% @

1

2

OSC1

GND1

OSC23GND2

4

RV41

GPU_VR_HOT#35,48

GPU_CLKREQ#7

JTAG_TRSTB
JTAG_TDI
JTAG_TMS

JTAG_TCK

GPU_CLKREQ#

XTALIN

12

RV46
1M_0402_5%

PX@

27MHZ_10PF_7V27000050

XTALOUT

1 2

@

10K_0402_5%

RV42

10K_0402_5%

EXO@

ŽŶŶĞĐƚ'W/KͺϮϴƚŽϭϬ<ƉƵůů
ĚŽǁŶƚŽĞŶĂďůĞD>W^

1 2

TOPAZ@

TOPAZ@

1 2

1 2

TV3Test_Point_16MIL@

1 2
1 2
1 2

PX@

1 2
1 2

1 2
1 2

1 2

PX@

1K_0402_5%

1

TV6Test_Point_16MIL@

TV15@

1

1 2
1 2

1 2

BLM15PD121SN1D_2P

1U_0402_6.3V6K

TV11@

TV12@

TV7Test_Point_16MIL@

TV13@
TV14@

PX@

CV21

4

1

1

@

1

RV1030_0402_5% EXO@
RV6710K_0402_5% @
RV1070_0402_5% @

RV68
RV1050_0402_5% EXO@

RV10120_0402_5% @
RV1240_0402_5% @

PX_EN

1 2

NC_DBG_VREFG

RV4510K_0402_5% PX@
RV5010K_0402_5% PX@

1
1

1

PX@

2

BP_0
VGA_VDDCI_SEN
BP_1

PLL_ANALOG_IN

GPU_GPIO0

VGA_SMB_DATA
VGA_SMB_CLK
GPU_GPIO5
GPU_VID5

GPU_GPIO8
GPU_GPIO9
GPU_GPIO10
GPU_GPIO11
GPU_GPIO12
GPU_GPIO13

GPU_VID3
GPU_GPIO16
GPU_GPIO17

GPIO_19_CTF
GPU_VID4
GPU_GPIO21
GPU_GPIO22
GPU_VID 2
GPU_VID 1
GPU_CLKREQ#_R

JTAG_TRSTB
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO

1

TESTEN

XTALIN
XTALOUT

XO_IN
XO_IN2

GPU_DPLUS
GPU_DMINUS

GPIO_28_FDO
+TSVDD

RV544.7K_0402_5% @

UV1B

N9

DBG_DATA16

L9

DBG_DATA15

AE9

DBG_DATA14

Y11

DBG_DATA13

AE8

DBG_DATA12

AD9

DBG_DATA11

AC10

DBG_DATA10

AD7

DBG_DATA9

AC8

DBG_DATA8

AC7

DBG_DATA7

AB9

DBG_DATA6

AB8

DBG_DATA5

AB7

DBG_DATA4

AB4

DBG_DATA3

AB2

DBG_DATA2

Y8

DBG_DATA1

Y7

DBG_DATA0

W6

NC # W 6

V6

NC # V 6

AC6

NC # A C 6

AC5

NC # A C 5

AA5

NC # A A 5

AA6

NC # A A 6

U1

NC#U1

W1

NC # W 1

U3

NC#U3

Y6

NC # Y 6

AA1

NC # A A 1

R1

SCL

R3

SDA

U6

GPIO_0

U1 0

NC _ G P I O _ 1

T10

NC _ G P I O _ 2

U8

SMBDATA

U7

SMBCLK

T9

GPIO_5_AC_BATT

T8

GPIO_6

T7

NC _ G P I O _ 7

P10

GPIO_8_ROMSO

P4

GPIO_9_ROMSI

P2

GPIO_10_ROMSCK

N6

NC _ G P I O _ 1 1

N5

NC _ G P I O _ 1 2

N3

NC _ G P I O _ 1 3

Y9

NC _ G P I O _ 1 4

N1

GPIO_15_PWRCNTL_0

M4

GPIO_16

R6

GPIO_17_THERMAL_INT

W10

NC _ G P I O _ 1 8

M2

GPIO_19_CTF

P8

GPIO_20_PWRCNTL_1

P7

GPIO_21

N8

GPIO_22_ROMCSB

AK10

GPIO_29

AM10

GPIO_30

N7

CLKREQB

L6

JTAG_TRSTB

L5

JTAG_TDI

L3

JTAG_TCK

L1

JTAG_TMS

K4

JTAG_TDO

K7

TESTEN

AF24

NC#AF24

AB13

NC_GENERICA

W8

NC_GENERICB

W9

NC_GENERICC

W7

NC_GENERICD

AD10

NC_GENERICE_HPD4

AJ9

NC # A J 9

AL9

DBG_CNTL0

AC14

NC_HPD1

AB16

PX_EN

AC16

NC_DBG_VREFG

AM28

XTALIN

AK28

XTALOUT

AC22

XO_IN

AB22

XO_IN2

SEYMOUR/FutureASIC

T4

DPLUS

T2

DMINUS

R5

GPIO28_FDO

AD17

TSVDD

AC17

TSVSS

@

I2C

PLL/CLOCK

DVO

GENERAL PURPOSE I/O

THERMAL

DPA

DPB

DPC

NC_AVSSN#AK26

NC_AVSSN#AJ25

NC_AVSSN#AG25

DAC1

NC_VDD1DI

FutureASIC/SEYMOUR/PARK

NC_SVI2#AK12

NC_SVI2#AL11
NC_SVI2#AJ11

NC_GENLK_CLK

NC_GENLK_VSYNC

NC_SWAPLOCKA
NC_SWAPLOCKB

DDC/AUX

NC_DDC1CLK

NC_DDC1DATA

NC_DDC2CLK

NC_DDC2DATA

NC_DDCVGACLK

NC_DDCVGADATA

NC # A F 2
NC # A F 4

NC # A G 3
NC # A G 5

NC # A H 3
NC # A H 1

NC # A K 3
NC # A K 1

NC # A K 5
NC # A M 3

NC # A K 6
NC # A M 5

NC # A J 7

NC # A H 6

NC # A K 8
NC#AL7

NC # V 4
NC # U5

NC # W 3

NC # V 2

NC # Y 4

NC # W 5

NC # A A 3

NC # Y 2

NC # J 8

NC _ HS Y N C
NC _ V S Y N C

NC_RSET

NC_AVDD

NC_AVSSQ

NC_VSS1DI

CEC_1

NC_AUX1P
NC_AUX1N

NC_AUX2P
NC_AUX2N

NC#AD20
NC#AC20

NC # A E 1 6

NC#AD16

NC _ R

NC _ G

NC _ B

PS_0

PS_1

PS_2

PS_3

TS_A

3

AF2
AF4

AG3
AG5

AH3
AH1

AK3
AK1

AK5
AM3

AK6
AM5

AJ7
AH6

AK8
AL7

V4
U5

VGA_VSSI_SEN

W3
V2

Y4
W5

PLL_ANALOG_OUT

AA3
Y2

J8

AM26

DIECRACKMON

AK26

AL25
AJ25

AH24
AG25

AH26

1 2

AJ27

RV22 4.7K_0402_5%

AD22

WƵůůĚŽǁŶĨŽƌŶŽŶĞK&&ĚĞƐŝŐŶ

AG24
AE22

AE23
AD23

CEC_1

AM12

GPU_SVD_R

AK12

GPU_SVT_R

AL11

GPU_SVC_R

AJ11

GENLK_CLK

AL13

GENLK_VSYNC

AJ13

AG13
AH12

PS_0

AC19

PS_1

AD19

PS_2

AE17

PS_3

AE20

AE19

AE6
AE5

AD2
AD4

AC11
AC13

AD13
AD11

VGA_VSS_SEN_R

AD20

VGA_CORE_SEN_R

AC20

AE16
AD16

AC1
AC3

1

TV10Test_Point_16MIL @

RV94

@

1 2

16.2K_0402_1%

 !"#

1 2

RV120

TOPAZ@

10K_0402_5%

TOPAZ@

1

TV5 Test_Point_16MIL @

1 2

RV110 0_0402_5%TOPAZ@
RV109 0_0402_5%TOPAZ@

1 2
1 2

RV111 0_0402_5%TOPAZ@

1

TV1 Test_Point_16MIL @

1

TV2 Test_Point_16MIL @

+VGA_CORE

12

RV24
100_0402_5%

TOPAZ@

1 2

RV125 0_0402_5%TOPAZ@

1 2

RV126 0_0402_5%TOPAZ@

12

RV23
100_0402_5%

TOPAZ@

+VGA_CORE

For Topaz, RV23/RV24 stuff 100ohm
For EXO, RV23/RV24 stuff 0hm

RV242 0_0402_5%@

12

2

CONFIGURATION STRAPS

ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE
GPIOS ARE USED, THEY M UST NOT CONFLICT DURING RES ET

Strap N ame DescriptionMLPS Bit

ROM_CONFIG[0]

Define the R OM type when S TRAP_B IOS_R OM_EN = 1,

ROM_CONFIG[1]

Define the p rimary mem ory-aperture s ize when STR AP_BI OS_RO M_EN = 0.

ROM_CONFIG[2]

Reserved fo r internal use only. Must be 1 at rese t.

The LSB (le ast signific ant bit) of the s trap option that

AUD_PORT_CONN_

indicates the num ber of aud io-capable d isplay outputs .

PINSTRAP[0]

1 = PCIe G EN3 is sup ported.
0 = PCIe G EN3 is not s upported .

0 = The CLKREQB power management capability is disabled
1 = The CLK REQB p ower manage ment capabili ty is enabled

N/A

Reserved for internal use only. Must be 0 at re set.

0 = The transmitte r half-swing is e nabled
1 = The transmitte r full-swing is e nabled

0 = Tx deemphasis disabled.
1 = Tx deemphasis enabled.

Reserved.

N/A

Reserved.

N/A

0 = Disable the external BI OS ROM device .
1 = Enable the external BIOS ROM device.

0 = VGA controller c apacity enabled.
1 = The device will not b e recognized as the system’s VG A

STRAP_BIF_VGA_DIS

controller.

N/A

Reserved 1

Board configuration relate d strapping, such as f or memory ID

BOARD_CONFIG[0]

100 = Hynix 1G

BOARD_CONFIG[1]

111 = Micron 1G

BOARD_CONFIG[2]

110 = Sam sung 1G

Determines the maximum numbe r of digital dis play audio endpoints
that will be presented to the OS and user.(Comb ine with PS_0[5])
111 = No usable end points.
110 = One usable endpoint.

AUD_PORT_CONN_

101 = Two usable endpoints.

PINSTRAP[1]

100 = Three usable endpoints.
011 = Four usable endpoints.

AUD_PORT_CONN_

010 = Five usable endpoints.

PINSTRAP[2]

001 = Six usable endpoints.
000 = All endpo ints are usable.

12

RV71

8.45K_0402_1%

PX@

PS_0

12

RV77

2K_0402_1%

PX@

12

RV60

10K_0402_5%

@

PS_2

12

RV69

4.75K_0402_1%

PX@

GPU_SVD 48
GPU_SVT 48
GPU_SVC 48

PS_0[1]
PS_0[2]
PS_0[3]

PS_0[4] N /A

PS_0[5]

PS_1[1]

STRAP_BIF_GEN3_EN_A

PS_1[2]

STRAP_BIF_CLK_PM_EN

PS_1[3]

STRAP_TX_CFG_DRV_
FULL_S WING

PS_1[4]

PS_1[5]

STRAP_TX_DEEMPH_EN

PS_2[1]

PS_2[2]

PS_2[3]

STRAP_BIOS_ROM_EN

PS_2[4]

PS_2[5]

PS_3[1]
PS_3[2]
PS_3[3]

PS_3[4]

PS_3[5]

MLPS

PS_0[5:1]

PS_1[5:1]

PS_2[5:1]

PS_3[5:1]

with BOM strcture control,
RV63,RV70 change to different value to
adjust VRAM config

with BOM strcture control,
when config PEG3
RV74 change to 8.45K,
RV80 change to 2K

VGA_VSS_SEN 48
VGA_CORE_SEN 48

SVDSVC

Output Voltage (V)

0 0

0

1

1

0

1

1

WRST# 35

1.1

1.0

0.9

0.8

Bit

11

11

11

11

680

82

10

NC

000 = Hynix 2G
010 = Micron 2G
001 = Sam sung 2G

1

CV15
.01U_0402_16V7-K

@

2

1

CV18
.01U_0402_16V7-K

@

2

0 0

+1.8VGS

GPU_SVD
GPU_SVC
GPU_SVT

12345

10 0

010 0

XXX

Bits [5:4]Capacitor Value (nF)

+3VGS

1

RECOMMENDED SETTINGS
0= DO NOT INSTAL L RESIST OR
1 = INSTALL 1 0K RESIST OR
X = DESIGN DEPE NDANT
NA = NOT APPLICA BLE

RECOMMENDE D
SETTINGS

001 = 256MB

1= GEN3 is s upported

1= Enable

0= Disable

111= No usable endpoints.

+1.8VGS+1.8VGS

12

RV74

8.45K_0402_1%

PX@

PS_1

12

1

RV80

PX@

RV63

RV70

ǂ

R_pu (ȍ)

NC

8450

4530

6980

4530

3240

3400

4750

1 2

0_0402_5%

1 2

0_0402_5%

+1.8VGS+1.8VGS

@

@

1 2

1 2

12

12

BOM

R_pd (ȍ)

EXO@

TOPAZ@

RV204
10K_0402_5%

PX@

RV207
10K_0402_5%

@

CV16
.01U_0402_16V7-K

@

2

1

CV19
.01U_0402_16V7-K

@

2

ǂ

4750

2000

2000

4990

4990

5620

10000

NC

+VDDIO_GPU

RV209
10K_0402_5%

@

1 2

RV210
10K_0402_5%

@

1 2

C(nF)R_pd( )

Bits [3:1]

2K_0402_1%

8.45K_0402_1%

PS_3

2K_0402_1%

R_pu( )

RV71=8.45k RV77=2K CV15=NC

RV74=8.45K RV80=2K CV16=NC

RV60=NC RV69=4.75K CV18=NC

RV63=X76 RV70=X76 CV19=NC

00

01

10

11

Note: 0402 1% resistors are requi red.

RV234

RV203

RV205
10K_0402_5%

@

1 2

RV206
10K_0402_5%

PX@

1 2

X

1

1

X

0

0

1

X

0

0

X

1

X

11

000

001

010

011

100

101

110

111

A A

5

C

GPU_RST#

GPU_RST#15

GPIO_19_CTF

21

@

SDM10U45LP-7_DFN1006-2-2

1 2

@

47K_0402_5%

4

DV2

RV132

RV128

12

RV131
100K_0402_5%

@

1 2

@

2.2K_0402_5%

QV13

2

MMBT3904WH_SOT323-3

B

@

E

@

3 1

1

2

0.1U_0201_6.3V6-K

CV215

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2017/03/14

2017/03/14

2017/03/14

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2



+3VGS

12

12

RV43

PX@

2017/03/14

2017/03/14

2017/03/14

RV44
47K_0402_5%

PX@

47K_0402_5%

VGA_SMB_CLK

VGA_SMB_DATA

+3VGS

2

G

S

61

QV4A

PX@

D

2N7002KDWH_SOT363-6

S

QV4B

2N7002KDWH_SOT363-6

Title

Title

Title

ATI_EXO-PRO_Main_MSIC

ATI_EXO-PRO_Main_MSIC

ATI_EXO-PRO_Main_MSIC

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Thursday, October 25, 2018

Thursday, October 25, 2018

Thursday, October 25, 2018

Date: Sheet of

Date: Sheet of

Date: Sheet of

5

G

34

PX@

D

S145AST

S145AST

S145AST

1

EC_SMB_CK3 6,30,35

EC_SMB_DA3 6,30,35

16 50

16 50

16 50

0.2

0.2

0.2

5

Vinafix.com

4

3

2

1

UV1F

D D

C C

@

B B

NC_VARY_BL

NC_UPHYAB_TMDPA_TX0N

NC_UPHYAB_TMDPA_TX0P

NC_UPHYAB_TMDPA_TX1N

NC_UPHYAB_TMDPA_TX1P

NC_UPHYAB_TMDPA_TX2N

NC_UPHYAB_TMDPA_TX2P

NC_UPHYAB_TMDPA_TX3N

NC_UPHYAB_TMDPA_TX3P

NC_TXOUT_L3P
NC_TXOUT_L3N

TM D P

NC_UPHYAB_TMDPB_TX0N

NC_UPHYAB_TMDPB_TX0P

NC_UPHYAB_TMDPB_TX1N

NC_UPHYAB_TMDPB_TX1P

NC_UPHYAB_TMDPB_TX2N

NC_UPHYAB_TMDPB_TX2P

NC_UPHYAB_TMDPB_TX3N

NC_UPHYAB_TMDPB_TX3P

NC_TXOUT_U3P
NC_TXOUT_U3N

NC_DIGON

AB11
AB12

AL15
AK14

AH16
AJ15

AL17
AK16

AH18
AJ17

AL19
AK18

AH20
AJ19

AL21
AK20

AH22
AJ21

AL23
AK22

AK24
AJ23

+VGA_CORE

A A

5

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2017/03/14

2017/03/14

2017/03/14

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Dat e

Deciphered Dat e

Deciphered Dat e

2017/03/14

2017/03/14

2017/03/14

2

Title

ATI_EXO-PRO_TMDP

ATI_EXO-PRO_TMDP

ATI_EXO-PRO_TMDP

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Thursday, October 25, 2018

Thursday, October 25, 2018

Thursday, October 25, 2018

S145AST

S145AST

S145AST

1

17 50

17 50

17 50

0.2

0.2

0.2

5

Vinafix.com

4

3

2

1

+1.8VGS

RV48 0_0603_5%PX@

D D

+0.95VGS

RV47 0_0603_5%PX@

C C

B B

1 2

1 2

(1.8V@425mA DP_VDDR)

1

1

2

2

1U_0402_6.3V6K

CV40 PX@

CV39 PX@

10U_0603_6.3V6M

(0.95V@560mA DP_VDDC)

1

1

2

2

1U_0402_6.3V6K

CV37 PX@

0.1U_0201_6.3V6-K

CV38 PX@

1 2

RV49

+DP_VDDR

+DP_VDDC

@

150_0402_1%

UV1G

AG15

NC_DP_VDDR#AG15

AG16

NC_DP_VDDR#AG16

AF16

NC_DP_VDDR#AF16

AG17

NC_DP_VDDR#AG17

AG18

NC_DP_VDDR#AG18

AG19

NC_DP_VDDR#AG19

AF14

DP_VDDR#AF14

AG20

NC_DP_VDDC#AG20

AG21

NC_DP_VDDC#AG21

AF22

NC_DP_VDDC#AF22

AG22

NC_DP_VDDC#AG22

AD14

DP_VDDC#AD14

AG14

NC_DP_VSSR_1

AH14

NC_DP_VSSR_2

AM14

NC_DP_VSSR_3

AM16

NC_DP_VSSR_4

AM18

NC_DP_VSSR_5

AF23

NC_DP_VSSR_6

AG23

NC_DP_VSSR_7

AM20

NC_DP_VSSR_8

AM22

NC_DP_VSSR_9

AM24

NC_DP_VSSR_10

AF19

NC_DP_VSSR_11

AF20

NC_DP_VSSR_12

AE14

DP_VSSR_13

AF17

NC_UPHYAB_DP_CALR

@

DP POWER

NC/DP POWER

NC#AE11
NC#AF11
NC#AE13
NC#AF13

NC#AG8

NC#AG10

NC#AF6
NC#AF7
NC#AF8
NC#AF9

NC#AE1
NC#AE3
NC#AG1
NC#AG6
NC#AH5

NC#AF10

NC#AG9
NC#AH8
NC#AM6
NC#AM8
NC#AG7

NC#AG11

NC#AE10

AE11
AF11
AE13
AF13
AG8
AG10

AF6
AF7
AF8
AF9

AE1
AE3
AG1
AG6
AH5
AF10
AG9
AH8
AM6
AM8
AG7
AG11

AE10

AA27
AB24
AB32
AC24
AC26
AC27
AD25
AD32
AE27

AF32
AG27
AH32

M32

W25
W26
W27

AA11

M12

UV1E

GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
GND_10
GND_11
GND_12

K28

GND_13

K32

GND_14

L27

GND_15
GND_16

N25

GND_17

N27

GND_18

P25

GND_19

P32

GND_20

R27

GND_21

T25

GND_22

T32

GND_23

U25

GND_24

U27

GND_25

V32

GND_26
GND_27
GND_28
GND_29

Y25

GND_30

Y32

GND_31

M6

GND_32

N13

GND_33

N16

GND_34

N18

GND_35

N21

P6

P9
R12
R15
R17
R20
T13
T16
T18
T21

T6
U15
U17
U20

U9
V13
V16
V18
Y10
Y15
Y17
Y20
R11
T11

N11
V11

@

GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
GND_60
GND_61
GND_62
GND_63
GND_64

GN D

VSS_MECH_1
VSS_MECH_2
VSS_MECH_3

GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87
GND_88
GND_89
GND_90
GND_91
GND_92
GND_93
GND_94
GND_95
GND_96
GND_97
GND_98

GND_99
GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_113
GND_114
GND_115
GND_116
GND_117
GND_118
GND_119

A3
A30
AA13
AA16
AB10
AB15
AB6
AC9
AD6
AD8
AE7
AG12
AH10
AH28
B10
B12
B14
B16
B18
B20
B22
B24
B26
B6
B8
C1
C32
E28
F10
F12
F14
F16
F18
F2
F20
F22
F24
F26
F6
F8
G10
G27
G31
G8
H14
H17
H2
H20
H6
J27
J31
K11
K2
K22
K6

A32
AM1
AM32

A A

5

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2017/03/14

2017/03/14

2017/03/14

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Dat e

Deciphered Dat e

Deciphered Dat e

2017/03/14

2017/03/14

2017/03/14

2

Title

ATI_EXO-PRO_DP Power

ATI_EXO-PRO_DP Power

ATI_EXO-PRO_DP Power

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Thursday, October 25, 2018

Thursday, October 25, 2018

Thursday, October 25, 2018

S145AST

S145AST

S145AST

1

18 50

18 50

18 50

0.2

0.2

0.2

5

Vinafix.com

CV501

33P_0402_50V8J

RF_PXNS@

RF

D D

change LV4 to SM01000MK00 (S SUPPRE_ BLM15AG221SN1 122)
as DFC suggest, footprint with
MURAT_BLM15PD121SN1D_2P

+1.8VGS

LV4

CV24

1

2

@

0.1U_0201_6.3V6-K

&ŽƌD

C C

+1.8VGS

LV5

BLM15PD121SN1D_2P

CV28

1

2

@

0.1U_0201_6.3V6-K

&ŽƌD

1 2

BLM15AG221SN1

1 2

(1.8V@130mA MPLL_PVDD)

PX@

CV34

CV26

1

1

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

PX@

PX@

(1.8V@75mA SPLL_PVDD)

PX@

CV29

CV30

1

1

2

2

1U_0402_6.3V6K

10U_0603_6.3V6M

PX@

PX@

CV27

1

2

1U_0402_6.3V6K

PX@

+SPLL_PVDD

+MPLL_PVDD

+1.35VGS

For DDR3/GDDR5, 1500mA@1.5V

CV51

CV48

1

1

2

2

10U_0603_6.3V6M

PX@

PX@

2.2U_0402_6.3V6M

+1.8VGS

RV1364 0_0402_5%PX@

+3VGS

RV1365 0_0402_5%PX@

+0.95VGS

1 2

LV6

BLM15PD121SN1D_2P

1

CV33

0.1U_0201_6.3V6-K

@

2

&ŽƌD

CV53

CV52

1

1

1

2

2

2

PX@

PX@

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

(1.8V@13mA VDD_CT)

1 2

(3.3V@25mA VDDR3)

1 2

PX@

4

CV55

CV56

CV54

1

2

PX@

2.2U_0402_6.3V6M

(0.95V@100mA SPLL_VDDC)

CV217

1

1

1

2

2

2

PX@

PX@

PX@

2.2U_0402_6.3V6M

0.1U_0201_6.3V6-K

0.01U_6.3V_K_X7R_0201

+VDD_C T

CV144

1

2

PX@

1U_0402_6.3V6K

+VDDR3

CV149

1

2

PX@

1U_0402_6.3V6K

+MPLL_PVDD

+SPLL_PVDD

+SPLL_VDDC

CV35

CV36

1

1

2

2

1U_0402_6.3V6K

0.1U_0201_6.3V6-K

PX@

PX@

3

UV1D

MEM I/O

H13

VD D R 1 _ 1

H16

VD D R 1 _ 2

H19

VD D R 1 _ 3

J10

VD D R 1 _ 4

J23

VD D R 1 _ 5

J24

VD D R 1 _ 6

J9

VD D R 1 _ 7

K10

VD D R 1 _ 8

K23

VD D R 1 _ 9

K24

VDDR1_10

K9

VDDR1_11

L11

VDDR1_12

L12

VDDR1_13

L13

VDDR1_14

L20

VDDR1_15

L21

VDDR1_16

L22

VDDR1_17

LEVEL
TRANSLATION

AA 2 0

VDD_CT_1

AA 2 1

VDD_CT_2

AB 2 0

VDD_CT_3

AB 2 1

VDD_CT_4

I/O

AA 1 7

VD D R 3 _ 1

AA 1 8

VD D R 3 _ 2

AB 1 7

VD D R 3 _ 3

AB 1 8

TV16@
TV17@
TV18@

VD D R 3 _ 4

1

V1 2

NC_VDDR4_1

1

Y12

NC_VDDR4_2

U12

1

NC_VDDR4_3

PLL

L8

MPLL_PVDD

H7

SPLL_PVDD

H8

SPLL_VDDC

J7

SPLL_PVSS

@

PCIE

PCIE_VDDC_1
PCIE_VDDC_2
PCIE_VDDC_3
PCIE_VDDC_4
PCIE_VDDC_5
PCIE_VDDC_6
PCIE_VDDC_7
PCIE_VDDC_8

PCIE_VDDC_9
PCIE_VDDC_10
PCIE_VDDC_11
PCIE_VDDC_12

CORE

POWER

BIF_VDD C_1
BIF_VDD C_2

ISO L AT E D
CORE I/O

PCIE_P VDD

NC#A B2 3
NC#A C2 3
NC#A D2 4
NC#A E2 4
NC#A E2 5
NC#A E2 6
NC#A F2 5
NC#A G2 6

VD D C _ 1
VD D C _ 2
VD D C _ 3
VD D C _ 4
VD D C _ 5
VD D C _ 6
VD D C _ 7
VD D C _ 8

VD D C _ 9
VD D C _ 1 0
VD D C _ 1 1
VD D C _ 1 2
VD D C _ 1 3
VD D C _ 1 4
VD D C _ 1 5
VD D C _ 1 6
VD D C _ 1 7
VD D C _ 1 8
VD D C _ 1 9
VD D C _ 2 0
VD D C _ 2 1
VD D C _ 2 2
VD D C _ 2 3
VD D C _ 2 4
VD D C _ 2 5

VD D C I _ 1
VD D C I _ 2
VD D C I _ 3
VD D C I _ 4
VD D C I _ 5
VD D C I _ 6
VD D C I _ 7
VD D C I _ 8

(1.8V@100mA PCIE_PVDD)

AM 3 0

AB 2 3
AC 2 3
AD 2 4
AE 2 4
AE 2 5
AE 2 6
AF 2 5
AG 2 6

(0.95V@1000mA PCIE_VDDC)

L23
L24
L25
L26
M2 2
N22
N23
N24
R22
T22
U22
V2 2

AA 1 5
N15
N17
R13
R16
R18

CV6651U_0201_6.3V6-MPX@

Y21
T12
T15
T17
T20
U13
U16
U18
V2 1
V1 5
V1 7
V2 0
Y13
Y16
Y18
AA 1 2
M1 1
N12
U11

R21
U21

M1 3
M1 5
M1 6
M1 7
M1 8
M2 0
M2 1
N20

1U_0402_6.3V6K

1

1

CV6641U_0201_6.3V6-MPX@

2

2

1

CV6611U_0201_6.3V6-MPX@

2

+1.8VGS

CV47

CV46

1

1

2

2

1U_0402_6.3V6K

10U_0603_6.3V6M

PX@

PX@

CV64

CV66

CV67

CV65

1

1

1

1

2

2

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

PX@

PX@

PX@

PX@

CV633

CV666

CV667

CV668

1

1

1

1

2

2

2

10U 6.3V M X5R 04 02

PX@

2

10U 6.3V M X5R 04 02

10U 6.3V M X5R 04 02

10U 6.3V M X5R 04 02

PX@

PX@

PX@

CV640

1

2

10U 6.3V M X5R 04 02

PX@

(0.95V@800mA BIF_VDDC)

1U_0402_6.3V6K

2

+0.95VGS

CV68

CV71

CV69

1

1

2

2

1U_0402_6.3V6K

PX@

PX@

CV636

CV637

1

1

2

2

10U 6.3V M X5R 04 02

10U 6.3V M X5R 04 02

PX@

PX@

CV642

CV643

1

1

2

2

10U 6.3V M X5R 04 02

10U 6.3V M X5R 04 02

PX@

PX@

1

1

CV502
33P_0402_50V8J

RF_PXNS@

2

2

10U_0603_6.3V6M

PX@

CV639

CV638

1

1

2

2

10U 6.3V M X5R 04 02

10U 6.3V M X5R 04 02

10U 6.3V M X5R 04 02

PX@

PX@

PX@

CV644

CV645

1

1

2

2

10U 6.3V M X5R 04 02

10U 6.3V M X5R 04 02

10U 6.3V M X5R 04 02

PX@

PX@

PX@

RF

CV76

CV75

CV77

CV74

CV73

1

1

2

2

10U 6.3V M X5R 04 02

10U 6.3V M X5R 04 02

PX@

PX@

CV647

CV646

1

1

2

2

10U 6.3V M X5R 04 02

10U 6.3V M X5R 04 02

PX@

PX@

+0.95VGS

1

2

10U 6.3V M X5R 04 02

PX@

CV649

CV648

1

2

10U 6.3V M X5R 04 02

PX@

1

CV41
1U_0402_6.3V6K

PX@

2

CV141

CV143

CV146

1

1

2

2

10U 6.3V M X5R 04 02

10U 6.3V M X5R 04 02

PX@

PX@

CV650

1

1

2

2

10U 6.3V M X5R 04 02

10U 6.3V M X5R 04 02

PX@

PX@

CV148

1

1

1

1

2

2

2

2

10U 6.3V M X5R 04 02

10U 6.3V M X5R 04 02

10U 6.3V M X5R 04 02

PX@

PX@

PX@

CV651

1

2

(GDDR3/DDR3 8.8A@1.12V VDDCI)

CV218

CV219

CV158

CV132

CV136

1

1

1

2

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

PX@

PX@

1

1

2

2

2

2

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

PX@

PX@

PX@

22UC_6.3VC_MC_X5RC_0603

CV150

1

2

10U 6.3V M X5R 04 02

PX@

+VGA_CORE

CV138

1

2

PX@

22UC_6.3VC_MC_X5RC_0603

1

+VGA_CORE

CV84

CV159

CV137

CV133

1

1

2

2

10U 6.3V M X5R 04 02

PX@

CV156

CV160

1

1

2

2

PX@

PX@

22UC_6.3VC_MC_ X5RC_0603

CV504

2.2U_0402_6.3V6M

CV151

1

1

2

2

10U 6.3V M X5R 04 02

10U 6.3V M X5R 04 02

PX@

PX@

CV134

CV135

1

1

1

CV503

2

2

2

2.2U_0402_6.3V6M

PX@

PX@

PX@

22UC_6.3VC_MC_ X5RC_0603

22UC_6.3VC_MC_ X5RC_0603

CV152

1

1

2

2

10U 6.3V M X5R 04 02

10U 6.3V M X5R 04 02

10U 6.3V M X5R 04 02

PX@

PX@

PX@

CV139

CV153

1

1

2

2

@

PX@

22UC_6.3VC_MC_ X5RC_0603

22UC_6.3VC_MC_ X5RC_0603

22UC_6.3VC_MC_ X5RC_0603

CV220

1

1

2

2

PX@

PX@

B B

A A

5

10U_0603_6.3V6M

+3VGS

CV511

CV513

1

1

2

2

@

@

1U_0402_6.3V6K

+1.8VGS

10U_0603_6.3V6M

+0.95VGS

10U_0603_6.3V6M

CV241

1

2

@

CV240

1

2

@

CV242

CV243

1

1

2

2

@

1U_0402_6.3V6K

10U_0603_6.3V6M

@

CV239

CV238

@

10U_0603_6.3V6M

CV521

1

1

2

1

2

2

@

@

1U_0402_6.3V6K

0.1U_0201_6.3V6-K

140S AST GPU VGS power change to PMIC solution, reserve old power solution capacitor

Security Classificat ion

Security Classificat ion

Security Classificat ion

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2017/03/14

2017/03/14

2017/03/14

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2017/03/14

2017/03/14

2017/03/14

Title

Title

Title

ATI_EXO-PRO_Power

ATI_EXO-PRO_Power

ATI_EXO-PRO_Power

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

S145AST

S145AST

S145AST

Thursday, October 25, 2018

Thursday, October 25, 2018

Thursday, October 25, 2018

19 50

19 50

19 50

1

0.2

0.2

0.2

5

Vinafix.com

4

3

2

1

DQA0_[31..0]

DQA1_[31..0]

D D

MAA0_[8..0]

MAA1_[8..0]

C C

B B

RV6 1

40.2_0402_1%

RV6 5

100_0402_1%

RV6 2

40.2_0402_1%

RV6 6

100_0402_1%

+1.35VGS

12

PX@

12

PX@

+1.35VGS

12

PX@

12

PX@

MV R E F D _ A

1

2

MV R E F S _ A

1

2

DQA0_[31..0] 21

DQA1_[31..0] 21

MAA0_[8..0] 2 1

MAA1_[8..0] 2 1

CV1 54
1U_0402_6.3V6K

PX@

CV1 57
1U_0402_6.3V6K

PX@

RV5 5

PX@

1 2

120_0402_1%

TV8Test_Point_16MIL@
TV9Test_Point_16MIL@

MV R E F D _ A
MV R E F S _ A

MEM_CALRP0

1
1

DQA0_0
DQA0_1
DQA0_2
DQA0_3
DQA0_4
DQA0_5
DQA0_6
DQA0_7
DQA0_8
DQA0_9
DQA0_10
DQA 0_ 11
DQA 0_ 12
DQA 0_ 13
DQA 0_ 14
DQA 0_ 15
DQA0_16
DQA0_17
DQA 0_ 18
DQA 0_ 19
DQA 0_ 20
DQA 0_ 21
DQA 0_ 22
DQA 0_ 23
DQA 0_ 24
DQA 0_ 25
DQA 0_ 26
DQA0_27
DQA0_28
DQA0_29
DQA 0_ 30
DQA 0_ 31
DQA 1_ 0
DQA 1_ 1
DQA 1_ 2
DQA 1_ 3
DQA 1_ 4
DQA 1_ 5
DQA 1_ 6
DQA 1_ 7
DQA 1_ 8
DQA 1_ 9
DQA 1_ 10
DQA 1_ 11
DQA 1_ 12
DQA 1_ 13
DQA1_14
DQA1_15
DQA 1_ 16
DQA 1_ 17
DQA 1_ 18
DQA 1_ 19
DQA 1_ 20
DQA 1_ 21
DQA 1_ 22
DQA 1_ 23
DQA 1_ 24
DQA 1_ 25
DQA 1_ 26
DQA 1_ 27
DQA 1_ 28
DQA 1_ 29
DQA 1_ 30
DQA 1_ 31

DRAMRST

CLKTESTA
CLKTESTB

K27

J29
H30
H32
G29
F28
F32
F30
C30
F27
A28
C28
E27
G26
D26
F25
A25
C25
E25
D24
E23
F23
D22
F21
E21
D20
F19
A19
D18
F17
A17
C17
E17
D16
F15
A15
D14
F13
A13
C13
E11
A11
C11
F11

A9

C9

F9

D8

E7
A7

C7

F7
A5
E5

C3

E1
G7
G6
G1
G3

J6

J1

J3

J5

K26

J26

J25

K25

L10

K8

L7

UV1 C

DQA0_0
DQA0_1
DQA0_2
DQA0_3
DQA0_4
DQA0_5
DQA0_6
DQA0_7
DQA0_8
DQA0_9
DQA0_10
DQA0_11
DQA0_12
DQA0_13
DQA0_14
DQA0_15
DQA0_16
DQA0_17
DQA0_18
DQA0_19
DQA0_20
DQA0_21
DQA0_22
DQA0_23
DQA0_24
DQA0_25
DQA0_26
DQA0_27
DQA0_28
DQA0_29
DQA0_30
DQA0_31
DQA1_0
DQA1_1
DQA1_2
DQA1_3
DQA1_4
DQA1_5
DQA1_6
DQA1_7
DQA1_8
DQA1_9
DQA1_10
DQA1_11
DQA1_12
DQA1_13
DQA1_14
DQA1_15
DQA1_16
DQA1_17
DQA1_18
DQA1_19
DQA1_20
DQA1_21
DQA1_22
DQA1_23
DQA1_24
DQA1_25
DQA1_26
DQA1_27
DQA1_28
DQA1_29
DQA1_30
DQA1_31

MVREFDA
MVREFSA

NC#J25
MEM_CALRP0

DRAM_RST

CLKTESTA
CLKTESTB

@

GDDR5/DDR3GDDR5/DDR3

MAA0_0/MAA_0
MAA0_1/MAA_1
MAA0_2/MAA_2
MAA0_3/MAA_3
MAA0_4/MAA_4
MAA0_5/MAA_5
MAA0_6/MAA_6

MAA0_7/MAA_7
MAA0_8/MAA_13
MAA0_9/MAA_15

MAA1_0/MAA_8

MAA1_1/MAA_9
MAA1_2/MAA_10
MAA1_3/MAA_11
MAA1_4/MAA_12

MAA1_5/MAA_BA2
MAA1_6/MAA_BA0
MAA1_7/MAA_BA1

MAA1_8/MAA_14

MAA1_9/RSVD

WCKA0_0/DQM A0_0

WCKA0B_0/DQMA0_1

WCKA0_1/DQM A0_2

WCKA0B_1/DQMA0_3

WCKA1_0/DQM A1_0

MEMORY INTERFACE

WCKA1B_0/DQMA1_1

WCKA1_1/DQM A1_2

WCKA1B_1/DQMA1_3

EDCA0_0/QSA0_0
EDCA0_1/QSA0_1
EDCA0_2/QSA0_2
EDCA0_3/QSA0_3
EDCA1_0/QSA1_0
EDCA1_1/QSA1_1
EDCA1_2/QSA1_2
EDCA1_3/QSA1_3

DDBIA0_0/QSA0_0B
DDBIA0_1/QSA0_1B
DDBIA0_2/QSA0_2B
DDBIA0_3/QSA0_3B
DDBIA1_0/QSA1_0B
DDBIA1_1/QSA1_1B
DDBIA1_2/QSA1_2B
DDBIA1_3/QSA1_3B

ADBIA0/ODTA0
ADBIA1/ODTA1

CSA0B_0
CSA0B_1

CSA1B_0
CSA1B_1

CLKA0

CLKA0B

CLKA1

CLKA1B

RASA0B
RASA1B

CASA0B
CASA1B

CKEA0
CKEA1

WEA0B
WEA1B

MA A 0 _ 0

K17

MA A 0 _ 1

J20

MA A 0 _ 2

H23

MA A 0 _ 3

G23

MA A 0 _ 4

G24

MA A 0 _ 5

H24

MA A 0 _ 6

J19

MA A 0 _ 7

K19

MA A 0 _ 8

G20
L17

MA A 1 _ 0

J14

MA A 1 _ 1

K14

MA A 1 _ 2

J11

MA A 1 _ 3

J13

MA A 1 _ 4

H11

MA A 1 _ 5

G11

MA A 1 _ 6

J16

MA A 1 _ 7

L15

MA A 1 _ 8

G14
L16

WCKA0_0

E32

WCKA0#_0

E30

WCKA0_1

A21

WCKA0#_1

C21

WCKA1_0

E13

WCKA1#_0

D12

WCKA1_1

E3

WCKA1#_1

F4

EDCA0_0

H28

EDCA0_1

C27

EDCA0_2

A23

EDCA0_3

E19

EDCA1_0

E15

EDCA1_1

D10

EDCA1_2

D6

EDCA1_3

G5

DDB I A0 _0

H27

DDB I A0 _1

A27

DDBIA0_2

C23

DDBIA0_3

C19

DDB I A1 _0

C15

DDB I A1 _1

E9

DDB I A1 _2

C5

DDB I A1 _3

H4

L18

ADBIA0

K16

ADBIA1

H26

CLK A 0

H25

CLK A #0

G9

CLK A 1

H9

CLK A #1

G22

RASA#0

G17

RASA#1

G19

CASA#0

G16

CASA#1

CSA 0 #_ 0

H22
J22

CSA 1 #_ 0

G13
K13

K20

CKEA0

J17

CKEA1

G25

WEA#0

H10

WEA#1

WCKA0_0 2 1
WCKA0#_0 21
WCKA0_1 2 1
WCKA0#_1 21
WCKA1_0 2 1
WCKA1#_0 21
WCKA1_1 2 1
WCKA1#_1 21

EDCA0_0 21
EDCA0_1 21
EDCA0_2 21
EDCA0_3 21
EDCA1_0 21
EDCA1_1 21
EDCA1_2 21
EDCA1_3 21

DDB I A0 _0 21
DDB I A0 _1 21
DDB I A0 _2 21
DDB I A0 _3 21
DDB I A1 _0 21
DDB I A1 _1 21
DDB I A1 _2 21
DDBIA1_3 21

ADBIA0 2 1
ADBIA1 2 1

CLK A 0 21
CLK A #0 2 1

CLK A 1 21
CLK A #1 2 1

RAS A #0 2 1
RAS A #1 2 1

CAS A #0 2 1
CASA#1 21

CSA 0 #_ 0 21

CSA 1 #_ 0 21

CKEA0 21
CKEA1 21

WEA#0 21
WEA#1 21

1 2

RV5 6

PX@

PX@

10_0402_5%

12

5

A A

DRAMRST

RV5 8

4.99K_0402_1%

1

CV1 47
120P_0402_50V8-J

PX@

2

RV5 7

1 2

51.1_0402_1%

PX@

DRAM_RST 21

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEI THER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEI THER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEI THER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2017/03/14

2017/03/14

2017/03/14

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Decipher ed Date

Decipher ed Date

Decipher ed Date

2

2017/03/14

2017/03/14

2017/03/14

Title

Title

Title

ATI_EXO-PRO_MEM IF

ATI_EXO-PRO_MEM IF

ATI_EXO-PRO_MEM IF

Size Doc ument Number Rev

Size Doc ument Number Rev

Size Doc ument Number Rev

Cus to m

Cus to m

Cus to m

Dat e: Sheet o f

Dat e: Sheet o f

Dat e: Sheet o f

S145AST

S145AST

S145AST

Thursday, October 25, 2018

Thursday, October 25, 2018

Thursday, October 25, 2018

20 50

20 50

20 50

1

0.2

0.2

0.2

5

Vinafix.com

1

CV522
1U_0402_6.3V6K

@

2

1

CV361
1U_0402_6.3V6K

@

2

1

CV524
1U_0402_6.3V6K

@

2

1

CV523
1U_0402_6.3V6K

@

2

1

CV526
1U_0402_6.3V6K

@

2

1

CV525
1U_0402_6.3V6K

PX@

2

PX@

CV86

0.1U_0201_6.3V6-K

10U_0603_6.3V6M

VREFD1_A0

VREFD2_A0

VREFC_A0

1

2

0.1U_0201_6.3V6-K

1

CD@

2

CV79

DQA0_[0..31]

MAA0_[0..8]

MAA1_[8..0]

PX@

1

1

CD@

2

2

CV88

0.1U_0201_6.3V6-K

CV87

0.1U_0201_6.3V6-K

PX@

PX@

1

1

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

CV81

CV80

DQA1_[31..0]20

PX@

1

1

1

CD@

CV505
33P_0402_50V8J

2

2

2

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K
CV635

CV628

RF_PXNS@

PX@

PX@

1

1

1

CD@

2

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

CV83

CV82

CV545

DQA0_[0..31]20

MAA0_[0..8]20

MAA1_[8..0]20

+1.35VGS

12

RV1018

2.37K_0402_1%

@

D D

12

RV1019

5.49K_0402_1%

@

+1.35VGS

12

RV1020

2.37K_0402_1%

@

12

RV1021

5.49K_0402_1%

@

+1.35VGS

12

RV1023

2.37K_0402_1%

C C

PX@

12

RV1022

5.49K_0402_1%

PX@

+1.35VGS

UV5 SIDE

PX@

PX@

1

1

1

CD@

2

2

2

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

CV85

CV552

CV155

+1.35VGS

UV5 SIDE

PX@

PX@

1

1

1

CD@

2

2

B B

2

CV78

CV548

10U_0603_6.3V6M

10U_0603_6.3V6M

CV634

DQA1_[31..0]

EDCA0_0

EDCA0_020

EDCA0_1

EDCA0_120

EDCA0_2

EDCA0_220

EDCA0_3

EDCA0_320

DDBIA0_0

DDBIA0_020

DDBIA0_1

DDBIA0_120

DDBIA0_2

DDBIA0_220

DDBIA0_3

DDBIA0_320

CLKA0

CLKA020

CLKA#0

CLKA#020

CKEA0

CKEA020

MAA0_2
MAA0_5
MAA0_4
MAA0_3

MAA0_7
MAA0_1
MAA0_0
MAA0_6
MAA0_8

ZQ_UV3

1 2

RV1360

PX@

120_0402_1%

ADBI A0

ADBIA020

RASA#0

RASA#020

CSA0#_0

CSA0#_020

CASA#0

CASA#020

WEA#0

WEA#020

WCKA0#_0

WCKA0#_020

WCKA0_0

WCKA0_020

WCKA0#_1

WCKA0#_120

WCKA0_1

WCKA0_120

VREFD1_A0
VREFD2_A0
VREFC_A0

DRAM_RST

DRAM_RST20

+1.35VGS

PX@

1

1

CD@

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

CV546

CV547

4

0) 1R0LUURU

UV5

MF=0 MF=1 MF=0MF=1

C2

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A4

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/ RF U/N C

A5

VPP/ NC1

U5

VPP/ NC2

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WCK23#

D4

WCK01 WCK23

P5

WCK23# WCK01#

P4

WCK23 WCK01

A10

VREFD1

U10

VREFD2

J14

VREF C

J2

RESET#

H1

VSS1

K1

VSS2

B5

VSS3

G5

VSS4

L5

VSS5

T5

VSS6

B10

VSS7

D10

VSS8

G10

VSS9

L10

VSS1 0

P10

VSS1 1

T10

VSS1 2

H14

VSS1 3

K14

VSS1 4

G1

VDD1

L1

VDD2

G4

VDD3

L4

VDD4

C5

VDD5

R5

VDD6

C10

VDD7

R10

VDD8

D11

VDD9

G11

VDD10

L11

VDD11

P11

VDD12

G14

VDD13

L14

VDD14

170-BALL

SGRAM GDDR5

H5GQ1H24AFR-T2L_BGA170

@

DQ24 DQ0
DQ25 DQ1
DQ26 DQ2
DQ27 DQ3
DQ28 DQ4
DQ29 DQ5
DQ30 DQ6
DQ31 DQ7
DQ16 DQ8
DQ17 DQ9

DQ18 DQ10
DQ19 DQ11
DQ20 DQ12
DQ21 DQ13
DQ22 DQ14
DQ23 DQ15
DQ8 DQ16
DQ9 DQ17
DQ10 DQ18
DQ11 DQ19
DQ12 DQ20
DQ13 DQ21
DQ14 DQ22
DQ15 DQ23
DQ0 DQ24
DQ1 DQ25
DQ2 DQ26
DQ3 DQ27
DQ4 DQ28
DQ5 DQ29
DQ6 DQ30
DQ7 DQ31

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21
VDDQ22
VDDQ23
VDDQ24
VDDQ25
VDDQ26
VDDQ27
VDDQ28
VDDQ29
VDDQ30
VDDQ31
VDDQ32
VDDQ33
VDDQ34
VDDQ35
VDDQ36

VSSQ 1

VSSQ 2

VSSQ 3

VSSQ 4

VSSQ 5

VSSQ 6

VSSQ 7

VSSQ 8

VSSQ 9
VSSQ 10
VSSQ 11
VSSQ 12
VSSQ 13
VSSQ 14
VSSQ 15
VSSQ 16
VSSQ 17
VSSQ 18
VSSQ 19
VSSQ 20
VSSQ 21
VSSQ 22
VSSQ 23
VSSQ 24
VSSQ 25
VSSQ 26
VSSQ 27
VSSQ 28
VSSQ 29
VSSQ 30
VSSQ 31
VSSQ 32
VSSQ 33
VSSQ 34
VSSQ 35
VSSQ 36

3

+1.35VGS

1 2

RV1346 60.4_0201_1%PX@

1 2

RV1347 60.4_0201_1%PX@

1 2

RV1349 60.4_0201_1%PX@

1 2

RV1348 60.4_0201_1%PX@

DQA0_1

A4

DQA0_2

A2

DQA0_7

B4

DQA0_5

B2

DQA0_6

E4

DQA0_4

E2

DQA0_3

F4

DQA0_0

F2

DQA0_8

A11

DQA0_9

A13

DQA0_10

B11

DQA0_11

B13

DQA0_14

E11

DQA0_12

E13

DQA0_15

F11

DQA0_13

F13

DQA0_22

U11

DQA0_20

U13

DQA0_23

T11

DQA0_21

T13

DQA0_19

N11

DQA0_18

N13

DQA0_16

M11

DQA0_17

M13

DQA0_27

U4

DQA0_28

U2

DQA0_26

T4

DQA0_29

T2

DQA0_25

N4

DQA0_30

N2

DQA0_24

M4

DQA0_31

M2

B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14

A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14

Byte 0

Byte 1

Byte 2

Byte 3

+1.35VGS

+1.35VGS

CLKA0
CLKA#0

CLKA1
CLKA#1

RV1363

EDCA1_120
EDCA1_020
EDCA1_220
EDCA1_320

DDBIA1_120
DDBIA1_020
DDBIA1_220
DDBIA1_320

CLKA120
CLKA#120
CKEA120

ADBI A120
CASA#120
WEA#120
RASA#120
CSA1#_020

WCKA1#_020
WCKA1_020

WCKA1#_120
WCKA1_120

1 2

PX@

120_0402_1%

+1.35VGS

EDCA1_1
EDCA1_0
EDCA1_2
EDCA1_3

DDBIA1_1
DDBIA1_0
DDBIA1_2
DDBIA1_3

CLKA1
CLKA#1
CKEA1

MAA1_4
MAA1_3
MAA1_2
MAA1_5

MAA1_0
MAA1_6
MAA1_7
MAA1_1
MAA1_8

ZQ_UV4

ADBI A1
CASA#1
WEA#1
RASA#1
CSA1#_0

WCKA1#_0
WCKA1_0

WCKA1#_1
WCKA1_1

VREFD1_A1
VREFD2_A1
VREFC_A1

DRAM_RST

0) 0LUURU

UV6

MF=0 MF=1 MF=0MF=1

C2

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A4

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/ RF U/N C

A5

VPP/ NC1

U5

VPP/ NC2

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WCK23#

D4

WCK01 WCK23

P5

WCK23# WCK01#

P4

WCK23 WCK01

A10

VREFD1

U10

VREFD2

J14

VREF C

J2

RESET#

H1

VSS1

K1

VSS2

B5

VSS3

G5

VSS4

L5

VSS5

T5

VSS6

B10

VSS7

D10

VSS8

G10

VSS9

L10

VSS1 0

P10

VSS1 1

T10

VSS1 2

H14

VSS1 3

K14

VSS1 4

G1

VDD1

L1

VDD2

G4

VDD3

L4

VDD4

C5

VDD5

R5

VDD6

C10

VDD7

R10

VDD8

D11

VDD9

G11

VDD10

L11

VDD11

P11

VDD12

G14

VDD13

L14

VDD14

170-BALL

SGRAM GDDR5

H5GQ1H24AFR-T2L_BGA170

@

DQ24 DQ0
DQ25 DQ1
DQ26 DQ2
DQ27 DQ3
DQ28 DQ4
DQ29 DQ5
DQ30 DQ6
DQ31 DQ7
DQ16 DQ8
DQ17 DQ9

DQ18 DQ10
DQ19 DQ11
DQ20 DQ12
DQ21 DQ13
DQ22 DQ14
DQ23 DQ15
DQ8 DQ16
DQ9 DQ17
DQ10 DQ18
DQ11 DQ19
DQ12 DQ20
DQ13 DQ21
DQ14 DQ22
DQ15 DQ23
DQ0 DQ24
DQ1 DQ25
DQ2 DQ26
DQ3 DQ27
DQ4 DQ28
DQ5 DQ29
DQ6 DQ30
DQ7 DQ31

VDDQ 1
VDDQ 2
VDDQ 3
VDDQ 4
VDDQ 5
VDDQ 6
VDDQ 7
VDDQ 8

VDDQ 9
VDDQ 10
VDDQ 11
VDDQ 12
VDDQ 13
VDDQ 14
VDDQ 15
VDDQ 16
VDDQ 17
VDDQ 18
VDDQ 19
VDDQ 20
VDDQ 21
VDDQ 22
VDDQ 23
VDDQ 24
VDDQ 25
VDDQ 26
VDDQ 27
VDDQ 28
VDDQ 29
VDDQ 30
VDDQ 31
VDDQ 32
VDDQ 33
VDDQ 34
VDDQ 35
VDDQ 36

VSSQ 10
VSSQ 11
VSSQ 12
VSSQ 13
VSSQ 14
VSSQ 15
VSSQ 16
VSSQ 17
VSSQ 18
VSSQ 19
VSSQ 20
VSSQ 21
VSSQ 22
VSSQ 23
VSSQ 24
VSSQ 25
VSSQ 26
VSSQ 27
VSSQ 28
VSSQ 29
VSSQ 30
VSSQ 31
VSSQ 32
VSSQ 33
VSSQ 34
VSSQ 35
VSSQ 36

VSSQ 1
VSSQ 2
VSSQ 3
VSSQ 4
VSSQ 5
VSSQ 6
VSSQ 7
VSSQ 8
VSSQ 9

2

UV6 SIDE

PX@

1

2

0.1U_0201_6.3V6-K
CV566

UV6 SIDE

PX@

1

2

1U_0402_6.3V6K

CV571

10U_0603_6.3V6M

2.37K_0402_1%

5.49K_0402_1%

2.37K_0402_1%

5.49K_0402_1%

2.37K_0402_1%

5.49K_0402_1%

PX@

1

1

CD@

2

2

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K
CV567

CV555

PX@

PX@

1

1

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

CV575

CV574

PX@

1

2

CV626

10U_0603_6.3V6M

DQA1_11

A4

DQA1_15

A2

DQA1_10

B4

DQA1_14

B2

DQA1_9

E4

DQA1_13

E2

DQA1_8

F4

DQA1_12

F2

DQA1_1

A11

DQA1_0

A13

DQA1_2

B11

DQA1_3

B13

DQA1_4

E11

DQA1_7

E13

DQA1_5

F11

DQA1_6

F13

DQA1_22

U11

DQA1_20

U13

DQA1_23

T11

DQA1_21

T13

DQA1_18

N11

DQA1_19

N13

DQA1_17

M11

DQA1_16

M13

DQA1_27

U4

DQA1_28

U2

DQA1_26

T4

DQA1_29

T2

DQA1_25

N4

DQA1_30

N2

DQA1_24

M4

DQA1_31

M2

B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14

A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14

+1.35VGS

Byte 1

Byte 0

Byte 2

Byte 3

+1.35VGS

+1.35VGS

+1.35VGS

PX@

PX@

1

1

2

2

0.1U_0201_6.3V6-K

CV561

CV553

PX@

1

1

CD@

2

2

1U_0402_6.3V6K

CV573

CV572

UV6 SIDE

PX@

PX@

1

1

2

2

CV577

10U_0603_6.3V6M

CV576

1

+1.35VGS

12

1

CV528

RV1025

1U_0402_6.3V6K

@

@

2

VREFD2_ A1

12

1

RV1026

CV527
1U_0402_6.3V6K

@

@

2

+1.35VGS

12

1

CV530

RV1028

1U_0402_6.3V6K

@

@

2

VREFD1_ A1

12

1

CV529

RV1027

1U_0402_6.3V6K

@

@

2

+1.35VGS

12

1

RV1029

CV532
1U_0402_6.3V6K

PX@

@

2

VREF C_ A1

12

1

CV531

RV1030

1U_0402_6.3V6K

PX@

PX@

2

PX@

1

1

1

1

CD@

CD@

2

0.1U_0201_6.3V6-K

CV554

CD@

1

2

1U_0402_6.3V6K

CV568

CV562
33P_0402_50V8J

RF_PXNS@

2

2

2

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K
CV565

CV629

CD@

PX@

1

1

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

CV569

CV570

A A

5

Title

Title

Security Classification

Security Classification

Security Classification

Iss u e d D at e

Iss u e d D at e

Iss u e d D at e

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2017/02/08

2017/02/08

2017/02/08

2

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2017/02/08

2017/02/08

2017/02/08

Title

ATI_EXO-PRO_VRAM_A

ATI_EXO-PRO_VRAM_A

ATI_EXO-PRO_VRAM_A

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

S145AST

S145AST

S145AST

Thursday, October 25, 2018

Thursday, October 25, 2018

Thursday, October 25, 2018

1

21 51

21 51

21 51

0.2

0.2

0.2

5

Vinafix.com

D D

C C

4

3

2

1

B B

A A

5

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2017/02/08

2017/02/08

2017/02/08

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered D ate

Deciphered D ate

Deciphered D ate

2

2017/02/08

2017/02/08

2017/02/08

Title

ATI_EXO-PRO_VRAM_B

ATI_EXO-PRO_VRAM_B

ATI_EXO-PRO_VRAM_B

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

S145AST

S145AST

S145AST

Thursday, October 25, 2018

Thursday, October 25, 2018

Thursday, October 25, 2018

22 51

22 51

1

22 51

0.2

0.2

0.2

5

Vinafix.com

LCD POWER CIRCUIT

+3VS +LCDVDD_CON

1U_0402_6.3V6K

1

C1

D D

PCH_ENVDD

2

PCH_ENVDD6

U7

5

OUT

IN

GND

4

OCB

EN

SY6288C20AAC_SOT23-5

PCH_ENVDD

12

R35
100K_0402_5%

1

1 2

R4 0_0805_5%

2

3

4

B+ to +LEDVDD POWER

C1106 22P_0402_50V8-J

1

C2

4.7U_0603_6.3V6K

2

1

2

RF_ NS @

V20B+

R22 0_0805_5%@

1 2

F2

1 2

3A_32V_0497003PKRHF

F2 change to SP040004S00

3

+LEDVDD

2

1

CMOS Camera

ϮϴϬŵŝůϮϴϬŵŝů

0.1U_0201_25V6-K

4.7U_0805_25V6-K
C25

C23

1

CD@

1

2

2

C23 0.1u for G HSW panel blink issue

+3VS

+3VS

1 2

R12 0 0_0402_5%

F3

0.5A_32V_ERBRD0R50X

+3VS _CMOS

1

C3

@

2

21

@

0.1U_0201_6.3V6-K

W= 40m ils

1

C24

2

EMC_NS@

C24 close to JEDP1

.047U_0201_6.3V6K

R9
100K_0402_1%

@

1 2

R15
100K_0402_1%

@

1 2

+5VS _TS+5V S

CTS 1

TS@

ME @

JEDP1

+LEDV DD

APU_EDP_TX0+6
APU_EDP_TX0-6

APU_EDP_TX1+6
APU_EDP_TX1-6

APU_EDP_AUX6
APU_EDP_AUX#6

APU_EDP_TX0+ EDP_TX0+
APU_EDP_TX0- EDP_TX0-

APU_EDP_TX1+ EDP_TX1+
APU_EDP_TX1- EDP_TX1-

APU_EDP_AUX EDP_A UX
APU_EDP_AUX# EDP_AUX#

APU_EDP_HPD6

W=6 0mils

DMIC_CLK36

DMI C_ DA TA36

USB20_P28
USB20_N28

1 2

C19 0.1U_0201_6.3V6-K
C16 0.1U_0201_6.3V6-K

1 2

C17 0.1U_0201_6.3V6-K

1 2
1 2

C18 0.1U_0201_6.3V6-K

C20 0.1U_0201_6.3V6-K

1 2
1 2

C21 0.1U_0201_6.3V6-K

+LCDVDD_CON

+3VS_CMOS

1 2

R18 2 0_0402_5%
R18 3 0_0402_5%

1 2

DI SP OF F#
INVT_PWM

USB20_P2_R
USB20_N2_R

W=4 0mils

1

EC_TS_ON35

2

USB20_N68
USB20_P68

RTS 3 0_0402_5%TS@

RTS 4 0_0402_5%TS@
RTS 5 0_0402_5%TS@

1 2
1 2

12

TS_RS

USB20_N6_CONN
USB20_P6_CONN

change symbol to SP021412291 by amy 0620

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

27

28

28

29

29

GND1

30

30

GND2

HIGHS_FC5AF301-3181H

JTS1

1

1

2

2

3

3

4

4

5

5

6

6

7

GND1

8

GND2

HIGHS_WS 83061-S0171-HF

ME @

31
32

EDP_AUX
EDP_AUX#

F12

1 2

RTS 1 0_0402_5%@

1 2

RTS 2 0_0402_5%TS@

F11

1 2

1 2

@

@

R8
100K_0402_1%

@

R13
100K_0402_1%

@

21

0.1u_0201_10V6K

21

APU output enable Voh min is 1.8V-0.45V=1.35V

+3VS

PCH_ENBKL

R11

@

1 2

C C

B B

BKOFF#35

PCH_ENBKL6

0_0402_5%

1 2

R12 0_0402_5%

R14 0_0402_5%

1 2

R10

4.7K_0402_5%

@

1 2

DI SP OF F#

ENBKL

12

R16
100K_0402_5%

PCH_EDP_PWM6

ENBKL 3 5

L12

USB20_N2 USB20_N2_R

USB20_P2 USB20_P2_R

DMIC_CLK

EMC_NS@

C11

1

2

33P_0402_50V8J

1

1

4

00

4

00

EXC24CH900U_4P

DI SP OF F#

EMC_NS@

EMC_NS@

1

2

1 2

R19 0_0402_5%

can cost down R20 for CZ

2

2

3

3

INVT_PWM

C12

470P_0201_50V7-K

EMC_NS@

INVT_PWM

12

R20
100K_0402_5%

C13

1

470P_0201_50V7-K

2

EMC

+3VS

0.5A_32V_ERBRD0R50X

Touch Screen

USB20_P6_CONN

USB20_P6

USB20_N6

A A

L15

1

1

00

00

00

4

00

4

EXC24CH900U_4P

EMC_NS@

&ŽƌD/

2

3

2

3

USB20_P6_CONN

USB20_N6_CONN

+5VS_TS

USB20_N6_CONN

1

D2

1

2

AZ5725-01F.R7GR_DFN1006P2X2

2

EMC_NS@

&Žƌ^

3

2

0.5A_32V_ERBRD0R50X

D75 3
AZC199-02S.R7G_SOT23-3

EMC_NS@

1

5

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEI THER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEI THER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEI THER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2017/03/14

2017/03/14

2017/03/14

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Decipher ed Date

Decipher ed Date

Decipher ed Date

2

2017/03/14

2017/03/14

2017/03/14

Title

eDP/CMOS/Touch screen

eDP/CMOS/Touch screen

eDP/CMOS/Touch screen

Size Do cu m ent Nu mb er Rev

Size Do cu m ent Nu mb er Rev

Size Do cu m ent Nu mb er Rev

Cus to m

Cus to m

Cus to m

Thursday, October 25, 2018

Thursday, October 25, 2018

Thursday, October 25, 2018

Dat e: Sheet of

Dat e: Sheet of

Dat e: Sheet of

S145AST

S145AST

S145AST

1

23 5 0

23 5 0

23 5 0

0.2

0.2

0.2

5

Vinafix.com

4

3

2

1

L2

HDMI_CLK-_C

HDMI_CLK+_C

D D

C C

B B

HDMI_CLK-_C

HDMI_CLK+_C

HDMI_TX0-_C

HDMI_TX0+_C

HDMI_TX1-_C

HDMI_TX1+_C

HDMI_TX2-_C

HDMI_TX2+_C

HDMI_TX0-_C

HDMI_TX0+_C

HDMI_TX1-_C

HDMI_TX1+_C

HDMI_TX2-_C

HDMI_TX2+_C

1 2

R29 499_0402_1%

1 2

R30 499_0402_1%

1 2

R31 499_0402_1%

1 2

R32 499_0402_1%

1 2

R33 499_0402_1%

1 2

R34 499_0402_1%

1 2

R37 499_0402_1%

1 2

R38 499_0402_1%

+3VS

EMC@

1

00

1

00

4

4

EXC24CH900U_4P

L3

EMC@

1

1

00

00

00

4

00

4

EXC24CH900U_4P

L4

EMC@

1

1

00

00

00

4

00

4

EXC24CH900U_4P

L5

EMC@

1

1

00

00

00

4

4

00

EXC24CH900U_4P

L2N7002KWT1G_SOT323-3

R42

2

2

3

3

2

2

3

3

2

2

3

3

2

2

3

3

2

G

1 2

@

100K_0402_5%

HDMI_CLK-_CON

HDMI_CLK+_CON

HDMI_TX0-_CON

HDMI_TX0+_CON

HDMI_TX1-_CON

HDMI_TX1+_CON

HDMI_TX2-_CON

HDMI_TX2+_CON

13

Q13

1 2

C26 3.3P_0201_50V8-C

1 2

C27 3.3P_0201_50V8-C

1 2

C28 3.3P_0201_50V8-C

1 2

C29 3.3P_0201_50V8-C

1 2

C30 3.3P_0201_50V8-C

1 2

C31 3.3P_0201_50V8-C

1 2

C32 3.3P_0201_50V8-C

1 2

C33 3.3P_0201_50V8-C

EMC

D

S

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

APU_HDMI_HPD6

APU_DDC_CLK6

APU_DDC_DATA6

+3VS

100K_0402_5%

R260

Q43

E3 1C

12

LMBT3904WT1G_SOT323- 3 B 2

APU_HDMI_TX0+6
APU_HDMI_TX0-6
APU_HDMI_TX1+6
APU_HDMI_TX1-6
APU_HDMI_TX2+6
APU_HDMI_TX2-6

APU_HDMI_CLK+6
APU_HDMI_CLK-6

Q1A

APU_DDC_DATA

Follow Zx05 and beema

1 2

R202 150K _0402_5%

C38 0.1U_0201_6.3V6- K
C37 0.1U_0201_6.3V6- K
C40 0.1U_0201_6.3V6- K
C39 0.1U_0201_6.3V6- K
C42 0.1U_0201_6.3V6- K
C41 0.1U_0201_6.3V6- K

C36 0.1U_0201_6.3V6- K
C35 0.1U_0201_6.3V6- K

S

L2N7002KDW1T1G_SOT363-6

R257

100K_0402_5%

1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2

Q1B

S

L2N7002KDW1T1G_SOT363-6

G

2

61

D

12

HDMI_TX 0+_C
HDMI_TX 0-_C
HDMI_TX 1+_C
HDMI_TX 1-_C
HDMI_TX 2+_C
HDMI_TX 2-_C

HDMI_CLK+_C
HDMI_CLK-_C

+3VS

G

5

HDMICLK _RAPU_DDC_CLK

34

D

HDMIDA T_R

R46 0_0402_5%@
R45 0_0402_5%@
R48 0_0402_5%@
R47 0_0402_5%@
R50 0_0402_5%@
R49 0_0402_5%@

R44 0_0402_5%@
R43 0_0402_5%@

+5VS_HDM I

3

2

D4

LBAT54SWT1G_SOT 323-3@

1

HDMI_DET

12
12
12
12
12
12

12
12

+5VS

SUSP12,37

HDMI_TX0+_CON
HDMI_TX0-_CON
HDMI_TX1+_CON
HDMI_TX1-_CON HDMI_DET
HDMI_TX2+_CON
HDMI_TX2-_CON

HDMI_CLK+_CON
HDMI_CLK-_CON

HDMI_DE T HDM I_DET

HDMIDA T_R

HDMICLK _R HDMICLK_R

+5VS_HDMI

D5

2

1

3

RB491D_SOT23-3

@

1 3

DSQ22

LP2301ALT1G_SOT23-3

G

2

+5VS_HDMI

18

7
9
4
6
1
3

8
5
2

11
10
12

ME@

D3

1



2



4



5

3



8

AZ1045-04F_DFN2510P10E-10-9

EMC_NS@

1.1A_8V_1206L110THYR

10U 6.3V M X5R 0402

JHDMI1

+5V_Power

TMDS_Data0+
TMDS_Data0­TMDS_Data1+
TMDS_Data1­TMDS_Data2+
TMDS_Data2-

TMDS_Data0_Shield
TMDS_Data1_Shield
TMDS_Data2_Shield

TMDS_Clock_Shield
TMDS_Clock+
TMDS_Clock-

ALLTO_C128AF-K1935-L

F1

21

CC1279

DDC/CEC_Ground

Hot_Pl ug_Detec t









@

GND1
GND2
GND3
GND4

Utility

9

HDMIDAT_R

8

7

+5VS_HDMI

6

EMC

+5VS_HDMI+5VS_HDMI_F

2

1

C34

0.1u_0201_10V6K

1

2

HDMICLK_R

15

SCL

HDMIDAT_R

16

SDA

13

CEC

17
19

14

20
21
22
23

RP2

2.2K_0404_4P2R_5%

1 4

2 3

D6

1









8

EMC_NS@









HDMI_TX0+_CON HDMI_TX0+_CON

A A

2

4

5

3

AZ1045-04F_DFN2510P10E-10-9

5

9

HDMI_CLK-_CONHDMI_CLK-_CON

8

7

HDMI_TX0-_CONHDM I_TX0-_CON HDMI_TX2+_CON

6

HDMI_TX1-_CONHDMI_CLK+_CON HDMI_CLK+_CON

HDMI_TX1+_CON

HDMI_TX2-_CON

D7

1



2



4



5

3



8

AZ1045-04F_DFN2510P10E-10-9

EMC_NS@

4









9

8

7

6

EMC

HDMI_TX1-_CON

HDMI_TX1+_CON

HDMI_TX2-_CON

HDMI_TX2+_CON

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEE RING DRAWING IS THE PROPRIETARY P ROPERTY OF LC FUTURE CENTER. AND CONT AINS CONFIDENTIAL

THIS SHEET OF ENGINEE RING DRAWING IS THE PROPRIETARY P ROPERTY OF LC FUTURE CENTER. AND CONT AINS CONFIDENTIAL

THIS SHEET OF ENGINEE RING DRAWING IS THE PROPRIETARY P ROPERTY OF LC FUTURE CENTER. AND CONT AINS CONFIDENTIAL
AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R& D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R& D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R& D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2017/03/14

2017/03/14

2017/03/14

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2017/03/14

2017/03/14

2017/03/14

Title

Title

Title

HDMI_CONN

HDMI_CONN

HDMI_CONN

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Thursday, October 25, 2018

Thursday, October 25, 2018

Thursday, October 25, 2018

Date: Sheet of

Date: Sheet of

Date: Sheet of

S145AST

S145AST

S145AST

1

24 5 0

24 5 0

24 5 0

0.2

0.2

0.2

A

www.teknisi-indonesia.com

LEFT SIDE USB3.0 PORT x2

+5VALW +USB_VCCA

1

C128
1U_0402_10V6K

2

1 1

+5VALW +USB_VCCD

1

C8808
1U_0402_10V6K

2

2 2

USB20_P3

USB20_N3

U2

5

OUT

IN

GND

4

USB_ON#25,35

OCB

ENB

SY6288D20AAC_SOT23-5

Low Active 2A

L13

EMC@

USB30_RX_N0 USB30_RX_R_N0

USB30_RX_P0 USB30_RX_R_P0

USB30_TX_C_N0 USB30_TX_R_N0

USB30_TX_C_P0 USB30_TX_R_P0

USB20_P4

USB20_N4

Follow S145WHL

USB_ON# USB_OC3 #

00

00

00

00

00

00

00

00

00

00

5

4

Low Active 2A

L17

4

0

112

EXC24CH900U_4P

112

4

EXC24CH900U_4P

L16

112

4

EXC24CH900U_4P

L8

4

112

EXC24CH900U_4P

U132

OUT

IN

GND

OCB

ENB

SY6288D20AAC_SOT23-5

EMC@

2

334

EMC@

2

334

EMC@

334

2

1

2

3

334

2

USB20_P3_R

USB20_N3_R

1

2

3

USB20_P4_R

USB20_N4_R

EMC

1

2

1

2

C8809
1000P_0201_50V7-K

EMC_NS@

USB_OC1#

C2078
1000P_0201_50V7-K

EMC_NS@

B

USB_OC1# 7

USB_OC3# 7

C

1 2

C126 0.1U_6.3V_K_X5R_0201

USB30_TX_N0 USB30_TX_C_N0 USB30_TX_R_N0

1 2

C124 0.1U_6.3V_K_X5R_0201

USB20_P48

USB20_N48

USB30_RX_P0 USB30_RX_R_P0

USB20_P4_R

USB20_N4_R

D11

1

2

312

D13
AZC199-02S.R7G_SOT23-3

EMC@

EMC

USB20_N38
USB20_P 38

312

Close to ConnectorFOR ESD

D43
AZC199-02S.R7G_SOT23-3

EMC@

USB20_P3_R

USB20_N3_R

+USB_VCCA

USB30_TX_P 08

USB30_TX_N08

USB30_RX_P08

USB30_RX_N08

1

EMC_NS@

2

AZ5725-01F.R7GR_DFN1006P2X2

+USB_VCCD

AZ5725-01F.R7GR_DFN1006P2X2

D

+USB_VCCA

1 2

C8811 100U_1206_6.3V6M

1 2

C8806 47U_6.3V_M_X5R_0805_H1.25

@

1 2

C1117 47U_6.3V_M_X5R_0805_H1.25

@

1 2

C125

1U_0402_10V6K@

1 2

C127

1U_0402_10V6K@

USB30_TX_C_P0 USB30_TX_R_P0USB30_TX_P0

1 2

R95 0_0402_5%@

1 2

R96 0_0402_5%@

1 2

R97 0_0402_5%@

1 2

R93 0_0402_5%@

1 2

R94 0_0402_5%@

1 2

R98 0_0402_5%@

USB30_RX_R_N0

USB30_RX_R_P0

USB30_TX_R_ P0

1 2

R942 0_0402_5%@

1 2

R3103 0_0402_5%@

USB20_P4_RUSB20_P4

USB20_N4_RUSB20_N4

USB30_RX_R_N0USB30_RX_N0

D12

9



8

7



 

AZ1045-04F_DFN2510P10E-10-9

USB20_N3_RUSB20_N3
USB20_P3_RUSB20_P 3

JUSB1

9

StdA_SSTX+

1

VBUS

8

StdA_SSTX-

3

D+

7

GND_DRAIN

2

D-

6

StdA_SSRX+

4

GND_1

5

StdA_SSRX-

ALLTO_C19043-10905-L

ͳͲȀͳ͸

EMC@

USB30_RX_R_N0

USB30_RX_R_P0

2



USB30_TX_R_N0USB30_TX_R_N0

4



USB30_TX_R_P0

516

3



8

+USB_VCCD

C8810 100U_1206_6.3V6M

C8807 47U_6.3V_M_X5R_0805_H1.25

@

C8804 47U_6.3V_M_X5R_0805_H1.25

@

C2060

C2059

ͳͲͳ͹

1

D34

1

EMC_NS@

2

2

1 2

1 2

1 2

1 2

1U_0402_10V6K@

1 2

1U_0402_10V6K@

JUSB3

1

VBUS

2

D-

3

D+
GND4GND1

ME@

ME@

10

GND_2

11

GND_3

12

GND_4

13

GND_5

GND2
GND3
GND4

ALLTO_C107G1-10803-L

E

5
6
7
8

1 2

1 2
1 2

1 2
1 2

1 2

Deciphered Date

Deciphered Date

Deciphered Date

D

USB30_TX_R_N1USB30_TX_C_N1USB30_ TX_N1
USB20_P5_RUSB 20_P 5_S
UARTA_P80_EN
USB20_N5_RUSB20_N5_S
USB30_RX_R _P1USB30_RX_P1

USB30_RX_R_N1

2017/03/14

2017/03/14

2017/03/14

+USB_VCCB

C4103 100U_1206_6.3V6M

C8802 47U_6.3V_M_X5R_0805_H1.25

C8803 47U_6.3V_M_X5R_0805_H1.25

C8800 1U_0402_10V6K

C8801 1U_0402_10V6K

1 2

1 2

@

1 2

@

1 2

@

1 2

@

9
1
8
3
7
2
6
4
5

ͳͲȀͳ͸

USB30_RX_R_N1

USB30_RX_R_P1

USB30_TX_R_N1 USB30_TX_R_N1

USB30_TX_R_P1

JUSB2

ME@

StdA_SSTX+
VBUS
StdA_SSTX­D+
GND_DRAIN

10

D-

GND_2

11

StdA_SSRX+

GND_3

12

GND_1

GND_4

13

StdA_SSRX-

GND_5

ALLTO_C19043-10905-L

D1

EMC@

USB30_RX_R_N1

9



USB30_RX_R_P1

2

8



4

7





USB30_TX_R_P1

516

 

3



8

AZ1045-04F_DFN2510P10E-10-9

Title

Title

Title

USB3.0 PORT (LEFT)

USB3.0 PORT (LEFT)

USB3.0 PORT (LEFT)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

S145AST

S145AST

S145AST

Thursday, October 25, 2018

Thursday, October 25, 2018

Thursday, October 25, 2018

Date: Sheet of

Date: Sheet of

Date: Sheet of

E

25 50

25 50

25 50

Follow S145WHL, U25 change to SA000074Q00

1

2

C8799
1U_0402_10V6K

USB_ON#25,35

USB_ON#

USB20_P5_S

USB20_N5_S



Set input

Set output Low

ͺͲ

Set input

Set output Low



XH

L

L

H

L

A

USB3.0 PORT

U25

5

IN

4

ENB

SY6288D20AAC_SOT23-5

Low Active 2A







DISABLE

D(+/-) to 1D(+/-)

D(+/-) to 2D(+/-)

L1

112

4

0

EXC24CH900U_4P

L6

112

4

0

EXC24CH900U_4P

L18

4

112

EXC24CH900U_4P

EC_TX31,35

EC_RX31,35

USB20_P58

USB20_N58

Set input

ENABLE

ͺͲ

DISABLE

ENABLE

OUT

GND

OCB

EMC@

EMC@

EMC@

1

2

USB_OC2#

3

USB_OC2# 7

1

C8798
1000P_0201_50V7-K

EMC_NS@

2

USB30_RX_R_N1USB30_RX_N1

2

USB30_RX_R_P1USB30_RX_P1

334

USB30_TX_R_N1USB30_TX_C_N1

2

USB30_TX_R_P1USB30_TX_C_P1

334

USB20_P5_R

334

USB20_N5_R

2



USBDEBUG7

R531 0_0402_5%

U129

EC_TX_C

1

1

2

R533 0_0402_5%Debug@

2

R536 0_0402_5%Debug@

1D+

EC_RX_C USB_UART_SEL

1

2

1D-

3

2D+

4

2D-

5

GND1

11

GND2

NCT3958Y_DFN10_3X3

Debug@

UARTA_P80_EN

B

2

2

Debug@

NCY3958Y

G

+3VALW

Debug@

1

VCC

OE#

12

R547
10K_0402_5%

USB_UART_SEL

13

D

L2N7002KWT1G_SOT323-3
Q56

S

Debug@

USB_UART_SEL

S

D+

D-

ͶͳͲ͵ͳͲͲͳͲͳ͸

USB30_TX_P 1 USB30_TX_R_P1USB30_TX_C_P1

1 2

USB30_TX_P18

USB30_TX_N18

USB30_RX_P18

USB30_RX_N18

USB20_P5_R

USB20_N5_R

1

10

2

R4692 0_0402_5%Debug@

9

USB20_P5_S

8

USB20_N5_S

7

6

C43 0.1U_6.3V_K_X5R_0201

1 2

C48 0.1U_6.3V_K_X5R_0201

USB30_RX_N1

Close to ConnectorFOR ESD

312

D751
AZC199-02S.R7G_SOT23-3

EMC@

+3VALW

USB20_P 5 USB20_P5_S

USB20_N5 USB20_N5_S

Security Classification

Security Classification

Security Classification

Iss u e d D at e

Iss u e d D at e

Iss u e d D at e

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

C

R539 0_0402_5%NODEBUG@

R541 0_0402_5%NODEBUG@

+USB_VCCB

AZ5725-01F.R7GR_DFN1006P2X2

2017/03/14

2017/03/14

2017/03/14

1

1

2

2

12

12

R24 0_0402_5%@

R26 0_0402_5%@
R23 0_0402_5%@

R25 0_0402_5%@
R60 0_0402_5%@

R64 0_0402_5%@

1

R538

R537

100K_0402_5%

0_0402_5%

Debug@

2

1 2

NODEBUG@

D752

EMC_NS@

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

+5VALW +USB_VCCB

3 3

4 4

0.2

0.2

0.2

5

Vinafix.com

4

3

2

1

+1.8VS

ͳ

2

2

D755

@

SCS00008K00

2

1

1

D264

RB751V-40_SOD323-2

PLT_RST#7,15,29,31,35

RTPM17 0_0402_5%TPM@

RTPM18 0_0402_5%@

+1.8VS

12

RTPM34

TPM@

10K_0402_5%

RB751V-40_SOD323-2

RTPM36 0_0402_5%TPM@

SPI_SI8

SPI_SO8

SPI_CLK8

+1.8VALW

D D

PCH_SPI_PIRQ#7

C C

B B

+1.8V_TPM

12

12

1

SPI_SI

SCS00008K00

@

1 2

+1.8V_TPM

RTPM35

@

10K_0402_5%

RTPM20 0_0402_5%TPM@
RTPM21 0_0402_5%TPM@

RTPM22 0_0402_5%TPM@

+5VALW

12

6

2

G1

1

TPM_SPI_PIRQ#

2
2

2

+1.8V_TPM

12

RTPM23

TPM@

10K_0402_5%

RTPM37
10K_0402_5%

TPM@

5

QTPM1A

D1

PJT7838_SOT363-6

TPM@

S1

1
1

1

3

G2

4

2

CTPM1

@

10U_0603_6.3V6M

1

TPM_PLT_RST#

QTPM1B

D2

PJT7838_SOT363-6

TPM@

S2

1

CTPM2

TPM@

4.7U_0402_6.3V6M

2

TPM_SPI_PIRQ#

TPM_SPI_SI
TPM_SPI_SOSPI_SO

SPI_CS_R#

TPM_SPI_CLKSPI_CLK

TPM_PLT_RST#

12

1

2

RTPM30

@

10K_0402_5%

CTPM3

0.1U_0201_6.3V6-K

TPM@

UTPM2

TPM@

18

SPI_PIRQ

21

MO S I

24

MI S O

20

SPI_CS

19

SPI_CLK

17

SPI_RST

6

GPIO

7

PP

+1.8V_TPM

1

CTPM4

0.1U_0201_6.3V6-K

TPM@

2

22

8

VPS

GND12NiC39NiC423NiC5

RTPM28 0_0402_5%

TPM_PIN2

12

TPM@

+3VALW

1 2

NiC11NiC2

32

+1.8V_TPM

RTPM14

TPM@

0_0603_5%

1

CTPM5

TPM@

0.1U_0402_10V7K

2

Ni C6
Ni C7
Ni C8

Ni C9
Ni C1 0
Ni C1 1
Ni C1 2
Ni C1 3
Ni C1 4
Ni C1 5
Ni C1 6
Ni C1 7
Ni C1 8
Ni C1 9
Ni C2 0

Ni C2 1
Ni C2 2

GND2

33

ST33HTPH2E32AHB4_VQFN32_5X5

RTPM38

@

0_0603_5%

1 2

RTPM38 staff for NationZ

2

CTPM6

TPM@

10U_0603_6.3V6M

1

TPM_GP2

3
4
5
10
11
12
13
14
15
16
25
26
27
28
31

29
30

TPM_PIN4

TPM_PIN27

TPM_PIN29

RTPM27 10K_0402_5%TPM@
RTPM24 0_0402_5%@

+1.8V_TPM

RTPM25 10K_0402_5%@

2
2

1 2

1
1

+1.8V_TPM
+1.8V_TPM

PIN29 reserve for TPM MS low power mode

+1.8V_TPM

12

RTPM32

@

TPM_PIN29 PLT_RST#

10K_0402_5%

2

RTPM29 0_0402_5%@

D754

RB751V-40_SOD323-2

@

SCS00008K00

1

12

A A

SPI_CS#_TPM8

5

+3VS_APU

RTPM33
10K_0402_5%

1 2

TPM@

1 2

D750 CUS357

2

RTPM19 0_0402_5%@

TPM@

1

+1.8V_TPM

12

RTPM26

TPM@

10K_0402_5%

SPI_CS_R#

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2017/03/14

2017/03/14

2017/03/14

3

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2017/03/14

2017/03/14

2017/03/14

2

Title

Title

Title

TPM

TPM

TPM

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

B

B

B

Date: Sheet of

Date: Sheet of

Date: Sheet of

Thursday, October 25, 2018

Thursday, October 25, 2018

Thursday, October 25, 2018

S145AST

S145AST

S145AST

1

26 50

26 50

26 50

0.2

0.2

0.2

5

Vinafix.com

4

3

2

1

D D

C C

B B

+3VALW +3VALW

1

CS33

0.1U_0201_6.3V6-K

2

CS36

1 2

0.1U_0201_6.3V6-K

+3VALW+3VS

1

CS34

0.1U_0201_6.3V6-K

2

+APU_CORE

1

2

CS30

0.1U_0201_6.3V6-K

A A

5

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEE RING DRAWING IS THE PROPRIETARY P ROPERTY OF LC FUTURE CENTER. AND CONT AINS CONFIDENTIAL

THIS SHEET OF ENGINEE RING DRAWING IS THE PROPRIETARY P ROPERTY OF LC FUTURE CENTER. AND CONT AINS CONFIDENTIAL

THIS SHEET OF ENGINEE RING DRAWING IS THE PROPRIETARY P ROPERTY OF LC FUTURE CENTER. AND CONT AINS CONFIDENTIAL
AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R& D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R& D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R& D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2017/03/14

2017/03/14

2017/03/14

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2017/03/14

2017/03/14

2017/03/14

Title

DP to CRT Convert(IT6515FN)

DP to CRT Convert(IT6515FN)

DP to CRT Convert(IT6515FN)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Thursday, October 25, 2018

Thursday, October 25, 2018

Thursday, October 25, 2018

Date: Sheet of

Date: Sheet of

Date: Sheet of

S145AST

S145AST

S145AST

1

27 5 0

27 5 0

27 5 0

0.2

0.2

0.2

5

Vinafix.com

D D

C C

4

3

2

1

B B

A A

5

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEI THER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEI THER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEI THER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2017/03/14

2017/03/14

2017/03/14

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Decipher ed Date

Decipher ed Date

Decipher ed Date

2

2017/03/14

2017/03/14

2017/03/14

Title

LAN_RTL8111GUL

LAN_RTL8111GUL

LAN_RTL8111GUL

Size Doc ument Number Rev

Size Doc ument Number Rev

Size Doc ument Number Rev

Cus to m

Cus to m

Cus to m

Dat e: Sheet of

Dat e: Sheet of

Dat e: Sheet of

S145AST

S145AST

S145AST

Thursday, October 25, 2018

Thursday, October 25, 2018

Thursday, October 25, 2018

28 50

28 50

28 50

1

0.2

0.2

0.2

5

Vinafix.com

4

3

2

1

EĞĞĚƐŚŽƌƚ

@

J8

2

112

JUMP_43X79

D D

C C

CD@

10U_0402_6.3V6-M

C2093

1

2

+3VS_SSD1+3VS

Min 3A

4.7U_0402_6.3V6M

C2037

1

1

C2094

2

2

CD@

10U 6.3V M X5R 0402

C7 10U_0603_6.3V6M

0.1U_6.3V_K_X5R_0201

1

1

C2095

@

2

2

JSSD1

1

GND_1

3

GND_2

5

PERN3

7

PERP3

9

GND_3

11

PETN3

13

PETP3

15

GND_4

17

PERN2

19

PERP2

21

GND_5

23

PETN2

25

PETP2

27

GND_6

PCIE_CRX_DTX_N14

PCIE_CRX_DTX_P14

PCIE_CTX_C_DRX_N14
PCIE_CTX_C_DRX_P14

PCIE_CRX_DTX_N04
PCIE_CRX_DTX_P04

PCIE_CTX_C_DRX_N04
PCIE_CTX_C_DRX_P04

CLK_PCIE_SSD#8
CLK_PCIE_SSD8

PCIE_CTX_C_DRX_N1
PCIE_CTX_C_DRX_P1

PCIE_CRX_DTX_N0
PCIE_CRX_DTX_P0

PCIE_CTX_C_DRX_N0
PCIE_CTX_C_DRX_P0

SSD_DET1

29

PERN1

31

PERP1

33

GND_7

35

PETN1

37

PETP1

39

GND_8

41

PERN0/SATA-B+

43

PERP0/SATA-B-

45

GND_9

47

PETN0/SATA-A-

49

PETP0/SATA-A+

51

GND_10

53

REFCLKN

55

REFCLKP

57

GND_11

59

NC

61

NC

63

NC

65

NC

67

N/C_1

69

PEDET

71

GND_12

73

GND_13

75

GND_14

77

PEG1

ARGOS_NASM0-S6701-TS40

ME@

Change Symbol to SP011511122 Bourne 0705

3.3V_1

3.3V_2
N/C_2
N/C_3

DAS/DSS#

3.3V_3

3.3V_4

3.3V_5

3.3V_6
N/C_4
N/C_5
N/C_6
N/C_7
N/C_8
N/C_9

N/C_10
N/C_11
N/C_12

DEVSLP

N/C_13
N/C_14
N/C_15
N/C_16
N/C_17

PERST#

CLKREQ#

PEWAKE#

N/C_18
N/C_19

SUSCLK

3.3V_7

3.3V_8

3.3V_9

PEG2

NC
NC
NCNC64

60
62

66

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58

68
70
72
74

76

+3VS_SSD1

SSD_1_CLKREQ_Q#

SUSCLK_SSD1

12

R72
10K_0402_5%

@

1 2

R4679 0_0402_5%

1

TP265@

@

1 2

R1 0_0402_5%

+3VS_SSD1

SSD_RST#

SSD_1_CLKREQ# 7

SUSCLK 7,11,31

B B

A A

5

+3VS_SSD1

+3VS_SSD1

12

R7

10K_0402_5%

SSD_SATA_PCIE_DET1#7

10K_0402_5%

@

12

@

R40

1 2

R41 0_0402_5%

@

^^ͺdη
ϬͲͲ^d
ϭͲͲW/

4

SSD_DET1

PLT_RST#7,15,26,31,35

APU_SSD_RST#7

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

PLT_RST#

APU_SSD_RST#

2017/03/14

2017/03/14

2017/03/14

R6

100K_0402_5%

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

@

1 2

R5 0_0402_5%

DV4

2

3

LBAT54AWT1G_SO T323-3

12

@

Deciphered D ate

Deciphered D ate

Deciphered D ate

2

RC33
10K_0402_5%

1 2

1

2017/03/14

2017/03/14

2017/03/14

SSD_RST#

Title

Title

Title

LAN_Transforme r

LAN_Transforme r

LAN_Transforme r

Size Document Numb er Rev

Size Document Numb er Rev

Size Document Numb er Rev

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

S145AST

S145AST

S145AST

Thursday, October 25, 2018

Thursday, October 25, 2018

Thursday, October 25, 2018

29 50

29 50

1

29 50

0.2

0.2

0.2

5

Vinafix.com

Fintek thermal sensor

+3VS

D D

1

C47

.1U_0402_10V6-K

2

@

+5VLP

EC_ON_R45

C254

0.1U_0603_25V7-M

@

1 2

over temperature threshold:
RSET=3*RTMH
92+/-30C
Hysteresis temperature threshold.
RHYST=(RSET*RTML)/(3*RTML-RSET)
56+/-30C

C C

B B

placed near DIMM

U1

1

REMOTE1+

REMOTE1-

REMOTE2+

REMOTE2-

2

3

4

5

F75303M_MSOP10

@

HW thermal sensor

U18

1

VCC

TMSNS1

2

GND

RHYST1

3

OT1

TMSNS2

4

RHYST2

OT2

G718TM1U_SOT23-8

@

EC_SMB_CK3

ALERT#

THERM#

TMSNS1

PHYST1

TMSNS2

PHYST2

SCL

SDA

GND

10

9

8

7

6

1 2

R175 10K_0402_5%@

1 2

R177 10K_0402_5%@

EC_SMB_DA3

THEM_ALERT#

THE RM _L

VCC

DP1

DN1

DP2

DN2

8

7

6

5

+3VS

R881

4.7K_0402_5%

@

1 2

21.5K_0402_1%

4

+3VS

R882

4.7K_0402_5%

@

1 2

EC_SMB_CK3 6,16,35

EC_SMB_DA3 6,16,35

+5VLP+5VLP +3VALW

R106

@

R107

21.5K_0402_1%

@

1 2

1 2

1 2

R108 0_0402_5%@

1 2

R176 0_0402_5%@

NTC_V1

NTC_V2

NTC_V1 35

NTC_V2 35

3

REMOTE+/-_R, REMOTE1+/-, REMOTE2+/-:
Trace width/space:10/10 mil
Trace length:<8"

REMOTE1+

C45

3300P_0402_50V7-K

REMOTE1-

@

1

2

B

2

Near GPU&VRAM

C

Q15
MMBT39 04WH _SOT32 3-3

E

3 1

@

2

REMOTE2+

C46

3300P_0402_50V7-K

REMOTE2-

@

1

2

B

2

Near CPU core

C

Q16

MMBT3904WH_SOT323-3

E

3 1

@

Near GPU&VRAM

12

R101

13.7K_0402_1%PX@

12

RT2

PX@

100K_0402_1%_TSM0B104F4251RZ

1 2

R4689
0_0402_5%

@

R102

PX@

0_0402_5%

1 2

EC_AGND EC_AGND

for layout optimized, change the EC_AGND to GND

1

Near CPU

+3VALW

12

R103

13.7K_0402_1%

NTC_V2NTC_V1

12

RT3
100K_0402_1%_TSM0B104F4251RZ

1 2

R4691
0_0402_5%

1 2

R4690
0_0402_5%

@

Near MB edge

+3VALW

12

R109

13.7K_0402_1%

NTC_V335

NTC_V3

12

RT4
100K_0402_1%_TSM0B104F4251RZ

C49

10U_0805_10V6K

+5VS

1 2

R52 0_0603_5%

1

2

C50

0.1u_0201_10V6K

EC_FAN_PWM35
EC_FAN_SPEED35

+5VS_FAN

1

2

@

JFAN1

1

1

2

2

3

3

4

4

5

GND1

6

GND2

HIGHS_WS33040-S0351-HF

ME@

A A

5

1 2

EC_AGND

R104
0_0402_5%

R105
0_0402_5%

@

1 2

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2017/03/14

2017/03/14

2017/03/14

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered D ate

Deciphered D ate

Deciphered D ate

2

2017/03/14

2017/03/14

2017/03/14

Title

Thermal sensor/FAN CONN/TPM

Thermal sensor/FAN CONN/TPM

Thermal sensor/FAN CONN/TPM

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Thursday, October 25, 2018

Thursday, October 25, 2018

Thursday, October 25, 2018

Date: Sheet of

Date: Sheet of

Date: Sheet of

S145AST

S145AST

S145AST

1

30 50

30 50

30 50

0.2

0.2

0.2

A

Vinafix.com

B

Mini-Express Card(WLAN/WiMAX)

C

+3VS_WLAN

D

E

JWLAN1

1 1

2 2

3 3

PCIE_WAKE#7,35

LAN_WAKE#35

WLAN_CLKREQ#7

USB20_P18
USB20_N18

PCIE_PTX_C_DRX_P14
PCIE_PTX_C_DRX_N14

PCIE_PRX_DTX_P14
PCIE_PRX_DTX_N14

CLK_PCIE_WLAN8
CLK_PCIE_WLAN#8

WLAN_CLKREQ_Q #

1 2

R4686 0_0402_5%@

1 2

R57 0_0402_5%@

R61 0_0402_5%

12

WLAN_CLKREQ_Q #

1

GND1

3

USB_D+

5

USB_D-

7

GND2

9

SDIO_ CLK

11

SDIO_ CMD

13

SDIO_DATA0

15

SDIO_DATA1

17

SDIO_DATA2

19

SDIO_DATA3

21

SDIO_WAKE#

23

SDIO_RESET#

25
27
29
31

33

GND3

35

PETP0

37

PETN0

39

GND4

41

PERP0

43

PERN0

45

GND5

47

REFCLKP0

49

REFCLKN0

51

GND6

53

CLKREQ0#

55

PEWAKE0#

57

GND7

59

RSRVD/PETP1

61

RSRVD/PETN1

63

GND8

65

RSRVD/PERP1

67

RERVD/PERN1

69

GND9

71

RSRVD/REFCLKP1

73

RSRVD/REFCLKN1

75

GND10

77

GND15

ARGOS_NASE0-S6701- TS40

PCM_OUT/I2S_SD_OUT

KEY E
PIN24~PIN31 NC PIN

UIM_POWER_SNK/CLKREQ1#

UIM_POWER_SRC /GPIO1/PEWAKE1#

ME@

3.3VAUX1

3.3VAUX2
LED1#

PCM_CLK/I2S_SCK

PCM_S YNC/I2 S_WS

PCM_IN/I2S_SD_IN

LED#2

GND11

UART_WAKE#

UART_RXD

UART_TXD
UART_CTS

UART_RTS
VENDOR_DEFINED1
VENDOR_DEFINED2
VENDOR_DEFINED3

COEX3
COEX2
COEX1

SUSCL K

PERST0 #
W_DISABLE2#
W_DISABLE1#

I2C_DATA

I2C_CLK

ALERT#

RSRVD

UIM_SWP/PERST1#

3.3VAUX3

3.3VAUX4

GND14

2
4
6
8
10
12
14
16
18
20
22

24
26
28
30

32
34
36
38
40
42
44
46
48
50
52
54
56

58
60
62
64
66
68
70
72
74

76

1

T2 @

1

T3 @

EC_TX_RSVD
EC_RX_RSVD

SUSCL K_R

BT_OF F#
WLAN_OFF#

APU_SMB_DATA_R
APU_SMB_CLK_R

EC_TX_ R

+3VS_WLAN

1 2

R62 0_0402_5%@

1 2

R63 0_0402_5%@

R88 0_0402_5%

R55 0_0402_5%

R53 1K_0402_5%
R56 0_0402_5%

R58 0_0402_5%@
R59 0_0402_5%@

R89 0_0402_5%

12

R186
100K_0402_5%

1 2

1 2
1 2

EĞĞĚƐŚŽƌƚ

@

J2

112

JUMP_43X79

12

12

12

12

EC_RX 25,35

SUSCLK 7,11,29
PLT_RST# 7,15,26,29,35
PCH_BT_OFF# 7
PCH_W LAN_O FF# 7

APU_SMB_DATA 7,12
APU_SMB_CLK 7,12

EC_TX 25,35

+3VS_WLAN+3VS

2

1

@

C8797

2

1

1

@

C6

22UC_6.3VC_MC_X5RC_0603

@

C8805

2

10U 6.3V M X5R 0402

1

@

C53

2

2

0.1U_0201_6.3V6-K

10U 6.3V M X5R 0402

Not support AOAC, delete AOAC power circuit 1015

4 4

A

+3VS

U131

@

OUT

GND

OCB

2017/03/14

2017/03/14

2017/03/14

D

1

2

3

5

IN

PWR_WLAN_EN35

Security Classificatio n

Security Classificatio n

Security Classificatio n

Issued Dat e

Issued Dat e

Issued Dat e

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEI THER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEI THER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEI THER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2017/03/14

2017/03/14

2017/03/14

C

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

PWR_WL AN_EN

Deciphered Date

Deciphered Date

Deciphered Date

4

EN

SY6288C20AAC_SOT23-5

+3VS_WLAN

Title

Title

Title

NGFF WLAN

NGFF WLAN

NGFF WLAN

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Thursday, October 25, 2018

Thursday, October 25, 2018

Thursday, October 25, 2018

Date: Sh eet of

Date: Sh eet of

Date: Sh eet of

S145AST

S145AST

S145AST

E

31 50

31 50

31 50

0.2

0.2

0.2

5

Vinafix.com

D D

C C

4

3

2

1

B B

A A

5

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2017/03/14

2017/03/14

2017/03/14

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered D ate

Deciphered D ate

Deciphered D ate

2

2017/03/14

2017/03/14

2017/03/14

Title

NA

NA

NA

Size Document Numb er Rev

Size Document Numb er Rev

Size Document Numb er Rev

Custom

Custom

Custom

Thursday, October 25, 2018

Thursday, October 25, 2018

Thursday, October 25, 2018

Date: Sheet of

Date: Sheet of

Date: Sheet of

S145AST

S145AST

S145AST

1

32 50

32 50

32 50

0.2

0.2

0.2

5

Vinafix.com

D D

C C

4

3

2

1

B B

A A

5

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2017/03/14

2017/03/14

2017/03/14

3

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2017/03/14

2017/03/14

2017/03/14

2

Title

NA

NA

NA

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

B

B

B

Thursday, October 25, 2018

Thursday, October 25, 2018

Date: Sheet of

Date: Sheet of

Date: Sheet of

Thursday, October 25, 2018

S145AST

S145AST

S145AST

1

33 50

33 50

33 50

0.2

0.2

0.2

A

Vinafix.com

B

C

D

E

F

G

H

1 1

2 2

3 3

+5VS_HDD

1

C74
1000P_0201_50V7-K

EMC_NS@

2

EMC

C1107 22P_0402_50V8-J

C75 0.1U_0201_6.3V6-K

C76 1U_0603_25V6M

1

1

2

@

@

2

C78 10U_0805_10V6K

C77 10U_0805_10V6K

1

1

@

2

2

C1108 22P_0402_50V8-J

1

1

RF_NS@

2

RF_NS@

2

SATA_PTX_DRX_P08
SATA_PTX_DRX_N08

SATA_PRX_DTX_N08
SATA_PRX_DTX_P08

SATA_PTX_DRX_P0
SATA_PTX_DRX_N0

SATA_PRX_DTX_P0

1 2

C66 0.01U_6.3V_K_X7R_0201

1 2

C67 0.01U_6.3V_K_X7R_0201

1 2

C68 0.01U_6.3V_K_X7R_0201

1 2

C69 0.01U_6.3V_K_X7R_0201

+5VS +5VS_HDD

EĞĞĚƐŚŽƌƚ

J3

JUMP_43X79

112

SATA_PTX_C_DRX_P0
SATA_PTX_C_DRX_N0

SATA_PRX_C_DTX_N0SATA_PRX_DTX_N0
SATA_PRX_C_DTX_P0

2

@

SATA HDD Conn.

JHDD1

ME@

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

HIGHS_FC5AF101-2931H

GND1

GND2

11

12

4 4

A

Titl e

Titl e

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER N EITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER N EITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER N EITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

D

2017/03/14

2017/03/14

2017/03/14

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

E

F

2017/03/14

2017/03/14

2017/03/14

Titl e

HDD/ODD CONN

HDD/ODD CONN

HDD/ODD CONN

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Thursday, October 25, 2018

Thursday, October 25, 2018

Thursday, October 25, 2018

Date: Sheet of

Date: Sheet of

Date: Sheet of

G

S145AST

S145AST

S145AST

34 50

34 50

34 50

H

0.2

0.2

0.2

5

Vinafix.com

D D

WRST#16

+3VL_EC

C C

B B

DE1

1 2

LRB751V-40T1G_SOD323-2

1 2

RE8 100K_0402_5%

+3VL_EC+3VALW

12

RE274

0_0402_5%

@

14

23

RPE5

2.2K_0404_4P2R_5%

EC_SMB_CK2
EC_SMB_DA2

+3VL_EC

14

23

RPE2

2.2K_0404_4P2R_5%

EC_SMB_CK1
EC_SMB_DA1

+3VS

14

23

RPE3

2.2K_0404_4P2R_5%

EC_SMB_CK3
EC_SMB_DA3

@

1

CE12
1U_0402_6.3V6K

2

KSI[0..7]36

KSO[0..17]36

12

RE273
0_0402_5%

RE59 0_0402_5%@

Add SMBUS for POWER
core IC 10/20

+3VL

Change PCH_CMOSP form PIN117 to pin35

KBRST#8
SERIRQ8

LPC_FRAME#8,11

LPC_AD38
LPC_AD28
LPC_AD18
LPC_AD08

CLK_PCI_EC8,11

EC_RX25,31
EC_TX25,31

APU_LPC_RST#8

EC_SCI#8
GATEA207

KSI[0..7]

KSO[0..17]

ON/OFF36

1 2

EC_SMB_CK143,44
EC_SMB_DA143,44
EC_SMB_CK246
EC_SMB_DA246
EC_SMB_CK36,16,30
EC_SMB_DA36,16,30

RE27 0_0402_5%

LAN_WAKE#31

PCH_CMOSP37

EC_RSMRST#7

Need EC modify GPH0 to OD output

PCIE_WAKE#7,31

AC_PRESENT7

EC_ON_LEC_ON

1 2

USB_ON#25

CLK_PCI_EC
WRST#

EC_RX
EC_TX
APU_LPC_RST#

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

ON/OFF

EC_SMB_CK1
EC_SMB_DA1

EC_SMB_CK3
EC_SMB_DA3

LAN_WAKE#

USB_ON#

AMD request SIC/SID˄EC_SMB2˅pull high 1K

DE2 RB751V-40_SOD323-2

RE86 0_0402_5%

Mirror Core strap

RE44 10K_0402_5%@

RE46 10K_0402_5%STN@

5

12

12

GPG2

A A

ǁŚĞŶŵŝƌƌŽƌ'W'ϮƉƵůůŚŝŐŚ
ǁŚĞŶŶŽŵŝƌƌŽƌ'W'ϮƉƵůůůŽǁ

+3VL_EC

SYSON

DE3 RB751V-40_SOD323-2

RE87 1K_0402_5%@

4

ůŽƐĞ

CE3 0.1U_0201_6.3V6-K

1 2

1 2

RE6 0_0402_5%

UE1

4

KBRST#/GPB6

5

SERIRQ/GPM6

6

LFRAME#/GPM5

7

LAD3/GPM3

8

LAD2/GPM2

9

LAD1/GPM1

10

LAD0/GPM0

13

LPCCLK/GPM4

14

WRST#

15

ECSMI#/GPD4

16

PWUREQ#/BBO/SMCLK2ALT/GPC7

17

LPCPD#/GPE6

22

LPCRST#/GPD2

23

ECSCI#/GPD3

126

GA20/GPB5

58

KSI0/STB#

59

KSI1/AFD#

60

KSI2/IN IT#

61

KSI3/SLIN#

62

KSI4

63

KSI5

64

KSI6

65

KSI7

36

KSO0/PD0

37

KSO1/PD1

38

KSO2/PD2

39

KSO3/PD3

40

KSO4/PD4

41

KSO5/PD5

42

KSO6/PD6

43

KSO7/PD7

44

KSO8/ACK#

45

KSO9/BUSY

46

KSO10/PE

51

KSO11/ERR#

52

KSO12/SLCT

53

KSO13

54

KSO14

55

KSO15

56

KSO16/SMOSI/GPC3

57

KSO17/SMISO/GPC5

110

PWRSW#

111

XLP_OUT

115

SMCLK1/GPC1

116

SMDAT1/GPC2

117

SMCLK2/PECI/GPF6

118

SMDAT2/PECIRQT#/GPF7

94

CRX1/SIN1/SMCLK3/GPH1/ID1

95

CTX1/SOUT1/GPH2/SMDAT3/ID2

112

VSTBY0

125

GPE4

33

GINT/CTS0#/GPD5

35

RTS1#/GPE5

93

CLKRUN#/GPH0/ID0

2

CK32KE/GPJ7

128

CK32K/GPJ6

IT8586E-AX_LQFP128_14X14

@

1 2

1 2

@

1 2

1 2

4

VCOREVCC

Int. K/B
Matr ix

+3VS

50

12

11

3

VCC

VBAT

VCORE

VSTBY126VSTBY5

IT8586E/AX
LQFP-128L

EXTERNAL SERIAL FLASH

SM Bus

WAKE UP

GPIO

Clock

VSS1

1

2_5VEN

1 2

RE1 0_0603_5%

1 2

RE3 0_0603_5%@

+3VL_EC_R

74

92

114

121

127

AVCC

VSTBY2

VSTBY3

VSTBY4

VSTBY(PLL)

PWM

LPC

SPI Flash ROM

VSS2

VSS4

VSS5

VSS349VSS6

27

91

113

122

1_2VEN 46

2_5VEN 46

75

+3VL

+3VALW

ůůĐĂƉĂĐŝƚŽƌƐĐůŽƐĞƚŽ

1

1

CE22

CE21

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

2

2

ŵŝŶŝŵƵŵƚƌĂĐĞǁŝĚƚŚϭϮŵŝů

24

PWM0/GPA0

25

PWM1/GPA1

28

PWM2/GPA2

29

PWM3/GPA3

30

PWM4/GPA4

31

PWM5/GPA5

TMRI0/GPC4
TMRI1/GPC6

ADC0/GPI0
ADC1/GPI1
ADC2/GPI2
ADC3/GPI3
ADC4/GPI4

PS2CLK2/GPF4
PS2DAT2/GPF5

GPH3/ID3
GPH4/ID4
GPH5/ID5
GPH6/ID6

AC_IN#

LID_SW#

EGAD/GPE1
EGCS#/GPE2
EGCLK/GPE3

SSCE0#/GPG2
SSCE1#/GPG0

DSR0#/GPG6

CRX0/GPC0

CTX0/TM A0/G PB2

RI1#/GPD0
RI2#/GPD1

TACH2/GPJ0

TACH0A/GPD6

L80LLAT/GPE7

32
34
120
124

66
67
68
69
70
71
72
73

78
79
80
81

85
86
87

GPF2

88

GPF3

89
90

96
97
98
99

101

NC1

102

NC2

103

NC3

105

NC4

108
109

82
83
84

77

GPJ1

100
106
104
107
119
123
18
21
76
48
47
19
20

PWM6/SSCK/GPA6

PWM7/RIG1#/GPA7

ADC

ADC5/DCD1#/GPI5
ADC6/DSR1#/GPI6
ADC7/CTS1#/GPI7

DAC2/TACH0B/GPJ2
DAC3/TACH1B/GPJ3

DAC

DAC4/DCD0#/GPJ4

DAC5/RIG0#/GPJ5

PS2CLK0/TMB0/CEC/GPF0

PS2DAT0/TMB1/GPF1

PS2

UART

GPIO

DTR1#/SBUSY/GPG1/ID7

TACH1A /TMA 1/GPD 7

L80HLAT/BAO/GPE0

AVSS

EC_AGND

Factory EC flash for STN

EC_SMB_CK1
EC_SMB_DA1

KSI7
KSI6
WRST#

3

+3VL_EC

+3VL_EC

1

1

1

CE24

CE23

0.1U_0201_6.3V6-K

2

2

0.1U_0201_6.3V6-K

EC_FAN_PWM

EC_APU_ALWEN

SUSP#

NTC_V3

MAINPWON1_EC
H_PROCHOT#_EC

1 2

RE57 0_0402_5%

1

TE 2 @

EC_LID_OUT#

1

ACOFF

ACIN#
LID_SW#

1 2

RE71 0_0402_5%

GPG2

EC_GFX_PWRGD

1

TE 1 @

SYSON
BKOFF#

EC_TS_ON
EC_FAN_SPEED

ACIN#

L2N7002KWT1G_SOT323-3

1

PAD @

IT1

1

PAD @

IT2

1

PAD @

IT3

1

PAD @

IT4

1

PAD @

IT5

1

PAD @

IT6

1

PAD @

IT7

ĨŽƌsZͺWhͺWtZ'ƵŶĚĞƌƐŚŽŽƚŝƐƐƵĞ

1

PAD @

IT8

Securi ty Cl assific ation

Securi ty Cl assific ation

Securi ty Cl assific ation

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.

3

1

CE25

CE11

0.1U_0201_6.3V6-K

2

2

0.1U_0201_6.3V6-K

@

PWR_LED# 36
BATT_C HG_LE D# 36
BATT_L OW_ LED# 36
VGA_AC_DET 16

EC_FAN_PWM 30
BEEP# 36

EC_APU_ALWEN 46

SUSP# 37,45,46

NTC_V1 30
NTC_V2 30
BATT_TEMP 43,44

ENBKL 23

ADP_I 44

NTC_V3 30

VR_APU_PWRGD 49

EC_RTCRST#_ON 9

PBTN_OUT# 7

APUALW_PW RGD 46

EC_LID_OUT# 36

CAPS_LED# 36
EC_VR_ON 49

TC 8 8@

EC_SYS_PWRGD 7

LID_SW# 36

EC_MUTE# 36

Nano G not support adapt ID( GPI7) 10/20

PM_SLP_S5# 7

PD reserve Junjun0824

BKOFF# 23

PM_SLP_S3# 7

NOVO# 36

EC_TS_ON 23

EC_FAN_SPEED 30

NUM_LED# 36

+3VL

12

RE56
100K_0402_5%

13

D

S

@

1 2

RE29 0_0402_5%@

1 2

RE276 0_0402_5%@

1 2

RE275 0_0402_5%

Add NTC_V3 for thermistor

1 2

RE26 1K_0402_5%@

EC_ON 45,46

1 2

RE91 0_0402_5%

Need EC modify GPH6 to OD output

GPG0 def mode GPO H
GPG1 def mode GPO L internal Pull down

2_5VEN

12

RE294 0_0402_5%@

PIN 21, NANO is 4 pin FAN, so delete EC_FAN_ANTI

1 2

RE92 0_0402_5%

@

Change GPIO setting, high active

1 2

RE88 0_0402_5%

QE2

2

G

VR_APU_PWRGD

1

CE20
1U_0402_6.3V6K

2

2017/03/14

2017/03/14

2017/03/14

2

1 2

LE1 0_0603_5%

1 2

LE2 0_0603_5%

HVB_EN 7,11

IDCHG 44

PSYS 44

MAINPWON 45

EC_ON set Push Pull

GPU_EC_HOT#

PWR_WLAN_EN

PWR_WLAN_EN 31

PCH_PWRBT# 7

PIN 48 20 ˈCZL and STN have no VDDCR_GFX, so delete VDDFX_PD and EC_GFX_PD

ACIN 44

CLK_PCI_EC

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciph ered Date

Deciph ered Date

Deciph ered Date

2

RE2 10_0402_5%

1

CE4

0.1U_0201_6.3V6-K

2

EC_AGND

VR_HOT#44,49

APUALW_PW RGD

1 2

EMC_NS@

2017/03/14

2017/03/14

2017/03/14

1

CE5
1000P 25V K X7R 0201

2

EC_AGND

1 2

RE90 0_0402_5%

2N7002KW_SOT323-3

H_PROCHOT#

1 2

RE34 0_0402_5%

H_PROCHOT#_EC

L2N7002KWT1G_SOT323-3

Need EC modify GPJ4 to OD output

2

CE29

0.1U_0201_6.3V6-K

1

@

APU_LPC_RST#

SYSON

BATT_TE MP

ACIN#

ON/OFF

PM_SLP_S3#

PM_SLP_S5#

1

+3VL_EC_R

EC_FAN_SPEED
EC_FAN_PWM
ENBKL
EC_LID_OUT#
EC_GFX_PWRGD

USB_ON#

SUSP#
LAN_WAKE#
EC_ON

LID_SW#

EC_APU_ALWEN
2_5VEN
SUSP#
SYSON
BKOFF#
PWR_WLAN_EN
EC_ON

2

G

PLT_RST#7,15,26,29,31

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

RE10 10K_0402_5%
RE11 10K_0402_5%@
RE9 100K_0402_5%@
RE93 10K_0402_5%@
RE279 10K_0402_5%@

RE15 10K_0402_5%

RE18 100K_0402_5%@
RE5 10K_0402_5%
RE58 100K_0402_5%@

RE38 100K_0402_5%

1 2

RE278 100K_0402_5%

1 2

RE277 100K_0402_5%@

1 2

RE19 100K_0402_5%

1 2

RE21 100K_0402_5%

1 2

RE40 10K_0402_5%

1 2

RE293 10K_0402_5%@

1 2

RE285 100K_0402_5%

13

D

QE6

S

@

13

D

QE1

2

G

S

@

1 2

RE89 0_0402_5%

1 2

CE2 10P_0402_50V8JE MC_NS@

1 2

CE1 220P_0402_50V7KEMC_NS@

1 2

CE13 0.1U_0201_6.3V6-KEMC_NS@

1 2

CE16 100P_0402_50V8JEMC_NS@

1 2

CE17 100P_0402_50V8JEMC_NS@

1 2

CE18 1U_0402_6.3V6KEMC_NS@

1 2

CE27 0.1U_0201_6.3V6-KEMC_NS@

1 2

CE28 0.1U_0201_6.3V6-KEMC_NS@

EC ITE8586LQFP

EC ITE8586LQFP

EC ITE8586LQFP

Thursday, October 25, 2018

Thursday, October 25, 2018

Thursday, October 25, 2018

1 2
1 2
1 2
1 2
1 2

1 2

1 2
1 2
1 2

1 2

1

CE26
47P_0201_25V8-J

@

2

1

2

1 2

CC1278

1000P_0402_25V7-K

CE14
47P_0402_50V8J

@

EMC_NS@

S145AST

S145AST

S145AST

+3VS

+5VALW

+3VL_EC

GPU_VR_HOT# 16,48

NOVO#

+3VS

1

+3VL

H_PROCHOT# 6,46

1

CC1277

0.01U_0201_25V6-K

EMC_NS@

2

1

CE19

0.1U_0201_6.3V6-K

2

EMC_NS@

35 50

35 50

35 50

EMC

0.2

0.2

0.2

5

Vinafix.com

ON/OFF switch

NOVO#35

D D

ON/OFFBTN#

J5

1 2

SHORT PADS

1 2

J6

SHORT PADS

NOVO#

ON/OFF

@

@

+3VL +3VALW

R82
100K_0402_5%

1 2

@

R85 0_0402_5%@

1 2

1 2

R119 0_0402_5%

R83
100K_0402_5%

1 2

+3VALW

R111
100K_0402_5%

@

1 2

ON/OFF

1 2

R268 0_0402_5%

D15

2

NOVO_BTN#

1

3

LBAT54CWT1G_SOT323-3

@

+3VL

R114
100K_0402_5%

1 2

ON/OFF 35

4

K/B Connector

KSI[0..7]

KSO[0..17 ]

PWR_CAPS_LED

C133 100P_0201_25V8J

CAPS_LED#

C117 100P_0201_25V8J

NUM_LED#_R

C118 100P_0201_25V8J

KSI[0..7] 35

KSO[0..17] 35

EMC_NS@

1 2

EMC_NS@

1 2

1 2

EMC_15_NS@

3

PWR_LED#

1

D46

1

AZ5123-01F.R7GR_DFN1006P2X2

EMC_NS@

2

2

CAPS_LED# NUM_LED#_R

1

D23

1

AZ5123-01F.R7GR_DFN1006P2X2

EMC_NS@

2

2

1

D22

1

AZ5123-01F.R7GR_DFN1006P2X2

EMC_15_NS@

2

2

For EMC

2

ON/OFFBTN#

1

D30

1

AZ5123-01F.R7GR_DFN1006P2X2

EMC@

2

2

PWR_LED#

R285 200_0402_1%

NUM_LED#35

CAPS_LED#35

+3VALW

R279 200_0402_1%15@
R281 0_0402_5%15@

KSO17

R280 0_0402_5%15@

KSO16

CAPS_LED# CAPS_LED#_R

R275 200_0402_1%

R84 0_0402_5%

1 2
1 2
1 2
1 2

1 2

1 2

ON/OFFBTN#

NUM_LED#_R
KSO17_R
KSO16_R
KSI1
KSI7
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15

PWR_CAPS_LED

1

JKB1

ME@

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

27

28

28

29

29

30

30

31

31

GND2

3232GND1

HIGHS_FC8AR321-3160-1H

34
33

EMC

LID Connector

R267 0_0402_5%

1 2

+3VL

+VCC_LID

1

@

2

U23

1

GND

OUTPUT

C1104

0.01U_0201_6.3V7-K

2

VCC

AH9247-W-7_SC59-3

3

1

C1105

0.01U_0201_6.3V7-K

@

2

LID_SW#

1

D17

1

AZ5123-01F.R7GR_DFN1006P2X2

EMC_NS@

2

2

For EMC

3

LID_SW# 35

IO Connector

BEEP#35

PCH_BEEP7

DA1

2

1

3

LBAT54CWT1G_SOT323-3

@

1 2

RA3026 0_0402_5%

1 2

RA3025 1K_0402_5%

PC_BEEP1 PC_BEEP

1 2

RA211 1K_0402_5%

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2

CA41

CA40

12

RA14
10K_0402_5%

@

2017/03/14

2017/03/14

2017/03/14

1 2

1 2

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

EC_MUTE#35

USB20_ N08
USB20_ P08

DMIC_CLK23

DMIC_DATA23

HDA_BITCLK_AUDIO7
HDA_SDOUT_AUDIO7

HDA_SD IN07

HDA_SYNC_ AUDIO7

+5VS

+3VS
+3VL

+3VALW

+1.8VS

2017/03/14

2017/03/14

2017/03/14

J1

1

1

2

PC_BEEP

NOVO_B TN#
EC_MUTE#

USB20_N0
USB20_P 0

DMIC_CLK
DMIC_DATA

HDA_BITCLK_AUDIO
HDA_SDO UT_AUDI O
HDA_SDI N0
HDA_SYNC_ AUDIO

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

GND1

22

GND2

HIGHS_FC5AF201-1151H

ME@

Title

Title

Title

KBD/PWR/IO/LED/TP Conn.

KBD/PWR/IO/LED/TP Conn.

KBD/PWR/IO/LED/TP Conn.

Size Docume nt Number Rev

Size Docume nt Number Rev

Size Docume nt Number Rev

Custom

Custom

Custom

Thursday, October 25, 2018

Thursday, October 25, 2018

Thursday, October 25, 2018

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

S145AST

S145AST

S145AST

36 50

36 50

36 50

C C

R141 0_0402_5%

TP_I2C0_SDA_R7

TP_I2C0_SCL_R7

B B

1 2

TP_I2C0_SDA_R

TP_I2C0_SCL_R

TP_PWR+3VS

1

2

C114

0.1U_6.3V_K_X5R_0201

1 2

R4687 0_0402_5%

1 2

R4688 0_0402_5%

Reserve level shift as I2C at APU side is 1.8V Level 10/28

LED

BATT_LOW_LED#35

A A

BATT_CHG_LED#35

PWR_LED#

PWR_LED#35

BATT_LOW_LED#

BATT_CHG_LED#

1

1

2

2

1

1

2

2

1

1

2

2

TP/B Connector

TP_I2C0_SDA_R

TP_I2C0_SCL_R

1

Q158A
PJT7838_SOT363-6

1 2

LED1

L-C192WDT-LCFC_WHITE
D31
AZ5725-01F.R7GR_DFN1006P2X2

EMC_NS@

1 2

LED2

L-C192JFCT-LCFC_SUPER_AMBER
D32
AZ5725-01F.R7GR_DFN1006P2X2

EMC_NS@

LED3

1 2

L-C192WDT-LCFC_WHITE

D33
AZ5725-01F.R7GR_DFN1006P2X2

EMC_NS@

5

Change from PS2 mode to I2C mode 10/19

EC_LID_OUT#35

PCH_TP_INT#7

1 2

RC1657 0_0402_5%@
RC1656 0_0402_5%@

1 2

+1.8VS

5

G2

4

D23S2

2

Q158B
PJT7838_SOT363-6

G1

D16S1

1 2

R142 1.5K_0402_5%

1 2

R143 470_0402_5%

R144 1.5K_0402_5%

1 2

1 2

R4677 0_0402_5%

1 2

R4678 0_0402_5%

1

2

EMC_NS@

C115

100P_0201_25V8J

+5VALW

+3VALW

+5VALW

EC_LID_OUT#_R
TP_INT#

TP_I2C0_SDA
TP_I2C0_SCL

TP_PWR

1

2

EMC_NS@

C116

100P_0201_25V8J

TP_PWR

14

23

RPC20

2.2K_0404_4P2R_5%

TP_I2C0_SDA

TP_I2C0_SCL

JTP1

1

1

2

2

3

3

4

4

5

5

6

6

7

GND1

8

GND2

HIGHS_FC5AF061-2931H

ME@

TP_I2C0_SCL
TP_I2C0_SDA

4

312

DT1

EMC_NS@

AZC199-02S.R7G_SOT23-3

0.2

0.2

0.2

A

Vinafix.com

+5VALW+5VLP

12

12

1 1

SUSP12,24

SUSP#35,45,46

SUSP

L2N7002KWT1G_SOT323-3

R15 6
100K_0402_5%

Q6

2

G

R15 7
100K_0402_5%

@

13

D

S

B

C

D

E

+1.8VALW to +1.8VS

Q39

+1.8VALW

2 2

+/- 2%

C14 1

10U_0603_6.3V6M

1

2

@

AONS32314_DFN8-5

5

1
2
3

4

Q39 change to SB00001NY00

1.8VS_GATE_R 1.8VS_GATE

1

C14 3

0.01U_0201_25V6-K

2

3 3

+3VALW to +3VALW_APU

R158 0_0402_5%@

4 4

PCH_CMOSP35

A

1 2

12

R16 4

100K_0402_5%

@

reserve to cut off APU 3VALW when clear CMOS

+/- 5% 1.5A

+1.8VS

1

C14 0
10U_0603_6.3V6M

2

R21 1

1 2

0_0402_5%

R21 2

1M_0402_5%

+3VALW +3VALW_APU

1 2

12

@

1

C12 9

0.1U_0201_6.3V6-K

2

@

R19 4

0_0402_5%

Need Short

JUMP_43X79

LP2301ALT1G_SOT23-3

Q29

1

C14 2
1U_0402_6.3V6K

2

J7

112

S

G

2

1

2

B

13

D

S

L2N7002KWT1G_SOT323-3

@

2

Id=3.2A

D

13

C13 1

0.1U_0201_6.3V6-K

@

AONS32314
VDS=30V VGS=20V, ID=32A,
Rds=8.7mohm @ VGS=10V
VGS(th)=2.25V Max

R21 4

12

130K_0402_5%

Q45

2

SUSP

G

1

C13 0

0.01U_0201_6.3V7-K

2

@

V20B+

2

G

12

R21 3
470_0603_5%

13

D

Q46

S

L2N7002KWT1G_SOT323-3

@

+0.95VALW to +0.95VS

Q41

+0.9 5VALW

+/- 1.5%

1

C14 6

@

10U_0603_6.3V6M

@

2

AONS32314_DFN8-5

5

4

Q41 change to SB00001NY00

320AST 0.6VS discharge Stuff
140S AST unstaff

+0.6VS

12

R15 9
47_0603_5%

@

13

D

Q8

2

SUSP

G

S

L2N7002KWT1G_SOT323-3

REV @

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEI THER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEI THER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEI THER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

C

2017/03/14

2017/03/14

2017/03/14

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Decipher ed Date

Decipher ed Date

Decipher ed Date

+0.9 5VS

1
2
3

0.95VS_GATE_R

1

C14 4

0.01U_0201_25V6-K

2

R19 3

1 2

0_0402_5%

820K_0402_5%

1

2

R18 7

&ŽƌŝƐŚĂƌŐĞ

12

13

D

D

S

2017/03/14

2017/03/14

2017/03/14

2N7002KW_SOT323-3 R EV @

C14 5
10U_0603_6.3V6M

1 2

0_0402_5%

1 2

12

@

R93 5
47_0603_5%

@

Q156

2

SUSP SUSP

G

AONS32314
VDS=30V VGS=20V, ID=32A,
Rds=8.7mohm @ VGS=10V
VGS(th)=2.25V Max

1

C14 7
1U_0402_6.3V6K

2

R20 6

1.8VS_GATE

0.9 5VS_ GAT E

R19 0
0_0402_5%

@

13

D

S

L2N7002KWT1G_SOT323-3

@

2N7002KW_SOT323-3 R EV @

Title

Title

Title

DC V TO VS INTERFACE

DC V TO VS INTERFACE

DC V TO VS INTERFACE

Size Do cu m ent Nu mb er Rev

Size Do cu m ent Nu mb er Rev

Size Do cu m ent Nu mb er Rev

Cus to m

Cus to m

Cus to m

Dat e: Sheet of

Dat e: Sheet of

Dat e: Sheet of

12

R18 9

470K_0402_5%

@

Q37

2

SUSP

G

+1.8 VS+ 2.5V

12

R93 9
47_0603_5%

@

13

D

Q157

S

Thursday, October 25, 2018

Thursday, October 25, 2018

Thursday, October 25, 2018

V20B+

Q40

2

G

L2N7002KWT1G_SOT323-3

2

G

S145AST

S145AST

S145AST

E

12

13

D

S

@

R188

@

470_0603_5%

37 5 0

37 5 0

37 5 0

0.2

0.2

0.2

5

Vinafix.com

4

3

2

1

Hole

D D

H2
HOLEA

1

PAD_C10P0D8P0

PCB Fedical Mark PAD

FD4901

FD4902

1

1

FD4903

FD4904

1

1

FD4905

1

FD4906

1

H3
HOLEA

1

PAD_CT7P0B6P0D3P2

H9
HOLEA

C C

B B

1

PAD_C7P0D4P0

H11
HOLEA

1

PAD_C7P0D2P8

H14
HOLEA

1

PAD_C7P0D2P4

H15
HOLEA

1

PAD_CT7P0B10P0D4P0

PAD_CT7P0B6P0D3P2

H10
HOLEA

1

PAD_C7P0D4P0

H12
HOLEA

1

PAD_C7P0D2P8

H16
HOLEA

PAD_CT7P0B10P0D4P0

1

H4
HOLEA

1

H13
HOLEA

1

PAD_C7P0D2P8

H5
HOLEA

1

PAD_CT7P0B6P0D3P2

H6
HOLEA

1

PAD_CT7P0B6P0D3P2

H7
HOLEA

1

PAD_CT7P0B6P0D3P2

H17
HOLEA

1

PAD_O2P5X3P0D2P5X3P0N

H19
HOLEA

1

PAD_C2P5D2P5N

H8
HOLEA

1

PAD_CT7P0B6P0D3P2

H18
HOLEA

1

PAD_O2P5X3P0D2P5X3P0N

SODIMM Shielding

SH1

SHIELDING_SUL-35A2M_9P2X3P3_1P

1

1

SH8
SHIELDING_SUL-35A2M_9P2X3P3_1P

SH2

SHIELDING_SUL-35A2M_9P2X3P3_1P

1

1

SH5

SHIELDING_SUL-35A2M_9P2X3P3_1P

1

1

SH6
SHIELDING_SUL-35A2M_9P2X3P3_1P

1

1

SH7
SHIELDING_SUL-35A2M_9P2X3P3_1P

1

1

A A

+VGA_CORE +3VS

1

C168

0.1U_0201_6.3V6-K

2

@

5

For EMC

1

C169

0.1U_0201_6.3V6-K

2

@

1

1

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2017/03/14

2017/03/14

2017/03/14

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered D ate

Deciphered D ate

Deciphered D ate

2

2017/03/14

2017/03/14

2017/03/14

Title

Hole

Hole

Hole

Size Document Numb er Rev

Size Document Numb er Rev

Size Document Numb er Rev

C

C

C

Thursday, October 25, 2018

Thursday, October 25, 2018

Thursday, October 25, 2018

Date: Sheet of

Date: Sheet of

Date: Sheet of

S145AST

S145AST

S145AST

1

38 50

38 50

38 50

0.2

0.2

0.2

5

Vinafix.com

4

3

2

1

ZZZ1

PCB PN

DA600014L00

D D

UC2

AMD A6-9225 2.6G/2C/1M/FT4

A6@
SA000091V00

UC2

AMD A9-9425 3.1G/2C/1M/FT4

A9@
SA000091U00

C C

ZZZ3

S8G X2@

ZZZ5

H8GX2@

ZZZ6

Samsung

X7646D12003

Hynix

X7646D12001

Mi c r o n

X7646D12002

ZZZ2

HDMI PN

RO00000040J

M8GX2@

HDMI@

UC2

AMD E2-9000 1.8G/2C/1M/FT4

E2@
SA00007WW10

UC2

AMD A4-9125 2.3G/2C/1M/FT4

A4@
SA000091X00

UV1

PX@

R17M-M1-70 GPU

HDMIPCB

SA000086K00

GPU

APU type

VRAM X76 BOM

RV63

UV5

H8G_VR@

H5GC8H24AJR-R0C

SA000081630

B B

UV5

M8G_VR@

UV6

H8G_VR@

H5GC8H24AJR-R0C

SA000081630

UV6

M8 G _ V R @

H8G_VR@

4.53K_0402_1%

SD03445318J

RV63

M8 G _ V R @

RV70

H8G_VR@

4.99K_0402_1%

SD03449918J

VRAM_Hynix 8GX2

A A

5

MT51J256M32HF-70:B

SA000081730

UV5

S8G_VR@

K4G80325FB-HC28

SA000081C00

4

MT51J256M32HF-70:B

SA000081730

UV6

S8G _VR@

K4G80325FB-HC28

SA000081C00

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Issued Date

Issued Date

Issued Date

3

2017/03/14

2017/03/14

2017/03/14

4.75K_0402_1%

SD03447518J

RV63

3.4K_0402_1%

SD03434018J

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

VRAM_Micro 8GX2

S8G_VR@

RV70

S8G_VR@

10K_0402_1%

SD03410028J

VRAM_Samsung 8GX2

2017/03/14

2017/03/14

2017/03/14

2

Title

Title

Title

Virtual symbol

Virtual symbol

Virtual symbol

Siz e Document Number Rev

Siz e Document Number Rev

Siz e Document Number Rev

Custom

Custom

Custom

Thursday, October 25, 2018

Thursday, October 25, 2018

Thursday, October 25, 2018

Date: Shee t of

Date: Shee t of

Date: Shee t of

140S AST

140S AST

140S AST

1

39 50

39 50

39 50

0.1

0.1

0.1

5

Vinafix.com

4

3

2

1

EC_APU_ALWEN

APUALW_PWRGD

EC

V

3

4

V

10VEC_SYS_PWRGD

V

12

SYSON

SUSP#,SUSP

V

EC_O N

A C I N #A 3

A 5

+3VALW

A 5

A L W _ P W R G D

A 4

B4

ON/OFF

D D

AC
MODE

BATT
MO D E

C C

A 1

VIN

BATT

B1

V

PU301

V

A 2

V

B+

B2

PU401

A 5

B5

V

B5

V

B5

V

B3

V

V

+5VALW

SUSP #

6

B B

V

U13
+5VS

PU501

V V

+0.675VS

1

2

EC_RSMRST#

PBTN_OUT#

PM_SLP_S3#
PM_SLP_S5#

PLT_RST# 11

KBRST#

6

7

PU501
+VSYSMEM

V

5

U13

V

+3VS

PU10

V

+1.5VS

Q39

V

+1.8VS

Q41

V

+0.95VS

V

PU603

V

V V

V

+0.95VALW

PU601

V

VVVV

V

+1.8VALW

V

PXS_PWREN

V

PU604

A P U

+3VGS
QV6

V

+1.35VGS

VV

QV9

+1.8VGS
QV2

+0.95VGS

V

QV3

+VGA_CORE

V

PU701

+0.775VALW

APU_S5_MUX_CTRL

V

Compare
UC4

V

QC1/QC2/QC3/QC4

+VDDCR_FCH_S5

V

V VVV

VR_GFX_PWRGD

+APU_GFX

V

V

VVV V

VGA

+APU_CORE_NB

+APU_CORE

A A

5

8

EC_GFX_ON

8

EC_V R_ON

9

VR_APU_PWRGD

4

VDDG FX_PD

V

PU90 1

V

+APU_GFX

V

PU80 1
+APU_CORE

V

PU80 1
+APU_CORE_NB

+APU_GFX

VR_GFX_PWRGD

+APU_CORE

+APU_CORE_NB

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2017/03/14

2017/03/14

2017/03/14

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered D ate

Deciphered D ate

Deciphered D ate

2

VGA_PW RGD

2017/03/14

2017/03/14

2017/03/14

Title

Title

Title

Power sequence Block

Power sequence Block

Power sequence Block

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Thursday, October 25, 2018

Thursday, October 25, 2018

Thursday, October 25, 2018

Date: Sheet of

Date: Sheet of

Date: Sheet of

S145AST

S145AST

S145AST

1

40 50

40 50

40 50

0.2

0.2

0.2

5

Vinafix.com

D D

C C

4

3

2

1

B B

A A

5

Title

Title

Securi ty Cl assific ation

Securi ty Cl assific ation

Securi ty Cl assific ation

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2017/03/14

2017/03/14

2017/03/14

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciph ered Date

Deciph ered Date

Deciph ered Date

2

2017/03/14

2017/03/14

2017/03/14

Title

DP to CRT Convert(I T6515FN)

DP to CRT Convert(I T6515FN)

DP to CRT Convert(I T6515FN)

Size Docum ent Number Rev

Size Docum ent Number Rev

Size Docum ent Number Rev

Custom

Custom

Custom

Thursday, October 25, 2018

Thursday, October 25, 2018

Thursday, October 25, 2018

Date: Sheet of

Date: Sheet of

Date: Sheet of

S145AST

S145AST

S145AST

1

41 50

41 50

41 50

0.2

0.2

0.2

5

Vinafix.com

B+

Adaptor

D D

EC_ON

4

RT

LV5083

Converter

FOR SYSTEM

EN PGOOD

+5VLP/ 100mA

+5VALW/8A

+3VALW/6A

+3VLP/ 100mA

ALW_PWRGD

3

2

1

LCFC

LCFC5028

1.2VEN

TI

BQ24780SRUYR

Battery Charger

Switch Mode

C C

SMBus

SUSP#

+5VALW

EC_APU_ALWEN

+3VALW

EC_APU_ALWEN

+1.8VALW

EC_APU_ALWEN

S5

S3

EN

EN

EN

PMIC

FOR SYS

+1.2V/6A

+0.6VS/1A

PGOOD

+0.95VALW/6A

PGOOD

+1.8VALW/3A

PGOOD

+0.775VALW/0.5A

APUALW_PWRGD

APUALW_PWRGD

+3.3VALW

Battery

2.5VEN

EN

+2.5V/0.5A

Li-ion

2S1P

RT

LV5095B

Converter

B B

PXS_PWREN

FOR 1.35VGS

+1.35VGA /8A

PGOODEN

RT

RT3662EBGQW

Switch Mode

PXS_PWREN

APU_SVID

A A

EC_VR_ON

FOR VGA_CORE

EN PGOOD

RT

RT3661AB

Switch Mode

VIDs

FOR CPU CORE&NB

EN

+VGA_CORE/28A

APU_CORE/22A

APU_CORE_NB/18A

PGOOD

VR_VGA_PWRGD

VR_APU_PWRGD

5

Title

Title

Securi ty Cl assific ation

Securi ty Cl assific ation

Securi ty Cl assific ation

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2017/03/14

2017/03/14

2017/03/14

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciph ered Date

Deciph ered Date

Deciph ered Date

2

2017/03/14

2017/03/14

2017/03/14

Title

Power Diagram

Power Diagram

Power Diagram

Size Docum ent Number Rev

Size Docum ent Number Rev

Size Docum ent Number Rev

Custom

Custom

Custom

S145AST

S145AST

S145AST

Monday, November 12, 2018

Monday, November 12, 2018

Monday, November 12, 2018

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

42 50

42 50

42 50

0.2

0.2

0.2

5

Vinafix.com

4

3

2

1

PL101

HCB2012KF-121T50_0805

1 2

EMC_NS@

D D

JDCIN1

1

1

2

GND1

3

GND2

4

GND3

5

GND4

6

GND5

7

GND6

ME @

HIGHS_PJSS0026-8B01H

C C

PF101

APDIN APDIN1

7A_24VDC_429007.WRML

21

12

12

EMC@

PC101

1000P_0402_50V7K

+3VL

B B

2

PC105

1

@

1U_0402_10V6K

PD101

2

1

3

LBAT54CWT1G_SOT323-3

PR104

1K_0603_1%

12

HCB2012KF-121T50_0805

EMC@

100P_0402_50V8J

PC102

PL102

1 2

PJ101

JUMP_43X79

112

RTC_VCCVCCRTC

EMC@

2

@

HIGHS_WS33020-S0351-HF

VIN

JBATT1

1

1

2

2

9

3

GND1

10

4

GND2

5
6
7

12

12

EMC@

EMC@

100P_0402_50V8J

PC104

PC103

1000P_0402_50V7K

JRTC1

1

1

2

2

3

GND1

4

GND2

ME @

SUYIN_125022HB008M202ZL

ME @

8

EC_SMCA

3

EC_SMDA

4
5
6
7
8

AZC199-02S.R7G_SOT23-3

12

PR106

100_0402_1%

BATT_TEMP_IN

PD103

EMC_NS@

3

1

1 2

PR107

100K_0402_1%

1 2

PR108

10K_0402_1%

2

12

PRTC1

BATT CR2032 3V 220MAH

RTC@

PR105

100_0402_1%

35mm cable

GC02001YB00 main source
GC02001Z800 2nd source

PL103

HCB2012KF-121T50_0805

1 2

PL104

HCB2012KF-121T50_0805

1 2

12

PC106

EMC@

1000P_0402_50V7K

EC_SMB_CK 1 35,44

EC_SMB_DA 1 35,44

+3VALW

BATT_TEMP 35,44

EMC@

EMC@

BATT+VBAT

12

PC107

0.01U_0402_25V7K

EMC@

A A

5

Titl e

Titl e

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER N EITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER N EITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER N EITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2017/03/14

2017/03/14

2017/03/14

3

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2017/03/14

2017/03/14

2017/03/14

2

Titl e

DCIN / RTC

DCIN / RTC

DCIN / RTC

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Monday, November 12, 2018

Monday, November 12, 2018

Monday, November 12, 2018

Date: Sheet of

Date: Sheet of

Date: Sheet of

S145AST

S145AST

S145AST

1

43 50

43 50

43 50

0.2

0.2

0.2

5

Vinafix.com

4

3

2

1

D D

VIN

C C

ACIN35

EC_SMB_DA135,43

EC_SMB_CK135,43

ADP_I35

IDCHG35

B B

PSYS35

VR_HOT#35,49

ΎŚĂƌŐĞĐƵƌƌĞŶƚůŝŵŝƚϳŝƐĐŚĂƌŐĞĐƵƌƌĞŶƚůŝŵŝƚϭϬĚƵƌŝŶŐƚƵƌďŽΎ

5

12

PC201

PQ201
AONS32314_DFN8-5

4
12

470P_0402_50V7K

780s_ACDRV_R

P2 P3

1
2
3

PR202

4.7_0603_5%

12

1
2
3

PC202

0.022U_0402_25V7K

PQ202
AON7408L_DFN8-5

S1
S2
S3

G

4

5

D

VIN VIN

12

12

PR206

PR207

4.02K_0603_1%

4.02K_0603_1%

12

PR208

43K_0402_1%

7.15K_0402_1%

1 2

PR215 0_0402_5%

1 2

PR217 0_0402_5%

1 2

PR218 0_0402_5%

12

1 2

PR227

143K_0402_1%

1U_0603_25V6K

PC213

1 2

PR231

20K_0402_1%

PC215

PR210

1 2

1 2

0.01U_0402_25V7K

ΎK<ͺϭϬŬƉƵůůŚŝŐŚнϯs>ŽĨŽƉĞŶĚƌĂŝŶŽƵƚƉƵƚĂƚΎ

Ύ^Dh^ͺϮϮŬƉƵůůŚŝŐŚнϯs>ͺŽĨŽƉĞŶĚƌĂŝŶŽƵƚƉƵƚĂƚΎ

*EC-ADC*
*EC-ADC reserve*
*EC-ADC*

12

12

PC225

@

100P_0402_50V8J

1 2

PR232 0_0402_5%

PR219 0_0402_5%

PR220 0_0402_5%

PR221 0_0402_5%

12

PC226

PC227

100P_0402_50V8J

100P_0402_50V8J

1 2

1 2

@

1 2

ΎsZͺ,KdͺϭŬƉƵůůŚŝŐŚнϭϴs^ŽĨŽƉĞŶĚƌĂŝŶŽƵƚƉƵƚĂƚWhΎ

+3VALW

@

PJ201

JUMP_43X79

2

112

1

PC203

2

10U_25V_M_X5R_0603

EMC_NS@

1

2

BATT+

2

3

PD201

1

LBAT54CWT1G_SOT323-3

12

PR209
10_1206_5%

780s_VCC

780s_ACDET

780s_CMSRC

780s_ACDRV

780s_ACOK

780s_SDA

780s_SCL

780s_IADP

780s_IDCHG

780s_PMON

780s_VR_HOT

780s_ILIM

PR226

0_0402_5%

1 2

780s_ILIM_R

12

12

PC229

PR230

100K_0402_1%

0.1U_0402_25V6

PC204

EMC_NS@

12

28

11

12

10

13

14

21

10U_25V_M_X5R_0603

PC206

0.1U_0402_25V6

VCC

6

ACDET

3

CMSRC

4

ACDRV

5

ACOK

SDA

SCL

7

IADP

8

IDCHG

9

PMON

PROCHOT#

CMPIN

CMPOUT

ILIM

1 2

PR228

32.4K_0402_1%

PR201

0.01_1206_1%

1

2

1 2

PC205

0.1U_0402_25V6

ACP

2

ACP

PU201

BQ24780SRUYR_QFN28_4X4

TB_STAT#

16

780s_TB#

4

3

12

PC231

220P_0402_50V7K

EMC_NS@

12

PC207

0.1U_0402_25V6

1

1

12

PC233

PC232

2

470P_0402_50V7K

1000P_25V_K_X7R_0402

EMC_NS@

EMC_UMA@

12

12

PC234

PC236

PC235

2

0.01U_0402_50V6-K

6800P_0402_25V7-K

1000P_25V_K_X7R_0402

EMC_NS@

EMC_NS@

EMC_UMA@

')UT*)ULL

ACN

1

ACN

BATDRV

BATSRC

15

BQ24780S_VDD

2.2U_10V_K_X5R_0603
PC214

REGN

BTST

HIDRV

PHASE

LODRV

BATPRES#

24

25

26

27

23

22

GND

29

PAD

18

17

20

SRP

19

SRN

1 2

0.047U_0603_16V7K

2.2_0603_5%

780s_BS

1 2

PR211

780s_HG

780s_LX

780s_LG

780s_BATDRV

780s_BATSRC 780s_BATSRC_R

780s_SRP

780s_SRN

PC216

10_0603_5%

PR222

1 2

1 2

PR224

10_0603_5%

1 2

PR225

10_0603_5%

12

5

4

321

5

4

321

BATT_TEMP 35,43

PQ205

PQ206

12

12

PC237

220P_0402_50V7K

EMC_NS@

12

PC209

AON7380_DFN8-5

2.2UH_PCMB063T-2R2MS_8A_20%

12

PR216

4.7_0805_5%

EMC_NS@

12

AON7380_DFN8-5

PC222
1000P_0603_25V7K

EMC_NS@

PC238

470P_0402_50V7K

EMC_NS@

1 2

0.1U_0402_25V6

EMC_NS@

1 2

1

2

EMC_UMA@

PL201

780s_SRP_R

780s_SRN_R

1

PC239

2

0.22U_25V_K_X5R_0402

PC211

1 2

10U_0805_25V6K

V20B+

12

12

PC242

PC240

PC241

0.01U_0402_50V6-K

6800P_0402_25V7-K

0.22U_25V_K_X5R_0402

EMC_NS@

EMC_NS@

EMC_UMA@

780s_BATDRV

12

PR203

499K_0402_1%

5

4

PQ203
AON6324_DFN8-5

321

12

PC208

0.01U_0402_25V7K

V20B+

PC212

10U_0805_25V6K

PR213

0.01_1206_1%

1

4

3

2

1 2

PC228

0.1U_0402_25V6

12

PC223

0.1U_0402_25V6

12

PC224

0.1U_0402_25V6

12

12

12

INGXMK澓
I[XXKTZ#狤狥狧'SG^
\URZGMK#狤9狣6
LY]#狪狢狢18+-狢^狣狤A狫 狪C#狢狣
Z[XHUHUUYZ
I[XXKTZ#狥'IUTZOT[K

PC230

PC217

PC221

10U_0805_25V6K

10U_0805_25V6K

BATT+

12

PC210

10U_0805_25V6K

10U_0805_25V6K

A A

5

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

3

2013/08/08

2013/08/08

2013/08/08

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciph ered Date

Deciph ered Date

Deciph ered Date

2013/08/05

2013/08/05

2013/08/05

2

Title

CHARGER

CHARGER

CHARGER

Size Docum ent Number Rev

Size Docum ent Number Rev

Size Docum ent Number Rev

Custom

Custom

Custom

Monday, November 12, 2018

Monday, November 12, 2018

Monday, November 12, 2018

Date: Sheet of

Date: Sheet of

Date: Sheet of

S145AST

S145AST

S145AST

44 50

44 50

44 50

0.2

0.2

0.2

1

5

Vinafix.com

D D

4

3

2

1

9

7

PU3501

VIN1

EN1

PGOOD1

VCC1

VIN2

EN2

PGOOD2

VCC2

VINSW1

ENSW1

VINSW2

ENSW2

+5VLP

25

VDDSW

LV5083AGQUF_UQFN36_5X4

AGND_217PGND_112PGND_2

13

BOOT1

VOUT1

VBYP3

BOOT2

VOUT2

VBYP5

VOUTSW1

VOUTSW2

AGND_3

32

LX1_1
LX1_2
LX1_3

LDO3

LX2_1
LX2_2
LX2_3

LDO5

8

+3VALW_BS

+3VALW_LX

+3VALW_P

і

100mA

ї

+5VALW_BS

+5VALW_LX

+5VALW_P

і

100mA

ї

+3VS_SW

3VS_SS

1 2

PC3562

2200P_0402_25V7-K

+5VS_SW

5VS_SS

1 2

PC3561

2200P_0402_25V7-K

1 2

10_0603_5%

+3VLP

1 2

10_0603_5%

3

1
2
35

6

4

5

22

23
24
36

19

21

20

29

31

SS1

28

26

SS2

AGND_1

0.1U_0603_25V7K

PR3511

PC3545 4.7U_0603_6.3V6K

PR3512

PC3554 0.1U_0603_25V7K

+5VLP

PC3541

1 2

1 2

1 2

PC3559

1 2

4.7U_10V_K_X5R_0603

12

PC3568

@

1U_0402_10V6K

PL3501

1 2

1.5UH_PCMB063T-1R5MS_10A_20%

PJ3505

@

2

112

JUMP_43X39

PL3502

1 2

1.5UH_PCMB063T-1R5MS_10A_20%

PJ3506

@

2

112

JUMP_43X79

PJ3507

@

2

112

JUMP_43X79

+3VALW

+3VL

+5VALW

+3VS

+5VS

1

PC3539

2

22UC_6.3VC_MC_X5RC_0603

1

PC3555

2

22UC_6.3VC_MC_X5RC_0603

+3VALW_LX

12

PR3508

2.2_0805_5%

EMC_NS@

+3VALW_SN

12

PC3532

1000P_0402_50V7K

EMC_NS@

PJ3502

+3VALW_P

1

1

1

PC3544

PC3543

2

1

2

PC3542

2

2

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

+5VALW_P

1

1

PC3553

PC3552

PC3551

2

2

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

+5VALW_LX

12

PR3509

2.2_0805_5%

EMC_NS@

+5VALW_SN

12

PC3533

1000P_0402_50V7K

EMC_NS@

@

2

112

JUMP_43X79

PJ3504

@

2

112

JUMP_43X79

狥<'2=
:*)#狨'

5)6#狪'
5<6#狣狤狢
,Y]#狧狢狢1.`
狧<'2=
:*)#狪'

5)6#狣狢'
5<6#狣狤狢
,Y]#狧狢狢1.`

+3VALW

+5VALW

PJ3501

@

2

V20B+

EC_ON35,46

*EC P-P 3.3V normal mode*

MAINPWON35

C C

EC_ON_R30

V20B+

+3VALW

+3VALW

B B

+5VALW

112

JUMP_43X79

0_0402_5%

PR3501

1 2

PD3501

1 2

LRB751V-40T1G_SOD323-2

PJ3503

@

2

112

JUMP_43X79

PR3513

100K_0402_5%

PR3514

100K_0402_5%

@

12

@

12

12

@

12

+3VALW_PG

ALW_PWRGD

1

2

@

1

2

@

12

12

PC3536

PC3534

PC3535

0.1U_0402_25V6

PC3546

0.1U_0402_25V6

PC3566

22UC_6.3VC_MC_X5RC_0603

PC3565

22UC_6.3VC_MC_X5RC_0603

10U_0805_25V6K

10U_0805_25V6K

EMC_NS@

0_0402_5%

PR3507

1 2

0_0402_5%

PR3510

1 2

12

12

PC3548

PC3547

EMC_NS@

10U_0805_25V6K

10U_0805_25V6K

12

PC3530

1U_0402_6.3V6K

12

PC3531

1U_0402_10V6K

+3VALW_EN

+5VALW_EN

SUSP#35,37,46

+3VALW_EN

+5VALW_EN

SUSP#

12

12

PR3517

1 2

0_0402_5%

PR3518

1 2

0_0402_5%

+3VALW_VIN

11

PC3538

1 2

PC3550

1 2

+3VS_EN

1U_0402_6.3V6K

+5VS_EN

1U_0402_6.3V6K

10

14

15

16

18

33

30

34

27

+3VALW_PG

@

PC3537

0.1U_0402_25V6
1U_0402_6.3V6K

+5VALW_VIN

ALW_PWRGD

@

PC3549

0.1U_0402_25V6

1U_0402_6.3V6K

12

PC3569

@

12

PC3570

@

A A

5

Title

Title

Securi ty Cl assific ation

Securi ty Cl assific ation

Securi ty Cl assific ation

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2013/08/08

2013/08/08

2013/08/08

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciph ered Date

Deciph ered Date

Deciph ered Date

2

2013/08/05

2013/08/05

2013/08/05

Title

CHARGER

CHARGER

CHARGER

Size Docum ent Number Rev

Size Docum ent Number Rev

Size Docum ent Number Rev

Custom

Custom

Custom

Monday, November 12, 2018

Monday, November 12, 2018

Monday, November 12, 2018

Date: Sheet of

Date: Sheet of

Date: Sheet of

S145AST

S145AST

S145AST

1

45 50

45 50

45 50

0.2

0.2

0.2

5

Vinafix.com

4

3

2

1

PC1911

0.1U_0402_25V6

PC1919

0.1U_0402_25V6

LV5028_0.95VALW_EN

LV5028_0.775VALW_EN

EMC_NS@

+1.2V_P

EMC_NS@

LV5028_VDDQ_EN

LV5028_VTT_EN

LV5028_1.8VALW_EN

LV5028_2.5V_EN

+0.6VS

TDC=1A

+1.8VALW

+3VALW

PJ1905

112

JUMP_43X39

@

PJ1906

112

JUMP_43X39

PJ1908

112

JUMP_43X39

PR1907

10_0603_5%

LV5028_0.775VALW_EN

LV5028_2.5V_EN

LV5028_0.95VALW_EN

LV5028_1.8VALW_EN

LV5028_VDDQ_EN

LV5028_VTT_EN

LV5028_0.95VALW_VIN

LV5028_V1.8VALW_VIN

PR1917

LV5028_0.775VALW_VIN

2

PC1927
10U_0603_6.3V6M

1

2

PC1934
10U_0603_6.3V6M

1

LV5028_CS

@

LV5028_2.5V_VIN

1 2

PC1902

12

2.2U_10V_K_X5R_0603

PR1909

1 2

10_0402_5%

12

PC1901

0.1U_0402_25V6

29

EN_LDO1

1

EN_LDO2

11

EN_V1P0A

16

EN_V1P8A

31

EN_VDDQ

36

EN_VTT

7

VIN_V1P0A1

8

VIN_V1P0A2

19

VIN_V1P8A

38

ї

VIN_VTT

39

і

VTT

40

VSNS_VTT

30

CS_VDDQ

5

VIN_LDO1

4

VIN_LDO2

PU1901
LV5028RPC_QFN40_5X5

LV5028_VSYS

28

27

VSYS

+5VLP

+1.2V_B+

2

PC1924
10U_0603_6.3V6M

1

+0.6VS_P

2

1

PC1926

2

1 2

@

2

@

2

33K_0402_1%

22UC_6.3VC_MC_ X5RC_0603

PR1901 0_0402_5%

LV5028_PMIC_EN

9

41

VCC

GND

SDA

PMIC_EN

SCL

PG_V1P0A

PG_V1P8A

PG_VDDQ

LX_V1P0A1
LX_V1P0A2
LX_V1P0A3
LX_V1P0A4

VO_V1P0A

LX_V1P8A1
LX_V1P8A2

VO_V1P8A

UGATE_VDDQ

BS_VDDQ

LX_VDDQ

LGATE_VDDQ

VSNS_VDDQ

LDO1

LDO2

FB_LDO2

1 2

PC1903

1 2

0.1U_0402_10V7K

25

26

24

OT

22

21

23

12
13
14
15

10

17
18

20

33

32

34

35

37

6

3

2

@

EC_ON 35,45

+3VALW

LV5028_EC_SMB_DA2

LV5028_EC_SMB_CK2

LV5028_ALERT#

APUALW_PWR GD

APUALW_PWR GD

LV5028_LX_0.95VALW

LV5028_LX_1.8VALW

LV5028_UG_1.2V

LV5028_BST_1.2V

LV5028_LX_1.2V

LV5028_LG_1.2V

+1.2V_P

+0.775VALW_P

+2.5V_P

+2.5V_FB

1 2

PR1925 0_0402_5%

1 2

PR1926 0_0402_5%

1 2

PR1912 0_0402_5%

*1.8VALW & 0.9VALW power on ready push APUALW_PWRGD*

1 2

0_0603_5%

@

PL1901

1 2

0.47UH_PCMB063T-R47MS_18A_20%

PL1902

1 2

1UH_PH041H-1R0MS_3.8A_20%

PR1916

PC1925

1 2

0.1U_0603_25V7-M

12

PR1920

24.9K_0402_1%

12

PR1921

10.5K_0402_1%

LV5028_UG_1.2V

LV5028_LG_1.2V

2

1

2

1

PC1928
10U_0603_6.3V6M

PC1935
10U_0603_6.3V6M

EC_SMB_DA2 35

EC_SMB_CK2 352_5VEN35

H_PROCHOT# 6,35

1

4

4

1

PC1912

2

1

PC1920

2

PJ1907

112

JUMP_43X39

PJ1909

112

JUMP_43X39

5

G

3

5

321

D

1

1

PC1914

PC1915

PC1913

2

2

2

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

1

PC1921

2

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

@

2

+0.775VALW

TDC=0.1A
VDDCR_FCH_S5 Voltage

@

=0.775V ±50mv in S3 S4 S5

2

+2.5V

TDC=0.676A
FB reference=0.75V

PQ1901
AON7408L_DFN8-5

S11S22S3

LV5028_LX_1.2V

PQ1902
AON7380_DFN8-5

22UC_6.3VC_MC_X5RC_0603

12

PR1915

100K_0402_5%

APUALW_PWR GD 35

+0.95VALW_P

1

1

PC1917

PC1916

2

2

@

@

+1.8VALW_P

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

1

1

PC1922

PC1923

2

2

@

@

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

PL1903

1 2

0.47UH_PCMB063T-R47MS_18A_20%

PR1922

4.7_0805_5%

EMC_NS@

1 2

12

PC1943
680P_0402_50V7K

EMC_NS@

PJ1902

2

112

TDC=6A

JUMP_43X79

Voltage =0.95V

@

reference AST OPN-specific ±50mv
OVP=120%

PJ1904

2

OCP=12A

112

TDC=3A

JUMP_43X79

Voltage =1.8V ±90mv

@

OVP=120%
OCP=6A

LV5028_LX_0.95VALW

PR1918

4.7_0603_5%

EMC_NS@

1 2

12

PC1930
680P_0402_50V7K

EMC_NS@

LV5028_LX_1.8VALW

PR1919

4.7_0603_5%

EMC_NS@

1 2

12

PC1931
680P_0402_50V7K

EMC_NS@

+0.95VALW

+1.8VALW

+1.2V_B+

12

PC1929

0.1U_0402_25V6

PC1933

PC1932

10U_0805_25V6K

10U_0805_25V6K

EMC_NS@

12

12

+1.2V_P

1

1

1

1

PC1937

PC1938

2

2

22UC_6.3VC_MC_X5RC_0603

1

1

PC1940

PC1939

PC1941

PC1942

2

2

2

2

@

@

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

PJ1910

2

112

V20B +

JUMP_43X79

@

@

PJ1911

2

112

+1.2V

JUMP_43X118

TDC=6A
Voltage =1.2V ±60mv
OVP=120%
OCP=200mV/13mohm=15A

1 2

1_2VEN35

D D

C C

SUSP#35,37,45

EC_APU_ALWEN35

+5VALW

+3VALW

B B

A A

PR1902 0_0402_5%

PC1909

0.1U_0402_10V7K

1 2

PR1904 0_0402_5%

PC1908

0.1U_0402_10V7K

1 2

PR1906 0_0402_5%

PC1907

0.1U_0402_10V7K

1 2

PR1908 0_0402_5%

PC1906

0.1U_0402_10V7K

1 2

PR1910 10K_0402_5%

PC1905

0.1U_0402_10V7K

1 2

PR1911 0_0402_5%

PC1904

0.1U_0402_10V7K

@

PJ1901

2

112

JUMP_43X39

@

PJ1903

2

112

JUMP_43X39

@

12

@

12

@

12

@

12

@

12

@

12

1

12

PC1910

2

22UC_6.3VC_MC_X5RC_0603

1

12

PC1918

2

22UC_6.3VC_MC_X5RC_0603

5

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZ ED BY LC FUTURE CENTER NEITHER T HIS SHEET NOR THE INFORMAT ION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZ ED BY LC FUTURE CENTER NEITHER T HIS SHEET NOR THE INFORMAT ION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZ ED BY LC FUTURE CENTER NEITHER T HIS SHEET NOR THE INFORMAT ION IT CONTAINS
MAY BE USED BY OR DISCLOSED T O ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF LC F UTURE CENTER.

MAY BE USED BY OR DISCLOSED T O ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF LC F UTURE CENTER.

4

3

MAY BE USED BY OR DISCLOSED T O ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF LC F UTURE CENTER.

2017/03/14

2017/03/14

2017/03/14

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered D ate

Deciphered D ate

Deciphered D ate

2

2017/03/14

2017/03/14

2017/03/14

Title

System PMIC

System PMIC

System PMIC

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Monday, November 12, 2018

Monday, November 12, 2018

Monday, November 12, 2018

1

S145AST

S145AST

S145AST

46 50

46 50

46 50

0.2

0.2

0.2

A

Vinafix.com

B

C

D

1 1

V20B+

+3VALW

+1.8VALW

2 2

+0.95VALW

3 3

PJ3601

2

JUMP_43X79

112

@

PXS_PWREN7,48

+5VALW

PXS_PWREN

PXS_PWREN

12

12

PC3602

PC3601

10U_0805_25V6K

10U_0805_25V6K

PX@

PX@

PD3601 RB751V-40_SOD323-2

PR3602

PC3604 0.1U_0402_25V6

1 2

PX@

PR3610

PC3614 0.1U_0402_25V6

1 2

@

PC3615 1U_0402_6.3V6K

1 2

@

PC3616 1U_0402_10V6K

12

PX@

1 2

PX@

1 2

@

1 2

PX@

1 2

@

PR3604

PR3617

PC3621 0.1U_0402_25V6

PC3622 1U_0402_6.3V6K

PC3609 0.1U_0402_25V6

PC3624 1U_0402_6.3V6K

@

1 2

PX@

1 2

200K_0402_1%

PX@

1 2

15K_0402_1%

PX@

1 2

20K_0402_1%

PX@

1 2

47.5K_0402_1%

+1.35V_VIN

+1.35VGS_EN

+3VGS_EN

+1.8VGS_ENPXS_PWREN

+0.95VGS_EN

PU3601

12

VI N 4

16

EN4

25

EN1

22

VI N 1

24

VC C _ S W

19

EN2

21

VI N 2

28

EN3

1

VI N 3 _ 1

2

VI N 3 _ 2

29

VI N 3 _ 3

PR3611

100K_0402_1%

@

1U_0402_6.3V6K

+1.35V_BST +1.35V_P

18

5

3

SW_1

AGND

VBOOT

4

SW_2

15

FB

23

VO U T 1

TH_ALT

14

1 2

PC3629

PX@

PX@

LV5095AGQUF_UQFN29_4X4

17

+1.35V_VCC

12

PGND_1

PGND_2

PGND_3

PGND_4

PGND_5

PGND_6

VO U T 2

VO U T 3 _ 1

VO U T 3 _ 2

PGOOD13VCC

12

PR3612
100K_0402_1%

@

6

7

8

9

10

11

20

26

27

PR3601
10_0603_5%

1 2

+1.35V_ FB

PX@

PC3603

0.1U_0603_25V7-M

1

+1.35V_ LX

2

PX@

PC3605 0.1U_0402_25V6

1 2

@

+3VGS_P

PC3618 1U_0402_6.3V6K

1 2

PX@

+1.8VGS_P

PC3623 1U_0402_6.3V6K

1 2

PX@

+0.95VGS_P

PC3625 1U_0402_6.3V6K

12

PX@

PL3601

0.68UH_PCMB063T-R68MN_16A_20%

1 2

12

PR3603

2.2_0603_5%

EMC_PXNS@

12

PC3619

1000P_0402_50V7K

EMC_PXNS@

PJ3605 JUMP_ 43X39

112

TDC=0.025A
Voltage=3.3V ±9%
Rdson=36mohm

PJ3603 JUMP_ 43X39

112

PJ3604

112

JUMP_4 3X39

PX@

1 2

1K_0402_1%

12

PC3620
560P_0402_50V7-K

PX@

@

2

+3VGS

@

2

+1.8VGS

@

2

+0.95VGS

PR3606

PX@

12

PR3608

1/16W_41.2K_1%_0402

PX@

12

PR3609

31.6K_0402_1%

PX@

TDC=0.33A
Voltage=1.8V ±3%
Rdson=18mohm

TDC=1.905A
Voltage=0.95V ±3%
Rdson=5mohm

@

PJ3602

2

112

1

1

1

PC3606

PC3611

2

2

PX@

PX@

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

1

1

PC3607

PC3608

2

2

2

@

PX@

PX@

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

JUMP_43X118

1

TDC=10A

PC3612

PC3613

2

@

Voltage=1.36V ±3% FB=0.6V
OCP=13A
OVP=130%

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

+1.35VGS

4 4

A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRA WING IS THE PROPRIETARY PROP ERTY OF LC FUTURE CENTER. A ND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRA WING IS THE PROPRIETARY PROP ERTY OF LC FUTURE CENTER. A ND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRA WING IS THE PROPRIETARY PROP ERTY OF LC FUTURE CENTER. A ND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRA NSFERED FROM THE CUSTODY O F THE COMPETENT DIVISIO N OF R&D

AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRA NSFERED FROM THE CUSTODY O F THE COMPETENT DIVISIO N OF R&D

AND TRADE SECRET INFORMATIO N. THIS SHEET MAY NOT BE TRA NSFERED FROM THE CUSTODY O F THE COMPETENT DIVISIO N OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

C

2013/08/15

2013/08/15

2013/08/15

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2013/08/15

2013/08/15

2013/08/15

Title

PWR_1.35VGS

PWR_1.35VGS

PWR_1.35VGS

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A2

A2

A2

Date: Sheet of

Date: Sheet of

Date: Sheet of

S145AST

S145AST

S145AST

Monday, November 12, 2018

Monday, November 12, 2018

Monday, November 12, 2018

D

47 50

47 50

47 50

0.2

0.2

0.2

5

Vinafix.com

4

3

2

1

PX@

PX@

PX@

PX@

2

PX@

60.4K_0402_1%

2

PR2419

PH2401

2

PX@

100K_0402_1%_TSM0B104F4251RZ

12

PX@

2

PR2423

PX@

7.87K_0402_1%

1

1

1

VGA_SVC

VGA_SVD

VGA_SVT

1

PX@

@

1 2

VGA_ V CC

VGA_PVCC

VGA_ S E T 1

VGA_ T S E NVGA_T SEN_ 1

1

PX@

1

PX@

GPU_VREF_PINSET

VGA_ I MO N

1

PX@

PX@

PC2429

.1U_0402_10V6-K

14

27

11

10

13

12

9

15

20

16

17

18

32

33

VCC

PVCC

SET1

TSEN

VREF_PINSET

IMON

VRHOT_L

PWROK

PGOOD

SVC

SVD

SVT

EN

GND

PX@

PU2401

RT3662EBGQW_WQFN32_4X4

VGA_ V DD I O

19

VDDIO

VGA_ V IN

1

VIN

21

VSEN

3

COMP

4

FB

2

RGND

22

NC

23

BOOT1

24

UGATE1

25

PHASE1

26

LGATE1

7

ISEN1P

8

ISEN1N

31

BOOT2

30

UGATE2

29

PHASE2

28

LGATE2

5

ISEN2P

6

ISEN2N

4

PC2411 100P_0402_50V8J

VGA_COMP

PR2414 30K_0402_1%

VGA_ F B

VGA_ B O O T 1

PR2411 2.2_0603_5%

VGA_ P H AS E 1

VGA_LGAT E1

VGA_ I SE N 1 P

VGA_ I SE N 1 N

1 2

VGA_ V CCVGA_ E N

PC2415

0.1U_0402_25V6

PX@

2 1

1 2

PX@

12

PX@

PX@

1 2

PR2408

PR2405

PX@

PR2409

PR2425

5

VGA_SET1_2

12

PX@

VGA_SET1_1

2

VGA_TSE N_2

12

PX@

VGA_TSE N_3

PX@

12

PX@

VGA_IMON_ 2

PX@

VGA_IMON_ 1

PX@

PR2401 4.7_0603_5%

2 1

PC2404 2.2U_10V_K_X5R_0402

1 2

PR2403 0_0603_5%

2 1

PC2407 2.2U_10V_K_X5R_0402

0_0402_5%

PR2410

1

PX@

11.3K_0402_1%

1 2

PR2406

0_0402_5%

PR2413

1 2

PX@

1 2

PR2418

24K_0402_1%

VRFF_R_1

PR2420

3.9_0402_1%

1 2

PR2422

12.1K_0402_1%

PX@

2

PR2432 10K_0402_5%

PX@

2

PR2431 10K_0402_5%

PX@

2

PR2430 10K_0402_5%

PX@

1 2

PR2426 0_0402_5%

PX@

1 2

PR2427 0_0402_5%

PX@

1 2

PR2428 0_0402_5%

2

PR2429

150K_0402_1%

1 2

PD2401

RB751V-40_SOD323-2

D D

+5VALW

196K_0402_1%

0_0402_5%

1

324K_0402_1%

1 2

PR2417

GPU_VREF_PINSET

C C

+3VGS

+VDDIO_GPU

+3VGS

B B

A A

0_0402_5%

PC2420 .47U_0402_6.3V6K

1 2

PH2402

100K_0402_1%_TSM0B104F4251RZ

1 2

14.3K_0402_1%

GPU_VR_HOT#16,35

VGA_PWRO K15

VR_VGA_PW RGD7,15

GPU_SVC16

GPU_SVD16

GPU_SVT16

PXS_PWREN7,47

1

2

PR2402 4.7_0402_5%

PX@

1

2

PC2405 2.2U_0402_6.3V6-K

PX@

1

2

PR2404 4.7_0402_5%

PX@

1

2

PC2408 1U_0402_25V6-K

PX@

2 1

PC2412 150P_0402_50V8-J

1

2

PR2415 10K_0402_1%

12

PC2409 0.22U_0603_25V7K

PX@

+VDDIO_GPU+5VALW

*local sense

12

PC2416
100P_0402_50V8J

PX@

12

PC2418

0.1U_0402_25V6

@

12

PC2419

0.1U_0402_25V6

@

VR output capacity*

V20B+

PX@

PX@

3

+VGA_COR E

1 2

PR2421

@

10_0402_5%

1 2

PR2424

@

10_0402_5%

*remote sense
GPU side*

VGA_UGAT E1

VGA_PHASE 1

VGA_LGAT E1

VGA_CORE _SEN 16

VGA_VSS_S EN 16

5

PQ2401

4

AON6380_DFN8-5

PX@

321

5

4

321

5

PQ2403

4

AON6324_DFN8-5

PX@

321

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2

*L/DCR=PC2414*(PR2407//PR2416)*

12

PQ2402

PR2412

4.7_0805_5%

EMC_PXNS@

AON6324_DFN8-5

PX@

12

PC2417

680P_0402_50V7K

EMC_PXNS@

2017/03/14

2017/03/14

2017/03/14

PL2401

0.22UH_CMMS063T-R22MS2R107_26A_20%

1 2

@

PJ2401
JUMPER

1 2

357_0402_1%

1.43K_0402_1%

1

2

2

PR2407

PX@

0.47U_0402_25V6K

VGA_ISEN1P

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

PR2416

PC2414

2 1

12

12

PC2401

0.1U_0402_25V6

EMC_PX@

PX@

@

PJ2402
JUMPER

1 2

1

PX@

PX@

VGA_ISEN1N

2017/03/14

2017/03/14

2017/03/14

1

1

1

+

+

PC2406

PC2413

2

2

2

330U_D2_2V_Y

330U_D2_2V_Y

PX@

PX@

TDC=21A EDC=1.5*28A=42A
voltage=VID_VDDC-I_VDDC×1mȍ±15 m V
undershoot 30mV
overshoot 50mV

1

1

1

1

PC2424

PC2423

PC2425

2

2

2

2

@

@

PX@

PX@

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

Title

Title

Title

PWR-XXXX

PWR-XXXX

PWR-XXXX

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

12

PC2402

PC2403

10U_0805_25V6K

PX@

PX@

1

+

+

PC2430

PC2410

2

330U_D2_2V_Y

PX@

CD@

1

PC2427

PC2426

2

PX@

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

Monday, November 12, 2018

Monday, November 12, 2018

Monday, November 12, 2018

1

10U_0805_25V6K

330U_D2_2V_Y

1

2

PX@

PC2428

22UC_6.3VC_MC_X5RC_0603

S145AST

S145AST

S145AST

V20B+

+VGA_CORE

48 50

48 50

48 50

0.2

0.2

0.2

5

Vinafix.com

PR2226

4.7_0603_5%

+5VALW V20B+

APU_VREF_PINSET

12

12

D D

VR_APU_PWRGD35

C C

APU_SVC_R

APU_SVD_R

APU_SVT_R

B B

12

PR2273

PR2271

PR2272

316K_0402_1%

34.8K_0402_1%

69.8K_0402_1%

12

PR2270

1.91K_0402_1%

+1.8VS

@

@

12

12

PR2262

1K_0402_1%

@

@

12

12

PR2265

220_0402_5%

APU_VREF_PINSET

12

12

PR2235

PR2219

15K_0402_1%

+3VS

PR2233

12

PR2263

1K_0402_1%

12

PR2266

220_0402_5%

12

33K_0402_1%

24K_0402_1%

PR2287

3.9_0402_1%

12

12

.47U_0402_6.3V6K

PC2286

/354ZKSVKXGZ[XKIUSVKTYGZOUTV[ZINUIQYOJK

/354ZKSVKXGZ[XKIUSVKTYGZOUTV[ZINUIQYOJK

VR_HOT#35,44

<8E.5:5*V[RRNOMN狣狪<9'6;YOJK

APU_PWROK6

APU_SVC6

APU_SVD6

APU_SVT6

EC_VR_ON35

@

PR2264

1K_0402_1%

@

@

12

12

PC2269

PC2268

PRE-PWROK METAL VID CODES

1U_0402_6.3V6K

.1U_0402_10V6-K

@

PR2267

220_0402_5%

SVDSVC

00
0

110 0.9V(Default)

11

1 2

1

PC2226
1U_10V_K_X5R_0603

2

0_0402_5%

PR2224

1 2

1

PC2227
1U_10V_K_X5R_0603

2

PR2232

60.4K_0402_1%

1 2

APU_TSEN_CORE_R APU_TSEN_CORE

APU_TSEN_NB_R AP U_TSEN_NB

1 2

PR2275 14.7K_0402_1%

APU_IMON_CORE_NTC

1 2

PR2276 11.8K_0402_1%

1 2

PR2277 13.7K_0402_1%

1 2

PR2278 13K_0402_1%

Boot Voltage

1.1V

1.0V

PH2203

1 2

100K_0402_1%_TSM0B104F4251RZ

ZKSVKXGZ[XKYKTYKV[ZNOMNZKSVKXGZ[XKGXKG

PR2218

60.4K_0402_1%

1 2

1 2

0_0402_5%

PR2201

1 2

APU_IMON_NB_NTC

100K_0402_1%_TSM0B104F4251RZ

ZKSVKXGZ[XKYKTYKV[ZNOMNZKSVKXGZ[XKGXKG

APU_IMON_CORE_R

PH2205

1 2

100K_0402_1%_TSM0B104F4251RZ

1 2

100K_0402_1%_TSM0B104F4251RZ

1 2

PR2222 0_0402_5%

1 2

PR2230 0_0402_5%

1 2

PR2234 0_0402_5%

1 2

PR2220 0_0402_5%

1 2

PR2223 0_0402_5%

PR2228 0_0402_5%

1 2

1 2

PR2229 0_0402_5%

8.87K_0402_1%

6.34K_0402_1%

PH2206

0.8V

APU_PVCC

PH2202

APU_VREF_PINSET_R

PR2231

APU_IMON_C ORE

1 2

PR2227

APU_IMON_NBAPU_IMON_NB_R

1 2

APU_VR_HOT_L

APU_PWROK_R

VR_APU_PGOOD_R

APU_SVC_R

APU_SVD_R

APU_SVT_R

12

PR2288

1M_0402_5%

APU_VCC

APU_SET1

APU_EN_R

4

17

34

13

12

23

15

14

16

11

18

3

19

20

21

29

1

2

39

40

41

PU2201

VCC

PVCC

SET1

TSE N

TSEN_NB

VREF_PINSET

IMON

IMON_NB

VRHOT_L

PWROK

PGOOD

SVC

SVD

SVT

EN

NC1

NC2

NC3

NC4

GND

RT3661ABGQW_WQFN40_5X5

VSEN_NB

COMP_NB

BOOT_NB

UGATE_NB

PHASE_NB

LGATE_NB

ISENP_NB

ISENN_NB

3

PR2269

4.7_0603_5%

1 2

1

PC2290

0.1U_50V_K_X5R_0402

2

1

2

APU_VIN

28

VIN

APU_VDDIO_R

22

VDDIO

APU_CORE_VSEN_R

8

VSEN

APU_CORE_COMP

5

COMP

APU_CORE_FB

6

FB

APU_CORE_RGND_R

4

RGN D

APU_CORE_BOOT 1

38

APU_CORE_UGAT E1

37

APU_CORE_PHASE1

36

APU_CORE_LGA TE1

35

APU_CORE_ISE N1P

9

APU_CORE_ISE N1N

10

APU_NB_VSEN_R

7

APU_NB_COMP

27

APU_NB_FB

26

APU_NB_BOOT

30

APU_NB_UGAT E

31

APU_NB_PHA SE

32

APU_NB_LGATE

33

APU_NB_ISENP

25

APU_NB_ISENN

24

1 2

PR2237

2.2_0603_5%

DCR sense
kevin routing

12

PC2237

0.1U_0402_25V6

@

12

PC2291

0.1U_0402_25V6

PR2211

2.2_0603_5%

BOOT_NB_R

1 2

12

PC2288

0.1U_0402_25V6

BOOT

UGA TE

PHASE

LGATE

ISEN1P

ISEN1N

FB_NB

PC2289
1U_0402_10V6K

1 2

PC2239 82P_0402_50V9-G

1 2

PR2250 39K_0402_1%

CORE_BOOT_R

1 2

PC2233

0.1U_0603_25V7-M

1 2

PC2206 82P_0402_50V9-G

1 2

PR2206 44.2K_0402_1%

PC2211

0.1U_0603_25V7-M

1 2

DCR sense
kevin routing

PR2225

2.2_0603_5%

1 2

1 2

PR2289 0_0402_5%

+1.8VS+5VALW

1 2

PC2238 150P_0402_50V8-J

1 2

PR2249 10K_0402_1%

5

4

PQ2203

AON6380_DFN8-5

321

5

4

PQ2204

AON6324_DFN8-5

321

1 2

PC2205 150P_0402_50V8-J

1 2

PR2205 10K_0402_1%

5

4

PQ2201

AON6380_DFN8-5

321

5

4

PQ2202

AON6324_DFN8-5

321

4

APU_NB_PHA SE

5

321

PQ2205

APU_NB_VSEN

PC2292

0.1U_0402_25V6

1 2

@

PR2290

APU_CORE_VSEN

1 2

0_0402_5%

12

PC2255

PR2202

@

AON6324_DFN8-5

APU_CORE_RGND

330P_0402_50V8J

1 2

0_0402_5%

PR2253 and PR2256 local sense
sense VR output capacity
PR2254 and PR2255 remote sense
sense CPU ball
kevin routing

12

APU_CORE_ISEN+

PR2204
100_0402_1%

1 2

PR2208
0_0402_5%

1 2

12

PR2214

EMC@

0_0402_5%

@

APU_NB_ISE N+

EMC@

0.22UH_PCME064T-R22MS0R985_28A_20%

PR2283
0_0402_5%

@

APU_CORE_ISEN1P

APU_CORE_ISEN1N

1.5K_0402_1%

1 2

APU_CORE_PHASE1

12

PR2268

4.7_0805_5%

EMC_NS@

CORE_SN

12

PC2234
680P_0402_50V7K

EMC_NS@

PR2204 local sense
sense VR output capacity
PR2208 remote sense
sense CPU ball
kevin routing with APU_VDD_SEN_L

12

PR2212

1/8W_1_5%_0805

NB_SN

12

PC2222

2200P_0402_50V7K

PR2253

100_0402_1%

1 2

PR2254

0_0402_5%

1 2

PR2256

100_0402_1%

1 2

PR2255
0_0402_5%

1 2

PL2202

1 2

PR2242

1.24K_0402_1%

1 2

+APU_CORE_NB

APU_VDDNB_SEN_H 6

0.36UH_PCMB063T-R36MS_20A_20%
PL2201

1 2

0.47U_0402_25V6K

PR2280

PC2287

1 2

PR2281
374_0402_1%

1 2

2

+APU_CORE

APU_VDDCORE_S EN_H 6

APU_VDD_SE N_L 6

12

PR2284
0_0402_5%

0.47U_0402_25V6K

@

PC2244

1 2

PR2243

1.24K_0402_1%

1 2

12

PR2215
0_0402_5%

@

1

V20B+

12

12

PC2229

PC2230

10U_0805_25V6K

1

1

+

+

PC2249

PC2251

2

2

330U_D2_2V_Y

1

1

1

PC2280

PC2279

PC2281

2

2

2

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

12

12

12

@

@

PC2228

PC2231

PC2232

0.1U_0402_25V6
10U_0805_25V6K

10U_0805_25V6K

EMC_NS@

10U_0805_25V6K

22A

TDC=22A EDC=29A
Voltage=VID_VDDCR_NB-(IDDCR_NB*4.0mȍ)±20m V

1

2

22UC_6.3VC_MC_X5RC_0603

1

PC2285

PC2284

2

22UC_6.3VC_MC_X5RC_0603

undershoot=20mV
overshoot=70mV

1

PC2253

2

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

330U_D2_2V_Y

1

1

PC2282

PC2283

2

2

CD@

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

+APU_CORE

1

1

1

PC2278

PC2277

PC2276

2

2

2

@

@

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

V20B+

1

12

12

PC2207

PC2208

PC2209

2

10U_0805_25V6K

10U_0805_25V6K

EMC_UMA@

18A

1

PC2270

2

22UC_6.3VC_MC_X5RC_0603

0.22U_25V_K_X5R_0402

1

1

+

+

PC2214

PC2215

2

2

330U_D2_2V_Y

330U_D2_2V_Y

1

1

1

PC2272

PC2275

PC2271

2

2

2

CD@

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

TDC=18A EDC=24A
Voltage=VID_VDDCR_NB-(IDDCR_NB*4.0mȍ)±20m V
undershoot=40mV
overshoot=70mV
VDDCR_FCH_S5=VDDCR_NB ±7% in S0

1

1

PC2273

PC2274

2

2

0.22U_6.3V_K_X5R_0402

0.22U_6.3V_K_X5R_0402

EMC@

EMC_DIS@

+APU_CORE_NB

A A

5

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2

2017/03/14

2017/03/14

2017/03/14

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2017/03/14

2017/03/14

2017/03/14

Title

PWR_CPU Core

PWR_CPU Core

PWR_CPU Core

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A1

A1

A1

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

Monday, November 12, 2018

Monday, November 12, 2018

Monday, November 12, 2018

S145AST

S145AST

S145AST

49 50

49 50

49 50

0.2

0.2

0.2

5

Vinafix.com

4

3

2

1

BOARD
Config.

14''

15''

17''

GPU

BOARD_ID0 BOARD_ID3

0

0 1

1 0

0

D D

C C

B B

A A

5

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2013/08/08

2013/08/08

2013/08/08

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2013/08/05

2013/08/05

2013/08/05

2

Title

Virtual symbol

Virtual symbol

Virtual symbol

Siz e Document Number Rev

Siz e Document Number Rev

Siz e Document Number Rev

Custom

Custom

Custom

Monday, November 12, 2018

Monday, November 12, 2018

Monday, November 12, 2018

Date: Shee t of

Date: Shee t of

Date: Shee t of

S145AST

S145AST

S145AST

1

50 50

50 50

50 50

0.2

0.2

0.2