LCFC DY512 schematics

A

1 1

B

C

D

E

LCFC Confidential

DY512 M/B Schematics Document

2 2

Intel Kabylake H-Processor with DDR4 + NV N17P-G0/G1 GPU

MB NM-B191

2016-11-25

3 3

4 4

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

A

B

REV:1.0

Issued Date

Issued Date

Issued Date

2015/02/26

2015/02/26

2015/02/26

C

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2016/02/26

2016/02/26

2016/02/26

D

Title

Title

Title

Cover Page

Cover Page

Cover Page

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Friday, November 25, 2016

Friday, November 25, 2016

Friday, November 25, 2016

DY512

DY512

DY512

E

175

175

175

1.0

1.0

1.0

A

B

C

D

E

NV N17P-G0 40W

NV N17P-G1 50W

1 1

Page 24~29 Page30~33

Typec CONN

Page37

2 2

Int. Camera

Dual DMIC

3 3

VRAM 256/128*32
GDDR5*4 4GB/2GB

HDMI Conn.

eDP Conn
FHD : 15" 1920*1080

Type C controller

RTS5400

SD/MMC

Page39

Page34

Page35

Page 36~37

DMIC

SPK Conn.

Page44

Page34

SATA HDD

Page42

SSD

Optane memory

Page41

CardReader

BH611FJ1LN

Page39

Codec

Realtek ALC3248

Page43

HP&Mic Combo Conn.

PCI-Express 8x Gen3

1GB/s * 8 Total 8GB/s

HDMI level shift
PS8203

eDP x2 Lane

2.7Gb/s * 2 Total 5.4Gb/s

DP Redriver
PS8330B

SATA Port2

PCIe Port9~12

One M.2 CONN

PCIe Port2

IO Board

Page35

DP x4Lane

5.4Gb/s * 4 Total 21.6Gb/s

USB 3.0 1x 5Gbps

USB2.0 1x 480Mbps

SATA Gen3 6Gbps

PCIE 4x Gen3

1GB/s * 4 Total 4GB/s

PCIe 1x Gne1 250MGB/s

USB2.0 1x 480Mbps
HD Audio(24MHz)

TMDS 2.97Gbps

Intel CPU
Kaby Lake-H 45W

BGA-1440
42mm*28mm

Page 5~11

DMI *4
1GB/s * 4 Total 4GB/s

Intel PCH

Kaby Lake-H

FCBGA
23mm*23mm

Page 14~22

LPC(24MHz)

EC
ITE IT8226-LQFP

Page45

Memory BUS (DDR4 non-ECC)
Dual Channel

1.2V DDR4 2400 MT/s

19.2GB/s *2 Total 38.4GB/s

USB Right

USB 3.0 2x 5Gbps

USB 2.0 2x 480Mbps

USB 2.0 1x 480Mbps

USB 2.0 Port2
USB 2.0 Port3

USB Left

PCIe 1x Gne1 250MGB/s

USB 2.0 1x 480Mbps
PCIe 1x Gne1 250MGB/s

SPI BUS(17/33/48MHz)

NGFF Card
WLAN&BT

SPI ROM
8MB

SPI ROM 4MB

TPM
Z32H320TC

Page46

DDR4-SO-DIMM X2

UP TO 8G x 2

USB 3.0 Port1
USB 3.0 Port2

Page43

USB2.0 Port1

LAN Realtek

RTL8111GUL(1000M)

PCIe Port4

PCIe Port3

USB2.0 Port11

Page41

Page18

Page18

Sub-board

Page 12,13

RJ45 Conn.

IO Board

IOBoard (RJ45/USB2.0/Aduiocombo jack)

Battery

Page58

4 4

A

B

Touch Pad Int.KBD

Page46 Page46

Thermal Sensor
Fintek F75303M

Page40

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

C

CPU FAN
GPU FAN

Page40

2015/02/26

2015/02/26

2015/02/26

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

TPBUTTON Board(OnlyforProvence‐5R)

Title

Title

2016/02/26

2016/02/26

2016/02/26

Title

Block Diagram

Block Diagram

Block Diagram

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

C

C

C

Friday, November 25, 2016

Friday, November 25, 2016

Friday, November 25, 2016

Date: Sheet of

Date: Sheet of

Date: Sheet of

DY512

DY512

DY512

E

1.0

1.0

275

275

275

1.0

A

B

C

D

E

Voltage Rails

Power Plane

1 1

State

S0

S3

2 2

S3
Battery only

S5 S4/AC Only

S5 S4
Battery only

S5 S4
AC & Battery
don't exist

3 3

USB2.0 Port table

Port Function

1

Right USB2

Left USB3

2

Left USB3

3

4

TypeC USB2

( O --> Means ON , X --> Means OFF )

+3VALW

B+

+5VALW

+1.0VALW

O

OO O

O

O

O X

O

O

O

XX

XX

+3VALW_PCH

OO

O

O

X

+2.5V

+1.2V

VCCST

O

O

O

X

X

X

+5VS
+3VS
VCCIO
VCCSTG
+0.6VS

CPU_CORE
GFX
VCCSA

+1.8V_AON
+1.8V_MAIN
NVVDD
NVVDDS
+0.95VGS
+1.35VGS

X

X

X

X

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

HSIO port Table

SIGNAL

Port Description

1
2
3

4

5
6
7

8
9

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

USB3#1
USB3#2
USB3#3
USB3#4
USB3#5
USB3#6

USB3#7 / PCIE#1
USB3#8 / PCIE#2
USB3#9 / PCIE#3
USB3#10 / PCIE#4

PCIE#5
PCIE#6
PCIE#7
PCIE#8
PCIE#9 / SATA#0
PCIE#10 / SATA#1

PCIE#11
PCIE#12

PCIE#13 / SATA#0
PCIE#14 / SATA#1
PCIE#15 / SATA#2
PCIE#16 / SATA#3
PCIE#17 / SATA#4
PCIE#18 / SATA#5
PCIE#19 / SATA#6
PCIE#20 / SATA#6

SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

HIGH HIGH HIGH HIGH

HIGH

LOWLOWLOW

HIGHHIGHHIGH

HIGH

HIGH

LOW

LOW

LOW

LOW LOW LOW LOW

ON

ON

ON

ON

ON

ONONON ON

ON

ON

OFF

OFF

OFF

OFF

OFF

LOW

OFF

OFF

OFF

BOM Structure Table

BTO ItemBOM Structure

Function

Left USB3
Left USB3

TypeC USB3

CarderReader(PCIE)

WLAN(PCIE)

LAN(PCIE)

PCIe x4 SSD

HDD(SATA3.0)
HDD cable(SATA3.0) Reserved

@
ME@
TPM@
CD@
EMC@
EMC_NS@
RF@
RF_NS@

OPT@
N16@
N17@

Not stuff
ME part(connector, hole)
For support TPM sku part
Cost down part
EMC part stuff
EMC part Not stuff
RF part stuff
RF part Not stuff

For GPU part
For N16 GPU part
For N17 GPU part

5

Camera

6
7

8
9

10

BT

11
12
13

4 4

14

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND C ONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CEN TER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CEN TER.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CEN TER.

C

2015/02/26

2015/02/26

2015/02/26

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

2016/02/26

2016/02/26

2016/02/26

Title

Notes List

Notes List

Notes List

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

Custom

Custom

Custom

Friday, November 25, 2016

Friday, November 25, 2016

Date: Sheet of

Date: Sheet of

Date: Sheet of

Friday, November 25, 2016

DY512

DY512

DY512

E

375

375

375

1.0

1.0

1.0

5

4

3

2

1

+3.3V_LDO_RTS5400

2.2K

D D

+3VALW

2.2K

EC_SMB_CK0
EC_SMB_DA0

RTS5400

Dual MOS

RTS5400_SM_SCL
RTS5400_SM_SDA

+3VALW
Control

+3VALW_R

Battery JBATT2

2.2K

EC

C C

B B

IT8226

EC_SMB_CK1
EC_SMB_DA1

+3VS

2.2K

EC_SMB_CK2
EC_SMB_DA2

+3VS_AON

2.2K

NV GPU( UV1 )

VGA_SMB_CK2
VGA_SMB_DA2

Dual MOS

+3VS_AON
Control

Change IC PU102
BQ24780SRUYR

+3VALW_PCH

2.2K

PCH( UH1 )

Dual MOS

SML1CLK
SML1DATA

+3VS
Control

Thermal sensor U1
F75303M

SMBUS Control Table

Thermal

VGA

Device

Smart Battery

Charger

SOURCE

+3VALW

IT8226

+3VS

PCH

+3VALW_PCH

0X16

0001 0010 b

2015/02/26

2015/02/26

2015/02/26

V

V XX

+3VGS

X

V

X

+3VALW

V

X

+3VS

X

EC SM Bus2 address

Device

Thermal Sensor F75303M

VGA

PCH

RTS5400

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

DDR1

+3VALW_PCH

PCH

A A

2.2K

PCH_SMBCLK
PCH_SMBDATA

5

+3VS
Control

Dual MOS

+3VS

2.2K

VGA_SMB_CK2
VGA_SMB_DA2

DDR2 WLAN

4

TP

EC_SMB_CK1 IT8226
EC_SMB_DA1

EC_SMB_CK2
EC_SMB_DA2

PCH_SMB_CLK
PCH_SMB_DATA

EC SM Bus1 address

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY O F LC F UTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY O F LC F UTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY O F LC F UTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLO SED TO ANY THIRD P ARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLO SED TO ANY THIRD P ARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

MAY BE USED BY OR DISCLO SED TO ANY THIRD P ARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2

SODIMMBATT IT8586E

X

Address

1001_100xb
0x41(default)
need to update

0xD4

2016/02/26

2016/02/26

2016/02/26

WLAN

Sensor

WiMAX

V

XXX

+3VS

V

XX

+3VS+3VS

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

TP

PCH

Module

X

V

X

+3VALW_PCH

VV

X

+3VALW_PCH

PCH SM Bus address

DDR DIMMA
DDR DIMMB

WLAN

Blank4

Blank4

Blank4

DY512

DY512

DY512

Friday, November 25, 2016

Friday, November 25, 2016

Friday, November 25, 2016

1

charger

V

X

X

AddressDevice

1010 000Xb
1010 010Xb

Rsvd

1.0

1.0

1.0

475

475

475

5

PCIE_CRX_GTX_N[0..7]24
PCIE_CRX_GTX_P[0..7]24

PCIE_CTX_C_GRX_N[0..7] 24

D D

C C

PCIE_CTX_C_GRX_P[0..7] 24

Change PEG from X16 to X8
HLZ SDV 20160510

PCIE_CRX_GTX_P7
PCIE_CRX_GTX_N7

PCIE_CRX_GTX_P6
PCIE_CRX_GTX_N6

PCIE_CRX_GTX_P5
PCIE_CRX_GTX_N5

PCIE_CRX_GTX_P4
PCIE_CRX_GTX_N4

PCIE_CRX_GTX_P3
PCIE_CRX_GTX_N3

PCIE_CRX_GTX_P2
PCIE_CRX_GTX_N2

PCIE_CRX_GTX_P1
PCIE_CRX_GTX_N1

PCIE_CRX_GTX_P0
PCIE_CRX_GTX_N0

PEG_COMP

I7 : SA00007HB20
I5 : SA00007HS10

E25
D25

E24
F24

E23
D23

E22
F22

E21
D21

E20
F20

E19
D19

E18
F18

D17
E17

F16
E16

D15
E15

F14
E14

D13
E13

F12
E12

D11
E11

F10
E10

G2

UC1C

PEG_RXP[0]
PEG_RXN[0]

PEG_RXP[1]
PEG_RXN[1]

PEG_RXP[2]
PEG_RXN[2]

PEG_RXP[3]
PEG_RXN[3]

PEG_RXP[4]
PEG_RXN[4]

PEG_RXP[5]
PEG_RXN[5]

PEG_RXP[6]
PEG_RXN[6]

PEG_RXP[7]
PEG_RXN[7]

PEG_RXP[8]
PEG_RXN[8]

PEG_RXP[9]
PEG_RXN[9]

PEG_RXP[10]
PEG_RXN[10]

PEG_RXP[11]
PEG_RXN[11]

PEG_RXP[12]
PEG_RXN[12]

PEG_RXP[13]
PEG_RXN[13]

PEG_RXP[14]
PEG_RXN[14]

PEG_RXP[15]
PEG_RXN[15]

PEG_RCOMP

4

SKYLAKE_HALO

BGA1440

PEG_TXP[0]
PEG_TXN[0]

PEG_TXP[1]
PEG_TXN[1]

PEG_TXP[2]
PEG_TXN[2]

PEG_TXP[3]
PEG_TXN[3]

PEG_TXP[4]
PEG_TXN[4]

PEG_TXP[5]
PEG_TXN[5]

PEG_TXP[6]
PEG_TXN[6]

PEG_TXP[7]
PEG_TXN[7]

PEG_TXP[8]
PEG_TXN[8]

PEG_TXP[9]
PEG_TXN[9]

PEG_TXP[10]
PEG_TXN[10]

PEG_TXP[11]
PEG_TXN[11]

PEG_TXP[12]
PEG_TXN[12]

PEG_TXP[13]
PEG_TXN[13]

PEG_TXP[14]
PEG_TXN[14]

PEG_TXP[15]
PEG_TXN[15]

B25
A25

B24
C24

B23
A23

B22
C22

B21
A21

B20
C20

B19
A19

B18
C18

A17
B17

C16
B16

A15
B15

C14
B14

A13
B13

C12
B12

A11
B11

C10
B10

Change PEG from X16 to X8
HLZ SDV 20160510

PCIE_CTX_GRX_P7
PCIE_CTX_GRX_N7

PCIE_CTX_GRX_P6
PCIE_CTX_GRX_N6

PCIE_CTX_GRX_P5
PCIE_CTX_GRX_N5

PCIE_CTX_GRX_P4
PCIE_CTX_GRX_N4

PCIE_CTX_GRX_P3
PCIE_CTX_GRX_N3

PCIE_CTX_GRX_P2
PCIE_CTX_GRX_N2

PCIE_CTX_GRX_P1
PCIE_CTX_GRX_N1

PCIE_CTX_GRX_P0
PCIE_CTX_GRX_N0

OPT@

OPT@

OPT@
OPT@

3

1 2

CC24 0.22U_0402_10V6K

1 2

CC8 0.22U_0402_10V6KOPT@

1 2

CC23 0.22U_0402_10V6KOPT@

1 2

CC7 0.22U_0402_10V6KOPT@

1 2

CC22 0.22U_0402_10V6KOPT@

1 2

CC6 0.22U_0402_10V6KOPT@

1 2

CC21 0.22U_0402_10V6K

1 2

CC5 0.22U_0402_10V6KOPT@

1 2

CC20 0.22U_0402_10V6KOPT@

1 2

CC4 0.22U_0402_10V6KOPT@

1 2

CC19 0.22U_0402_10V6KOPT@

1 2

CC3 0.22U_0402_10V6KOPT@

1 2

CC18 0.22U_0402_10V6K

1 2

CC2 0.22U_0402_10V6K

1 2

CC17 0.22U_0402_10V6KOPT@

1 2

CC1 0.22U_0402_10V6KOPT@

PCIE_CTX_C_GRX_P7
PCIE_CTX_C_GRX_N7

PCIE_CTX_C_GRX_P6
PCIE_CTX_C_GRX_N6

PCIE_CTX_C_GRX_P5
PCIE_CTX_C_GRX_N5

PCIE_CTX_C_GRX_P4
PCIE_CTX_C_GRX_N4

PCIE_CTX_C_GRX_P3
PCIE_CTX_C_GRX_N3

PCIE_CTX_C_GRX_P2
PCIE_CTX_C_GRX_N2

PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_N1

PCIE_CTX_C_GRX_P0
PCIE_CTX_C_GRX_N0

2

PEG_COMP

CAD Note:
Trac ewidth=12mils,Spacing=15mil
Maxlength=400mils.

1 2

RC1 24.9_0402_1%

1

VCCIO

DMI_CRX_PTX_P019
DMI_CRX_PTX_N019

B B

A A

DMI_CRX_PTX_P119
DMI_CRX_PTX_N119

DMI_CRX_PTX_P219
DMI_CRX_PTX_N219

DMI_CRX_PTX_P319
DMI_CRX_PTX_N319

5

DMI_CRX_PTX_P0
DMI_CRX_PTX_N0

DMI_CRX_PTX_P1
DMI_CRX_PTX_N1

DMI_CRX_PTX_P2
DMI_CRX_PTX_N2

DMI_CRX_PTX_P3
DMI_CRX_PTX_N3

D8

DMI_RXP[0]

E8

DMI_RXN[0]

E6

DMI_RXP[1]

F6

DMI_RXN[1]

D5

DMI_RXP[2]

E5

DMI_RXN[2]

J8

DMI_RXP[3]

J9

DMI_RXN[3]

SKYLAKE-H-CPU_BGA1440

@

4

3 OF 14

DMI_TXP[0]

DMI_TXN[0]

DMI_TXP[1]

DMI_TXN[1]

DMI_TXP[2]

DMI_TXN[2]

DMI_TXP[3]

DMI_TXN[3]

B8
A8

C6
B6

B5
A5

D4
B4

DMI_CTX_PRX_P0
DMI_CTX_PRX_N0

DMI_CTX_PRX_P1
DMI_CTX_PRX_N1

DMI_CTX_PRX_P2
DMI_CTX_PRX_N2

DMI_CTX_PRX_P3
DMI_CTX_PRX_N3

DMI_CTX_PRX_P0 19
DMI_CTX_PRX_N0 19

DMI_CTX_PRX_P1 19
DMI_CTX_PRX_N1 19

DMI_CTX_PRX_P2 19
DMI_CTX_PRX_N2 19

DMI_CTX_PRX_P3 19
DMI_CTX_PRX_N3 19

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND C ONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CEN TER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CEN TER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CEN TER.

3

2015/02/26

2015/02/26

2015/02/26

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/02/26

2016/02/26

2016/02/26

Title

Title

Title

CPU (1/7) DMI,PEG

CPU (1/7) DMI,PEG

CPU (1/7) DMI,PEG

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

Custom

Custom

Custom

Friday, November 25, 2016

Friday, November 25, 2016

Date: Sheet of

Date: Sheet of

Date: Sheet of

Friday, November 25, 2016

DY512

DY512

DY512

1

575

575

575

1.0

1.0

1.0

5

VCCST

1 2

RC11 1K_0402_5%

1 2

RC174 10K_0402_5%@

D D

56.2_0402_1%

SVID_ALERT#65
SVID_CLK65
SVID_DATA65

C C

DDR_PG_CTRL

RC179
10K_0402_5%

@

1 2

B B

CPUCORE_ON49,65

A A

H_THRMTRIP#_R

H_CATERR#

VCCST

12

RC76

RC66

100_0402_1%

1 2

1 2

RC65 220_0402_5%

1 2

RC3 0_0402_5%

1 2

RC14 0_0402_5%

+1.2V

Add RC184 HLZ SIV 0811

12

RC184

1K_0402_5%

B

2

E

3 1

C

QC1
MMBT3904WH_SOT323-3

+3VS

R292

10K_0402_5%

@

1 2

Q1

2

G

1 2

C120 .1U_0402_10V6-K@

1 2

C52 .1U_0402_10V6-K

1 2

C126 .1U_0402_10V6-K@

1 2

C127 .1U_0402_10V6-K

1 2

C133 .1U_0402_10V6-K@

1 2

C128 .1U_0402_10V6-K@

1

C925
.1U_0402_10V6-K

@

2

+3VALW

RC177

1 2

+3VALW

1 2

13

D

S

@

100K_0402_5%

SM_PG_CTRL

R291

10K_0402_5%

2

2N7002KW_SOT323-3

H_PROCHOT#_R
H_CPUPWRGD
H_THRMTRIP#
BUF_CPU_RST#
H_PM_SYNC
CPU_TRIGIN

PCH_CPU_BCLK17
PCH_CPU_BCLK#17

PCH_CPU_PCIBCLK17
PCH_CPU_PCIBCLK#17

PCH_CPU_NSSC_CLK17
PCH_CPU_NSSC_CLK#17

RC178

100K_0402_5%

CPU_TRIGIN22
PCH_TRIGIN22

VCCST

12

RC75
1K_0402_5%

RC50

13

D

S

2N7002KW_SOT323-3

H_PROCHOT#49,65

H_CPUPWRGD16

CPU_PLTRST#14

H_PM_SYNC14

H_PM_DOWN14

EC_PECI14,49

H_THRMTRIP#14,24

SM_PG_CTRL 61

1 2

VR_SVID_ALRT#_R
VR_SVID_CLK
VR_SVID_DAT

+3VS

1 2

Q2

G

Change C52&C127 from @ to stuff HLZ SIV 0811

VCCST

PCH_TRIGIN

60.4_0402_1%

4

RC28

1 2
1 2

1 2
1 2

1 2
1 2

1K_0402_5%

1 2

RC9

499_0402_1%

1 2
1 2

1 2
1 2

1 2

30_0402_1%

VCCST_PWRGD

C929
330P_0402_50V8J

0_0402_5%
0_0402_5%

0_0402_5%

0_0402_5%

TC100
TC101
TC102
TC103

TC104
TC105

RC29
RC15

RC13 0_0402_5%
RC17

RC16 0_0402_5%

12

RC7

RC32 0_0402_5%
RC22 0_0402_5%

RC33 20_0402_1%
RC34 0_0402_5%

RC4

12

Add C929 HLZ SIV 0811

CPU_BCLK
CPU_BCLK#

CPU_PCIBCLK
CPU_PCIBCLK#

CPU_NSSC_CLK
CPU_NSSC_CLK#

VR_SVID_ALRT#_R
VR_SVID_CLK
VR_SVID_DAT
H_PROCHOT#_R

DDR_PG_CTRL

VCCST_PWRGD
VCCPWRGOOD_0_R

BUF_CPU_RST#
H_PM_SYNC
H_PM_DOWN_R
EC_PECI
H_THRMTRIP#_R

H_CATERR#

1

PAD @

1

PAD @

1

PAD @

1

PAD @

1

PAD @

1

PAD @

CPU_TRIGIN
CPU_TRIGOUT

UC1E

B31

BCLKP

A32

BCLKN

D35

PCI_BCLKP

C36

PCI_BCLKN

E31

CLK24P

D31

CLK24N

BH31

VIDALERT#

BH32

VIDSCK

BH29

VIDSOUT

BR30

PROCHOT#

BT13

DDR_VTT_CNTL

H13

VCCST_PWRGD

BT31

PROCPWRGD

BP35

RESET#

BM34

PM_SYNC

BP31

PM_DOWN

BT34

PECI

J31

THERMTRIP#

BR33

SKTOCC#

BN1

PROC_SELECT#

BM30

CATERR#

SKYLAKE-H-CPU_BGA1440

@

UC1K

D1

RSVD_TP_1

E1

RSVD_TP_2

E3

RSVD_TP_3

E2

RSVD_TP_4

BR1

RSVD_TP_5

BT2

RSVD_TP_6

BN35

RSVD_23

J24

RSVD_24

H24

RSVD_25

BN33

RSVD_26

BL34

RSVD_27

N29

RSVD_28

R14

RSVD_29

AE29

RSVD_30

AA14

RSVD_31

A36

RSVD_32

A37

RSVD_33

H23

PROC_TRIGIN

J23

PROC_TRIGOUT

F30

RSVD_34

E30

RSVD_35

B30

RSVD_36

C30

RSVD_37

G3

RSVD_38

J3

RSVD_39

BR35

RSVD_40

BR31

RSVD_41

BH30

RSVD_42

SKYLAKE-H-CPU_BGA1440

@

1K_0402_1%

XDP_PREQ#

RC57

VCCST

12

@

3

SKYLAKE_HALO

BGA1440

5 OF 14

SKYLAKE_HALO

BGA1440

11 OF 14

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]

CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]

CFG[17]
CFG[16]
CFG[19]
CFG[18]

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]

PROC_TDO

PROC_TDI
PROC_TMS
PROC_TCK

PROC_TRST#
PROC_PREQ#
PROC_PRDY#

CFG_RCOMP

12

BN25
BN27
BN26
BN28
BR20
BM20
BT20
BP20
BR23
BR22
BT23
BT22
BM19
BR19
BP19
BT19

BN23
BP23
BP22
BN22

BR27
BT27
BM31
BT30

BT28
BL32
BP28
BR28

BP30
BL30
BP27

BT25

RSVD_TP_7
RSVD_TP_8

RSVD_TP_9

RSVD_TP_10

RSVD_43
RSVD_44

VSS_447

RSVD_TP_11
RSVD_TP_12

RSVD_TP_13
RSVD_TP_14

RSVD_45
RSVD_46

RSVD_47
RSVD_48

VSS_448

RSVD_TP_15
RSVD_TP_16

RSVD_49
RSVD_50
RSVD_51

NCTF_1
NCTF_2
NCTF_3
NCTF_4
NCTF_5
NCTF_6

CFG1

RC146
1K_0402_5%

@

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15

RC175

49.9_0402_1%

BM33
BL33

BJ14
BJ13

BK28
BJ28

BJ18
BJ16

BK16

BK24
BJ24

BK21
BJ21

BT17
BR17

BK18
BJ34

BJ33

G13
AJ8
BL31

B2
B38
BP1
BR2
C1
C38

2

1

PAD@

TC89

CFG3 42

1

PAD@

TC77

1

PAD@

TC78

1

PAD@

TC79

1

PAD@

TC80

1

PAD@

TC81

1

PAD@

TC82

1

PAD@

TC83

1

PAD@

TC84

1

PAD@

TC85

1

PAD@

TC86

1

PAD@

TC87

1

PAD@

TC88

1

PAD@

TC27

1

PAD@

TC28

1

PAD@

TC29

1

PAD@

TC42

XDP_TDO 42

XDP_TDI 42
XDP_TMS 42
XDP_TCK 42

XDP_TRST# 42
XDP_PREQ# 42

XDP_PRDY# 42

RC176
51_0402_1%

20150527_Mount

1 2

1 2

RC176 to enable
DCI function

1

PAD@

TC90

1

PAD@

TC91

1

PAD@

TC92

1

PAD@

TC93

1

PAD@

TC94

1

PAD@

TC95

1

PAD@

TC96

1

PAD@

TC97

1

PAD@

TC98

1

PAD@

TC99

VCCIO

CFG7
CFG6
CFG5
CFG4
CFG2
CFG0

CFGSTRAPSforCPU(InternalPH)

Stall reset sequence after PCU PLL lock until de-asserted

1 = (Default) Normal Operation; No stall.

CFG0

0 = Stall.

12

12

RC139
1K_0402_5%

@

RC56
1K_0402_5%

@

Reserved configuration lane

N/A

CFG1

PCI Express* Static x16 Lane Numbering Reversal

1 = Normal operation

CFG2

0 = Lane reserval

Reserved configuration lane

N/A

CFG3

eDP enabl

e

1 = Disabled.

CFG4

0 = Enable

PCI Express* Bifurcatio

00 = 1 x8, 2 x4 PCI Express*

01 = reserved

CFG[6:5]

10 = 2 x8 PCI Express*

11 = 1 x16 PCI Express*

PEG Trainin

CFG7

Reserved configuration lane

CFG[19:8]

12

RC140
1K_0402_5%

@

12

RC53
1K_0402_5%

g

1 = (default) PEG Train immediately
following RESET# deassertion.

0 = PEG Wait for BIOS for training.

N/A

12

RC141
1K_0402_5%

@

12

RC54
1K_0402_5%

12

12

n

RC142
1K_0402_5%

@

RC52
1K_0402_5%

@

.

.

.

12

12

RC143
1K_0402_5%

@

RC51
1K_0402_5%

@

1

12

12

.

RC144
1K_0402_5%

@

RC55
1K_0402_5%

@

Reserved Cap HLZ SDV 0616

5

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2015/02/26

2015/02/26

2015/02/26

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/02/26

2016/02/26

2016/02/26

Title

CPU (2/7) PM, XDP, CLK, CFG

CPU (2/7) PM, XDP, CLK, CFG

CPU (2/7) PM, XDP, CLK, CFG

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

C

C

C

Friday, November 25, 2016

Friday, November 25, 2016

Friday, November 25, 2016

Date: Sheet of

Date: Sheet of

Date: Sheet of

DY512

DY512

DY512

1

675

675

675

1.0

1.0

1.0

5

4

3

2

1

SKYLAKE_HALO

BGA1440

1 OF 14

DDR0_DQ[16]/DDR0_DQ[32]
DDR0_DQ[17]/DDR0_DQ[33]
DDR0_DQ[18]/DDR0_DQ[34]
DDR0_DQ[19]/DDR0_DQ[35]
DDR0_DQ[20]/DDR0_DQ[36]
DDR0_DQ[21]/DDR0_DQ[37]
DDR0_DQ[22]/DDR0_DQ[38]
DDR0_DQ[23]/DDR0_DQ[39]
DDR0_DQ[24]/DDR0_DQ[40]
DDR0_DQ[25]/DDR0_DQ[41]
DDR0_DQ[26]/DDR0_DQ[42]
DDR0_DQ[27]/DDR0_DQ[43]
DDR0_DQ[28]/DDR0_DQ[44]
DDR0_DQ[29]/DDR0_DQ[45]
DDR0_DQ[30]/DDR0_DQ[46]
DDR0_DQ[31]/DDR0_DQ[47]

DDR0_DQ[32]/DDR1_DQ[0]
DDR0_DQ[33]/DDR1_DQ[1]
DDR0_DQ[34]/DDR1_DQ[2]
DDR0_DQ[35]/DDR1_DQ[3]
DDR0_DQ[36]/DDR1_DQ[4]
DDR0_DQ[37]/DDR1_DQ[5]
DDR0_DQ[38]/DDR1_DQ[6]
DDR0_DQ[39]/DDR1_DQ[7]
DDR0_DQ[40]/DDR1_DQ[8]

DDR0_DQ[41]/DDR1_DQ[9]
DDR0_DQ[42]/DDR1_DQ[10]
DDR0_DQ[43]/DDR1_DQ[11]
DDR0_DQ[44]/DDR1_DQ[12]
DDR0_DQ[45]/DDR1_DQ[13]
DDR0_DQ[46]/DDR1_DQ[14]
DDR0_DQ[47]/DDR1_DQ[15]
DDR0_DQ[48]/DDR1_DQ[32]
DDR0_DQ[49]/DDR1_DQ[33]
DDR0_DQ[50]/DDR1_DQ[34]
DDR0_DQ[51]/DDR1_DQ[35]
DDR0_DQ[52]/DDR1_DQ[36]
DDR0_DQ[53]/DDR1_DQ[37]
DDR0_DQ[54]/DDR1_DQ[38]
DDR0_DQ[55]/DDR1_DQ[39]
DDR0_DQ[56]/DDR1_DQ[40]
DDR0_DQ[57]/DDR1_DQ[41]
DDR0_DQ[58]/DDR1_DQ[42]
DDR0_DQ[59]/DDR1_DQ[43]
DDR0_DQ[60]/DDR1_DQ[44]
DDR0_DQ[61]/DDR1_DQ[45]
DDR0_DQ[62]/DDR1_DQ[46]
DDR0_DQ[63]/DDR1_DQ[47]

SKYLAKE-H-CPU_BGA1440

DDRA_ODT0
DDRA_ODT1

DDRA_MA0
DDRA_MA1
DDRA_MA2
DDRA_MA3
DDRA_MA4
DDRA_MA5
DDRA_MA6
DDRA_MA7
DDRA_MA8
DDRA_MA9
DDRA_MA10_AP
DDRA_MA11
DDRA_MA12
DDRA_MA13
DDRA_BG1
DDRA_ACT#

DDRA_PARITY
DDRA_ALERT#

DDRA_DQS#0
DDRA_DQS#1
DDRA_DQS#2
DDRA_DQS#3
DDRA_DQS4
DDRA_DQS5
DDRA_DQS6
DDRA_DQS7

DDRA_DQS0
DDRA_DQS1
DDRA_DQS2
DDRA_DQS3
DDRA_DQS#4
DDRA_DQS#5
DDRA_DQS#6
DDRA_DQS#7

AG1

DDR0_CKP[0]

AG2

DDR0_CKN[0]

AK1

DDR0_CKN[1]

AK2

DDR0_CKP[1]

AL3

DDR0_CLKP[2]

AK3

DDR0_CLKN[2]

AL2

DDR0_CLKP[3]

AL1

DDR0_CLKN[3]

AT1

DDR0_CKE[0]

AT2

DDR0_CKE[1]

AT3

DDR0_CKE[2]

AT5

DDR0_CKE[3]

AD5

DDR0_CS#[0]

AE2

DDR0_CS#[1]

AD2

DDR0_CS#[2]

AE5

DDR0_CS#[3]

AD3

DDR0_ODT[0]

AE4

DDR0_ODT[1]

AE1

DDR0_ODT[2]

AD4

DDR0_ODT[3]

AH5

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

AH1

DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]

AU1

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]

AH4

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

AG4

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

AD1

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

AH3

DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]

AP4

DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]

AN4

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

AP5

DDR0_MA[3]

AP2

DDR0_MA[4]

AP1

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]

AP3

DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]

AN1

DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]

AN3

DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]

AT4

DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]

AH2

DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]

AN2

DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]

AU4

DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]

AE3

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

AU2

DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

AU3

DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#

AG3

DDR0_PAR

AU5

DDR0_ALERT#

BR5

DDR0_DQSN[0]

BL3

DDR0_DQSN[1]

BG3

DDR0_DQSN[2]/DDR0_DQSN[4]

BD3

DDR0_DQSN[3]/DDR0_DQSN[5]

AB3

DDR0_DQSP[4]/DDR1_DQSP[0]

V3

DDR0_DQSP[5]/DDR1_DQSP[1]

R3

DDR0_DQSP[6]/DDR1_DQSP[4]

M3

DDR0_DQSP[7]/DDR1_DQSP[5]

BP5

DDR0_DQSP[0]

BK3

DDR0_DQSP[1]

BF3

DDR0_DQSP[2]/DDR0_DQSP[4]

BC3

DDR0_DQSP[3]/DDR0_DQSP[5]

AA3

DDR0_DQSN[4]/DDR1_DQSN[0]

U3

DDR0_DQSN[5]/DDR1_DQSN[1]

P3

DDR0_DQSN[6]/DDR1_DQSN[4]

L3

DDR0_DQSN[7]/DDR1_DQSN[5]

AY3

DDR0_DQSP[8]

BA3

DDR0_DQSN[8]

@

DDRA_CLK012
DDRA_CLK0#12
DDRA_CLK1#12
DDRA_CLK112

D D

C C

B B

DDRA_CKE012
DDRA_CKE112

DDRA_CS0#12
DDRA_CS1#12

DDRA_ODT012
DDRA_ODT112

DDRA_BA012
DDRA_BA112
DDRA_BG012

DDRA_MA16_RAS#12
DDRA_MA14_WE#12
DDRA_MA15_CAS#12

DDRA_MA[0..9]12

DDRA_MA10_AP12
DDRA_MA1112
DDRA_MA1212
DDRA_MA1312
DDRA_BG112
DDRA_ACT#12

DDRA_PARITY12
DDRA_ALERT#12

DDRA_DQS#[0..7] 12
DDRA_DQS[0..7] 12

DDR0_DQ[0]
DDR0_DQ[1]
DDR0_DQ[2]
DDR0_DQ[3]
DDR0_DQ[4]
DDR0_DQ[5]
DDR0_DQ[6]
DDR0_DQ[7]
DDR0_DQ[8]

DDR0_DQ[9]
DDR0_DQ[10]
DDR0_DQ[11]
DDR0_DQ[12]
DDR0_DQ[13]
DDR0_DQ[14]
DDR0_DQ[15]

DDR0_ECC[0]
DDR0_ECC[1]
DDR0_ECC[2]
DDR0_ECC[3]
DDR0_ECC[4]
DDR0_ECC[5]
DDR0_ECC[6]
DDR0_ECC[7]

DDR CHANNEL

A

UC1A

DDRA_DQ0

BR6

DDRA_DQ1

BT6

DDRA_DQ2

BP3

DDRA_DQ3

BR3

DDRA_DQ4

BN5

DDRA_DQ5

BP6

DDRA_DQ6

BP2

DDRA_DQ7

BN3

DDRA_DQ8

BL4

DDRA_DQ9

BL5

DDRA_DQ10

BL2

DDRA_DQ11

BM1

DDRA_DQ12

BK4

DDRA_DQ13

BK5

DDRA_DQ14

BK1

DDRA_DQ15

BK2

DDRA_DQ16

BG4

DDRA_DQ17

BG5

DDRA_DQ18

BF4

DDRA_DQ19

BF5

DDRA_DQ20

BG2

DDRA_DQ21

BG1

DDRA_DQ22

BF1

DDRA_DQ23

BF2

DDRA_DQ24

BD2

DDRA_DQ25

BD1

DDRA_DQ26

BC4

DDRA_DQ27

BC5

DDRA_DQ28

BD5

DDRA_DQ29

BD4

DDRA_DQ30

BC1

DDRA_DQ31

BC2

DDRA_DQ32

AB1

DDRA_DQ33

AB2

DDRA_DQ34

AA4

DDRA_DQ35

AA5

DDRA_DQ36

AB5

DDRA_DQ37

AB4

DDRA_DQ38

AA2

DDRA_DQ39

AA1

DDRA_DQ40

V5

DDRA_DQ41

V2

DDRA_DQ42

U1

DDRA_DQ43

U2

DDRA_DQ44

V1

DDRA_DQ45

V4

DDRA_DQ46

U5

DDRA_DQ47

U4

DDRA_DQ48

R2

DDRA_DQ49

P5

DDRA_DQ50

R4

DDRA_DQ51

P4

DDRA_DQ52

R5

DDRA_DQ53

P2

DDRA_DQ54

R1

DDRA_DQ55

P1

DDRA_DQ56

M4

DDRA_DQ57

M1

DDRA_DQ58

L4

DDRA_DQ59

L2

DDRA_DQ60

M5

DDRA_DQ61

M2

DDRA_DQ62

L5

DDRA_DQ63

L1
BA2

BA1
AY4
AY5
BA5
BA4
AY1
AY2

+VREF_CA_DIMMA_R

PAD

TC109

@

+VREF_DQ_DIMMB_R

DDRA_DQ[0..63] 12

+VREF_DQ_DIMM_R +V_DDR_REF_R

1

CAD Note:
Trace width=20mil,Spcing=20mils

DDR_VREF_CA : Connected to VREF_CA on DIMM CH-A
DDR0_VREF_DQ : NC
DDR1_VREF_DQ : Connected to VREF_CA on DIMM CH-B

DDRB_CLK013
DDRB_CLK0#13
DDRB_CLK1#13
DDRB_CLK113

DDRB_CKE013
DDRB_CKE113

DDRB_CS0#13
DDRB_CS1#13

DDRB_ODT013
DDRB_ODT113

DDRB_MA16_RAS#13
DDRB_MA14_WE#13
DDRB_MA15_CAS#13

DDRB_BA013
DDRB_BA113
DDRB_BG013
DDRB_MA[0..9]13

DDRB_MA10_AP13
DDRB_MA1113
DDRB_MA1213
DDRB_MA1313
DDRB_BG113
DDRB_ACT#13

DDRB_PARITY13
DDRB_ALERT#13

DDRB_DQS#[0..7]13

DDRB_DQS[0..7]13

RC147

1 2

0_0402_5%

1 2

RC36 0_0402_5%
RC37

1 2

0_0402_5%

+V_DDR_REFA_R

@

+V_DDR_REFB_R

DDRB_MA0
DDRB_MA1
DDRB_MA2
DDRB_MA3
DDRB_MA4
DDRB_MA5
DDRB_MA6
DDRB_MA7
DDRB_MA8
DDRB_MA9
DDRB_MA10_AP
DDRB_MA11
DDRB_MA12
DDRB_MA13
DDRB_BG1
DDRB_ACT#

DDRB_PARITY
DDRB_ALERT#

DDRB_DQS#0
DDRB_DQS#1
DDRB_DQS#2
DDRB_DQS#3
DDRB_DQS#4
DDRB_DQS#5
DDRB_DQS#6
DDRB_DQS#7

DDRB_DQS0
DDRB_DQS1
DDRB_DQS2
DDRB_DQS3
DDRB_DQS4
DDRB_DQS5
DDRB_DQS6
DDRB_DQS7

DDRB_ODT0
DDRB_ODT1

AM9

DDR1_CKP[0]

AN9

DDR1_CKN[0]

AM8

DDR1_CKN[1]

AM7

DDR1_CKP[1]

AM11

DDR1_CLKP[2]

AM10

DDR1_CLKN[2]

AJ10

DDR1_CLKP[3]

AJ11

DDR1_CLKN[3]

AT8

DDR1_CKE[0]

AT10

DDR1_CKE[1]

AT7

DDR1_CKE[2]

AT11

DDR1_CKE[3]

AF11

DDR1_CS#[0]

AE7

DDR1_CS#[1]

AF10

DDR1_CS#[2]

AE10

DDR1_CS#[3]

AF7

DDR1_ODT[0]

AE8

DDR1_ODT[1]

AE9

DDR1_ODT[2]

AE11

DDR1_ODT[3]

AH10

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

AH11

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

AF8

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

AH8

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]

AH9

DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]

AR9

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]

AJ9

DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]

AK6

DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]

AK5

DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

AL5

DDR1_MA[3]

AL6

DDR1_MA[4]

AM6

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]

AN7

DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]

AN10

DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]

AN8

DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]

AR11

DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]

AH7

DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]

AN11

DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]

AR10

DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]

AF9

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

AR7

DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

AT9

DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#

AJ7

DDR1_PAR

AR8

DDR1_ALERT#

BP9

DDR1_DQSN[0]/DDR0_DQSN[2]

BL9

DDR1_DQSN[1]/DDR0_DQSN[3]

BG9

DDR1_DQSN[2]/DDR0_DQSN[6]

BC9

DDR1_DQSN[3]/DDR0_DQSN[7]

AC9

DDR1_DQSN[4]/DDR1_DQSN[2]

W9

DDR1_DQSN[5]/DDR1_DQSN[3]

R9

DDR1_DQSN[6]

M9

DDR1_DQSN[7]

BR9

DDR1_DQSP[0]/DDR0_DQSP[2]

BJ9

DDR1_DQSP[1]/DDR0_DQSP[3]

BF9

DDR1_DQSP[2]/DDR0_DQSP[6]

BB9

DDR1_DQSP[3]/DDR0_DQSP[7]

AA9

DDR1_DQSP[4]/DDR1_DQSP[2]

V9

DDR1_DQSP[5]/DDR1_DQSP[3]

P9

DDR1_DQSP[6]

L9

DDR1_DQSP[7]

AW9

DDR1_DQSP[8]

AY9

DDR1_DQSN[8]

BN13

DDR_VREF_CA

BP13

DDR0_VREF_DQ

BR13

DDR1_VREF_DQ

@

SKYLAKE_HALO

BGA1440

DDR1_DQ[0]/DDR0_DQ[16]
DDR1_DQ[1]/DDR0_DQ[17]
DDR1_DQ[2]/DDR0_DQ[18]
DDR1_DQ[3]/DDR0_DQ[19]
DDR1_DQ[4]/DDR0_DQ[20]
DDR1_DQ[5]/DDR0_DQ[21]
DDR1_DQ[6]/DDR0_DQ[22]
DDR1_DQ[7]/DDR0_DQ[23]
DDR1_DQ[8]/DDR0_DQ[24]

DDR1_DQ[9]/DDR0_DQ[25]
DDR1_DQ[10]/DDR0_DQ[26]
DDR1_DQ[11]/DDR0_DQ[27]
DDR1_DQ[12]/DDR0_DQ[28]
DDR1_DQ[13]/DDR0_DQ[29]
DDR1_DQ[14]/DDR0_DQ[30]
DDR1_DQ[15]/DDR0_DQ[31]
DDR1_DQ[16]/DDR0_DQ[48]
DDR1_DQ[17]/DDR0_DQ[49]
DDR1_DQ[18]/DDR0_DQ[50]
DDR1_DQ[19]/DDR0_DQ[51]
DDR1_DQ[20]/DDR0_DQ[52]
DDR1_DQ[21]/DDR0_DQ[53]
DDR1_DQ[22]/DDR0_DQ[54]
DDR1_DQ[23]/DDR0_DQ[55]
DDR1_DQ[24]/DDR0_DQ[56]
DDR1_DQ[25]/DDR0_DQ[57]
DDR1_DQ[26]/DDR0_DQ[58]
DDR1_DQ[27]/DDR0_DQ[59]
DDR1_DQ[28]/DDR0_DQ[60]
DDR1_DQ[29]/DDR0_DQ[61]
DDR1_DQ[30]/DDR0_DQ[62]
DDR1_DQ[31]/DDR0_DQ[63]
DDR1_DQ[32]/DDR1_DQ[16]
DDR1_DQ[33]/DDR1_DQ[17]
DDR1_DQ[34]/DDR1_DQ[18]
DDR1_DQ[35]/DDR1_DQ[19]
DDR1_DQ[36]/DDR1_DQ[20]
DDR1_DQ[37]/DDR1_DQ[21]
DDR1_DQ[38]/DDR1_DQ[22]
DDR1_DQ[39]/DDR1_DQ[23]
DDR1_DQ[40]/DDR1_DQ[24]
DDR1_DQ[41]/DDR1_DQ[25]
DDR1_DQ[42]/DDR1_DQ[26]
DDR1_DQ[43]/DDR1_DQ[27]
DDR1_DQ[44]/DDR1_DQ[28]
DDR1_DQ[45]/DDR1_DQ[29]
DDR1_DQ[46]/DDR1_DQ[30]
DDR1_DQ[47]/DDR1_DQ[31]

DDR1_DQ[48]
DDR1_DQ[49]
DDR1_DQ[50]
DDR1_DQ[51]
DDR1_DQ[52]
DDR1_DQ[53]
DDR1_DQ[54]
DDR1_DQ[55]
DDR1_DQ[56]
DDR1_DQ[57]
DDR1_DQ[58]
DDR1_DQ[59]
DDR1_DQ[60]
DDR1_DQ[61]
DDR1_DQ[62]
DDR1_DQ[63]

DDR1_ECC[0]
DDR1_ECC[1]
DDR1_ECC[2]
DDR1_ECC[3]
DDR1_ECC[4]
DDR1_ECC[5]
DDR1_ECC[6]
DDR1_ECC[7]

DDR CHANNEL B

DDR_RCOMP[0]

2 OF 14

DDR_RCOMP[1]
DDR_RCOMP[2]

SKYLAKE-H-CPU_BGA1440

DDR4 COMPENSATIONSIGNALS

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

CAD Note:
Trace width=12~15mil,Spcing=20mils
Maxtracelength=500mil

1 2

RC5 121_0402_1%

1 2

RC6 75_0402_1%

1 2

RC8 100_0402_1%

UC1B

BT11
BR11
BT8
BR8
BP11
BN11
BP8
BN8
BL12
BL11
BL8
BJ8
BJ11
BJ10
BL7
BJ7
BG11
BG10
BG8
BF8
BF11
BF10
BG7
BF7
BB11
BC11
BB8
BC8
BC10
BB10
BC7
BB7
AA11
AA10
AC11
AC10
AA7
AA8
AC8
AC7
W8
W7
V10
V11
W11
W10
V7
V8
R11
P11
P7
R8
R10
P10
R7
P8
L11
M11
L7
M8
L10
M10
M7
L8

AW11
AY11
AY8
AW8
AY10
AW10
AY7
AW7

G1
H1
J2

DDRB_DQ0
DDRB_DQ1
DDRB_DQ2
DDRB_DQ3
DDRB_DQ4
DDRB_DQ5
DDRB_DQ6
DDRB_DQ7
DDRB_DQ8
DDRB_DQ9
DDRB_DQ10
DDRB_DQ11
DDRB_DQ12
DDRB_DQ13
DDRB_DQ14
DDRB_DQ15
DDRB_DQ16
DDRB_DQ17
DDRB_DQ18
DDRB_DQ19
DDRB_DQ20
DDRB_DQ21
DDRB_DQ22
DDRB_DQ23
DDRB_DQ24
DDRB_DQ25
DDRB_DQ26
DDRB_DQ27
DDRB_DQ28
DDRB_DQ29
DDRB_DQ30
DDRB_DQ31
DDRB_DQ32
DDRB_DQ33
DDRB_DQ34
DDRB_DQ35
DDRB_DQ36
DDRB_DQ37
DDRB_DQ38
DDRB_DQ39
DDRB_DQ40
DDRB_DQ41
DDRB_DQ42
DDRB_DQ43
DDRB_DQ44
DDRB_DQ45
DDRB_DQ46
DDRB_DQ47
DDRB_DQ48
DDRB_DQ49
DDRB_DQ50
DDRB_DQ51
DDRB_DQ52
DDRB_DQ53
DDRB_DQ54
DDRB_DQ55
DDRB_DQ56
DDRB_DQ57
DDRB_DQ58
DDRB_DQ59
DDRB_DQ60
DDRB_DQ61
DDRB_DQ62
DDRB_DQ63

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

DDRB_DQ[0..63] 13

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2015/02/26

2015/02/26

2015/02/26

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/02/26

2016/02/26

2016/02/26

Title

CPU (3/7) DDRVI

CPU (3/7) DDRVI

CPU (3/7) DDRVI

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

C

C

C

Friday, November 25, 2016

Friday, November 25, 2016

Friday, November 25, 2016

Date: Sheet of

Date: Sheet of

Date: Sheet of

DY512

DY512

DY512

1

775

775

775

1.0

1.0

1.0

5

4

3

2

1

D D

HDMI D2
HDMI D1
HDMI D0
HDMI CLK

Different to Y710
HLZ SDV 20160510

Type C DP

C C

HDMI_TX2+36
HDMI_TX2-36
HDMI_TX1+36
HDMI_TX1-36
HDMI_TX0+36
HDMI_TX0-36
HDMI_TXC+36
HDMI_TXC-36

TYPE-C_DP_TXP037
TYPE-C_DP_TXN037
TYPE-C_DP_TXP137
TYPE-C_DP_TXN137
TYPE-C_DP_TXP237
TYPE-C_DP_TXN237
TYPE-C_DP_TXP337
TYPE-C_DP_TXN337

TYPE-C_DP_AUXP37
TYPE-C_DP_AUXN37

HDMI_TX2+
HDMI_TX2­HDMI_TX1+
HDMI_TX1­HDMI_TX0+
HDMI_TX0­HDMI_TXC+
HDMI_TXC-

TYPE-C_DP_TXP0
TYPE-C_DP_TXN0
TYPE-C_DP_TXP1
TYPE-C_DP_TXN1
TYPE-C_DP_TXP2
TYPE-C_DP_TXN2
TYPE-C_DP_TXP3
TYPE-C_DP_TXN3

TYPE-C_DP_AUXP
TYPE-C_DP_AUXN

UC1D

K36

DDI1_TXP[0]

K37

DDI1_TXN[0]

J35

DDI1_TXP[1]

J34

DDI1_TXN[1]

H37

DDI1_TXP[2]

H36

DDI1_TXN[2]

J37

DDI1_TXP[3]

J38

DDI1_TXN[3]

D27

DDI1_AUXP

E27

DDI1_AUXN

H34

DDI2_TXP[0]

H33

DDI2_TXN[0]

F37

DDI2_TXP[1]

G38

DDI2_TXN[1]

F34

DDI2_TXP[2]

F35

DDI2_TXN[2]

E37

DDI2_TXP[3]

E36

DDI2_TXN[3]

F26

DDI2_AUXP

E26

DDI2_AUXN

C34

DDI3_TXP[0]

D34

DDI3_TXN[0]

B36

DDI3_TXP[1]

B34

DDI3_TXN[1]

F33

DDI3_TXP[2]

E33

DDI3_TXN[2]

C33

DDI3_TXP[3]

B33

DDI3_TXN[3]

A27

DDI3_AUXP

B27

DDI3_AUXN

SKYLAKE-H-CPU_BGA1440

@

SKYLAKE_HALO

BGA1440

4 OF 14

EDP_TXP[0]
EDP_TXN[0]
EDP_TXP[1]
EDP_TXN[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]

EDP_AUXP
EDP_AUXN

EDP_DISP_UTIL

EDP_RCOMP

PROC_AUDIO_CLK
PROC_AUDIO_SDI

PROC_AUDIO_SDO

CPU_EDP_TX0+

D29
E29
F28
E28
B29
A29
B28
C28

C26
B26

A33

D37

CPU_EDP_TX0­CPU_EDP_TX1+
CPU_EDP_TX1-

CPU_EDP_AUX
CPU_EDP_AUX#

EDP_COMP

CPU_EDP_TX0+ 35
CPU_EDP_TX0- 35
CPU_EDP_TX1+ 35
CPU_EDP_TX1- 35

CPU_EDP_AUX 35
CPU_EDP_AUX# 35

COMPENSATIONPU FOR eDP

CADNote:Tracewidth=20mils,Spacing=25mil,
Maxlength=100mils.

PROC_AUDIO_CLK_CPU

G27

PROC_AUDIO_SDO_CPU

G25

PROC_AUDIO_SDI_CPU_R

G29

20_0402_1%

12

RH762
33_0402_5%

@

1

CH264
10P_0402_50V8J

2

@

Delete eDP Lane2&3
HLZ SDV 20160510

VCCIO

12

RC4924.9_0402_1%

RC180

1 2

Place near CPU.

Need create 5% P/N

PROC_AUDIO_CLK_CPU 16
PROC_AUDIO_SDO_CPU 16

PROC_AUDIO_SDI_CPU 16

PROC_AUDIO_SDO_CPU

Reserved Cap HLZ SDV 0616

1 2

CH14 10P_0402_50V8J @

B B

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND C ONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CEN TER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CEN TER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CEN TER.

3

2015/02/26

2015/02/26

2015/02/26

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/02/26

2016/02/26

2016/02/26

Title

CPU (4/7) eDP, DDI

CPU (4/7) eDP, DDI

CPU (4/7) eDP, DDI

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

Custom

Custom

Custom

Friday, November 25, 2016

Friday, November 25, 2016

Date: Sheet of

Date: Sheet of

Date: Sheet of

Friday, November 25, 2016

DY512

DY512

DY512

1

875

875

875

1.0

1.0

1.0

MAX 68A

VCCCPUCORE

D D

C C

UC1G

AA13

VCC_1

AA31

VCC_2

AA32

VCC_3

AA33

VCC_4

AA34

VCC_5

AA35

VCC_6

AA36

VCC_7

AA37

VCC_8

AA38

VCC_9

AB29

VCC_10

AB30

VCC_11

AB31

VCC_12

AB32

VCC_13

AB35

VCC_14

AB36

VCC_15

AB37

VCC_16

AB38

VCC_17

AC13

VCC_18

AC14

VCC_19

AC29

VCC_20

AC30

VCC_21

AC31

VCC_22

AC32

VCC_23

AC33

VCC_24

AC34

VCC_25

AC35

VCC_26

AC36

VCC_27

AD13

VCC_28

AD14

VCC_29

AD31

VCC_30

AD32

VCC_31

AD33

VCC_32

AD34

VCC_33

AD35

VCC_34

AD36

VCC_35

AD37

VCC_36

AD38

VCC_37

AE13

VCC_38

AE14

VCC_39

AE30

VCC_40

AE31

VCC_41

AE32

VCC_42

AE35

VCC_43

AE36

VCC_44

AE37

VCC_45

AE38

VCC_46

AF35

VCC_47

AF36

VCC_48

AF37

VCC_49

AF38

VCC_50

K13

VCC_51

K14

VCC_52

L13

VCC_53

N13

VCC_54

N14

VCC_55

N30

VCC_56

N31

VCC_57

N32

VCC_58

N35

VCC_59

N36

VCC_60

N37

VCC_61

N38

VCC_62

P13

VCC_63

SKYLAKE-H-CPU_BGA1440

@

5

SKYLAKE_HALO

BGA1440

7 OF 14

VCC_64
VCC_65
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
VCC_72
VCC_73
VCC_74
VCC_75
VCC_76
VCC_77
VCC_78
VCC_79
VCC_80
VCC_81
VCC_82
VCC_83
VCC_84
VCC_85
VCC_86
VCC_87
VCC_88
VCC_89
VCC_90
VCC_91
VCC_92
VCC_93
VCC_94
VCC_95
VCC_96
VCC_97
VCC_98
VCC_99
VCC_100
VCC_101
VCC_102
VCC_103
VCC_104
VCC_105
VCC_106
VCC_107
VCC_108
VCC_109
VCC_110
VCC_111
VCC_112
VCC_113
VCC_114
VCC_115
VCC_116
VCC_117
VCC_118
VCC_119
VCC_120
VCC_121
VCC_122
VCC_123
VCC_124
VCC_125
VCC_126

VCC_SENSE

VSS_SENSE

VCCCPUCORE

V32
V33
V34
V35
V36
V37
V38
W13
W14
W29
W30
W31
W32
W35
W36
W37
W38
Y29
Y30
Y31
Y32
Y33
Y34
Y35
Y36
L14
P29
P30
P31
P32
P33
P34
P35
P36
R13
R31
R32
R33
R34
R35
R36
R37
R38
T29
T30
T31
T32
T35
T36
T37
T38
U29
U30
U31
U32
U33
U34
U35
U36
V13
V14
V31
P14

VCCSENSE_R

AG37

VSSSENSE_R

AG38

VCCGFXCORE

UC1N

AJ29

VCCGT_109

AJ30

VCCGT_110

AJ31

VCCGT_111

AJ32

VCCGT_112

AJ33

VCCGT_113

AJ34

VCCGT_114

AJ35

VCCGT_115

AJ36

VCCGT_116

AK31

VCCGT_117

AK32

VCCGT_118

AK33

VCCGT_119

AK34

VCCGT_120

AK35

VCCGT_121

AK36

VCCGT_122

AK37

VCCGT_123

AK38

VCCGT_124

AL13

VCCGT_125

AL29

VCCGT_126

AL30

VCCGT_127

AL31

VCCGT_128

AL32

VCCGT_129

AL35

VCCGT_130

AL36

VCCGT_131

AL37

VCCGT_132

AL38

VCCGT_133

AM13

VCCGT_134

AM14

VCCGT_135

AM29

VCCGT_136

AM30

VCCGT_137

AM31

VCCGT_138

AM32

VCCGT_139

AM33

VCCGT_140

AM34

VCCGT_141

AM35

VCCGT_142

AM36

VCCGT_143

AN13

VCCGT_144

AN14

VCCGT_145

AN31

VCCGT_146

AN32

VCCGT_147

AN33

VCCGT_148

AN34

VCCGT_149

AN35

VCCGT_150

AN36

VCCGT_151

AN37

VCCGT_152

AN38

VCCGT_153

AP13

VCCGT_154

AP14

VCCGT_155

AP29

VCCGT_156

AP30

VCCGT_157

AP31

VCCGT_158

AP32

VCCGT_159

AP35

VCCGT_160

AP36

VCCGT_161

AP37

VCCGT_162

AP38

VCCGT_163

AR29

VCCGT_164

AR30

VCCGT_165

AR31

VCCGT_166

AR32

VCCGT_167

AR33

VCCGT_168

AR34

VCCGT_169

AR35

VCCGT_170

AR36

VCCGT_171

AT14

VCCGT_172

AT31

VCCGT_173

AT32

VCCGT_174

AT33

VCCGT_175

AT34

VCCGT_176

AT35

VCCGT_177

AT36

VCCGT_178

AT37

VCCGT_179

AT38

VCCGT_180

AU14

VCCGT_181

AU29

VCCGT_182

AU30

VCCGT_183

AU31

VCCGT_184

AU32

VCCGT_185

AU35

VCCGT_186

AU36

VCCGT_187

AU37

VCCGT_188

AU38

VCCGT_189

SKYLAKE-H-CPU_BGA1440

@

SKYLAKE_HALO

BGA1440

14 OF 14

VCCGTX_1
VCCGTX_2
VCCGTX_3
VCCGTX_4
VCCGTX_5
VCCGTX_6
VCCGTX_7
VCCGTX_8

VCCGTX_9
VCCGTX_10
VCCGTX_11
VCCGTX_12
VCCGTX_13
VCCGTX_14
VCCGTX_15
VCCGTX_16
VCCGTX_17
VCCGTX_18
VCCGTX_19
VCCGTX_20
VCCGTX_21
VCCGTX_22

VCCGT_SENSE

VSSGTX_SENSE

VSSGT_SENSE

VCCGTX_SENSE

4

VCCGFXCORE

AF29
AF30
AF31
AF32
AF33
AF34
AG13
AG14
AG31
AG32
AG33
AG34
AG35
AG36
AH13
AH14
AH29
AH30
AH31
AH32
AJ13
AJ14

AH38
AH35
AH37
AH36

VCCGT_SENSE_R
VSSGT_SENSE_R

1

PAD@

TC60

PAD@

1

TC62

VCCGFXCORE

UC1H

BG34

VCCGT_1

BG35

VCCGT_2

BG36

VCCGT_3

BH33

VCCGT_4

BH34

VCCGT_5

BH35

VCCGT_6

BH36

VCCGT_7

BH37

VCCGT_8

BH38

VCCGT_9

BJ37

VCCGT_10

BJ38

VCCGT_11

BL36

VCCGT_12

BL37

VCCGT_13

BM36

VCCGT_14

BM37

VCCGT_15

BN36

VCCGT_16

BN37

VCCGT_17

BN38

VCCGT_18

BP37

VCCGT_19

BP38

VCCGT_20

BR37

VCCGT_21

BT37

VCCGT_22

BE38

VCCGT_23

BF13

VCCGT_24

BF14

VCCGT_25

BF29

VCCGT_26

BF30

VCCGT_27

BF31

VCCGT_28

BF32

VCCGT_29

BF35

VCCGT_30

BF36

VCCGT_31

BF37

VCCGT_32

BF38

VCCGT_33

BG29

VCCGT_34

BG30

VCCGT_35

BG31

VCCGT_36

BG32

VCCGT_37

BG33

VCCGT_38

BC36

VCCGT_39

BC37

VCCGT_40

BC38

VCCGT_41

BD13

VCCGT_42

BD14

VCCGT_43

BD29

VCCGT_44

BD30

VCCGT_45

BD31

VCCGT_46

BD32

VCCGT_47

BD33

VCCGT_48

BD34

VCCGT_49

BD35

VCCGT_50

BD36

VCCGT_51

BE31

VCCGT_52

BE32

VCCGT_53

BE37

VCCGT_54

SKYLAKE-H-CPU_BGA1440

@

MAX 55A

SKYLAKE_HALO

BGA1440

8 OF 14

VCCGT_55
VCCGT_56
VCCGT_57
VCCGT_58
VCCGT_59
VCCGT_60
VCCGT_61
VCCGT_62
VCCGT_63
VCCGT_64
VCCGT_65
VCCGT_66
VCCGT_67
VCCGT_68
VCCGT_69
VCCGT_70
VCCGT_71
VCCGT_72
VCCGT_73
VCCGT_74
VCCGT_75
VCCGT_76
VCCGT_77
VCCGT_78
VCCGT_79
VCCGT_80
VCCGT_81
VCCGT_82
VCCGT_83
VCCGT_84
VCCGT_85
VCCGT_86
VCCGT_87
VCCGT_88
VCCGT_89
VCCGT_90
VCCGT_91
VCCGT_92
VCCGT_93
VCCGT_94
VCCGT_95
VCCGT_96
VCCGT_97
VCCGT_98

VCCGT_99
VCCGT_100
VCCGT_101
VCCGT_102
VCCGT_103
VCCGT_104
VCCGT_105
VCCGT_106
VCCGT_107
VCCGT_108

3

VCCGFXCORE

AV29
AV30
AV31
AV32
AV33
AV34
AV35
AV36
AW14
AW31
AW32
AW33
AW34
AW35
AW36
AW37
AW38
AY29
AY30
AY31
AY32
AY35
AY36
AY37
AY38
BA13
BA14
BA29
BA30
BA31
BA32
BA33
BA34
BA35
BA36
BB13
BB14
BB31
BB32
BB33
BB34
BB35
BB36
BB37
BB38
BC29
BC30
BC31
BC32
BC35
BE33
BE34
BE35
BE36

VCCGT_SENSE

VCCGT_SENSE65
VSSGT_SENSE65

VCC_SENSE

VCCCORE_SENSE65

VSSCORE_SENSE65

2

CRB place to CPU

VCCGFXCORE

12

RC60
100_0402_1%

RC40 0_0402_5%
RC41 0_0402_5%

12

RC63
100_0402_1%

CRB place to CPU

VCCCPUCORE

12

RC59
100_0402_1%

12

RC62
100_0402_1%

1 2
1 2

RC38 0_0402_5%

RC39 0_0402_5%

VCCGT_SENSE_R
VSSGT_SENSE_R

CADNote:RC38SHOULDBEPLACEDCLOSETO CPU

1 2

CADNote:RC39SHOULDBEPLACEDCLOSETO CPU

1 2

VCCSENSE_R

VSSSENSE_R

1

SDV Cost down list:
10U 10Pcs

VCCGFXCORE

1U 28Pcs

10U_0402_6.3V6M

10U_0402_6.3V6M

1

1

CC107

CC108

2

B B

VCCCPUCORE

1

2

10U_0402_6.3V6M

CC62

Cost down list:
10U 5Pcs
1U 19Pcs

10U_0402_6.3V6M

1

1

CC80

2

2

10U_0402_6.3V6M

10U_0402_6.3V6M

1

1

1

1

CC77

CC78

CC79

CC82

2

2

2

2

@

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1

1

1

CC76

CC74

CC75

2

2

2

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1

CC81

2

10U_0402_6.3V6M

1

1

1

CC88

CC91

CC83

2

2

2

@

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1

1

1

CC92

CC86

CC89

2

2

2

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1

1

CC84

CC87

2

2

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1

1

CC90

CC85

2

2

@

10U_0402_6.3V6M

1

1

1

CC173

CC100

CC101

2

2

2

10U_0402_6.3V6M

10U_0402_6.3V6M

1

CC99

2

10U_0402_6.3V6M

10U_0402_6.3V6M

1

1

1

CC94

CC97

2

1

1

CD75

CC93

CC95

2

2

@

@

33P_0402_50V8J

RF_NS@

2

CD76
33P_0402_50V8J

RF_NS@

2

10uF 28pcs

Near CPU

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1

1

1

CH93

2

2

@

1U_0201_6.3V6K

1

1

CH121

2

2

A A

@

1U_0201_6.3V6K

1

1

CH151

2

2

@

1

1

CH96

CH94

CH95

2

2

2

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1

1

1

CH122

CH123

CH124

2

2

2

@

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1

1

1

CH149

CH150

CH153

2

2

2

@

1U_0201_6.3V6K

1U_0201_6.3V6K

1

CH99

2

@

1

CH127

2

1

CH155

2

1

CH100

CH101

2

@

1U_0201_6.3V6K

1U_0201_6.3V6K

1

CH128

CH129

2

@

1U_0201_6.3V6K

CH156

1U_0201_6.3V6K

1

2

1U_0201_6.3V6K

1

2

1uF 64pcs

1

1

CH97

CH98

2

2

@

1U_0201_6.3V6K

1U_0201_6.3V6K

1

1

CH125

CH126

2

2

@

1U_0201_6.3V6K

1U_0201_6.3V6K

1

1

CH154

CH152

2

2

5

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1

1

1

1

1

1

CH104

CH102

CH130

CH105

CH103

2

2

2

1

2

2

@

@

@

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1

1

1

CH131

CH132

CH133

2

2

2

@

1

CH106

CH107

CH108

2

2

2

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1

1

1

CH135

CH136

CH134

2

2

2

@

Change CH109&CH110&CH135&CH140 from stuff to@
Change CH93&CH122&CH105&CH150 from @ to stuff
HLZ SIV 0811

1U_0201_6.3V6K

1

1

1

CH109

CH110

CH111

2

2

2

@

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1

1

1

CH137

CH138

CH140

2

2

2

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1

1

1

1

CH112

CH113

2

2

1U_0201_6.3V6K

1

1

CH139

CH142

2

2

4

1

CH115

CH116

CH114

2

2

2

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1

1

1

CH141

CH143

CH144

2

2

2

@

1U_0201_6.3V6K

1

1

1

CH117

CH118

CH119

CH120

2

2

2

@

@

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1

1

1

CH147

CH145

CH148

CH146

2

2

2

3

2

@

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1

1

1

CH158

CH157

2

2

2

@

@

@

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1

1

1

CH185

CH187

2

2

2

@

1U_0201_6.3V6K

1U_0201_6.3V6K

1

1

CH213

CH215

2

2

SIV Cost down list:
10U 9Pcs
1U 19Pcs

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1

1

CC110

2

2

1U_0201_6.3V6K

1

CH159

CH160

2

@

CH186

1

1

CC102

CC104

CC106

2

2

@

@

1U_0201_6.3V6K

1U_0201_6.3V6K

1

1

CH161

CH164

2

2

@

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1

1

1

CH188

CH190

CH191

2

2

2

@

1U_0201_6.3V6K

1U_0201_6.3V6K

1

1

CH218

2

2

@

1

2

@

CH220

10U_0402_6.3V6M

CC103

1U_0201_6.3V6K

1

CH165

2

1U_0201_6.3V6K

1

CH192

2

@

10U_0402_6.3V6M

10U_0402_6.3V6M

1

1

CC111

CC109

2

2

1U_0201_6.3V6K

1

CH167

2

1U_0201_6.3V6K

1U_0201_6.3V6K

1

1

CH195

2

2

@

1U_0201_6.3V6K

1

2

10uF 35pcs

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1

1

1

CC116

CC119

CC120

2

2

2

@

1U_0201_6.3V6K

1

CH168

2

@

1U_0201_6.3V6K

1U_0201_6.3V6K

1

1

CH194

CH196

CH197

2

2

@

@

CH235

Security Classification

Security Classification

Security Classification

2

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1

1

1

CC112

CC115

2

2

2

@

1U_0201_6.3V6K

1U_0201_6.3V6K

1

2

@

1U_0201_6.3V6K

1

1

CH170

CH172

CH173

2

2

@

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1

1

1

1

CH200

CH201

CH203

2

2

2

2

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1

1

1

CC113

1U_0201_6.3V6K

CC123

CC118

CC128

2

2

2

@

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1

1

1

CH204

2

1

CH205

CH206

CH202

2

2

2

10U_0402_6.3V6M

10U_0402_6.3V6M

1

2

@

1

2

1U_0201_6.3V6K

CH208

10U_0402_6.3V6M

1

1

CC125

CC127

2

2

@

1U_0201_6.3V6K

1U_0201_6.3V6K

1

CH182

CH180

2

@

1

2

@

1uF 68pcs

LC Future Center Secret Data

LC Future Center Secret Data

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY O F L C FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY O F L C FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY O F L C FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLO SED TO ANY THIRD P ARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLO SED TO ANY THIRD P ARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLO SED TO ANY THIRD P ARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/02/26

2015/02/26

2015/02/26

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2016/02/26

2016/02/26

2016/02/26

10U_0402_6.3V6M

1

CC121

2

1

2

@

1U_0201_6.3V6K

CH210

10U_0402_6.3V6M

10U_0402_6.3V6M

1

CC124

CC131

2

1U_0201_6.3V6K

1

CH184

CD77
33P_0402_50V8J

RF_NS@

2

1

1

CC134

2

2

@

1

CD78
33P_0402_50V8J

RF_NS@

2

Near CPU

Title

Title

Title

CPU (5/7) PWR, BYPASS

CPU (5/7) PWR, BYPASS

CPU (5/7) PWR, BYPASS

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

D

D

D

Friday, November 25, 2016

Friday, November 25, 2016

Friday, November 25, 2016

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

10U_0402_6.3V6M

CC132

DY512

DY512

DY512

975

975

975

1.0

1.0

1.0

5

AA6
AE12
AF5
AF6
AG5
AG9
AJ12
AL11
AP6
AP7
AR12
AR6
AT12
AW6
AY6
J5
J6
K12
K6
L12
L6
R6
T6
W6

Y12
BH13

G11

H30
H29
G30
H28

J28

VCCSA_SENSE_R

M38

VSSSA_SENSE_R

M37

VCCIO_SENSE_R

H14

VSSIO_SENSE_R

J14

+1.2V

130mA

60mA
20mA

150mA

VCCSA

J30
K29
K30
K31
K32
K33
K34
K35
L31
L32
L35
L36

10U_0603_6.3V6M

CC149

AG12

L37
L38
M29
M30
M31
M32
M33
M34
M35
M36

G15
G17
G19
G21
H15
H16
H17
H19
H20
H21
H26
H27
J15
J16
J17
J19
J20
J21
J26
J27

D D

MAX 5.5A

VCCIO

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

1

CC147

CC148

2

2

2

C C

SKYLAKE_HALO

UC1I

SKYLAKE-H-CPU_BGA1440

@

VCCSA_1
VCCSA_2
VCCSA_3
VCCSA_4
VCCSA_5
VCCSA_6
VCCSA_7
VCCSA_8
VCCSA_9
VCCSA_10
VCCSA_11
VCCSA_12
VCCSA_13
VCCSA_14
VCCSA_15
VCCSA_16
VCCSA_17
VCCSA_18
VCCSA_19
VCCSA_20
VCCSA_21
VCCSA_22

VCCIO_1
VCCIO_2
VCCIO_3
VCCIO_4
VCCIO_5
VCCIO_6
VCCIO_7
VCCIO_8
VCCIO_9
VCCIO_10
VCCIO_11
VCCIO_12
VCCIO_13
VCCIO_14
VCCIO_15
VCCIO_16
VCCIO_17
VCCIO_18
VCCIO_19
VCCIO_20
VCCIO_21

BGA1440

9 OF 14

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8

VDDQ_9
VDDQ_10
VDDQ_11
VDDQ_12
VDDQ_13
VDDQ_14
VDDQ_15
VDDQ_16
VDDQ_17
VDDQ_18
VDDQ_19
VDDQ_20
VDDQ_21
VDDQ_22
VDDQ_23
VDDQ_24

VDDQC

VCCPLL_OC_1
VCCPLL_OC_2

VCCST
VCCSTG_1
VCCSTG_2

VCCPLL_1
VCCPLL_2

VCCSA_SENSE
VSSSA_SENSE

VCCIO_SENSE

VSSIO_SENSE

4

MAX 2.8AMAX 11.1A

+1.2V

10U_0603_6.3V6M

1

CC172

2

+1.2V

VCCST

VCCSTG

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

VCCST

+1.2V

2

1U_0402_6.3V6K

1

CH251

2

CH249

2

10U_0603_6.3V6M

1

2

CH250

1

CC51

2

VCCSA

1

2

1

2

1U_0402_6.3V6K

1

CC150

2

1U_0402_6.3V6K

1

CH242

2

VDDQDECOUPLING

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

CC53

CC52

2

2

10U_0603_6.3V6M

1

CC136

2

1U_0402_6.3V6K

CH222

1

2

1U_0402_6.3V6K

1

CH252

2

10U_0603_6.3V6M

1

CC54

2

10uF 7pcs

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

CC141

CC140

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

CH223

CH221

2

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

CC57

CC56

CC55

2

2

3

10U_0603_6.3V6M

10U_0603_6.3V6M

1

CC142

2

1

1

CC139

CC138

2

2

1uF 3pcs

CC58

10U_0603_6.3V6M

1

CC59

2

10U_0603_6.3V6M

1

2

10U_0603_6.3V6M

1

2

10U_0603_6.3V6M

1

CD79

CC137

33P_0402_50V8J

RF_NS@

2

Near CPU

CC60

1

CD80
33P_0402_50V8J

RF_NS@

2

TC56
TC58

TC75
TC74

TC45
TC76

TC47
TC48

TC49
TC51

TC54
TC53
TC52

1
1

1
1

1
1

1
1

1
1

1
1
1

PAD @
PAD @

PAD @
PAD @

PAD @
PAD @

PAD @
PAD @

PAD @
PAD @

PAD @
PAD @
PAD @

2

UC1J

BJ17

VCCOPC_1

BJ19

VCCOPC_2

BJ20

VCCOPC_3

BK17

VCCOPC_4

BK19

VCCOPC_5

BK20

VCCOPC_6

BL16

VCCOPC_7

BL17

VCCOPC_8

BL18

VCCOPC_9

BL19

VCCOPC_10

BL20

VCCOPC_11

BL21

VCCOPC_12

BM17

VCCOPC_13

BN17

VCCOPC_14

BJ23

RSVD_1

BJ26

RSVD_2

BJ27

RSVD_3

BK23

RSVD_4

BK26

RSVD_5

BK27

RSVD_6

BL23

RSVD_7

BL24

RSVD_8

BL25

RSVD_9

BL26

RSVD_10

BL27

RSVD_11

BL28

RSVD_12

BM24

RSVD_13

BL15

VCCOPC_SENSE

BM16

VSSOPC_SENSE

BL22

RSVD_14

BM22

RSVD_15

BP15

VCCEOPIO_1

BR15

VCCEOPIO_2

BT15

VCCEOPIO_3

BP16

RSVD_16

BR16

RSVD_17

BT16

RSVD_18

BN15

VCCEOPIO_SENSE

BM15

VSSEOPIO_SENSE

BP17

RSVD_19

BN16

RSVD_20

BM14

VCC_OPC_1P8_1

BL14

VCC_OPC_1P8_2

BJ35

RSVD_21

BJ36

RSVD_22

AT13

ZVM#

AW13

MSM#

AU13

ZVM2#

AY13

MSM2#

BT29

OPC_RCOMP

BR25

OPCE_RCOMP

BP25

OPCE_RCOMP2

SKYLAKE-H-CPU_BGA1440

@

SKYLAKE_HALO

BGA1440

10 OF 14

1

CC63

22U_0603_6.3V6-M

CC64

22U_0603_6.3V6-M

1

1

2

2

B B

CRB place to CPU

VCCSA_SENSE

VCCSA_SENSE65
VSSSA_SENSE65

A A

5

12

RC151
100_0402_1%

1 2

RC150 0_0402_5%

1 2

RC148 0_0402_5%

12

RC149
100_0402_1%

VCCSA_SENSE_R
VSSSA_SENSE_R

4

22U_0603_6.3V6-M

CC65

22U_0603_6.3V6-M

CC66

1

1

2

2

VCCIO_SENSE

VCC_IO_SEN64
VSS_IO_SEN64

CRB place to CPU

VCCIOVCCSA

12

RC155
100_0402_1%

0_0402_5%
RC154

RC152

12

0_0402_5%

RC153
100_0402_1%

3

VCCIO_SENSE_R

1 2

@

VSSIO_SENSE_R

1 2

@

For Merge

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/02/26

2015/02/26

2015/02/26

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/02/26

2016/02/26

2016/02/26

Title

Title

Title

CPU (6/7) PWR, BYPASS

CPU (6/7) PWR, BYPASS

CPU (6/7) PWR, BYPASS

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

C

C

C

Friday, November 25, 2016

Friday, November 25, 2016

Friday, November 25, 2016

Date: Sheet of

Date: Sheet of

Date: Sheet of

DY512

DY512

DY512

1

10 75

10 75

10 75

1.0

1.0

1.0

5

SKYLAKE_HALO

D D

C C

B B

UC1F

Y38

VSS_1

Y37

VSS_2

Y14

VSS_3

Y13

VSS_4

Y11

VSS_5

Y10

VSS_6

Y9

VSS_7

Y8

VSS_8

Y7

VSS_9

W34

VSS_10

W33

VSS_11

W12

VSS_12

W5

VSS_13

W4

VSS_14

W3

VSS_15

W2

VSS_16

W1

VSS_17

V30

VSS_18

V29

VSS_19

V12

VSS_20

V6

VSS_21

U38

VSS_153

U37

VSS_22

U6

VSS_23

T34

VSS_24

T33

VSS_25

T14

VSS_26

T13

VSS_27

T12

VSS_28

T11

VSS_29

T10

VSS_30

T9

VSS_31

T8

VSS_32

T7

VSS_33

T5

VSS_34

T4

VSS_35

T3

VSS_36

T2

VSS_37

T1

VSS_38

R30

VSS_39

R29

VSS_40

R12

VSS_41

P38

VSS_42

P37

VSS_43

P12

VSS_44

P6

VSS_45

N34

VSS_46

N33

VSS_47

N12

VSS_48

N11

VSS_49

N10

VSS_50

N9

VSS_51

N8

VSS_52

N7

VSS_53

N6

VSS_54

N5

VSS_55

N4

VSS_56

N3

VSS_57

N2

VSS_58

N1

VSS_59

M14

VSS_60

M13

VSS_61

M12

VSS_62

M6

VSS_63

L34

VSS_64

L33

VSS_65

L30

VSS_66

L29

VSS_67

K38

VSS_68

K11

VSS_69

K10

VSS_70

K9

VSS_71

K8

VSS_72

K7

VSS_73

K5

VSS_74

K4

VSS_75

K3

VSS_76

K2

VSS_77

SKYLAKE-H-CPU_BGA1440

@

BGA1440

6 OF 14

4

VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98

VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152

NCTFVSS_1

3

SKYLAKE_HALO

UC1L

K1
J36
J33
J32
J25
J22
J18
J10
J7
J4
H35
H32
H25
H22
H18
H12
H11
G28
G26
G24
G23
G22
G20
G18
G16
G14
G12
G10
G9
G8
G6
G5
G4
F36
F31
F29
F27
F25
F23
F21
F19
F17
F15
F13
F11
F9
F8
F5
F4
F3
F2
E38
E35
E34
E9
E4
D33
D30
D28
D26
D24
D22
D20
D18
D16
D14
D12
D10
D9
D6
D3
C37
C31
C29
C27

D38

BT32
BT26
BT24
BT21
BT18
BT14
BT12

BR36
BR34
BR29
BR26
BR24
BR21
BR18
BR14
BR12

BP34
BP33
BP29
BP26
BP24
BP21
BP18
BP14
BP12

BN34
BN31
BN30
BN29
BN24
BN21
BN20
BN19
BN18
BN14
BN12

BM38
BM35
BM28
BM27
BM26
BM23
BM21
BM13
BM12

BL29
BK29
BK15
BK14

BJ32

BJ31

BJ25

BJ22
BH14
BH12

BG38
BG13
BG12
BF33
BF12
BE29

BC34
BC12
BB12

C17
C13

C9

BT9
BT5

BR7

BP7

BN9
BN7
BN4
BN2

BM9
BM6
BM2

BH9
BH8
BH5
BH4
BH1

BE6
BD9

BGA1440

VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238

SKYLAKE-H-CPU_BGA1440

@

12 OF 14

VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299

NCTFVSS_2
NCTFVSS_3
NCTFVSS_4
NCTFVSS_5
NCTFVSS_6
NCTFVSS_7

C25
C23
C21
C19
C15
C11
C8
C5
BM29
BM25
BM18
BM11
BM8
BM7
BM5
BM3
BL38
BL35
BL13
BL6
BK25
BK22
BK13
BK6
BJ30
BJ29
BJ15
BJ12
BH11
BH10
BH7
BH6
BH3
BH2
BG37
BG14
BG6
BF34
BF6
BE30
BE5
BE4
BE3
BE2
BE1
BD38
BD37
BD12
BD11
BD10
BD8
BD7
BD6
BC33
BC14
BC13
BC6
BB30
BB29
BB6
BB5

C2
BT36
BT35
BT4
BT3
BR38

UC1M

BB4

VSS_300

BB3

VSS_301

BB2

VSS_302

BB1

VSS_303

BA38

VSS_304

BA37

VSS_305

BA12

VSS_306

BA11

VSS_307

BA10

VSS_308

BA9

VSS_309

BA8

VSS_310

BA7

VSS_311

BA6

VSS_312

B9

VSS_313

AY34

VSS_314

AY33

VSS_315

AY14

VSS_316

AY12

VSS_317

AW30

VSS_318

AW29

VSS_319

AW12

VSS_320

AW5

VSS_321

AW4

VSS_322

AW3

VSS_323

AW2

VSS_324

AW1

VSS_325

AV38

VSS_326

AV37

VSS_327

AU34

VSS_328

AU33

VSS_329

AU12

VSS_330

AU11

VSS_331

AU10

VSS_332

AU9

VSS_333

AU8

VSS_334

AU7

VSS_335

AU6

VSS_336

AT30

VSS_337

AT29

VSS_338

AT6

VSS_339

AR38

VSS_340

AR37

VSS_341

AR14

VSS_342

AR13

VSS_343

AR5

VSS_344

AR4

VSS_345

AR3

VSS_346

AR2

VSS_347

AR1

VSS_348

AP34

VSS_349

AP33

VSS_350

AP12

VSS_351

AP11

VSS_352

AP10

VSS_353

AP9

VSS_354

AP8

VSS_355

AN30

VSS_356

AN29

VSS_357

AN12

VSS_358

AN6

VSS_359

AN5

VSS_360

AM38

VSS_361

AM37

VSS_362

AM12

VSS_363

AM5

VSS_364

AM4

VSS_365

AM3

VSS_366

AM2

VSS_367

AM1

VSS_368

AL34

VSS_369

AL33

VSS_370

AL14

VSS_371

AL12

VSS_372

AL10

VSS_373

AL9

VSS_374

AL8

VSS_375

AL7

VSS_376

AL4

VSS_377

SKYLAKE-H-CPU_BGA1440

@

2

SKYLAKE_HALO

BGA1440

13 OF 14

VSS_378
VSS_379
VSS_380
VSS_381
VSS_382
VSS_383
VSS_384
VSS_385
VSS_386
VSS_387
VSS_388
VSS_389
VSS_390
VSS_391
VSS_392
VSS_393
VSS_394
VSS_395
VSS_396
VSS_397
VSS_398
VSS_399
VSS_400
VSS_401
VSS_402
VSS_403
VSS_404
VSS_405
VSS_406
VSS_407
VSS_408
VSS_409
VSS_410
VSS_411
VSS_412
VSS_413
VSS_414
VSS_415
VSS_416
VSS_417
VSS_418
VSS_419
VSS_420
VSS_421
VSS_422
VSS_423
VSS_424
VSS_425
VSS_426
VSS_427
VSS_428
VSS_429
VSS_430
VSS_431
VSS_432
VSS_433
VSS_434
VSS_435
VSS_436
VSS_437
VSS_438
VSS_439
VSS_440
VSS_441
VSS_442
VSS_443
VSS_444
VSS_445
VSS_446

NCTFVSS_8

NCTFVSS_9
NCTFVSS_10
NCTFVSS_11
NCTFVSS_12

AK30
AK29
AK4
AJ38
AJ37
AJ6
AJ5
AJ4
AJ3
AJ2
AJ1
AH34
AH33
AH12
AH6
AG30
AG29
AG11
AG10
AG8
AG7
AG6
AF14
AF13
AF12
AF4
AF3
AF2
AF1
AE34
AE33
AE6
AD30
AD29
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AC38
AC37
AC12
AC6
AC5
AC4
AC3
AC2
AC1
AB34
AB33
AB6
AA30
AA29
AA12
A30
A28
A26
A24
A22
A20
A18
A16
A14
A12
A10
A9
A6

B37
B3
A34
A4
A3

1

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2015/02/26

2015/02/26

2015/02/26

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/02/26

2016/02/26

2016/02/26

Title

CPU (6/7) PWR, VSS

CPU (6/7) PWR, VSS

CPU (6/7) PWR, VSS

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

C

C

C

Friday, November 25, 2016

Friday, November 25, 2016

Friday, November 25, 2016

Date: Sheet of

Date: Sheet of

Date: Sheet of

DY512

DY512

DY512

1

11 75

11 75

11 75

1.0

1.0

1.0

5

DDR4 SO-DIMM A

DDRA_DQ47
DDRA_DQ07

D D

C C

+3VS +3VS +3VS

12

B B

12

DDRA_DQS#07
DDRA_DQS07

DDRA_DQ77
DDRA_DQ37
DDRA_DQ137
DDRA_DQ127

DDRA_DQ157
DDRA_DQ147
DDRA_DQ217
DDRA_DQ207
DDRA_DQS#27

DDRA_DQS27
DDRA_DQ227
DDRA_DQ187
DDRA_DQ297
DDRA_DQ287

DDRA_DQ277
DDRA_DQ307

DDRA_CKE07
DDRA_BG17

DDRA_BG07
DDRA_MA127

DDRA_MA97
DDRA_MA87

DDRA_MA67

RD22
0_0402_5%

@

DDRA_SA0 DDRA_SA1 DDRA_SA2

RD23
0_0402_5%

12

12

RD24
0_0402_5%

@

RD25
0_0402_5%

Change JDDRL1 from Foxconn to ARGOSY
HLZ SDV 20160510

+1.2V

+1.2V

JDDRL1A

RVS

1

DDRA_DQ4

DDRA_DQ0
DDRA_DQS#0

DDRA_DQS0
DDRA_DQ7
DDRA_DQ3
DDRA_DQ13
DDRA_DQ12

DDRA_DQ15
DDRA_DQ14
DDRA_DQ21
DDRA_DQ20
DDRA_DQS#2

DDRA_DQS2
DDRA_DQ22

DDRA_DQ18

DDRA_DQ29
DDRA_DQ28

DDRA_DQ27
DDRA_DQ30

DDRA_CKE0
DDRA_BG1

DDRA_BG0
DDRA_MA12 DDRA_MA11

DDRA_MA9
DDRA_MA8

DDRA_MA6

12

RD26
0_0402_5%

@

12

RD27
0_0402_5%

VSS_1

3

DQ5

5

VSS_3

7

DQ1

9

VSS_5

11

DQS0_C

DM0_n/DBI0_n/NC

13

DQS0_t

15

VSS_8

17

DQ7

19

VSS_10

21

DQ3

23

VSS_12

25

DQ13

27

VSS_14

29

DQ9

31

VSS_16

33

DM1_n/DBl1_n/NC

35

VSS_17

37

DQ15

39

VSS_19

41

DQ10

43

VSS_21

45

DQ21

47

VSS_23

49

DQ17

51

VSS_25

53

DQS2_c

DM2_n/DBl2_n/NC

55

DQS2_t

57

VSS_28

59

DQ23

61

VSS_30

63

DQ19

65

VSS_32

67

DQ29

69

VSS_34

71

DQ25

73

VSS_36

75

DM3_n/DBl3_n/NC

77

VSS_37

79

DQ30

81

VSS_39

83

DQ26

85

VSS_41

87

CB5/NC

89

VSS_43

91

CB1/NC

93

VSS_45

95

DQS8_c

97

DQS8_t

99

VSS_48

101

CB2/NC

103

VSS_50

105

CB3/NC

107

VSS_52

109

CKE0

111

VDD_1

113

BG1

115

BG0

117

VDD_3

119

A12

121

A9

123

VDD_5

125

A8

127

A6

129

VDD_7

ARGOS_D4AR0-26001-1P52

ME@

DQS1_c
VSS_18
VSS_20
VSS_22
VSS_24
VSS_26
VSS_27
VSS_29
VSS_31
VSS_33
VSS_35

DQS3_c
VSS_38
VSS_40
VSS_42

CB4/NC
VSS_44
CB0/NC
VSS_46

DBI8_n/DBI_n/NC

VSS_47
CB6/NC
VSS_49
CB7/NC
VSS_51

RESET_n

ALERT_n

SPD Address = 0H

+1.2V

2

VSS_2

4

DQ4

6

VSS_4

8

DQ0

10

VSS_6

12
14

VSS_7

16

DQ6

18

VSS_9

20

DQ2

22

VSS_11

24

DQ12

26

VSS_13

28

DQ8

30

VSS_15

32
34

DQS1_t

36
38

DQ14

40
42

DQ11

44
46

DQ20

48
50

DQ16

52
54
56
58

DQ22

60
62

DQ18

64
66

DQ28

68
70

DQ24

72
74
76

DQS3_t

78
80

DQ31

82
84

DQ27

86
88
90
92
94
96
98
100
102
104
106
108
110

CKE1

112

VDD_2

114

ACT_n

116
118

VDD_4

120

A11

122

A7

124

VDD_6

126

A5

128

A4

130

VDD_8

Layout Note:
Place near DIMM

4

+1.2V

DDRA_DQ1
DDRA_DQ5

DDRA_DQ6
DDRA_DQ2
DDRA_DQ9
DDRA_DQ8
DDRA_DQS#1

DDRA_DQS1
DDRA_DQ10
DDRA_DQ11
DDRA_DQ16
DDRA_DQ17

DDRA_DQ19
DDRA_DQ23
DDRA_DQ24
DDRA_DQ25
DDRA_DQS#3

DDRA_DQS3
DDRA_DQ26
DDRA_DQ31

PCH_DRAMRST#
DDRA_CKE1

DDRA_ACT#
DDRA_ALERT#

DDRA_MA7
DDRA_MA5

DDRA_MA4

DDRA_DQ1 7
DDRA_DQ5 7

DDRA_DQ6 7
DDRA_DQ2 7
DDRA_DQ9 7
DDRA_DQ8 7
DDRA_DQS#1 7

DDRA_DQS1 7
DDRA_DQ10 7
DDRA_DQ11 7
DDRA_DQ16 7
DDRA_DQ17 7

DDRA_DQ19 7
DDRA_DQ23 7
DDRA_DQ24 7
DDRA_DQ25 7
DDRA_DQS#3 7

DDRA_DQS3 7
DDRA_DQ26 7
DDRA_DQ31 7

DDRA_CKE1 7
DDRA_ACT# 7

DDRA_ALERT# 7
DDRA_MA11 7

DDRA_MA7 7
DDRA_MA5 7

DDRA_MA4 7

1

CD69

0.1U_0402_10V7K

2

@

Layout Note:
Place near DIMM

+0.6VS

MAX 0.5A

1U_0402_6.3V6K

1

CD23

2

PCH_DRAMRST# 13,16

1

1

CD25

CD24

2

2

10U_0402_6.3V6M

3

+3VS

10U_0402_6.3V6M

RD18

1 2

0_0402_5%

+2.5V

2

+1.2V +1.2V

+1.2V +1.2V

JDDRL1B

DDRA_MA3

CD27

1

2

CD59

1U_0402_6.3V6K

DDRA_MA1
DDRA_CLK0

DDRA_CLK0#
DDRA_PARITY

DDRA_BA1
DDRA_CS0#

DDRA_MA14_WE#
DDRA_ODT0

DDRA_CS1#
DDRA_ODT1

DDRA_DQ33
DDRA_DQ37
DDRA_DQS#4

DDRA_DQS4
DDRA_DQ38
DDRA_DQ39
DDRA_DQ44
DDRA_DQ41

DDRA_DQ43
DDRA_DQ46
DDRA_DQ50
DDRA_DQ52
DDRA_DQS#6

DDRA_DQS6
DDRA_DQ54
DDRA_DQ51
DDRA_DQ57
DDRA_DQ61

DDRA_DQ62
DDRA_DQ58
SMB_CLK_S3

DDRA_VDDSPD

1

1

CD28
.1U_0402_10V6-K

2

2

1

CD60

2

1U_0402_6.3V6K

DDRA_MA17
DDRA_CLK07

DDRA_CLK0#7
DDRA_PARITY7

DDRA_BA17
DDRA_CS0#7

DDRA_MA14_WE#7 DDRA_MA16_RAS# 7

DDRA_ODT07
DDRA_CS1#7

DDRA_ODT17

DDRA_DQ337
DDRA_DQ377
DDRA_DQS#47

DDRA_DQS47
DDRA_DQ387
DDRA_DQ397
DDRA_DQ447
DDRA_DQ417

DDRA_DQ437
DDRA_DQ467
DDRA_DQ507
DDRA_DQ527
DDRA_DQS#67

DDRA_DQS67
DDRA_DQ547
DDRA_DQ517
DDRA_DQ577
DDRA_DQ617

DDRA_DQ627

DDRA_DQ587

SMB_CLK_S313,16,45,50

2.2U_0603_6.3V6K

RD20

1 2

0_0402_5%

+2.5V

MAX 0.5A

1

1

CD57

CD58

2

2

10U_0402_6.3V6M

10U_0402_6.3V6M

RVS

131

A3

133

A1

135

VDD_9

137

CK0_t

139

CK0_c

141

VDD_11

143

Parity

145

BA1

147

VDD_13

149

CS0_n

151

WE_n/A14

153

VDD_15

155

ODT0

157

CS1_n

159

VDD_17

161

ODT1

163

VDD_19

165

C1/CS3_n/NC

167

VSS_53

169

DQ37

171

VSS_55

173

DQ33

175

VSS_57

177

DQS4_c

DM4_n/DBl4_n/NC

179

DQS4_t

181

VSS_60

183

DQ38

185

VSS_62

187

DQ34

189

VSS_64

191

DQ44

193

VSS_66

195

DQ40

197

VSS_68

199

DM5_n/DBl5_n/NC

201

VSS_69

203

DQ46

205

VSS_71

207

DQ42

209

VSS_73

211

DQ52

213

VSS_75

215

DQ49

217

VSS_77

219

DQS6_c

DM6_n/DBl6_n/NC

221

DQS6_t

223

VSS_80

225

DQ55

227

VSS_82

229

DQ51

231

VSS_84

233

DQ61

235

VSS_86

237

DQ56

239

VSS_88

241

DM7_n/DBl7_n/NC

243

VSS_89

245

DQ62

247

VSS_91

249

DQ58

251

VSS_93

253

SCL

255

VDDSPD

257

VPP_1

259

VPP_2

261

GND_1

ARGOS_D4AR0-26001-1P52

ME@

+VREF_CA_DIMMA_R

EVENT_n/NF

VDD_10
CK1_t/NF
CK1_c/NF

VDD_12

A10/AP

VDD_14

RAS_n/A16

VDD_16

CAS_n/A15

VDD_18

C0/CS2_n/NC

VREFCA

VSS_54
VSS_56
VSS_58
VSS_59
VSS_61
VSS_63
VSS_65
VSS_67

DQS5_c

DQS5_t
VSS_70

VSS_72
VSS_74
VSS_76
VSS_78
VSS_79
VSS_81
VSS_83
VSS_85
VSS_87

DQS7_c

DQS7_t
VSS_90

VSS_92
VSS_94

GND_2

1

CD1

0.022U_0402_16V7-K

2

12

RD4

24.9_0402_1%

For EMC

DQ36
DQ32

DQ39
DQ35
DQ45
DQ41

DQ47
DQ43
DQ53
DQ48

DQ54
DQ50
DQ60
DQ57

DQ63
DQ59

DDRA_MA2

132

A2

A0

BA0

A13

SA2

SDA
SA0

Vtt

SA1

DDRA_EVENT#

134
136

DDRA_CLK1

138

DDRA_CLK1#

140
142

DDRA_MA0

144

DDRA_MA10_AP

146
148

DDRA_BA0

150

DDRA_MA16_RAS#

152
154

DDRA_MA15_CAS#

156

DDRA_MA13

158
160
162

+VREF_CA_DIMMA

164

DDRA_SA2

166
168

DDRA_DQ36

170
172

DDRA_DQ32

174
176
178
180

DDRA_DQ35

182
184

DDRA_DQ34

186
188

DDRA_DQ40

190
192

DDRA_DQ45

194
196

DDRA_DQS#5

198

DDRA_DQS5

200
202

DDRA_DQ47

204
206

DDRA_DQ42

208
210

DDRA_DQ48

212
214

DDRA_DQ49

216
218
220
222

DDRA_DQ53

224
226

DDRA_DQ55

228
230

DDRA_DQ56

232
234

DDRA_DQ60

236
238

DDRA_DQS#7

240

DDRA_DQS7

242
244

DDRA_DQ59

246
248

DDRA_DQ63

250
252

SMB_DATA_S3

254

DDRA_SA0

256
258

DDRA_SA1

260
262

1 2

RD2
2_0402_5%

Note:
VREFtracewidth:20 milsatleast
Spacing:20milstoothersignal/planes
PlacenearDIMMscoket

+1.2V

12

12

+0.6VS

RD1
1K_0402_1%

RD3

1

DDRA_MA2 7DDRA_MA37

DDRA_CLK1 7
DDRA_CLK1# 7

DDRA_MA0 7

DDRA_MA10_AP 7
DDRA_BA0 7

DDRA_MA15_CAS# 7
DDRA_MA13 7

DDRA_DQ36 7
DDRA_DQ32 7

DDRA_DQ35 7
DDRA_DQ34 7
DDRA_DQ40 7
DDRA_DQ45 7
DDRA_DQS#5 7

DDRA_DQS5 7
DDRA_DQ47 7
DDRA_DQ42 7
DDRA_DQ48 7
DDRA_DQ49 7

DDRA_DQ53 7
DDRA_DQ55 7
DDRA_DQ56 7
DDRA_DQ60 7
DDRA_DQS#7 7

DDRA_DQS7 7
DDRA_DQ59 7
DDRA_DQ63 7
SMB_DATA_S3 13,16,45,50

Change RD2 to 0ohm jump

+VREF_CA_DIMMA

.1U_0402_10V6-K

CD21

1

1K_0402_1%

2

240_0402_5%

DDRA_EVENT#

1

2

CD2

2.2U_0603_6.3V6K

+1.2V

12

RD5

1

2

.1U_0402_10V6-K

CD3

MAX 3A

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

1

CD97

CD98

EMC_NS@

A A

5

2

4

EMC_NS@

0.1U_0402_10V7K

1

1

CD96

CD95

EMC_NS@

2

EMC_NS@

2

0.1U_0402_10V7K

1

2

CD7

+1.2V

10U_0603_6.3V6M

1

2

CD8

10U_0603_6.3V6M

1

2

CD9

10U_0603_6.3V6M

1

2

10U_0603_6.3V6M

10U_0603_6.3V6M

CD11

CD10

1

2

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

CD12

1

2

Issued Date

Issued Date

Issued Date

10U_0603_6.3V6M

CD13

1

2

10U_0603_6.3V6M

1

2

CD14

2015/02/26

2015/02/26

2015/02/26

10U_0603_6.3V6M

1

1

CD15

2

2

1U_0402_6.3V6K

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

1

CD16

2

1U_0402_6.3V6K

Deciphered Date

Deciphered Date

Deciphered Date

1

2

CD17

1U_0402_6.3V6K

2

Change DDR4 220u to B2

HLZ SVD 0527

1

1

CD18

CD65

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

2016/02/26

2016/02/26

2016/02/26

1

CD66

2

1

1

CD67

2

1U_0402_6.3V6K

1U_0402_6.3V6K

Change CD81 & CD82 from @ to stuff based on RF requirement

HLZ SIT 0924

1

CD19

+

CD68

2

2

1U_0402_6.3V6K

Title

Title

Title

DDRVI SO-DIMM A

DDRVI SO-DIMM A

DDRVI SO-DIMM A

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

CD81
33P_0402_50V8J

RF@

2

@

220U_B2_6.3VM_R25M

Near JDDRL1

Friday, November 25, 2016

Friday, November 25, 2016

Friday, November 25, 2016

DY512

DY512

DY512

1

1

CD82
33P_0402_50V8J

RF@

2

12 75

12 75

12 75

1.0

1.0

1.0

5

DDR4 SO-DIMM B

DDRB_DQ27

D D

C C

B B

DDRB_DQ57
DDRB_DQS#07

DDRB_DQS07
DDRB_DQ67
DDRB_DQ37
DDRB_DQ107
DDRB_DQ147

DDRB_DQ127
DDRB_DQ137
DDRB_DQ227
DDRB_DQ187
DDRB_DQS#27

DDRB_DQS27
DDRB_DQ207
DDRB_DQ197
DDRB_DQ277
DDRB_DQ317

DDRB_DQ307
DDRB_DQ247

DDRB_CKE07 DDRB_CKE1 7
DDRB_BG17

DDRB_BG07
DDRB_MA127

DDRB_MA97
DDRB_MA87

DDRB_MA67

+3VS +3VS +3VS

12

RD28
0_0402_5%

@

DDRB_SA0 DDRB_SA1 DDRB_SA2

12

RD29
0_0402_5%

12

12

RD30
0_0402_5%

RD31
0_0402_5%

@

Change JDDRH1 from Foxconn to ARGOSY and RVS to STD
HLZ SDV 20160510

+1.2V

JDDRH1A

STD

1

RD33
0_0402_5%

@

RD32
0_0402_5%

VSS_1

3

DQ5

5

VSS_3

7

DQ1

9

VSS_5

11

DQS0_C

DM0_n/DBI0_n/NC

13

DQS0_t

15

VSS_8

17

DQ7

19

VSS_10

21

DQ3

23

VSS_12

25

DQ13

27

VSS_14

29

DQ9

31

VSS_16

33

DM1_n/DBl1_n/NC

35

VSS_17

37

DQ15

39

VSS_19

41

DQ10

43

VSS_21

45

DQ21

47

VSS_23

49

DQ17

51

VSS_25

53

DQS2_c

DM2_n/DBl2_n/NC

55

DQS2_t

57

VSS_28

59

DQ23

61

VSS_30

63

DQ19

65

VSS_32

67

DQ29

69

VSS_34

71

DQ25

73

VSS_36

75

DM3_n/DBl3_n/NC

77

VSS_37

79

DQ30

81

VSS_39

83

DQ26

85

VSS_41

87

CB5/NC

89

VSS_43

91

CB1/NC

93

VSS_45

95

DQS8_c

DBI8_n/DBI_n/NC

97

DQS8_t

99

VSS_48

101

CB2/NC

103

VSS_50

105

CB3/NC

107

VSS_52

109

CKE0

111

VDD_1

113

BG1

115

BG0

117

VDD_3

119

A12

121

A9

123

VDD_5

125

A8

127

A6

129

VDD_7

ARGOS_D4AS0-26001-1P52

ME@

DDRB_DQ2
DDRB_DQ5
DDRB_DQS#0

DDRB_DQS0
DDRB_DQ6
DDRB_DQ3
DDRB_DQ10
DDRB_DQ14

DDRB_DQ12
DDRB_DQ13
DDRB_DQ22
DDRB_DQ18
DDRB_DQS#2

DDRB_DQS2
DDRB_DQ20
DDRB_DQ19
DDRB_DQ27
DDRB_DQ31

DDRB_DQ30
DDRB_DQ24

DDRB_CKE0 DDRB_CKE1
DDRB_BG1

DDRB_BG0
DDRB_MA12

DDRB_MA9
DDRB_MA8

DDRB_MA6

12

12

SPD Address = 2H

4

2

VSS_2

4

DQ4

6

VSS_4

8

DQ0

10

VSS_6

12
14

VSS_7

16

DQ6

18

VSS_9

20

DQ2

22

VSS_11

24

DQ12

26

VSS_13

28

DQ8

30

VSS_15

32

DQS1_c

34

DQS1_t

36

VSS_18

38

DQ14

40

VSS_20

42

DQ11

44

VSS_22

46

DQ20

48

VSS_24

50

DQ16

52

VSS_26

54
56

VSS_27

58

DQ22

60

VSS_29

62

DQ18

64

VSS_31

66

DQ28

68

VSS_33

70

DQ24

72

VSS_35

74

DQS3_c

76

DQS3_t

78

VSS_38

80

DQ31

82

VSS_40

84

DQ27

86

VSS_42

88

CB4/NC

90

VSS_44

92

CB0/NC

94

VSS_46

96
98

VSS_47

100

CB6/NC

102

VSS_49

104

CB7/NC

106

VSS_51

108

RESET_n

110

CKE1

112

VDD_2

114

ACT_n

116

ALERT_n

118

VDD_4

120

A11

122

A7

124

VDD_6

126

A5

128

A4

130

VDD_8

Layout Note:
Place near DIMM

+1.2V+1.2V +1.2V

PCH_DRAMRST#

DDRB_ACT#
DDRB_ALERT#

DDRB_MA11
DDRB_MA7

DDRB_MA5
DDRB_MA4

DDRB_DQ4
DDRB_DQ0

DDRB_DQ1
DDRB_DQ7
DDRB_DQ8
DDRB_DQ9
DDRB_DQS#1

DDRB_DQS1
DDRB_DQ11
DDRB_DQ15
DDRB_DQ17
DDRB_DQ16

DDRB_DQ23
DDRB_DQ21
DDRB_DQ28
DDRB_DQ25
DDRB_DQS#3

DDRB_DQS3
DDRB_DQ26
DDRB_DQ29

DDRB_DQ4 7
DDRB_DQ0 7

DDRB_DQ1 7
DDRB_DQ7 7
DDRB_DQ8 7
DDRB_DQ9 7
DDRB_DQS#1 7

DDRB_DQS1 7
DDRB_DQ11 7
DDRB_DQ15 7
DDRB_DQ17 7
DDRB_DQ16 7

DDRB_DQ23 7
DDRB_DQ21 7
DDRB_DQ28 7
DDRB_DQ25 7
DDRB_DQS#3 7

DDRB_DQS3 7
DDRB_DQ26 7
DDRB_DQ29 7

DDRB_ACT# 7
DDRB_ALERT# 7

DDRB_MA11 7
DDRB_MA7 7

DDRB_MA5 7
DDRB_MA4 7

1

CD70

0.1U_0402_10V7K

2

@

Layout Note:
Place near DIMM

+0.6VS

MAX 0.5A

1

CD49

2

1U_0402_6.3V6K

3

PCH_DRAMRST# 12,16

+3VS

1

1

CD50

CD51

2

2

10U_0402_6.3V6M

10U_0402_6.3V6M

RD19

1 2

0_0402_5%

+2.5V

DDRB_MA37
DDRB_MA17

DDRB_CLK07
DDRB_CLK0#7

DDRB_PARITY7

DDRB_BA17
DDRB_CS0#7

DDRB_MA14_WE#7

DDRB_ODT07
DDRB_CS1#7

DDRB_ODT17

DDRB_DQ387
DDRB_DQ357
DDRB_DQS#47

DDRB_DQS47
DDRB_DQ337
DDRB_DQ327
DDRB_DQ407
DDRB_DQ417

DDRB_DQ427
DDRB_DQ467
DDRB_DQ527
DDRB_DQ487
DDRB_DQS#67

DDRB_DQS67
DDRB_DQ507
DDRB_DQ517
DDRB_DQ577
DDRB_DQ617

DDRB_DQ567
DDRB_DQ607

SMB_CLK_S312,16,45,50

RD21

1 2

0_0402_5%

+2.5V

1

CD53

2.2U_0603_6.3V6K

2

MAX 0.5A

1

CD63

2

10U_0402_6.3V6M

1

2

CD64

10U_0402_6.3V6M

2

+1.2V +1.2V

+1.2V +1.2V

JDDRH1B

DDRB_MA3
DDRB_MA1

DDRB_CLK0
DDRB_CLK0#

DDRB_PARITY

DDRB_BA1
DDRB_CS0#

DDRB_MA14_WE#
DDRB_ODT0

DDRB_CS1#
DDRB_ODT1

DDRB_DQ38
DDRB_DQ35
DDRB_DQS#4

DDRB_DQS4
DDRB_DQ33
DDRB_DQ32
DDRB_DQ40
DDRB_DQ41

DDRB_DQ42
DDRB_DQ46
DDRB_DQ52
DDRB_DQ48
DDRB_DQS#6

DDRB_DQS6
DDRB_DQ50
DDRB_DQ51
DDRB_DQ57
DDRB_DQ61

DDRB_DQ56
DDRB_DQ60
SMB_CLK_S3

DDRB_VDDSPD

1

CD54
.1U_0402_10V6-K

2

1

CD61

2

1U_0402_6.3V6K

1

2

CD62

1U_0402_6.3V6K

131

A3

133

A1

135

VDD_9

137

CK0_t

139

CK0_c

141

VDD_11

143

Parity

145

BA1

147

VDD_13

149

CS0_n

151

WE_n/A14

153

VDD_15

155

ODT0

157

CS1_n

159

VDD_17

161

ODT1

163

VDD_19

165

C1/CS3_n/NC

167

VSS_53

169

DQ37

171

VSS_55

173

DQ33

175

VSS_57

177

DQS4_c

179

DQS4_t

181

VSS_60

183

DQ38

185

VSS_62

187

DQ34

189

VSS_64

191

DQ44

193

VSS_66

195

DQ40

197

VSS_68

199

DM5_n/DBl5_n

201

VSS_69

203

DQ46

205

VSS_71

207

DQ42

209

VSS_73

211

DQ52

213

VSS_75

215

DQ49

217

VSS_77

219

DQS6_c

221

DQS6_t

223

VSS_80

225

DQ55

227

VSS_82

229

DQ51

231

VSS_84

233

DQ61

235

VSS_86

237

DQ56

239

VSS_88

241

DM7_n/DBl7_n/NC

243

VSS_89

245

DQ62

247

VSS_91

249

DQ58

251

VSS_93

253

SCL

255

VDDSPD

257

VPP_1

259

VPP_2

261

GND_1

ARGOS_D4AS0-26001-1P52

ME@

STD

EVENT_n/NF

C0/CS2_n/NC

DM4_n/DBl4_n/NC

DM6_n/DBl6_n/NC

132

A2

134
136

VDD_10

138

CK1_t/NF

140

CK1_c/NF

142

VDD_12

144

A0

146

A10/AP

148

VDD_14

150

BA0

152

RAS_n/A16

154

VDD_16

156

CAS_n/A15

158

A13

160

VDD_18

162
164

VREFCA

166

SA2

168

VSS_54

170

DQ36

172

VSS_56

174

DQ32

176

VSS_58

178
180

VSS_59

182

DQ39

184

VSS_61

186

DQ35

188

VSS_63

190

DQ45

192

VSS_65

194

DQ41

196

VSS_67

198

DQS5_c

200

DQS5_t

202

VSS_70

204

DQ47

206

VSS_72

208

DQ43

210

VSS_74

212

DQ53

214

VSS_76

216

DQ48

218

VSS_78

220
222

VSS_79

224

DQ54

226

VSS_81

228

DQ50

230

VSS_83

232

DQ60

234

VSS_85

236

DQ57

238

VSS_87

240

DQS7_c

242

DQS7_t

244

VSS_90

246

DQ63

248

VSS_92

250

DQ59

252

VSS_94

254

SDA

256

SA0

258

Vtt

260

SA1

262

GND_2

+VREF_DQ_DIMMB_R

RD12

2_0402_5%

1

CD29

0.022U_0402_16V7-K

2

12

RD14

24.9_0402_1%

For EMC

DDRB_MA2

DDRB_CLK1
DDRB_CLK1#

DDRB_MA0

DDRB_MA10_AP
DDRB_BA0

DDRB_MA16_RAS#
DDRB_MA15_CAS#

DDRB_MA13

+VREF_CA_DIMMB
DDRB_SA2

DDRB_DQ34
DDRB_DQ39

DDRB_DQ36
DDRB_DQ37
DDRB_DQ44
DDRB_DQ45
DDRB_DQS#5

DDRB_DQS5
DDRB_DQ47
DDRB_DQ43
DDRB_DQ54
DDRB_DQ55

DDRB_DQ53
DDRB_DQ49
DDRB_DQ59
DDRB_DQ62
DDRB_DQS#7

DDRB_DQS7
DDRB_DQ63
DDRB_DQ58
SMB_DATA_S3

DDRB_SA0
DDRB_SA1

+1.2V

Change RD12 to 0ohm jump

12

RD11

1 2

1K_0402_1%

12

1K_0402_1%

RD13

CAD Note:
Trace width=20mil,Spcing=20mils

1

DDRB_MA2 7

DDRB_CLK1 7
DDRB_CLK1# 7

DDRB_MA0 7

DDRB_MA10_AP 7
DDRB_BA0 7

DDRB_MA16_RAS# 7
DDRB_MA15_CAS# 7

DDRB_MA13 7

DDRB_DQ34 7
DDRB_DQ39 7

DDRB_DQ36 7
DDRB_DQ37 7
DDRB_DQ44 7
DDRB_DQ45 7
DDRB_DQS#5 7

DDRB_DQS5 7
DDRB_DQ47 7
DDRB_DQ43 7
DDRB_DQ54 7
DDRB_DQ55 7

DDRB_DQ53 7
DDRB_DQ49 7
DDRB_DQ59 7
DDRB_DQ62 7
DDRB_DQS#7 7

DDRB_DQS7 7
DDRB_DQ63 7
DDRB_DQ58 7
SMB_DATA_S3 12,16,45,50

+0.6VS

+VREF_CA_DIMMB

1

2

CD47

.1U_0402_10V6-K

DDRB_EVENT#DDRB_EVENT#

240_0402_5%

1

2

2.2U_0603_6.3V6K

CD30

+1.2V

12

RD6

1

2

.1U_0402_10V6-K

CD31

+1.2V

MAX 3A

10U_0603_6.3V6M

10U_0603_6.3V6M

CD35

CD36

1

A A

2

10U_0603_6.3V6M

CD37

1

2

CD38

1

2

10U_0603_6.3V6M

CD39

1

2

10U_0603_6.3V6M

CD40

1

2

10U_0603_6.3V6M

CD41

1

2

10U_0603_6.3V6M

CD42

1

2

10U_0603_6.3V6M

1

2

1

2

CD43

1U_0402_6.3V6K

1

CD44

2

1

CD45

2

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

1

CD46

2

1U_0402_6.3V6K

CD71

1U_0402_6.3V6K

1

2

CD72

1U_0402_6.3V6K

1

2

1

CD73

2

1U_0402_6.3V6K

Change CD83 & CD84 from @ to stuff based on RF requirement

HLZ SIT 0924

CD74

1U_0402_6.3V6K

1

CD83
33P_0402_50V8J

RF@

2

1

CD84
33P_0402_50V8J

RF@

2

1

CD4
33P_0402_50V8J

RF@

2

Add CD4 based on RF requirement

HLZ SIT 0924

Near JDDRH1

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2015/02/26

2015/02/26

2015/02/26

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/02/26

2016/02/26

2016/02/26

Title

DDRVI SO-DIMM B

DDRVI SO-DIMM B

DDRVI SO-DIMM B

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

C

C

C

Friday, November 25, 2016

Friday, November 25, 2016

Friday, November 25, 2016

Date: Sheet of

Date: Sheet of

Date: Sheet of

DY512

DY512

DY512

1

13 75

13 75

13 75

1.0

1.0

1.0

5

4

3

2

1

D D

EC_SCI#20,49

PCIE_PTX_DRX_P1145

NGFF SSD

C C

NGFF SSD

PCIE_PTX_DRX_N1145
PCIE_PRX_DTX_P1145
PCIE_PRX_DTX_N1145

PCIE_PTX_DRX_P1245
PCIE_PTX_DRX_N1245
PCIE_PRX_DTX_P1245
PCIE_PRX_DTX_N1245

EC_SCI#

+3VS

12

RH133
10K_0402_5%

1 2

RH95 0_0402_5%

PCIE_PTX_DRX_P11
PCIE_PTX_DRX_N11
PCIE_PRX_DTX_P11
PCIE_PRX_DTX_N11

PCIE_PTX_DRX_P12
PCIE_PTX_DRX_N12
PCIE_PRX_DTX_P12
PCIE_PRX_DTX_N12

UH1C

AV2

CL_CLK

AV3

CL_DATA

AW2

CL_RST#

R44

GPP_G8/FAN_PWM_0

R43

GPP_G9/FAN_PWM_1

U39

GPP_G10/FAN_PWM_2

N42

GPP_G11/FAN_PWM_3

U43

GPP_G0/FAN_TACH_0

U42

GPP_G1/FAN_TACH_1

U41

GPP_G2/FAN_TACH_2

M44

GPP_G3/FAN_TACH_3

U36

GPP_G4/FAN_TACH_4

P44

GPP_G5/FAN_TACH_5

T45

GPP_G6/FAN_TACH_6

T44

GPP_G7/FAN_TACH_7

B33

PCIE11_TXP

C33

PCIE11_TXN

K31

PCIE11_RXP

L31

PCIE11_RXN

AB33

GPP_F10/SCLOCK

AB35

GPP_F11/SLOAD

AA44

GPP_F13/SDATAOUT0

AA45

GPP_F12/SDATAOUT1

B38

PCIE14_TXN/SATA1B_TXN

C38

PCIE14_TXP/SATA1B_TXP

D39

PCIE14_RXN/SATA1B_RXN

E37

PCIE14_RXP/SATA1B_RXP

C36

PCIE13_TXN/SATA0B_TXN

B36

PCIE13_TXP/SATA0B_TXP

G35

PCIE13_RXN/SATA0B_RXN

E35

PCIE13_RXP/SATA0B_RXP

A35

PCIE12_TXP

B35

PCIE12_TXN

H33

PCIE12_RXP

G33

PCIE12_RXN

J45

PCIE20_TXP/SATA7_TXP

K44

PCIE20_TXN/SATA7_TXN

N38

PCIE20_RXP/SATA7_RXP

N39

PCIE20_RXN/SATA7_RXN

H44

PCIE19_TXP/SATA6_TXP

H43

PCIE19_TXN/SATA6_TXN

L39

PCIE19_RXP/SATA6_RXP

L37

PCIE19_RXN/SATA6_RXN

SKYLAKE-H-PCH_FCBGA837

@

CLINK

FAN

SPT-H_PCH

3 OF 12

PCIE9_RXN/SATA0A_RXN

PCIE9_RXP/SATA0A_RXP
PCIE9_TXN/SATA0A_TXN

PCIE9_TXP/SATA0A_TXP

PCIE10_RXN/SATA1A_RXN
PCIE10_RXP/SATA1A_RXP

PCIE10_TXN/SATA1A_TXN
PCIE10_TXP/SATA1A_TXP

PCIE15_RXN/SATA2_RXN
PCIE15_RXP/SATA2_RXP
PCIE15_TXN/SATA2_TXN

PCIE15_TXP/SATA2_TXP

PCIe/SATA

PCIE16_RXN/SATA3_RXN
PCIE16_RXP/SATA3_RXP
PCIE16_TXN/SATA3_TXN

PCIE16_TXP/SATA3_TXP

PCIE17_RXN/SATA4_RXN
PCIE17_RXP/SATA4_RXP
PCIE17_TXN/SATA4_TXN

PCIE17_TXP/SATA4_TXP

PCIE18_RXN/SATA5_RXN
PCIE18_RXP/SATA5_RXP
PCIE18_TXN/SATA5_TXN

PCIE18_TXP/SATA5_TXP

GPP_E8/SATALED#
GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2
GPP_F0/SATAXPCIE3/SATAGP3
GPP_F1/SATAXPCIE4/SATAGP4
GPP_F2/SATAXPCIE5/SATAGP5
GPP_F3/SATAXPCIE6/SATAGP6
GPP_F4/SATAXPCIE7/SATAGP7

GPP_F21/EDP_BKLTCTL

GPP_F20/EDP_BKLTEN

HOST

GPP_F19/EDP_VDDEN

PLTRST_PROC#

THERMTRIP#

PECI

PM_SYNC

PM_DOWN

G31
H31
C31
B31

G29
E29
C32
B32

F41
E41
B39
A39

D43
E42
A41
A40

H42
H40
E45
F45

K37
G37
G45
G44

AD44
AG36
AG35
AG39
AD35
AD31
AD38
AC43
AB44

W36
W35
W42

PCH_THRMTRIP#_R

AJ3

PCH_PECI

AL3

H_PM_SYNC_R

AJ4

CPU_PLTRST#

AK2

H_PM_DOWN

AH2

PCIE_SATA_PRX_DTX_N9
PCIE_SATA_PRX_DTX_P9
PCIE_SATA_PTX_DRX_N9
PCIE_SATA_PTX_DRX_P9

PCIE_PRX_DTX_N10
PCIE_PRX_DTX_P10
PCIE_PTX_DRX_N10
PCIE_PTX_DRX_P10

Add Reserved HDD cable
HLZ SDV 20160510

Delete HDD Cable SATA signal
HLZ SDV 20160510

SATA_LED#

SSD_DET#

RH34 620_0402_5%
RH35 13_0402_5%
RH13 30_0402_1%

Change RH35 from 43 to 12.1 due to follow DG&CRB
HLZ SDV 0601

1 2

RH15 10K_0402_5%

1 2
1 2
1 2

PCIE_SATA_PRX_DTX_N9 45
PCIE_SATA_PRX_DTX_P9 45
PCIE_SATA_PTX_DRX_N9 45
PCIE_SATA_PTX_DRX_P9 45

PCIE_PRX_DTX_N10 45
PCIE_PRX_DTX_P10 45
PCIE_PTX_DRX_N10 45
PCIE_PTX_DRX_P10 45

SATA_PRX_DTX_N2 46
SATA_PRX_DTX_P2 46
SATA_PTX_DRX_N2 46
SATA_PTX_DRX_P2 46

+3VS

SSD_DET# 45

PCH_EDP_PWM 35
PCH_EDP_ENBKL 35
PCH_EDP_ENVDD 35

H_THRMTRIP# 6,24

H_PM_SYNC 6

CPU_PLTRST# 6

H_PM_DOWN 6

NGFF SSD

NGFF SSD

HDD

HDD Cable

RH781

1 2

@

0_0402_5%

Add RH781_@ for PCH PECI
HLZ SIV 0811

EC_PECI 6,49

B B

CPU_PLTRST#

H_PM_DOWN
PCH_PECI

1 2

CH263 0.1U_0402_25V6 EMC_NS@

1 2

CH6 .1U_0402_10V6-K @

1 2

CH7 .1U_0402_10V6-K @

Reserved Cap HLZ SDV 0616

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND C ONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CEN TER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CEN TER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CEN TER.

5

4

3

2015/02/26

2015/02/26

2015/02/26

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/02/26

2016/02/26

2016/02/26

Title

PCH (1/9) PCIe/SATA/GPPFG

PCH (1/9) PCIe/SATA/GPPFG

PCH (1/9) PCIe/SATA/GPPFG

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

Custom

Custom

Custom

Friday, November 25, 2016

Friday, November 25, 2016

Date: Sheet of

Date: Sheet of

Date: Sheet of

Friday, November 25, 2016

DY512

DY512

DY512

1

14 75

14 75

14 75

1.0

1.0

1.0

5

4

3

2

1

D D

USB30_TX_P147

LEFT USB (3.0)

LEFT USB (3.0)

USB30_RX_N147
USB30_RX_P147
USB30_TX_N247
USB30_TX_P247
USB30_RX_N247
USB30_RX_P247

USB30_TX_N1
USB30_TX_P1
USB30_RX_N1
USB30_RX_P1
USB30_TX_N2
USB30_TX_P2
USB30_RX_N2
USB30_RX_P2

3D Camera

Delete 3D camera
HLZ SDV 20160510

TYPE-C_USB3_TX_P338
TYPE-C_USB3_TX_N338

Type C USB3.0

C C

B B

TYPE-C_USB3_RX_P338
TYPE-C_USB3_RX_N338

Add TypeC USB3
HLZ SDV 20160510

Different to Y710
HLZ SDV 20160510

HDMI_HPD36
TYPE-C_DP_HPD37

PCH_EDP_HPD35

TYPE-C_USB3_TX_P3
TYPE-C_USB3_TX_N3
TYPE-C_USB3_RX_P3
TYPE-C_USB3_RX_N3

PCH_EDP_HPD

UH1F

C11

USB3_1_TXN

B11

USB3_1_TXP

B7

USB3_1_RXN

A7

USB3_1_RXP

B12

USB3_2_TXN/SSIC_1_TXN

A12

USB3_2_TXP/SSIC_1_TXP

C8

USB3_2_RXN/SSIC_1_RXN

B8

USB3_2_RXP/SSIC_1_RXP

B15

USB3_6_TXN

C15

USB3_6_TXP

K15

USB3_6_RXN

K13

USB3_6_RXP

B14

USB3_5_TXN

C14

USB3_5_TXP

G13

USB3_5_RXN

H13

USB3_5_RXP

D13

USB3_3_TXP/SSIC_2_TXP

C13

USB3_3_TXN/SSIC_2_TXN

A9

USB3_3_RXP/SSIC_2_RXP

B10

USB3_3_RXN/SSIC_2_RXN

B13

USB3_4_TXP

A14

USB3_4_TXN

G11

USB3_4_RXP

E11

USB3_4_RXN

SKYLAKE-H-PCH_FCBGA837

@

UH1E

AW4

GPP_I0/DDPB_HPD0

AY2

GPP_I1/DDPC_HPD1

AV4

GPP_I2/DDPD_HPD2

BA4

GPP_I3/DDPE_HPD3

BD7

GPP_I4/EDP_HPD

SKYLAKE-H-PCH_FCBGA837

@

SPT-H_PCH

LPC/eSPI

USB

SATA

6 OF 12

SPT-H_PCH

5 OF 12

GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS0#

GPP_A6/SERIRQ/ESPI_CS1#

GPP_A7/PIRQA#/ESPI_ALERT0#

GPP_A0/RCIN#/ESPI_ALERT1#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

GPP_G19/SMI#
GPP_G18/NMI#

GPP_E6/DEVSLP2
GPP_E5/DEVSLP1
GPP_E4/DEVSLP0
GPP_F9/DEVSLP7
GPP_F8/DEVSLP6
GPP_F7/DEVSLP5
GPP_F6/DEVSLP4
GPP_F5/DEVSLP3

GPP_I7/DDPC_CTRLCLK

GPP_I8/DDPC_CTRLDATA

GPP_I5/DDPB_CTRLCLK

GPP_I6/DDPB_CTRLDATA

GPP_I9/DDPD_CTRLCLK

GPP_I10/DDPD_CTRLDATA

GPP_F14
GPP_F23
GPP_F22

GPP_G23
GPP_G22
GPP_G21
GPP_G20

GPP_H23

BB3
BD6
BA5
BC4
BE5
BE6

Y44
V44
W39

L43
L44
U35
R35
BD36

AT22
AV22
AT19
BD16

BE16
BA17
AW17
AT17
BC18

BC17
AV19

M45
N43

AE45
AG43
AG42
AB39
AB36
AB43
AB42
AB41

DDPC_CLK
DDPC_DATA
DDPB_CLK
DDPB_DATA
DDPD_CLK
DDPD_DATA

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_FRAME#
SERIRQ

KBRST#

CLK_PCI_EC_R
CLK_PCI_TPM_R

PCH_SMI#

DEVSLP0_R

RH84 22_0402_5%
RH87 22_0402_5%TPM@

1

TC110 PAD @

DEVSLP0_R 45

1

PAD @

PAD @

DDPB_CLK 36
DDPB_DATA 36

1

IT28

IT36

LPC_AD0 49,50USB30_TX_N147
LPC_AD1 49,50
LPC_AD2 49,50
LPC_AD3 49,50

LPC_FRAME# 49,50
SERIRQ 49,50

KBRST# 49

1 2
1 2

HDMI

CLK_PCI_EC
CLK_PCI_TPM

1

1

CH266

CH265

EMC_NS@

2

NGFF SSD

2

10P_0402_50V8J

Add Port C/D strap
HLZ SDV 20160510

DDPC_DATA

DDPD_DATA

DDPB_CLK

DDPB_DATA

DDPB_CTRLDATA
The signal has a weak internal pull-down.
H Port B is detected.

*

L Port B is not detected.

DDPC_CTRLDATA
The signal has a weak internal pull-down.
H Port C is detected.

*

L Port C is not detected. (Default)

DDPD_CTRLDATA
The signal has a weak internal pull-down.
H Port D is detected.
L Port D is not detected. (Default)

*

EMC_NS@

10P_0402_50V8J

CLK_PCI_EC 49
CLK_PCI_TPM 50

12

12

12

12

KBRST#
PCH_SMI#

SERIRQ

+3VS

RH82.2K_0402_5%

RH102.2K_0402_5% @

+3VS

RH322.2K_0402_5%

RH332.2K_0402_5%

+3VS

12

RH11310K_0402_5%

12

RH12910K_0402_5% @

+3VS

12

RH10410K_0402_5%

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND C ONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CEN TER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CEN TER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CEN TER.

3

2015/02/26

2015/02/26

2015/02/26

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/02/26

2016/02/26

2016/02/26

Title

PCH (2/9) USB3/GPPAEFGHI

PCH (2/9) USB3/GPPAEFGHI

PCH (2/9) USB3/GPPAEFGHI

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

Custom

Custom

Custom

Friday, November 25, 2016

Friday, November 25, 2016

Date: Sheet of

Date: Sheet of

Date: Sheet of

Friday, November 25, 2016

DY512

DY512

DY512

1

15 75

15 75

15 75

1.0

1.0

1.0

5

PCH_HDA_RST#48
PCH_HDA_SYNC48
PCH_HDA_BIT_CLK48
PCH_HDA_SDOUT48

D D

PROC_AUDIO_SDO_CPU8

PROC_AUDIO_SDI_CPU8

PROC_AUDIO_CLK_CPU8

C C

Change RH56 from stuff to @
HLZ SIV 0811

+3VALW_PCH

B B

+3VALW_PCH

A A

1 2

RH56 10K_0402_5%@

+3VALW

1 2

RH17 10K_0402_5%

1 2

RH58 10K_0402_5%

1 2

RH60 10K_0402_5%

1 2

RH80 1K_0402_5%

1 2

RH747 20K_0402_5%

+3VS

1 2

RH67 10K_0402_5%

1 2

RH65 8.2K_0402_5%

1 2

RH16 100K_0402_5%
RH54 10K_0402_5%

1 2

RH59 10K_0402_5%

1 2

RH61 100K_0402_5%@

1 2

RH101 2.2K_0402_5%

1 2

RH102 2.2K_0402_5%

1 2

RH765 2.2K_0402_5%

1 2

RH766 2.2K_0402_5%

1 2

RH767 2.2K_0402_5%

SMBALERT# / GPP_C2
0 = Disable Intel ME Crypto Transport Layer Security
(TLS) cipher suite (no confidentiality). (Default)
1 = Enable Intel ME Crypto Transport Layer Security
(TLS) cipher suite (with confidentiality). Must be
pulled up to support Intel AMT with TLS and Intel
SBA (Small Business Advantage) with TLS.

SML0ALERT# / GPP_C5
0 = LPC Is selected for EC. (Default)
1 = eSPI Is selected for EC.

SML1ALERT# / PCHHOT#/GPP_B23
This signal has an internal pull-down

PCH_HDA_RST# HDA_RST#

ME_FLASH49

PROC_AUDIO_SDI_CPU
PROC_AUDIO_CLK_CPU PROC_AUDIO_CLK_PCH

Change PM_PWRBTN#_R PWR

HLZ SDV 0606

12

SMB_ALERT#

@
@

SMB0_ALERT#
SMB1_ALERT#

12

CH12.1U_0402_10V6-K@

12

CH21.1U_0402_10V6-K@

RPH1

1 8
2 7
3 6
4 5

33_0804_8P4R_5%

1

CH77
100P_0402_50V8J

2

EMC_NS@

PCH_PWROK42,49

EC_RSMRST#42,49

DPWROK_EC49

SUSWARN#

PM_PWRBTN#_R

PCH_AC_PRESENT_R

BATLOW#
WAKE#
PCH_LAN_WAKE#

SYS_RESET#
PM_CLKRUN#

SYS_PWROK_R
PCH_PWROK
PCH_RSMRST#_R
PCH_DPWROK_R

SML0CLK
SML0DATA

1 2

RH768 2.2K_0402_5%

1 2

RH769 2.2K_0402_5%

1 2

RH770 2.2K_0402_5%

EC_RSMRST#
PROC_AUDIO_SDI_CPU

HDA_SYNCPCH_HDA_SYNC
HDA_BIT_CLKPCH_HDA_BIT_CLK
HDA_SDOUTPCH_HDA_SDOUT

For EMC

PCH_HDA_SDIN048

1 2

RH9 0_0402_5%

RH754
RH755

12

30_0402_1%

12

30_0402_1%

PLACE NEAR PCH

PCH_RTCRST#49

1 2

RH12 0_0402_5%

1 2

RH14 0_0402_5%

1 2

RH239 0_0402_5%

1 2

RH68 0_0402_5%@

SMB1_ALERT#44

@
@
@

Strap

HDA_BIT_CLK
HDA_RST#
PCH_HDA_SDIN0

HDA_SDOUT
HDA_SYNC

Reserved Cap HLZ SDV 0616

5

4

UH1D

BA9

HDA_BCLK

BD8

HDA_RST#

BE7

HDA_SDI0

BC8

HDA_SDI1

BB7

HDA_SDO

BD9

HDA_SYNC

BD1

RSVD_BD1

BE2

PROC_AUDIO_SDO_PCHPROC_AUDIO_SDO_CPU

PCH_RTCRST#
PCH_SRTCRST#

PCH_PWROK_R
PCH_RSMRST#_R

PCH_DPWROK_R
SMB_ALERT#
PCH_SMBCLK
PCH_SMBDATA
SMB0_ALERT#
SML0CLK
SML0DATA
SMB1_ALERT#
SML1CLK
SML1DATA

*

RSVD_BE2

AM1

DISPA_SDO

AN2

DISPA_SDI

AM2

DISPA_BCLK

AL42

GPP_D8/I2S0_SCLK

AN42

GPP_D7/I2S0_RXD

AM43

GPP_D6/I2S0_TXD

AJ33

GPP_D5/I2S0_SFRM

AH44

GPP_D20/DMIC_DATA0

AJ35

GPP_D19/DMIC_CLK0

AJ38

GPP_D18/DMIC_DATA1

AJ42

GPP_D17/DMIC_CLK1

BC10

RTCRST#

BB10

SRTCRST#

AW11

PCH_PWROK

BA11

RSMRST#

AV11

DSW_PWROK

BB41

GPP_C2/SMBALERT#

AW44

GPP_C0/SMBCLK

BB43

GPP_C1/SMBDATA

BA40

GPP_C5/SML0ALERT#

AY44

GPP_C3/SML0CLK

BB39

GPP_C4/SML0DATA

AT27

GPP_B23/SML1ALERT#/PCHHOT#

AW42

GPP_C6/SML1CLK

AW45

GPP_C7/SML1DATA

SKYLAKE-H-PCH_FCBGA837

@

W=20mils W=20mils

VCCRTC +RTCVCC

+3VALW_PCH

SPKR / GPP_B1
The signal has a weak internal pull-down.
0 = Disable ¨Top Swap
1 = Enable ¨Top Swa
on access to SPI and firmware hub, so the processor
believes it fetches the alternate boot block instead of
the original boot-block. PCH will invert A16 (default
for cycles going to the upper two 64-KB blocks in the
FWH or the appropriate address lines (A16, A17, o
A18) as selected in Top Swap Block size soft stra
(handled through FITC).

1 2

RH2 0_0402_5%

1 2

RH28

@

1K_0402_5%

4

p〃 mode. This inverts an addres

mode. (Default)

〃

PCH is Master PCH is salve

1 2

+3VALW_PCH

4

RH114 2.2K_0402_5%

1 2

RH116 2.2K_0402_5%

PCH_SMBCLK

PCH_SMBDATA

AUDIO

SPT-H_PCH

GPP_A12/BMBUSY#/ISH_GP6/SX_EXIT_HOLDOFF#

GPP_A13/SUSWARN#/SUSPWRDNACK

SMBUS

JTAG

4 OF 12

1

CH1

1U_0402_6.3V6K

CD@

2

PCH_BEEP

s

)

r
p

+3VS

2

G

6 1

D

5

QH1A 2N7002KDWH_SOT363-6

G

3 4

S

D

QH1B 2N7002KDWH_SOT363-6

3

ADD PM_CLKRUN# for Nuvoton TPM

HLZ SIT 0920

BB17

PM_CLKRUN#

GPP_A8/CLKRUN#
GPD11/LANPHYPC
GPD9/SLP_WLAN#

DRAM_RESET#

GPP_B2/VRALERT#

GPP_B1

GPP_G17/ADR_COMPLETE

GPP_B0

GPP_B11

SYS_PWROK

WAKE#

GPD6/SLP_A#

SLP_LAN#

GPP_B12/SLP_S0#

GPD4/SLP_S3#
GPD5/SLP_S4#

GPD10/SLP_S5#

GPD8/SUSCLK

GPD0/BATLOW#

GPP_A15/SUSACK#

GPD2/LAN_WAKE#

GPD1/ACPRESENT

SLP_SUS#

GPD3/PWRBTN#

SYS_RESET#

GPP_B14/SPKR

PROCPWRGD

ITP_PMODE

JTAGX
JTAG_TMS
JTAG_TDO

JTAG_TDI

JTAG_TCK

AW22
AR15
AV13

PCH_DRAMRST#

BC14
BD23
AL27
AR27
N44
AN24

SYS_PWROK_R

AY1
BC13

WAKE#
SLP_A#

BC15

SLP_LAN#

AV15

SLP_S0

BC26

PM_SLP_S3#_R

AW15

PM_SLP_S4#_R

BD15

PM_SLP_S5#_R

BA13
AN15

SUSCLK

BD13

BATLOW#
SUSACK#_R

BB19

SUSWARN#_R

BD19

PCH_LAN_WAKE#

BD11

PCH_AC_PRESENT_R

BB15

PM_SLP_SUS#_R

BB13

PM_PWRBTN#_R

AT13

SYS_RESET#

AW1

PCH_BEEP

BD26

H_CPUPWRGD

AM3
AT2

AR3
AR2
AP1
AP2
AN3

1
1
1

1

PM_CLKRUN# 50

PAD @

TH30

PAD @

TH31

PAD @

TH32

PAD @

TH33

JTAGX 42

PCH_TMS 42

PCH_TDO 42

PCH_TDI 42
PCH_TCK 42

1 2

RH193 0_0402_5%

1 2

RH69 0_0402_5%

1 2

RH70 0_0402_5%

1 2

RH71 0_0402_5%

1 2

1 2
1 2
1 2

12

RH66 0_0402_5%@
RH74 0_0402_5%

RH76 0_0402_5%
RH77 0_0402_5%@
RH75 0_0402_5%

CMOS

Total Length 8000 mils

+RTCVCC

1U_0402_6.3V6K

1 2

RH3 20K_0402_5%

1 2

RH4 20K_0402_5%

1U_0402_6.3V6K

1

CH4

CH5

12

JME1

@

SHORT PADS

2

1

12

2

JCMOS1
SHORT PADS@

PCH_SRTCRST#

1

PAD @

PCH_RTCRST#

TC111

Place JUMPER under RAM door

AS EMC request

PCH_PWROK SYS_PWROK_R PCH_DPWROK_R

CH83

.1U_0402_10V6-K

EMC_NS@

1

2

.1U_0402_10V6-K

CH84

EMC_NS@

1

2

.1U_0402_10V6-K

DIMM1, DIMM2, Mini CARD, TP

2015/02/26

2015/02/26

2015/02/26

+3VS

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

2N7002KDWH
Vth= min 1V, max 2.5V
ESD 2KV

SMB_CLK_S3

S

SMB_DATA_S3

3

1 2

RH115 2.2K_0402_5%

1 2

RH117 2.2K_0402_5%

SMB_CLK_S3 12,13,45,50

SMB_DATA_S3 12,13,45,50

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

CH85

EMC_NS@

+3VALW_PCH

1

2

Deciphered Date

Deciphered Date

Deciphered Date

2

+1.2V

12

RH756
470_0402_5%

PCH_DRAMRST# 12,13

SYS_PWROK 42,49

PCIE_WAKE# 45,49

PM_SLP_S3# 49
PM_SLP_S4# 49

SUSCLK 45
SUSACK# 49

SUSWARN# 49

AC_PRESENT 49
PM_SLP_SUS# 49

PBTN_OUT# 49
SYS_RESET# 42
PCH_BEEP 48
H_CPUPWRGD 6

SUSACK#_R
SUSWARN#_R

Add Testpad for Box RTC discharge Hai SVT 1118

2

*

1 2

RH121 2.2K_0402_5%

1 2

RH122 2.2K_0402_5%

SML1CLK

SML1DATA

2016/02/26

2016/02/26

2016/02/26

+3VALW_PCH

+3VALW_PCH

1 2

RH25 1K_0402_5%@

HDA_SDO This signal has a weak internal pull-down.
0 = Enable security measures defined in the Flash Descript or.
1 = Disable Flash Descriptor Security (override) . This
strap should only be asserted high using external pull­ up in manufacturing/debug environments ONLY.

1 2

RH31 1K_0402_5%@

2

G

6 1

D

5

QH2A 2N7002KDWH_SOT363-6

G

3 4

S

D

QH2B 2N7002KDWH_SOT363-6

Title

Title

Title

PCH (3/9) HDA,RTC,SMBUS,PM

PCH (3/9) HDA,RTC,SMBUS,PM

PCH (3/9) HDA,RTC,SMBUS,PM

Size

Size

Size

Document Number Rev

Document Number Rev

Document Number Rev

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

ME_FLASH

HDA_SYNC

+3VS

EC_SMB_CK2

S

EC_SMB_DA2

Friday, November 25, 2016

Friday, November 25, 2016

Friday, November 25, 2016

1

CRB Reserve

1 2

RH745 0_0402_5%

GPU, EC, Thermal Sensor

EC_SMB_CK2 27,44,49

EC_SMB_DA2 27,44,49

DY512

DY512

DY512

1

16 75

16 75

16 75

1.0

1.0

1.0

5

4

3

2

1

UH1G

AR17

D D

+1.0VALW

1 2

RH198 0_0402_5%

Delete TBT CLK REQ
HLZ SDV 20160510

+3VS

C C

1 2

RH89 10K_0402_5%

1 2

RH90 10K_0402_5%

1 2

RH91 10K_0402_5%

1 2

RH93 10K_0402_5%

1 2

RH94 10K_0402_5%

XTAL24_OUT

B B

LAN_CLKREQ#
WLAN_CLKREQ#
CR_CLKREQ#
SSD_CLKREQ#
GPU_CLKREQ#

RH92 1M_0402_5%

1

1

CH9

3.9P_0402_50V8-B

2

YH2

24MHZ_6PF_7V24000032

PCH_CPU_NSSC_CLK6

PCH_CPU_NSSC_CLK#6

PCH_CPU_BCLK6

+VCCCLK

GND12OSC2
OSC1

PCH_CPU_BCLK#6

RH6 2.7K_0402_1%

Delete TBT CLK REQ
HLZ SDV 20160510

12

3
4

GND2

1 2

CR_CLKREQ#43

WLAN_CLKREQ#45

LAN_CLKREQ#50

SSD_CLKREQ#45

GPU_CLKREQ#24

XTAL24_IN

1

CH10

3.9P_0402_50V8-B

2

XTAL24_OUT
XTAL24_IN

PCH_CLK_BIASREF
PCH_RTCX1

PCH_RTCX2

CR_CLKREQ#
WLAN_CLKREQ#
LAN_CLKREQ#

SSD_CLKREQ#

GPU_CLKREQ#

GPP_A16/CLKOUT_48

G1

CLKOUT_CPUNSSC_P

F1

CLKOUT_CPUNSSC

G2

CLKOUT_CPUBCLK_P

H2

CLKOUT_CPUBCLK

A5

XTAL24_OUT

A6

XTAL24_IN

E1

XCLK_BIASREF

BC9

RTCX1

BD10

RTCX2

BC24

GPP_B5/SRCCLKREQ0#

AW24

GPP_B6/SRCCLKREQ1#

AT24

GPP_B7/SRCCLKREQ2#

BD25

GPP_B8/SRCCLKREQ3#

BB24

GPP_B9/SRCCLKREQ4#

BE25

GPP_B10/SRCCLKREQ5#

AT33

GPP_H0/SRCCLKREQ6#

AR31

GPP_H1/SRCCLKREQ7#

BD32

GPP_H2/SRCCLKREQ8#

BC32

GPP_H3/SRCCLKREQ9#

BB31

GPP_H4/SRCCLKREQ10#

BC33

GPP_H5/SRCCLKREQ11#

BA33

GPP_H6/SRCCLKREQ12#

AW33

GPP_H7/SRCCLKREQ13#

BB33

GPP_H8/SRCCLKREQ14#

BD33

GPP_H9/SRCCLKREQ15#

R13

CLKOUT_PCIE_N15

R11

CLKOUT_PCIE_P15

P1

CLKOUT_PCIE_N14

R2

CLKOUT_PCIE_P14

W7

CLKOUT_PCIE_N13

Y5

CLKOUT_PCIE_P13

U2

CLKOUT_PCIE_N12

U3

CLKOUT_PCIE_P12

SKYLAKE-H-PCH_FCBGA837

@

SPT-H_PCH

CLKOUT_ITPXDP_P

CLKOUT_CPUPCIBCLK

CLKOUT_CPUPCIBCLK_P

CLKOUT_PCIE_N0
CLKOUT_PCIE_P0

CLKOUT_PCIE_N1
CLKOUT_PCIE_P1

CLKOUT_PCIE_N2
CLKOUT_PCIE_P2

CLKOUT_PCIE_N3
CLKOUT_PCIE_P3

CLKOUT_PCIE_N4
CLKOUT_PCIE_P4

CLKOUT_PCIE_N5
CLKOUT_PCIE_P5

CLKOUT_PCIE_N6
CLKOUT_PCIE_P6

CLKOUT_PCIE_N7
CLKOUT_PCIE_P7

CLKOUT_PCIE_N8
CLKOUT_PCIE_P8

CLKOUT_PCIE_N9
CLKOUT_PCIE_P9

CLKOUT_PCIE_N10
CLKOUT_PCIE_P10

CLKOUT_PCIE_N11

RH1

1 2

10M_0402_5%
YH1

1 2

CLKOUT_PCIE_P11

7 OF 12

32.768KHZ_9PF_X1A0001410002

1

CH2
10P_0402_50V8J

2

CLKOUT_ITPXDP

L1
L2

J1
J2

N7
N8

L7
L5

D3
F2

E5
G4

D5
E6

D8
D7

R8
R7

U5
U7

W10
W11

N3
N2

P3
P2

R3
R4

PCH_RTCX1

PCH_RTCX2

1

CH3
10P_0402_50V8J

2

CLK_PCIE_CR#
CLK_PCIE_CR

CLK_PCIE_WLAN#
CLK_PCIE_WLAN

CLK_PCIE_LAN#
CLK_PCIE_LAN

CLK_PCIE_SSD#
CLK_PCIE_SSD

CLK_PCIE_GPU#
CLK_PCIE_GPU

PCH_CPU_PCIBCLK# 6
PCH_CPU_PCIBCLK 6

CLK_PCIE_CR# 43

CLK_PCIE_CR 43

CLK_PCIE_WLAN# 45

CLK_PCIE_WLAN 45

CLK_PCIE_LAN# 50

CLK_PCIE_LAN 50

CLK_PCIE_SSD# 45

CLK_PCIE_SSD 45

Delete TBT CLK
HLZ SDV 20160510

CLK_PCIE_GPU# 24
CLK_PCIE_GPU 24

CR

WLAN

LAN

M.2 SSD

GPU

Change CH9 & CH10 from 3.3P to 3.9P HLZ SIT 0921 Change CH2 & CH3 from 6.8P to 10P HLZ SIT 0921

Change CH9 & CH10 from 4.7P to 3.3P HLZ SIV 0811 Change YH1 based on common pool HLZ SIV 0811

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND C ONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CEN TER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CEN TER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CEN TER.

3

2015/02/26

2015/02/26

2015/02/26

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/02/26

2016/02/26

2016/02/26

Title

PCH (3/9) CLOCK,GPPBH

PCH (3/9) CLOCK,GPPBH

PCH (3/9) CLOCK,GPPBH

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

Custom

Custom

Custom

Friday, November 25, 2016

Friday, November 25, 2016

Date: Sheet of

Date: Sheet of

Date: Sheet of

Friday, November 25, 2016

DY512

DY512

DY512

1

17 75

17 75

17 75

1.0

1.0

1.0

5

4

3

2

1

UH1A

BD17

GPP_A11/PME#

AG15

RSVD_1

AG14

RSVD_2

AF17

D D

SPI_CLK_PCH_0
SPI_CLK_PCH_1

1

CH267

10P_0402_50V8J

2

EMC_NS@

SPI_CLK_PCH_049

SPI_CS0#_R49

SPI_SI_R049

SPI_SO_R049

SPI_CLK_PCH_0
SPI_CLK_PCH_1

SPI_CS0#_R
SPI_CS1#_R

SPI_SI_R0
SPI_SI_R1 SPI_SI

SPI_SO_R0
SPI_SO_R1

SPI_WP#_R0
SPI_WP#_R1 SPI_WP#

SPI_HOLD#_R0
SPI_HOLD#_R1

1

CH268

10P_0402_50V8J

2

EMC_NS@

1 2

RH105 33_0402_5%

1 2

RH106 33_0402_5%

1 2

RH107 0_0402_5%

1 2

RH108 0_0402_5%

1 2

RH109 33_0402_5%

1 2

RH110 33_0402_5%

1 2

RH111 33_0402_5%

1 2

RH112 33_0402_5%

1 2

RH250 33_0402_5%

1 2

RH249 33_0402_5%

1 2

RH252 33_0402_5%

1 2

RH251 33_0402_5%

SPI_CLK_PCH
SPI_CS0#
SPI_CS1#

SPI_SO

SPI_HOLD#

1

PAD @

TC107

1

PAD @

TC108

SPI_SI
SPI_SO
SPI_CS0#
SPI_CLK_PCH
SPI_CS1#

SPI_WP#42

SPI_WP#
SPI_HOLD#

RSVD_3

AE17

RSVD_4

AR19

TP2

AN17

TP1

BB29

SPI0_MOSI

BE30

SPI0_MISO

BD31

SPI0_CS0#

BC31

SPI0_CLK

AW31

SPI0_CS1#

BC29

SPI0_IO2

BD30

SPI0_IO3

AT31

SPI0_CS2#

AN36

GPP_D1/SPI1_CLK

AL39

GPP_D0/SPI1_CS#

AN41

GPP_D3/SPI1_MOSI

AN38

GPP_D2/SPI1_MISO

AH43

GPP_D22/SPI1_IO3

AG44

GPP_D21/SPI1_IO2

SKYLAKE-H-PCH_FCBGA837

@

SPT-H_PCH

GPP_G12/GSXDOUT

GPP_G13/GSXSLOAD

GPP_G15/GSXSRESET#

GPP_H18/SML4ALERT#

GPP_H17/SML4DATA

GPP_H16/SML4CLK

GPP_H15/SML3ALERT#

GPP_H14/SML3DATA

GPP_H13/SML3CLK

GPP_H12/SML2ALERT#

GPP_H11/SML2DATA

GPP_H10/SML2CLK

1 OF 12

GPP_B13/PLTRST#

GPP_G16/GSXCLK

GPP_G14/GSXDIN

GPP_E3/CPU_GP0
GPP_E7/CPU_GP1
GPP_B3/CPU_GP2
GPP_B4/CPU_GP3

INTRUDER#

PLT_RST#

BB27

P43
R39
R36
R42
R41

AF41
AE44
BC23
BD24

BC36
BE34
BD39
BB36
BA35
BC35
BD35

RH753 4.7K_0402_5%

AW35
BD34

BE11

RH743 1M_0402_5%

12

RH43
100K_0402_5%

@

1 2

PLT_RST# 27,42,43,45,49,50

+3VS

12

GPP_H12
This strap should sample LOW. There should NOT be any
on-board device driving it to opposite direction during
strap sampling.

+RTCVCC

500mA500mA

SPI_CLK_PCH_1

SPI_CLK_PCH_0

+3V_SPI+3VALW_PCH

RH742

1 2

10_0402_5%

EMC_NS@

RH119

1 2

10_0402_5%

EMC_NS@

1

CH247

10P_0402_50V8J

2

EMC_NS@

1

CH11

10P_0402_50V8J

2

EMC_NS@

C C

RH771 1K_0402_5%

SPI_HOLD#

SPI0_MOSI
SPI0_MISO
This signal has an internal pull-up.
This strap should sample HIGH. There should NOT be any
on-board device driving it to opposite direct ion during
strap sampling.

64Mb Flash ROM

SPI_CS0#_R
SPI_SO_R0
SPI_WP#_R0

B B

Change UC3 Value from W25Q64FVSSIG_SO8 to W25Q64FVSSIQ_SO8
HLZ SIV 0811

UC3

1

CS#

2

DO

HOLD#

3

WP#

4

GND

W25Q64FVSSIQ_SO8

8

VCC

SPI_HOLD#_R0

7

SPI_CLK_PCH_0

6

CLK

SPI_SI_R0

5

DI

250mA

+3V_SPI

1

2

1 2

@

CH13
.1U_0402_10V6-K

Delete socket

+3VALW_PCH

RH123 1K_0402_5%
RH125 1K_0402_5%
RH772 1K_0402_5%
RH773 1K_0402_5%

32Mb Flash ROM

SPI_CS1#_R

1

SPI_SO_R1

2

SPI_WP#_R1

3
4

1 2
1 2
1 2

@

1 2

@

UC7

CS#

VCC

DO

HOLD#

WP#

CLK

GND

DI

W25Q32FVSSIQ_SO8

Delete socket

8
7
6
5

SPI_WP#
SPI_HOLD#
SPI_SO
SPI_SI

SPI_HOLD#_R1
SPI_CLK_PCH_1
SPI_SI_R1

250mA

+3V_SPI

1

CH246
.1U_0402_10V6-K

2

+3VS

+3V_SPI

1. If support DS3, connect to +3VS and don't s uppor t EC mir r or c ode;

2. If don't support DS3, connect to +3VALW_PCH and support EC mirror code.

*

1 2

RC171 0_0402_5%

1 2

RC172 0_0402_5%@

For EMI

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2015/02/26

2015/02/26

2015/02/26

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2016/02/26

2016/02/26

2016/02/26

2

Title

PCH (5/9) SPI,SMBUS,GPPBEGH

PCH (5/9) SPI,SMBUS,GPPBEGH

PCH (5/9) SPI,SMBUS,GPPBEGH

Size

Size

Size

Document Number Rev

Document Number Rev

Document Number Rev

Custom

Custom

Custom

Friday, November 25, 2016

Friday, November 25, 2016

Friday, November 25, 2016

Date: Sheet of

Date: Sheet of

Date: Sheet of

DY512

DY512

DY512

1

18 75

18 75

18 75

1.0

1.0

1.0

5

D D

4

3

2

1

DMI_CTX_PRX_N05
DMI_CTX_PRX_P05
DMI_CRX_PTX_N05
DMI_CRX_PTX_P05
DMI_CTX_PRX_N15
DMI_CTX_PRX_P15
DMI_CRX_PTX_N15
DMI_CRX_PTX_P15
DMI_CTX_PRX_N25
DMI_CTX_PRX_P25
DMI_CRX_PTX_N25
DMI_CRX_PTX_P25
DMI_CTX_PRX_N35
DMI_CTX_PRX_P35
DMI_CRX_PTX_N35

CADNote:
Trace width=15mils ,Spacing=15mil

C C

Cardreader

WLAN

LAN

Thunderbolt
x 4

B B

PCIE_PTX_C_DRX_N243
PCIE_PTX_C_DRX_P243
PCIE_PRX_DTX_N243
PCIE_PRX_DTX_P243
PCIE_PRX_DTX_N345
PCIE_PRX_DTX_P345
PCIE_PTX_C_DRX_N345
PCIE_PTX_C_DRX_P345
PCIE_PRX_DTX_N450
PCIE_PRX_DTX_P450
PCIE_PTX_C_DRX_N450
PCIE_PTX_C_DRX_P450

Maxlength=N/Amils.

DMI_CRX_PTX_P35

1 2

CH240 .1U_0402_10V6-K

1 2

CH241 .1U_0402_10V6-K

1 2

CH17 .1U_0402_10V6-K

1 2

CH18 .1U_0402_10V6-K

1 2

CH15 .1U_0402_10V6-K

1 2

CH16 .1U_0402_10V6-K

HLZ SDV 20160510

RH741

DMI_CTX_PRX_N0
DMI_CTX_PRX_P0
DMI_CRX_PTX_N0
DMI_CRX_PTX_P0
DMI_CTX_PRX_N1
DMI_CTX_PRX_P1
DMI_CRX_PTX_N1
DMI_CRX_PTX_P1
DMI_CTX_PRX_N2
DMI_CTX_PRX_P2
DMI_CRX_PTX_N2
DMI_CRX_PTX_P2
DMI_CTX_PRX_N3
DMI_CTX_PRX_P3
DMI_CRX_PTX_N3
DMI_CRX_PTX_P3

100_0402_1%

1 2

PCIE_PTX_DRX_N2
PCIE_PTX_DRX_P2
PCIE_PRX_DTX_N2
PCIE_PRX_DTX_P2
PCIE_PRX_DTX_N3
PCIE_PRX_DTX_P3
PCIE_PTX_DRX_N3
PCIE_PTX_DRX_P3
PCIE_PRX_DTX_N4
PCIE_PRX_DTX_P4
PCIE_PTX_DRX_N4
PCIE_PTX_DRX_P4

PCIE_RCOMN

PCIE_RCOMP

UH1B

L27

DMI_RXN0

N27

DMI_RXP0

C27

DMI_TXN0

B27

DMI_TXP0

E24

DMI_RXN1

G24

DMI_RXP1

B28

DMI_TXN1

A28

DMI_TXP1

G27

DMI_RXN2

E26

DMI_RXP2

B29

DMI_TXN2

C29

DMI_TXP2

L29

DMI_RXN3

K29

DMI_RXP3

B30

DMI_TXN3

A30

DMI_TXP3

B18

PCIE_RCOMPN

C17

PCIE_RCOMPP

H15

PCIE1_RXN/USB3_7_RXN

G15

PCIE1_RXP/USB3_7_RXP

A16

PCIE1_TXN/USB3_7_TXN

B16

PCIE1_TXP/USB3_7_TXP

B19

PCIE2_TXN/USB3_8_TXN

C19

PCIE2_TXP/USB3_8_TXP

E17

PCIE2_RXN/USB3_8_RXN

G17

PCIE2_RXP/USB3_8_RXP

L17

PCIE3_RXN/USB3_9_RXN

K17

PCIE3_RXP/USB3_9_RXP

B20

PCIE3_TXN/USB3_9_TXN

C20

PCIE3_TXP/USB3_9_TXP

E20

PCIE4_RXN/USB3_10_RXN

G19

PCIE4_RXP/USB3_10_RXP

B21

PCIE4_TXN/USB3_10_TXN

A21

PCIE4_TXP/USB3_10_TXP

K19

PCIE5_RXN

L19

PCIE5_RXP

D22

PCIE5_TXN

C22

PCIE5_TXP

G22

PCIE6_RXN

E22

PCIE6_RXP

B22

PCIE6_TXN

A23

PCIE6_TXP

L22

PCIE7_RXN

K22

PCIE7_RXP

C23

PCIE7_TXN

B23

PCIE7_TXP

K24

PCIE8_RXN

L24

PCIE8_RXP

C24

PCIE8_TXN

B24

PCIE8_TXP

SKYLAKE-H-PCH_FCBGA837

@

SPT-H_PCH

DMI

PCIe/USB 3

USB 2.0

2 OF 12

USB2N_1
USB2P_1
USB2N_2
USB2P_2
USB2N_3
USB2P_3
USB2N_4
USB2P_4
USB2N_5
USB2P_5
USB2N_6
USB2P_6
USB2N_7
USB2P_7
USB2N_8
USB2P_8
USB2N_9

USB2P_9
USB2N_10
USB2P_10
USB2N_11
USB2P_11
USB2N_12
USB2P_12
USB2N_13
USB2P_13
USB2N_14
USB2P_14

GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#

GPP_F15/USB2_OCB_4
GPP_F16/USB2_OCB_5
GPP_F17/USB2_OCB_6
GPP_F18/USB2_OCB_7

USB2_COMP

USB2_VBUSSENSE

RSVD_AB13

USB2_ID

GPD7/RSVD

AF5
AG7
AD5
AD7
AG8
AG10
AE1
AE2
AC2
AC3
AF2
AF3
AB3
AB2
AL8
AL7
AA1
AA2
AJ8
AJ7
W2
W3
AD3
AD2
V2
V1
AJ11
AJ13

AD43
AD42
AD39
AC44
Y43
Y41
W44
W43

AG3
AD10
AB13
AG2

BD14

USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2

Del TS HLZ SDV 20160510

USB20_N6
USB20_P6

Some PCH config not support USB port 6 & 7.

Del XBOX & Anti-ghost HLZ SDV 20160510

1

TH28

1

USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#

USB2_ COMP

TH29

USB20_N10
USB20_P10

USB20_N0 50
USB20_P0 50
USB20_N1 47
USB20_P1 47
USB20_N2 47
USB20_P2 47
TYPE-C_PCH_USB20_N4 38
TYPE-C_PCH_USB20_P4 38

USB20_N6 35
USB20_P6 35

PAD@
PAD@

USB20_N10 45
USB20_P10 45

USB_OC1# 47
USB_OC2# 50
USB_OC3# 38

Within 500 mils

RC183
1K_0402_5%

1 2

1 2

RIGHT USB (2.0)

LEFT USB (3.0)
LEFT USB (3.0)

Type C

Camera

Debug port, reserved test point

Buletooth

USB 3.0
USB 2.0
TypeC

RC182
1K_0402_5%

RH127
113_0402_1%

1 2

USB_OC4#
USB_OC7#
USB_OC6#
USB_OC3#

USB_OC0#
USB_OC5#
USB_OC2#
USB_OC1#

4 5
3 6
2 7
1 8

4 5
3 6
2 7
1 8

+3VALW_PCH

RPH5

10K_1206_8P4R_5%
RPH6

10K_1206_8P4R_5%

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND C ONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CEN TER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CEN TER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CEN TER.

3

2015/02/26

2015/02/26

2015/02/26

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/02/26

2016/02/26

2016/02/26

Title

PCH (5/9) DMI, PCIe, USB2, GPPEF

PCH (5/9) DMI, PCIe, USB2, GPPEF

PCH (5/9) DMI, PCIe, USB2, GPPEF

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

Custom

Custom

Custom

Friday, November 25, 2016

Friday, November 25, 2016

Date: Sheet of

Date: Sheet of

Date: Sheet of

Friday, November 25, 2016

DY512

DY512

DY512

1

19 75

19 75

19 75

1.0

1.0

1.0

5

+3VS

PCH_BT_OFF#
PCH_WLAN_OFF#

+3VALW_PCH +3VALW_PCH

RH750

PCH_WLAN_OFF#

EC_SCI#
PCH_BT_OFF#

PCH_GPIO5227

PCH_GPIO5327

2

G

1 2

GPP_B18_NO_REBOOT

1 2

RH780 0_0402_5%

VGA_ALERT_PCH#

12

DV5 RB751V-40_SOD323-2

@

PCH_UART2_TXD
PCH_UART2_RXD

PCH_GPIO52
PXS_PWREN_R
PXS_RST#_R
PCH_GPIO53

13

D

QC13
2N7002KW_SOT323-3

@

S

1 2
1 2

1 2

@

0_0402_5%

CC96

12
12

1

@

2

RH160 10K_0402_5%
RH161 10K_0402_5%

GPP_B18_NO_REBOOT42

PXS_PWREN
PXS_RST#

PCH_WLAN_OFF#45

LAN_PWR_ON#50

PCH_BT_OFF#45

PCH_UART2_TXD45

PCH_UART2_RXD45

EC_SCI#14,49

VGA_PWRGD24,27

VGA_ALERT#27

RC10 0_0402_5%OPT@
RC12 0_0402_5%

RC170

.1U_0402_10V6-K

D D

Delete PCH_TS_ON# signal

HLZ SDV 0606

Delete 3D_FR & PCH_CMOS_ON signal

HLZ SDV 0606

Change RC10 from 1K to 0ohm HLZ SIV 0811

C C

PXS_PWREN27,28,70
PXS_RST#27

VGA_GATE#49

4

GSPI1_MOSI / GPP_B22
This field determines the destination of accesses to the
BIOS memory range. Also controllable using Boot BIOS
Destination bit (Bus0, Device31, Function0, offset BCh,
bit 6).

@

@

4.7K_0402_5%

UH1K

AT29

GPP_B22/GSPI1_MOSI

AR29

GPP_B21/GSPI1_MISO

AV29

GPP_B20/GSPI1_CLK

BC27

GPP_B19/GSPI1_CS#

BD28

GPP_B18/GSPI0_MOSI

BD27

GPP_B17/GSPI0_MISO

AW27

GPP_B16/GSPI0_CLK

AR24

GPP_B15/GSPI0_CS#

AV44

GPP_C9/UART0_TXD

BA41

GPP_C8/UART0_RXD

AU44

GPP_C11/UART0_CTS#

AV43

GPP_C10/UART0_RTS#

AU41

GPP_C15/UART1_CTS#/ISH_UART1_CTS#

AT44

GPP_C14/UART1_RTS#/ISH_UART1_RTS#

AT43

GPP_C13/UART1_TXD/ISH_UART1_TXD

AU43

GPP_C12/UART1_RXD/ISH_UART1_RXD

AN43

GPP_C23/UART2_CTS#

AN44

GPP_C22/UART2_RTS#

AR39

GPP_C21/UART2_TXD

AR45

GPP_C20/UART2_RXD

AR41

GPP_C19/I2C1_SCL

AR44

GPP_C18/I2C1_SDA

AR38

GPP_C17/I2C0_SCL

AT42

GPP_C16/I2C0_SDA

AM44

GPP_D4/ISH_I2C2_SDA/ISH_I2C3_SDA

AJ44

GPP_D23/ISH_I2C2_SCL/ISH_I2C3_SCL

SKYLAKE-H-PCH_FCBGA837

@

SPT-H_PCH

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C2_SCL

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C2_SDA

11 OF 12

3

GPP_D10
GPP_D11

GPP_D16/ISH_UART0_CTS#
GPP_D15/ISH_UART0_RTS#

GPP_D12

GPP_H20/ISH_I2C0_SCL
GPP_H19/ISH_I2C0_SDA

GPP_H22/ISH_I2C1_SCL
GPP_H21/ISH_I2C1_SDA

GPP_A23/ISH_GP5
GPP_A22/ISH_GP4
GPP_A21/ISH_GP3
GPP_A20/ISH_GP2
GPP_A19/ISH_GP1
GPP_A18/ISH_GP0
GPP_A17/ISH_GP7

GPP_D9

AL44
AL36
AL35
AJ39

AJ43
AL43
AK44
AK45

BC38
BB38

BD38
BE39

BC22
BD18
BE21
BD22
BD21
BB22
BC19

PCH_GPD9
PCH_GPD10
PCH_GPD11
PCH_GPD12

PCH_GPA23
PCH_GPA22
PCH_GPA21

Bit 6

0

1

Boot BIOS
Destination

SPI (Default)

LPC

SKU ID

PCH_GPD9
PCH_GPD10
PCH_GPD11
PCH_GPD12

PCH_GPA23
PCH_GPA22
PCH_GPA21

2

+3VALW

RH155

RH153

1 2

1060M@

10K_0402_5%

RH159

1 2

1050M@

10K_0402_5%

RH163

NOBL@

1 2

10K_0402_5%

RH195

BL@

1 2

10K_0402_5%

10K_0402_5%

10K_0402_5%

RH152

@

1 2

RH158

RH157

@

1 2

1. Add KB BL GPIO

2. Delete DZ510 / DY512 BOM structure

HLZ SIT 0923

@

1 2

@

1 2

RH774

@

1 2

10K_0402_5%

RH775

@

1 2

10K_0402_5%

RH776

@

1 2

10K_0402_5%

RH777

@

1 2

10K_0402_5%

RH778

@

1 2

10K_0402_5%

RH779

@

1 2

10K_0402_5%

1

10K_0402_5%

10K_0402_5%

PCH_GPD9

DY512

DZ510

PCH_GPD10Function

X

X

NV 1050M

NV 1060M

KB BL

No KB BL

PCIE SSD

B B

Optane memory

X

X

X

X 0

XX X X

PCH_GPD11

X

X

0X

1

X

X

X

RSV

RSV

A A

XX XX

PCH_GPD12

X

X

X

X

0

1

X

PCH_GPD21

X

X

X

X

X

X

XX

X

X

X

X

X

X

1

XXXX

PCH_GPD22

PCH_GPD23

X

X

X

X

X

X

X

X

X

XX

XX

XX

XXX

XX X

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2015/02/26

2015/02/26

2015/02/26

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/02/26

2016/02/26

2016/02/26

Title

PCH (6/9) GPPPABCD, I2C

PCH (6/9) GPPPABCD, I2C

PCH (6/9) GPPPABCD, I2C

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

C

C

C

Friday, November 25, 2016

Friday, November 25, 2016

Friday, November 25, 2016

Date: Sheet of

Date: Sheet of

Date: Sheet of

DY512

DY512

DY512

1

20 75

20 75

20 75

1.0

1.0

1.0

5

4

3

2

1

+1.0VALW +VCCPRIM_1P0

Need short

JUMP_43X79

Need short

JUMP_43X79

+1.0VS_VCCAPLLEBB

+VCCPRIM_1P0

+VCCUSBPLL_1P0

+VCCHDAPLL_1P0

1U_0402_6.3V6K

CH30

75ohm@100Mhz 200mA

+3VALW

1 2

BLM15GA750SN1D_2P

+3VS

1 2

BLM15GA750SN1D_2P

@

JC2

112

@

JC3

112

@

CH25

1 2

1U_0402_6.3V6K

0.08A+0.03A=0.11A

+VCCHDA

+VCCDSW

+VCCPRIM_1P0

LH1

LH3

.1U_0402_10V6-K

2

+1.0VS_VCCMPHY

2

1

@

2

+VCCHDA

CH248

+1.0VALW 4A
+3VALW 0.225A
+3VALW_PCH 1.222A

D D

+1.0VS_VCCMPHY

C C

+1.0VS_VCCMPHYPLL

NEAR PCH PIN

CH257

22U_0603_6.3V6-M

1

1

@

@

2

2

B B

+VCCPRIM_1P0

RH203 0_0805_5%

1 2

LH2

1 2

BLM15GA750SN1D_2P

75ohm@100Mhz 200mA

+1.0VS_VCCMPHY +1.0VS_VCCMPHYPLL

RH199 0_0402_5%

RH200 0_0402_5%

CH256

22U_0603_6.3V6-M

1U_0402_6.3V6K

1

CH255

2

@

+VCCUSBPLL_1P0

+VCCHDAPLL_1P0

1U_0402_6.3V6K

1

CH259

2

+VCCPRIM_1P0

+VCCPRIM_1P0

+VCCPRIM_1P0

1 2

1 2

+1.0VS_VCCMPHY

CH29

22U_0603_6.3V6-M

1

1

2

2

1U_0402_6.3V6K

1

CH258

2

Change CH248 from @ to stuff due to power noise test fail
HLZ SIV 0811

Total 2.899A

DCPDSW_1P0

0.242A

700mA

0.075A

Total 2.899A

0.012A

0.033A

0.06A

Total 0.195A

CH254

22U_0603_6.3V6-M

2

1

4A

0.885A

0.078A

0.082A

0.229A

0.114A

0.065A

0.35mA

0.007A

+VCCPFUSE_3P3

+VCCPGPPD

+VCCPGPPA

+VCCPGPPBCH

+VCCPGPPEF

+VCCPGPPG

+VCCPRIM_3P3

+VCCPRTCPRIM

1

2

+V3.3A_VCCATS

.1U_0402_10V6-K

CH262

1

2

1U_0402_6.3V6K

+VCCPGPPD+VCCPFUSE_3P3

1 2

RH220 0_0402_5%

1 2

RH221 0_0402_5%

1 2

RH222 0_0402_5%

1 2

RH223 0_0402_5%

1 2

RH224 0_0402_5%

1 2

RH225 0_0402_5%

1 2

RH226 0_0402_5%

1 2

RH746 0_0402_5%

CH23

1 2

1 2

+VCCPRIM_3P3

.1U_0402_10V6-K

CH20

1

2

1

2

UH1H

AA23

VCCPRIM_1P0_1

AA26

VCCPRIM_1P0_2

AA28

VCCPRIM_1P0_3

AC23

VCCPRIM_1P0_4

AC26

VCCPRIM_1P0_5

AC28

VCCPRIM_1P0_6

AE23

VCCPRIM_1P0_7

AE26

VCCPRIM_1P0_8

Y23

VCCPRIM_1P0_9

Y25

VCCPRIM_1P0_10

BA29

DCPDSW_1P0

N17

VCCCLK1_1

R19

VCCCLK3_2

U20

VCCCLK4_3

V17

VCCCLK2_4

R17

VCCCLK2_5

K2

VCCCLK5_6

K3

VCCCLK5_7

U21

VCCMPHY_1P0_1

U23

VCCMPHY_1P0_2

U25

VCCMPHY_1P0_3

U26

VCCMPHY_1P0_4

V26

VCCMPHY_1P0_5

A43

VCCMPHYPLL_1P0_1

B43

VCCMPHYPLL_1P0_2

C44

VCCPCIE3PLL_1P0_1

C45

VCCPCIE3PLL_1P0_2

V28

VCCAPLLEBB_1P0

AC17

VCCPRIM_1P0_16

AJ5

VCCUSB2PLL_1P0_1

AL5

VCCUSB2PLL_1P0_2

AN19

VCCHDAPLL_1P0

BA15

VCCHDA

W15

VCCDSW_3P3_1

SKYLAKE-H-PCH_FCBGA837

@

NEAR
K2

1U_0402_6.3V6K

CH253

22U_0603_6.3V6-M

1

1

CH22

@

2

2

@

+3VALW_PCH

+3VALW

1 2

RH206 0_0402_5%@

1 2

RH205 0_0402_5%

SPT-H_PCH

CORE

MPHY

USB

+VCCDSW

8 OF 12

VCCGPIO

2

CH80
1U_0402_6.3V6K

1

@

AL22

VCCPRIM_1P0_17

VCCDSW_3P3_2

VCCPGPPA

VCCPGPPBCH_1
VCCPGPPBCH_2

VCCPGPPEF_1
VCCPGPPEF_2

VCCPGPPG

VCCPRIM_3P3

VCCPRIM_1P0_15

VCCATS

VCCRTCPRIM_3P3

VCCRTC
DCPRTC

VCCPRIM_1P0_11
VCCPRIM_1P0_12
VCCPRIM_1P0_13
VCCPRIM_1P0_14

VCCSPI_1
VCCSPI_2

VCCSPI_3
VCCPGPPD_1
VCCPGPPD_2
VCCPGPPD_3
VCCPGPPD_4

VCCPRIM_3P3_1
VCCPRIM_3P3_2
VCCPRIM_3P3_3

Total 2.899A

BA24

Total 0.195A

BA31
BC42

BD40
AJ41
AL41
AD41
AN5

Total 0.117A

AD15

Total 2.899A

AD13

0.007A

BA20

0.35mA

BA22

0.35mA

BA26

DCPRTC

AJ20
AJ21
AJ23
AJ25

BE41
BE43
BE42
BC44
BA45
BC45
BB45

BD3
BE3
BE4

VCCRTC +VCCRTC_3P3

1 2

RH216 0_0402_5%

0.082A

0.229A

0.114A

0.065A

Total 2.899A

0.029A

0.078A

Total 0.117A

+VCCDSW
+VCCPGPPA

+VCCPGPPBCH
+VCCPGPPEF
+VCCPGPPG

+VCCPRIM_3P3

+V3.3A_VCCATS
+VCCPRTCPRIM
+VCCRTC_3P3

+3V_SPI

+VCCPGPPD

+VCCPFUSE_3P3

+VCCPRIM_1P0

+VCCPRIM_1P0

1U_0402_6.3V6K

1

CH244

2

+VCCPRIM_1P0

+VCCPGPPA

NEAR
BA31

.1U_0402_10V6-K

CH245

1

2

2

CH26

1

.1U_0402_10V6-K

.1U_0402_10V6-K

CH260

1

@

2

Total 0.117A

Total 0.117A

.1U_0402_10V6-K

CH261

1

@

NEAR

2

BA31

Total 0.685A

+3VS

12

RH759
0_0805_5%

@

RH2190_0402_5%

RH110_0402_5% @

+VCCPGPPG +VCCPGPPEF

.1U_0402_10V6-K

CH243

.1U_0402_10V6-K

CH82

1

@

@

2

+3VALW_PCH

RH760
0_0805_5%

1 2

layout requirement RH760 do not change to R short

+3VALW_PCH+3VS

1

2

.1U_0402_10V6-K

CH81

@

+VCCPGPPBCH

1

2

.1U_0402_10V6-K

CH28

+V3.3A_VCCATS

@

1U_0402_6.3V6K

1

CH36

2

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2015/02/26

2015/02/26

2015/02/26

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/02/26

2016/02/26

2016/02/26

Title

PCH (7/9) PWR

PCH (7/9) PWR

PCH (7/9) PWR

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

C

C

C

Friday, November 25, 2016

Friday, November 25, 2016

Friday, November 25, 2016

Date: Sheet of

Date: Sheet of

Date: Sheet of

DY512

DY512

DY512

1

21 75

21 75

21 75

1.0

1.0

1.0

5

SPT-H_PCH

UH1L

C42

VSS_149

D10

VSS_150

D12

VSS_151

D15

VSS_152

D16

VSS_153

D17

VSS_154

D19

D D

C C

B B

A A

VSS_155

D21

VSS_156

D24

VSS_157

D25

VSS_158

D27

VSS_159

D29

VSS_160

D30

VSS_161

D31

VSS_162

D33

VSS_163

D35

VSS_164

D36

VSS_165

E13

VSS_166

E15

VSS_167

E31

VSS_168

E33

VSS_169

F44

VSS_170

F8

VSS_171

G42

VSS_172

G9

VSS_173

H17

VSS_174

H19

VSS_175

H22

VSS_176

H24

VSS_177

H27

VSS_178

H29

VSS_179

H3

VSS_180

H35

VSS_181

J10

VSS_182

J11

VSS_183

J3

VSS_184

J39

VSS_185

J5

VSS_186

T42

VSS_187

U10

VSS_188

U11

VSS_189

U14

VSS_190

U17

VSS_191

U18

VSS_192

U28

VSS_193

U29

VSS_194

U31

VSS_195

U32

VSS_196

U33

VSS_197

U38

VSS_198

U4

VSS_199

U8

VSS_200

V18

VSS_201

V20

VSS_202

V21

VSS_203

V23

VSS_204

V25

VSS_205

V29

VSS_206

V3

VSS_207

V45

VSS_208

W14

VSS_209

W31

VSS_210

W32

VSS_211

W33

VSS_212

W38

VSS_213

W4

VSS_214

W8

VSS_215

Y17

VSS_216

12 OF 12

SKYLAKE-H-PCH_FCBGA837

@

VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285

AB11
AB7
AB14
AB31
AB32
AB38
AB4
AB5
AC1
AC20
AC21
AC25
AC29
AC45
AB8
AD11
AD14
AB15
AD32
AD33
AD36
AD4
AD8
AE18
AE20
AE21
AE25
AE28
AL10
AL11
AL13
AL17
AL19
AL24
AL29
AL32
AL33
AL38
AM15
AM17
AM19
AM22
AM24
AM27
AM29
AM45
AN11
AN22
AN27
AN31
AN39
AN7
AN8
AP11
AP4
AR33
AR34
AR42
AR9
AT10
AT15
AT36
AT9
AU1
AU35
AU36
AU39
AU45
C4

4

SPT-H_PCH

UH1I

AC18

VSS_1

AN4

VSS_2

AN10

VSS_3

BE14

VSS_4

BE18

VSS_5

BE23

VSS_6

BE28

VSS_7

BE32

VSS_8

BE37

VSS_9

BE40

VSS_10

BE9

VSS_11

C10

VSS_12

C2

VSS_13

C28

VSS_14

C37

VSS_15

J7

VSS_16

K10

VSS_17

K27

VSS_18

K33

VSS_19

K36

VSS_20

K4

VSS_21

K42

VSS_22

K43

VSS_23

L12

VSS_24

L13

VSS_25

L15

VSS_26

L4

VSS_27

L41

VSS_28

L8

VSS_29

M35

VSS_30

M42

VSS_31

N10

VSS_32

N15

VSS_33

N19

VSS_34

N22

VSS_35

N24

VSS_36

N35

VSS_37

N36

VSS_38

N4

VSS_39

N41

VSS_40

N5

VSS_41

P17

VSS_42

P19

VSS_43

P22

VSS_44

P45

VSS_45

R10

VSS_46

R14

VSS_47

R22

VSS_48

R29

VSS_49

R33

VSS_50

R38

VSS_51

R5

VSS_52

T1

VSS_53

T2

VSS_54

T4

VSS_55

Y18

VSS_56

Y20

VSS_57

Y21

VSS_58

Y26

VSS_59

Y28

VSS_60

Y29

VSS_61

A18

VSS_62

A25

VSS_63

A32

VSS_64

A37

VSS_65

AA17

VSS_66

AA18

VSS_67

AA20

VSS_68

AA21

VSS_69

AA25

VSS_70

AA29

VSS_71

AA4

VSS_72

AA42

VSS_73

AB10

VSS_74

9 OF 12

SKYLAKE-H-PCH_FCBGA837

@

VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98

VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148

AR5
AR7
U15
AL4
AE29
AE4
AE42
AF18
AF20
AF21
AF23
AF25
AF26
AF28
AF29
AG11
AG13
AG31
AG32
AG33
AG38
AG4
AH1
AH17
AH18
AH20
AH21
AH23
AH25
AH26
AH28
AH29
AH45
AJ10
AJ14
AJ15
AJ17
AJ18
AJ26
AJ28
AJ29
AJ31
AJ32
AJ36
AK4
AK42
AU7
AV17
AV24
AV27
AV31
AV33
AV6
AW13
AW19
AW29
AW37
AW9
AY38
AY45
B25
B3
B37
B40
B6
BA1
BB11
BB16
BB21
BB25
BB30
BB34
BC2
BD43

3

UH1J

BD2

VSS_286

BD45

VSS_287

BD44

VSS_288

BE44

VSS_289

D45

VSS_290

A42

VSS_291

B45

VSS_292

B44

VSS_293

A4

VSS_294

A3

VSS_295

B2

VSS_296

A2

VSS_297

B1

VSS_298

BB1

VSS_299

BC1

VSS_300

A44

VSS_301

C1

RSVD_5

D1

RSVD_6

SKYLAKE-H-PCH_FCBGA837

@

SPT-H_PCH

10 OF 12

2

RSVD_7
RSVD_8

RSVD_9
RSVD_10
RSVD_11

RSVD_12
RSVD_13
RSVD_14
RSVD_15
RSVD_16
RSVD_17
RSVD_18

PREQ#
PRDY#

CPU_TRST#

PCH_TRIGOUT

PCH_TRIGIN

PCH_TRIGIN

AR22
W13
U13
P31
N31

P27
R27
N29
P29
AN29
R24
P24

AT3
AT4
AY5

PCH_TRIGOUT

AL2
AK1

RH758 30_0402_1%1 2

CH8.1U_0402_10V6-K @

1 2

1

PCH_PREQ# 42
PCH_PRDY# 42
CPU_TRST# 42

CPU_TRIGIN 6
PCH_TRIGIN 6

Reserved Cap HLZ SDV 0616

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

2015/02/26

2015/02/26

2015/02/26

3

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2016/02/26

2016/02/26

2016/02/26

2

Title

PCH (9/9) VSS

PCH (9/9) VSS

PCH (9/9) VSS

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

B

B

B

Friday, November 25, 2016

Friday, November 25, 2016

Date: Sheet of

Date: Sheet of

Date: Sheet of

Friday, November 25, 2016

DY512

DY512

DY512

1

22 75

22 75

22 75

1.0

1.0

1.0

5

N17P-G1 GPIO

GPIO I/O
GPIO0
GPIO1

D D

GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14

C C

GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24
GPIO25
GPIO26

B B

GPIO27ININ

ACTIVE

-

OUT

-

OUT

-

IN

-

OUT

-

OUT

N/A

IN Active low Frame Lock

-

OUT

OUT

N/A

-

OUT

-

I/O

-

OUT

-

OUT

-

IN

OUT

N/A
N/A

IN

N/A

IN

-

OUT

N/A

IN

N/A

IN

OUT

N/A

N/A
N/A

I/O

N/A

I/O

-

OUT

N/A

N/A
N/A

N/A

Function Description
PWM Output to control NVVDD
FB Enable for GC6 2.1
GPU wake signal for GC6 2.1
PWM Output to control the SRAM power supply
GPU power sequencing for GC6 2.1 --- 1V8_MAIN_EN

Phase Shedding, NVVDD_PSI
Panel Backlight enable
Memory voltage Control
Active Low Therm al Alert
Memory VREF Control
Panel Power enable
AC power detect or power supply overdraw input
LCD Panel Backlight Enable
Hot Plug Detect for IFPA
Hot Plug Detect for IFPB
System side PCIe reset monitor
Hot Plug Detect for IFPD
Hot Plug Detect for IFPE
3D Vision L/R Signal

GC5_MODE

UNUSED

UNUSED

GPU PCIe self-reset control
Hot Plug Detect for IFPF

UNUSED

UNUSED

Hot Plug Detect for IFPC

N17P-G1 Power Sequence

+1.8VS_AON

+1.8VGS

NVVDD

NVVDDS/+1.0VGS

NVVDDS/+1.0VGS

4

(100K pull Down)

NVVDD

I/O Termination

(10K pull High)

3

STRAP2

L

L

L

H

H

ROM_SO

L

L

L

H

H

H

H

L

L

L

L

H

H

H

H

STRAP5

M

M

M

M

L

L

L

L

H

H

H

L

L

L

L

STRAP1

L

H

H

H

H

ROM_SI

LL

L

H

H

L

L

H

H

L

M

M

H

L

M

M

H

STRAP4

H

H

L

L

H

M

M

L

H

H

L

LH

H

H

L

L

STRAP0

L

L 00010

H

L

H

ROM_SCLK

L

H

L

H

L

H

L

H

M

L

H

M

M

L

H

M

STRAP3

H

L

H

L

M

H

L

M

H

L

H

L

H

L

H

L

RAMCFG[4:0]

00000

00011

00110

00111

SOR_EXPOSED[3:0]

1111 DEFAULT

SMB_ALT_ADDR

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

1110

1101

1100

1011

1010

1001

1000

0111

0110

0101

0100

0011

0010

0001

0000

DEVID_SEL

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

2

H=High: Tied to 1.8V
M=Middle: Tied to 0.9V
L=Low: Tied to 0V

1:ENABLE 0:DISABLE

SOR0/1/2/3 ENABLE

PCIE_CFG

1

1

0

0

1

1

0

0

1

1

0

0

10

1

0

0

VGA_DEVICE

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1 DEFAULT

0

1

1:SMB_ALT_ADDR ENABLE
0:SMB_ALT_ADDR DISABLE

1:DEVID_SEL REBRAND
0:DEVID_SEL ORIGNAL

1:PCIE_CFG LOW POWER
0:PCIE_CFG HIGH POWER

1:VGA_DEVICE ENABLE
0:VGA_DEVICE DISABLE

FBVDDQ

A A

1. All power rail ramp up time should be larger than 40us
and is recommended to be less than 2ms.

2. T (from 1V8_MAIN_EN to PEX_DVDD/NVVDD_Pgood)
must NOT exceed 4ms.

3. All 3.3V devices that connect to the GPU must be
powered after 1V8_AON; GPU can NOT have any 3.3V
leakage path before 1V8_AON present.

4. The previous power rail must ramp up to 90% before
the next power rail can start ramping up.

5

1. NVVDDS/PEX_DVDD must ramp down before NVVDD, all
other power rails can ramp down together with NVVDD.

2. All 3.3V devices that connect to the GPU must be
ramp down before 1V8_AON; GPU can NOT have any 3.3V
leakage path after 1V8_AON and 1.8V_MAIN power down.

3. The previous power rail must ramp down to 10% before
the next power rail can start ramping down.

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2015/02/26

2015/02/26

2015/02/26

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/02/26

2016/02/26

2016/02/26

Title

Title

Title

VGA Notes List

VGA Notes List

VGA Notes List

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

C

C

C

Friday, November 25, 2016

Friday, November 25, 2016

Friday, November 25, 2016

Date: Sheet of

Date: Sheet of

Date: Sheet of

DY512

DY512

DY512

1

23 75

23 75

23 75

1.0

1.0

1.0