LCFC DIS M schematics

A

1 1

B

C

D

E

Compal C

2 2

DIS M

/B Schematics Document

AMD S

toney Ridge FT4

onfidential

LA-G241P

3 3

2018

R E V

-03-12

：

：

1 . 0

：：

4 4

Secu

Secu

Secu

rity Classification

rity Classification

rity Classification

Issued Date

Issued Date

Issued Date

THIS

THIS

THIS

SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2018

2018

2018

/03/12 2019/03/ 12

/03/12 2019/03/ 12

/03/12 2019/03/ 12

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Comp

Comp

Comp

al Electronics, Inc.

al Electronics, Inc.

Titl

Titl

Titl

e

e

e

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Cust

Cust

Cust

om

om

om

Date : Sheet

Date : Sheet

D

Date : Sheet

al Electronics, Inc.

Cove

Cove

Cove

r Page

r Page

r Page

LA-G

LA-G

LA-G

241P

241P

241P

1 43Monday, March 12 , 2018

1 43Monday, March 12 , 2018

1 43Monday, March 12 , 2018

E

1.0

1.0

1.0

o f

o f

o f

A

www.schematic-x.blogspot.com

B

C

D

E

1 1

AMD R17M-M1-70

A

PCIe x4

D Stoney Ridge FT4

M

2133 MHz 1.2V

DDR4 SO-DIMM X1

VRAM(GDDR5)*2 2GB

eDP Conn.

HDMI Conn.

2 2

RJ45 Conn.

LAN

Realtek
RTL8106E-CG
10/100

eDP X1 (2 Lanes)

DP X1 (4 Lanes)

PCIe x1

AMD
Stoney Ridge FT4

Processor
BGA 769

USB3.0 x2
USB2.0 x2

USB2.0 x1

SATA X1

SATA X1

Left USB3.0 x2

Int. Camera

HDD Conn.

ODD Conn.

PCIe X1 for WLAN

WLAN / BT

(1 Lanes)

USB2.0 x1 for BT

HDA

Audio Codec

Realtek
ALC3240-VA3-CG

Int. Speaker

Stereo / Mono

Combo Jack

SD Conn.

3 3

Realtek
RTS5146-GR

Card Reader

USB2.0 x1

I2C

Touch Pad

Headphone / MIC

SPILPC

EC

ENE
KB9022QD

Th

LED

4 4

A

B

ermal Diode

Int. KBD

SPI ROM

8MB
XMC
XM25QU64ARIG

Se

Se

Se

curity Classification

curity Classification

curity Classification

Issued Date

Issued Date

Issued Date

TH

TH

TH

IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

20

20

20

18/03/12 2019/03/12

18/03/12 2019/03/12

18/03/12 2019/03/12

Compal Secret Data

Compal Secret Data

Compal Secret Data

De

De

De

ciphered Date

ciphered Date

ciphered Date

D

Com

Com

Com

pal Electronics, Inc.

pal Electronics, Inc.

Ti

Ti

Title

tle

tle

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Cu

Cu

Cu

stom

stom

stom

Date : Sheet

Date : Sheet

Date : Sheet

pal Electronics, Inc.

Bl

Bl

Bl

ock Diagram

ock Diagram

ock Diagram

LA

LA

LA

-G241P

-G241P

-G241P

E

2 43Monday, March 12, 2018

2 43Monday, March 12, 2018

2 43Monday, March 12, 2018

of

of

of

1.

1.

1.

0

0

0

A

B

C

D

E

V

oltage Rails

D

P

ower Plane

V

IN

B

+

+

APU_CORE

+

AP

1 1

2 2

U_CORE_NB ON

+3VALW

+3VS

+1.8VALW

+1.8VS

+0.95VALW

+0.9

5VS

+1.2V

+2.5

V

+0.6V

+5VALW

+5VS

+RTCVBATT

+0.775 VALW

SMBUS Control Table

EC_SMB_CK1
EC_SMB_DA1

APU_SCLK0
APU_SDATA0

EC_SMB_CK2
EC_SMB_DA2

escription

Ada

ter power supply (19V)

p

AC or battery power rail for power circuit.

Core voltage for APU

Vol

age for On-die VGA of APU

t

3.3V always on power rail

.3V switched power rail

3

1.

8V always on power rail

1.8V switched power rail

0.95V always on power rail

0.95V switched power rail

1.2V power rail for APU and DDR

2.5V switched power rail for DDR

0.6V switched power r ail for DDR terminator

5V always on power r ail

5V switched power rail

RTC power

0.775V always on power rail

APU

SOURCE

ENE9022

+3VL

APU

+3VS

ENE9022

+3VS

BATT NPCE388N

X X

V

+3

VALW

X

X

X

V

+1.8VS

S

0 S3 S5

ONO

O

N

O

N

ON ON

ON

ON

ON

ON

ON

ON

ON

ON ONON

IMM

WLAN

SO-D

X

X

V

+3VS

X X

X

ON

N

ONONON

OFF

OFF

OFF

O

O

O

NON

O

OFF

ON

OFF OFF

ON ON

OFF O

OFF

ON

OFF

ONON

OFFOF

F

ON O

OFF O

ONONON

Thermal
Sensor

X

X

FF

N

FF

FF

N

FF

X

X

V

+3VS

A

PU PCIE PORT LIST

DevicePor t

0

L

AN

1
2

LAN

W

3

USB Port Table

USB 2.0USB 3.0

0
1
2
3

USB2 port5

425@

4
5
6
7

USB

X4E

ZZZ

1
2

USB

OC MAPPING

0
1
2
3

APU part

UC1

A9_9

3 External
USB Port

WLAN/BT Combo
Camera
Card Reader

Left US
Left USB3.0 port 2

PortOC#

USB3 port1

level BOM

X4E_15@

B3.0 port 1

HDMI

ZZZ

logo

45@

STA

E

T

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF) LOW

SIGNA L

SLP_S3 # S LP_S5# +VALW +V +VS Clock

HIGH HIGH

HIGHHIGH

HIGH

HIGH

LOW

HIGH

LOW

BOM Structure Table

BOM Structure I tem

45@
UMA @
DIS @
HDT @
X4E_ 15@
X76 @
EMI @
@EM I@
ESD @
@ES D@
RF@
@RF @
CON N@
2HD D@
8111 GLDO @
@
S2G @
H2G @
M2G @

For HDMI Logo

For UMA SKU

For DIS SKU

AMD Dubeg Header

X4E level BOM For 15"

X76 level BOM

EMI pop component

EMI Un pop component

ESD pop component

ESD Un pop component

RF pop component

RF Un pop component

ME part

2nd HDD component

LAN chip 8111LDO pop component

Unpop

Samsung VRAM SKU

Hynix VRAM SKU

Micron VRAM SKU

ON

ON

ON

ON

ON

ONONON ON

ON

ON

OFF

OFF

OFF

OFF

OFF

LOW

OFF

OFF

OFF

EC SM Bus1 address EC SM Bus2 address

X4EA

A9_9

Devi

ce

Smart Battery

Char

3 3

ger

Address

0001

011x b

0001

0010 b

DDR SM Bus address

Device

DDR

DIMM1

Address

1010

000X b

HEX

Device

APU

16H

12H

GPU SM Bus address

HEX

Device

GPU

A0H

Address

100

1 100X b

Address

0100

0001 b

HEX

98H

HEX

0

X41H

425_R3

SA0000BGS20

UC1

A6_9

A6-9

225_R3

SA0000BGT20

UC1

A4_9

225@

125@

BS38L51

HDMI

Logo

RO00

00003HM

PCB part

ZZZ

ODD@

PCB

DLADE LA-G241P LS-G201P/G202P 02

D

AZ29700101

ZZZ

DmyO

DD@

A4_9

125_R3

SA0000BM510

UC1

E2_9

000@

E2_9

000_R3

SA00009W8 10

4 4

A

B

PCB

DLADE LA-G241P LS-G201P 02

DAZ29700201

Secu

Secu

Secu

rity Classification

rity Classification

rity Classification

Issued Date

Issued Date

Issued Date

THIS

THIS

THIS

SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2018

2018

2018

/03/12 2019/03/12

/03/12 2019/03/12

/03/12 2019/03/12

Compal Secret Data

Compal Secret Data

Compal Secret Data

Decip

Decip

Decip

hered Date

hered Date

hered Date

D

Compal E

Compal E

Titl

Titl

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Cust

Cust

Cust

Date : Sheet

Date : Sheet

Date : Sheet

Compal E

e

e

om

om

om

lectronics, Inc.

lectronics, Inc.

lectronics, Inc.

NOTE

NOTE

NOTE

S LIST

S LIST

S LIST

LA-G

LA-G

LA-G

241P

241P

241P

E

of

of

of

3 43Monday, March 12, 2018

3 43Monday, March 12, 2018

3 43Monday, March 12, 2018

1.0

1.0

1.0

5

D D

4

3

2

1

UC1B

PCIE_

LAN

WLA

N WLAN

C C

GPU GPU

+0.95

VS

B B

ARX_DTX _P0<20>

PCIE_

ARX_DTX _N0<20>

PCIE_

ARX_DTX _P2<22>

PCIE_

ARX_DTX _N2<22>

PCIE_

ARX_GTX _P0<11>

PCIE_

ARX_GTX _N0<11>

PCIE_

ARX_GTX _P1<11>

PCIE_

ARX_GTX _N1<11>

PCIE_

ARX_GTX _P2<11>

PCIE_

ARX_GTX _N2<11>

PCIE_

ARX_GTX _P3<11>

PCIE_

ARX_GTX _N3<11>

1 2

RC1 196

_0402_1 %

P_ZVD

U4

P_GPP

U5

P_GPP

R8

P_GPP

R10

P_GPP

R5

P_GPP

R4

P_GPP

N4

P_GPP

N5

P_GPP

L5

P_GFX

L4

P_GFX

J5

P_GFX

J4

P_GFX

G5

P_GFX

G4

P_GFX

D7

P_GFX

E7

P_GFX

DP

U8

P_ZVD

DP

A6-92

00E_BGA 769

@

_RXP0
_RXN0

_RXP1
_RXN1

_RXP2
_RXN2

_RXP3
_RXN3

_RXP0
_RXN0

_RXP1
_RXN1

_RXP2
_RXN2

_RXP3
_RXN3

PCIE

PCIE_

P_GPP
P_GPP

P_GPP
P_GPP

P_GPP
P_GPP

P_GPP
P_GPP

P_GFX
P_GFX

P_GFX
P_GFX

P_GFX
P_GFX

P_GFX
P_GFX

_TXP0

_TXN0

_TXP1

_TXN1

_TXP2

_TXN2

_TXP3

_TXN3

_TXP0

_TXN0

_TXP1

_TXN1

_TXP2

_TXN2

_TXP3

_TXN3

P_ZVS

PCIE_

PCIE_
PCIE_

PCIE_
PCIE_

PCIE_
PCIE_

PCIE_
PCIE_

PCIE_
PCIE_

P_ZVS

S

ATX_DRX _P0
ATX_DRX _N0

ATX_DRX _P2
ATX_DRX _N2

ATX_GRX _P0
ATX_GRX _N0

ATX_GRX _P1
ATX_GRX _N1

ATX_GRX _P2
ATX_GRX _N2

ATX_GRX _P3
ATX_GRX _N3

1 2

RC2 196

D2
D1

C2
C1

B2
B1

A3
B3

A4
B4

A5
B5

A6
B6

A7
B7

W8

S

1 2

CC1 0.1
CC2 0.1

CC3 0.1
CC4 0.1

CC104 0
CC105 0

CC106 0
CC107 0

CC108 0
CC109 0

CC110 0
CC111 0

1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

_0402_1 %

U_0201_ 10V6K
U_0201_ 10V6K

U_0201_ 10V6K
U_0201_ 10V6K

PCIE_

ATX_C_D RX_P0 <20>

PCIE_

ATX_C_D RX_N0 <20>

PCIE_

ATX_C_D RX_P2 <22>

PCIE_

ATX_C_D RX_N2 < 22>

.22U_040 2_6.3V6KDIS@
.22U_040 2_6.3V6KDIS@

.22U_040 2_6.3V6KDIS@
.22U_040 2_6.3V6KDIS@

.22U_040 2_6.3V6KDIS@
.22U_040 2_6.3V6KDIS@

.22U_040 2_6.3V6KDIS@
.22U_040 2_6.3V6KDIS@

PCIE_
PCIE_

PCIE_
PCIE_

PCIE_
PCIE_

PCIE_
PCIE_

LAN

ATX_C_G RX_P0 <11 >
ATX_C_G RX_N0 <11>

ATX_C_G RX_P1 <11 >
ATX_C_G RX_N1 <11>

ATX_C_G RX_P2 <11 >
ATX_C_G RX_N2 <11>

ATX_C_G RX_P3 <11 >
ATX_C_G RX_N3 <11>

A A

Securit

Securit

Securit

y Classification

y Classification

y Classification

2018/

2018/

2018/

03/12 2019/03/1 2

03/12 2019/03/1 2

Issued Date

Issued Date

Issued Date

THIS

THIS

THIS

SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

03/12 2019/03/1 2

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compa

Compa

Compa

l Electronics, Inc.

l Electronics, Inc.

Title

Title

Title

S

S

S

ize Document Number Re v

ize Document Number Re v

ize Document Number Re v
Custo

Custo

Custo

m

m

m

Date : Sheet

Date : Sheet

2

Date : Sheet

l Electronics, Inc.

GPP &

GPP &

GPP &

PCIE

PCIE

PCIE

LA-G2

LA-G2

LA-G2

41P

41P

41P

4 43Monday, March 12 , 2018

4 43Monday, March 12 , 2018

4 43Monday, March 12 , 2018

1

1.0

1.0

1.0

o f

o f

o f

5

4

3

2

1

DDR

A_SMA[13 ..0]<10>

_

D D

DDR_

A_SBG1<10>

DDR_

A_SACT#<10>

DDR_

A_SBS0#<10>

DDR_

A_SBS1#<10>

DDR_

A_SBG0<10>

DDR_

DDR_
DDR_

DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_

DDR_
DDR_
DDR_
DDR_

A_RST#<10>
A_EVENT #<10>

DDR_
DDR_

DDR_
DDR_

DDR_
DDR_

DDR_
DDR_
DDR_

A_SDM[7..0 ]<10>

A_SDQS0<10>
A_SDQS0 #<10>
A_SDQS1<10>
A_SDQS1 #<10>
A_SDQS2<10>
A_SDQS2 #<10>
A_SDQS3<10>
A_SDQS3 #<10>
A_SDQS4<10>
A_SDQS4 #<10>
A_SDQS5<10>
A_SDQS5 #<10>
A_SDQS6<10>
A_SDQS6 #<10>
A_SDQS7<10>
A_SDQS7 #<10>

A_CLK0<10>
A_CLK0#<10>
A_CLK1<10>
A_CLK1#<10>

A_CKE0<10>
A_CKE1<10>

A_ODT0<10>
A_ODT1<10>

A_SCS0#<10>
A_SCS1#<10>

A_SRAS#<1 0>
A_SCAS#<1 0>
A_SW E#<10>

APU_

T1

+1.2

C C

B B

EVENT# pull high

V

1 2

RC4 1K

_0402_5 %

DDR_

A_EVENT #

ESD

ESD@

1 2

CC11

2 100P_0402 _50V8J

DDR_

A_RST#

DDR_
DDR_

MA_VREF DQ

DDR

A_SMA0

_

DDR

A_SMA1

_
_

A_SMA2

DDR
DDR

A_SMA3

_
_

A_SMA4

DDR
DDR

A_SMA5

_
_

A_SMA6

DDR
DDR

A_SMA7

_

DDR

A_SMA8

_

DDR

A_SMA9

_
DDR_A_S MA10
DDR_A_S MA11
DDR_A_S MA12
DDR_A_S MA13

DDR_

A_SDM0

DDR_

A_SDM1

DDR_

A_SDM2

DDR_

A_SDM3

DDR_

A_SDM4

DDR_

A_SDM5

DDR_

A_SDM6

DDR_

A_SDM7

A_RST#
A_EVENT #

AG3

W35
W38
W34

U38
U37
U34
R35
R38
N38

AG34

R34
N37

AN35

AJ38

AG35

N34

B35
D40
K40

AE41
AL40

AU40

BA37

B36
A36
E40
D41

K41
U41

U40
AF41
AE40

AM40
AM41

AV40
AV41
BA36
AY36

AC35
AC34
AA34
AA32
AE38
AE37
AA37
AA38

G38
AA41

AN37
AU38
AL34
AN34

AL35
AR37

AJ34

AR38

AJ37
AN38
AL38

AA40

L38
L35

T41

L40

J38
J34
L34
J37

Y41

UC1A

8

A6-9

@

M_A

D0

D

M_A

D1

D

M_A

D2

D

M_A

D3

D

M_A

D4

D

M_A

D5

D
D

D6

M_A
M_A

D7

D
D

D8

M_A
M_ADD9
M_ADD10
M_ADD11
M_ADD12
M_ADD13
M_AD

D14/M_BG1

M_AD

D15/M_ACT_L

M_BA

NK0

M_BA

NK1

M_BA

NK2/M_BG0

M_DM

0

M_DM

1

M_DM

2

M_DM

3

M_DM

4

M_DM

5

M_DM

6

M_DM

7

M_DQ

S_H0

M_DQ

S_L0

M_DQ

S_H1

M_DQ

S_L1

M_DQ

S_H2

M_DQ

S_L2

M_DQ

S_H3

M_DQ

S_L3

M_DQ

S_H4

M_DQ

S_L4

M_DQ

S_H5

M_DQ

S_L5

M_DQ

S_H6

M_DQ

S_L6

M_DQ

S_H7

M_DQ

S_L7

M_CL

K_H0

M_CL

K_L0

M_CL

K_H1

M_CL

K_L1

M_CL

K_H2

M_CL

K_L2

M_CL

K_H3

M_CL

K_L3

M_RE

SET_L

M_EV

ENT_L

M0_C

KE0

M0_C

KE1

M1_C

KE0

M1_C

KE1

M0_O

DT0

M0_O

DT1

M1_O

DT0

M1_O

DT1

M0_C

S_L0

M0_C

S_L1

M1_C

S_L0

M1_C

S_L1

M_RA

S_L/M_RAS_L_ADD16

M_CA

S_L/M_CAS_L_ADD15

M_WE

_L/M_WE_L_ADD14

M_VR

EF

M_VR

EFDQ

200E_BG A769

MEM

O

RY

M_ZV

M_D

A

M_D

A

M_D

A

M_D

A

M_D

A

M_D

A
A

M_D
M_D

A

M_DATA8

M_DATA9
M_DATA10
M_DATA11
M_DATA12
M_DA

TA13

M_DA

TA14

M_DA

TA15

M_DA

TA16

M_DA

TA17

M_DA

TA18

M_DA

TA19

M_DA

TA20

M_DA

TA21

M_DA

TA22

M_DA

TA23

M_DA

TA24

M_DA

TA25

M_DA

TA26

M_DA

TA27

M_DA

TA28

M_DA

TA29

M_DA

TA30

M_DA

TA31

M_DA

TA32

M_DA

TA33

M_DA

TA34

M_DA

TA35

M_DA

TA36

M_DA

TA37

M_DA

TA38

M_DA

TA39

M_DA

TA40

M_DA

TA41

M_DA

TA42

M_DA

TA43

M_DA

TA44

M_DA

TA45

M_DA

TA46

M_DA

TA47

M_DA

TA48

M_DA

TA49

M_DA

TA50

M_DA

TA51

M_DA

TA52

M_DA

TA53

M_DA

TA54

M_DA

TA55

M_DA

TA56

M_DA

TA57

M_DA

TA58

M_DA

TA59

M_DA

TA60

M_DA

TA61

M_DA

TA62

M_DA

TA63

DDIO_MEM_S3

TA0
TA1
TA2
TA3
TA4
TA5
TA6
TA7

A34
B34
A38
B38
A33
B33
A37
B37

B41
C40
F41
G40
A40
B40
E41
F40

J40
J41
N40
N41
H40
H41
M40

M41

R40
T40
W40
Y40
P40
P41
V40
V41

AD41
AD40
AH41
AH40
AB40
AC40
AF40
AG40

AK41
AK40
AP41
AP40
AJ41
AJ40
AN41
AN40

AT40
AU41
AY40
BA40
AR40
AT41
AW40
AY41

BA38
AY37
BA34
BA33
AY39
AY38
AY35
AY34

AB41

DDR

A_SDQ0

_

DDR

A_SDQ1

_
_

A_SDQ2

DDR
DDR

A_SDQ3

_
_

A_SDQ4

DDR
DDR

A_SDQ5

_
_

A_SDQ6

DDR
DDR

A_SDQ7

_

DDR

A_SDQ8

_
DDR_A_S DQ9
DDR_A_S DQ10
DDR_A_S DQ11
DDR_A_S DQ12
DDR_A_S DQ13
DDR_

A_SDQ14

DDR_

A_SDQ15

DDR_

A_SDQ16

DDR_

A_SDQ17

DDR_

A_SDQ18

DDR_

A_SDQ19

DDR_

A_SDQ20

DDR_

A_SDQ21

DDR_

A_SDQ22

DDR_

A_SDQ23

DDR_

A_SDQ24

DDR_

A_SDQ25

DDR_

A_SDQ26

DDR_

A_SDQ27

DDR_

A_SDQ28

DDR_

A_SDQ29

DDR_

A_SDQ30

DDR_

A_SDQ31

DDR_

A_SDQ32

DDR_

A_SDQ33

DDR_

A_SDQ34

DDR_

A_SDQ35

DDR_

A_SDQ36

DDR_

A_SDQ37

DDR_

A_SDQ38

DDR_

A_SDQ39

DDR_

A_SDQ40

DDR_

A_SDQ41

DDR_

A_SDQ42

DDR_

A_SDQ43

DDR_

A_SDQ44

DDR_

A_SDQ45

DDR_

A_SDQ46

DDR_

A_SDQ47

DDR_

A_SDQ48

DDR_

A_SDQ49

DDR_

A_SDQ50

DDR_

A_SDQ51

DDR_

A_SDQ52

DDR_

A_SDQ53

DDR_

A_SDQ54

DDR_

A_SDQ55

DDR_

A_SDQ56

DDR_

A_SDQ57

DDR_

A_SDQ58

DDR_

A_SDQ59

DDR_

A_SDQ60

DDR_

A_SDQ61

DDR_

A_SDQ62

DDR_

A_SDQ63

MEM_

MA_ZVDD IO

Plac

e them close to APU within 1"

DDR

A_SDQ[63 ..0] < 10>

_

1 2

RC3 39

.2_0402_ 1%

+1.2

V

A A

Secu

Secu

Secu

rity Classification

rity Classification

rity Classification

2018

2018

2018

/03/12 2019/03/ 12

/03/12 2019/03/ 12

Issued Date

Issued Date

Issued Date

THIS

THIS

THIS

SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

/03/12 2019/03/ 12

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Comp

Comp

Comp

al Electronics, Inc.

al Electronics, Inc.

Titl

Titl

Titl

e

e

e

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Cust

Cust

Cust

om

om

om

Date : Sheet

Date : Sheet

2

Date : Sheet

al Electronics, Inc.

Memo

Memo

Memo

ry

ry

ry

LA-G

LA-G

LA-G

241P

241P

241P

5 43Monday, March 12 , 2018

5 43Monday, March 12 , 2018

5 43Monday, March 12 , 2018

1

1.0

1.0

1.0

o f

o f

o f

5

D D

+1.8V

S

RPC14

APU_SVT

18

APU_SVC

27

APU_SVD

36
45

1

K_0804_8P4 R_5%

@

+1.8V

S

RPC1

1K

+1.8V

S

1 2

RC13 30

1 2

RC14 30

C C

B B

ESD

1 2

CC113 10 0P_

1 2

CC114 10 0P_

1 2

CC115 10 0P_

PU

on EC side

EC_SM

B_CK2<12,25>

EC_SM

B_DA2<12,25>

18
27
36
45

_0804_8P4R _5%

0_0402_5%
0_0402_5%

0402_50V8JESD@

0402_50V8JESD@

0402_50V8JESD@

H_PRO
APU_S
APU_A
APU_S

CHOT#
ID
LERT#
IC

APU_P
APU_R

+1.8V

6 1

D

QC2B
PJ

2

G

WRGD
ST#

H_PRO

CHOT#

APU_P

WRGD

APU_R

ST#

S

5

3 4

SGD

QC2A
PJ

T138KA_SOT36 3-6

S

T138KA_SOT36 3-6

APU_S

APU_S

H_PRO

APU_P

APU_S
APU_S
APU_S

IC

ID

4

UC1C

AY/SVI2/ JTAG/ TEST

DISPL

IC
ID
LERT#
CHOT#

WRGD
ST#

DI
DO

AE34
AM15
AM17
AM19

AP13
AP15
AP17
AR13
AR15
AR17

AU13
AU15
AU17

AV11
AV13
AV15
AV17

H27
E27
D27

B30
B29
A30
A31

G
D29

B25
A27
B27
B26
A29
A26
A25

D11
D13

E31
H11
H13

L11

AN8

AU4

AV7
AV9

AY3
AY7

SVT
SVC
SVD

SIC
SID
ALERT
PROCH

25

PWROK
RESET

TDI
TDO
TCK
TMS
TRST_L
DBRDY
DBREQ_L

VDD_18 Domain

D9

RSVD_
RSVD_
RSVD_

E4

RSVD_
RSVD_
RSVD_
RSVD_
RSVD_
RSVD_
RSVD_
RSVD_
RSVD_
RSVD_
RSVD_
RSVD_
RSVD_
RSVD_
RSVD_
RSVD_
RSVD_
RSVD_
RSVD_
RSVD_
RSVD_
RSVD_
RSVD_
RSVD_
RSVD_
RSVD_
RSVD_
RSVD_

A6-92

@

_L

OT_L

_L

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31

00E_BGA769

VT<38>
VC<38>
VD<38>

CHOT#<25>

WRGD<38>

APU_S
APU_S
APU_A
H_PRO

APU_P
APU_R

APU_T
APU_T
APU_TCK
APU_TMS
APU_TRST#
APU_DBRDY
APU_DBREQ#

VDD_1

8 Domain

but 3.3V tolerant

VDD_18 Domain

DP_ST

EREOSYNC/TEST36

VDDCR

VDDCR

VDDIO

VDD_18 Domain

DP_VA

DP_AU

_CPU_SENSE

_MEM_S3_SENSE

VDDP_

VSS_S
VSS_S

DP_BL

DP_DI

GON

RY_BL

X_ZVSS

DP_ZV

DP0_A

UXP

DP0_A

UXN

DP0_H

DP1_A

UXP

DP1_A

UXN

DP1_H

DP2_AUXP
DP2_AUXN

DP2_HPD

DP0_TXP0
DP0_TXN0
DP0_T
DP0_T
DP0_T
DP0_T
DP0_T
DP0_T

DP1_T
DP1_T
DP1_T
DP1_T
DP1_T
DP1_T
DP1_T
DP1_T

DP2_T
DP2_T
DP2_T
DP2_T
DP2_T
DP2_T
DP2_T
DP2_T

TEST4
TEST5
TEST6

TEST9
TEST1
TEST1
TEST1
TEST1
TEST1
TEST1
TEST1

TEST2

TEST2

TEST3

TEST4

_NB_SENSE

SENSE

ENSE_A
ENSE_B

3

ENBKL

B23

ON

B24
A24

D21
B18

SS

G15
H15
D15

PD

G17
H17
D17

PD

G19
H19
D19

A9
B9
A10

XP1

B10

XN1

A11

XP2

B11

XN2

A12

XP3

B12

XN3

A14

XP0

B14

XN0

A15

XP1

B15

XN1

A16

XP2

B16

XN2

A17

XP3

B17

XN3

A19

XP0

B19

XN0

A20

XP1

B20

XN1

A21

XP2

B21

XN2

A22

XP3

B22

XN3

H
G
H
R
N32

0

G21

4

H21

5

D23

6

E23

7

A28

8

B28

9

N8

8_H

N10

8_L

H31

1

D25
B31

1

D31
E33
D35
AM21

D33
AM23

_R

ENVDD

_R

INVT_

PWM_R

DP_AU

X_ZVSS

DP_ZVS

S

APU_T

29

APU_T

29

APU_T

25

APU_T

32

APU_T
APU_T
APU_T
APU_T
APU_T
APU_T
APU_T
APU_T
APU_T
APU_T
APU_T
APU_T

EST4
EST5
EST6
EST9
EST10
EST14
EST15
EST16
EST17
EST18
EST19
EST28_H
EST28_L
EST31
EST36
EST41

1 2

RC1

6 1

1 2

RC1

7 2

EDP_A
EDP_A
EDP_H

APU_D
APU_D
APU_D

EDP_TXP0 <17>
EDP_TXN0 <17>
EDP_T
EDP_T

APU_D
APU_D
APU_D
APU_D
APU_D
APU_D
APU_D
APU_D

T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T16

T18

T60

VSS_S

5

0_0402_1%

K

_0402_1%

UXP <17>
UXN <17>
PD <17>

P1_AUXP <18>
P1_AUXN <18 >
P1_HPD <18>

XP1 <17>
XN1 < 17>

P1_P0 <18>
P1_N0 <18>
P1_P1 <18>
P1_N1 <18>
P1_P2 <18>
P1_N2 <18>
P1_P3 <18>

<18>

P1_N3

APU_T
APU_T
APU_T

ENSE1

eDP

H

DMI

eDP

HDMI

EST17
EST16
EST14

T15
T19
T61

APU_V

DD_SEN <38>

APU_V

DDNB_SEN <38>

APU_V

DDP_RUN_FB _H <37>

APU_V

RPC2

18
27
36
45

1K

_0804_8P4R _5%

@

DD_RUN_FB_ L <38 >

2

+1.8V

S

QC1

2

Gat

e

1

ENBKL

_R

Drain

3

Sourc

S139WT1 G_SC70-3

LBS

e

+LCDVDD_CONN PWR switch enable pin VIH=1.2V

ENVDD

INVT_

_R

PWM_R

RC20 0_

1

2

ENBKL

_R

INVT_

PWM_R

1 2

+1.8V

S

5

UC21

P

NC

Y

A

G

74

AUP1G07GW_S C70-5

3

SA00005U600

RC22 100K_

RC24 4.7K_

APU_T
APU_T
APU_T

0402_5%@

+3VS

4

1 2

1 2

EST18
EST19
RST#

+3V

1 2

RC21

4.

1 2

RPC3

1 8
2 7
3 6
4 5

1K

S

8

RC1
2

2K_0402_5%

.

7K_0402_5%

0402_5%

0402_5%

+1.8V

_0804_8P4R _5%

S

ENBKL

APU_E

NVDD < 17>

APU_I

NVT_PWM <17>

1

<17,25>

HDT+

+3VS

5

UC22

1

P

NC

4

Y

APU_R

ST#_EC<25>

A A

5

2

A

G

74

AUP1G07GW_S C70-5

3

SA00007WE0 0
@

RC30 0_

12

0402_5%@

APU_R

ST#

Stoney Ridge FP4_FT4 Interlock July_2017 ver 2.1:
To enable HDMI, it must be pull ed up to 1.8V_S0 rail
by 1K ohm resistor

APU_T

EST36

4

1 2

RC25 1K

1 2

RC26 1K

_0402_5%

_0402_5%@

+1.8V

S

3

Debug conn - HDT@

+1.8V

S

JHDT1

APU_T

RST#

1 2

RC27 3

CC7 0.

1 8
2 7
3 6
4 5

Secur

Secur

Secur

ity Classification

ity Classification

ity Classification

Issued Date

Issued Date

Issued Date

THIS

THIS

THIS

SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

HDT@

3_0402_5%

HDT@

1 2

01U_0402_ 16V7K

RPC5

10

K_0804_8P4 R_5%

HDT@

APU_T

RST#_R

APU_T

RST#_R

HDT_P

11

HDT_P

13

HDT_P

HDT_P

11

HDT_P

13

HDT_P

15

2018/

2018/

2018/

03/12 2019/03/12

03/12 2019/03/12

03/12 2019/03/12

15

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciph

Deciph

Deciph

ered Date

ered Date

ered Date

1

3

5

7

9

11

13

15

17

19

2

2

1

2

4

3

4

6

5

6

8

7

8

10

9

10

12

11

12

14

13

14

16

15

16

18

17

18

20

19

20

S

AMTE_ASP-136446 -07-B

CONN@

+1.8V

S

APU_T

APU_T

APU_T

APU_T

APU_P

APU_R

APU_D

APU_D

APU_T

APU_T

CK

MS

DI

DO

WRGD

ST#

BRDY

BREQ#

EST19

EST18

APU_T
APU_T
APU_T
APU_D

Title

Title

Title

S

S

S

ize Document Number Re v

ize Document Number Re v

ize Document Number Re v
Custo

Custo

Custo

m

m

m

Date : Sheet

Date : Sheet

Date : Sheet

RPC4

CK

1 8

MS

2 7

DI

3 6

BREQ#

4 5

1K

HDT@

Compal El

Compal El

Compal El

Display

Display

Display

LA-G241P

LA-G241P

LA-G241P

_0804_8P4R _5%

ectronics, Inc.

ectronics, Inc.

ectronics, Inc.

/ SVI2

/ SVI2

/ SVI2

1

1.0

1.0

1.0

of

of

of

6 43Monday, March 12, 2018

6 43Monday, March 12, 2018

6 43Monday, March 12, 2018

5

4

3

2

1

PWRGD_R

SCL

SDA

C215

UC1D

AE4

PCI

_RST_L/EGPIO26

E

AG1

RSM

ST_L

R

AD2

PWR

BTN_L/AGPIO0

_

AE2

PWR

GOOD

_

AF1

SYS

RESET_L/AGPIO1

_

AE7

E

_L/AGPIO2

WAK

AC2

SLP

S3_L

_

AG4

_

S5_L

SLP

AB1

S0A

_GPIO/AGPIO10

3

AA7

S5_

UX_CTRL/EGPIO42

M

AF2

T

0

TES

AE1

TES

1/TMS

T

AC8

TES

2

T

AH2

AC_PRES/USB_OC4_L/IR_RX0/AGPIO23

AA4

IR_TX0/USB_OC5_L/AGPIO13

AG8

IR_TX1/USB_OC6_L/AGPIO14

AL5

IR_RX1/AGPIO15

AE8

IR_LED_L/LLB_L/AGPIO12

AY32

CLK_

REQ0_L/SATA_IS0_L/SATA_ZP0_L/AGPIO92

AY31

CLK_

REQ1_L/AGPIO115

AV29

CLK_

REQ2_L/AGPIO116

AP31

CLK_

REQ3_L/SATA_IS1_L/SATA_ZP1_L/EGPIO131

AV35

CLK_

REQG_L/OSCIN/EGPIO132

AB2

USB_

OC0_L/TRST_L/AGPIO16

AG2

USB_

OC1_L/TDI/AGPIO17

AJ1

USB_

OC2_L/TCK/AGPIO18

AH1

USB_

OC3_L/TDO/AGPIO24

AY6

AZ_B

ITCLK/I2S_BCLK_MIC

BA6

AZ_S

DIN0/I2S_DATA_MIC0

AY5

AZ_S

DIN1/I2S_LR_PLAYBACK

BA5

AZ_S

DIN2/I2S_DATA_PLAYBACK

AY4

AZ_R

ST_L/I2S_LR_MIC

BA3

AZ_S

YNC/I2S_BCLK_PLAYBACK

BA4

AZ_S

DOUT/I2S_DATA_MIC1

AY22

I2C0

_SCL/EGPIO145

BA22

I2C0

_SDA/EGPIO146

AU19

I2C1

_SCL/EGPIO147

AV19

I2C1

_SDA/EGPIO148

VDD_18 Domain
and OD ty pe

BA2

X32K

_X1

AY2

X32K

_X2

A6-9

200E_BGA769

@

+1.8

VS

12

12

RC146

RC147

.2K_0402_5%
2

1

1

C215

0

1

100P_0402_50V8J

2

2

@

@

SYS_

PWRGD_EC

.2K_0402_5%
2

5

34

SGD

QC17A
P

JT138KA_SOT363-6

+3VA

1

NC

2

A

1 2

RC64 0_

I

/SD/AZ/GP IO/RTC/MI SC

ACP

VDD_18_S5 Domain

2

G

61

S

D

QC17B
P

JT138KA_SOT363-6

LW

5

UC24

P

4

Y

G

74

AUP1G07GW_SC70-5

3

SA00007WE00
@

SD_

SD_

WR_CTRL/AGPIO102

P

SD_

SD_

SD_

SD_
SD_
SD_

SD_

SCL

/I2C2_SCL/EGPIO113

0

SDA

/I2C2_SDA/EGPIO114

0

1

/I2C3_SCL/AGPIO19

SCL
SDA

/I2C3_SDA/AGPIO20

1

AGPIO6/LDT_RST_L

AGPIO7/LDT_PWROK

BLIN

K/USB_OC7_L/AGPIO11

GENI

GA20

FANO

VDD_18 Domain

UART

0_CTS_L/EGPIO135

UART

UART

0_RTS_L/EGPIO137

UART

UART

UART

UART

+3VS

0402_5%@

0_INTR/AGPIO139

1_CTS_L/BT_I2S_BCLK/EGPIO140

UART

1_RXD/BT_I2S_SDI/EGPIO141

UART

1_RTS_L/EGPIO142

UART

1_TXD/BT_I2S_SDO/EGPIO143

1_INTR/BT_I2S_LRCLK/AGPIO144

12

12

RC144

RC145

.2K_0402_5%

.2K_0402_5%

2

2

+3VA

LW

12

RC63

4.

7K_0402_5%

APU_F

P/EGPIO101

W

SD_

D/AGPIO25

C

LK/EGPIO95

C

MD/EGPIO96

C

ED/EGPIO93

L

D

ATA0/EGPIO97
ATA1/EGPIO98

D

ATA2/EGPIO99

D

ATA3/EGPIO100

D

AGPIO3
AGPIO4
AGPIO5

AGPI
AGPI

AGPI

NT2_L/AGPIO90
SPKR

/AGPIO91

IN/AGPIO126

FANI

N0/AGPIO84

UT0/AGPIO85

0_RXD/EGPIO136

0_TXD/EGPIO138

HVBE

RTCC

I2C0_

SCL_TP <27>

I2C0_

SDA_TP <27>

CH_PWRGD_R

BA28
AY29
AY13

H

DETECT

DD_ODD_

BA14

PXS

RST#

_

AY15

DGP

PWR_EN

U_

BA29

BT_

FF#

O

AY14

O

FF#

WL_

BA13

DG

PU_PWRGD

APU_

BA16

MODE

_ID#

L

AY16

APU_

CLK0

S

AY33

APU_

DATA0

S

BA32

AC5
AC4

AJ7

AGPIO3

AK2
AK1
AL4
AJ2
AJ4

O8

AG5

O9

AD1

O40

AJ8

AGPI

O11

AR29
AP29
AU35

GATE

A20

AV33
AU33

AP23
AP25
AR25
AV25
AU23

AP21
AV21
AP19
AV23
AR21

AP27

N_L

RTC_CL

K

AN4

LK

RC12

9 0

RC13

0 0

RC16

4 0

H

DD_ODD_

PXS

RST# <11>

_

DGP

PWR_EN <13,25,40,41>

U_

1 2
1 2
1 2

S

CLK0 <10>

APU_
APU_

DATA0 <10>

S

TP_I

NT# <27>
APU_S
GATE

A20 <25>

T28

T26

RTC_CL

H

L

DETECT <24 >

_0201_5%@
_0201_5%@
_0402_5%@

PKR <19>

K <22>

APU_P

CIE_RST#_R

LPC_F
LPC_CL
LPC_CL

APU_

T_OFF#

B
W

L_OFF#

APU_

U_

PWRGD

DGP

DDR4

11/16 confirm with BIOS member

RC71 33

BOOT FAIL
TIMER
ENABLED

BOOT FAIL
TIMER
DISABLED
(DEFAULT)

RAME#<8,25>

K0_EC<8,25>
K1<8>

APU_

T_OFF# <22>

B

APU_

L_OFF# <22>

W

1 2

_0402_5%

150

CC9

1

P_0402_50V8J

2

Use 48MHz crystal
CLK and generate
both internal and
external CLK
(DEFAULT)

Use 100MHz PCIE
CLK as reference
CLK and generate
internal CLK only

+3VS

12

RC75
10

K_0402_5%

AGPI

O3

RTC_CL

K

SYS_

RST#

12

@

RC76
2K

_0402_5%

MC7

4VHC1G08DFT2G SC70 5P

APU_

DATA0

S

RC16

APU_

AGP

HDD_ODD_DETECT

HDD/

MODEL

_ID#

2 2

CLK0

S

RC16

3 2

I

O11

RC69 1

ODD Detect

0K_0402_5% @
0K_0402_5% @

Model size (reserve strap pin)

+3VA

LW

CC10

1 2

0.

1U_0201_10V6K

5

2

12

@

RC77
10

12

RC78
2K

SA00000OH00

LPC_

SPI ROM
(DEFAULT)

LPC ROM

K_0402_5%

_0402_5%

1

@

1 2

RC73 0_

FRAME#LPC_CLK0 _EC LPC_C LK1

ENHANCED RESET
LOGIC
(for quicker S5
resume)
(DEFAULT)

TRADITION
RESET

+3VA

12

RC79
10

K_0402_5%

12

@

RC80
2K

_0402_5%

P

B

Y

A

G

3

AGPIO3
<INT PU>

LW

4

UC23

0402_5%@

12

RC81
10

12

@

RC82
2K

1 2
1 2

@

K_0402_5%

_0402_5%

12
12

.2K_0402_5%
.2K_0402_5%

12

0

K_0402_5%@

12

RC15810K_0402_5%

12

RC15910K_0402_5% @ODD@

RC1561
RC1571

RTC_
<INT PU>

COIN BATT
ON BOARD
(DEFAULT)

COIN BATT
NOT ON
BOARD

12

RC83
10

K_0402_5%

12

@

RC84
2K

_0402_5%

+3V

S

+3V

LW

A

+3VS

Functio n

+3VS

APU_P

CLK

12

RC85
10

K_0402_5%

12

@

RC86
2K

_0402_5%

ODD

2nd HDD

CIE_RST# <11,20,22>

SYS_RST #
<INT PU>

NORMAL
RESET MODE
(DEFAULT)

SHORT RST
MODE

Detect

0

1

A

LW

+3V

1 2

RC34 2
RC35 2
RC36 1

D D

+3VS

+3VS

+3VS

C C

+3VS

+3VA

LW

1 2
1 2

@ESD@

1 2

CC16

2 1

HDA_SYNC_AUDIO<19>
HDA_SDOUT_AUDIO<19>
HDA_BITCLK_AUDIO<19>

RPC12

1 8
2 7
3 6
4 5

1

0K_0804_8P4R_5%

RPC13

1 8
2 7
3 6
4 5

1

0K_0804_8P4R_5%

1 2

RC133 1

1 2

RC134 1

1 2

RC41 10

1 2

RC44 10

1 2

RC45 10

1 2

RC46 10

.
.
K

00P_0402_50V8J

GATE

LAN_CL
CLK_

WLAN_

2K_0402_5%@
2K_0402_5%@

_0402_5%@

A20

REQ3#

0K_0402_5%UMA@
0K_0402_5%DIS@

K_0402_5%@

K_0402_5%@
K_0402_5%
K_0402_5%

KREQ#

CLKREQ#

APU_
APU_
APU_

E

MI

RPC6

1 8
2 7
3 6
4 5

33_0804_8P4R_5%

EMI@

VGA_

APU_B

PBTN_
USB_
USB_

EST0

T

EST2

T

EST1

T

SYS

E

SATA

DEVS
DEVS

CLKREQ#

T_OFF#

OUT#
OC0#
OC1#

_

RST#

SD

_ACT# <8>

LP1 <8>
LP0 <8>

HDA_SYNC
HDA_SDOUT
HDA_BITCLK

RPC9

1 8
2 7
3 6
4 5

1K

_0804_8P4R_5%

1 2

RC49 10

12

RC52 10

12

RC53 10

12

RC54 10

1 2

RC160 1

1 2

RC161 1

DGPU_

K_0402_5%@
K_0402_5%
K_0402_5%

K_0402_5%@
0K_0402_5%
0K_0402_5%

PBT

N_

PM_

S

PM_

S

M

UX_CTRL<9>

S5_

1 2

RC38 1

1 2

RC39 1

1 2

RC40 1

LAN_CL

WLAN_

CLKREQ#< 22>

VGA_

CLKREQ#<12>

USB_

HDA_S
HDA_S
HDA_RS

HDA_B
HDA_S
HDA_S
HDA_S
I2C1_
I2C1_

SCL
SDA

RC66 0_

HDA_S

DOUT
YNC

T#

ITCLK
DIN1
DIN2
DIN0

PWRGD<40>

OUT#<25>

LP_S3#<25>
LP_S5#<25,33,36>

KREQ#<20>

OC1#<26>

1 2

DIN0<19>

T31

5
5
5

K_0402_5%
K_0402_5%
K_0402_5%

0402_5%@

APU_

EC_RS

PBT
APU_
SYS
APU_

PM_
PM_

S5_

LAN_CL

WLAN_
CLK_
VGA_

USB_
USB_

HDA_B
HDA_S
HDA_S
HDA_S
HDA_RS
HDA_S
HDA_S

I2C0_
I2C0_
I2C1_
I2C1_

32K_

32K_

CIE_RST#_R

P

RST#_R

M

OUT#

N_

CH_PWRGD_R

F
RST#

_

CIE_WAKE#

P

LP_S3#

S

LP_S5#

S

UX_CTRL

M

APU_
APU_
APU_

KREQ#

CLKREQ#
REQ3#
CLKREQ#

OC0#
OC1#

DGPU_

ITCLK
DIN0
DIN1
DIN2

T#
YNC
DOUT

SCL
SDA
SCL
SDA

X1

X2

EST0

T
T

EST1
EST2

T

I2C Port 0: Touch Pad

+1.8

VALW

1 2

RC59 0_

EC_RSM

B B

RST#<25>

RB751 Ma x Vf=0.37V

1 2

DC3
RB75

1V-40 SOD-323

SCS00003500

0402_5%@

@

EC_RSM

47

K_0402_5%

RST#_R

12

RC60

2

CC8

0.1

U_0201_10V6K

1

I2C0_

I2C0_

100P_0402_50V8J

32.768KMHz CRYSTAL

32K_

X1

32K_

1

CC12

12

P_0402_50V8J

2

X2

EC

SYS_

PWRGD_EC<25>

12

RC87 20

M_0402_5%

YC32

1 2

32

.768KHZ_9PF_X1A000141000200

1

CC11

12

P_0402_50V8J

2

A A

Secu

Secu

Secu

rity Classification

rity Classification

rity Classification

Issu

Issu

Issued Date

ed Date

ed Date

THIS

THIS

THIS

SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPER TY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPER TY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPER TY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE C OMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHE R THIS SHEET NOR THE INFORM ATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHE R THIS SHEET NOR THE INFORM ATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHE R THIS SHEET NOR THE INFORM ATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS , INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS , INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS , INC.

2018

2018

2018

Comp

Comp

Compal Secret Data

al Secret Data

2

al Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

/03/12 2019/03/12

/03/12 2019/03/12

/03/12 2019/03/12

Comp

Comp

Comp

al Electronics, Inc.

al Electronics, Inc.

Titl

Titl

Title

e

e

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

Cust

Cust

Cust

om

om

om

Date : Sheet

Date : Sheet

Date : Sheet

al Electronics, Inc.

GPIO

GPIO

GPIO

/ AZ / I2C

/ AZ / I2C

/ AZ / I2C

LA-G

LA-G

LA-G

241P

241P

241P

1

7 43Monday, March 12, 2018

7 43Monday, March 12, 2018

7 43Monday, March 12, 2018

1.0

1.0

1.0

of

of

of

5

4

3

2

1

UC1E

SATA_

ATX_DRX _P0<23>

SATA_

HDD

D D

+0.95VS

O

DD

RC88 1K_0402 _1%
RC89 1K_0402 _1%

GPU

LAN

WLA

N

C C

B B

+3VS

RC90 10

RC112 1

LPC_R

ST#<25>

1 2

1 2

K_0402_ 5%@

0K_0402 _5%

10

RC94

0K_0402_5%

@

1 2

KBRST

LPC_P

D#

1 2

RC93 33_04

15

CC13

0P_0402_50V8J

1

2

ATX_DRX _N0<23>

ARX_DTX _N0<23>

SATA_

ARX_DTX _P0<23>

SATA_

ATX_DRX _P1<24>

SATA_
SATA_

ATX_DRX _N1<24>

SATA_

ARX_DTX _N1<24>

SATA_

ARX_DTX _P1<24>

12
12

SATA_

ACT#<7>

DEVSL

P0<7>

DEVSL

P1<7>

CLK_P

EG_VGA<11>

CLK_P

EG_VGA#<11>

CLK_P

CIE_LAN<20>

CLK_P

CIE_LAN#<20>

CLK_P

CIE_WL AN<22 >

CLK_P

CIE_WL AN#<22>

#

LPC_C

LK0_EC<7,25>

LPC_C

LK1<7>

LPC_F

RAME#<7,25>

LPC_A

D0<25>

LPC_A

D1<25>

LPC_A

D2<25>

LPC_A

D3<25>

02_5%

LPC_C

LKRUN#< 25>

EC_SC

I#<25>

SERIR

Q<25>

SATA_ZV SS
SATA_ZV DDP

48M_X

1

48M_X

2

LPC_R

ST#_R

LPC_P

D#

BA10
AY10

AY12
BA12

AY9
BA9

BA8
AY8

AU11
AP11

AY30
AV31
AU31

AU27

BA25
BA24
AY24
BA
AY
AY
AY

AY27
AY26

AC1

AA8
BA27
AV27

H2
H1

M2
M1

L2
L1

K2
K1

J2
J1

F2

F1

26
28
25
23

A6-92

@

SATA_

TX0P

SATA_

TX0N

SATA_

RX0N

SATA_

RX0P

SATA_

TX1P

SATA_

TX1N

SATA_

RX1N
RX1P

SATA_

SATA_ZVSS
SATA_ZVDDP

SATA_

ACT_L/AGPIO130

DEVSL

P0/EGPIO67

DEVSL

P1/EGPIO70

GFX_C

LKP

GFX_C

LKN

GPP_C

LK0P

GPP_C

LK0N

GPP_C

LK1P

GPP_C

LK1N

GPP_C

LK2P

GPP_C

LK2N

GPP_C

LK3P

GPP_C

LK3N

X48M_

X1

X48M_

X2

X25M_

48M_OSC

LPCCL

K0/EGPIO74

LPCCL

K1/EGPIO75

LFRAM

E_L
LAD0
LAD1
LAD2
LAD3

LPC_R

ST_L

LPC_C

LKRUN_L/AGPIO88

LPC_P

D_L/AGPIO21

LPC_P

ME_L/AGPIO22

LPC_S

MI_L/AGPIO86

SERIR

Q/AGPIO87

00E_BGA 769

48MHz CRYSTAL

48M_X

2_R

48M_X

1

1

4

4

1

2

1_R

YC48
48

MHZ_8PF _7V48000010

SJ10000 JP00

CC15

6.

8P_0402 _50V8C

RC103 1

2

2

A A

3

3

1

CC16

6.

8P_0402 _50V8C

2

12

M_0402_ 5%

5

1 2

RC105 3

1 2

RC104 3

3_0402_ 5%EMI@

3_0402_ 5%EMI@

EMI

48M_X

2

48M_X

1

APU_S

PI_CS1#

APU_S

PI_MISO

APU_S

PI_WP#

Securit

Securit

Securit

y Classification

y Classification

y Classification

Issued Date

Issued Date

Issued Date

THIS

THIS

THIS

SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

CLK/S

VDD_18 Domain
but OD type

8MB S

UC2

1

CS#

2

DO(IO

1)

3

WP#(I

O2)

4

GND

XM2

5QU64AH IGT SOP 8P

SA0000B JU00

ATA/USB/SPI/LPC

USBCL

K/25M_48M_OSC

USB_S

VDD_18 Domain

SPI_C

LK/ESPI_CLK/EGPIO117

SPI_D

O/ESPI_DAT0/EGPIO121

SPI_D

I/ESPI_DAT1/EGPIO120

SPI_H

OLD_L/ESPI_DAT3/EGPIO133

SPI_W

P_L/ESPI_DAT2/EGPIO122

SPI_C

SPI_T

PM_CS_L/AGPIO76

ESPI_

ESPI_

SPI_C

ALERT_L/LDRQ0_L

RESET_L/KBRST_L/AGPIO129

S2_L/ESPI_CS_L/EGPIO119

PI ROM

8

VCC

HOLD#

7

(IO3)

6

CLK

5

DI(IO

0)

2018/

2018/

2018/

03/12 2019/03/1 2

03/12 2019/03/1 2

03/12 2019/03/1 2

3

USB_Z

VSS

USB_H

SD0P

USB_H

SD0N

USB_H

SD1P
SD1N

USB_H

SD2P

USB_H
USB_HSD2N

USB_HSD3P
USB_HSD3N

USB_H

SD4P

USB_H

SD4N

USB_H

SD5P

USB_H

SD5N

USB_H

SD6P

USB_H

SD6N

USB_H

SD7P

USB_H

SD7N

USB_S

S_ZVSS

S_ZVDDP

USB_S

S_0TXP

USB_S

S_0TXN

USB_S

S_0RXP

USB_S

S_0RXN

USB_S

S_1TXP

USB_S

S_1TXN

USB_S

S_1RXP

USB_S

S_1RXN

USB_S

S_2TXP

USB_S

S_2TXN

USB_S

S_2RXP

USB_S

S_2RXN

S1_L/EGPIO118

APU_S

PI_HOLD#

APU_S

PI_CLK_R

APU_S

PI_MOSI

AL8

USB_Z

AN7

AW1
AW2

AV1
AV2

AU1
AU2

AT1
AT2

AR1
AR2

AP1
AP2

AN1
AN2

AM1
AM2

W4
W5

T1
T2

V2
V1

R1
R2

W2
W1

P1
P2

Y2
Y1

AY17
AY20
BA17
BA18
BA20
AY21
BA21

AY18
BA30
AY19

Compal Secret Data

Compal Secret Data

Compal Secret Data

VSS

USB20
USB20

USBSS
USBSS

APU_S
APU_S
APU_S
APU_S
APU_S
APU_S

KBRST
APU_S

+1.8V

S

1

CC14

0.

1U_0201 _10V6K

2

Deciphered Date

Deciphered Date

Deciphered Date

_ZVSS
_ZVDD

PI_CLK
PI_MOSI
PI_MISO
PI_HOLD#
PI_WP#
PI_CS1#

#

PI_CS2#

@

1 2

RC108 1

_P2
_N2

1 2

RC100 1

1 2

RC101 1

KBRST

1.8K_040 2_1%

USB20

_P1 <22>

USB20

_N1

USB20_P 3 <21>
USB20_N 3 <21>

USB20

_P5 < 26>

USB20

_N5

USB20

_P6 < 26>

USB20

_N6

K_0402_ 1%
K_0402_ 1%

USB3_

ATX_DRX _P1 <26>

USB3_

ATX_DRX _N1 <26>

USB3_

ARX_DTX _P1 <26>

USB3_

ARX_DTX _N1 < 26>

USB3_

ATX_DRX _P2 <26>

USB3_

ATX_DRX _N2 <26>

USB3_

ARX_DTX _P2 <26>

USB3_

ARX_DTX _N2 <26>

RC102 3

# <25>

USB20

_N2

USB20

_P2

+1.8V

2

T

<22>

B

Camera

Card Reader

<26>

<26>

USB 3.0 (MB)

USB 3.0 (MB)

+0.95

VALW

USB 3

.0 (MB)

USB 3.0 (MB)

APU_S

12

3_0402_ 5%EMI@

PI_CLK_R

EMI

1 2

R951 0_

1 2

R950 0_

S

0402_5%@

0402_5%@

RPC11

1 8
2 7
3 6
4 5

1

0K_0804 _8P4R_5%

Compa

Compa

Title

Title

Title

S

S

S

ize Document Number Re v

ize Document Number Re v

ize Document Number Re v
Custo

Custo

Custo

Date : Sheet

Date : Sheet

Date : Sheet

Compa

SATA

SATA

SATA

m

m

m

SPI R

USB20

_N2_R

USB20

_P2_R

APU_S

PI_HOLD#

APU_S

PI_WP#

APU_S

PI_CS1#

APU_S

PI_CS2#

l Electronics, Inc.

l Electronics, Inc.

l Electronics, Inc.

/ USB / LPC / SPI

/ USB / LPC / SPI

/ USB / LPC / SPI

LA-G2

LA-G2

LA-G2

41P

41P

41P

1

OM

USB20

USB20

_N2_R <17 >

_P2_R <17>

o f

o f

o f

8 43Monday, March 12 , 2018

8 43Monday, March 12 , 2018

8 43Monday, March 12 , 2018

1.0

1.0

1.0

5

4

3

2

1

AJ31

R19
H23

A2

A8
A13
A18
A23
A32
A35
A39

B8
B13
B32
B39

C3
C5
C7

C9
C11
C13
C15
C17
C19
C21
C23
C25
C27
C29
C31
C33
C35
C37
C39
C41

E1
E2

E3
E21
E25
E29
E35
E38
E39

G1
G2

G3
G11
G13
G23
G27
G31
G35
G37
G39
G41

J3
J8

J39

L3
L8

0K_0402_5%

UC1G

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_

A6-9

@

215

_

214

_

213

_

1

_
_

2
3

_

4

_

5

_
_

6
7

_

8

_

9

_

10

_
_

11
12

_

13

_

21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58

200E_BGA769

1.5V

+RTCBA

1

CC18

0.

22U_0402_6.3V6K

2

GND

L13

VSS

59

_

L19

VSS

60

_

L21

VSS

61

_

L23

VSS

62

_

L25

_

63

VSS

L27

VSS

64

_

L29

VSS

65

_

L31

VSS

66

_

L39

_

67

VSS

L41

VSS

68

_

N1

VSS

69

_

N2

VSS

70

_

N3

VSS

71

_

N39

_

72

VSS

R3

VSS

73

_

R11

VSS

74

_

R13

VSS_75

R15

VSS_76

R17

VSS_77

R21

VSS_78

R23

VSS_79

R25

VSS_80

R27

VSS_81

R29

VSS_

82

R31

VSS_

83

R39

VSS_

84

R41

VSS_

85

U1

VSS_

86

U2

VSS_

87

U3

VSS_

88

U10

VSS_

89

U39

VSS_

90

W3

VSS_

91

W10

VSS_

92

W11

VSS_

93

W13

VSS_

94

W15

VSS_

95

W17

VSS_

96

W19

VSS_

97

W21

VSS_

98

W23

VSS_

99

W25

VSS_

100

W27

VSS_

101

W29

VSS_

102

W31

VSS_

103

W39

VSS_

104

W41

VSS_

105

AA1

VSS_

106

AA2

VSS_

107

AA3

VSS_

108

AA5

VSS_

109

AA10

VSS_

110

AA39

VSS_

111

AC3

VSS_

112

AC7

VSS_

113

AC10

VSS_

114

AC11

VSS_

115

AC13

VSS_

116

AC15

VSS_

117

AC17

VSS_

118

AC19

VSS_

119

W>=15mils

+RTCBA

UC25

TT_R

3

Vout

1

Vin

2

GND

AP

2138N-1.5TRG1_SOT23-3

SA000066U00

12

AA35
AC32
AC37
AE32
AE35
AG32
AG37

AR35

AA25
AA27
AA29
AA31

AM11
AM13

UC1F

J35
L32

L37
N35
R37
U32
U35
W32
W37

AJ32
AJ35
AL32
AL37

K21
K23
K25
K27
K29
K31
N21
N23
N25
N27
N29
N31
U23
U25
U27
U29
U31

AR4
AR5
AR7
AU7

AJ11
AL11
AL13

AJ21
AJ23
AJ25
AJ27
AL23
AL25
AL27
AL29

A6-9

@

+1.

V

CC42 1

80P_0402_50V8J

1

2

CC37 1

1

80P_0402_50V8J

2

CC43 1

1

80P_0402_50V8J

2

2

U

nder APU

+1.2V

+APU_

CORE

+1.

V

2

CC21 2

CC23 2

CC22 2

CC20 2

1

1

1

1

2U_0603_6.3V6M

2U_0603_6.3V6M

2U_0603_6.3V6M

2U_0603_6.3V6M

2

2

2

2

D D

1 2

RC120 0_0402_5%@

CC28 2

CC30 22U_0603_6.3V6M

CC26 2

CC24 2

1

2U_0603_6.3V6M

2

CC29 22U_0603_6.3V6M

CC27 2

CC25 2

1

1

1

1

1

1

@

@

@

2U_0603_6.3V6M

2U_0603_6.3V6M

2U_0603_6.3V6M

2U_0603_6.3V6M

2

2

2

2

2

2

+3VS_APU+3VS

CC76 0

CC44 1

1

1

.22U_0402_6.3V6K

0U_0603_6.3V6M

2

2

CC31 0

1

.22U_0402_6.3V6K

2

CC36 0

CC35 0

CC32 0

CC33 0

CC34 0

1

1

1

1

1

.22U_0402_6.3V6K

.22U_0402_6.3V6K

.22U_0402_6.3V6K

.22U_0402_6.3V6K

.22U_0402_6.3V6K

2

2

2

2

2

CC41 0

CC38 0

CC39 0

CC40 0

1

1

1

1

.22U_0402_6.3V6K

.22U_0402_6.3V6K

.22U_0402_6.3V6K

.22U_0402_6.3V6K

2

2

2

2

DIMMS /GND

Under APU ACROSS +1.2V_V DDQ AND VSS SPLIT

+APU_

CORE_NB

C C

CC72 0

CC74 0

CC73 0

CC75 0

1

1

.22U_0402_6.3V6K

.22U_0402_6.3V6K

2

2

CC45 22U_0603_6.3V6M

1

1

.22U_0402_6.3V6K

1

.22U_0402_6.3V6K

2

2

2

+1.8

VS

CC47 0

CC46 10U_0603_6.3V6M

1

1

.22U_0402_6.3V6K

2

2

CC48 1

12

U_0201_6.3V6M

Out s ide of APU

+3VA

CC51 1

1

0U_0603_6.3V6M

2

LW

CC52 0

1

.22U_0402_6.3V6K

2

+1.8

CC53 1

0U_0603_6.3V6M

VALW

CC54 0

1

1

.22U_0402_6.3V6K

2

2

+0.9

CC70 1

0U_0603_6.3V6M

5VALW

CC71 0

1

1

.22U_0402_6.3V6K

2

2

CC49 1

CC50 1

12

12

U_0201_6.3V6M

U_0201_6.3V6M

Under APU

CC56 1

CC55 1

1

1

0U_0603_6.3V6M

0U_0603_6.3V6M

2

2

+1.8

VS

+VDDCR_F

CH_ALW

+0.9

5VALW

0.8A

+0.9

5VS

7

A

+VDDCR_F

CH_ALW

CC57 0

1

.22U_0402_6.3V6K

2

+RTC_B

ATT

+1.8

VS

0.2A

W>=15mils

Under APUUnder APUUnder APUUnder APU

B B

+0.95VS OF APU

+0.9

5VS

CC61 1

CC60 1

CC59 1

CC58 1

1

1

1

12

U_0201_6.3V6M

0U_0603_6.3V6M

0U_0603_6.3V6M

0U_0603_6.3V6M

2

2

2

+0.9

5VS

CC62 10U_0603_6.3V6M

CC63 0.22U_0402_6.3V6K

1

1

2

2

VDD

O_MEM_S3_1

I

VDD

O_MEM_S3_2

I

VDD

O_MEM_S3_3

I

VDD

O_MEM_S3_4

I
I

O_MEM_S3_5

VDD
VDD

O_MEM_S3_6

I

VDD

O_MEM_S3_7

I

VDD

O_MEM_S3_8

I
I

O_MEM_S3_9

VDD
VDD

O_MEM_S3_10

I

VDD

O_MEM_S3_11

I

VDD

O_MEM_S3_12

I

VDD

O_MEM_S3_13

I
I

O_MEM_S3_14

VDD
VDD

O_MEM_S3_15

I

VDD

O_MEM_S3_16

I
VDDIO_MEM_S3_17
VDDIO_MEM_S3_18
VDDIO_MEM_S3_19
VDDIO_MEM_S3_20
VDDIO_MEM_S3_21

VDDC

R_CPU_1

VDDC

R_CPU_2

VDDC

R_CPU_3

VDDC

R_CPU_4

VDDC

R_CPU_5

VDDC

R_CPU_6

VDDC

R_CPU_7

VDDC

R_CPU_8

VDDC

R_CPU_9

VDDC

R_CPU_10

VDDC

R_CPU_11

VDDC

R_CPU_12

VDDC

R_CPU_13

VDDC

R_CPU_14

VDDC

R_CPU_15

VDDC

R_CPU_16

VDDC

R_CPU_17

VDDC

R_CPU_18

VDDC

R_CPU_19

VDDC

R_CPU_20

VDDC

R_CPU_21

VDDC

R_FCH_S5_1

VDDC

R_FCH_S5_2

VDDC

R_FCH_S5_3

VDDC

R_FCH_S5_4

VDDP

_S5_1

VDDP

_S5_2

VDDP

_S5_3

VDDP

_1

VDDP

_2

VDDP

_3

VDDP

_4

VDDP

_5

VDDP

_6

VDDP

_7

VDDP

_8

VDDB

T_RTC_G

VDDI

O_AUDIO

200E_BGA769

POW

R

E

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDCR_NB_17
VDDCR_NB_18
VDDCR_NB_19
VDDCR_NB_20
VDDCR_NB_21
VDDCR_NB_22
VDDCR_NB_23
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC

EC_CLE

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDD_
VDD_

VDD_
VDD_

AR_CMOS#<25>

R_NB_1

C

R_NB_2

C

R_NB_3

C

R_NB_4

C
C

R_NB_5
R_NB_6

C

R_NB_7

C

R_NB_8

C
C

R_NB_9

R_NB_10

C

R_NB_11

C

R_NB_12

C

R_NB_13

C
C

R_NB_14
R_NB_15

C

R_NB_16

C

R_NB_24
R_NB_25
R_NB_26
R_NB_27
R_NB_28
R_NB_29
R_NB_30
R_NB_31
R_NB_32
R_NB_33
R_NB_34
R_NB_35
R_NB_36
R_NB_37
R_NB_38
R_NB_39
R_NB_40
R_NB_41
R_NB_42
R_NB_43
R_NB_44
R_NB_45
R_NB_46
R_NB_47
R_NB_48
R_NB_49
R_NB_50

VDD_
VDD_

18_S5_1
18_S5_2

VDD_
VDD_

33_S5_1
33_S5_2

18_1
18_2

33_1
33_2

E9
E11
E13
E15
E17
E19
G7
J7
K11
K13
K15
K17
K19
L7
L10
L15
L17
N7
N11
N13
N15
N17
N19
R7
U7
U11
U13
U15
U17
U19
U21
W7
AA11
AA13
AA15
AA17
AA19
AA21
AA23
AE11
AE13
AE15
AE17
AE19
AE21
AE23
AE25
AE27
AE29
AE31

AJ15
AL17

AJ13
AL15

AJ19
AL21

AJ17
AL19

RC111 0

1.5A

0.5A

0.2A

0.2A

1 2

+AP

CORE_NB

U_

+1.8

VS

+1.8

VALW

+3VS

_APU

+3VA

LW

W>=15mils

+RTC_B

ATT

1 2

_0402_5%@

RC113 1

@

12

CLRP1
S

HORT PADS

TT

CC19
1U_

AC21
AC23
AC25
AC27
AC29
AC31
AC38
AC39
AC41

AE3

AE5
AE10
AE39

AG3

AG7
AG10
AG11
AG13
AG15
AG17
AG19
AG21
AG23
AG25
AG27
AG29
AG31
AG39
AG41

AJ3

AJ5

AJ10
AJ29
AJ39

AL1

AL2

AL3

AL7

AL10
AL31
AL39

AL41
AM25
AM27
AM29
AM31

AN3
AN5

AN39

AR3
AR11
AR19
AR23
AR27
AR31
AR39
AR41

AU3

AU9
AU21
AU25
AU29

0201_6.3V6M

UC1H

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_

A6-9

200E_BGA769

@

GND

AU39

VSS

120

182

_

_

AW3

VSS

121

183

_

_

AW5

VSS

122

184

_

_

AW7

VSS

123

185

_

_
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_

AW9

_

186

AW11

187

_

AW13

188

_

AW15

189

_

AW17

_

190

AW19

191

_

AW21

192

_

AW23

193

_

AW25

194

_

AW27

_

195

AW29

196

_

AW31

197

_

AW33
AW35
AW37
AW39
AW41
AY1
AY11
BA7

205

BA11

206

BA15

207

BA19

208

BA23

209

BA31

210

BA35

211

BA39

212

_

124
125

_

126

_

127

_
_

128
129

_

130

_

131

_

132

_
_

133
134

_

135

_

143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181

+5VALW+0.7

75VALW

1

RC153

Out s ide of APU

+3VA

+0.9

CC69 180P_0402_50V8J

1

2

Under APU

5VS

S5_M

UX_CTRL<7>

4

CC64 1

CC65 1

1

1

0U_0603_6.3V6M

0U_0603_6.3V6M

2

2

A A

CC68 0.22U_0402_6.3V6K

CC66 1

CC67 1

1

1

1

0U_0603_6.3V6M

0U_0603_6.3V6M

2

2

2

5

1 2

2

N7002KDW_SOT-363-6

S5_MUX_C TRL:
Enable MUX(S0 to S3)-->LOW
Disable MUX(S3 to S0)-->HIGH

00K_0402_5%

LW

1

RC152

00K_0402_5%

5

QC22A

QC22B
2

N7002KDW_SOT-363-6

1 2

61

D

G

2

S

34

+0.7

R944
1

00K_0402_5%

1 2

75MOS

D

G

S

+APU_

CORE_NB

3

+5VA

LW

12

8

UC26A

3

P

+

2

+0.7

75MOS

-

G

A

S393MTR-G1_SO8

4

Secu

Secu

Secu

THIS

THIS

THIS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE C OMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHE R THIS SHEET NOR THE INFORM ATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHE R THIS SHEET NOR THE INFORM ATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHE R THIS SHEET NOR THE INFORM ATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS , INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS , INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS , INC.

RC150

1

K_0402_5%

CORE_

ed Date

ed Date

5

6

NB_GATE

+5VA

LW

12

8

P

+

-

G

4

RC151

UC26B

1

K_0402_5%

0.77

5VALW_GATE

7

O

A

S393MTR-G1_SO8

Comp

Comp

Compal Secret Data

al Secret Data

2018

2018

2018

/03/12 2019/03/12

/03/12 2019/03/12

/03/12 2019/03/12

al Secret Data

2

4

.7U_0402_6.3V6M

Deciphered Date

Deciphered Date

Deciphered Date

1

O

rity Classification

rity Classification

rity Classification

Issu

Issu

Issued Date

SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPER TY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPER TY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPER TY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

4

.7U_0402_6.3V6M

+0.7

75VALW

2

CC130

1

+APU_

CC129

CORE_NB

2

1

QC18
AO

1 3

D

QC20
AO

1 3

D

QC19
AO

3416L_SOT23-3

S

S

G

G

2

2

2

QC21

AO

3416L_SOT23-3

S

S

G

G

2

Titl

Titl

Titl

e

e

e

Size

Size

Size

Cust

Cust

Cust

om

om

om

Date : Sheet

Date : Sheet

Date : Sheet

+VDDCR_F

3416L_SOT23-3

D

13

CORE_

NB_GATE

3416L_SOT23-3

D

13

0.77

5VALW_GATE

Comp

Comp

Comp

Document Number Re v

Document Number Re v

Document Number Re v

2
2U_0603_6.3V6M

12

CC132

2

CC131
4

.7U_0402_6.3V6M

1

al Electronics, Inc.

al Electronics, Inc.

al Electronics, Inc.

Powe

Powe

Powe

r / GND

r / GND

r / GND

LA-G

LA-G

LA-G

241P

241P

241P

1

CH_ALW

2

4

4

2U_0603_6.3V6M

.7U_0402_6.3V6M

.7U_0402_6.3V6M

2

2

12

CC133

CC134

CC135

1

1

of

of

of

9 43Monday, March 12, 2018

9 43Monday, March 12, 2018

9 43Monday, March 12, 2018

1.0

1.0

1.0

5

Stone

D D

C C

B B

+3V

PLACE

A LL THE BELOW RESISTO RS CLOS E TO SODIM M

SPD ADDRESS FOR CHANNEL A :
SA0 = 0; SA1 = 0; SA2 = 0.

Layout Note:
Place near JDIMM1.257,259

+2.5V +0.6V

10

CD203

U_0603_6.3V6M

1

@

2

Layout Note:
PLACE THE CAP near JDIMM1. 164

+0.6V

_DDR_VREFCA

2

CD210

0.

1U_0201_10V6K

1

y So-DIMM1

S

CRB has no reserve PU

12

@

2

RD20
1

K_0402_5%

0

12

@

RD205
0_0402_5%

1U_

10

CD204

U_0603_6.3V6M

1

12

0201_6.3V6M

2

CD205

1

@

2

2

CD211
10

1

+3V

10uF*
1uF*2

0.1U_0201_10V6K

CD206

CRB:
1u

*1

0.1u *2
180p *1

CAUSD:
1u *1
10u *1

1000pF* 1

0.1uF* 1

00P_0402_50V7K

S

12

@

RD20
1

12

@

RD206
0_0402_5%

2

K_0402_5%

0

+3V

3

12

12

Layout Note:
Place near JDIMM1.258

follow CRB
CAUSD only 0.1u*1 follow CAUSD

S

@

RD20
1

0

@

RD207
0_0402_5%

S

4.
7U_0402_6.3V6M

1

2

4

K_0402_5%

SA2_DIM1SA1_DIM1SA0_DIM1

CD207

1

2

+3VS

2

1

0.
1U_0201_10V6K

0.
1U_0201_10V6K

10uF*2
1uF*1

CD208

2

CD201

1

CRB only 1u*1

2.
2U_0402_6.3V6M

CD202

PLACE NEAR TO PIN

Layout Note:
Place near JDIMM1

CAUSD:

CRB DIMM1 is

10uF*8

0.1u *7

1uF*8

0.1u reseve *6
100u *2

10

10

U_0603_6.3V6M

U_0603_6.3V6M

CD214

CD215

1

1

1

@

2

2

2

A A

330uF* 1

10

10U_0603_6.3V6M

U_0603_6.3V6M

CD216

CD217

1

1

2

2

10

10U_0603_6.3V6M

10

U_0603_6.3V6M

U_0603_6.3V6M

CD220

CD218

CD219

1

1

2

2

@

10u *6
10u reseve *2
1u *4

+1.2V+1.2V

1u reserve*4
330u reserve *1

10
U_0603_6.3V6M

1U_

1U_

1U_

CD222

CD223

CD221

1

12

0201_6.3V6M

2

CD224

12

12

0201_6.3V6M

0201_6.3V6M

4

D

S

DQ[63..0]<5>

DR_A_

D

S

DM[7..0]<5>

DR_A_

DR_A_

MA[13..0]<5>

D

S

+1.2V

DIMM Side

+0.6V

0_

_0402_5%

0402_5%@

_DDR_VREFCA

2

CD213

0.

1U_0201_10V6K

1

DDR_A_A

DDR_A_P

LERT#

AR

@

2

CD212

0.

1U_0201_10V6K

1

RD208
1K

_0402_1%

1 2

RD209
1K

_0402_1%

1 2

+1.2V

1 2

RD201 1K

1 2

RD210

+1.2V

1U_

1U_

1U_

1U_

CD225

CD226

12

12

12

0201_6.3V6M

0201_6.3V6M

1U_

CD227

CD228

CD229

12

0201_6.3V6M

0201_6.3V6M

1

12

0201_6.3V6M

+

CD230

@

33

0U_D3_2.5VY_R6M

2

3

DR_A_

DQ5

D

S

D

S

DQ1

D

S

DR_A_

D

S

DR_A_

DDR_A_SDQS2#< 5>
DDR_A_SDQS2<5>

DR_A_

DQS0#<5>
DQS0<5>

D

S

DQ7

DR_A_

D

S

DQ3

DR_A_

DR_A_

DQ13

D

S

D

S

DQ9

DR_A_

D

S

DM1

DR_A_

D

S

DQ15

DR_A_

DR_A_

DQ10

D

S

D

S

DQ21

DR_A_

DDR_A_SDQ17

DDR_A_SDQ23

DDR_A_S

DQ18

DDR_A_S

DQ24

DDR_A_S

DQ29

DDR_A_S

DM3

DDR_A_S

DQ30

DDR_A_S

DQ26

For E CC DIM M For E CC DIM M

DDR_A_CK

E0<5>

DDR_A_S

BG1<5>

DDR_A_S

BG0<5>

DDR_A_S

MA12

DDR_A_S

MA9

DDR_A_S

MA8

DDR_A_S

MA6

DDR_A_S

MA3

DDR_A_S

DDR_A_CL

K0<5>

DDR_A_CL

K0#<5>

DDR_A_S

BS1#<5>

DDR_A_S

CS0#<5>

DDR_A_S

WE#<5>

DDR_A_O

DT0<5>

DDR_A_S

CS1#<5>

DDR_A_O

DT1<5>

DDR_A_S

DQS4#<5>

DDR_A_S

DQS4<5>

DDR_A_S

DQS6#<5>

DDR_A_S

DQS6<5>

+2.5V

+3VS

APU_SCL

K0< 7>

DDR_A_P

DDR_A_S

DDR_A_S

DDR_A_S

DDR_A_S

DDR_A_S

DDR_A_S

DDR_A_S

DDR_A_S

DDR_A_S

DDR_A_S

DDR_A_S

DDR_A_S

DDR_A_S

DDR_A_S

DDR_A_S

DDR_A_S

DDR_A_S

DDR_A_S

MA1

AR

DQ37

DQ33

DQ38

DQ34

DQ44

DQ40

DM5

DQ46

DQ42

DQ52

DQ53

DQ55

DQ51

DQ61

DQ56

DM7

DQ62

DQ58

JDIMM1

1

VSS

3

DQ5

5

VSS

7

DQ1

9

VSS

11

DQS0_

13

DQS0_

1

5

VSS

1

7

DQ7

1

9

VSS

1

2

DQ3

2

3

VSS

5

2

DQ1

3

2

7

VSS

9

2

DQ9

3

1

VSS

33

DM1*/

3

5

VSS

7

3

DQ1

5

9

3

VSS

1

4

DQ1

0

4

3

VSS
DQ2145DQ20

47

VSS
DQ1749DQ16

51

VSS
DQS2_C53DM2*/DBI2*
DQS2_T55VSS
VSS57DQ22

59

DQ23
VSS61DQ18

63

DQ19
VSS65DQ28

67

DQ29
VSS69DQ24

71

DQ25
VSS73DQS3_

75

DM3*/

77

VSS
DQ3079DQ31

81

VSS
DQ2683DQ27

85

VSS

87

CB5_N

89

VSS

91

CB1_N

93

VSS

95

DQS8_

97

DQS8_
VSS99CB6_N

101

CB2_N

103

VSS

105

CB3_N

107

VSS

10

9

CKE0

11

1

VDD1

113

BG1

115

BG0

11

7

VDD3

119

A12

121

A9

12

3

VDD5

125

A8

127

A6

12

9

VDD7

131

A3

133

A1

13

5

VDD9

1

37

CK0_T

1

39

CK0_C

1

41

VDD11

143

PARIT

145

BA1

1

47

VDD13

149

S0*

151

A14_W

1

53

VDD15

15

5

ODT0

157

S1*

1

59

VDD17

16

1

ODT1

1

63

VDD19

165

S3*/C

167

VSS

16

9

DQ37

171

VSS

17

3

DQ33

175

VSS

177

DQS4_

179

DQS4_

181

VSS

18

3

DQ38

185

VSS

18

7

DQ34

189

VSS

19

1

DQ44

193

VSS

19

5

DQ40

197

VSS

199

DM5*/

201

VSS

20

3

DQ46

205

VSS

20

7

DQ42

209

VSS

21

1

DQ52

213

VSS

21

5

DQ49

217

VSS

219

DQS6_

221

DQS6_

223

VSS

22

5

DQ55

227

VSS

22

9

DQ51

231

VSS

23

3

DQ61

235

VSS

23

7

DQ56

239

VSS

241

DM7*/

243

VSS

24

5

DQ62

247

VSS

24

9

DQ58

251

VSS

253

SCL

255

VDDSP

25

7

VPP1

25

9

VPP2

REN_40-42271-26001RHF

DE

SP07001CW00

CONN@

DBI1*

DBI3*

Y

1

DBI5*

DBI7*

2

2

VSS

4

DQ4

6

VSS

8

DQ0

1

VSS

12

DM0*/

C

DBI0*

1

VSS

T

1

DQ6

1

VSS

2

DQ2

2

VSS

2

DQ1

2

2

VSS

2

DQ8

3

VSS

32

DQS1_

C

34

DQS1_

T

3

VSS

3

DQ1

4

4

VSS

4

DQ1

1

4

VSS

46
48

VSS

50
52

VSS

54
56
58
60

VSS

62
64

VSS

66
68

VSS

70
72

VSS

74

C

76

DQS3_

T

78

VSS

80
82

VSS

84
86

VSS

88

CB4_N

C

C

90

VSS

92

CB0_N

C

C

94

VSS

96

DM8*/

C

DBI8*

98

VSS

T

100

C

102

VSS

C

104

CB7_N

C

106

VSS

C

108

RESET

*

11

CKE1

11

VDD2

11

ACT*

116

ALERT

*

11

VDD4

120

A11

122

A7

12

VDD6

126

A5

128

A4

13

VDD8

132

A2

134

EVENT

*

1

VDD10

1

CK1_T

1

CK1_C

1

VDD12

144

A0

146

A10_A

P

1

VDD14

150

BA0

152

A16_R

E*

AS*

1

VDD16

156

A15_C

AS*

158

A13

1

VDD18

162

S2*/C

0

164

VREFC

A

166

SA2

168

VSS

17

DQ36

172

VSS

17

DQ32

176

VSS

178

DM4*/

C

DBI4*

180

VSS

T

18

DQ39

184

VSS

18

DQ35

188

VSS

19

DQ45

192

VSS

19

DQ41

196

VSS

198

DQS5_

C

200

DQS5_

T

202

VSS

20

DQ47

206

VSS

20

DQ43

210

VSS

21

DQ53

214

VSS

21

DQ48

218

VSS

220

DM6*/

C

DBI6*

222

VSS

T

22

DQ54

226

VSS

22

DQ50

230

VSS

23

DQ60

234

VSS

23

DQ57

238

VSS

240

DQS7_

C

242

DQS7_

T

244

VSS

24

DQ63

248

VSS

25

DQ59

252

VSS

254

SDA

256

SA0

D

258

VTT

260

SA1

261

GND

262

GND

DR_A_

DQ4

D

S

D

S

DQ0

DR_A_

0

D

S

DM0

DR_A_

4

D

S

DQ6

DR_A_

6
8

D

S

DQ2

DR_A_

0
2

DR_A_

DQ12

D

4
6
8
0

6
8
0
2
4

0
2
4

8

4

0

36
38
40
42

48

54

60

0

4

2

6

0

4

4

8

2

6

4

8

2

6

6

0

S

D

S

DR_A_

D

S

DR_A_

DR_A_

D

S

D

S

DR_A_

DDR_A_SDQ16

DDR_A_SDM2

DDR_A_SDQ22

DDR_A_S

DDR_A_S

DDR_A_S

DDR_A_S

DDR_A_S

DDR_A_RS

DDR_A_A

DDR_A_S
DDR_A_S

DDR_A_S
DDR_A_S

DDR_A_S

DDR_A_S

DDR_A_S

DDR_A_S

SA2_DI

M1

DDR_A_S

DDR_A_S

DDR_A_S

DDR_A_S

DDR_A_S

DDR_A_S

DDR_A_S

DDR_A_S

DDR_A_S

DDR_A_S

DDR_A_S

DDR_A_S

DDR_A_S

DDR_A_S

DDR_A_S

DDR_A_S

DDR_A_S

DDR_A_S

SA0_DI

M1

SA1_DI

M1

DQ8

DQ14

DQ11

DQ20

DQ19

DQ28

DQ25

DQ31

DQ27

LERT#

MA11
MA7

MA5
MA4

MA2

MA0

MA10

MA13

DQ36

DQ32

DM4

DQ39

DQ35

DQ45

DQ41

DQ47

DQ43

DQ49

DQ48

DM6

DQ54

DQ50

DQ60

DQ57

DQ63

DQ59

D

S

DQS1# <5>

DR_A_
DR_A_

DQS1 <5>

D

S

DDR_A_S

DQS3# <5>

DDR_A_S

DQS3 <5>

T#

DDR_A_RS

T# <5>

DDR_A_CK

E1 <5>

DDR_A_S

ACT# <5>

DDR_A_E

VENT# <5>

<5>

DDR_A_CL

K1

DDR_A_CL

K1# <5>

DDR_A_S

BS0# <5>

DDR_A_S

RAS# <5>

CAS# <5>

DQS5# <5>
DQS5 <5>

DQS7# <5>
DQS7 <5>

TA0 <7>

+0.6V

+0.6V

DDR_A_S

DDR_A_S
DDR_A_S

DDR_A_S
DDR_A_S

APU_SDA

+1.2V+1.2V

DDR_A_RS

_DDR_VREFCA

S

1

T#

CD231 10

ESD@

1 2

ESD

0P_0402_50V8J

Secur

Secur

Secur

ity Classification

ity Classification

ity Classification

Issue

Issue

Issue

d Date

d Date

d Date

THIS

THIS

THIS

SHEET OF ENGINEE RING DRAWING IS TH E PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

SHEET OF ENGINEE RING DRAWING IS TH E PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

SHEET OF ENGINEE RING DRAWING IS TH E PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE C OMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHE R THIS SHEET NOR THE INFORM ATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHE R THIS SHEET NOR THE INFORM ATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHE R THIS SHEET NOR THE INFORM ATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS , INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS , INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS , INC.

2018/

2018/

2018/

Compa

Compa

Compa

l Secret Data

l Secret Data

2

l Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

03/12 2019/03/12

03/12 2019/03/12

03/12 2019/03/12

Compa

Compa

Compa

l Electronics, Inc.

l Electronics, Inc.

Title

Title

Title

S

S

S

ize

ize

ize

Document Number Re v

Document Number Re v

Document Number Re v

Date : Sheet

onday, March 12, 2018

Date : Sheet

onday, March 12, 2018

Date : Sheet

onday, March 12, 2018

l Electronics, Inc.

DDR4_DIMM

DDR4_DIMM

DDR4_DIMM

LA-G2

LA-G2

LA-G2

41P

41P

41P

1

10 43M

10 43M

10 43M

1.0

1.0

1.0

of

of

of

1

A A

PCIE_ATX_C_GRX_P0<4>
PCIE_ATX_C_GRX_N0<4>

PCIE_ATX_C_GRX_P1<4>
PCIE

_ATX_C_GRX_N1<4>

PCIE

_ATX_C_GRX_P2<4>

PCIE

_ATX_C_GRX_N2<4>

PCIE

_ATX_C_GRX_P3<4>

PCIE

_ATX_C_GRX_N3<4>

B B

PXS_

PXS_

APU_

RST#

PCIE_RST#

RST#

CLK_

PEG_VGA<8>

CLK_

+3VG

S

UV2

DIS@

5

1

P

IN1

O

2

IN2

G

3

PEG_VGA#<8>

RV2 1K

4

12

RV4
10

0K_0402_5%

DIS@

RV31

C C

53 100K_0402_5%@DIS@

PXS_

APU_

12

RST#<7>

PCIE_RST#<7,20,22>

MC

74VHC1G08DFT2G_SC70-5

1 2

DIS@

PLT_R

CLK_
CLK_

2

PEG_VGA
PEG_VGA#

_0402_1%

ST_VGA#

UV1

IS@

A D

AF30

PCIE_RX0P

AE31

PCIE_RX0N

AE29

PCIE_RX1P

AD28

PCIE

_RX1N

AD30

PCIE

_RX2P

AC31

PCIE

_RX2N

AC29

PCIE

_RX3P

AB28

PCIE

_RX3N

AB30

PCIE

_RX4P

AA31

PCIE

_RX4N

AA29

PCIE

_RX5P

Y28

PCIE

_RX5N

Y30

PCIE

_RX6P

W31

PCIE

_RX6N

W29

PCIE

_RX7P

V28

PCIE

_RX7N

V30

NC#V

30

U31

NC#U

31

U29

NC#U

29

T28

NC#T

28

T30

NC#T

30

R31

NC#R

31

R29

NC#R

29

P28

NC#P

28

P30

NC#P

30

N31

NC#N

31

N29

NC#N

29

M28

NC#M

28

M30

NC#M

30

L31

NC#L

31

L29

NC#L

29

K30

NC#K

30

CLOC

K

AK30

PCIE

_REFCLKP

AK32

PCIE

_REFCLKN

N10

TEST

_PG

AL27

PERS

TB

216-0842024-A11-MAR_FCBGA_631P

3

PCIE_TX0P
PCIE_TX0N

PCIE_TX1P
PCIE

_TX1N

PCIE

_TX2P

PCIE

_TX2N

PCIE

_TX3P

PCIE

_TX3N

PCIE

_TX4P

PCIE

_TX4N

PCIE

_TX5P

PCIE

_TX5N

PCIE

_TX6P

PCIE

_TX6N

PCIE

_TX7P

PCIE

_TX7N

NC#W
NC#W

NC#V

CALIBRATIO N

PCIE

PCIE

NC#U

NC#U
NC#U

NC#T
NC#T

NC#T
NC#T

NC#P
NC#P

NC#P
NC#P

NC#M
NC#N

_CALR_TX

_CALR_RX

PCI

EXPRESS INTERFACE

AG31

AG29
AF28

AF27
AF26

AD27
AD26

AC25
AB25

Y23
Y24

AB27
AB26

Y27
Y26

W24

24

W23

23

V27

27

U26

26

U24

24

U23

23

T26

26

T27

27

T24

24

T23

23

P27

27

P26

26

P24

24

P23

23

M27

27

N26

26

Y22

AA22

PCIE_ARX_C_GTX_N0

PCIE_ARX_C_GTX_P1
PCIE_ARX_C_GTX_N1

PCIE

_ARX_C_GTX_P2

PCIE

_ARX_C_GTX_N2

PCIE

_ARX_C_GTX_P3

PCIE

_ARX_C_GTX_N3

1 2

RV1 1.

DIS@

1 2

RV3 1K

DIS@

PCIE_ARX_C_GTX_P0

AH30

1 2

CV1 0.22U_0402_6.3V6KDIS@

1 2

CV2 0.22U_0402_6.3V6KDIS@

1 2

CV3 0.22U_0402_6.3V6KDIS@

1 2

CV4 0.22U_0402_6.3V6KDIS@

1 2

CV5 0.

1 2

CV6 0.

1 2

CV7 0.

1 2

CV8 0.

+0.9

5VGS

69K_0402_1%

_0402_1%

PCIE_ARX_GTX_P0 <4>
PCIE_ARX_GTX_N0 <4>

PCIE_ARX_GTX_P1 <4>
PCIE

22U_0402_6.3V6KDIS@
22U_0402_6.3V6KDIS@

22U_0402_6.3V6KDIS@
22U_0402_6.3V6KDIS@

PCIE
PCIE

PCIE
PCIE

4

_ARX_GTX_N1 <4>

_ARX_GTX_P2 <4>
_ARX_GTX_N2 <4>

_ARX_GTX_P3 <4>
_ARX_GTX_N3 <4>

U

se GPU Display Port outpud

No

F

@

UV1

DIS

VARY_BL

DIGON

TXCA

P_DPA3P

TXCA

M_DPA3N

TX0P

_DPA2P

TX0M

_DPA2N

TX1P

_DPA1P

TX1M

_DPA1N

TX2P

_DPA0P

TX2M

_DPA0N

NC_T

XOUT_L3P

NC_T

XOUT_L3N

TMDP

TXCB

P_DPB3P

TXCB

M_DPB3N

TX3P

_DPB2P

TX3M

_DPB2N

TX4P

_DPB1P

TX4M

_DPB1N

TX5P

_DPB0P

TX5M

_DPB0N

NC_T

XOUT_U3P

NC_T

XOUT_U3N

2160

856030-A0_FCBGA631

AB11
AB12

AL15
AK14

AH16
AJ15

AL17
AK16

AH18
AJ17

AL19
AK18

AH20
AJ19

AL21
AK20

AH22
AJ21

AL23
AK22

AK24
AJ23

5

+VG

_CORE

A

PLT_R

ST_VGA#<40>

D D

Secu

Secu

Secu

rity Classification

rity Classification

rity Classification

Issu

Issu

Issu

ed Date

ed Date

ed Date

THIS

THIS

THIS

SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2018

2018

2018

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

/03/12 2019/03/12

/03/12 2019/03/12

/03/12 2019/03/12

Deciphered Date

4

Comp

Comp

Comp

al Electronics, Inc.

al Electronics, Inc.

Titl

Titl

Titl

e

e

e

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Cust

Cust

Cust

om

om

om

Date: Sheet

Date: Sheet

Date: Sheet

al Electronics, Inc.

R17-

R17-

R17-

M1-70_PCIE/DP

M1-70_PCIE/DP

M1-70_PCIE/DP

LA-G

LA-G

LA-G

241P

241P

241P

5

of

of

of

11 43Monday, March 12, 2018

11 43Monday, March 12, 2018

11 43Monday, March 12, 2018

1.0

1.0

1.0

1

+3VGS

12

12

DIS@

2

G

6 1

D

@ 12

DIS@

RV6

RV5

47K

QV1

A

@

DIS

S

47K

_0402_5%

_0402_5%

GPU_S

VD

GPU_S

VC

M1-30/M1-70 colay level circuit
M1-30

5

G

B

QV1

DIS

A A

B B

+1.8V

GS

1

+3VGS

RV154 5

RV17 1 K

+3VGS

RV369

+3VGS

RV315

EC_SM

EC_SMB_CK2<6,25>

RV152

0K_0402_5%

1 2

1 2

DIS@

1 8
2 7
3 6
4 5

RPV34

1 1K_0402_5%DIS@

B_DA2<6,25>

@

12

@

@

@ 12

10K_0402_5%

1

1 2

.11K_0402_5%

_0402_5%

JTAG_
JTAG_
JTAG_
JTAG_

10K_8P4R_5%

JTAG_

12

L

GPIO1

RV151
0K_0402_5%

DIS@

TDI_GPU
TMS_GPU
TCK
TRSTB

TDO_GPU

3 4

S

D

N7002SDW1T1G 2N SOT-363

2

9_CTF

TESTE

N

GPU_G

PIO5

RV315

@

2

N7002SDW1T1G 2N SOT-363

L

2 10K_0402_5%

System Power Level Reduction Request

27MHz CRYSTAL

RV20

DIS@

1M

UT_R

YV2
27M

HZ_10PF_XRCGB27M000F2P18R0

1

1

NC

DIS@

@

12

RV901K

_0402_5%

SJ10000UI00

NC

2

@

3

4

PCC_G

2

CV90

0.

1U_0201_10V K X5R

1

XTALI

N

3

12

CV17

15

PIO_6

K_0402_5%

ROCHOT#

XTALO

12

CV18

DIS@

+3VGS

RV91

@

1 2

_0402_1%

1 2

C C

XTALO

GPU_P

Peak

D D

@

UT

RV164

3

0_0402_5%

15

P_0402_50V8J

10

GPU_P

ROCHOT#<40>

Current Control (Reversed)

2

VGA_S

VGA_SMB_CK3

GPU_G

PIO5_VGA#<25>

RV93 0_

1 2

1 2

0402_5%@

0402_5%@

RV94 0_

must implemented count

P_0402_50V8J

DIS@

+1.8V

MB_DA3

@

T222

@

T221

GPU_S

VD_R

GPU_S

VC_R

VGA_C

GS

LV2 0_0

1 2

DIS@

CV19 10

DIS@

CV20 1U

DIS@

CV21 0.

RV21 1 0

FB_VD

DCI

1

PLL_A

nalog_in

1

DV1

1 2

RV195 0

LKREQ#<7>

402_5%@

12

U_0603_6.3V6M

12

_0201_6.3V6M

12

1U_0201_10V6K

1 2

Enabl

e MLPS

RB7

4.

51V_SOD323

@

+VGA_

K_0402_5%@

+1.8VGS

RV81

7K_0402_5%

DIS@

+VGA_

@

21

_0402_5%

GPU_S

GPIO1
GPU_S

CORE

RV29 1 0
RV59 1 0

13mA

1 2

CORE

VD_R

9_CTF

VC_R

DIS@1 2
DIS@1 2

1 2

T20
T20
T20
T20
T20
T20
T20
T20
T20
T21
T21
T21
T21
T21
T21
T216
T217

RV82

4.

7K_0402_5%

DIS@

T223
T224

VGA_S
VGA_S
GPU_G
PCC_G

+VGA_

JTAG_
JTAG_
JTAG_
JTAG_
JTAG_

TESTE

T4935 @

T218 @

XTALI
XTALO

GPIO2
+TSVD

@

1

@

2

@

3

@

4

@

5

@

6

@

7

@

8

@

9

@

0

@

1

@

2

@

3

@

4

@

5

@
@

@
@

MB_DA3
MB_CK3

PIO5

PIO_6

CORE

TRSTB
TDI_GPU
TCK
TMS_GPU
TDO_GPU

N

N

UT

K_0402_5%
K_0402_5%

8
D

3

tor Divider Lookup Lable

B

@

UV1

DIS

AF2

NC#AF

2

AF4

4

1

N9

DBG_D

ATA16

1

L9

DBG_D

ATA15

1

AE9

DBG_D

ATA14

1

Y11

DBG_D

ATA13

1

AE8

DBG_D

ATA12

AD9

1

ATA11

DBG_D

1

AC10

DBG_D

ATA10

1

AD7

DBG_D

ATA9

AC8

1
1

AC7
1
1
1
1
1
1
1

AC6

AC5

BP_0

BP_1

1
1

W10

AK10
AM10

AF24

AB13

AD10

1

AC

PX_EN

A

1

AC16

AM28
AK28

A
AB22

A
A

DBG_D
DBG_D

AB9

DBG_D

AB8

DBG_D

AB7

DBG_D

AB4

DBG_D

AB2

DBG_D

Y8

DBG_DATA1

Y7

DBG_DATA0

W6

NC#W6

V

6

NC#V6

NC#AC
NC#AC

AA5

NC#AA

AA6

NC#AA

U

1

NC#U1

W

1

NC#W1

U

3

NC#U3

Y

6

NC#Y6

AA1

NC#AA

R1

SCL

R3

SDA

GENERAL PURPOSE I/O

U6

GPIO_

U10

GPIO_

T10

GPIO_

U8

SMBDA

U7

SMBCL

T9

GPIO_

T8

GPIO_

T7

GPIO_

P10

GPIO_

P4

GPIO_

P2

GPIO_

N6

GPIO_

N5

GPIO_

N3

GPIO_

Y9

GPIO_

N1

GPIO_

M4

GPIO_

R6

GPIO_
GPIO_

M2

GPIO_

P8

GPIO_

P7

GPIO_

N8

GPIO_
GPIO_
GPIO_

N7

CLKRE

L6

JTAG_

L5

JTAG_

L3

JTAG_

L1

JTAG_

K4

JTAG_

K7

TESTE
NC#AF

GENER

W8

GENER

W9

GENER

W7

GENER
GENER

AJ9

NC#AJ

AL9

NC#AL

14

HPD1

B16

PX_EN

DBG_V

XTALI
XTALO

C22

XO_IN
XO_IN

T

4

DPLUS

T2

DMINU

R5

GPIO2

D17

TSVDD

C17

TSVSS

ATA8
ATA7
ATA6
ATA5
ATA4
ATA3
ATA2

5
6

5
6

1

I2C

0
1
2

TA

K
5_AC_BATT
6
7_BLON
8_ROMSO
9_ROMSI
10_ROMSCK
11
12
13
14_HPD2
15_PWRCNTL_0
16
17_THERMAL_INT
18
19_CTF
20_PWRCNTL_1
21
22_ROMCSB
29
30

QB

TRSTB
TDI
TCK
TMS
TDO
N
24

ICA

ICB

ICC

ICD

ICE
9
9

REFG

PLL/CLOCK

N

UT

2

SEYMOUR/FutureASIC

THERM

S

8_FDO

21608

56030-A0_FCBGA631

D

VO

AL

DPA

DPB

DPC

AVSSN

AVSSN

AVSSN

DAC1

Fut

ureASIC/SEYMOUR /PARK

GENLK

GENLK

SWAPL
SWAPL

DD

C/AUX

DDCVG

DDCVG

RSVD#
RSVD#
RSVD#

DDC1D

DDC2D

DDC1C

DDC2C

NC#AD
NC#AC

NC#AE

NC#AD

NC#AF

NC#AG
NC#AG

NC#AH
NC#AH

NC#AK
NC#AK

NC#AK
NC#AM

NC#AK
NC#AM

NC#AJ7

NC#AH6

NC#AK8

NC#AL7

NC#V4
NC#U5

NC#W3
NC#V2

NC#Y4
NC#W5

NC#AA

NC#Y2

#AG25

HSYNC
VSYNC

AVSSQ

VDD1D

VSS1D

CEC_1

_VSYNC

AUX1P
AUX1N

AUX2P
AUX2N

ADATA

NC#J8

#AK26

#AJ25

RSET

AVDD

OCKA
OCKB

AG3

3

AG5

5

AH3

3

AH1

1

AK3

3

AK1

1

AK5

5

AM3

3

AK6

6

AM5

5

AJ7
AH6

AK8
AL7

V

4

U

5

W

3

V

2

Y

4

W

5

PLL_A

AA3

3

Y

2

J

8

AM26

R

AK26

AL25

G

AJ25

AH24

B

AG25

A

H26

A

J27

AD

22

AG

24

A

E22

AE23

I

AD23

I

A

M12

AK12

AK12

AL11

AL11

AJ11

AJ11

AL13

_CLK

AJ13

AG13
AH12

AC

19

PS_0

AD

19

PS_1

AE

17

PS_2

AE

20

PS_3

AE

19

TS_A

AE6

LK

AE5

ATA

A

D2

A

D4

AC11

LK

AC13

ATA

A

D13

A

D11

AD20

20

AC20

20

AE16

16

AD16

16

AC1

ACLK

AC3

Resis

0402 1% resistors are equired

N

C

8.45k

4.53k

6.98k

4.53k

3.24k

3.4k

4.75k

Capacitor Divider Lookup Lable

Cap (nF) Bitd [5:4]

680nF

82nF

10

nF 1 0

NC

nalog_out

12

RV83
16

.2K_0402_1%

@

The resistor is not

+3VGS

12

RV162
4

.7K_0402_5%

@

WAKEB

12

RV163
4

.7K_0402_5%

DIS@

RV155 0

1 2
1 2
1 2

+VGA_

NSE_VGA

NSE_VGA

_0402_5%@
_0402_5%@
_0402_5%@

CORE

RV156 0
RV157 0

PS_0

PS_1

PS_2

PS_3

VSSSE
VCCSE

Boot-VID Code

SVC

0
0
1
1

VSSSE
VCCSE

GPU_S
GPU_S
GPU_S

NSE_VGA <40>

4

R_pd (ohm)R_pu (ohm)

Bitd [3:1]

4.75k

000

2k

001

2k

010

4.99k

011

4.99k

100

5.6

2k

101

10k

110

N

C

111

00

01

11

needed on production.

VD

GPU_S
GPU_S
GPU_S

Voltage
Selected (V)

0
1 1.0
0
1 0.8

1.1

0.9

VD <40>
VT <40>
VC <40>

VT
VC

NSE_VGA <40 >

SVD

PS_0[5:4]=11

chang

PS_1[3:1]=001

PS_1[5:4]=11

PS_2[3:1]=000

PS_2[5:4]=11

PS_3[3:1]=000

PS_3[5:4]=11

GPU_S
GPU_S

PS_

PS_1

PS_2

CV11

PS_3

10

10

12

RV8

8.4

0

CV2

e to support gen3 11/24

CV28

@

CV15

K_0402_5%

VD
VC

K_0402_5%

DIS

12

1

RV9

9

2K_

@

2

DIS

_0402_10V

0.68U

+1.8VGS

12

DIS@

RV11

8.45K_0402_1%

12

1

DIS@

RV12

@

2K

_0402_1%

2

_0402_10V

0.68U

+1.8V

GS

12

@

RV28

8.

45K_0402_1%

12

1

RV13

4.

75K_0402_1%

2

DIS@

U_0402_16V

0.082

+1.8V

GS

12

X76@

RV15

8.

45K_0402_1%

12

1

X76@

RV16

4.

@

75K_0402_1%

2

SD034475180

_0402_10V

0.68U

+1.8V

GS

RV84

RV87
10

K_0402_5%

@

DIS@

1 2

1 2

RV89

RV88
10

K_0402_5%

DIS@

@

1 2

1 2

GS

+1.8V

3:1]=001

PS_0[

5K_0402_1%

@

0402_1%

@

5

Name :

Strap

PS_0[1] ROM_CONFIG[0]

PS_0[2] ROM_CONFIG[1]

PS_0[3] ROM_CONFIG[2]

PS_0[

4] N/A

PS_0[5] AUD_PO RT_CONN_PINSTRAP[0]

Strap Name :

PS_1[1] STRAP_BIF_ GEN3_EN_A

PS_1[2] TRAP_BIF_CLK_PM_EN

PS_1[3] N/A

PS_1[4] STRAP_TX_CFG_DRV_FULL_SWING

PS_1[

5] STRAP_TX_DEE MPH_EN

Strap

Name :

PS_2[

1] N/A

PS_2[2] N/A

PS_2[

3] STRAP_BIOS_ROM_EN

PS_2[

4] STRAP_BIF_VGA_DIS

PS_2[5] N/A

Strap Name :

PS_3[1] BOARD_CONFIG[0] (Memory ID )

PS_3[

2] BOARD_CONFIG[1] (Memory ID )

PS_3[

3] BOARD_CONFIG[2] (Memory ID )

PS_3[4] AUD_PO RT_CONN_PINSTRAP[1]

PS_3[

5] AUD_PO RT_CONN_PINSTRAP[2]

ZZZ

ZZZ

X7677538L52

X7677538L53

H2G

M2G

@

@

VRAM Type
Need reference

X76 Schemat i c

ZZZ

X7677538L51

S2G

@

Secur

Secur

Secur

ity Classification

ity Classification

ity Classification

Issued Date

Issued Date

Issued Date

THIS

THIS

THIS

SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

2

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2018/

2018/

2018/

Compa

Compa

Compa

l Secret Data

l Secret Data

l Secret Data

Deciphered Date

Deciphered Date

03/12 2019/03/12

03/12 2019/03/12

03/12 2019/03/12

Deciphered Date

4

Compa

Compa

Compa

l Electronics, Inc.

l Electronics, Inc.

Title

Title

Title

S

S

S

ize Document Number Re v

ize Document Number Re v

ize Document Number Re v

Custo

Custo

Custo

m

m

m

Date: Sheet

Date: Sheet

Date: Sheet

l Electronics, Inc.

R17-M1-70_M

R17-M1-70_M

R17-M1-70_M

LA-G241P

LA-G241P

LA-G241P

5

SIC

SIC

SIC

12 43Friday, March 16, 2018

12 43Friday, March 16, 2018

12 43Friday, March 16, 2018

of

of

of

1.0

1.0

1.0

5

1.8VALW TO +1.8VGS

+
+0.95VALW TO +0.95VGS

Load switch

D D

+0.

5VALW

9

CV29

1U_0201_6.3V6M

12

1

@

U1895V

1

VOUT

VIN1

2

VOUT

DGPU

_PWR_EN

C C

DIS@

150K_0402_5%

RV16

42

DGPU

12

_PWR_EN_R

0.1U_0201_10V K X5R

1

CV1380

DIS@

2

+VL

+1.8

VALW

CV30

1U_0201_6.3V6M

12

1

@

VIN1

3

ON1

4

VBIA

5

ON2

6

VIN2

7

VIN2

EM52

SA0000BKC00

DIS@

S

VOUT
VOUT

GPAD

09VF_DFN14_3X2

+3VALW to +3VGS

DGPU

_PWR_EN#

2

G

+3VA

13

B B

+5VA

LW

RV44

DIS@

2

0K_0402_5%

1 2

DGPU

_PWR_EN<7,25,40,41>

DIS@

RV16

44 10_0402_5%

LW

DIS@

1 2

RV43

D

DIS@

QV18
2

N7002KW_SOT323-3

S

QV16
P

J2301_SOT23-3

S

G

2

3.4K_0402_1%

DIS@

3VGS

_EN#

CT1

GND

CT2

1
1

2
2

D

13

14
13

12

11

10

9
8

1

5

1

DIS@

CV83
0

.1U_0201_10V7K

2

+3VG

DIS@

4

+0.9

5VGS

VGS

DIS@

CV31
0

.1U_0201_10V7K

2

G

QV17
2

N7002KW_SOT323-3

DIS@

CV32
0

.1U_0201_10V7K

1 2

DGPU

_PWR_EN#

1 2

@

CV28

12200P_0402_50V7K

1 2

@

S

CV36

1

4

U_0201_6.3V6M

.7U_0402_6.3V6M

1

12

@

2

CV27

+1.8

12200P_0402_50V7K

1 2

CV37

12

RV42

@

6

80_0603_5%

@

13

D

S

3

8

VGS

+1.

+0.9

5VGS

DGPU

CV261

12

U_0201_6.3V6M

CV301

@

0U_0603_6.3V6M

_PWR_EN#

@

1

CV331

@

2

U_0201_6.3V6M

+

DP_VDD R

1

CV271

@

2

0U_0603_6.3V6M

+DP_VDD C

280mA

12

AG15
AG16
AF16
AG17
AG18
AG19
AF14

AG20
AG21
AF22
AG22
AD14

AG14

AH14
AM14
AM16
AM18

AF23

AG23
AM20
AM22
AM24

AF19

AF20

AE14

AF17

+VGA

_CORE

RV45
4

DIS@

1 2

13

D

2

G

S

2

No

se GPU Display Port outpud

U

UV1

DIS

G

@

DP POWER

V

DDR#AG15

DP_
DP_VDDR#AG16
DP_VDDR#AF16
DP_VDDR#AG17
DP_VDDR#AG18
DP_VDDR#AG19
DP_VDDR#AF14

DP_V

DDC#AG20

DP_V

DDC#AG21

DP_V

DDC#AF22

DP_V

DDC#AG22

DP_V

DDC#AD14

DP_V

SSR

DP_V

SSR

DP_V

SSR

DP_V

SSR

DP_V

SSR

DP_V

SSR

DP_V

SSR

DP_V

SSR

DP_V

SSR

DP_V

SSR

DP_V

SSR

DP_V

SSR

DP_V

SSR

DPAB

_CALR

2160

856030-A0_FCBGA631

70_0603_5%

DIS@

QV11
2

N7002KW_SOT323-3

NC/

D

P POWER

A

NC#

NC#AF11

NC#AE13

NC#AF13

NC#AG8

NC#AG10

NC#A
NC#A
NC#A
NC#A

NC#A
NC#A
NC#A
NC#A
NC#A

NC#A

NC#A
NC#A
NC#A
NC#A
NC#A

NC#A

NC#A

+1.8

D

AE11

E11

AF11
AE13
AF13
AG8
AG10

AF6

F6

AF7

F7

AF8

F8

AF9

F9

AE1

E1

AE3

E3

AG1

G1

AG6

G6

AH5

H5

AF10

F10

AG9

G9

AH8

H8

AM6

M6

AM8

M8

AG7

G7

AG11

G11

AE10

E10

VGS

RV57
4

70_0603_5%

@

1 2

61

DGPU

2

G

S

QV21

A

@

L2N7002DW1T1G 2N SOT-363

_PWR_EN#

A
A
A
A
A
A
A
A
A
A
AG27
AH32

W2
W2
W2

AA

UV1

27

A

GND

24

B

GND

B

32

GND

C

24

GND

26

C

GND

27

C

GND

25

D

GND

32

D

GND

27

E

GND

F

32

GND
GND
GND

K28

GND

K32

GND

L27

GND

M32

GND

N2

5

GND

N2

7

GND

P2

5

GND

P3

2

GND

R2

7

GND

T2

5

GND

T3

2

GND

U2

5

GND

U2

7

GND

V3

2

GND

5

GND

6

GND

7

GND

Y2

5

GND

Y3

2

GND

M6

GND

N1

3

GND

N1

6

GND

N1

8

GND

N2

1

GND

P6

GND

P9

GND

R1

2

GND

R1

5

GND

R1

7

GND

R2

0

GND

T1

3

GND

T1

6

GND

T1

8

GND

T2

1

GND

T6

GND

U1

5

GND

U1

7

GND

U2

0

GND

U9

GND

V1

3

GND

V1

6

GND

V1

8

GND

Y1

0

GND

Y1

5

GND

Y1

7

GND

Y2

0

GND

R1

1

GND

T1

1

GND

11

GND

M1

2

GND

N1

1

GND

V1

1

GND

2160

+0.9

DIS

E

@

GND

856030-A0_FCBGA631

5VGS

RV56
4

70_0603_5%

@

1 2

34

D

DGPU

5

G

S

QV21

B

@

L2N7002DW1T1G 2N SOT-363

1

VSS_
VSS_
VSS_

_PWR_EN#

MECH
MECH
MECH

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

A
A
A
A
A
A
A
A
A
A
AE7
AG12
AH10
AH28
B10
B12
B1
B1
B1
B2
B2
B2
B2
B6
B8
C1
C3
E2
F1
F1
F1
F1
F1
F2
F2
F2
F2
F2
F6
F8
G1
G2
G3
G8
H1
H1
H2
H2
H6
J2
J3
K1
K2
K2
K6

A32
AM1
AM32

3

0

3
A

13

A

16
10

B

15

B

6

B

9

C

6

D
D

8

4
6
8
0
2
4
6

2
8
0
2
4
6
8

0
2
4
6

0
7
1

4
7

0

7
1
1

2

A A

Secu

Secu

Secu

rity Classification

rity Classification

rity Classification

Issu

Issu

Issu

ed Date

ed Date

ed Date

THIS

THIS

THIS

SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2018

2018

2018

/03/12 2019/03/12

/03/12 2019/03/12

/03/12 2019/03/12

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal E

Compal E

Titl

Titl

Titl

e

e

e

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Cust

Cust

Cust

Date: Sheet

Date: Sheet

Date: Sheet

Compal E

om

om

om

R17-M1-

R17-M1-

R17-M1-

LA-G

LA-G

LA-G

lectronics, Inc.

lectronics, Inc.

lectronics, Inc.

70_PWR

70_PWR

70_PWR

241P

241P

241P

1

o f

o f

o f

13 43Monday, March 12, 2018

13 43Monday, March 12, 2018

13 43Monday, March 12, 2018

1.0

1.0

1.0