LCFC CG516 schematics

A

1 1

B

C

D

E

LCFC Confidential

G Project M/B Schematics Document

2 2

AMD FP4 Bristol Ridge and Stoney Ridge SOC with DDRVI

AMD R16M-M1-30

2015-06-06

REV:1.0

3 3

4 4

Titl e

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

A

B

2013/08/15

C

LC Future Center Secret Data

Deciphered Date

2013/08/15

D

Titl e

Cover Page

Size

Document Number Rev

Custom

Date: Sheet

Tuesday, April 12, 2016

CG516

E

1 51

1.0

of

LCFC

File

A

confidential

Name

Toronto

:

B

C

I

0

E

R

16

Package

.

Conn

eDP

Int

.

r

““

Int

.

^

Conexant

M-M

:

256

*

4

2

DP

VGA

-

ITE

IT

Camera

USB

MIC

Conn

Codec

CXI

~

23

16

GB

6516

2.0

1802

AMD

3

S

1

VRAM

DDR3L

Conn

HDMl

CRT

Conn

.

2

3

VGA

Conn

RJ

45

30

1

-

mmX

BFN

Port

3

.

SATA

LAN

RTL

mm

33

“

18 23

8111

Z

W

mm

HDD

ODD

Realtek

GUL

SATA

PCIe

4

Port

SPK

x

PortO

Portl

Gen

PCI

PEG

2

Conn

3

/

8

HDMl

DP

eDP

USB

SATA

PCIe

HD

x

0-3

.

Express

-

GenJfBristol

PEG

/

4

Lane

x

Lane

Purt

x

2

x

Lane

2

lx

2.0

Gen

3

Genl

lx

Audio

Port

0

~

portO

ridgem

7

/

2

TPM

reserve

b

Bristol

Stoney

m

AMD

Ridge Ridge

(

Integrated

3

7

nil

FP

BGA

mm

LPC

*

968

-

2

4

9

APU

TDP

FCH

mm

dllii

(

V

3.0

2.0

BUS

Channel

DDR

lx lx

lx

4

15

W W

Memory

Single

1.2

USB USB

USB

)

lx

2.0

USB

2.0

lx

USB

3.0

USB

2.0

lx

2.0

USB PCle

lx

SPI

BUS

DDR

B

1866

MT

USB

r

USB

Cardreader

RTS

NGFF

WLAN

Key

SPI

8

4

)

^

/

S

Left

2.0

3.0

V

I

11

•

:

Wh

USB

i

USB

UsBYoPonl

I

5170

Card

&

BT

E

ROM

MB

DDR

Li

Port

5

Portl

m

Right

2.0

Right

USB

-

GRT

USB

PCIe USB

2.0

4

-SO-

UP

"

!

:

JUSBl

T

H

1

PorTo

2.0

Realtek

2.0

Portl

Port

2

I

DB

Port

TO

Ji

J

j

board

4

DIMM

G

x

8

^

XI

1

LH

USB

:

USB

|

I

reserved

Sub

USB

TP

Sub

.

-

board

BOARD

board

-

SD/MMCConn

r

USB

USf

USB

DDR

Right

PortO

0

.

2

Right

lOPdn

2

Port

3.0

USB

for

4

DRAM

pcs

4

iJ

6

\

2

I

3.0

14

15

!

x

board

6

DOWN

for

Z

'

1

2

-

«

3

EC

IT

8886

HE

-

AXLQFP

128

USB

BOARD

&

Mic

HP

4

A

Combo

B

Conn

.

Touch

Pad

Int

.

KB

Security

Issued

THIS

SHEETOFENGINEERING

AND

TRADE

DEPARTMENT

BE

MAY

D

Classification

Date

SECRET

EXCEPT

BY

USED

OR

c

Thermal

DRAWING

INFORMATION

AS

AUTHORIZED

DISCLOSED

NCT

THIS

.

ANY

TO

BY

IS

SHEET

THIRD

Sensor

7718

reserve

2013/08

PROPRIETARY

THE

MAY

FUTURE

LC

PARTY

W

/

15

NOT

CENTER

WITHOUT

PROPERTY

TRANSFERED

BE

LC

NEITHER

PRIOR

Thermistor

Future

Deciphered

FUTURE

LC

OF

FROM

THE

THIS

SHEET

WRITTEN

CONSENT

Center

CUSTODY

NOR

CENTER

THE

OF

Secret

Data

Date

CONTAINS

AND

.

OF

COMPETENT

THE

INFORMATIONITCONTAINS

FUTURE

LC

CENTER

D

2013/08/15

CONFIDENTIAL

DIVISION

.

OF

R&D

Size

Date

Title

Cust

TP

ODD

Block

Document

m

>

:

BOARD

Diagram

Number

Tuesday

April

2016

12

.

TSheet

E

of

51

2

A

Voltage Rails

power

1 1

plane

State

( O --> Means ON , X --> Means OFF )

B+ (+20VSB)

+3VL

+5VLP

+5VALW +3VALW

(+3VALW_APU) +1.8VALW

+0.775VALW +APU_GFX

+1.2V (+VSYSMEM_APU)

+5VS +3VS +1.8VS +1.5VS +0.95VS +0.6VS +2.5VS

+APU_CORE +APU_CORE_NB+0.95VALW

+VGA_CORE +3VGS +1.8VGS +1.35VGS +0.95VGS

B

SIGNAL

STATE

S0 (Full ON)

S1 (Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

DRAM Config.

SLP_S3# SLP_S5# +VALW +V +VS Clock

HIGH HIGH

LOW

LOW LOW

BOARD_ID0 APIO8

0: 14'' 1: 15'' 1: UMA

C

HIGHHIGH

HIGHLOW

LOW

BOARD_ID1 AGPIO10

0: Dis

ON

BOARD_ID2 AGPIO16 internal pull up 40K

0: No KBL 0: KBL

ONONON ON

ON

OFF

LOW

OFF

D

E

BOM Structure Table

BTO ItemBOM Structure

S0

S3

S5 S4/AC

2 2

S5 S4/ Battery only

S5 S4/AC & Battery don't exist

O

X

O

X

O

XX

X

XXX

OO

X

USB Port Table

USB 3.0USB 2.0 Port

EHCI0

0 1

xHCI 2

3

ST Port device

0

RIGHT USB (2.0)

1

RIGHT USB (2.0)

2

Blue Tooth

3

Camera

4

Card Reader USB 2.0 bus

5

LEFT USB (3.0)

6

N/A

7

N/A

BR Port device

RIGHT USB (2.0)

N/A

Blue Tooth Camera Card Reader USB 2.0bus LEFT USB (3.0)

RIGHT USB (3.0)

N/A

@

ME@ 14@ 15@

EMC@

EMC_NS@

EMC_14@

EMC_15@

RF@

RF_PXNS@

UMA@

PX@

EXO@

SMBUS Control Table

SOURCE

EC_SMB_CK0 EC_SMB_DA0

3 3

EC_SMB_CK1 EC_SMB_DA1

EC_SMB_CK2 EC_SMB_DA2

EC_SMB_CK3 EC_SMB_DA3

IT886H

+3VL

IT886H

+3VL

IT886H

+3VS

IT886H

+3VALW

GPU BATT SODIMM WLAN Thermal

XX XX VV

V

+3VS_VGA

XV

X

Sensor

X

XX

VV XXXX

1.8VS

X VXXX XX

APUIT8586E

Charger

Vcore VR

GFxcore VRPMIC

PCIE PORT LIST

Port Device

0

X

XX

VX

X

+3VALW

GPP

X

GFX

X

XX

N/A

1

WLAN

2

LAN

3

N/A

0 1

ST

2

GPU

3 4 5

N/A

6

BR GPU

TOPAZ@

TPM@

KBL@

HDT@

BR@

ST@

BRPX@

Not stuff Connector For 14" part For 15" part EMC Part EMC reserve Part EMC 14 part EMC 15 part RF Part RF GPU reserve part UMA SKU ID part Discrete GPU SKU part EXO GPU Part TOPAZ GPU Part TPM part keyboard backlight part HDT Debug part Bristol Ridge Part Stoney Ridge part Bristol Ridge Discrete Part

7

APU_SCLK0 APU_SDATA0

EC SM Bus0 address

Device

4 4

PMIC

GFxcore VR

APU SM Bus address

Device

DDR4 SO-DIMM

WLAN

APU

+3VS

Addr ess

?

Addr ess

?

RSVD

VVXXX X X

EC SM Bus1 address

Device

Battery

Charger

A

Addr ess

0X16

0001 0010 b

EC SM Bus2 address

Device

Thermal Sensor

GPU

APU SB-TSI

B

Addr ess

1001_100xb(reserve)

0x41(default)

releate to F3x1E4[SbiAddr] or Address Sele ct Pins setting

XXX

EC SM Bus3 address

Device

Vcore VR

Addr ess

?

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

C

2013/08/15

VRAM

LC Future Center Secret Data

Deciphered Date

D

S4GX4@

M4GX4@

H4GX4@

S2G@

M2G@

H2G@

HDMI@

2013/08/15

X76 SAMSUNG 2G X76 MICRON 2G X76 HYNIX 2G SAMSUNG 2G MICRON 2G HYNIX 2G

HDMI Logo

Title

Notes List

Size

Document Number Rev

Custom

Tuesday, April 12, 2016

Date: Sheet

CG516

E

351

1.0

of

5

D D

WLAN LAN

+0.95VS

PCIE_PRX_DTX_P131 PCIE_PRX_DTX_N131

PCIE_PRX_DTX_P228 PCIE_PRX_DTX_N228

RC1 196_0402_1%

1 2

PCIE_PRX_DTX_P1 PCIE_PRX_DTX_N1

PCIE_PRX_DTX_P2 PCIE_PRX_DTX_N2

P_TX_ZVDD

4

UC2B

PCIE

U10

U9 T6

T5 T9

T8 P7

P6 U7

P_GPP_RXP0 P_GPP_RXN0

P_GPP_RXP1 P_GPP_RXN1

P_GPP_RXP2 P_GPP_RXN2

P_GPP_RXP3 P_GPP_RXN3

P_ZVDDP

P_GPP_TXP0 P_GPP_TXN0

P_GPP_TXP1 P_GPP_TXN1

P_GPP_TXP2 P_GPP_TXN2

P_GPP_TXP3 P_GPP_TXN3

P_ZVSS/P_RX_ZVDDP

3

R1 R2

R4 R3

N1 N2

N4 N3

U6

PCIE_PTX_DRX_P1 PCIE_PTX_DRX_N1

PCIE_PTX_DRX_P2 PCIE_PTX_DRX_N2

P_RX_ZVDD

1 2 1 2

1 2

2

CC10.1U_0201_6.3V6-K CC20.1U_0201_6.3V6-K

CC30.1U_0201_6.3V6-K CC40.1U_0201_6.3V6-K

RC3196_0402_1%

PCIE_PTX_C_DRX_P1 PCIE_PTX_C_DRX_N1

PCIE_PTX_C_DRX_P2 PCIE_PTX_C_DRX_N2

PCIE_PTX_C_DRX_P1 31 PCIE_PTX_C_DRX_N1 31

PCIE_PTX_C_DRX_P2 28 PCIE_PTX_C_DRX_N2 28

1

WLAN LAN

PCIE_CRX_GTX_P015

C C

B B

A A

PCIE_CRX_GTX_N015 PCIE_CRX_GTX_P115

PCIE_CRX_GTX_N115 PCIE_CRX_GTX_P215

PCIE_CRX_GTX_N215 PCIE_CRX_GTX_P315

PCIE_CRX_GTX_N315 PCIE_CRX_GTX_P415

PCIE_CRX_GTX_N415 PCIE_CRX_GTX_P515

PCIE_CRX_GTX_N515 PCIE_CRX_GTX_P615

PCIE_CRX_GTX_N615 PCIE_CRX_GTX_P715

PCIE_CRX_GTX_N715

5

PCIE_CRX_GTX_P0 PCIE_CRX_GTX_N0

PCIE_CRX_GTX_P1 PCIE_CRX_GTX_N1

PCIE_CRX_GTX_P2 PCIE_CRX_GTX_N2

PCIE_CRX_GTX_P3 PCIE_CRX_GTX_N3

PCIE_CRX_GTX_P4 PCIE_CRX_GTX_N4

PCIE_CRX_GTX_P5 PCIE_CRX_GTX_N5

PCIE_CRX_GTX_P6 PCIE_CRX_GTX_N6

PCIE_CRX_GTX_P7 PCIE_CRX_GTX_N7

P10

P_GFX_RXP0

P9

P_GFX_RXN0

N6

P_GFX_RXP1

N5

P_GFX_RXN1

N9

P_GFX_RXP2

N8

P_GFX_RXN2

L7

P_GFX_RXP3

L6

P_GFX_RXN3

L10

P_GFX_RXP4

L9

P_GFX_RXN4

K6

P_GFX_RXP5

K5

P_GFX_RXN5

K9

P_GFX_RXP6

K8

P_GFX_RXN6

J7

P_GFX_RXP7

J6

P_GFX_RXN7

@

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

FP4 REV 0.93

Issued Date

P_GFX_TXP0 P_GFX_TXN0

P_GFX_TXP1 P_GFX_TXN1

P_GFX_TXP2 P_GFX_TXN2

P_GFX_TXP3 P_GFX_TXN3

P_GFX_TXP4 P_GFX_TXN4

P_GFX_TXP5 P_GFX_TXN5

P_GFX_TXP6 P_GFX_TXN6

P_GFX_TXP7 P_GFX_TXN7

AMD-CARRIZO_FP4-BGA968

M2 M1

L1 L2

L4 L3

J1 J2

J4 J3

H2 H1

G1 G2

G4 G3

2013/08/15

PCIE_CTX_GRX_P0 PCIE_CTX_GRX_N0

PCIE_CTX_GRX_P1 PCIE_CTX_GRX_N1

PCIE_CTX_GRX_P2 PCIE_CTX_GRX_N2

PCIE_CTX_GRX_P3 PCIE_CTX_GRX_N3

PCIE_CTX_GRX_P4 PCIE_CTX_GRX_N4

PCIE_CTX_GRX_P5 PCIE_CTX_GRX_N5

PCIE_CTX_GRX_P6 PCIE_CTX_GRX_N6

PCIE_CTX_GRX_P7 PCIE_CTX_GRX_N7

Stoney Ridge not support GFX4-GFX7

LC Future Center Secret Data

Deciphered Date

3

1 2 1 2

CC50.22U_0201_6.3V6-K PX@ CC60.22U_0201_6.3V6-K PX@

CC70.22U_0201_6.3V6-K PX@ CC80.22U_0201_6.3V6-K PX@

CC90.22U_0201_6.3V6-K PX@ CC100.22U_0201_6.3V6-K PX@

CC110.22U_0201_6.3V6-K PX@ CC120.22U_0201_6.3V6-K PX@

CC180.22U_0201_6.3V6-K BRPX@ CC300.22U_0201_6.3V6-K BRPX@

CC310.22U_0201_6.3V6-K BRPX@ CC330.22U_0201_6.3V6-K BRPX@

CC320.22U_0201_6.3V6-K BRPX@ CC340.22U_0201_6.3V6-K BRPX@

CC350.22U_0201_6.3V6-K BRPX@ CC360.22U_0201_6.3V6-K BRPX@

2013/08/15

PCIE_CTX_C_GRX_P0 PCIE_CTX_C_GRX_N0

PCIE_CTX_C_GRX_P1 PCIE_CTX_C_GRX_N1

PCIE_CTX_C_GRX_P2 PCIE_CTX_C_GRX_N2

PCIE_CTX_C_GRX_P3 PCIE_CTX_C_GRX_N3

PCIE_CTX_C_GRX_P4 PCIE_CTX_C_GRX_N4

PCIE_CTX_C_GRX_P5 PCIE_CTX_C_GRX_N5

PCIE_CTX_C_GRX_P6 PCIE_CTX_C_GRX_N6

PCIE_CTX_C_GRX_P7 PCIE_CTX_C_GRX_N7

2

PCIE_CTX_C_GRX_P0 15 PCIE_CTX_C_GRX_N0 15

PCIE_CTX_C_GRX_P1 15 PCIE_CTX_C_GRX_N1 15

PCIE_CTX_C_GRX_P2 15 PCIE_CTX_C_GRX_N2 15

PCIE_CTX_C_GRX_P3 15 PCIE_CTX_C_GRX_N3 15

PCIE_CTX_C_GRX_P4 15 PCIE_CTX_C_GRX_N4 15

PCIE_CTX_C_GRX_P5 15 PCIE_CTX_C_GRX_N5 15

PCIE_CTX_C_GRX_P6 15 PCIE_CTX_C_GRX_N6 15

PCIE_CTX_C_GRX_P7 15 PCIE_CTX_C_GRX_N7 15

Title

FP4 (PCIE I/F)

Size

Document Number Rev

Custom

Tuesday, April 12, 2016

Date: Sheet

Tuesday, April 12, 2016

CG516

1

GPUGPU

4 51

1.0

of

5

Stoney Ridge not support ChannelA

4

3

DDRB_DQS[0..7]12,13 DDRB_DQS#[0..7]12,13

2

DDRB_DQS[0..7] DDRB_DQS#[0..7]

1

UC2A

CC14

@

MEMORY A

MA_ZVDDIO_MEM_S

FP4 REV 0.93

AMD-CARRIZO_FP4-BGA968

+MEM_VREF

1

CC15

2

@

0.1U_0201_6.3V6-K

1000P_0201_50V7-K

MA_DATA0 MA_DATA1 MA_DATA2 MA_DATA3 MA_DATA4 MA_DATA5 MA_DATA6 MA_DATA7

MA_DATA8

MA_DATA9 MA_DATA10 MA_DATA11 MA_DATA12 MA_DATA13 MA_DATA14 MA_DATA15

MA_DATA16 MA_DATA17 MA_DATA18 MA_DATA19 MA_DATA20 MA_DATA21 MA_DATA22 MA_DATA23

MA_DATA24 MA_DATA25 MA_DATA26 MA_DATA27 MA_DATA28 MA_DATA29 MA_DATA30 MA_DATA31

MA_DATA32 MA_DATA33 MA_DATA34 MA_DATA35 MA_DATA36 MA_DATA37 MA_DATA38 MA_DATA39

MA_DATA40 MA_DATA41 MA_DATA42 MA_DATA43 MA_DATA44 MA_DATA45 MA_DATA46 MA_DATA47

MA_DATA48 MA_DATA49 MA_DATA50 MA_DATA51 MA_DATA52 MA_DATA53 MA_DATA54 MA_DATA55

MA_DATA56 MA_DATA57 MA_DATA58 MA_DATA59 MA_DATA60 MA_DATA61 MA_DATA62 MA_DATA63

MA_CHECK0 MA_CHECK1 MA_CHECK2 MA_CHECK3 MA_CHECK4 MA_CHECK5 MA_CHECK6 MA_CHECK7

H17 J17 F20 H20 E17 F17 K18 E20

A21 C21 C23 D23 B20 B21 B23 A23

G22 H22 E25 G25 J20 E22 H23 J23

F26 E27 J26 J27 H25 E26 G28 G29

AN26 AP29 AR26 AP24 AN29 AN27 AR29 AR27

AU26 AV29 AU25 AW25 AU29 AU28 AW26 AT25

AV23 AW23 AV20 AW20 AR23 AT23 AR20 AT20

BB23 BB22 BB20 AY19 BA23 BC23 BC21 BB21

K26 K28 N26 N28 J29 K25 L29 N25

AD29

MA_ZVDDIO

1 2

RC33 39.2_0402_1%@

SO-DIMM1

+1.2V

4

SO-DIMM0

SO-DIMM1

MEM_MB_RST#12,13

SO-DIMM

SO-DIMM0 SO-DIMM1

+1.2V

1 2

RC9 1K_0402_5%

AE28

MA_ADD0

Y27

MA_ADD1

Y29

MA_ADD2

Y26

MA_ADD3

+1.2V

@

W28

MA_ADD4

W29

MA_ADD5

W26

MA_ADD6

U29

MA_ADD7

W25

MA_ADD8

U26

MA_ADD9

AG29

MA_ADD10

U27

MA_ADD11

T28

MA_ADD12

AK26

MA_ADD13

T26

MA_ADD14/MA_BG1

T25

MA_ADD15/MA_ACT_L

AG26

MA_BANK0

AG27

MA_BANK1

T29

MA_BANK2/MA_BG0

E19

MA_DM0

D21

MA_DM1

K21

MA_DM2

F29

MA_DM3

AP28

MA_DM4

AV26

MA_DM5

AR22

MA_DM6

BC22

MA_DM7

K29

MA_DM8

H19

MA_DQS_H0

G19

MA_DQS_L0

B22

MA_DQS_H1

A22

MA_DQS_L1

F23

MA_DQS_H2

E23

MA_DQS_L2

G27

MA_DQS_H3

F27

MA_DQS_L3

AP25

MA_DQS_H4

AP26

MA_DQS_L4

AW27

MA_DQS_H5

AV27

MA_DQS_L5

AV22

MA_DQS_H6

AU22

MA_DQS_L6

BA21

MA_DQS_H7

AY21

MA_DQS_L7

L27

MA_DQS_H8

L26

MA_DQS_L8

AE25

MA_CLK_H0

AE26

MA_CLK_L0

AD26

MA_CLK_H1

AD27

MA_CLK_L1

AB28

MA_CLK_H2

AB29

MA_CLK_L2

AB25

MA_CLK_H3

AB26

MA_CLK_L3

N29

MA_RESET_L

AE29

MA_EVENT_L

P27

MA_CKE0

P29

MA_CKE1

AK27

MA0_ODT0

AL26

MA0_ODT1

AH25

MA1_ODT0

AL25

MA1_ODT1

AH26

MA0_CS_L0

AL29

MA0_CS_L1

AH29

MA1_CS_L0

AL28

MA1_CS_L1

AG24

MA_RAS_L/MA_RAS_L_ADD16

AK29

MA_CAS_L/MA_CAS_L_ADD15

AH28

MA_WE_L/MA_WE_L_ADD14

B19

MA_VREFDQ

T32

M_VREF

@

12

1

CC13

2

@

.047U_0201_6.3V6K

5

D D

C C

B B

+MEM_VREF

RC4

1K_0402_1%

A A

1K_0402_1%

RC5

DDRB_MA[13..0]12,13

DDRB_BG112 DDRB_ACT#12,13

DDRB_BA012,13 DDRB_BA112,13 DDRB_BG012,13

DDRB_DM[7..0]12,13

1

TC20@

1

TC8@

1

TC9@

DDRB_CLK012 DDRB_CLK0#12 DDRB_CLK112 DDRB_CLK1#12 DDRB_CLK213 DDRB_CLK2#13

1 2

RC240 10_0402_5%

MEM_MB_EVENT#12

DDRB_CKE012,13 DDRB_CKE112

DDRB_ODT012 DDRB_ODT112 DDRB_ODT213

DDRB_CS0#12 DDRB_CS1#12 DDRB_CS2#13

DDRB_MA16_RAS#12,13 DDRB_MA15_CAS#12,13 DDRB_MA14_WE#12,13

1

TC70@

MEM_MB_EVENT#

DDRB_MA0 DDRB_MA1 DDRB_MA2 DDRB_MA3 DDRB_MA4 DDRB_MA5 DDRB_MA6 DDRB_MA7 DDRB_MA8 DDRB_MA9 DDRB_MA10 DDRB_MA11 DDRB_MA12 DDRB_MA13 DDRB_BG1 DDRB_ACT#

DDRB_BA0 DDRB_BA1 DDRB_BG0

DDRB_DM0 DDRB_DM1 DDRB_DM2 DDRB_DM3 DDRB_DM4 DDRB_DM5 DDRB_DM6 DDRB_DM7 DDRB_DM8

DDRB_DQS0 DDRB_DQS#0 DDRB_DQS1 DDRB_DQS#1 DDRB_DQS2 DDRB_DQS#2 DDRB_DQS3 DDRB_DQS#3 DDRB_DQS4 DDRB_DQS#4 DDRB_DQS5 DDRB_DQS#5 DDRB_DQS6 DDRB_DQS#6 DDRB_DQS7 DDRB_DQS#7 DDRB_DQS8 DDRB_DQS#8

DDRB_CLK0 DDRB_CLK0# DDRB_CLK1 DDRB_CLK1# DDRB_CLK2 DDRB_CLK2#

MEM_MB_RST#_R MEM_MB_EVENT#

DDRB_CKE0 DDRB_CKE1

DDRB_ODT0 DDRB_ODT1 DDRB_ODT2

DDRB_CS0# DDRB_CS1# DDRB_CS2#

DDRB_MA16_RAS# DDRB_MA15_CAS# DDRB_MA14_WE#

APU_M_VREFDQ

AG31

MB_ADD0

AC30

MB_ADD1

AC31

MB_ADD2

AB32

MB_ADD3

AA32

MB_ADD4

AA33

MB_ADD5

AA31

MB_ADD6

Y33

MB_ADD7

AA30

MB_ADD8

W32

MB_ADD9

AG32

MB_ADD10

Y32

MB_ADD11

W33

MB_ADD12

AL31

MB_ADD13

W30

MB_ADD14/MB_BG1

V32

MB_ADD15/MB_ACT_L

AH32

MB_BANK0

AG33

MB_BANK1

W31

MB_BANK2/MB_BG0

D25

MB_DM0

D29

MB_DM1

E33

MB_DM2

J33

MB_DM3

AR30

MB_DM4

AW30

MB_DM5

BC30

MB_DM6

BC26

MB_DM7

N33

MB_DM8

B26

MB_DQS_H0

A26

MB_DQS_L0

B30

MB_DQS_H1

A30

MB_DQS_L1

F32

MB_DQS_H2

E32

MB_DQS_L2

K32

MB_DQS_H3

J32

MB_DQS_L3

AR32

MB_DQS_H4

AR33

MB_DQS_L4

AW32

MB_DQS_H5

AW33

MB_DQS_L5

BA29

MB_DQS_H6

AY29

MB_DQS_L6

BA25

MB_DQS_H7

AY25

MB_DQS_L7

P32

MB_DQS_H8

N32

MB_DQS_L8

AE33

MB_CLK_H0

AE32

MB_CLK_L0

AE30

MB_CLK_H1

AE31

MB_CLK_L1

AD32

MB_CLK_H2

AD33

MB_CLK_L2

AC33

MB_CLK_H3

AC32

MB_CLK_L3

T33

MB_RESET_L

AG30

MB_EVENT_L

U32

MB_CKE0

U33

MB_CKE1

AL30

MB0_ODT0

AM32

MB0_ODT1

AJ32

MB1_ODT0

AM33

MB1_ODT1

AJ33

MB0_CS_L0

AL32

MB0_CS_L1

AJ30

MB1_CS_L0

AL33

MB1_CS_L1

AH33

MB_RAS_L/MB_RAS_L_ADD16

AK32

MB_CAS_L/MB_CAS_L_ADD15

AJ31

MB_WE_L/MB_WE_L_ADD14

A19

MB_VREFDQ

@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

UC2I

MEMORY B

MB_ZVDDIO_MEM_S

FP4 REV 0.93

AMD-CARRIZO_FP4-BGA968

2013/08/15

A25

MB_DATA0

C25

MB_DATA1

C27

MB_DATA2

D27

MB_DATA3

B24

MB_DATA4

B25

MB_DATA5

B27

MB_DATA6

A27

MB_DATA7

A29

MB_DATA8

C29

MB_DATA9

B32

MB_DATA10

D32

MB_DATA11

B28

MB_DATA12

B29

MB_DATA13

A31

MB_DATA14

C31

MB_DATA15

E30

MB_DATA16

E31

MB_DATA17

G33

MB_DATA18

G32

MB_DATA19

C33

MB_DATA20

D33

MB_DATA21

G30

MB_DATA22

G31

MB_DATA23

J30

MB_DATA24

J31

MB_DATA25

L33

MB_DATA26

L32

MB_DATA27

H32

MB_DATA28

H33

MB_DATA29

L30

MB_DATA30

L31

MB_DATA31

AN31

MB_DATA32

AP32

MB_DATA33

AT32

MB_DATA34

AU32

MB_DATA35

AN33

MB_DATA36

AN32

MB_DATA37

AR31

MB_DATA38

AT33

MB_DATA39

AU30

MB_DATA40

AV32

MB_DATA41

BA33

MB_DATA42

AY32

MB_DATA43

AU33

MB_DATA44

AU31

MB_DATA45

AW31

MB_DATA46

AY33

MB_DATA47

BC31

MB_DATA48

BB30

MB_DATA49

BB28

MB_DATA50

AY27

MB_DATA51

BB32

MB_DATA52

BA31

MB_DATA53

BC29

MB_DATA54

BB29

MB_DATA55

BB27

MB_DATA56

BB26

MB_DATA57

BB24

MB_DATA58

AY23

MB_DATA59

BA27

MB_DATA60

BC27

MB_DATA61

BC25

MB_DATA62

BB25

MB_DATA63

N30

MB_CHECK0

N31

MB_CHECK1

R33

MB_CHECK2

R32

MB_CHECK3

M32

MB_CHECK4

M33

MB_CHECK5

R30

MB_CHECK6

R31

MB_CHECK7

AF32

LC Future Center Secret Data

DDRB_DQ0 DDRB_DQ1 DDRB_DQ2 DDRB_DQ3 DDRB_DQ4 DDRB_DQ5 DDRB_DQ6 DDRB_DQ7

DDRB_DQ8 DDRB_DQ9 DDRB_DQ10 DDRB_DQ11 DDRB_DQ12 DDRB_DQ13 DDRB_DQ14 DDRB_DQ15

DDRB_DQ16 DDRB_DQ17 DDRB_DQ18 DDRB_DQ19 DDRB_DQ20 DDRB_DQ21 DDRB_DQ22 DDRB_DQ23

DDRB_DQ24 DDRB_DQ25 DDRB_DQ26 DDRB_DQ27 DDRB_DQ28 DDRB_DQ29 DDRB_DQ30 DDRB_DQ31

DDRB_DQ32 DDRB_DQ33 DDRB_DQ34 DDRB_DQ35 DDRB_DQ36 DDRB_DQ37 DDRB_DQ38 DDRB_DQ39

DDRB_DQ40 DDRB_DQ41 DDRB_DQ42 DDRB_DQ43 DDRB_DQ44 DDRB_DQ45 DDRB_DQ46 DDRB_DQ47

DDRB_DQ48 DDRB_DQ49 DDRB_DQ50 DDRB_DQ51 DDRB_DQ52 DDRB_DQ53 DDRB_DQ54 DDRB_DQ55

DDRB_DQ56 DDRB_DQ57 DDRB_DQ58 DDRB_DQ59 DDRB_DQ60 DDRB_DQ61 DDRB_DQ62 DDRB_DQ63

MB_ZVDDIO

Deciphered Date

2

DDRB_DQ[63..0] 12,13

DQ bit swapping is allowed in a byte lane.

SO-DIMM

APU

DQ2 UD1.0

DA0

DQ7

DA1

DQ6

DA2

DQ0

DA3

DQ1

DA4

DQ5

DA5

DQ4

DA6

DQ3

DA7

DQ12

DA8

DQ13

DA9

DQ11

DA10

DQ10

DA11

DQ9

DA12

DQ8

DA13

DQ15

DA14

DQ14

DA15

DQ20

DA16

DQ16

DA17

DQ19

DA18

DQ18

DA19

DQ17

DA20

DQ21

DA21

DQ22

DA22

DQ23

DA23

DQ24

DA24

DQ28

DA25

DQ30

DA26

DQ26

DA27

DQ25

DA28

DQ29

DA29

DQ27

DA30

DQ31

DA31

1 2

RC10 39.2_0402_1%

2013/08/15

DRAM

APU

UD1.3

UD1.4

UD1.5

UD1.2

UD1.7

UD1.1

UD1.6

UD1.11

UD1.9

UD1.12

UD1.14

UD1.13

UD1.15

UD1.8

UD1.10

UD2.7

UD2.3

UD2.4

UD2.1

UD2.0

UD2.2

UD2.6

UD2.5

UD2.9

UD2.11

UD2.12

UD2.8

UD2.13

UD2.15

UD2.14

UD2.10

+1.2V

Title

FP4 (MEM)

Size

Document Number Rev

Custom

Tuesday, April 12, 2016

Date: Sheet

DA32

DA33

DA34

DA35

DA36

DA37

DA38

DA39

DA40

DA41

DA42

DA43

DA44

DA45

DA46

DA47

DA48

DA49

DA50

DA51

DA52

DA53

DA54

DA55

DA56

DA57

DA58

DA59

DA60

DA61

DA62

DA63

SO-DIMM

DQ39

DQ36

DQ35

DQ34

DQ37

DQ32

DQ38

DQ33

DQ45

DQ44

DQ47

DQ46

DQ40

DQ41

DQ43

DQ42

DQ55

DQ49

DQ54

DQ48

DQ53

DQ52

DQ50

DQ51

DQ61

DQ56

DQ63

DQ58

DQ60

DQ57

DQ59

DQ62

CG516

1

DRAM

UD3.1

UD3.6

UD3.2

UD3.7

UD3.5

UD3.3

UD3.4

UD3.0

UD3.15

UD3.9

UD3.14

UD3.8

UD3.13

UD3.11

UD3.12

UD3.10

UD4.0

UD4.3

UD4.2

UD4.7

UD4.5

UD4.1

UD4.6

UD4.4

UD4.14

UD4.10

UD4.11

UD4.12

UD4.13

UD4.9

UD4.15

UD4.8

551

of

1.0

5

APU_DP2_TX0+26

RC279 0_0402_5%@ RC213 0_0402_5%@ RC215 0_0402_5%@

RC280 0_0402_5%@ RC217 0_0402_5%@ RC219 0_0402_5%@

1 2

RC31 0_0402_5%@

APU_DP2_TX0-26 APU_DP2_TX1+26

APU_DP2_TX1-26

APU_HDMI_TX2+25 APU_HDMI_TX2-25

APU_HDMI_TX1+25 APU_HDMI_TX1-25

APU_HDMI_TX0+25 APU_HDMI_TX0-25

APU_HDMI_CLK+25 APU_HDMI_CLK-25

APU_EDP_TX0+23 APU_EDP_TX0-23

APU_EDP_TX1+23 APU_EDP_TX1-23

1 2 1 2 1 2

APU_PWROK50,51

+1.8VS

12

RC18

D D

C C

B B

300_0402_5%

APU_RST#

PLACE CC16 CAPS CLOSE TO APU,CRB reserve 27pf

1

CC16 220P_0201_25V7-K

2

@

+1.8VS

12

RC19 300_0402_5%

APU_PWROK

PLACE CC17 CAPS CLOSE TO APU,CRB reserve 27pf

1

CC17 220P_0201_25V7-K

2

@

RPC10 1K_0404_4P2R_5%

1 4

APU_SIC

APU_SID

2 3

1

2

@

1

2

@

+1.8VS+1.8VS

G

S

G

2

QC6B DMN5L06DWK-7 2N SOT363-6

S

61

D

QC6A DMN5L06DWK-7 2N SOT363-6

APU_SVT

CC214 1000P_0201_50V7-K

APU_GFX_SVT

CC215 1000P_0201_50V7-K

5

34

D

DP to VGA

HDMI

eDP

APU_SVT50

APU_SVC50 APU_SVD50

APU_GFX_SVT51

APU_GFX_SVC51 APU_GFX_SVD51

H_PROCHOT#36

EC_SMB_CK2 16,30,36

EC_SMB_DA2 16,30,36

With HDT+ Header

+1.8VS

RC7 1K_0402_5%

1 2

APU_TRST#

A A

2

CC84

0.01U_0201_10V6K

1

1 2

RC76 33_0402_5%HDT@

5

1 8

2 7

RPC17 10K_0804_8P4R_5%

HDT@

3 6

4 5

APU_TRST#_R

JHDT1

@

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

SAMTE_ASP-136446-07-B

2 4 6 8 10 12 14 16

RC273 33_0402_5%HDT@

18 20

4

APU_TCK APU_TMS APU_TDI APU_TDO APU_PWROK_BUF APU_RST#_BUF APU_DBRDY

1 2

APU_TEST19_PLLTEST0 APU_TEST18_PLLTEST1

4

APU_DP2_TX0+ APU_DP2_TX0-

APU_DP2_TX1+ APU_DP2_TX1-

APU_HDMI_TX2+ APU_HDMI_TX2-

APU_HDMI_TX1+ APU_HDMI_TX1-

APU_HDMI_TX0+ APU_HDMI_TX0-

APU_HDMI_CLK+ APU_HDMI_CLK-

APU_EDP_TX0+ APU_EDP_TX0-

APU_EDP_TX1+ APU_EDP_TX1-

APU_SVT_RA APU_SVC_RA APU_SVD_RA

APU_GFX_SVT_RA APU_GFX_SVC_RA APU_GFX_SVD_RA

APU_SIC APU_SID

APU_RST# APU_PWROK

APU_PROCHOT#_R ALERT#

APU_TDI APU_TDO APU_TCK APU_TMS APU_TRST# APU_DBRDY APU_DBREQ#

APU_DBREQ#

B6

DP2_TXP0

A6

DP2_TXN0

D7

DP2_TXP1

C7

DP2_TXN1

A7

DP2_TXP2

B7

DP2_TXN2

D9

DP2_TXP3

C9

DP2_TXN3

A2

DP1_TXP0

A3

DP1_TXN0

B4

DP1_TXP1

A4

DP1_TXN1

D5

DP1_TXP2

C5

DP1_TXN2

A5

DP1_TXP3

B5

DP1_TXN3

E2

DP0_TXP0

E1

DP0_TXN0

E3

DP0_TXP1

E4

DP0_TXN1

D1

DP0_TXP2

D2

DP0_TXN2

C1

DP0_TXP3

B1

DP0_TXN3

C15

SVT0

D17

SVC0

D19

SVD0

B15

SVT1

B16

SVC1

A18

SVD1

B18

SIC

C17

SID

D15

RESET_L

C19

PWROK

A15

PROCHOT_L

B17

ALERT_L

H15

TDI

H14

TDO

D13

TCK

G15

TMS

J14

TRST_L

C13

DBRDY

A11

DBREQ_L

@

RPC5

1K_0804_8P4R_5%

2

CC213

0.01U_0201_10V6K

1

HDT@

DISPLAY/SVI2/JTAG/TEST

DP_STEREOSYNC/TEST36

FP4 REV 0.93

+1.8VS+1.8VS

18 27 36 45

APU_PWROK

APU_RST#

UC2C

DP_ZVSS

DP_AUX_ZVSS

DP_BLON

DP_DIGON

DP_VARY_BL

DP2_AUXP

DP2_AUXN

DP2_HPD

DP1_AUXP

DP1_AUXN

DP1_HPD

DP0_AUXP

DP0_AUXN

DP0_HPD

RSVD_1 TEMPIN0 TEMPIN1 TEMPIN2

TEMPINRETURN

TEST410 TEST411

TEST4 TEST5 TEST6

TEST9 TEST10 TEST14 TEST15 TEST16 TEST17 TEST11 TEST18 TEST19

TEST28_H TEST28_L

TEST31 TEST37

VDDCR_GFX_SENSE

VDDCR_NB_SENSE

VDDCR_CPU_SENSE

VDDP_SENSE

VSS_SENSE

AMD-CARRIZO_FP4-BGA968

0.1U_0201_6.3V6-K

UC6

3 2 1

APU_TDIAPU_DBREQ#

2

1

A9 B9 G5 G6 F11

H9 G9 E9

F7 E7 F5

F8 E8 G8

K24 E15 E14 E12 F14 AK24 AL24 P24 N24 AN24 AB8 Y9 B10 D11 A10 C11 B11 A14 B14

A13 B13 P26 E11 A17

H11 J12 G12 AY18

H12

CC25

HDT@

2A GND 1A

CC212

0.01U_0201_10V6K

@

3

DP_2K_ZVSS DP_150_ZVSS DP_ENBKL DP_ENVDD DP_EDP_PWM

APU_DP2_AUX APU_DP2_AUX# APU_DP2_HPD

APU_DDC_CLK APU_DDC_DATA APU_HDMI_HPD

APU_EDP_AUX APU_EDP_AUX# APU_EDP_HPD

Core_type

TEST410 TEST411 TEST4 TEST5

APU_TEST14_BP0 APU_TEST15_BP1 APU_TEST16_BP2 APU_TEST17_BP3 APU_TEST11_BP4 APU_TEST18_PLLTEST1 APU_TEST19_PLLTEST0

APU_TEST28_H_PLLCHARZ APU_TEST28_L_PLLCHARZ APU_TEST31_MEM_TEST APU_TEST36_STEREOSYNC APU_TEST37

APU_VDDGFX_SEN_H APU_VDDNB_SEN_H APU_VDDCORE_SEN_H VDD_095_FB_H

APU_VSS_SEN_L

1

2

SN74LVC2G07YZPR_WCSP6HDT@

4

2Y

5

VCC

6

1Y

RC55 2K_0402_1% RC12 150_0402_1%

+1.8VS+1.8VS

12

3

1 2 1 2

Hot Plug Detect pins is I-IO18-S,but 3.3V tolerant.

APU_DP2_AUX 26

1 1 1

TC13@

1

TC14@

1 2

RC21 1K_0402_5%@

1

TC18@

1 2

RC23 1K_0402_5%@

1 2

RC24 1K_0402_5%@

1 2

RC189 1K_0402_5%@

1 1 1

APU_DP2_AUX# 26 APU_DP2_HPD 26

APU_DDC_CLK 25 APU_DDC_DATA 25 APU_HDMI_HPD 25

APU_EDP_AUX 23 APU_EDP_AUX# 23 APU_EDP_HPD 23

TC16@ TC17@

TC21@ TC23@ TC25@

DP to VGA

HDMI

eDP

1 2

RC239 100K_0402_5%@

RPC14

1 2

RC259 1K_0402_5%@

1 2

RC28 1K_0402_5%

1 2

RC27 1K_0402_5%@

1 2

RC29 1K_0402_5%@

1 2

RC30 1K_0402_5%@

+3VALW_APU

14 23

1K_0404_4P2R_5%

Tes t36 p ul l hi gh f or AP U re ad E DI D by H DM I DD C si gna l

APU_VDDGFX_SEN_H 51 APU_VDDNB_SEN_H 50 APU_VDDCORE_SEN_H 50

1

@

TC26

1 2

RC236 0_0402_5%@

1 2

RC237 0_0402_5%@

RC32 300_0402_5%

12

RC36 300_0402_5%

APU_PWROK_BUF

APU_RST#_BUF

APU_VDD_SEN_L 50 APU_VDDGFX_SEN_L 51

APU_VDDNB_SEN_H APU_VDDCORE_SEN_H APU_VDD_SEN_L APU_VDDGFX_SEN_H APU_VDDGFX_SEN_L

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPR IETARY PROPERTY OF LC FUTURE CENTER. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPR IETARY PROPERTY OF LC FUTURE CENTER. AND CO NTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

1 1 1 1 1

2013/08/15

+3VS_APU

+1.8VS

TC27@ TC28@ TC29@ TC30@ TC31@

LC Future Center Secret Data

2

To E DP pa nel

DP_EDP_PWM

12

RC11 100K_0402_5%

DP_ENVDD

12

RC13 100K_0402_5%

@

DP_ENBKL

12

RC14 100K_0402_5%

@

Deciphered Date

2

APU_DDC_CLK APU_DDC_DATA

APU_EDP_HPD

ALERT# APU_PROCHOT#_R

+3VS_APU

+3VALW_APU

RC71 10K_0402_5%

1 2

61

D

2

G

S

+3VALW_APU

RC73 10K_0402_5%

@

1 2

61

D

2

G

S

LCD Power IC can change for PCH_ENVDD for cost down

+3VALW_APU

RC75 10K_0402_5%

@

1 2

61

D

2

G

S

PCH_ENBKL con EC 1.8V level GPI pin cost down

12

RC70

4.7K_0402_5%

34

D

5

QC8B

G

DMN5L06DWK-7 2N SOT363-6

S

QC8A DMN5L06DWK-7 2N SOT363-6

1 2

RC205 0_0402_5%@

+3VS_APU

12

RC74

4.7K_0402_5%

@

34

D

5

QC9B

G

DMN5L06DWK-7 2N SOT363-6

@

S

QC9A DMN5L06DWK-7 2N SOT363-6

@

1 2

RC206 0_0402_5%@

+3VS_APU

RC77

2.2K_0402_5%

@

1 2

34

D

5

QC10B

G

DMN5L06DWK-7 2N SOT363-6

@

S

QC10A DMN5L06DWK-7 2N SOT363-6

@

1 2

RC207 0_0402_5%

2013/08/15

FP4 (DISPLAY/CLK/MISC)

Custom

RPC18

1 4 2 3

2.2K_0404_4P2R_5%

1 2

RC35 100K_0402_5%

RPC11

1K_0404_4P2R_5%

PCH_ENBKL 23

Title

Size

Document Number Rev

Tuesday, April 12, 2016

Date: Sheet

1

23 14

PCH_EDP_PWM 23

PCH_ENVDD 23

CG516

1

+3VS_APU

+1.8VS

6 51

of

1.0

5

1 2

RC38 33_0402_5%

RC243 0_0402_5%@

1 2

RB751V-40_SOD323-2

1 2

RC95 0_0402_5%@

RC92

DC3

RC20

2.2K_0402_5%

@

1 2

TEST0 TEST1 TEST2

RC197 15K_0402_5%

1 2

PXS_PWREN_R

VR_VGA_PWRGD

RC46 33_0402_5%

1

CC20 150P_0402_50V8-J

2

1 2

1

CC19 100P_0201_25V8J

2

12

DC1

PCIE_WAKE# 28,31,36

SYS_RESET#

APU_LPC_RST#30,36

PLT_RST#15,28,31

D D

EC_RSMRST#36

12

RC43 100K_0402_5%@

EC set RSMRST OD output

C C

EC_SYS_PWRGD36

PCIE_WAKE#_RA

RC88 0_0402_5%

AGPIO5

RC84

2.2K_0402_5%

@

1 2

RC195 15K_0402_5%

1 2

RC98 10K_0402_5%PX@ RC101 100K_0402_5%@

RC100 10K_0402_5%@ RC104 2K_0402_5%UMA@

SDM10U45LP-7_DFN1006-2-2

1 2 1 2

B B

+3VALW_APU

+3VS_APU

A A

+3VS_APU

@ @

0_0402_5%

2 1

@

RC85 1K_0402_5%

@

1 2

RC196 15K_0402_5%

1 2

12

5

LPC_RST#_R

PCIE_RST#_R

+1.8VALW

12

RC53 1K_0402_5%

1

2

+3VS_APU

1

2

Connected to 10-ms RC-delay circuit on VDD_18_S5 power rail.

(CRB PWR Dealy: 22K/0.1uF)

RSMRST#_R

CC21

0.1U_0402_25V6

12

RC72 10K_0402_5%

@

SYS_PWRGD_R

1

CC22

0.1U_0201_6.3V6-K

2

@

RB751V-40_SOD323-2

CC38

0.1U_0201_6.3V6-K

DC4

1 2

@

PBTN_OUT#36

PM_SLP_S3#36 PM_SLP_S5#36

SYS_PWRGD_R

2/22: change to 50K ohm for Crystal vendor suggest

4

RC191 0_0402_5%@

SYS_RESET#11

PM_SLP_S3#

RC193 0_0402_5%@

PM_SLP_S5#

RC194 0_0402_5%@

APU_S5_MUX_CTRL9

KBRST#36 GATEA2036 EC_SCI#36

AC_PRESENT36

PCH_WLAN_OFF#31

WLAN_CLKREQ#31

LAN_CLKREQ#28 PCH_BT_OFF#31

GPU_CLKREQ#16

USB_OC1#32 USB_OC2#37

SUSCLK11,31

I2C1SDA I2C1SCL I2C0SCL I2C0SDA

RC201 0_0402_5%@

HDA_SDIN035

RPC3

1 8 2 7 3 6 4 5

10K_0804_8P4R_5%

Max ESR < 65K ohm !!

1 2

1 2 1 2

1 2

CC23

1

2

LPC_RST#_R PCIE_RST#_R

RSMRST#_R PWRBTN#_RPBTN_OUT#

SYS_PWRGD_R SYS_RESET# PCIE_WAKE#_RA

PM_SLP_S3#_R PM_SLP_S5#_R

BOARD_ID1 APU_S5_MUX_CTRL

TEST0 TEST1 TEST2

KBRST#

AC_PRESENT BOARD_ID4 BOARD_ID5 BOARD_ID3 AGPIO12 PCH_WLAN_OFF# WLAN_CLKREQ# LAN_CLKREQ# PCH_BT_OFF# GPU_CLKREQ# BOARD_ID2 USB_OC1# USB_OC2#

HDA_BITCLK HDA_SDIN0_R HDA_SDIN1 HDA_SDIN2 HDA_RST# HDA_SYNC HDA_SDOUT

I2C0SCL I2C0SDA I2C1SCL I2C1SDA

RC102

1 2

20M_0402_5%

YC1

1 2

32.768KHZ_12.5PF_202740-PG14

20P_0402_50V8

BB12

LPC_RST_L

AN7

PCIE_RST_L/EGPIO26

AE4

RSMRST_L

AE1

PWR_BTN_L/AGPIO0

BC9

PWR_GOOD

AF2

SYS_RESET_L/AGPIO1

AG2

WAKE_L/AGPIO2

AK7

SLP_S3_L

AH5

SLP_S5_L

AE8

S0A3_GPIO/AGPIO10

AH8

S5_MUX_CTRL/EGPIO42

AH6

TEST0

AK8

TEST1/TMS

AE3

TEST2

AY15

ESPI_RESET_L/KBRST_L/AGPIO129

BC19

GA20IN/AGPIO126

AD7

LPC_PME_L/AGPIO22

BB13

LPC_SMI_L/AGPIO86

AG3

AC_PRES/USB_OC4_L/IR_RX0/AGPIO23

AD5

IR_TX0/USB_OC5_L/AGPIO13

AL8

IR_TX1/USB_OC6_L/AGPIO14

AN8

IR_RX1/AGPIO15

AE2

IR_LED_L/LLB_L/AGPIO12

BC15

CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/AGPIO92

BB17

CLK_REQ1_L/AGPIO115

BC17

CLK_REQ2_L/AGPIO116

BB18

CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/EGPIO131

BB16

CLK_REQG_L/OSCIN/EGPIO132

AH9

USB_OC0_L/TRST_L/AGPIO16

AG1

USB_OC1_L/TDI/AGPIO17

AH2

USB_OC2_L/TCK/AGPIO18

AL9

USB_OC3_L/TDO/AGPIO24

AU6

AZ_BITCLK/I2S_BCLK_MIC

AR8

AZ_SDIN0/I2S_DATA_MIC0

AP6

AZ_SDIN1/I2S_LR_PLAYBACK

AR5

AZ_SDIN2/I2S_DATA_MIC1

AU9

AZ_RST_L/I2S_LR_MIC

AT9

AZ_SYNC/I2S_BCLK_PLAYBACK

AR7

AZ_SDOUT/I2S_DATA_PLAYBACK

BB10

I2C0_SCL/EGPIO145

BB9

I2C0_SDA/EGPIO146

BB7

I2C1_SCL/EGPIO147

BC7

I2C1_SDA/EGPIO148

AG7

32K_X1

32K_X2

1

CC210

2

HDA_RST_AUDIO#35

HDA_SYNC_AUDIO35 HDA_BITCLK_AUDIO35 HDA_SDOUT_AUDIO35

RTCCLK

AT1

X32K_X1

AT2

X32K_X2

@

change YC1 PN to ESPON S CRYSTAL 32.768KHZ X1A000141000300, footprint no change

20P_0402_50V8

PXS_PWREN_R/PXS_RST#_R/VR_VGA_PWRGD internal pull up 40k

4

3

ACPI/SD/AZ/GPIO/ RTC/I2C/UART/ MISC

FP4 REV 0.93

RPC4

1 8 2 7 3 6 4 5

33_0804_8P4R_5%

3

2

RC41 10K_0402_5%

NOKBL@

1 2

RC49 2K_0402_5%

1 2

APU_SMB_CLK APU_SMB_DATA

SCL1 SDA1

AGPIO5 LDT_RST_L LDT_PWROK BOARD_ID0 BOARD_ID6 VDDGFX_PD

AGPIO40 AGPIO64

APU_SHUTDOWN# AGPIO69

BLINK HVB_EN

VR_VGA_PWRGD PXS_PWREN_R

2013/08/15

RC262

AGPIO40 AGPIO64 AGPIO65

AGPIO3 AGPIO4 AGPIO5

AGPIO8 AGPIO9

HDA_RST# HDA_SYNC HDA_BITCLK HDA_SDOUT

1 2

1K_0402_5%

RC40 10K_0402_5%

UMA@

1 2

RC269 10K_0402_5%

PX@

1 2

BB2 BB5 BC2 BB4 AY5

BC3 BA3 BC5 BA5 BB6

BA15 AY17

AG5 AG4

AL5 AL6 AJ1 AJ3 AH1 AJ4 AK5 AD8 AG8 AW15 AU15

AT15 AU12 AT14 AR14 BC13

BA17 AN5 BB14

BA19 BC18

BB19 AY9

AW8 AV5 AV8 AW9

AV11 AU7 AT11 AR11 AP9

RC39 10K_0402_5%

15@

BOARD_ID0 BOARD_ID1 BOARD_ID2 BOARD_ID3 BOARD_ID4 BOARD_ID5 BOARD_ID6

UC2D

UART1_CTS_L/BT_I2S_BCLK/EGPIO140

UART1_INTR/BT_I2S_LRCLK/AGPIO144

AMD-CARRIZO_FP4-BGA968

BR@

1 2

RC47 10K_0402_5%

14@

1 2

SD0_WP/EGPIO101

SD0_PWR_CTRL/AGPIO102

SD0_CD/AGPIO25

SD0_CLK/EGPIO95

SD0_CMD/EGPIO96

SD0_DATA0/EGPIO97 SD0_DATA1/EGPIO98 SD0_DATA2/EGPIO99

SD0_DATA3/EGPIO100

SD0_LED/EGPIO93

SCL0/I2C2_SCL/EGPIO113

SDA0/I2C2_SDA/EGPIO114

SCL1/I2C3_SCL/AGPIO19

SDA1/I2C3_SDA/AGPIO20

AGPIO6/LDT_RST_L

AGPIO7/LDT_PWROK

VDDGFX_PD/AGPIO39

AGPIO66/SHUTDOWN_L

AGPIO68/SGPIO_CLK

AGPIO69/SGPIO_LOAD

AGPIO71/SGPIO_DATAOUT

AGPIO72/SGPIO_DATAIN

SPKR/AGPIO91

BLINK/USB_OC7_L/AGPIO11

GENINT1_L/AGPIO89 GENINT2_L/AGPIO90

FANIN0/AGPIO84

FANOUT0/AGPIO85

UART0_CTS_L/EGPIO135

UART0_RXD/EGPIO136

UART0_RTS_L/EGPIO137

UART0_TXD/EGPIO138

UART0_INTR/AGPIO139

UART1_RXD/BT_I2S_SDI/EGPIO141

UART1_RTS_L/EGPIO142

UART1_TXD/BT_I2S_SDO/EGPIO143

RC261

RC260

BR@

1 2

1K_0402_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

RC257 10K_0402_5%

@

1 2

RC258 2K_0402_5%

KBL@

@

1 2

@

1

TC61

@

1

TC44

@

1

TC71

@

1

TC45

1

@

TC59

1

TC62@

1

TC63@

1

TC64@

1

TC65@

1

TC72@

RPC2

1 4 2 3

@

10K_0404_4P2R_5%

1

TC67@

1

TC68@

1 2

RC278 0_0402_5%@

1 2

RC109 0_0402_5%@

LC Future Center Secret Data

Deciphered Date

2

1 2

APU_SMB_CLK 12,31 APU_SMB_DATA 12,31

AGPIO3 11

VDDGFX_PD 36

ECBTN 36

APU_SHUTDOWN# 16

PCH_BEEP 35

HVB_EN 11 VR_VGA_PWRGD 15,49

RC265 10K_0402_5%

@

RC264 2K_0402_5%

@

+3VALW_APU

RC263 10K_0402_5%

@

1 2

RC266 2K_0402_5%

1 2

RC268 2K_0402_5%

@

1 2

RC267 10K_0402_5%

@

1 2

DIMM1, DIMM2, M ini CARD

VR_GFX_PWRGD 36,51

PXS_PWREN 19,48,49

2013/08/15

1

ID2--5 internal pull up 40K

ID6 internal pull low 40K

+3VS_APU

+3VALW_APU

APU_SMB_CLK APU_SMB_DATA

KBRST# WLAN_CLKREQ# PCH_BT_OFF# PCH_WLAN_OFF#

LAN_CLKREQ# GATEA20

GPU_CLKREQ# APU_SHUTDOWN#

PBTN_OUT# AC_PRESENT PCIE_WAKE#_RA AGPIO5

USB_OC1# USB_OC2#

AGPIO12 PM_SLP_S3# PM_SLP_S5#

BLINK VDDGFX_PD

RPC9

23 14

2.2K_0404_4P2R_5% RPC6

18 27 36 45

10K_0804_8P4R_5%

1 2

RC67 10K_0402_5%

1 2

RC78 10K_0402_5%

1 2

RC64 10K_0402_5%UMA@

1 2

RC96 2K_0402_5%@

RPC15

1 8 2 7 3 6 4 5

10K_0804_8P4R_5%

RPC16

1 4 2 3

10K_0404_4P2R_5%

1 2

RC141 10K_0402_5%

1 2

RC203 2.2K_0402_5%@

1 2

RC208 2.2K_0402_5%@

1 2

RC158 10K_0402_5%@

1 2

RC247 10K_0402_5%@

BLINK isn't strap pin, don't need pull high

AGPIO40 AGPIO69

VDDGFX_PD GPU_CLKREQ# HDA_BITCLK

HDA_SDIN0_R APU_SHUTDOWN#

RSMRST#_R SYS_PWRGD_R

HDA_SDIN2 HDA_SDIN1

Title

FP4 (GEVENT/GPIO/SD/AZ)

Size

Document Num ber Rev

Custom

Custom Date: Sheet

Date: Sheet

1 2

RC93 10K_0402_5%

1 2

RC248 10K_0402_5%BR@

1 2

RC250 10K_0402_5%@

1 2

RC65 2K_0402_5%PX@

1 2

RC90 1K_0402_5%BR@

1 2

RC91 10K_0402_5%@

1 2

RC256 2K_0402_5%@

1 2

RC87 100K_0402_5%

1 2

RC89 100K_0402_5%

1 2

RC241 10K_0402_5%

1 2

RC242 10K_0402_5%

CG516

Tuesday, April 12, 2016

1

7 51

of

1.0

5

SATA_PTX_DRX_P034 SATA_PTX_DRX_N034

HDD

D D

1 2

RC270 10K_0402_5%

1 2

RC271 10K_0402_5%

CLK_PCIE_GPU15 CLK_PCIE_GPU#15

CLK_PCIE_WLAN31 CLK_PCIE_WLAN#31

CLK_PCIE_LAN28 CLK_PCIE_LAN#28

C C

+3VS_APU

1 2

RC99 10K_0402_5%@

1 2

RC103 10K_0402_5%

EC_SPI_CLK36 EC_SPI_CS0#36

EC_SPI_D136

B B

+3VALW

+1.8VS

+3VL_EC

PCH_SPI_CS0# PCH_SPI_D1 PCH_SPI_D2

A A

PCH_SPI_CS0# PCH_SPI_CLK PCH_SPI_D0 PCH_SPI_D1 PCH_SPI_D2 PCH_SPI_D3

RC245 0_0402_5%@ RC246 0_0402_5%@ RC276 0_0402_5%@

UC3

1

/CS

2

DO(IO1)

3

/WP(IO2)

4

GND

EC_SPI_D036 EC_SPI_D236 EC_SPI_D336 PXS_RST#15

1 2 1 2 1 2

/HOLDor/RESET(IO3)

W25Q64FWSSIQ_SO8

5

ODD

+0.95VS

TPM_CLK30 CLK_PCI_EC11,36 LPC_CLK111

PXS_RST#

+VCC_SPI

8

VCC

7 6

CLK

5

DI(IO0)

8M ROM

PCH_SPI_CS0# 36 PCH_SPI_CLK 36 PCH_SPI_D0 36 PCH_SPI_D1 36 PCH_SPI_D2 36 PCH_SPI_D3 36

SATA_PRX_DTX_N034 SATA_PRX_DTX_P034

SATA_PTX_DRX_P134 SATA_PTX_DRX_N134

SATA_PRX_DTX_N134 SATA_PRX_DTX_P134

1 2

RC113 1K_0402_1%

1 2

RC114 1K_0402_1%

1 2

RC143 10K_0402_5%

CLK_PCIE_GPU CLK_PCIE_GPU_R CLK_PCIE_GPU# CLK_PCIE_GPU#_R

CLK_PCIE_WLAN CLK_PCIE_WLAN_R

CLK_PCIE_LAN CLK_PCIE_LAN_R CLK_PCIE_LAN#

EC_SPI_CLK EC_SPI_CS0#

EC_SPI_D1 EC_SPI_D0 EC_SPI_D2 EC_SPI_D3

50mA

PCH_SPI_D3 PCH_SPI_CLK PCH_SPI_D0

RC117 0_0402_5%@ RC118 0_0402_5%@

RC119 0_0402_5%@ RC120 0_0402_5%@

RC121 0_0402_5%@ RC122 0_0402_5%@

1 2

RC125 22_0402_5%TPM@

1 2

RC126 3.3_0402_1%

1 2

RC127 0_0402_5%@

LPC_AD030,36 LPC_AD130,36 LPC_AD230,36 LPC_AD330,36

LPC_FRAME#11,30,36

SERIRQ30,36

LPC_CLKRUN#30

RC149 RC209 0_0402_5%@

RC202 0_0402_5%@ RC144 10K_0402_5% RC199 0_0402_5%@ RC198 0_0402_5%@ RC132 0_0402_5%@ RC133 0_0402_5%@ RC116 0_0402_5%@

CC219 and CC218 should 27pf as EMC suggest

1 2 1 2

1 2

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

EC_SPI_D2 EC_SPI_D3 EC_SPI_CS0#

+VCC_SPI

1

2

4

1

TC53 @

TC54 @

10K_0402_5%

LPCCLK0

CC204

0.1U_0201_6.3V6-K

4

SATA_PTX_DRX_P0 SATA_PTX_DRX_N0

SATA_PRX_DTX_N0 SATA_PRX_DTX_P0

SATA_PTX_DRX_P1 SATA_PTX_DRX_N1

SATA_PRX_DTX_N1 SATA_PRX_DTX_P1

SATA_CALRN SATA_CALRP EGPIO67 EGPIO70 AGPIO130

CLK_PCIE_WLAN#_RCLK_PCIE_WLAN#

CLK_PCIE_LAN#_R

X14M_25M_48M_OSC

48M_X1

48M_X2

LPCCLK0 LPCCLK1

1

AGPIO21

SPI_CLK SPI_CS0# EGPIO119 SPI_D1 SPI_D0 SPI_D2 SPI_D3

RC254 10K_0402_5% RC255 10K_0402_5% RC253 10K_0402_5%

12

1 2 1 2 1 2

RC282 0_0201_5%

EMC_NS@

1

CC219 22P_0201_25V8

EMC_NS@

2

AU3 AU4

AW4 AW3

AW1

AW2 AT17 AT12 BB15

AU2

AU1

BC10

AW14

AY13 BB11

BA11 AY11 BA13 AV14

BC14 BC11

BC6

AW7

AW11 AW12

EMC

AV1 AV2

AY2 AY1

BA1

AE9

BB8 BA9

AY7 BA7

U4 U3

U1 U2

W4 W3

W1 W2

Y2 Y1

T2

T1

@

3

UC2E

SATA_TX0P SATA_TX0N

SATA_RX0N SATA_RX0P

SATA_TX1P SATA_TX1N

SATA_RX1N SATA_RX1P

SATA_ZVSS SATA_ZVDDP DEVSLP0/EGPIO67 DEVSLP1/EGPIO70 SATA_ACT_L/AGPIO130

SATA_X1

SATA_X2

GFX_CLKP GFX_CLKN

GPP_CLK0P GPP_CLK0N

GPP_CLK1P GPP_CLK1N

GPP_CLK2P GPP_CLK2N

GPP_CLK3P GPP_CLK3N

X25M_48M_OSC

X48M_X1

X48M_X2

LPCCLK0/EGPIO74 LPCCLK1/EGPIO75

LAD0 LAD1 LAD2 LAD3 LFRAME_L ESPI_ALERT_L/LDRQ0_L SERIRQ/AGPIO87 LPC_CLKRUN_L/AGPIO88 LPC_PD_L/AGPIO21

SPI_CLK/ESPI_CLK/EGPIO117 SPI_CS1_L/EGPIO118 SPI_CS2_L/ESPI_CS_L/EGPIO119 SPI_DI/ESPI_DATA/EGPIO120 SPI_DO/EGPIO121 SPI_WP_L/EGPIO122 SPI_HOLD_L/EGPIO133 SPI_TPM_CS_L/AGPIO76

+1.8VS

CLK/SATA/USB/SPI/LPC

FP4 REV 0.93

USBCLK/25M_48M_OSC

USB_ZVSS

USB_HSD0P USB_HSD0N

USB_HSD1P USB_HSD1N

USB_HSD2P USB_HSD2N

USB_HSD3P USB_HSD3N

USB_HSD4P USB_HSD4N

USB_HSD5P USB_HSD5N

USB_HSD6P USB_HSD6N

USB_HSD7P USB_HSD7N

USB_SS_ZVSS

USB_SS_ZVDDP

USB_SS_0TXP USB_SS_0TXN

USB_SS_0RXP USB_SS_0RXN

USB_SS_1TXP USB_SS_1TXN

USB_SS_1RXP USB_SS_1RXN

USB_SS_2TXP USB_SS_2TXN

USB_SS_2RXP USB_SS_2RXN

USB_SS_3TXP USB_SS_3TXN

USB_SS_3RXP USB_SS_3RXN

AMD-CARRIZO_FP4-BGA968

CLK_USB48M

AP8

USB_RCOMP

AP5

USB20_P0

AR2

USB20_N0

AR1

USB20_P1

AR3

USB20_N1

AR4

USB20_P2

AN2

USB20_N2

AN1

USB20_P3

AN3

USB20_N3

AN4

USB20_P4

AM1

USB20_N4

AM2

USB20_P5

AL2

USB20_N5

AL1

USB20_P6

AL3

USB20_N6

AL4 AK2

AJ2

USB3.0 port0 must map to USB2.0 port4, USB3.0 port1 must map to USB2.0 port5, USB3.0 port2 must map to USB2.0 port6, USB3.0 port4 must map to USB2.0 port7

USBSS_CALRN

AD2

USBSS_CALRP

AD1 AA3

AA4 W9

W8

USB30_TX_P1

AA2

USB30_TX_N1

AA1

USB30_RX_P1

W5

USB30_RX_N1

W6

USB30_TX_P2

AC1

USB30_TX_N2

AC2

USB30_RX_P2

Y6

USB30_RX_N2

Y7 AC4

AC3

Connect the four USB 3.0 ports to onboard devices first

AB5 AB6

starting from the lower ports and then the remaining ports can be used for routing to USB 3.0 connectors. Less than four USB 3.0 ports can be utilized provided the unused ports are higher-numbered consecutive ports. None of the four USB 3.0 ports can be configured as USB 2.0 external ports.

1 1 2

RC112 11.8K_0402_1%

USB20_P0 37 USB20_N0 37

USB20_P1 37 USB20_N1 37

USB20_P2 31 USB20_N2 31

USB20_P3 23 USB20_N3 23

USB20_P4 33 USB20_N4 33

USB20_P5 32 USB20_N5 32

USB20_P6 37 USB20_N6 37

1 2

RC123 1K_0402_1%

1 2

RC124 1K_0402_1%

USB30_TX_P1 32 USB30_TX_N1 32

USB30_RX_P1 32 USB30_RX_N1 32

USB30_TX_P2 37 USB30_TX_N2 37

USB30_RX_P2 37 USB30_RX_N2 37

48MHz/10pF Crystal

EC_SPI_CLK

LPCCLK1

12

RC281 0_0201_5%

EMC_NS@

1

CC218 22P_0201_25V8

EMC_NS@

2

EMC

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2013/08/15

RC139 10_0402_5%

EMC_NS@

1 2

1

CC26

10P_0201_25V8G

EMC_NS@

2

EMC

LC Future Center Secret Data

Deciphered Date

1

CC28 10P_0402_50V8-J

2

TC69@

RIGHT USB (2.0)

Right USB (2.0) for stoney ridge only

Blue Tooth

Camera

Card Reader

LEFT USB (3.0)

Right USB (3.0) for Bristiol Ridge

+0.95VALW

LEFT USB (3.0)

Right USB (3.0) for Bristiol Ridge

1 2

RC140 1M_0402_5%

YC2

1

OSC1 NC12OSC2

48MHZ_10PF_7V48000017

2013/08/15

2

NC2

4 3

1

48M_X1 48M_X2

change YC2 PN to TXC 48MHZ 10PF X1E000021083400 footprint apply is on going

1

CC29 12P_0402_50V8-J

2

Titl e

FP4 (SATA/USB/LPC/SPI)

Size

Document Number Rev

Custom

Date: Sheet

Tuesday, April 12, 2016

CG516

of

8 51

of

8 51

of

1

8 51

1.0

5

+1.2V

1

CC59

2

22U_0603_6.3V6-M

1

CC60

2

@

22U_0603_6.3V6-M

SIT1CD@

CC53

2

1

CC62

CC61

2

@

22U_0603_6.3V6-M

SIT1CD@

RC210 0_0805_5%BR@

1

2

22U_0603_6.3V6-M

1 2

1

CC54

2

22U_0603_6.3V6-M

1

CC57

CC55

2

22U_0603_6.3V6-M

CC58

CC56

2

22U_0603_6.3V6-M

SIT1CD@

Wake-on-Ring not supported: +VDDIO_AZ_APU Connect to +1.5V S0 rail

1

D D

CC42

2

@

1

RC210,CC180,CC181 must add BRUMA@ in Virtual symbol

+3VS

C C

+VCCRTC

B B

+0.95VS

S5_MUX_CTRL: Enable MUX(S0 to S3)-->LOW Disable MUX(S3 to S0)-->HIGH

APU_S5_MUX_CTRL7

A A

+3VS_APU

RC214

1 2

@

1

0_0402_5%

CC187

2

10U_0603_6.3V6M

+0.95VS

1

CC175

CC174

CC171

2

10U_0603_6.3V6M

SIT1CD@

OK

+APU_CORE_NB

1

CC138

CC139

CC140

2

0.22U_0201_6.3V6-K

OK

1 2

RC231 10K_0402_5%

1

EMC_NS@

2

CC225

CC224

0.1U_0201_6.3V6-K

OK EMC

RC228

5

1

CC167

2

10U_0603_6.3V6M

1

CC141

2

0.22U_0201_6.3V6-K

1

CC37

2

1U_0402_6.3V6K

1 2

0_0402_5%

+1.8VS

1

CC186

2

1

CC178

2

10U_0603_6.3V6M

1

CC143

CC142

2

0.22U_0201_6.3V6-K

SIT1CD@

UC5

1

Vin

2

GND

AP2138N-1.5TRG1_SOT23-3

+3VALW_APU

FCHMOS@

1

CC173

2

0.22U_0201_6.3V6-K

10U_0603_6.3V6M

1

CC177

2

0.22U_0201_6.3V6-K

1

CC144

CC146

2

0.22U_0201_6.3V6-K

SIT1CD@

3

Vout

+20VSB

12

RC230 100K_0402_5%

@

FCHMOS@

2

G

QC5A 2N7002KDWH_SOT363-6

12

RC272

100K_0402_5%

@

+5VALW

+1.8VALW

1

CC197

2

SIT1CD@

1

2

0.22U_0201_6.3V6-K

1

CC194

2

1U_0402_6.3V6K

12

RC227 1M_0402_5%

FCHMOS@

61

D

S

+3VALW_APU

0.22U_0201_6.3V6-K

CC145

+RTCBATT

100K_0402_5%

1

CC188

CC189

2

10U_0603_6.3V6M

0.22U_0201_6.3V6-K

1

CC201

CC198

CC202

2

0.22U_0201_6.3V6-K

1

CC195

2

@

180P_0402_50V8-J

CC196

@

0.22U_0201_6.3V6-K

2

follow CRB reserve

12

34

D

QC5B

5

2N7002KDWH_SOT363-6

G

FCHMOS@

S

12

RC232

FCHMOS@

1 2

RC275 0_0402_5%

1 2

RC274 0_0402_5%@

4

+1.2V

3A

U25

1

CC157

2

1

CC203

2

0.22U_0201_6.3V6-K

1

CC199

2

@

0.22U_0201_6.3V6-K

JCMOS1 SHORT PADS

@

+APU_CORE_NB

FCH_S5_POWER

1

CC159

CC158

2

0.22U_0201_6.3V6-K

SIT1CD@

OK

RC212 0_0402_5%@

+0.95VS_GFX_APU+0.95VS

12

BR@

RC229

100_0402_5%

@

+3VALW_APU

1

CC190

2

1

CC217 47P_0402_50V8J

RF@

2

180P_0402_50V8-J

1

CC200

2

@

0.22U_0201_6.3V6-K

12

RC8

@

470_0603_5%

13

D

QC7

2

G

S

2N7002KW_SOT323-3

@

RC234 0_0402_5%FCHMOS@

1

CC160

2

0.22U_0201_6.3V6-K

1 2

1

CC181

CC180

2

BR@

10U_0603_6.3V6M

1

CC191

2

0.22U_0201_6.3V6-K

10U_0603_6.3V6M

EC_RTCRST#_ON

1 2

1

CC161

CC163

2

0.22U_0201_6.3V6-K

+VDDIO_AZ_APU+VAUDIO

CC184

1

2

0.22U_0201_6.3V6-K

+0.95VALW

+RTCBATT

12

RC15 100K_0402_5%

@

3 2

1

2

0.22U_0201_6.3V6-K

SIT1CD@

1

CC185

2

1U_0402_6.3V6K

SIT1CD@

1

CC182

2

RC6

EC_RTCRST#_ON 36

+3VALW_APU_FCH

FCHMOS@

8

UC4A

P

+_1

O1

-_1

G

AS393MTR-G1_SO8

4

1

CC165

2

180P_0402_50V8-J

1

CC193

2

1U_0402_6.3V6K

+VDDCR_FCH_S5

1

CC183

2

10U_0603_6.3V6M

0.22U_0201_6.3V6-K

+APU_CORE_NB

+RTCBATT_APU

1 2

1K_0402_5%

COMP_OUT1

1

+0.775VALW

FCH_S5_POWER_COMP FCH_S5_POWER

1

CC124 220P_0201_25V7-K

2

@

CC216

0.1U_0201_6.3V6-K

@

FCH_S5_POWER_COMP

+3VALW_APU_FCH

2

1

4

+0.95VALW

U28

W24 W27

AB24 AB27 AB30 AB33 AD25 AD28 AD30 AE24 AE27

AF30

AF33 AG25 AG28 AH24 AH27 AH30 AK25 AK28 AK30 AK33

AL27 AM30

AR19

0.2A

AE6

1.5A

AE5

AP19

0.2A

AP21 AP16

1.5A

AP18 AP10

0.5A

AR9

AP15

0.2A

AR15 AN12

0.8A

AP12 AP13

0.2A

AR12

+0.95VS

AW19

7A

AU17 AU19 AV17 AV19

AW17

AL12

12A

AL13

AL15

AL18

AL21 AN13 AN16 AN19 AN22

AR17

1

CC192

2

0.22U_0201_6.3V6-K

+APU_CORE_NB

+5VALW

RC146 10K_0402_5%

1 2

FCHMOS@

RC235 0_0402_5%

FCHMOS@

1 2

RC224 0_0603_5%

1 2

RC225 0_0603_5%@

+3VALW_APU_FCH

8

UC4B

5

P

+_2

O2

6

-_2

G

AS393MTR-G1_SO8

4

FCHMOS@

P25

VDDIO_MEM_S3_1

P28

VDDIO_MEM_S3_2

T24

VDDIO_MEM_S3_3

T27

VDDIO_MEM_S3_4 VDDIO_MEM_S3_5 VDDIO_MEM_S3_6

V30

VDDIO_MEM_S3_7

V33

VDDIO_MEM_S3_8 VDDIO_MEM_S3_9 VDDIO_MEM_S3_10

Y25

VDDIO_MEM_S3_11

Y28

VDDIO_MEM_S3_12

Y30

VDDIO_MEM_S3_13 VDDIO_MEM_S3_14 VDDIO_MEM_S3_15 VDDIO_MEM_S3_16 VDDIO_MEM_S3_17 VDDIO_MEM_S3_18 VDDIO_MEM_S3_19 VDDIO_MEM_S3_20 VDDIO_MEM_S3_21 VDDIO_MEM_S3_22 VDDIO_MEM_S3_23 VDDIO_MEM_S3_24 VDDIO_MEM_S3_25 VDDIO_MEM_S3_26 VDDIO_MEM_S3_27 VDDIO_MEM_S3_28 VDDIO_MEM_S3_29 VDDIO_MEM_S3_30 VDDIO_MEM_S3_31 VDDIO_MEM_S3_32 VDDIO_MEM_S3_33 VDDIO_MEM_S3_34 VDDIO_MEM_S3_35

VDDIO_AUDIO VDDP_GFX_2

VDDP_GFX_1 VDD_33_1

VDD_33_2 VDD_18_1

VDD_18_2 VDD_18_S5_1

VDD_18_S5_2 VDD_33_S5_1

VDD_33_S5_2 VDDP_S5_1

VDDP_S5_2 VDDCR_FCH_S5_1

VDDCR_FCH_S5_2 VDDP_6

VDDP_1 VDDP_2 VDDP_3 VDDP_4 VDDP_5

VDDCR_NB_1 VDDCR_NB_2 VDDCR_NB_3 VDDCR_NB_4 VDDCR_NB_5 VDDCR_NB_6 VDDCR_NB_7 VDDCR_NB_8 VDDCR_NB_9

VDDBT_RTC_G

AMD-CARRIZO_FP4-BGA968@

1 2

FCHMOS@

COMP_OUT2

7

3

AON6414AL_DFN8-5

5

FCHMOS@

+5VALW

1 2

RC226 0_0402_5%

3

POWER

FP4 REV 0.93

QC1

4

RC148 10K_0402_5%

FCHMOS@

1 2 FCHMOS@

UC2F

VDDCR_CPU_1 VDDCR_CPU_2 VDDCR_CPU_3 VDDCR_CPU_4 VDDCR_CPU_5 VDDCR_CPU_6 VDDCR_CPU_7 VDDCR_CPU_8

VDDCR_CPU_9 VDDCR_CPU_10 VDDCR_CPU_11 VDDCR_CPU_12 VDDCR_CPU_13 VDDCR_CPU_14 VDDCR_CPU_15 VDDCR_CPU_16 VDDCR_CPU_17 VDDCR_CPU_18 VDDCR_CPU_19 VDDCR_CPU_20 VDDCR_CPU_21 VDDCR_CPU_22 VDDCR_CPU_23 VDDCR_CPU_24 VDDCR_CPU_25 VDDCR_CPU_26 VDDCR_CPU_42 VDDCR_CPU_31 VDDCR_CPU_43 VDDCR_CPU_32 VDDCR_CPU_44 VDDCR_CPU_33 VDDCR_CPU_45 VDDCR_CPU_34 VDDCR_CPU_46 VDDCR_CPU_35 VDDCR_CPU_47 VDDCR_CPU_36 VDDCR_CPU_28 VDDCR_CPU_29 VDDCR_CPU_40 VDDCR_CPU_30 VDDCR_CPU_37 VDDCR_CPU_49 VDDCR_CPU_38 VDDCR_CPU_39 VDDCR_CPU_48 VDDCR_CPU_41 VDDCR_CPU_27

VDDCR_GFX_14 VDDCR_GFX_15 VDDCR_GFX_16 VDDCR_GFX_17 VDDCR_GFX_18 VDDCR_GFX_19 VDDCR_GFX_20 VDDCR_GFX_21 VDDCR_GFX_22 VDDCR_GFX_23 VDDCR_GFX_24 VDDCR_GFX_25 VDDCR_GFX_26 VDDCR_GFX_27 VDDCR_GFX_28 VDDCR_GFX_29

VDDCR_GFX_1

VDDCR_GFX_2

VDDCR_GFX_3

VDDCR_GFX_4

VDDCR_GFX_5

VDDCR_GFX_6

VDDCR_GFX_7

VDDCR_GFX_8

VDDCR_GFX_9 VDDCR_GFX_10 VDDCR_GFX_11 VDDCR_GFX_12 VDDCR_GFX_30 VDDCR_GFX_31 VDDCR_GFX_32 VDDCR_GFX_33 VDDCR_GFX_34 VDDCR_GFX_35 VDDCR_GFX_36 VDDCR_GFX_37 VDDCR_GFX_13

1 2 3

RC223 0_0402_5%@

AON6414AL_DFN8-5

5

FCHMOS@

2

+APU_CORE

U8 W7 W12 W15 W18 W21 Y8 Y10 Y13 Y16 Y19 Y22 AB7 AB9 AB12 AB15 AB18 AB21 AD6 AD10 AD13 AD16 AD19 AD22 AE7 AE12 AK9 AG10 AK10 AG13 AK13 AG16 AK16 AG19 AK19 AG22 AK22 AH7 AE18 AE21 AH21 AG6 AH12 AN6 AH15 AH18 AL7 AK6 AE15

L8 L13 L16 L19 L22 N7 N12 N15 N18 N21 P8 P13 P16 P19 P22 T7 F12 F15 G11 G14 J8 J9 J11 K7 K12 K13 K15 K16 T12 T15 T18 T21 U13 U16 U19 U22 K19

+APU_GFX

1

CC129

2

SIT1CD@

+APU_GFX

1

CC147

2

BR@

0.22U_0201_6.3V6-K

+1.2V

VDDCR_CPU

VDDCR_NB

VDDCR_GFX

VDDIO_MEM_S3

VDDCR_FCH_S5

VDDP

VDDP_GFX

VDDP_S5

VDD_18

VDD_18_S5

VDD_33

VDD_33_S5

VDDIO_AUDIO

VDDBT_RTC_G

1 2

RC218 0_0402_5%@

QC2 AON6414AL_DFN8-5

1 2 3

FCHMOS@

1 2

QC3

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPR IETARY PROPERTY OF LC FUTURE CENTER. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPR IETARY PROPERTY OF LC FUTURE CENTER. AND CO NTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

5

4

1 2

RC222 0_0402_5%@

QC4

1 2 3

AON6414AL_DFN8-5

1 2 3

4

FCHMOS@

2013/08/15

1

CC131

CC133

CC132

CC130

2

0.22U_0201_6.3V6-K

BR@

CC168

SIT1CD@

0.22U_0201_6.3V6-K

SIT1CD@

OK

1

CC148

CC149

CC151

CC150

2

BR@

0.22U_0201_6.3V6-K

SIT1CD@

OK

1

2

1

CC170

CC172

CC169

2

0.22U_0201_6.3V6-K

DECOUPLING BETWEEN PROCESSOR AND DIMMs ACROSS VDDIO AND VSS SPLIT

Design Guide CRBG FP4

9*22uf 0603 8*0.22uf 0402 1*180pf 0402 4*22uf 0603 8*0.22uf 0402 1*180pf 0402 9*22uf 0603 9*0.22uf 0402 1*180pf 0402 8*22uf 0603 6*0.22uf 0402 split*4 1*180pf 0402 split*2 2*10uf 0402 1*0.22uf 0402

4*10uf 0402 1*0.22uf 0402 1*180pf 0402 1*10uf 0402 1*0.22uf 0402

1*10uf 0402 1*0.22uf 0402

1*22uf 0603 1*10uf 0402

1*10uf 0402 1*0.22uf 0402

1*10uf 0402 1*10uf 0402

1*0.22uf 0402

1

CC134

2

0.22U_0201_6.3V6-K

1

CC153

CC152

2

BR@

0.22U_0201_6.3V6-K

CC179

0.22U_0201_6.3V6-K

1

CC135

2

0.22U_0201_6.3V6-K

1

CC154

2

BR@

0.22U_0201_6.3V6-K

1

2

180P_0402_50V8-J

3*1uf 0402

1*0.22uf 0402

QC1/QC2/QC3/QC4 Rds on should less possible, CRB is 11.8mohm, there is no load swtich for 0.775V power, so it need mos

+VDDCR_FCH_S5

1 2

RC233 0_0603_5%@

+APU_CORE_NB

5

CC207

LC Future Center Secret Data

2

12

Deciphered Date

CC127

+0.775VALW

12

10U_0603_6.3V6M

CC208

1

CC128

2

@

22U_0603_6.3V6-M

10U_0603_6.3V6M

1

CC136

CC137

2

180P_0402_50V8-J

0.22U_0201_6.3V6-K

1

CC156

2

BR@

0.22U_0201_6.3V6-K

1

CC176

2

180P_0402_50V8-J

SIT1CD@

9*22uf 0805 8*0.22uf 0402 1*180pf 0402 4*22uf 0805 8*0.22uf 0402 1*180pf 0402 10*22uf 0805 9*0.22uf 0402 1*180pf 0402 8*22uf 0603 6*0.22uf 0402 split*4 1*180pf 0402 split*2 2*10uf 0603 1*0.22uf 0402

4*10uf 0603 1*0.22uf 0402 1*180pf 0402 1*10uf 0603 1*0.22uf 0402

1*10uf 0603 1*0.22uf 0402

1*22uf 0603 1*10uf 0402

1*10uf 0603 1*0.22uf 0402

1*10uf 0603 1*10uf 0403

1*0.22uf 0402

3*1uf 0402

1*0.22uf 0402

1

CC126

CC125

2

@

22U_0603_6.3V6-M

4.7U_0402_6.3V6M

+5VALW

1

CC209

2

1U_0402_6.3V6K

2013/08/15

1

CC155

2

180P_0402_50V8-J

13*22uf 0603 8*0.22uf 0402 1*180pf 0402 6*22uf 0603 8*0.22uf 0402 split *5 1*180pf 0402 13*22uf 0603 9*0.22uf 0402 1*180pf 0402 8*22uf 0603 8*0.22uf 0402 split*4 1*180pf 0402 split*2 2*10uf 0603 1*0.22uf 0402

4*10uf 0603 1*0.22uf 0402 1*180pf 0402 1*10uf 0603 1*0.22uf 0402

1*10uf 0603 1*0.22uf 0402

1*22uf 0603 1*10uf 0603

1*10uf 0603 1*0.22uf 0402

1*10uf 0603 1*10uf 0603

1*0.22uf 0402

3*1uf 0402

1*0.22uf 0402

1

CC162

2

4.7U_0402_6.3V6M

Decoupling cap near APU ball

UC7

1

VIN1_1

2

VIN1_2

3

VIN2 VCC4EN

G5018RD1U_TDFN8_3X3

FP4 (POWER&DECOUPLING)

Size

Custom

Date: Sheet

CC166

CC164

2

10U_0603_6.3V6M

SIT1CD@

8

VOUT_1

7

VOUT_2

6

SEL

5 9

GND

Title

Document Number Rev

Tuesday, April 12, 2016

1

2

0.22U_0201_6.3V6-K

1 2

RC277 0_0603_5%

CG516

1

APU_S5_MUX_CTRL

9 51

+VDDCR_FCH_S5

of

1.0

5

4

3

2

1

GND

FP4 REV 0.93

AMD-CARRIZO_FP4-BGA968@

UC2H

VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212

VSS_213 VSS_215 VSS_214

AV30 AV33 AW22 AY4 AY6 AY8 AY10 AY12 AY14 AY16 AY20 AY22 AY24 AY26 AY28 AY30 BB1 BB33 BC4 BC8 BC12 BC16 BC20 BC24 BC28 BC32

L24 AL10 AK21

UC2J

1

TC4@

1

TC6@

1

TC5@

U30 U31

AN30

RSVD_2 RSVD_3 RSVD_4

@

FP4 REV 0.93

AMD-CARRIZO_FP4-BGA968

UC2G

VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62

GND

FP4 REV 0.93

AMD-CARRIZO_FP4-BGA968@

VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98

VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124

L28 M4 M30 N10 N13 N16 N19 N22 N27 P1 P2 P4 P5 P12 P15 P18 P21 P30 P33 T4 T10 T13 T16 T19 T22 T30 U5 U12 U15 U18 U21 U24 V1 V2 V4 W10 W13 W16 W19 W22 Y4 Y5 Y12 Y15 Y18 Y21 Y24 AB1 AB2 AB4 AB10 AB13 AB16 AB19 AB22 AD4 AD9 AD12 AD15 AD18 AD21 AD24

A8 A12 A16 A20 A24

D D

C C

B B

A28 A32

B12 B33

D10 D12 D14 D16 D18 D20 D22 D24 D26 D28 D30

F19 F22 F25 F30 F33

G17 G20 G23 G26

H30

J15 J19 J22 J25 J28

K10 K22 K27 K30 K33

L12 L15 L18 L21 L25

B2

B8

C3

D4

D6

D8

F1

F2

F4

F9

G7

H4

J5

K1

K2

K4

L5

AE10 AE13 AE16 AE19 AE22

AF1 AF4

AG9 AG12 AG15 AG18 AG21

AH4 AH10 AH13 AH16 AH19 AH22

AK1

AK4

AK12 AK15 AK18 AL16 AL19 AL22

AM4

AN9 AN10 AN15 AN18 AN21 AN25 AN28

AP1

AP2

AP4

AP7

AP22 AP27 AP30 AP33

AR6 AR25 AR28

AT4

AT19 AT22 AT30

AU5

AU8 AU11 AU14 AU20 AU23 AU27

AV4

AV7

AV9

AV12 AV15 AV25

VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

2013/08/15

LC Future Center Secret Data

Deciphered Date

3

2013/08/15

Title

FP4 (VSS)

Size

Document Number Rev

Custom

Tuesday, April 12, 2016

Date: Sheet

2

Tuesday, April 12, 2016

CG516

1

of

10 51

1.0

5

4

+3VS +3VS +3VS +3VALW_APU +3VALW_APU +3VALW_APU +3VS_APU

3

2

1

12

RC152

D D

LPC_FRAME#8,30,36

LPC_CLK18

CLK_PCI_EC8,36

AGPIO37

SYS_RESET#7

SUSCLK7,31

HVB_EN7

C C

10K_0402_5%

12

RC159 2K_0402_5%

@

12

RC153 10K_0402_5%

12

RC160 2K_0402_5%

@

12

RC154 10K_0402_5%

@

12

RC161 2K_0402_5%

12

RC155 10K_0402_5%

12

RC162 2K_0402_5%

@

12

RC156 10K_0402_5%

12

RC163 2K_0402_5%

@

12

RC157 10K_0402_5%

12

RC164 2K_0402_5%

@

RC81 10K_0402_5%

@

1 2

12

RC79

0_0402_5%

@

STRAP PINS

LFRAME_L

Signal

Typ e

SPI ROM

PULL

HIGH

B B

PULL LOW

LPC ROM

LPCCLK1 LPCCLK0 AGPI O3SYS_RESET_L

II

II II I

Internal CLK Gen

DefaultDefault

Reserved

Boot Fail Timer Enabled

Boot Fail Timer Disabled

Default

RTCCLK

I

RTC Coin Battery is implemented

Default

RTC Coin Battery is not i mplemented

Normal Power Up &Reset Timing

Default

Reserved

Int pull-upInt pull-upInt pull-up

I

Enhanced reset logic (for quicker S5 resume)

Default

traditional reset logic

HVB_EN

floating

Disable HVB on FP4 plat forms

Default

connected to VSS

Enable HVB on FP4 platforms

Type I straps become valid immediately after capture with the rising edge of RSMRST_L,they are captured only once when power is first applied to the processor Type II straps become valid after PWR_GOOD is asserted,straps are captured every time the systems powers up from the S5 state. A transition from S3 to S0 does not trigger capture.

Type II straps should be pulled up to S0 power rail to prevent leakage when the signal is connected to a device in S0 power domain. If the LPC bus is connected to devices that are on S0 power rail, then a pull-up resistor to VDD_33 is implemented.

All Strap pins must be configured with either external pull-up or pull-down resistors. Platforms that are designed for AOAC complaint are recommended to use the Alternate Reset by strapping this pin to ‘ 1’ for CZ

AGPIO3

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2013/08/15

3

LC Future Center Secret Data

Deciphered Date

2013/08/15

2

Title

FP4 (STRAPS)

Size

Document Number Rev

Custom

Date: Sheet

Tuesday, April 12, 2016

CG516

11 51

1

1.0

of

5

DDR3 SO-DIMM A

JDDR1A

D D

C C

+1.2V

RD273 240_0402_1%@ RD274 240_0402_1%@

DDRB_CKE05,13 DDRB_BG15

DDRB_BG05,13

B B

A A

+1.2V

12

+3VS +3VS

12

RD26

10K_0402_5%

12

RD268 0_0402_5%

@

DDRB_DQ5 DDRB_DQ4 DDRB_DQS#0

DDRB_DQS0 DDRB_DQ1 DDRB_DQ7 DDRB_DQ9 DDRB_DQ12 DDRB_DM1 DDRB_DQ14 DDRB_DQ15 DDRB_DQ11 DDRB_DQ10 DDRB_DQ21 DDRB_DQ20 DDRB_DQS#2

DDRB_DQS2 DDRB_DQ23 DDRB_DQ18 DDRB_DQ29 DDRB_DQ28 DDRB_DM3 DDRB_DQ26 DDRB_DQ27

1 2 1 2

DDRB_CKE0 DDRB_BG1

DDRB_BG0 DDRB_MA12

DDRB_MA9 DDRB_MA8

DDRB_MA6 DDRB_MA4

RD258 1K_0402_1%

DDR4_ALERT

+3VS

12

RD269

10K_0402_5%

1 2

@

RD28 0_0402_5%

@

DDRB0_SA0 DDRB0_SA1 DDRB0_SA2

1

VSS_1

3

DQ5

5

VSS_3

7

DQ1

9

VSS_5

11

DQS0_C

DM0_n/DBIO_n/NC

13

DQS0_t

15

VSS_8

17

DQ7

19

VSS_10

21

DQ3

23

VSS_12

25

DQ13

27

VSS_14

29

DQ9

31

VSS_16

33

DM1_n/DBl1_n/NC

35

VSS_17

37

DQ15

39

VSS_19

41

DQ10

43

VSS_21

45

DQ21

47

VSS_23

49

DQ17

51

VSS_25

53

DQS2_c

DM2_n/DBl2_n/NC

55

DQS2_t

57

VSS_28

59

DQ23

61

VSS_30

63

DQ19

65

VSS_32

67

DQ29

69

VSS_34

71

DQ25

73

VSS_36

75

DM3_n/DBl3_n/NC

77

VSS_37

79

DQ30

81

VSS_39

83

DQ26

85

VSS_41

87

CB5/NC

89

+1.2V +1.2V

VSS_43

91

CB1/NC

93

VSS_45

95

DQS8_c

DM8_n/DBI8_n/NC

97

DQS8_t

99

VSS_48

101

CB2/NC

103

VSS_50

105

CB3/NC

107

VSS_52

109

CKE0

111

VDD_1

113

BG1

115

BG0

117

VDD_3

119

A12

121

A9

123

VDD_5

125

A8

127

A6

129

VDD_7

ARGOS_D4AS0-26001-1P60

ME@

+1.2V

12

RD11

1K_0402_1%

1 2

12

RD270

10K_0402_5%

@

RD29 0_0402_5%

@

1 2

VSS_2 VSS_4 VSS_6 VSS_7

VSS_9 VSS_11 VSS_13 VSS_15

DQS1_c DQS1_t VSS_18

VSS_20 VSS_22 VSS_24 VSS_26 VSS_27 VSS_29 VSS_31 VSS_33 VSS_35

DQS3_c DQS3_t VSS_38

VSS_40 VSS_42

CB4/NC VSS_44 CB0/NC VSS_46

VSS_47 CB6/NC VSS_49 CB7/NC VSS_51

RESET_n

VDD_2 ACT_n

ALERT_n

VDD_4

VDD_6

VDD_8

RD10 1K_0402_1%

15mil

1

2

CD262

0.1U_0201_6.3V6-K

DQ4 DQ0

DQ6 DQ2

DQ12

DQ8

DQ14 DQ11 DQ20 DQ16

DQ22 DQ18 DQ28 DQ24

DQ31 DQ27

CKE1

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120

A11

122

A7

124 126

A5

128

A4

130

+VREF_CA

1

2

CD116

0.1U_0201_6.3V6-K

CD117

1

2

1000P_0201_50V7-K

4

DDRB_DQ6 DDRB_DQ3 DDRB_DM0 DDRB_DQ2 DDRB_DQ0 DDRB_DQ8 DDRB_DQ13 DDRB_DQS#1

DDRB_DQS1

DDRB_DQ16 DDRB_DQ17 DDRB_DM2 DDRB_DQ22 DDRB_DQ19 DDRB_DQ25 DDRB_DQ24 DDRB_DQS#3

DDRB_DQS3 DDRB_DQ31 DDRB_DQ30

forMEM_MB_RST#overshootissue

MEM_MB_RST# DDRB_CKE1

DDRB_ACT# DDR4_ALERT

DDRB_MA11 DDRB_MA7

DDRB_MA5

DDRB_CKE1 5 DDRB_ACT# 5,13

+3VS +VDDSPD

1 2

RD271 0_0402_5%

+2.5VS

1 2

RD272 0_0402_5%@

LayoutNote:PlacenearJDDR1

+0.6VS

CD249

@

+2.5V

CD122

3

DDRB_MA14_WE#5,13

MEM_MB_RST# 5,13

1

CD120

2

@

0.1U_0201_6.3V6-K

1

CD251

CD250

@

2

1

2

0.1U_0201_6.3V6-K

CD248

+VDDSPD

CD28

1U_0402_6.3V6K

4.7U_0402_6.3V6M

1

2

APU_SMB_CLK7,31 APU_SMB_DATA 7,31

1

2

follow CRB1pcs 1uf+2pcs 0.1uf+ 1pcs180pf

1U_0402_6.3V6K

0.1U_0201_6.3V6-K

1

CD124

CD123

2

180P_0402_50V8-J

0.1U_0201_6.3V6-K

1

CC206

2

DDRB_CLK05 DDRB_CLK0#5

1 2

RD259 0_0402_5%

DDRB_BA15,13

DDRB_CS0#5

DDRB_ODT05

DDRB_CS1#5

DDRB_ODT15

CD29

0.1U_0201_6.3V6-K

CD16

CD261

@

+1.2V

1

2

1

2

follow CRB6pcs 0.1uffollow CRB1pcs 4.7uf+ 1pcs0.1uf

0.1U_0201_6.3V6-K

10U_0603_6.3V6M

22P_0402_50V8-J

CD17

CD63

@

2

+1.2V

JDDR1B

DDRB_MA3 DDRB_MA1

DDRB_CLK0 DDRB_CLK1 DDRB_CLK0#

DDRB_BA1 DDRB_CS0#

DDRB_MA14_WE# DDRB_ODT0

DDRB_CS1# DDRB_ODT1

DDRB_DQ39 DDRB_DQS#4

DDRB_DQS4 DDRB_DQ38 DDRB_DQ35 DDRB_DQ41 DDRB_DQ44 DDRB_DM5 DDRB_DQ43 DDRB_DQ47 DDRB_DQ53

DDRB_DQS#6 DDRB_DQS6

DDRB_DQ48 DDRB_DQ55 DDRB_DQ56 DDRB_DQ57 DDRB_DM7 DDRB_DQ63 DDRB_DQ59 DDRB_DQ62 APU_SMB_CLK APU_SMB_DATA

+2.5V

CD121

RF@

RF

0.1U_0201_6.3V6-K

1

CD18

2

1

CD66

@

2

10U_0603_6.3V6M

131

A3

133

A1

135

VDD_9

137

CK0_t

139

CK0_c

141

VDD_11

143

Parity

145

BA1

147

VDD_13

149

CS0_n

151

WE_n/A14

153

VDD_15

155

ODT0

157

CS1_n

159

VDD_17

161

ODT1

163

VDD_19

165

C1/CS3_n/NC

167

VSS_53

169

DQ37

171

VSS_55

173

DQ33

175

VSS_57

177

DQS4_c

179

DQS4_t

181

VSS_60

183

DQ38

185

VSS_62

187

DQ34

189

VSS_64

191

DQ44

193

VSS_66

195

DQ40

197

VSS_68

199

DM5_n/DBl5_n/NC

201

VSS_69

203

DQ46

205

VSS_71

207

DQ42

209

VSS_73

211

DQ52

213

VSS_75

215

DQ49

217

VSS_77

219

DQS6_c

221

DQS6_t

223

VSS_80

225

DQ55

227

VSS_82

229

DQ51

231

VSS_84

233

DQ61

235

VSS_86

237

DQ56

239

VSS_88

241

DM7_n/DBl7_n/NC

243

VSS_89

245

DQ62

247

VSS_91

249

DQ58

251

VSS_93

253

SCL

255

VDDSPD

257

VPP_1

259

CD20

CD67

@

VPP_2

261

GND_1

ARGOS_D4AS0-26001-1P60

ME@

0.1U_0201_6.3V6-K

1

CD21

2

1

2

22U_0603_6.3V6-M

1

2

1

2

1

2

22U_0603_6.3V6-M

EVENT_n

VDD_10

VDD_12

A10/AP

VDD_14

RAS_n/A16

VDD_16

CAS_n/A15

VDD_18

C0/CS2_n/NC

VREFCA

VSS_54 VSS_56 VSS_58

DM4_n/DBl4_n/NC

VSS_59 VSS_61 VSS_63 VSS_65 VSS_67

DQS5_c DQS5_t VSS_70

VSS_72 VSS_74 VSS_76 VSS_78

DM6_n/DBl6_n/NC

VSS_79 VSS_81 VSS_83 VSS_85 VSS_87

DQS7_c DQS7_t VSS_90

VSS_92 VSS_94

GND_2

0.1U_0201_6.3V6-K

1

CD22

2

CD19 22P_0402_50V8-J

RF@

CK1_t

CK1_c

DQ36 DQ32

DQ39 DQ35 DQ45 DQ41

DQ47 DQ43 DQ53 DQ48

DQ54 DQ50 DQ60 DQ57

DQ63 DQ59

A2

A0

BA0

A13

SA2

SDA SA0

Vtt

SA1

0.1U_0201_6.3V6-K

132 134 136 138 140 142 144

146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232 234 236 238 240 242 244 246 248 250 252 254 256 258 260

262

LP2301ALT1G_SOT23-3

1

CD23

@

2

1

CD260 22P_0402_50V8-J

RF@

2

+1.2V

SUSP25,38

0.1U_0201_6.3V6-K

CD58

EMC@

DDRB_DQ[0..63] DDRB_DQS[0..7] DDRB_DQS#[0..7] DDRB_MA[0..13] DDRB_DM[0..7]

DDRB_MA2 MEM_MB_EVENT#

DDRB_CLK1# DDRB_MA0

DDRB_MA10 DDRB_BA0

DDRB_MA16_RAS# DDRB_MA15_CAS#

DDRB_MA13

DDRB0_SA2 DDRB_DQ33DDRB_DQ36 DDRB_DQ37 DDRB_DM4 DDRB_DQ32 DDRB_DQ34 DDRB_DQ40 DDRB_DQ45 DDRB_DQS#5

DDRB_DQS5 DDRB_DQ42 DDRB_DQ46 DDRB_DQ52 DDRB_DQ51DDRB_DQ49 DDRB_DM6 DDRB_DQ50 DDRB_DQ54 DDRB_DQ60 DDRB_DQ61 DDRB_DQS#7

DDRB_DQS7 DDRB_DQ58

DDRB0_SA0 DDRB0_SA1

QD1

27P 25V J NPO 0201

1

CD59

@

2

1

CD12 22P_0402_50V8-J

RF@

2

S

G

2

@

0.1U_0201_6.3V6-K

1

2

RF

MEM_MB_EVENT# 5

DDRB_CLK1 5 DDRB_CLK1# 5

DDRB_BA0 5,13

DDRB_MA16_RAS# 5,13 DDRB_MA15_CAS# 5,13

+VREF_CA

+0.6VS

D

13

27P 25V J NPO 0201

1

CD60

EMC@

2

1

DDRB_DQ[0..63] 5,13 DDRB_DQS[0..7] 5,13 DDRB_DQS#[0..7] 5,13 DDRB_MA[0..13] 5,13

DDRB_DM[0..7] 5,13

+2.5VS+2.5V

1

CD61

@

2

180P_0402_50V8-J

0.1U_0201_6.3V6-K

1

CD62

1

CC211

@

2

SPD Address = A2H

5

Title

Security Classification

Issued Date

THIS SHEET OF ENGINE ERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CON TAINS CONFIDENTIAL

THIS SHEET OF ENGINE ERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CON TAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF L C FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF L C FUTURE CENTER.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF L C FUTURE CENTER.

3

2013/08/15

LC Future Center Secret Data

Deciphered Date

2

2013/08/15

Title

DDRIII SO-DIMM A

Size

Document Number Rev

Custom

Tuesday, April 12, 2016

Date: Sheet

CG516

1

12 51

1.0

of

5

DDRB_MA0 DDRB_MA1 DDRB_MA2 DDRB_MA3 DDRB_MA4 DDRB_MA5 DDRB_MA6 DDRB_MA7 DDRB_MA8 DDRB_MA9 DDRB_MA10 DDRB_MA11 DDRB_MA12

D D

RF

C C

B B

A A

DDRB_DQS#0 DDRB_DQS0 DDRB_DQS#1 DDRB_DQS1

+1.2V

DDRB_DQS#4 DDRB_DQS4 DDRB_DQS#5 DDRB_DQS5

+1.2V

DDRB_MA14_WE#5,12 DDRB_MA15_CAS#5,12 DDRB_MA16_RAS#5,12

DDRB_CLK2#5 DDRB_CLK25

DDRB_CKE05,12

1 2 1 2 1 2 1 2

1 2 1 2

DDRB_BA05,12 DDRB_BA15,12

DDRB_ACT#5,12 DDRB_CS2#5

1 2

DDRB_BG05,12 DDRB_ODT25

1 2 1 2

MEM_MB_RST#5,12

1 2 1 2 1 2 1 2

1 2 1 2

1 2

1 2 1 2

DDRB_MA13 DDRB_MA14_WE#

DDRB_MA15_CAS# DDRB_MA16_RAS#

DDRB_CLK2# DDRB_CLK2

DDRB_CKE0 DDRB_DQS#0D

RD15015_0201_5%

DDRB_DQS0D

RD15115_0201_5%

DDRB_DQS#1D

RD15215_0201_5%

DDRB_DQS1D

RD15315_0201_5%

DDRB_DM1DDDRB_DM1

RD23115_0201_5%

DDRB_DM0DDDRB_DM0

RD23015_0201_5%

DDRB_BA0 DDRB_BA1

DDRB_ACT# DDRB_CS2#

RD2601K_0402_1%

DDRB_BG0 DDRB_ODT2

RD2610_0402_5%

TEN1 TEN2

RD25110K_0402_5%

MEM_MB_RST#

1

CD132

2

@

0.1U_0201_6.3V6-K

DDRB_MA0 DDRB_MA1 DDRB_MA2 DDRB_MA3 DDRB_MA4 DDRB_MA5 DDRB_MA6 DDRB_MA7 DDRB_MA8 DDRB_MA9 DDRB_MA10 DDRB_MA11 DDRB_MA12 DDRB_MA13

DDRB_MA14_WE# DDRB_MA15_CAS# DDRB_MA16_RAS#

DDRB_CLK2# DDRB_CLK2

DDRB_CKE0 DDRB_DQS#4D

RD23815_0201_5%

DDRB_DQS4D

RD23915_0201_5%

DDRB_DQS#5D

RD24015_0201_5%

DDRB_DQS5D

RD24115_0201_5%

DDRB_DM5DDDRB_DM5

RD24315_0201_5%

DDRB_DM4DDDRB_DM4

RD24215_0201_5%

DDRB_BA0 DDRB_BA1

DDRB_ACT# DDRB_CS2#

RD2661K_0402_1%

DDRB_BG0 DDRB_ODT2

RD2670_0402_5%

TEN3

RD25510K_0402_5%

MEM_MB_RST#

1

CD161

2

@

0.1U_0201_6.3V6-K

UD1

P3

A0

P7

A1

R3

A2

N7

A3

N3

A4

P8

A5

P2

A6

R8

A7

R2

A8

R7

A9

M3

A10/AP

T2

A11

M7

A12/BC_N

T8

A13

L2

WE_N/A14

M8

CAS_N/A15

L8

RAS_N/A16

K8

CK_C

K7

CK_T

K2

CKE

F3

LDQS_C

G3

LDQS_T

A7

UDQS_C

B7

UDQS_T

E2

NF/UDM_N/UDBI_N

E7

NF/LDM_N/LDBI_N

N2

BA0

N8

BA1

L3

ACT_N

L7

CS_N

P9

ALERT_N

M2

BG0

K3

ODT

T3

PAR

N9

TEN

P1

RESET_N

F1

VSSQ1

H1

VSSQ2

A2

VSSQ3

D2

VSSQ4

E3

VSSQ5

A8

VSSQ6

D8

VSSQ7

E8

VSSQ8

C9

VSSQ9

H9

VSSQ10

F9

ZQ

12

RD116

MT40A512M16HA083EA_FBGA96

240_0402_1%

@

UD3

P3

A0

P7

A1

R3

A2

N7

A3

N3

A4

P8

A5

P2

A6

R8

A7

R2

A8

R7

A9

M3

A10/AP

T2

A11

M7

A12/BC_N

T8

A13

L2

WE_N/A14

M8

CAS_N/A15

L8

RAS_N/A16

K8

CK_C

K7

CK_T

K2

CKE

F3

LDQS_C

G3

LDQS_T

A7

UDQS_C

B7

UDQS_T

E2

NF/UDM_N/UDBI_N

E7

NF/LDM_N/LDBI_N

N2

BA0

N8

BA1

L3

ACT_N

L7

CS_N

P9

ALERT_N

M2

BG0

K3

ODT

T3

PAR

N9

TEN

P1

RESET_N

F1

VSSQ1

H1

VSSQ2

A2

VSSQ3

D2

VSSQ4

E3

VSSQ5

A8

VSSQ6

D8

VSSQ7

E8

VSSQ8

C9

VSSQ9

H9

VSSQ10

F9

ZQ

12

RD118

MT40A512M16HA083EA_FBGA96

240_0402_1%

@

G2

DQ0

F7

DQ1

H3

DQ2

H7

DQ3

H2

DQ4

H8

DQ5

J3

DQ6

DDRB_DQ5D DDRB_DQ5 DDRB_DQ16D DDRB_DQ16

J7

DQ7

A3

DQ8

DDRB_DQ9D DDRB_DQ9

B8

DQ9

C3

DQ10

DDRB_DQ8D DDRB_DQ8

C7

DQ11

C2

DQ12

DDRB_DQ12D DDRB_DQ12

C8

DQ13

D3

DQ14

D7

DQ15

+1.2V

D1

VDD1

J1

VDD2

L1

VDD3

R1

VDD4

B3

VDD5

G7

VDD6

B9

VDD7

J9

VDD8

L9

VDD9

T9

VDD10

A1

VDDQ1

C1

VDDQ2

G1

VDDQ3

F2

VDDQ4

J2

VDDQ5

F8

VDDQ6

J8

VDDQ7

A9

VDDQ8

D9

VDDQ9

G9

VDDQ10

B1

VPP1

R9

VPP2

M1

VREFCA

E1

VSS1

K1

VSS2

N1

VSS3

T1

VSS4

B2

VSS5

G8

VSS6

E9

VSS7

K9

VSS8

M9

VSS9

T7

NC

DDRB_DQ39D

G2

DQ0

DDRB_DQ32D

F7

DQ1

DDRB_DQ34D

H3

DQ2

DDRB_DQ37D

H7

DQ3

DDRB_DQ38D DDRB_DQ38

H2

DQ4

DDRB_DQ36D

H8

DQ5

DDRB_DQ33D

J3

DQ6

DDRB_DQ35D

J7

DQ7

A3

DQ8

B8

DQ9

DDRB_DQ47D

C3

DQ10

C7

DQ11

C2

DQ12

DDRB_DQ44D

C8

DQ13

D3

DQ14

D7

DQ15

+1.2V

D1

VDD1

J1

VDD2

L1

VDD3

R1

VDD4

B3

VDD5

G7

VDD6

B9

VDD7

J9

VDD8

L9

VDD9

T9

VDD10

A1

VDDQ1

C1

VDDQ2

G1

VDDQ3

F2

VDDQ4

J2

VDDQ5

F8

VDDQ6

J8

VDDQ7

A9

VDDQ8

D9

VDDQ9

G9

VDDQ10

B1

VPP1

R9

VPP2

M1

VREFCA

E1

VSS1

K1

VSS2

N1

VSS3

T1

VSS4

B2

VSS5 VSS6 VSS7 VSS8 VSS9

NC

CD234

G8 E9 K9 M9

T7

1

CD189

2

1000P_0201_50V7-K

1

CD235

2

1000P_0201_50V7-K

4

DDRB_DQ0DDRB_DQ0D

RD16615_0201_5%

DDRB_DQ6DDRB_DQ6D

RD17215_0201_5%

DDRB_DQ4DDRB_DQ4D

RD17015_0201_5%

DDRB_DQ1DDRB_DQ1D

RD16715_0201_5%

DDRB_DQ2DDRB_DQ2D

RD16815_0201_5%

DDRB_DQ3DDRB_DQ3D

RD16915_0201_5%

DDRB_DQ7DDRB_DQ7D

RD17315_0201_5%

RD17115_0201_5%

DDRB_DQ14DDRB_DQ14D

RD18015_0201_5%

RD17515_0201_5%

DDRB_DQ15DDRB_DQ15D

RD18115_0201_5% RD17415_0201_5%

DDRB_DQ10DDRB_DQ10D

RD17615_0201_5% RD17815_0201_5%

DDRB_DQ11DDRB_DQ11D

RD17715_0201_5%

DDRB_DQ13DDRB_DQ13D

RD17915_0201_5%

+2.5V

1

CD202

CD203

2

1U_0402_6.3V6K

0.1U_0201_6.3V6-K

CD188

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

+VREF_CA

1

2

0.1U_0201_6.3V6-K

serReschangeto 0201from0402

DDRB_DQ39

RD20515_0201_5%

DDRB_DQ32

RD20315_0201_5%

DDRB_DQ34

RD20415_0201_5%

DDRB_DQ37

RD20215_0201_5% RD20015_0201_5%

DDRB_DQ36

RD19915_0201_5%

DDRB_DQ33

RD19815_0201_5%

DDRB_DQ35

RD20115_0201_5%

DDRB_DQ43DDRB_DQ43D

RD21315_0201_5%

DDRB_DQ41DDRB_DQ41D

RD21015_0201_5%

DDRB_DQ47

RD20915_0201_5%

DDRB_DQ45DDRB_DQ45D

RD20615_0201_5%

DDRB_DQ46DDRB_DQ46D

RD21115_0201_5%

DDRB_DQ44

RD21215_0201_5%

DDRB_DQ42DDRB_DQ42D

RD20815_0201_5%

DDRB_DQ40DDRB_DQ40D

RD20715_0201_5%

DDRB_DQS#6 DDRB_DQS6 DDRB_DQS#7 DDRB_DQS7

DDRB_DM7 DDRB_DM7D DDRB_DM6 DDRB_DM6D

+2.5V

1

CD237

CD236

2

1U_0402_6.3V6K

0.1U_0201_6.3V6-K

+VREF_CA

1

2

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

0.1U_0201_6.3V6-K

DDRB_DQS#2 DDRB_DQS2 DDRB_DQS#3 DDRB_DQS3

+1.2V

1 2 1 2 1 2 1 2

1 2 1 2

1 2

1 2 1 2

1 2 1 2 1 2 1 2

1 2 1 2

1 2

1 2 1 2

3

P3

P7 R3 N7 N3

P8

P2 R8 R2 R7 M3

T2 M7

T8

L2 M8

L8

K8

K7

K2

F3 G3

A7

B7

E2

E7 N2

N8

L3

L7

P9 M2

K3

T3 N9

P1

F1 H1

A2 D2

E3

A8 D8

E8 C9 H9

F9

12

RD117 240_0402_1%

@

UD4

P3

A0

P7

A1

R3

A2

N7

A3

N3

A4

P8

A5

P2

A6

R8

A7

R2

A8

R7

A9

M3

A10/AP

T2

A11

M7

A12/BC_N

T8

A13

L2

WE_N/A14

M8

CAS_N/A15

L8

RAS_N/A16

K8

CK_C

K7

CK_T

K2

CKE

F3

LDQS_C

G3

LDQS_T

A7

UDQS_C

B7

UDQS_T

E2

NF/UDM_N/UDBI_N

E7

NF/LDM_N/LDBI_N

N2

BA0

N8

BA1

L3

ACT_N

L7

CS_N

P9

ALERT_N

M2

BG0

K3

ODT

T3

PAR

N9

TEN

P1

RESET_N

F1

VSSQ1

H1

VSSQ2

A2

VSSQ3

D2

VSSQ4

E3

VSSQ5

A8

VSSQ6

D8

VSSQ7

E8

VSSQ8

C9

VSSQ9

H9

VSSQ10

F9

ZQ

12

RD119

MT40A512M16HA083EA_FBGA96

240_0402_1%

@

UD2

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP

DQ10

A11

DQ11

A12/BC_N

DQ12

A13

DQ13 DQ14 DQ15

WE_N/A14 CAS_N/A15 RAS_N/A16

VDD1 VDD2

CK_C

VDD3

CK_T

VDD4 VDD5

CKE

VDD6 VDD7

LDQS_C

VDD8

LDQS_T

VDD9

UDQS_C

VDD10

UDQS_T

VDDQ1

NF/UDM_N/UDBI_N

VDDQ2

NF/LDM_N/LDBI_N

VDDQ3 VDDQ4

BA0

VDDQ5

BA1

VDDQ6 VDDQ7

ACT_N

VDDQ8

CS_N

VDDQ9

ALERT_N

VDDQ10

BG0

VPP1 VPP2

ODT

VREFCA

PAR

VSS1

TEN

VSS2 VSS3

RESET_N

VSS4 VSS5

VSSQ1

VSS6

VSSQ2

VSS7

VSSQ3

VSS8

VSSQ4

VSS9

VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9 VSSQ10

ZQ

MT40A512M16HA083EA_FBGA96

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9

VDD10 VDDQ1

VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9

VDDQ10

VPP1 VPP2

VREFCA

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9

NC

G2

DQ0

F7

DQ1

DDRB_DQ21D DDRB_DQ21

H3

DQ2

H7

DQ3

H2

DQ4

H8

DQ5

J3

DQ6

J7

DQ7

A3

DQ8

B8

DQ9

DDRB_DQ31D

C3 C7 C2 C8

DDRB_DQ30D

D3

DDRB_DQ29D DDRB_DQ29

D7

+1.2V D1 J1 L1 R1 B3 G7 B9 J9 L9 T9

A1 C1 G1 F2 J2 F8 J8 A9 D9 G9

B1 R9

M1 E1

K1 N1 T1 B2 G8 E9 K9 M9

T7

NC

G2 F7

DDRB_DQ50D

H3 H7 H2 H8 J3 J7

DDRB_DQ63D

A3

DDRB_DQ61D DDRB_DQ61

B8 C3

DDRB_DQ58D DDRB_DQ58

C7

DDRB_DQ59D

C2

DDRB_DQ60D DDRB_DQ60

C8

DDRB_DQ56D DDRB_DQ56

D3

DDRB_DQ62D DDRB_DQ62

D7

+1.2V D1 J1 L1 R1 B3 G7 B9 J9 L9 T9

A1 C1 G1 F2 J2 F8 J8 A9 D9 G9

B1 R9

M1 E1

K1 N1 T1 B2 G8 E9 K9 M9

T7

+VREF_CA

1

CD230

CD231

2

1000P_0201_50V7-K

+1.2V

CD266

CD267

47P_0201_25V8-J

1

EMC_NS@

2

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

+VREF_CA

1

CD239

CD238

2

0.1U_0201_6.3V6-K

1000P_0201_50V7-K

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

0.1U_0201_6.3V6-K

1

EMC@

2

DDRB_DQ20DDRB_DQ20D

RD18715_0201_5%

DDRB_DQ19DDRB_DQ19D

RD18815_0201_5% RD18615_0201_5%

DDRB_DQ17DDRB_DQ17D

RD18315_0201_5%

DDRB_DQ18DDRB_DQ18D

RD18915_0201_5%

DDRB_DQ23DDRB_DQ23D

RD18415_0201_5%

DDRB_DQ22DDRB_DQ22D

RD18515_0201_5% RD18215_0201_5%

DDRB_DQ27DDRB_DQ27D

RD19215_0201_5%

DDRB_DQ24DDRB_DQ24D

RD19015_0201_5%

DDRB_DQ31

RD19715_0201_5%

DDRB_DQ25DDRB_DQ25D

RD19115_0201_5%

DDRB_DQ26DDRB_DQ26D

RD19315_0201_5%

DDRB_DQ28DDRB_DQ28D

RD19615_0201_5%

DDRB_DQ30

RD19515_0201_5% RD19415_0201_5%

+2.5V

1

CD233

CD232

2

1U_0402_6.3V6K

0.1U_0201_6.3V6-K

CD271

CD269

CD268

27P 25V J NPO 0201

1

EMC@

2

DDRB_DQ48DDRB_DQ48D

RD22115_0201_5%

DDRB_DQ53DDRB_DQ53D

RD21415_0201_5%

DDRB_DQ50

RD21615_0201_5%

DDRB_DQ49DDRB_DQ49D

RD21815_0201_5%

DDRB_DQ55DDRB_DQ55D

RD22015_0201_5%

DDRB_DQ52DDRB_DQ52D

RD21515_0201_5%

DDRB_DQ54DDRB_DQ54D

RD21715_0201_5%

DDRB_DQ51DDRB_DQ51D

RD21915_0201_5%

DDRB_DQ63

RD22715_0201_5% RD22215_0201_5%

DDRB_DQ57DDRB_DQ57D

RD22315_0201_5% RD22515_0201_5%

DDRB_DQ59

RD22415_0201_5% RD22815_0201_5% RD22615_0201_5% RD22915_0201_5%

+2.5V

1

CD240

CD241

2

0.1U_0201_6.3V6-K

CD272

CD270

27P 25V J NPO 0201

1

EMC@

2

1U_0402_6.3V6K

DDRB_MA0 DDRB_MA1 DDRB_MA2 DDRB_MA3 DDRB_MA4 DDRB_MA5 DDRB_MA6 DDRB_MA7 DDRB_MA8 DDRB_MA9 DDRB_MA10 DDRB_MA11 DDRB_MA12 DDRB_MA13

DDRB_MA14_WE# DDRB_MA15_CAS# DDRB_MA16_RAS#

DDRB_CLK2# DDRB_CLK2

DDRB_CKE0 DDRB_DQS#2D

RD23215_0201_5%

DDRB_DQS2D

RD23315_0201_5%

DDRB_DQS#3D

RD23415_0201_5%

DDRB_DQS3D

RD23515_0201_5%

DDRB_DM3DDDRB_DM3

RD23715_0201_5%

DDRB_DM2DDDRB_DM2

RD23615_0201_5%

DDRB_BA0 DDRB_BA1

DDRB_ACT# DDRB_CS2#

RD2641K_0402_1%

DDRB_BG0 DDRB_ODT2

RD2650_0402_5% RD25310K_0402_5%

MEM_MB_RST#

1

CD160

2

@

0.1U_0201_6.3V6-K

DDRB_MA0 DDRB_MA1 DDRB_MA2 DDRB_MA3 DDRB_MA4 DDRB_MA5 DDRB_MA6 DDRB_MA7 DDRB_MA8 DDRB_MA9 DDRB_MA10 DDRB_MA11 DDRB_MA12 DDRB_MA13

DDRB_MA14_WE# DDRB_MA15_CAS# DDRB_MA16_RAS#

DDRB_CLK2# DDRB_CLK2

DDRB_CKE0 DDRB_DQS#6D

RD24415_0201_5%

DDRB_DQS6D

RD24515_0201_5%

DDRB_DQS#7D

RD24615_0201_5%

DDRB_DQS7D

RD24715_0201_5% RD24915_0201_5%

RD24815_0201_5%

DDRB_BA0 DDRB_BA1

DDRB_ACT# DDRB_CS2#

RD2621K_0402_1%

DDRB_BG0 DDRB_ODT2

RD2630_0402_5%

TEN4

RD25710K_0402_5%

MEM_MB_RST#

1

CD162

2

@

0.1U_0201_6.3V6-K

2

DDRB_DQ[0..63] DDRB_DQS[0..7] DDRB_DQS#[0..7] DDRB_MA[0..13] DDRB_DM[0..7]

CD163changefromKtoJ

DDRB_CLK2#

RD122 39_0402_5%

DDRB_CLK2

2/22:changetoKbackformaterilstockrisk, andthischange hasconf ir mto AMD

CD274

CD273

27P 25V J NPO 0201

47P_0201_25V8-J

1

EMC@

EMC_NS@

2

CD277

CD275

CD276

27P 25V J NPO 0201

47P_0201_25V8-J

1

EMC_NS@

2

LayoutNote:PlacenearDRAM

27P 25V J NPO 0201

3A@1.5V

1

EMC@

+1.2V

2

followSCL 20pcs0.22uf

0.22U_0201_6.3V6-K

1

CD155

CD154

2

3A@1.5V

+1.2V

0.22U_0201_6.3V6-K

1

CD173

CD174

2

+1.2V

0.22U_0201_6.3V6-K

1

CD215

CD218

@

2

+0.6VS

followSCL 10pcs0.22uf

0.22U_0201_6.3V6-K

1

CD148

CD146

2

+0.6VS

0.22U_0201_6.3V6-K

1

CD252

CD259

@

2

1

2

1

2

1

2

1

2

1

2

DDRB_MA0 DDRB_MA1 DDRB_MA2 DDRB_MA3 DDRB_MA4 DDRB_MA5 DDRB_MA6 DDRB_MA7 DDRB_MA8 DDRB_MA9 DDRB_MA10 DDRB_MA11 DDRB_MA12 DDRB_MA13

DDRB_MA14_WE# DDRB_MA15_CAS# DDRB_MA16_RAS#

DDRB_ACT# DDRB_ODT2

DDRB_CS2# DDRB_CKE0

DDRB_BA0 DDRB_BA1

DDRB_BG0

0.22U_0201_6.3V6-K

CD142

0.22U_0201_6.3V6-K

CD169

0.22U_0201_6.3V6-K

1

CD212

@

2

0.22U_0201_6.3V6-K

CD139

0.22U_0201_6.3V6-K

RD123 39_0402_5%

RD148 39_0402_5% RD149 39_0402_5% RD124 39_0402_5% RD125 39_0402_5% RD126 39_0402_5% RD127 39_0402_5% RD128 39_0402_5% RD129 39_0402_5% RD130 39_0402_5% RD131 39_0402_5% RD132 39_0402_5% RD133 39_0402_5% RD134 39_0402_5% RD135 39_0402_5%

RD138 39_0402_5% RD139 39_0402_5% RD140 39_0402_5%

RD144 39_0402_5% RD147 39_0402_5%

RD145 39_0402_5% RD141 39_0402_5%

RD142 39_0402_5% RD143 39_0402_5%

RD146 39_0402_5%

0.22U_0201_6.3V6-K

1

CD127

2

0.22U_0201_6.3V6-K

1

CD165

2

0.22U_0201_6.3V6-K

1

CD211

@

2

0.22U_0201_6.3V6-K

1

CD138

2

+0.6VS

1

CD263 22P_0402_50V8-J

RF@

2

DDRB_DQ[0..63] 5,12 DDRB_DQS[0..7] 5,12 DDRB_DQS#[0..7] 5,12 DDRB_MA[0..13] 5,12

DDRB_DM[0..7] 5,12

1 2 1 2

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

1 2 1 2 1 2

1 2 1 2

1 2

0.22U_0201_6.3V6-K

CD141

0.22U_0201_6.3V6-K

CD167

0.22U_0201_6.3V6-K

CD201

0.22U_0201_6.3V6-K

1

2

0.22U_0201_6.3V6-K

1

2

0.22U_0201_6.3V6-K

1

2

1

2

CD152

CD172

+1.2V

1

2

CD245

CD264 22P_0402_50V8-J

RF@

0.22U_0201_6.3V6-K

1

CD150

2

0.22U_0201_6.3V6-K

1

CD171

2

CD133 22P_0402_50V8-J

RF@

0.22U_0201_6.3V6-K

1

CD246

2

1

1 2

CD163 0.01UF_0402_25V7-K

+0.6VS

0.22U_0201_6.3V6-K

1

CD158

CD143

2

0.22U_0201_6.3V6-K

1

CD175

CD168

2

1

CD153 22P_0402_50V8-J

RF@

2

0.22U_0201_6.3V6-K

1

CD244

CD243

2

+2.5V

1

CC205

2

180P_0402_50V8-J

+1.2V

0.22U_0201_6.3V6-K

1

CD137

2

0.22U_0201_6.3V6-K

1

CD166

2

0.22U_0201_6.3V6-K

1

CD242

2

1

CD265 22P_0402_50V8-J

RF@

2

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE S ECRET INFORMATION. TH IS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. TH IS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. TH IS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2

2013/08/15

LC Future Center Secret Data

Deciphered Date

2013/08/15

Title

DDRIII SO-DIMM B

Size

Document Num ber Rev

Custom

Date: Sheet

Tuesday, April 12, 2016

1

CG516

13 51

1.0

of

5

4

3

2

1

Power-Up/Down Sequence

"Topaz" has the following requirements with regards to power-supply sequencing to

D D

avoid damaging the ASIC:

All the ASIC supplies must reach their respective nominal voltages within 20 ms of the start of the ramp-up sequence, though a shorter ramp-up duration is preferred. The maximum slew rate on all rails is 50 mV/μ s. It is recommended that the 3.3-V rail ramp up first. The 3.3-V, 1.8-V, and 0.95-V rails must reach their ready state at least 10 μ s before VDDC, VDDCI, and VMEMIO start to ramp up. The power rails that are shared with other components on the system should be gated for the dGPU so that when the dGPU is powered down (for example AMD PowerXpress idle state), all the power rails are removed from the dGPU. The gate circuits must meet the slew rate requirement (such as ≤ 50 mV/μ s). For power down, reversing the ramp-up sequence is recommended.

VRAM ID config

Memory Type

NA

128Mx16

NA

VRAM ID PU resistor PD resistor

PS_3[3:1]

100

111

RV63 RV70

4.53K 4.99K

NC4.75K

NA

110

10K3.4K

0~ 20ms

VDDR3(+3VGS)

C C

VDD_CT(+1.8VGS)

0~ 20ms

256Mx16

PCIE_VDDC(+0.95VGS)

Hynix

H5TC4G63CFR-N0C 4Gb 900(1G)

Micron

MT41J256M16LY-091G:N 4Gb 900(1G)

Samsung

K4W4G1646E-BC1A 4Gb 900(1G)

000

010

001

NC 4.75K

4.53K 2K

8.45K 2K

10us min.

VDDR1(+1.35VGS)

VDDC/VDDCI(+VGA_CORE)

PERSTb(GPU_RST#)

100ms min.

100us min.

REFCLK(CLK_PCIE_VGA)

B B

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2013/08/08

LC Future Center Secret Data

Deciphered Date

2

2013/08/05

Title

VGA Notes List

Size

Document Number Rev

Custom

Tuesday, April 12, 2016

Date: Sheet

CG516

1

14 51

1.0

of

5

PCIE_CTX_C_GRX_P[7..0]4 PCIE_CTX_C_GRX_N[7..0]4

PCIE_CTX_C_GRX_P[7..0] PCIE_CTX_C_GRX_N[7..0]

4

UV1A

3

PCIE_CRX_GTX_P[7..0] PCIE_CRX_GTX_N[7..0]

2

PCIE_CRX_GTX_P[7..0] 4 PCIE_CRX_GTX_N[7..0] 4

1

PCIE_CTX_C_GRX_P0 PCIE_CTX_C_GRX_N0

D D

C C

B B

PCIE_CTX_C_GRX_P1 PCIE_CTX_C_GRX_N1

PCIE_CTX_C_GRX_P2 PCIE_CTX_C_GRX_N2

PCIE_CTX_C_GRX_P3 PCIE_CTX_C_GRX_N3

PCIE_CTX_C_GRX_P4 PCIE_CTX_C_GRX_N4

PCIE_CTX_C_GRX_P5 PCIE_CTX_C_GRX_N5

PCIE_CTX_C_GRX_P6 PCIE_CTX_C_GRX_N6

PCIE_CTX_C_GRX_P7 PCIE_CTX_C_GRX_N7

AF30

AE31

AE29 AD28

AD30 AC31

AC29 AB28

AB30 AA31

AA29

Y28

Y30

W31

W29

V28

V30 U31

U29

R31

R29 P28

P30 N31

N29 M28

M30

K30

T28

T30

L31

L29

PCIE_RX0P PCIE_RX0N

PCIE_RX1P PCIE_RX1N

PCIE_RX2P PCIE_RX2N

PCIE_RX3P PCIE_RX3N

PCIE_RX4P PCIE_RX4N

PCIE_RX5P PCIE_RX5N

PCIE_RX6P PCIE_RX6N

PCIE_RX7P PCIE_RX7N

NC#V30 NC#U31

NC#U29 NC#T28

NC#T30 NC#R31

NC#R29 NC#P28

NC#P30 NC#N31

NC#N29 NC#M28

NC#M30 NC#L31

NC#L29 NC#K30

PCIE_TX0P PCIE_TX0N

PCIE_TX1P PCIE_TX1N

PCIE_TX2P PCIE_TX2N

PCIE_TX3P PCIE_TX3N

PCIE_TX4P PCIE_TX4N

PCIE_TX5P PCIE_TX5N

PCIE_TX6P PCIE_TX6N

PCIE_TX7P PCIE_TX7N

NC#W24 NC#W23

NC#V27

PCI EXPRESS INTERFACE

NC#U26

NC#U24 NC#U23

NC#T26 NC#T27

NC#T24 NC#T23

NC#P27 NC#P26

NC#P24 NC#P23

NC#M27

NC#N26

PCIE_CRX_C_GTX_P0 PCIE_CRX_GTX_P0

AH30

PCIE_CRX_C_GTX_N0 PCIE_CRX_GTX_N0

AG31

PCIE_CRX_C_GTX_P1

AG29

PCIE_CRX_C_GTX_N1

AF28

PCIE_CRX_C_GTX_P2

AF27

PCIE_CRX_C_GTX_N2

AF26

PCIE_CRX_C_GTX_P3

AD27

PCIE_CRX_C_GTX_N3

AD26

PCIE_CRX_C_GTX_P4 PCIE_CRX_GTX_P4

AC25

PCIE_CRX_C_GTX_N4

AB25

PCIE_CRX_C_GTX_P5

Y23

PCIE_CRX_C_GTX_N5

Y24

PCIE_CRX_C_GTX_P6

AB27

PCIE_CRX_C_GTX_N6

AB26

PCIE_CRX_C_GTX_P7

Y27

PCIE_CRX_C_GTX_N7

Y26

W24 W23

V27 U26

U24 U23

T26 T27

T24 T23

P27 P26

P24 P23

M27 N26

change the GPU PN to AMD(EXO-S3 PRO), symbol check ok 11/4 change to PC sample SA000074V10

1 2 1 2

CV10.22U_0201_6.3V6-K PX@ CV20.22U_0201_6.3V6-K PX@

CV30.22U_0201_6.3V6-K PX@ CV40.22U_0201_6.3V6-K PX@

CV50.22U_0201_6.3V6-K PX@ CV60.22U_0201_6.3V6-K PX@

CV70.22U_0201_6.3V6-K PX@ CV80.22U_0201_6.3V6-K PX@

CV170.22U_0201_6.3V6-K BRPX@ CV90.22U_0201_6.3V6-K BRPX@

CV130.22U_0201_6.3V6-K BRPX@ CV110.22U_0201_6.3V6-K BRPX@

CV140.22U_0201_6.3V6-K BRPX@ CV120.22U_0201_6.3V6-K BRPX@

CV100.22U_0201_6.3V6-K BRPX@ CV200.22U_0201_6.3V6-K BRPX@

with BOM strcture control, CV1--CV8 change to 0.22uf for CZ

PCIE_CRX_GTX_P1 PCIE_CRX_GTX_N1

PCIE_CRX_GTX_P2 PCIE_CRX_GTX_N2

PCIE_CRX_GTX_P3 PCIE_CRX_GTX_N3

PCIE_CRX_GTX_N4

PCIE_CRX_GTX_P5 PCIE_CRX_GTX_N5

PCIE_CRX_GTX_P6 PCIE_CRX_GTX_N6

PCIE_CRX_GTX_P7 PCIE_CRX_GTX_N7

CLOCK

AK30

PCIE_REFCLKP

AK32

PCIE_REFCLKN

N10

TEST_PG

AL27

PERSTB

S IC 216-0867-071 A0 FCBGA 631P GPU 12

EXO@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

CALIBRATION

PCIE_CALR_TX

PCIE_CALR_RX

Y22 AA22

RV3 1.69K_0402_1%PX@ RV5 1K_0402_1%PX@

2013/08/08

3

1 2 1 2

VR_VGA_PWRGD7,49

LC Future Center Secret Data

Deciphered Date

+0.95VGS

GPU_RST# VR_VGA_PWRGD

PX@

DV3

2 3

2013/08/05

1

LBAT54AWT1G SOT323

2

VGA_PWROK

Titl e

Size

Custom

Date: Sheet

VGA_PWROK 49

ATI_JET-LE_PCIE

Document Number Rev

Tuesday, April 12, 2016

CG516

1

15 51

of

1.0

1 2

GPU_RST#

CLK_PCIE_GPU CLK_PCIE_GPU#

RV41K_0402_1% PX@

12

RV6 100K_0402_5%

PX@

4

CLK_PCIE_GPU8 CLK_PCIE_GPU#8

GPU_RST#16

1 2

RV7 0_0402_5%@

+3VGS

A A

PXS_RST#8 PLT_RST#7,28,31

5

1

IN1

VCC

2

OUT

IN2

GND

MC74VHC1G08DFT2G_SC70-5

3

PX@

UV2

GPU_RST#

4

5

Reserve

D D

+3VGS

1 2

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

1 2

GPU_GPIO5

RV810K_0402_5% @

GPU_GPIO0

RV910K_0402_5% @

GPU_GPIO8

RV1210K_0402_5% @

GPU_GPIO9

RV1310K_0402_5% @

GPU_GPIO10

RV1410K_0402_5% @

GPU_GPIO11

RV2510K_0402_5% @

GPU_GPIO12

RV9610K_0402_5% @

GPU_GPIO13

RV3410K_0402_5% @

GPU_GPIO22

RV8110K_0402_5% @

GPU_VID1

RV9710K_0402_5% @

GPU_GPIO21

RV9810K_0402_5% @

GPU_VID5

RV9910K_0402_5% @

GPU_VID2

RV10610K_0402_5% @

GPU_GPIO17

RV101110K_0402_5% @

+1.8VGS

RV93 RV95

1 2

4.7K_0402_5%

1 2

4.7K_0402_5%

TOPAZ@ TOPAZ@

Reserve

+1.8VGS

RB751V-40_SOD323-2

DV1

1 2

RV104 0_0402_5%PX@

10K_0402_5%

1 2

RV64

1K_0402_5%

+VGA_CORE

TV6PAD @

1 2

LV3

BLM15PD121SN1D_2P

(1.8V@20mA TSVDD)

+VGA_CORE

1 2

RV100 0_0402_5%

TOPAZ@

1 2

RV101 0_0402_5%

TOPAZ@

1 2

RV102 0_0402_5%

TOPAZ@

1 2

RV108 0_0402_5%

TOPAZ@

C C

+3VGS

B B

1 2 1 2 1 2

1 2

12

CV25

PX@

8P_0201_25V8-D

2

1

YV1

PX@

OSC1

GND1

OSC23GND2

4

12

CV32

PX@

8P_0201_25V8-D

nosymbolfor 8pfcap,PLMhasPN,changethe PN

RV41

+3VGS

+VGA_CORE_GPIO1 +VGA_CORE_GPIO2 +VGA_CORE_GPIO14 +VGA_CORE_GPIO18

GPU_VR_HOT#36,49

JTAG_TRSTB

RV7210K_0402_5% @

JTAG_TDI

RV7510K_0402_5% @

JTAG_TMS

RV7810K_0402_5% @

JTAG_TCK

RV4010K_0402_5% @

XTALIN

12

RV46 1M_0402_5%

PX@

27MHZ_10PF_7V27000050

XTALOUT

1 2

@

10K_0402_5%

RV42

10K_0402_5%

EXO@

ConnectGPIO_28to10K pull downtoenableMLPS.

VGA_AC_DET36

GPU_VR_HOT#

GPU_SVD

GPU_SVC

GPU_VR_HOT#

GPU_CLKREQ#7

1 2

@

1 2

TV3PAD@

1 2 1 2 1 2

PX@

1 2 1 2

PX@

1 2 1 2

1

TV11

TV12

TV13PAD @ TV14PAD @

PAD

RV1030_0402_5% EXO@ RV6710K_0402_5% @ RV1070_0402_5% @

RV68 RV1050_0402_5% EXO@

RV10120_0402_5% @ RV1240_0402_5% @

PAD TV7

PX_EN

RV4510K_0402_5% PX@ RV5010K_0402_5% PX@

PX@

4

BP_0 VGA_VDDCI_SEN

1

@

BP_1 PLL_ANALOG_IN

1

@

GPU_GPIO0 +VGA_CORE_GPIO1 +VGA_CORE_GPIO2 VGA_SMB_DATA VGA_SMB_CLK GPU_GPIO5 GPU_VID5

GPU_GPIO8 GPU_GPIO9 GPU_GPIO10 GPU_GPIO11 GPU_GPIO12

1

GPU_GPIO13 +VGA_CORE_GPIO14 GPU_VID3 GPU_GPIO16 GPU_GPIO17 +VGA_CORE_GPIO18 GPIO_19_CTF GPU_VID4 GPU_GPIO21 GPU_GPIO22 GPU_VID2 GPU_VID1 GPU_CLKREQ#_R

JTAG_TRSTB JTAG_TDI JTAG_TCK JTAG_TMS JTAG_TDO

1

@

TESTEN

1 2 1 2 1 2

1 2

XTALIN XTALOUT

XO_IN XO_IN2

GPU_DPLUS

1

GPU_DMINUS

1

GPIO_28_FDO +TSVDD

1

CV21

2

PX@

1U_0402_6.3V6K

TOPAZ@ TOPAZ@ TOPAZ@

UV1B

N9

DBG_DATA16

L9

DBG_DATA15

AE9

DBG_DATA14

Y11

DBG_DATA13

AE8

DBG_DATA12

AD9

DBG_DATA11

AC10

DBG_DATA10

AD7

DBG_DATA9

AC8

DBG_DATA8

AC7

DBG_DATA7

AB9

DBG_DATA6

AB8

DBG_DATA5

AB7

DBG_DATA4

AB4

DBG_DATA3

AB2

DBG_DATA2

Y8

DBG_DATA1

Y7

DBG_DATA0

W6

NC#W6

V6

NC#V6

AC6

NC#AC6

AC5

NC#AC5

AA5

NC#AA5

AA6

NC#AA6

U1

NC#U1

W1

NC#W1

U3

NC#U3

Y6

NC#Y6

AA1

NC#AA1

R1

SCL

R3

SDA

U6

GPIO_0

U10

NC_GPIO_1

T10

NC_GPIO_2

U8

SMBDATA

U7

SMBCLK

T9

GPIO_5_AC_BATT

T8

GPIO_6

T7

NC_GPIO_7

P10

GPIO_8_ROMSO

P4

GPIO_9_ROMSI

P2

GPIO_10_ROMSCK

N6

NC_GPIO_11

N5

NC_GPIO_12

N3

NC_GPIO_13

Y9

NC_GPIO_14

N1

GPIO_15_PWRCNTL_0

M4

GPIO_16

R6

GPIO_17_THERMAL_INT

W10

NC_GPIO_18

M2

GPIO_19_CTF

P8

GPIO_20_PWRCNTL_1

P7

GPIO_21

N8

GPIO_22_ROMCSB

AK10

GPIO_29

AM10

GPIO_30

N7

CLKREQB

L6

JTAG_TRSTB

L5

JTAG_TDI

L3

JTAG_TCK

L1

JTAG_TMS

K4

JTAG_TDO

K7

TESTEN

AF24

NC#AF24

AB13

RV1120_0402_5%

NC_GENERICA

W8

NC_GENERICB

W9

RV1130_0402_5%

NC_GENERICC

W7

NC_GENERICD

AD10

RV1140_0402_5%

NC_GENERICE_HPD4

AJ9

NC#AJ9

AL9

DBG_CNTL0

AC14

NC_HPD1

AB16

PX_EN

RV544.7K_0402_5% @

AC16

NC_DBG_VREFG

AM28

XTALIN

AK28

XTALOUT

AC22

XO_IN

AB22

XO_IN2

SEYMOUR/FutureASIC

T4

DPLUS

T2

DMINUS

R5

GPIO28_FDO

AD17

TSVDD

AC17

TSVSS

S IC 216-0867-071 A0 FCBGA 631P GPU 12

EXO@

I2C

PLL/CLOCK

DVO

GENERAL PURP OSE I/O

THERMAL

DPA

NC#AM3

NC#AM5

DPB

DPC

NC_AVSSN#AK26

NC_AVSSN#AJ25

NC_AVSSN#AG25

DAC1

NC_HSYNC NC_VSYNC

NC_RSET NC_AVDD

NC_AVSSQ

NC_VDD1DI

NC_VSS1DI

FutureASIC/SEYMOUR/PARK

NC_SVI2#AK12 NC_SVI2#AL11 NC_SVI2#AJ11

NC_GENLK_CLK

NC_GENLK_VSYNC

NC_SWAPLOCKA NC_SWAPLOCKB

DDC/AUX

NC_DDC1CLK

NC_DDC1DATA

NC_AUX1P NC_AUX1N

NC_DDC2CLK

NC_DDC2DATA

NC_AUX2P NC_AUX2N

NC#AD20 NC#AC20

NC#AE16 NC#AD16

NC_DDCVGACLK

NC_DDCVGADATA

NC#AF2 NC#AF4

NC#AG3 NC#AG5

NC#AH3 NC#AH1

NC#AK3 NC#AK1

NC#AK5

NC#AK6

NC#AJ7 NC#AH6

NC#AK8 NC#AL7

NC#V4 NC#U5

NC#W3

NC#V2 NC#Y4

NC#W5

NC#AA3

NC#Y2 NC#J8

CEC_1

AF2 AF4

AG3 AG5

AH3 AH1

AK3 AK1

AK5 AM3

AK6 AM5

AJ7 AH6

AK8 AL7

V4 U5

W3 V2

Y4 W5

AA3 Y2

J8

AM26

NC_R

AK26 AL25

NC_G

AJ25 AH24

NC_B

AG25 AH26

AJ27

AD22 AG24

AE22 AE23

AD23

AM12

AK12 AL11 AJ11

AL13 AJ13

AG13 AH12

AC19

PS_0

AD19

PS_1

AE17

PS_2

AE20

PS_3

AE19

TS_A

AE6 AE5

AD2 AD4

AC11 AC13

AD13 AD11

AD20 AC20

AE16 AD16

AC1 AC3

3

VGA_VSSI_SEN

1

PLL_ANALOG_OUT

DIECRACKMON

1 2

PulldownfornoneOBFF design

CEC_1

1

GPU_SVD_R

RV110 0_0402_5%TOPAZ@

GPU_SVT_R

RV109 0_0402_5%TOPAZ@

GPU_SVC_R

RV111 0_0402_5%TOPAZ@

GENLK_CLK

1

GENLK_VSYNC

1

PS_0 PS_1 PS_2 PS_3

1 2

RV115 0_0402_5%TOPAZ@

1 2

RV116 0_0402_5%

TOPAZ@

VGA_VSS_SEN_R VGA_CORE_SEN_R

RV242 0_0402_5%@

RV243 0_0402_5%@

TV10 PAD@

1 2

RV94

@

16.2K_0402_1%

ReserveforTo pa z

TOPAZ@

1 2

RV120

10K_0402_5%

RV224.7K_0402_5% TOPAZ@

TV5

@

PAD

1 2 1 2 1 2

TV1 PAD@ TV2 PAD@

+VGA_CORE

1 2

RV125 0_0402_5%TOPAZ@

1 2

RV126 0_0402_5%

TOPAZ@

For Topaz, RV16/RV19 stuff 100ohm for EXO, RV16/RV19 stuff 0hm.

12

+VGA_CORE

RV24

0_0402_5%

EXO@

RV23

0_0402_5%

EXO@

GPU_SVD 49 GPU_SVT 49 GPU_SVC 49

VGA_VSS_SEN 49 VGA_CORE_SEN 49

WRST# 36

APU_SHUTDOWN# 7

2

CONFIGURATION STRAPS

ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET

MLPS Bit

Strap Name

PS_0[1]

ROM_CONFIG[0]

PS_0[2]

ROM_CONFIG[1]

PS_0[3]

ROM_CONFIG[2]

PS_0[4] N/A Reserved for internal use only. Must be 1 at reset. 1

AUD_PORT_CONN_ PINSTRAP[0]

PS_0[5]

PS_1[1]

STRAP_BIF_GEN3_EN_A

PS_1[2]

STRAP_BIF_CLK_ PM_EN

PS_1[3]

STRAP_TX_CFG_DRV _ FULL_SWING

PS_1[4]

PS_1[5]

STRAP_TX_DEEMPH_EN PS_2[1] PS_2[2]

PS_2[3]

STRAP_BIOS_ROM_ EN

PS_2[4]

STRAP_BIF_VGA_DIS

PS_2[5] N/A Reserv ed 1

PS_3[1]

BOARD_CONFIG[ 0]

PS_3[2]

BOARD_CONFIG[ 1]

PS_3[3]

BOARD_CONFIG[ 2]

AUD_PORT_CONN_ PINSTRAP[1]

PS_3[4]

AUD_PORT_CONN_

PS_3[5]

PINSTRAP[2]

Define the ROM type when STRAP_BIOS_ROM_EN = 1, Define the primary memory-aperture si ze when STRAP_BIOS_ROM_EN = 0.

The LSB (least significant bit) of the strap option that indicates the number of audio-capable display outputs.

1 = PCIe GEN3 is supported. 0 = PCIe GEN3 is not supported.

0 = The CLKREQB power management capability is disabled 1 = The CLKREQB power management capabi lity is enabled

N/A

Reserved for internal use only. Must be 0 at reset. 0 = The transmitter half- swing is enabled

1 = The transmitter full-sw ing is enabled 0 = Tx deemphasis disabled.

1 = Tx deemphasis enabled. Reserved.

N/A

Reserved.

N/A

0 = Disable the external BIOS ROM device. 1 = Enable the external BIOS ROM device.

0 = VGA controller capacity enabled. 1 = The device will not b e recognized as the system’ s V GA controller.

Board configuration related strapping, such as for memory ID

100 = Hynix 1G 111 = Micron 1G 110 = Samsung 1G

Determines the maximum number of digital display audio endpoints that will be presented to the OS and user.(Combine with PS_0[5]) 111 = No usable endpoints. 110 = One usable endpoint. 101 = Two usable endpoints. 100 = Three usable endpoints. 011 = Four usable endpoints. 010 = Five usable endpoints. 001 = Six usable endpoints. 000 = All endpoints are usable.

+1.8VGS +1.8VGS

12

RV71

8.45K_0402_1%

PX@

PS_0

12

1

CV15

RV77

2K_0402_1%

PS_2

4.75K_0402_1%

MLPS

PS_0[5:1] PS_1[5:1] PS_2[5:1] PS_3[5:1]

with BOM strcture control, RV63,RV70 change to different value to adjust VRAM config

with BOM strcture control, when config PEG3 RV74 change to 8.45K, RV80 change to 2K

SVC SVD

00

0

1

0

1

.01U_0402_16V7-K

@

PX@

2

+1.8VGS +1.8VGS

12

RV60 10K_0402_5%

@

12

1

CV18

RV69

.01U_0402_16V7-K

@

PX@

2

Bit 54321 11 11 11 11

XXX

Capacitor Value (nF)

680 82 10 NC

Output Voltage (V)

1.1

1.0

0.9

0.8

GPU_SVD GPU_SVC GPU_SVT

000 = Hynix 2G 010 = Micron 2G 001 = Samsung 2G

001 00001

1

RECOMMENDED SETTINGS 0= DO NOT INSTALL RESISTOR 1 = INSTALL 10K RESISTOR X = DESIGN DEPENDANT NA = NOT APPLICABLE

Description

001 = 256MB

1= Not support

1= Enable

0= Disable

111= No usable endpoints.

12

RV74

8.45K_0402_1%

PX@

PS_1

12

RV80

2K_0402_1%

PX@

12

RV63

8.45K_0402_1%

@

PS_3

12

RV70

2K_0402_1%

@

BOM R_pd( )　C(nF)

R_pu( ) RV71=8.45k RV77=2K CV15=NC RV74=NC RV77=4.75K CV16=NC

0

RV60=NC RV69=4.75K CV18=NC RV63=X76 RV70=X76 CV19=X76

R_pu (Ω )

R_pd (Ω )

NC 8450 4530 6980 4530

Bits [5:4]

00

3240 3400

01

4750

10 11

Note: 0402 1% resistors are required.

1 2

+1.8VGS

RV234

RV203

1 2

0_0402_5%

1 2

0_0402_5%

RV205 10K_0402_5%

@

RV206 10K_0402_5%

PX@

RV204 10K_0402_5%

PX@

1 2

RV207 10K_0402_5%

@

1 2

EXO@

TOPAZ@

RECOMMENDED SETTINGS

1

CV16 .01U_0402_16V7-K

@

2

1

CV19 .01U_0402_16V7-K

@

2

4750 2000 2000 4990 4990 5620 10000 NC

+VDDIO_GPU+3VGS

1 2

X

1

X

0 0

1

X

0 0

X

1

X

11

Bits [3:1]

000 001 010 011 100 101 110 111

RV209 10K_0402_5%

@

RV210 10K_0402_5%

@

GPU_RST#

GPU_RST#15

A A

5

GPIO_19_CTF

21

SDM10U45LP-7_DFN1006-2-2

1 2

@

47K_0402_5%

4

RV132

DV2

RV128

12

RV131 1K_0402_5%

@

1 2

@

2.2K_0402_5%

C

QV13

2

MMBT3904WH_SOT323-3

B

@

0.1U_0201_6.3V6-K

E

3 1

1

CV215

2

Security Classification

Issued Date

THIS SHEET OF ENG INEERING DRAWIN G IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENG INEERING DRAWIN G IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2013/08/08

LC Future Center Secret Data

InternalVGA Thermal Sensor

VGA_SMB_CLK

VGA_SMB_DATA

Deciphered Date

2

47K_0402_5%

2013/08/05

RV43

PX@

+3VGS

12

RV44 47K_0402_5%

PX@

QV4A 2N7002KDWH_SOT363-6

+3VGS

G

2

S

61

PX@

D

G

5

S

QV4B

2N7002KDWH_SOT363-6

Title

ATI_JET-LE_Main_MSIC

Size

Document Number Rev

Custom

Tuesday, April 12, 2016

Date: Sheet

34

D

PX@

CG516

1

EC_SMB_CK2 6,30,36

EC_SMB_DA2 6,30,36

16 51

1.0

of

LCFC CG516 schematics

Specifications and Main Features

Frequently Asked Questions

User Manual