L-Card E20-10, E20-10-1, E20-10-D, E20-10-D-1-I, E20-10-D-1 User Manual

A family of universal modules of the ADC, DAC

Measuring voltage converters

E20-10
E20-10-1
E20-10-D
E20-10-D-1
E20-10-D-I
E20-10-D-1-I

User manual

Revision 2.01.00

October 2017

http://en.lcard.ru

[e-mail]

DAQ SYSTEMS DESIGN, MANUFACTURING & DISTRIBUTION

Author of the manual:

A.V. Garmanov

L-CARD LLC

117105, Mosc ow , Varsha vskoye shosse, 5, block 4, bld. 2
tel.: [phone]

fax: [phone]

Internet contacts:

http://en.lcard.ru

E-Mail:

Sales department: [e-mail]
Tec hn ica l sup port: [e-mail]

E20-10 module © Copyright 2005-2017, L-Card LLC. All rights reserved.

Manual

Date

Notes to the updates

1.00.02 –

1.00.07

05-2006 -
05-2007

Guidelines on E20-10 revision А release of which was
completed in late 2007.

2.00.01

04-2008

The m anua l is significantly amended, updated due to addition

2.00.02

04-2008

Table in p. 7.3 is updated, p. 3.3.4 is added, table 5-5 is
updated, er ror is corrected in table 6-3

2.00.03

09-2008

FPGA (p. 3.3.4) firmware upgrade details are updated.

2.00.04

10-2008

Explanatory figure is added in p. 4.4.

2.00.05

10-2008

FPGA (p. 3.3.4) firmware upgrade details are updated.

2.00.06

04-2009

E20-10 (p. 3.3.2)design versions designation system is
changed and amended

2.00.07

12-2009

Paragraph 6.5.4.3 ha s new ver si on

2.00.08

06-2010

Paragraph updated 7.1.3

2.00.09

07-2010

Paragraph 6.3 edited

2.00.10

06-2011

P.5.2.2 edite d. Paragraph 6.5.1 added

2.00.11

03-2012

Man or c hang e s in do cumen t a tion

2.00.12

09-2012

ADC frame is oversi zed up t o 8192 s amples!

inpu t is un c onnected

2.00.13

11-2012

Details are added to p. 3.3.4

2.00.14

02-2013

Details on revision B.01 are entered. (p. 2.1)

2.00.15

03-2013

Paragraph 2.1 edited

2.00.16

01-2014

Paragraph 6.5.1 edited

2.00.17

02-2014

table 6-7, p. 7.4, p. 6.5.1 are updated

2.00.18

12-2014

Details on new fi rmware 2.00.10, p. 3.3.4 are adde d

2.01.00

10-2017

Industrial design versions are added

Revision history of this document

revision

of num erou s de ta i l s o n E20-10 revision В.

Characteristic is added to Table 7.1 : Zero offs et when AD C

The characteristics according to the results
preparation of L-CARD Vol tage measu rin g converter series for
certification as Means of Measurement

The latest re vision of this document is always be ing reco rded on the CD-ROM incl uded in

the del ivery p ac ka ge (p. 3.3). B e si de s , you can find the latest revision in the library of files on our
website http://en.lcard.ru/download

.

Contents

1. What this document is about ................................................................................................................ 6

1.1. On revisions А, B and В.01 of moduleE20-10........................................................................... 6

1.2. Desi gna tion s ystem....................................................................................................................... 7

1.3. Design versi ons ............................................................................................................................. 7

1.4. How to read this manual?............................................................................................................. 8

2. Primary application properties ............................................................................................................. 9

2.1. Complete list of user differences of revisions А, В and B.01 for E20-10 module ................ 11

3. Gene ral description ............................................................................................................................. 14

3.1. Device applicat ion ...................................................................................................................... 14

3.2. Appearance ................................................................................................................................. 14

3.3. Module configuration ................................................................................................................. 16

3.3.1. Standard supply package ................................................................................................... 16

3.3.2. Design versi ons .................................................................................................................. 16

3.3.3. Software delivery ............................................................................................................... 17

3.3.3.1. Operational software ...................................................................................................... 17

3.3.3.2. Libra ry Lus ba p i .............................................................................................................. 17

3.3.3.3. LComp library ................................................................................................................ 17

3.3.3.4. Opti o nal so ft ware ........................................................................................................... 18

3.3.4. FPGA firmware versions ................................................................................................... 18

4. Install ation and customization ........................................................................................................... 20

4.1. Module connecting to computer ................................................................................................ 20

4.2. USB drivers installation ............................................................................................................. 20

4.2.1. USB drivers installation from Lusbapi ............................................................................. 20

4.2.2. USB drivers installation from LComp .............................................................................. 20

4.3. Recognition of the module ......................................................................................................... 21

4.4. Differences in USB driver of Lusbapi library .......................................................................... 22

5. Overview of the hardware components and operation principles ................................................... 25

5.1. Block diagram ............................................................................................................................. 25

5.2. E20-10 operating principle. ....................................................................................................... 28

5.2.1. Chan n el sampli ng principle ............................................................................................... 29

5.2.2. Synchronization in E20-10 ................................................................................................ 30

5.2.2.1. Synchronization modes.................................................................................................. 32

5.2.3. Data fo rm at of E20-10 ....................................................................................................... 37

5.2.3.1. Coding of word siz e ov er l oa ding si gn E20-10 or revision А ..................................... 37

5.2.3.2. Coding of data continuous area start in E20-10 of revision B .................................... 37

5.2.4. FIFO buffer and its overloading elim ina tion l o gic .......................................................... 38

5.2.5. Readings adjustment (calibration) .................................................................................... 38

5.2.6. ADC wor d s ize overflow w a rn ing .................................................................................... 38

5.2.7. DAC optional ..................................................................................................................... 39

6. Connection of signals ......................................................................................................................... 40

6.1. Gene ral Information ................................................................................................................... 40

6.2. External c on nect ors .................................................................................................................... 40

6.3. Analog sig na l conn e ct ors ............................................................................................................. 1

6.3.1. Digita l signa l an d e xterna l po w er conn e ct ors .................................................................. 43

6.4. Characte ristic s o f s ig na l line inpu ts and outputs ...................................................................... 45

6.4.1. Operating mode .................................................................................................................. 45

6.4.2. Power-off mode .................................................................................................................. 46

E20-10 User Manual

Limiting through currents .................................................................................................. 47

6.4.3.

6.4.4. External power supply input characteristic ...................................................................... 47

6.4.5. External p ower supply ou t pu ts char a c teristic ................................................................... 48

6.5. Spe cification and connection examples .................................................................................... 49

6.5.1. Connections to USB ........................................................................................................... 49

6.5.2. Multimodule connections .................................................................................................. 50

6.5.3. Circuits GND, GND* and AGND .................................................................................... 51

6.5.4. ADC input connecting ....................................................................................................... 52

6.5.4.1. Intrinsic input current of ADC analog input ................................................................ 52

6.5.4.2. Connecting to high-resistance output and alternate current output ............................ 52

6.5.4.3. On sta nda rd fe el er o s cillographic gauge connectivity ................................................ 53

6.5.4.4. On ef fe ct o f throug h cu r rent s on si gna l-to-noise ratio................................................. 53

6.5.4.5. How can you find out tha t t h e through-currents degrade the signal-to-noise ratio in

your c o nnecti on diagra m? ............................................................................................................. 54

6.5.4.6. How to solve the problem if the through currents are detected? ................................ 54

6.5.4.7. On disconnected ADC inputs ........................................................................................ 54

6.5.1. Dig it a l lines an d s ynch ron ization lines connecting.......................................................... 54

7. Specifications ...................................................................................................................................... 56

7.1. ADC............................................................................................................................................. 56

7.1.1. E20-10, E20-10-I, E20-10-D-I: limits of the pe rmissible relativ e basic error of

measuring the ac volt a ge .................................................................................................................... 58

7.1.2. E20-10-1, E20-10-1-I, E20 -10-D-1-I : limits of th e pe rmissible relativ e basic error of

measuring the ac volt a ge .................................................................................................................... 58

7.1.3. ADc synchr oniza ti o n s y st em ............................................................................................. 59

7.2. DAC............................................................................................................................................. 59

7.3. Digital lines ................................................................................................................................. 60

7.4. Power ........................................................................................................................................... 61

7.5. Physical properties ..................................................................................................................... 62

7.6. Oper ation conditions .................................................................................................................. 63

7.6.1. Nor ma l c onditi o n s .............................................................................................................. 63

7.6.2. Oper ating conditions .......................................................................................................... 63

8. Problems so lution under abnormal situations ................................................................................... 64

8.1. How to be consulted. .................................................................................................................. 65

9. Bibliography........................................................................................................................................ 66

List of tables. ............................................................................................................................................... 67

List of figure s. ............................................................................................................................................. 67

1. What this document is about

This documen t is a User Manual w ritten in a1 user-friendl y manner a s far a s po s s ible. It

describes the technical (hardware) properties of E20-10, explains the operation rules a nd princ iples
of functioning, contains specifications and contents of delivery.

This documen t does no t cover any programming or software issues . These iss ues are given

in progr amm er's ma nu a l [1].

So, You need two documents to operate with E20-10: user manual and programm er's

manual.

1.1. On revisions А, B and В.01 of module E20-10.

Rapidly de v elopin g pres en t element base a nd technol ogies and long-term experience in

ser ial production of E20-10, many user stories are causes of s ign ificant redesigning of project E20-
10: to add a significant number of additional useful functions and properties saving compatibility
with previous functions as m uch a s possib le keep ing the same va lue category for data acquisit ion
devices. Revision B is assigned to new E20-10 and its manufacturing has started with 2008.
Revision А executed before the end of 2007 of E20-10 module is taken out of production but, of
cour s e, i s b ei ng supported by L-Card, and its des cr ipt ion is given in th is manual. E20-10 of

revision В– it is a technologically new device, so, next observe that any changes in E20-10 revision
А into revision В are impossible.

In 2013 L-Card issued new revision B.01 di f f er e nt fr o m older ones in signi fi ca ntly exten de d

power voltage range, see p. 7.4, pag e 61.

Complete list of А, В and В.01 revision differences can be found in p. 2.1 of this manual.

Unless otherwise specified, throughout the text of this manual when it comes to

revision B the same informa t ion relates to revision B.01 as well.

In 2017 the certification of modules of L-CARD series including E20-10 modules as of

industrial versions was started.

Characteristics of revision B.01 gi ven in thi s manual comp ly with L -CARD-E20-10

characteristics.

1

but not according to GOST

E20-10 User Manual

E20-

10-

-

-

Модификация

преобразователя

1

Полоса частот
пропускания

5 МГц

D

ЦАП (2 канала)
присутствует

ЦАП
отсутствует

Преобразователи напряж ения

измерительные

I

+5

…

+

55

°

С

-40

…

+60

°

С

С лакировкой

Нет
индекса

Нет
индекса

D

Нет
индекса

1

Полоса частот
пропускания 1,2 МГц

Converter

modification

There is a DAC (2
channels)

With polish

DAC
no

No
index D

No
index

No
index 1

Measur ing volt a ge

converters

Bandwidth
of 5 MHz

Bandwidth
of 1.2 MHz

1.2. Designation system

1.3. Design versions

• E20-10 (ADC frequency bandwidth of 1.2 MHz, 2-channel DAC is not available).

• E20-10-D (ADC frequency bandwidth of 1.2 MHz, 2-channel DAC is available).

• E20-10-1 (ADC frequenc y bandwid th of 5 MHz, 2-channel DAC is not available).

• E20-10-D-1 (ADC frequency bandwidth of 5 MHz, 2-c hannel DAC is av ailab le) .

• E20-10-D-I (ADC frequency bandwidth of 1.2 MHz 2-channel DAC is available,

industria l design version ).

• E20-10-D-1-I (ADC frequency bandwidth of 5 MHz 2-channel DAC is available,

industria l design version ).

Industrial versio ns (with a lphabetic notation "I") designed to ope rate under
temperature from -40 to +60 °С have cards sealed with varnishing that improves the product
environmental res istance.

More detailed information on operational conditions see in Appendix 0.

1.4. How to read this manual?

Sket c hy infor ma tion o n pr imar y ap plicat i o n propertie s o f E20-10 is given in Chapter 2.

This chapter is targeted for wide range of stakeholders.

In Chapters 3, 0, 6 detail s relatin g to practi cal work it s elf wit h E20-10 are given. The

issues discussed herein will be of interest for specialists and operators.

Whe n ex ploratory r ea ding, Chapt er 5 can be missed because it describes internal

architect ure of mod ule E20-10 which is essential when closer looking.

In Chapter 0 the specifications for E20-10 are given. List if characteristics on E20-10 given

herein is intended for specialis ts.

In Chapter 8 practical information on problems sol ution under abnor mal situations is given.

E20-10 User Manual

2. Primary application properties

E20-10 — is a module o f hi g h-speed analog-digital conv er si on with USB 2.0 interface. The

product primar y ap plication proper t i es are su mm e d up belo w in s hort.

• Continuous 16-bit data acquisition with frequency up to 10 MHz is provided by USB2.0

2

interface

• 4-cha nn el arc hite ctur e w ith on e 14-bit ADC, switch, input buffer amplifiers, filters in each

channel.
impossible.

• Each o f ADC 4 cha nn el s ca n s et in softwar e th e f ollowi n g i npu t signa l sub-ranges

individ ually per cha nnel: ±3.0V, ±1.0V, ±0.3V.

• Each channel has LPF (l ow pass filter ) 3-ord er with fr eq uen c y cut-off of 1.25 MHz

(optimal bandwidt h f or 4 -channel ADC conversion mode and frequency is 10 MHz)
improvin g si gnal -noise-rate. Other LPF frequency cut-offs a re possible (p. 3.3.2).

.

Due to input buffer amplifiers the dynamic switching interference eff ect is

• ADC conversi on frequenc y F

can be s et wi t hin the range from 1. 00 to 10.0 MHz. ADC

ADC

conversion frequency can be both as set in software, frequency spectrum in megahertz is
determi n ed from the f ormu la F

= 30/к, where к = {3,4, 5, ..., 30}, and as external with

ADC

any frequency of from 1.00 to 10.0 MHz (lower data acquisition frequency can be
reached by interframe delay setting).

• Maximum data acquisition fr equenc y p er c ha n nel is F

,/п, where п = {1,2,3,4} —

ADC

number of sampled channels.

• In module control table the frame — ran dom s equen c e of channel sampling with length of

from 1 to 256 can be programmed. Size of sampled channels will be selected cyclically
from the set size table and order of output data samples E20-10 will comply with
cha n n e ls sequence.

3

• Inte r frame ADC sampl ing delay can be programmed from 0 to 65535

of ADC conve r s ion

frequency periods . Due to this the lower sampling frequencies can be implemented per

channel.

• Multi-mod e syste m has advance d s y nc hronizati on mode s f or da t a a cqu isition an d/or ADC

conversi on frequenc y. F or e xa m ple, by c onnecting modules E20-10 according to one
setting devi ce - many receivers diagram the synchronous multi-mo du le data a cqu isition
sy st em can b e achieve d!

• Architecture external ly completely downloaded: downloaded FPGA

, controller firmware

can be updated. Due to this the use r can update firmwares with latest versions by himself.

• FIFO data internal buffer with size of 8 MV bu f f ers da t a sav i ng their lo s s i n case when

4

computer operating system "thinks"

(to 400 ms at an acquisition frequency of 10 MHz to

4 s at an acquisition f requency of 1 MHz).

• Digital input-output i s prese nted in form of 16 input and 16 output dig ital TTL-compatible

lines. Digital outputs can be optional translated in the third state.

• Two-channel 12-bit DAC (option) allows to set constant voltage within ±5 V under

asynchronous mode operation.

• External device power supply outp ut ±12 V, 35 mA

2

Under full-speed (USB1.1) mode the maximum available frequency makes 500 kHz

3

In E20-10 revision B

4

for example, in Windows – in non-real-time (off-line) system

• Power supply of E20-10 from external unr e gulate d source is +8V...+40 V5 (po w er supply

circuit fro m USB i s n ot u sed). It can b e netw or k card o f -220/=12 V (in cluded in the
delivery.). Under off-line conditions E20-10 can be energiz ed fro m ex t er na l power sup pl y
sourc e of from +9 to +27 V. Power consumptio n — max. 4.5 W
E20-10 module has ex t ended supply voltage range f rom +8 to + 40 V .

In addition, revision В forE20-10 module in comparison with revision A has a number of

improved parameters and optional capabilities listed below (p. 2.1).

5

for module revision B.01

6

In E20-10 revision B

6

. Revision B.01 f or

E20-10 User Manual

Characteristic, parameter, function,

property

E20-10 revision А

E20-10 of revisions B and B.01,

L-CARD-E20-10

Interframe delay range

0-255 ADC c onversion

0-65535 ADC conversion frequency

Power c onsumption

to 5 W

to 4.5 W

Typical signal -to-noise rat io

70 dB

73 dB

Minimum data ac q u isition rate

2.1. Complete list of user differences of revisions А, В

and B.01 for E20-10 module

Since 2008 L-Card has decided to release E20-10 of revision В with advanced useful

quality.

All E20-10 modules of 2006 and 2007 production years should be related to revision А (see

labe l on the bod y bottom), since 2008 L-Card has star te d t o pr o du c e E20-10 of revision В.

In 2013 L-Card has started to release revision B.01 with extended power voltage range.

Revisions B an d B.01 are not diffe red in program. Revision B.01 spec if ied on label on body bottom
face , new power volt age range "+8.0...+40 V" is specified on body to p cover.

E20-10 module has signed in 2017 as modification in L-CARD Measuring voltage converter

series.

All consumer diff erenc es of E20-10 of revisions А and В are given in Table:

Data calibration procedure...
(p.

5.2.5)

(p. 5.2.1)

(p. 7.4)
Power supply voltage

ADC i nput offset current software
di sconnecting capability (p.

Intrinsic input curre nt of ADC analog
input ( p.

(p. 7.1)

maximum interframe delay and ADC
conversi on f requency of 1 MHz (p.

7.1)

6.5.4.1)

at

7.1)

is performed on computer
(by imple me nting of the
relevant library function)

frequency periods

is performed inside E20-10 by
FPGA hardware.

periods

+9.0...+27 V +9.0...+27 V (revision B)

+8.0...+40 V (revision B.01)

no yes

-15...0 µA (typical value ­7 µA)

7.8 kb y t e/ s 30 byt e/s

10 nA (typical value ) , if input
current is not specially on

Input res istance of analog input min. 5 MOhm 10 MOhm ± 5%
Inter-channel i nterfere nce , not more

than (p.

- at constant volta ge

- at frequency of 1 kHz

- at frequency of 1 MHz
Operating current of output of +5V of

external devices power supply

7.1):

-50 dB

-70 dB

-60 dB
35 mA 35 mA (revision B)

-70 dB

-75 dB

-65 dB

100 mA (revision B.01)

Characteristic, parameter, function,

property

E20-10 revision А

E20-10 of revisions B and B.01,

L-CARD-E20-10

Synchroni zation start mode s for data

Marker mode of first fra me – logic

no

yes

restart is not required, because of the

Number of design versions

2 (fixed)

4

acquisition "ac cording to level" of
signal of selected physical channel

5.2.2)

(p.

ind icator of data continuous section

5.2.3.2)

(p.

no yes

Capability to set additional permit
conditions for ADC data recordi ng in
buffer memor y E20-10:

- "acc or ding to differ ential" signa l in
ADC selected channel,

- blockage of set number of frames
transmission from the beginning of data
acquisition ( p.

5.2.2)

Mode of hardware acquisition st opping
according set number of collect ed data
frames (p.

5.2.2)

On stop the data acquisition restart can
be started, for example, per external
sync-signal START. In practice this
capability allows to implement start­stop opera tion for seve r al data
acquisition st art modes

In initiating of internal memory
overflow 8 MV E20-10event
recognizable in hardware (computer­caused spooling by USB high dela y)
(p.

5.2.4)

no yes

no yes

data acquisition
mandatory compute r ­sourced restart is requi red

requir ed minimum number of data
frames will be automatically
(hard ware logic) deleted from buffer
memory of E20-10 to eliminate
overfl ow, and program-accessible
overfl ow indicator is activa ted.

ADC word size overflow indicator per
ADC channel (p.

5.2.6).

External minor constr uction features

15)

(page

Internal major construction feature s 2-storied construction

(p. 3.3.2)

Certificate of Means of Measurement No

7

In this case the references to product E20-10 of L-CARD LLC are required in Your system end user

documentation.

E20-10 User Manual

inserted in ADC data
flow (in relevant mod e
initiation)

BNC connectors (ADC
inputs) ha ve flanges with
4 screws

based on two boards

is not i nse r ted in ADC data flow and
raise s t he releva nt pr ogram event

BNC connectors (ADC i nputs)
without f langes have one nut
retaining

More reli ab l e 1-storied single-board
construc tion, in particul ar, easy-to­use E20-10 without body as built-in
ADC module in Your system

7

.

6 (for L-CARD-E20-10)

E20-10

- Not available L-CARD-

E20-10 (under certification)

As shown in table above, revision В of E20-10 module has better useful quality in variety of
significant par ameters in comparison wit h r ev ision А!

3. General description

This ch apter describes E20-10 device application, informs about required and optional

equipment, content of software package for CD-ROM as well as contains the start operation
instructions.

3.1. Device application

E20-10 is s mall-bodie d mu l t ifunct i onal m easuring modu l e connecte d to PC throug h U S B

2.0-i nt erface . Th e m odu le is intend e d f or rapid fl ow capture with ADC c onversion frequency of to
10 MHz.

Bas ic functions of E20-10:

• 4-channel ADC of 10 MHz with c hannel multiplexing , with buffered input, with advanced

functions of internal, external, multi-module synchronization

• digital asynchronous input-output

• 2-channel asynchronous DAC (option)

Fast E20-10 modul e i s comple m e nted wit h s o m e sl ower ADC USB -modules: E-154, E14-

140, E14-440 and is intend e d for creati ng multi-channel measuring analog data acquisition systems

as well as for digital control and mo nitor ing of externa l de vi c es state.

3.2. Appearance

Revisions А and В of E20-10 mod u le have minor e xterna l dif f erences (fig . 3 -1, fig. 3-2). In

addition, on factory label ( on the body bottom) of E20-10 module of revision А the production
years 2006 or 2007 are specified, and on label of revision В – 2008 o r later. Moreover, on the la bel
the design version of E20-10 module is specified in compli ance with agreed not ation (p. 3.3.2).

E20-10 User Manual

Fig. 3-1. E20-10 revision А

appearance

Fig. 3-2. E20-10 revision В

appearance

Appearances of E20-10 of revision B and B.01 are simil ar.
Details on revision B.01 are s pe cifie d on label on b ody bottom wall .
Power supply v oltage range is specified on body top cover.

Design version

Description

E20-10

Bas ic design version — without DAC, bandwidth of 1.25 MHz per
ADC channel

E20-10-D

2-channel DAC bandwidth of 1.25 MHz of each ADC channel. This
version was named as "E20-10D" in ol d notati on

E20-10-1

With out DAC, bandwidt h of 5 MHz of e ach ADC channel (des ign
version is available for revision В only)

E20-10-D-1

With 2-channe l DAC, bandwidth of 5 MHz of e ac h ADC ch annel
(design version is available for revision В only)

3.3. Module configuration

3.3.1. St anda rd su pply packag e

• module E20-10 (1 pcs.)

• com munication cable on USB 2.0 (1 pcs.) — А-В type, length of 1.3...2.0 m

• network card for E20-10 power s upply from alternate current network of 220 V, 50 Hz

• ma gnetic sweep cable of conne ctor (1pcs.) — DB-37M with housing DP-37P — for

digit a l s ignal cable termina t ing pro ducti on

• ma gnetic sweep cable of conne ctor (1pcs.) — DJK-10A — for extern power supply

circuit cable terminating production, if required, to energize E20-10 not from circuit of
220V through attached network card but from different source of +9...+27 V

• ma gnetic sweep cable of conne ctor (1pcs.) — MDN-9P — for production of magnetic

swee p cable to externa l device power supply outputs of ± 12 V and to DAC outputs.

• CD-ROM with documents and software.

Attention! DAC is not included in standard supply package (p.3.3.2).

If required, use hub stations, power units for them and auxiliary USB-cables. When dealing

with E20-10 the user mu s t bu y t hi s equ ipm ent by him s el f in t hird-party manufacturers. The same is
related to not included in delivery package intercon ne cting w ires, auxiliar y cable s , connectors and
terminals to connect sign al sources a nd arran ge network interface communications.

3.3.2. Des ign v ersi ons

E20-10 is produced in the following design versions:

Attention! Specify the required design version in ordering E20-10.

Design version is specified on factory l abe l on the bod y bottom.

Anot her ADC channel bandwidths are available as agreed upon with L-Card.

E20-10 User Manual

library including all sources, import libraries,

Designs on module programming examples across different

3.3.3. So ftware del ivery

3.3.3.1. Operational software

For historical reasons, L-Card LLC firm pr ov i d e cu r rentl y t w o librar i es for th e u ser t o

opera te wit h m odu le E20-10, as follows: Lusbapi and LComp. Both libraries are intended to
operate under Windows’98/2000/XP/Vista environments. Both Lusbapi, and LCo mp provide
complete functional support for module E20-10. LComp library benefit is wider support the
product p er fo r m e d b y L-Card LLC. So, Lusbapi supports USB devices only, and LComp library
provide additionally operation with ISA and PCI products of L-Card LLC.

Attention! Both libraries Lusbapi and LCo mp have programming interfaces incompatible

com plet el y bu t t h ey use the same universal USB driver named Ldevusbu.sys.

3.3.3.2. Library Lusbapi

The w hol e Lusbapi library package is located in accompanied to module branded CD-

ROM in base direct or y \USB\Lusbapi. The same libr a ry ca n be do w nload e d fr o m ou r w eb s ite

en.lcard.ru from the section " Fil e Li brary ". There, in subsection "Software for Windows" you

shou ld select t h e self -extracting archive lusbapiXY.exe, w h ere X.Y denotes the software current
version nu mber . At the time o f this manua l wr iti ng, th e late st Lusbapi libr ary has versi o n 3.2, and
its archive is named

The stru cture o f arr ange m en t on brande d CD-ROM of all Lusbapi library components is

given in table below (paths are specified relatively to base directory \USB\Lusbapi):

lusbapi34.exe.

Directory Intended pur po s e

\DLL\ Lusbapi

declaration modules and, etc.

\DRV\
\E20-10\DOC\ Doc umentatio n Inc luding prog rammer 's ma nual on o perat ion

\E20-10\Examples\

To provide Your applications proper operation with module E20-10 it is recommended to

copy binary file of \DLL\Bin\Lusbapi.dll library to directory %SystemRoot%\system32, tha t can
be im pl ement e d by us ing fin i sh e d ba tch fil e \DLL\CopyLusbapi.bat. This operation is often
applied because Windows’98/2000/XP/Vista, if required, searches aut omatically the require d
libraries in specified directory. On the other hand, Lusbapi.dll library can be conceptually loc ated
in dir e ctory o f ultimat e applica t i on or in one of the di rector ies spe cifie d in e nviro n m en t variable
PATH.

All user required components of Lusbapi library (include files, programming examples
and, etc.) are moved to target computer by copying of required directories and files from delivered
branded CD-ROM.

USB driver of module and inf-file.

with Lusbapi library.

development environments: Borland C++ 5.02, Borland C++
Builder 5.0, Delphi 6.0 and MS Visual C++ 6.0.

3.3.3.3. LComp library

LComp library is presented in form of installation tool LComp.exe, whi ch is lo ca t e d on
branded CD-ROM in directory \DLL\LComp. The same library can be downloaded from our

website en.lcard.ru from the section "File Library". There, in subsection "Software for Windows"
you should select self-ext r acting archive lcomp.exe.

Installat io n tool LComp.exe is intended for proper arrangement of all components of
LComp library on user's computer. Moreover, such required LComp components as so urces,
import libraries, decla r a t io n m odule s , pr o gr ammi ng exam ples, el e ct roni c do cu m e nt a tion a nd , et c.
will be located in dire c tory assigned by the user in librar y instal lation .

3.3.3.4. Optional software

• Free program L-Graph II. It is intended for operation on Windows'XP only. L-Graph II

opera tes with modu l e E20-10 through LComp library. This program is higher-end version
of L-Graph I. For example, it offers the possibility to user to view and record data fr o m
ADC sim u l t ane o usly. L-Graph II can be installed using installation tool
\LGraph2\setup.exe from bra nde d CD-ROM attached to the module. L-Graph II
distribution can be also downloaded from our website en.lcard.ru from the section

Library". There, from subsection "LGraph2 software package" you mus t s elect

distribution lgraph2.zip.

• Commercial program of multi-channel recorder PowerGraph. The program is i ntended to

record, process and hold analog signals and allows to use personal computer as tape
recorder. Windows'98/2000/XP/Vista. Developing, delivering and technical support –
"Interoptica-S "LLC , www.powergraph.ru
module E20-10 includes demo version PowerGraph located in directory \P_graph on
our branded CD-ROM.

. Standard software package delivered with

"File

• Comme r cial automation complex ACTest for experimental and process plants. This

comple x is intended to rea l-time view, record, store and process data.

Windows'98/2000/XP. Developing, delivering and technical support – "Automated
systems laboratory" LLC, www.actech.ru

module E20-10 includes demo version ACTest located in directory ACTest on our
branded CD-ROM.

. Sta ndard s o ft wa re pa ck a ge del ivered wit h

3.3.4. FP GA f irmwar e ve rsions

In E20-10 FPGA firmware version and creation date are programm-accessible [ 1]. The
current delivered FPGA firmware is integrated into delivered program library functions.
Conceptually, you can update E20-10 firmware by two ways: download upgraded software in

"Files library" or order FPGA firmware new file in L-Card ([e-mail]

initialization function E20-10. The last way is technically appropriate only if exchanged FPGA
firmwares are compatible on program library functions – th is and res t user inform ation about
available firmwares of E20-10 is given in ta ble below.

You ca n f ind out about ac tual FPGA fir m ware of Your module E20-10 using utility
ModulesViewer which can be downloaded from website L-Card from section Files library

) and use it in calling

.

E20-10 User Manual

rev.В are recommended to update firmware

Firmware

version

1.00.06

dd. 15.01.07.

2.00.03

dd. 10.04.08.

2.00.05

dd. 24.07.08.

2.00.06

dd. 01.09.08г.

Firmware descripti on

Final firmware E20-10 rev.А.

First firmware of serial E20-10 rev.В.
Users applying internal calibration in E20-10

to elder version where the effect to damage individual data sampl es in code approximating
to ADC word si ze edge has been eliminated . Negative ef fects have not be en found when
internal calibr ation is off.

Updated firmware of serial E20-10 rev.В.

In FPGA 2.00.05 firmware the add itional prog r am start is not required unde r
addi tional sta rtup condition "on

and shut down condition "on number of M re corded fra mes", due completing of the next
shutdown condition fulfillment the addi tional data acquisition start will begin
automaticall y upon completing of new start condition fulfillment. For anot her start

conditions

FPGA 2.00.05 firmwa re is simi lar to 2.00.03 firmware. Als o refer to

signal passing t hrough given level in selected channel"

table 5-5 notes to it.

FPGA 2.00.0 3 an d 2.00.0 5 fir mwares are f ully compatible on program library func tions.
Updated firmware of serial E20-10 rev.В.

One-channel mode sensitive data acquisition fault has been eliminated.

1.00.07

dd. 29.10.08.

2.00.07

dd. 05.09.12.

2.00.08

dd. 20.11.12.

2.00.10

dd. 15.12.14.

Updated firmware of serial E20-10 rev.A.
Data corruption in repetiti ve interleaving of external start and program shutdown has been

eliminated (this relates to rev.A only). FP GA 1.00.07 firmware means simultaneous
upgrad ing of AVR contr oller firmware .

For E20 -10 rev.В the embedded software upgrading enabling to boost maximum possible

frame size up to 8192 samples of ADC has been d eveloped ! To upgr ade it is required to

alter AVR controller and upgrade library re mot ely (FPGA 2.00.07 firmware has been yet
added in which). Compatibility with old software of upper level is existed.

Firmware for E20-10 rev.В. In comparison with version 2.00.07, the fault on odd data
interference in ADC buffer in additional data acquisition starti ng on si gnal START under
data acquisiti on pr ogr am shutdown mod e has been el iminated.

Firmware for E20-10 rev.В. Data acquisition restart on signal START fault has been
eliminated.

4. Ins t allation an d c u stomizat ion

4.1. Module connecting to computer

Inspe ct packa ge and p rod uct comp onents for mech an ical damage s. Switch on the computer
if it was off and download operating system Windows’98/2000/XP/Vista. These particular operating
systems are enabled to support adequate operation of USB interface.

USB i nt erface spec ificat i on provides us ers wit h op er a tiona l capabiliti es to wor k with
peripheral devices under t rue mode Plug&Play. This means that USB standard provides
device"hot" connection to live computer, its automated recognition by operating system
immediately upon connecting and next downloading of drivers relevant to this device. Moreover,
USB device can be disconnected from comp uter at any time. In addition, the computer c an be
swit c hed on if USB device has been p reviousl y connec ted.

Hardwared connecting of m odule E20-10 to computer is as follows: apply external power to
E20-10 by connecting ne twork car d included in delivery p ac kage, conne ct USB m odu le co nn e ctor

to computer USP port using cable incl uded in delivery package . All specific aspects to conne ct
signals are described in Ch.6, in particular, on connectin g to USB, ref er to p. 6.5.1.

Note that when operating with drivers L Comp you should download f irst the dr ivers 4.2.2
and conne ct E20-10 once this is done.

4.2. USB drivers installat ion

Procedures on USB drivers in stallation from l ibr a ries Lusbapi and LComp are a bit
different for E20-10 module. These particular differen ce s are described in the following two
paragraphs.

4.2.1. US B dri vers inst allat ion fr om Lu sbapi

Whe n very first connecting of E20-10 module to computer using included standard USB
cable the operating system should request driver files for first-time connected USB device. In this
case, it is required to specify inf-file fr om Lusbapi l ibr a ry fro m ou r branded CD-ROM:
\USB\Lusbapi\DRV\Lusbapi.inf. Whi le doing so the oper ating system copies itself all fil e s
requir ed for it to necessary slots and performs all necessary entries in its regist ry . Windows system
should su bs e qu e ntly perfor m s o cal led enumeration procedure of USB device, see description
below in p. 4.3 "Recognition of the module".

4.2.2. US B dri vers inst allat ion fr om L Comp

Prior to use module E20-10 with application of LComp li brary it i s re quired to perf orm
installa tio n tool LComp.exe located on branded CD-ROM in directory \DLL\LComp. In addition,
this tool ins talls to user target computer all nece s sary files required f or operating system duri ng
reco g ni tion m odu le E20-10 when it is firstly connec ted to computer USB port. Upon successful
completion of pr og r a m LComp.exe only you may connect module to computer using included
standard USB cable. W h ile doing so, Windows sy stem s ha l l p erform numeratio n procedure for USB
device, see description in the following paragraph of this manual.

E20-10 User Manual

4.3. Recognition of the module

As w as mentione d above , the opera ting system Windows shall perform numeration
procedure for eac h co n necte d USB de vi ce . Su c h proce du r e for USB devices is performed on-the-fly

when they are co nnected to computer without any user inter a c ting or cl ient sof tware.

During the executio n of numeration the module USB indicator – LED, located near to USB
connector E20-10, sha ll fla sh continu ousl y, and upon completi o n it s ha ll be red or gr ee n. This wil l
mean that connected USB device is recogn ized properly by operating system an d is ready for
further operation. Indicator's color informs about E20-10 co n n ecti o n s peed to int erfa ce USB

• red – full speed,

• green – high speed.

You can further check connected module validity of recognition by operating system in
"Device Manager" . There, in app eared s e ct ion "L-Card USB devices" device E20-10 will be
dis pla yed, a s it, for exampl e, is show n in figur e below:

8

:

In further working with module E20-10 the oper a ting system will a lready know the location
of driver for this type of the device and will load it automatically during product connecting to the
computer.

8

In E20-10 revision В the indicator is flashing when data transmitting on USB–it is a natural occurance.

4.4. Differences in USB driver of Lusbapi library

From the version 3.2 in Lusbapi library the primar y fil e of USB driver, now it is call ed
Ldevusbu.sys inst ead of ol d Ldevusb.sys. So, those users who has already installed on
computers USB drivers fr o m Lusbapi library of version 3.1 or la ter shall be ve ry attentive during
moving to ne w er li br a ry, becau s e he mu st chan ge module E20-10 to opera te wit h ne w USB drivers.
To do this the user must perform several standard actions using "Device Manager" .

Firstly, you may verify that mo dule E20-10 connected to the computer operates with old
USB driver Ldevusb.sys. To do this you sh ou ld find in "Device Manager" th e device of
module E20-10 type and consecutive call of panel with its features. Then, on this panel you should
move to bookm a rk "Driver" on which click on button " Driver Details…" . In this case the panel
with li st of all dr iver s e na bled for s el e cted d evi ce will ap pea r. In ou r ca se, dri v er Ldevusb.sys
shall be in this list. Th is m ean s, tha t to operat e with module E20-10 the USB drivers from Lusbapi
libra ry of version 3.1 or older are used.

To move to new USB driver (from Lusbapi library of version 3.2 or newer) you should
perf orm the followin g a ctions. Selec t in “Device Manager” the same moduleE20-10 mentioned in
previous paragraph and call pop-up men u us ing right clicking. The fo llowing picture must be as a
result of these actions:

E20-10 User Manual

Then, you should acti vate the driver upgrade point usin g left clicking. It should be noted
that depending on Windows configuratio n the information pane ls of type to alert abo ut failure of
driver digi ta l signature and propose to find drivers in Internet may be displayed. Then, you should
move to standard information panels “Hardware Update Wi z ard” on which you s h ould sp e ci f y
selection varian ts given on f igures below and click button “Next” :

Then, the following panel will appear on which you should just click the button “Have
Disk…” ().

In this case, in appeared dialogue box “Install From Disk ” you should s p ec if y inf-file
\USB\Lusbapi\DRV\Lusbapi.inf from our branded CD-ROM and click button“OK”. Upo n
completion, on return to previous panel you should click button “Next” :

Now, the only you need is to drive the nail home, in other words, you have to be reassured
by Windows tha t driv er s insta llation f or m odu le E20-10 is completed successfully and the device is
ready for further operation.

I n g enera l, to op er a te wi th E20-10 USB drivers bot h a s o f ol d ( v ersion 3.1 or older) as new
(version3.2 or ne w er) Lusbapi libraries can be simultaneously installed on computer. The thing is
USB driver from exactly which library would be selected by operating system during module
connecting to computer. Yo u ma y c lear up this sit ua tion and make a decis ion on used ( active) USB
driver by viewin g in “Device Manager” as it was m e ntione d in the be gi nning of this paragraph.
Using operational tools of “Device Manager” you can s wi t c h back an d f orth with reas o na ble
facility among both USB drivers, i.e. as you want you can make active these particular drivers
whi ch are r equ i red for curr en t operat i n g w ith modu le E20-10.

E20-10 User Manual

5. Overview of the hardwa re components

and operation principles

Firstly, th e description of hardw a re components which provides insig ht into E20-10
oper a tion principles is given in this c hap ter a nd detailin g of oper ational ch aracter istics is given
belo w . D e s cripti o n do es not cover low-level definition of hardware but it is quite s ufficient for
und er standi n g of product i mp ort ant perfor ma nce charact eristics.

5.1. Block diagram

Module E20-10 contains process nodes shown on diagram (fig. 5-1). Consider next
functional unit E20-10 according to this diagram.

Four identic al analog paths consist of in put offset current control ci rcuit, inp ut static
commutator, controlled amplifier, active LPF of 3-order.

Input offset cur rent contr ol circuit is available in revision В of module E20-10 only. In
revision A typical input offset current makes -7 µA ( in particular, th is curre nt cause d oversw ing to
ADC scale negative values under quiescent ADC analog input). This current was amplifier
component property applied in revis ion A. Amplifier with incomparably lower inp ut current may be
applied in revision B. But, due to the fact of input current existence of revision A could be used in
different propositions (for example, as signal external source connecting sign), that in revision B the
negative offset cur rent can be live on command (therewith, offset curre nt is gener ated artificially) to
be compatib le with old revisi on, but input offset current is dead by de fault in revision B (p.6.5.4.1).

Input static com mutator is designe d to enga g e m o d e f or measuring module E20-10 own zero
independently per ADC channel. Measuring of own zero prior data acquisition session and
program record-keeping of measured value may compensate long-term temperature and time ADC
zero drift. It should be noted, that this commutator is unappropriated for such zero compensation
"on-fly" (i.e., during data acquisition).

Controlled ampl ifier has 3 transfer ratios programmed individually for each ADC channel.
These transfer ratios implement input ADC subranges: ±3 V, ±1 В, ±0.3 V.

Active LPF in basic version has boundary frequency of 1.25 MHz (optimal for 4-channel

9

mode at maximum acquisition frequency), and another versions
frequencies are tec hnically possible (p. 3.3.2).

Signal from active LPF outputs of each channel enters to dynamic commutator pe r forming
swit c hing o f signal s wi th AD C c on v ersion fr eque nc y from four analog paths to ADC input.
Chan n el numbers switchin g s e qu e nce is ar bi t r a ri l y given in control li st.

Pipelined ADC — 14-bit high-frequency A DC of LTC2245 type of Linear Technology. This
ADC has two major features which have a direct effect on E20-10 archi tectur e: deeply pi p el ined
architect ure of this ADC, ADC conversion frequency r ange of from 1.0 to 10 MHz.

Data enters to FPGA from ADC output. In revision А E20-10, beside the above mentioned
mixi ng of ADC word siz e ov erloading fea ture the data flow is not furt her converted bec a us e
cali br a tion pr o c e du r e is impl e m en t e d h ere by up pe r-level tools (in comp u ter). To cal ibr ate flow of
10 megasamp les per seco nd (20 MB/s) "on-the-fly", especially if more than one module E20-10is

connect ed t o the computer, – is a reso urc e-intensive procedure even for modern computer, so,in
revision B of m odule E20-10 the data cal ibration procedure is imple m ented by FPGA tools.

9

this issue are to be arranged with L-CARD

of E20-10 with other boundary

In module of revision А the series Aceх FPGA is used, in revision B the more resource­intensive FPGA of series Cyc lon is used. These downloade d FPGA of Altera corporation perform
full range of fast-acting logic operations in E20-10. FPGA firmware is downloaded from the

10

computer t hroug h U SB at each program init ia l isin g o f E20-10

. L-Card does not rule out FPGA

firmware upgrading (see p. 3.3.4) due to updat ing of E20-10.

Microcontrol ler AV R AtMega162 of Atme l corp or a t ion ( hereafter - AVR)— this contr oll er
performs asynchronous programmable control of module (on upper-level commands), supporting
information interchange through USB , F PGA do wnl oadi n g an d c on t rol pro c edu re, st or i ng
cali br a tion factors and pr oduct serial nu mber.

In revision А E20-10 USB-controlle r ISP1581 is used – this is low-level USB controller
controlled from AVR. More advanced USB-controller ISP1583 is used in re vision B . Both these
controllers of NXP corporation support protocols of full- an d hig h-speed USB interface.

SDRAM -based FIFO buffer of 8 MV is us e d t o buffer ADC data fl o w. Such de pt h of the
buffer is quite sufficient for operating under any operating system at ADC maximum conversion

11

freq ue ncy of 10 MHz

. Contr ol logic o f SDRAM is impl e m ented in F PGA (detailed information

about FIFO s e e in p.5.2.4).

Two-channel asy nchronous DAC (option) is contr olled f rom AVR a s ynchr onou sl y o nl y
using control pipe of USB interface and by relevant function of upper level.

Digital input r egister D I1...DI16 strobe s 16 TTL-lines of data exactly parallel from digital
inpu t s, A VR r ea d s re gister cont e nt. Note , that D I16 line has program mable alternative func tion of
bi-directional acquisition signal START .

10

it is enough to download firmware once upon E20-10 energizing

11

without interframe delays and other settings slowing down data acquisition

E20-10 User Manual

FPGA

Статический
коммутатор

Вход 1

Управляемый

усилитель

Активный

ФНЧ

Канал 1

Канал 2

Канал 3

Канал 4

Вход 2

Вход 3

Вход 4

конвейер-

ное

АЦП

Буфер

FIFO

8 MB

USB

контрол-

лер

Преобра-

зователь

напряжения

Вход

+9...+27 В

Контрол-

лер

AVR

Цифровой

ввод-

вывод

ЦАП

2

канала

USB

DI1...DI15

Выходы ЦАП:

Выход

±12 В

DO1...DO16

TTL-линии:

DAC1

DAC2

SYNC

Динами-

ческий

коммутатор

DI16 / START

START

DI16

16

15

Логика

калибровки

и доп. условий

разрешения

записи (рев.В)

данные

синхрони-

зация

Управление
входным
током
смещения
(рев. В)

Конвейерный АЦП

Размер

кадра

Логика

калибровки

данных
(рев. В)

Логика

разрешения

записи в

буфер FIFO

Счётчик

задержки

записи

заданного

количества

кадров от

начала сбора

Логика

устранения

переполнения

(рев. В)

Счётчик

количества

собранных

кадров

данных

Логика управления

процессом сбора

данных

конвейерным АЦП

(триггер START)

Внешний старт от

перепада сигнала START

Программный старт-стоп

Старт-стоп от уровня

сигнала START (рев. В)

Стоп по количеству собранных кадров (рев.B)

Логика

разрешения

записи по

аналоговому

уровню и
переходу

через уровень

FIFO
8 MB

вход

выход

Дополнительные условия

разрешения записи в буфер FIFO (рев.В)

вход

выход

USB-

интерфейс

Указатель

на строку

управляющей

таблицы

Логика

управляющей

таблицы

управляющая

таблица

Входы АЦП

Аналоговые

каналы АЦП

Динамичечкий

коммутатор

Счётчик

межкадровой

задержки

Сигнал START в режиме "ведущий"

Input 1

Input 2

Input 3

Input 4

synchroniz

data

Input

offset
current
control

(rev. В)

Channel 2

Channel 1

Channel 3

Channel 4

Static

commutat or

Controlled

Active

LPF

converter

DAC

2 channels

Control-

Digital

input

FIFO

controller

Input

+9...+27 V

Output

±12 V

DAC outputs:

TTL-lines:

Logic of

and additional

(rev.B)

ADC anal og

channels

Dynamic

commutator

ADC inputs

Data

(rev. В )

Interframe

counter

control table

Logic on write

on analog level

Pipeli ned ADC

Size

frame

Data frame

Set frame

USB-

interface

Overflow

logic (rev. В)

input

input

output

output

Logic on write

buffer

FIFO

8 MV

FPGA

Pipelined

ADC

write enable

ation

calibration

conditions

ampli fier

buffer

8 MV

ler

AVR

USB

Voltage

Dynamic

commutator

-output

delay

Fig. 5-1. Block diagram E20-10

calibration

logic

enable

and transition

though the

level

enable

in FIFO

amount w ri ting

delay

from

acquisition

start counter

collected

amount
counter

elimination

Fig. 5-2. Explanation of data acquisition equipment logic interaction in E20-10

Digital output register DO1...D O 16 sets exactly parall el 16 -bit data on TT L-ou t pu ts for
programmable controllability of the third outputs state as well as for controllability of the third state
on signal EN_OE (table 6-2).

START acquisition start synchronization i nput-output. If digital line DI16 for input
asynchronous function is not active, then this digital line may be set in software to functions
"mas t er " ( ou tput) or " sla v e" (input) o f ST A RT signa l . These fea t u res can be used, for exampl e, for
multi-module synchronization of data acquisition start for several E20-10 according to diagram
"on e mast er – some slaves" (p. 5.2.2).

Digital input-output of ADC sync hr onizati on freque nc y SYN C can be used fro multi-module
synchronization of ADC conversion frequency synchronization of several E20-10 according to
diagram "one master – some slaves" (p. 5.2.2).

Voltage convert er converts unstable input voltage of +9V...+ 27V into stable power supply
voltages for internal nodes of E20-10. Auxiliar y volta ge o f ±12V is output from transm itter output
to ana lo g outpu ts connector of modu le E20-10 for ex ternal de vice powe r supply.

LED indic a tor (not shown on di agra m , ou t pu t to front panel of module) is controlled
directly from AVR. Connection conditions on US B and other events are signalized by mo de a nd
color of emission, details see in Programmer's manual [1].

5.2. E20-10 operating principle.

USB-module E20-10 does not use power supply circuit of USB 2.0 interface. To switch on
module it is re quired to apply power voltage of +9.0V...+27V to it

6.3.1) from network ca r d in cl uding in delivery packa ge (p. 3.3.1) or from ex t er na l c on s t a nt -voltage

sou r c e. Pow er supply cir cuit par am et ers for E20-10 see in p. 7.4.

Upon switching on the program of USB-device upgraded in AVR completes proced ure on
connecting on USB as soo n as computer conne c tion wi ll be detected.

Upon successful detecting of E20-10 by your computer operating system the
ready to oper a te on level of software app li cations using delivered by L-Card lib rary functions, in
particula r , one of these func tions is FP GA E20-10 downloading – this download is required to be
performed once upon as E20-10 switching on (see Programmer's manual [1]).

At the close of FPGA download from software level all information about this module E20-
10, in particular, serial number, module revision, AVR firmware v er sion, FPGA firmware version
will be available.

Prior to start data acquisition it is required to configurate it in software, because you m ay not
change conf iguration settings during data acquisition. Main configuration parameters are:

• ADC conversi on frequenc y (within the range of f rom 1.0 to 10 MHz).

• Data acquisit ion frame s ize: f r am e s ize, interf r am e delay duration Number of sampled

inpu t channel s ca n b e f le xible c on f igurated fr o m 1 to 4. ADC convers ion fr equenc y is
divided am ong sam pled channel s in a cc ordan c e wi t h t he ir qu a nt i t y an d sampling order
(frequency). The required sampling order of channe l s f orming th e fra m e i s pr e vi ously
recorded in co ntrol l ist with size of from 1 to 256 ADC paths, m. Whe n data acquisit ion
the numbers of channels are repeatedly read with given ADC conversion frequency
(1.. .10MHz) and are sent to dynamic comm utator as control s ign al. To achieve dat a
acquisition lower frequencies the interframe delay is programmed which allows to achieve
lower data acquisit ion frequencies . Under given nonzero interfram e delay upon
completion of contro l list access cycle (in frame completion) the relevant number of

12

On trigging E20-10 power supply voltage should be min. +9.5 V.

13

device driver installation is performed under first-time connecting (p.4.2)

12

through power connector (p.

13

module is

E20-10 User Manual

nonoperating periods of ADC conversion frequency is inserted; data on these periods are
deleted on hardware level and, due to this, traffic on USB is not overloaded with garbage.

• ADC conversi on frequenc y s ynchronizat ion mode (p. 5.2.2). To implement external and

multimodule synchronization mechanism of ADC conversion frequency you should use
configure d bi-directional TTL-signal SYNC (p. 6.3.1).

• Acquisition start mode (p. 5.2.2). To implement ext er nal, mul timo du le synchron ous star t

of data a cquisi t i on you can use con f igure d bi-directional TTL-signal START (p. 6.3.1).

• ADC channel input param e ters. It is noteworthy, that each channel individual installations

on required voltage input subrange, on input offset current as well as on own zero
measurement mode are not controlled in real time (synchronously) but they are controlled
st a ti cally and asynch ronously from AVR.

Main functional nodes engaged in data acquisition are shown in fig. 5-2. Note, that fairly
large number of new functional nodes implemented in revision B have not been available in
revision A (see verbal instructions of "Rev. В" on this figure).

In E20-10 of revision А "data acqui sit io n contr ol lo gi c" is start in g of "ADC —FIFO—USB-
interfac e" pipeline fr o m progra m sta r t e ve nt or fr om external START signal edge. In fact,

"START Trigger" indicates ADC start state (in combination with control list logic). In revision А

pipe line st op ping (START tri gger cl ea r ing) i s p er f ormed according to progr am pipe line st op ping
event only (followed by FIF O da ta clearing) an d logic o f wr ite ena bl e i n FI F O buffer is ac ti vated
fro m interframe d ela y mecha nis m onl y (i nterframe de l a y k e y po i nt is des cr ibed in p. 5.2.1).
Specifically, that START outpu t signal s tate under "master" mode is fully complies with "START
trigger" stat e.

In E20-10 of revision В the additional logic of write enable in FIFO buffer ( acquisition
sto pping ) whic h is dire ctly relating to da ta analysis a t AD C output is interstitia l dow n stream of
ADC pipeline but upstream of FIFO buffer: write enable on analog level, given amount of frames
fro m a cqu i s i tion sta rt w ri te delay cou nt er , c ol l ecte d frame s a mount cou nter. Al l t h e se ne w

functional nodes are involved in new synchronization mechanism of revision В (see description of

all synchronization modes in p. 5.2.2.1) , bu t , i t is impor t a nt to note , tha t th e s e m e chani s m s ar e
completely rela t e d n ot to ac quisition pi peline starting bu t t o o pe r a tion of wr i t e e na b l e to FI FO
buff er me c hani s m onl y agai n st ADC pre viou sl y tr i g g ered in co njunc tio n with "control li st logi c".

It follows, that "START trigger" as well as START sync signal under "master" mode
behavior logic is unrelated to "added logic of write enable in buffer". This feature will be essential
to the understanding of synchronization modes described below (p.5.2.2) w her e S TART sig nal i s
involved.

5.2.1. Ch annel sampl ing princ iple

In E20-10 acquisi tion fr ame size can be se t of from 1 to 256 (to 8192 ADC paths in FPGA
new fi rmware, p. 3.3.4). The following can be set: random sequence of channel numbers inside the
fr ame, specified in co ntrol lis t as well as interframe delay of from 0 to 255 AD C conversi on
freq ue ncy pe riods (fo r E20-10 of revisio n A ) or from 0 to 65535 ADC periods (for E20-10 of
revision B). T h e given size of co ntrol li st is always equa l to a c quisition frame si z e. Und er any
synchronization mode the data acquisition start is always bound to channel number specified on top
of control list and nonzero interframe de lay is always inse rted upon c ompleti on of last channel
number sampling at the bottom of control list of a given size. In any case, if data acquisition is not
stopped the next channel number will be taken from top of control list (and following the period of
frame given size from 1 to 256) upon completion of channel number sampling given in last string of
control list. Each period of ADC channel number periodic reading from control list as well as each
period of interframe delay counting are bou nd to given A D C c onver si on fre qu e n cy period of E20-
10 (from 1.0 to 10 MHz).

5.2.2. Syn chron izat ion i n E20-10

If synchro nizati on is not r e qu ired, t ha t i nt ernal ADC conver si on frequenc y s ou rce is use d i n
E20-10 as well as simple program data acquisition start. But, E20-10 has also exter nal
synchronization tools both as on ADC conversion frequency as on acquisition start. These are two
independent mechanisms which can be used both as separately and as together.

Synchronizati on on ADC c onve r sion fre quency (within possible range 1.0 – 10 MHz) is
performed using SYNC line which can be configured in software to output or to input (table 5-1).
Due to this the f ollowin g problems can be so lved:

• ADC conversion fr equenc y -based synchronization of several E20-10. To do this

you should switch on several E20-10 according to diagram "master-slaves"
connecting similar circuits GND and SYNC of several E20-10.

• Conversion frequency synchronization signal E20-10 generati n g t o e xterna l de vice,

for example, to frequency meter to monitor conversion frequency.

• External sync hroniza tion on TTL-s ignal (w ith freq ue ncy of 1. 0 – 10 MHz and on-

off time 2) for external synchronization of one or more E20-10 on ADC co nver sion
frequency.

The following problems m ay be s olved using acquisit ion start synchroni z ati on via START
line configured in software to input or to output (table 5-2):

• Transmitting of acquisition program start internal signal through START line for

synchrono us s tarting data acquisition in other modules E20-10. To do this, you
should swi t ch on s e veral E20-10 according to diagram "master-slaves " connecting
similar circuits GND and START of several E20-10

• E20-10 data acquisition start synchronization from external source of TTL -signal.

• Transmitting of acquisition program start internal signal in E20-10through ST ART

TTL-line to external d e vice for s ynchro nization or indica tion of data acquisi t io n
process.

Module E20-10 of revision "В" supports addit ional permit condi tions f or ADC data
recording in buf fer memor y of E20-10 (on edg e i n select e d ADC cha nnel, disabl i ng trans m issio n o f
given amount of frames from acquisition start), as well as additional conditions for acquisition
stopping (on data collected frames amount). In addition, "on level" data acquisition mode series is
added in revision B. These additional synchronization conditions improve synchronization tools of
module E20-10 of revis io n "B" in compar ison wi t h re vision "A".

The following limitation should be noted: addi tional c onditions for ADC data recording

and acquisiti on stopping permi t conditions can be applied inside o ne E20-10 module only and they
have no effe ct on STA RT si gnal behavior in inte r m odule sync hr onization ac c or ding to master­slaves principle. At the same ti m e, i f de s i red, in differ ent modu les E20-10 the similar auxiliary

conditions for data recording and acquisition stopping permit conditions may be made , and as a
result, under connecting "master-slaves " m odule s E20-10 on START signals you may achieve
conditions for synchronous operation of additional conditions for data and acquisi tion st opping
recording permi t condit ions in diff er en t m odu les E20-10 .

It is natural, that in multimodule connections of E20-10 on "master-slave" principle the user
must judiciously configurate control lists, interframe delays (and in E20-10 of revisio n B the
additional conditions for buffer write enable as well) of these modules in order to be able to make
sense of relative time connections among the sample flows obtained from these modules. Master
E20-10 should be earlier started in software to collect data, because they should enter in start
waiting from master, and in this case, upon slave data acquisition starting completion the data
acquisition in masters will b e sta r ted in ha rdwar e an d s yn c hronousl y wit h s lave E20-10.

It shou ld be not ed, that when SY N C line co n fi gu r a ting to fu n ction " slave" (u nder externa l
synchronization of ADC conversion frequency from digital TTL- sy nc signa l externa l s ource) it will

E20-10 User Manual

be incorrectly to feed SYNC pulses outside more rapidly than in 100 ns (10 MHz) or less often than
in 1000 ns (1.0 MHz), bec ause under this mode SYNC pulse is fed di rectly to ADC LTC2245, and,
according to manufacturer's documents, this ADC operates within conversion frequency range of
from 1.0 to 10 MHz. Severe require m e nts are also pose d on SYNC signal on-off time (p.7.1.3). It is
natural, that SYNC signal from "master" E20-10 complies wit h th ese requirements.

Note, that TTL-line D I16/STAR T configurated "on input" , electrically ha s pull-up resistor
(providing specific one state of unconnected input), and TTL-line SYNC configurated "on i nput"
does n ot ha v e pul l -up resistor, i. e. certainty of SYNC unconnected input state is not provided, table

6-2.

Synchronization

frequency

n

30

n

30

Implemented

E20-10

"software":

table 5-3

Software asynchronous start. S topping possible

"software – master on

table 5-3

START signal of maste r E20-10 is fed by active

5.2.2.1. Synchronization modes

Possible synchronization modes for E20-10 are given in tables below. Take note of
information about what exactly revisions of E20-10 one mode is implem e nted.

Table5-1. Modes of synchronization on ADC conversion frequency

(on SYNC signal)

on ADC

conversion

"internal" A, V

"internal-master" A, V SYNC li ne is configura ted to output: signal with on-off

"external - slave" A, V SYNC line is used "on input" for sync hr onization from

Implemented

in revisions

of E20-10

Notes

ADC conversion frequency:

where, n=3,4,5,…,29,30.
SYNC li ne is not used (transfered to Z-state)

time 2 and ADC conversion frequency is generated:

MHz, where, n=3,4,5,…,29,30.

ADC data physical sampling moment corresponds to
SYNC output signal ed ge

TTL-output of external device: signal with frequenc y of
from 1.0 to 10 MHz, wit h on-off time 2 (meander) is
required

MHz,

Table5-2. Acquisition start synchronization modes (on START signal)

Data acquisition start

synchronization

- without additional start
conditions

- with additional start
conditions,

START signal":

- without additional start
conditions

- with additional start
conditions.

in version

A, V

V

A, V

V

Notes

conditions – table 5-5
START lin e is in Z-state

level "1" (connected slave E20-10 shall be in "on
START signal edge " condition). Stopping possible
conditions –
START li ne is in "on output" state

table 5-5

E20-10 User Manual

Implemented

E20-10

"external - slave on START

table 5-3.

Sta rt on S TART signal

"external – slave on S TART

table 5-3.

Sta rt on S TART signal

"on level" data acquisition

5-3.

V On signal analog le vel in selected channel

Additional conditions

Implemented in

version E20-10

Notes

Blockage of give n N number of f r ames record ing
from the a cquisition start

B

0 ≤ N ≤ 16777214,
where, N-integral

On bott omup t ransiti on through the given signal level

frames recording fr om a cquisition start

B

0 ≤ N ≤ 16777214,

On top-down transiti on through the given signal level

frames recording fr om a cquisition start

B

0 ≤ N ≤ 16777214,

"on level" acquisition modes

Impleme

E20-10

Notes

"on signa l level above threshold of si gnal in 1 ADC cha nnel"

B

Stoppi ng will occur at

"on signa l level above threshold of si gnal in 2 ADC cha nnel"

B

"on signa l level above threshold of si gnal in 3 ADC cha nnel"

B

"on signa l level above threshold of si gnal in 4 ADC cha nnel"

B

"on signa l level below threshold of signal in 1 ADC channel"

B

"on signa l level below threshold of signal in 2 ADC channel"

B

"on signa l level below threshold of signal in 3 ADC channel"

B

"on signa l level below threshold of signal in 4 ADC channel"

B

Data acquisition start

synchronization

signal edge":

- without additional
conditions

- with additional start
conditions.

signal fall":

- without additional
conditions

- with additional start
conditions.

synchronizat ion modes, table

in version

A, V

V

A, V

V

Notes

Stoppi ng possible conditions -

table 5-5.

Possibl e stopping conditions see in table5-5.

Table 5-3. Capability to set additional permit conditions for ADC data recording in

buffer memory E20-10:

in sel ected channel and blockage of N number of

in sel ected channel and blockage of N number of

(acquisition start and s top is performed on si gnal

Table 5-4. "On level" synchronization modes

nted in

level)

revision

fram e end e dg e

where, N-integral

where, N-integral

Acquisition stopping conditions

Implemented in

version E20-10

Notes

Software asynchronous stopping

A, B

based on frame edges

On number M of recorded frames

implement start-stop acquisition mod e

B

0 ≤ M ≤ 16777215,

10

1

Table 5-5. Acquisition stopping conditions

acquisition restartable (see notes 1, 2) under
sett led start conditions, for example, to

where, M-integral

Note1:

In FPGA firmware of version 2.00.03 (details on firmware versions see in p. 3.3.4)
for restarti n g und er an y start condit ion it is re quired to ac tiv ate software restart on
upper software level (i.e. single start on condition is executed in practice). In FPGA

2.00.05 firmware th e a dditional prog r a m s tart is not required under addit ional star tup
condition

condition "on number of M r ecorded frames", due completing of the next stopping c ondition
fulfillment t he additional data acquisi tion start will begin aut omatically upon completi ng of
new start condition fulfillment (i.e. multiple start on conditi on in practice) . For another
start conditions

"on t r ansmission t hr ough given si gnal leve l in selected channel" and stopping

FPGA 2. 00.05 f irmware is similar to 2.00.03 firmwa re.

Note 2:

In future FPGA firmwares it is technically possible to implement software control of
single-multiple s tart modes (in the context of note 1) on any sp e ci fic star t c onditi o n
upo n st o pping "

mode i s re quired to solve Your problems.

on number M of record ed frames". Make an enquiry to L-Card, if suc h

Visual illu stration of E20-10 synchroniza tion modes is given in diagrams fig. 5-3. Frame
size equal to 4, inte rframe delay duration equal to 6 ADC conversion freque ncy pe riods are taken as
an example on diagrams; frame is configurated on sequence sampling of all 4 channels. Under such

configurations the data numeration frequency per ADC channel will make

given ADC

conversion frequency.

Common case fig. 5-3for applying all p o s si ble syn c hroniza tion c on di t i o n s ( ex c e pt "on
level" syn ch r o nization conditi o n s w hich ar e discus s e d individu ally) is show n on top diagram. In
E20-10 of revision A the software data acquisition start (or on START signal edge) was applied,
and upon start data were certainly recorded in FIFO buffer until data acqui sition software stopping
from upper level was sent (despite of frame edges). In E20-10 of revision В you may use the
configurations on additional recording conditions on signal edge, for example, as shown in diagram,
in ADC 3-rd channel. In thi s ca s e, frames will not fa ll in FIFO buffer (and, thu s , wi ll no t fa ll in
USB) till given additional condition will be fulfilled. As soon as the condition is fulfilled in the
current frame, the data be gi ning fr om the n ext frame will be fed into t h e FI F O an d ca n b e r ol l e d
back via USB. Blockage of transmission of given amount of frames starting from acquisition can be
sett le d i n re vi s i o n B ind i v idually or as th e s e c on d a dditi o na l co n dition.

Stopping based on given amount of frames collection is provided in revision B except for
asynchronous software acquisition stopping; furthermore, stopping edge will co m pl y with en d o f
last collected f r ame. In pr actice, this capability allows to carry out acquisition start-sto p op eration
und er pres el ec ted star t m od e (pay atte nt ion on not e s to table 5-5 on single and multi pl e start
capabilities).

As it was mentio ned in p. 5.2 and as shown in diagrams, START signal behavior does not
depend on addi tion al s tart conditions if it is configur ated "on output ("slave") .

Data acquis ition on signal level synchro nizati on mode (above or below give n threshold) in
select e d (on diagram - on 3-rd) phys ical ADC channel is shown on bottom diagram ( fig. 5-3) (in

E20-10 User Manual

rev. В only). Based on fig. 5-2, compa ring thresh old valu e will be perfor m e d wi t h cal i bra ted sampl e
value, because data calibration logic in E20-10 rev. В is ups tream of logic of permission fo r
recordin g i n FIFO bu ff er. Logi c o f th is sync hr o nizati o n mode i s bas e d on logic of permis si on f or
data recording in FIFO buffer, in addition, ADC functional node (in combination with control list
logic) is started in advance and ADc sample values analysis from the relevant physical channel of

E20-10 hardware is performed prior data recording in FIFO buffer. E20-10 will stay in waiting
condition until preset re cording c ondit ion are not f ulfilled (table 5-4). Upon fulfilling of recording

conditio n in cu r rent frame FIFO buffer will begin to fill up until recording condition "on level" are
being fulfilled. In condition default the record will be stopped until condition "on level" will be
fulfilled again or until software stopping command will be sent . Thereb y, signa l ar eas bei n g
selected on level on selected number of synchronizing channel and data from other physical
channels written in frame will occur in FIFO buffer under "on level" synchronization mode.
Thereof, all these data can be rolled back to computer due to their entering to FIFO buffer E20-10 .

Whe n s yn c hr o nizin g "on lev el " analog si gnal in E20-10 rev. В for software recognition of
data co ntinuity edg e s the ma r k i n g m ec hani sm has bee n int rodu c e d f or t h e f irst sam ple of dat a
continuous area obtaining from E20-10 (fig. 5-2). If marker mode is activated, that logic artifact
providing to differ beginni ng of next data continuo us a rea on upper software l evel is inserte d in the
first sample of each data continuous area. Way of viewing marker in the data format of E20-10 rev.
В is exp l a ined in p. 5.2.3.

1

2

3

4

1

2

3

4

Размер

кадра

Размер

межкадровой

задержки

1

2

3

4

1

2

3

4

Запрет передачи

заданного количества

кадров от начала

сбора данных

(рев. В)

2

3

4

1

2

3

4

1

2

3

4

Количество кадров, записанных в буфер

Остановка на
границе кадра
по количеству
кадров,
записанных в
буфер
(рев. В) или
программная
асинхронная
остановка
(рев. A, В)

Ожидание выполнения
дополнительного условия
аналоговой синхронизации
старта по перепаду сигнала
(рев. В)

Старт АЦП
(программный или по
перепаду сигнала
START в режиме
"ведомый"), рев.А,В

Период

частоты

АЦП

Логический
уровень выходного
сигнала START (в
режиме
"ведущий"),
рев.А,В

0

1 0

Все режимы синхронизации (кроме режимов "по уровню")

1

2

3

4

1

2

3

4

1

2

3

4

1

2

3

4

1

2

3

4

Прерывание записи на
границе кадра (до
следующего
выполнения условия “по
уровню”) или
программная
асинхронная остановка

Ожидание выполнения
дополнительного
условия аналоговой
синхронизации старта
“по уровню" (рев. В)

Старт АЦП
(программный
или по перепаду
сигнала START
в режиме
"ведомый")

Логический
уровень
выходного
сигнала
START (в
режиме
"ведущий")

0

1 0

1

2

3

4

1

2

3

4

Запись в буфер.

Режим по уровням сигнала в выбранном канале АЦП

(рев. В)

1

1

Принятые обозначения:

Сэмпл от указан-
ного физического
канала АЦП не
передан в буфер

FIFO.

Сэмпл от
указанного
физического
канала АЦП
передан в буфер

FIFO.

Межкадровая
задержка
длительностью
1 период частоты
АЦП

Дополнительное
условие “по уровню”
выполнено. Запись
начнётся со следующего
кадра.

Доп. условие "по
уровню" не
выполнено. Запись
прервётся после
окончания текущего
кадра

1

2

3

4

2

3

4

1

2

3

4

Ожидание выполнения
дополнительного
условия аналоговой
синхронизации старта
“по уровню"

Дополнительное
условие “по уровню”
выполнено. Запись
начнётся со следующего
кадра.

После
программной
остановки

1

1

Сэмпл от указанного
физического канала
АЦП передан в буфер
FIFO. Сэмпл содержит
маркер первого кадра
(если режим маркера
включён)

1

Запись в буфер.

ADC start (software or
on START signal edge
u

rev. А, V

Logic
level of output
START signal ( in
"master" mode),

rev. А, V

ADC start
(software or on
START signal
edge in "slave"
mode)

Expectation of additional
condition fulfilling for
analog synchronization of

start on signal edge (rev. В)

Output signal
logic level

START (in
"master"
mode)

Record in buffer

Additional

condition "on level" has
been fulfilled. Record will
start from the next frame.

Number of recorded in buffer frames

Blockage of transmitting of
Expectation of additional
condition fu
synchronization of start on

signal edge (rev. В)

ADC

frequency

Duration of

inter

frame delay

Frame size

Record interrupting at
frame edge (until further
fulfillment of condition "on
level") or software
asynchronous stopping

Expectation of "on level"
start analog
synchronization additional
condition fulfilling

Stopping at frame
edge on number of
frames recorded in

buffer (rev. В) or

software
asynchronous
stopping (rev. A
V)

Additional

condition "on level" has
been fulfilled. Record will
st

Record in buffer

After

software

stopping

Sample from given
physic al A DC c ha nne l is
transm itte d to FIF O
buffer. Sample contains
marker of the first frame
(if marker mode is

activated)

Sample from given
phy
channel is
transm itte d to FIF O
buffer.

Interframe de lay w ith
duration of 1
frequency period

ADC

Sample from given
physical AD C
channel is no t
transm itte d to buffer

FIFO.

Agreed notation

Mode on si g na l lev els in s elected AD C c hann el (rev. В)

All synchronization modes (except "on level" modes)

Additional
condition "on level" has
not
Record will interrupt
after end the current

frame.

­period

nder "slave" mode),

lfilling for analog

E20-10 User Manual

Record in buffer Record in buffer. Fig. 5-3. Sync hr on iz ati on mo d e diagr am s

given amount of frames

from

data acquisition start

(rev. В)

,

sical ADC

been fulfilled.

art from the next frame.

5.2.3. Data format of E20-10

Data format from E20-10 in normal mode (by default) is 16-bit signed integers (in radix

complement) within the range of from -8192 to +8191. Th is me ans , that 14 low bits ar e information
ones a n d 2 hi g h bits co nta in ext e nded si g n o f ra di x co m plem en t. Bi na ry the data looks like (15-th
bit is shown left, 0-th bit - right)

14

:

sssXXXXXXXXXXXXX,

where, s – extende d si g n o f radix co m plemen t , X – code positions
Lack of information content of two code high bits provides their value manipulation in

specific cases described in pp. 5.2.3.1, 5.2.3.2.

5.2.3.1. C oding of word size overloadi ng sign E20-10 or

revision А

In E20-10 of revision А the following coding of word size overloading sign is applied (if the

relevant mode is activated): when no overloading, that data are transmitted unchanged, when
overloading – the data are tr ansmitted with inverted 14-th data bit

š:

sšsXXXXXXXXXXXXX,

Based on radix complement represent ation of a number fe a tures, s uc h inversion of 14-th bit,
in any way, will be cause of resulting value of 16-bit code over the range of -8192…+8191, – this
is sof tware det e ctabl e si g n of over loadi ng .

In E20-10 of revision В the word size overloading sign is not inserted in data format (p.

5.2.6).

5.2.3.2. C oding of data continuous area sta rt in E20-10 of

revision B

In E20-10 of revision В the data continuous area beginning marker is appl ie d w hich is c od e d
by ins erting value "01" in fiel d of posit ions <15..14>, if m a r ker mode is activated:

01sXXXXXXXXXXXXX,

Such representation of marker gives simple criteria of its software detecting - this is code
value over 8191.

14

In most programming languages, this format complies with "signed small integer".

5.2.4. FIF O buff er and its ov erloa ding elimi nati on lo gic

E20-10 has on boa rd 8 Mbyte mem or y wh ere FIF O bu f fer is organiz e d. Such depth of
buffer is enough to, for example, compensate 400 ms of spooling delay via USB by operating
system at maximum acquisition frequency of 10 MHz (with zero interframe delay). Experiments
show, that this time interva l is fair enough even in operation under Windows ( unde r operating
system of unreal time) at average load of operating system with rest applications, in the absence of
explicit c omputer resource exhaustion (see details in Programmer's manual [1]). Thereof,
maximum spooling de lay time will increase pro portionally to decreasing of data transmission t raffic
in computer during data acquisition frequency decreasing and when setting to non-zero interframe
dela y. We refer red in de tail on b uffer overflow sit uation processing inside E20-10.

In E20-10 of revision А FIFO buffer overflow occurrence causes data acquisition stopping
and upper-level program necessity to restart E20-10, that leads to time-cons uming "freezing" of
E20-10 out of data acquisition process. This problem has been strongly taken into account in E20-
10 of revision B. Here, the specific hardware logic for FIFO buffer overflow elimination against
cont inuou s ac qu isitio n has bee n e ntered . Overflow elimination logic will sp oo l fro m FIFO data
with volume multiple of minimum requi red one to eliminate FIFO ove rflow capability at the
appr oa c h t o ed ge of 8 megabit of da t a col l e c te d i n FI FO. These emergency spooled data are th rown
fro m da ta fl ow but, in pr incip l e , da ta acquisiti o n w ithout channel nu mb er accountin g fa il u re at
upp er l e v el can be co nt i nued due to thr o w n da t a volume mu l tiple a lways o f frame size. So, in E20-

10 of revision В FIFO buffer overflow will always leads to unavoidable (in this case) data flow
break but unlike revision А, you may not restart data acquisition E20-10.

It is noteworthy, that all revisions of E20-10 have uppe r softw a re level tools to al arm FIFO
overflow occurrence which indicat e the use r d a ta flow from E20-10 brea k a ge (d et a i l s see in
Programmer's manual [1]).

5.2.5. Re ading s adj ustmen t (c alib ration )

Module E20-10 is del ivere d w it h ca librat i ons rec orded in L-Card. Relevant calibration
factors (product serial number and other additional details as well) are recorded in Flash-memor y o f
AVR controller.

Using calibration fact or s stored in Flash-mem ory of AV R co ntroll er you may ac c ount of fs e t
and s ca le error s (of gain factor) of analog path at each range.

In revision А of module E20-10 the data cal ibration procedure is impleme nted with upper
level tools (in computer), and in revision В – with tools of E20-10 itself. Working with pure

uncal i br a ted da ta i n bo th revisions, on demand, the calibration mechanism may not be used , but yo u
should take into account, that in this case dispersion in readings of different instances of modules
E20-10 can reach 5 % o f s ca le.

It also important to note, that in E20-10 or revision В the linear calibration arithmetic – is
inte ge r o f ADC data w ithin t h e range –8192…8191. Calibration factors under calibrating of E20-
10 at manufacturer are set in such a way that extreme points of each ADC input subrange
corr e s pond to calibrated code values ±8000.

5.2.6. ADC word size overflow warning

ADC word size overflow signal is available at ADC chip output LTC2245, it is gene rated for eac h
ADC sample and this signal is used in E20-10 for this overflow warning . In overfl ow case ADC
uncalibrated code takes one of extreme value -8192 or 8191 – depe nding on sign of input volta ge supplied
to ADC input.

E20-10 User Manual

It should be particularly emphasi zed that in E20-10 not overflow alarm of ADC spec ified input
subrange is captur ed but signal level alarm out put over ADC spec ified subrange wh ich resulting in incorrect
present ation of this level by transmitter due to excessing conve rsion physi cal ed ges.

In E20-10 of revision А when the relevant mode is selected, the ADC word size overflow
alarm is mixe d in 16-bit data format in such a way that

that 8191will be issued, and under negative overflow – much less tha n -8192. It is und erstood, that on upper
level if You acti vate overflow al arm in software then You must use range -8192...8191 excessing eve nts for
overfl ow software warning and prior to process sample d signal in your progr am You must l imit data range
up to -8192...8191. If You apply calibration of ADC dat a at upper level og library function the
abovementioned principle to select overflow alarm is not changed the only difference being linear data
calibration function is applied for E20-10 output data.

under posi tive overflow the code r ather more

In revision В the developers decided to abandon overflow alarm mixing in data flow and to
perform c hannel-by-channel warning vi a control pi pe channel of USB interface and relevant library
functions. Moreover, the procedure of software request on definite quantity of data from E20-10 of
revision В has been agreed with relevant software overflow presence bit in data quantity requested.

5.2.7. DA C opt ional

Two-channel asy nchronous DAC (option) is contr olled f rom AVR a s ynchr onou sl y o nl y
using control pipe of USB interface and by relevant function of upper level. This means, that DAC
can be used for slow reproducin g of constant voltages only under asynchronous control mode with
mean time for response - tens milliseconds, depending on response current time of computer
operating system.

6. Connection of signals

Signal ass ignments on E20-10co n n e ctor s a s w ell a s si gnal maximum p ermi s sible
ch ar acteristics and connecting w ays ar e explained in this chapte r.

6.1. General Information

The system user shall connect the signals and solder the connectors. Magnetic sweep cable
for s ignal connectors (except cable B N C) are incl uded in delivery package (p.3.3).

Inst allation of signal cir cuits wi th c onnection of sign al source s , sens or s , etc. to E20-10
module must be carried out by a qua lified specialist.

User c onne cting re su lt ing in ex c e e di n g o f ma ximum pe rmis sible voltage and current values
may ca use E20-10 par amete rs degradation or fail u re of E20-10, comput e r an d other conne cted
equipment. L-Card will not b e liable for damage caus ed by electrically im proper signal
connecting .

For more deta ils on wa y of signa l co nnection to the me asuring system an d noise
suppression, refe r to specialized a r ticle titled: Solutions of problem s on e lectro-compatibility and

interference protection duri ng conne cting of m e as ur ing equipment through the example of L-Card

L company product. [2]. References to articles on L.[3] connectin g e xa mple s as well a s on
optimizat ion of L.[4] c onnec ti ons are given in Chapter Bibliography of this manual on page 66.

6.2. External connectors

This ch apter describes in details connectors of E20-10 from external connections point of
view.

Volt age r anges given in tables in describing of signals made out to connector pins are
always speci fied in r e lation to AGND cont act for anal og signals and in relation to GND contact ­for digital ones .

E20-10 connectors packaging concept is as follows: analog signal connectors are in front,
digital - at the rear.

E20-10 User Manual

3

12

456

78

9

-12В

+12В

AGND

Канал 2
ЦАП

Канал 1

ЦАП

1 ADC channel

4 ADC channel

2 ADC channel

3 ADC channel

1,2 ADC channels

Outp uts + 1 2 V,

2 ADC
chann

1 ADC

channel

+12V

-12V

6.3. Analog signal connectors

-12V

Fig. 6-1. Anal og inp ut con ne ctors

el

Fig. 6-2. Anal og out put co nne ctor s

The four analog inputs of E20-10 module con ne ctors type is -BNC pl ug in socket type with
corresponding cable connector of BNC cable plug type. Channel matching is shown in fig. 6-1. The
same matching is graphically s ho w n o n E20-10 body.

Actually, in case of accurate handling of E20-10it is n ot prohi bi t e d (but not recommen de d!)
to use domestic connector CP-50 instead of foreign-made BNC as a cable connector, but in this

Signal

Common

Direct

Description

1 ADC

AGND

input

Single-p ha s e (with co mm on land) 1 ADC channel

2 ADC

AGND

input

Single-phase (with common land) 2 ADC channel

3 ADC

AGND

input

Single-phase (with common land) 3 ADC channel

4 ADC

AGND

input

Single-phase (with common land) 4 ADC channel

1 ADC

AGND

output

Single-phase (with common land) 1 ADC channel

2 ADC

AGND

output

Single-phase (with common land) 2 ADC channel

+12V, -12V

AGND

outputs

Bipolar (relative to A G ND ) ex ternal device power

AGND

- - Analog lan d E20-10

case15 po ss ible difficu lties can arise when conne cting or di s c onnect i ng this c o nnect or w i th the plu g

in con n e ctor BN C onE20-10 module.

Attention! Due to the non-conformity of domestic (made in Russia) connectors to the BNC
standard, use of СР-50 co n necto rs (cable part s or adapters) in som e cases can cause a damage of
plug in connectors BN C in E20-10.

Type of DAC analog output connectors and power outputs for E20-10 — 9-contact socke t
MiniDIN. Contact assignment is shown in fig. 6-2. Relevant cable connector - is 9-con tact cable
plug MiniDIN.

Table. 6-1.

On connectors analog signal assignment

designation

channel

channel

channel

channel

channel

channel

point

ion

input, connector screen is connected with AGND

input, connector screen is connected with AGND

input, connector screen is connected with AGND

input, connector screen is connected with AGND

output

output

output

15

Historical roots of this problem belong to the non-conformity of metric standards of the former USSR to the western

inch standards.

E20-10 User Manual

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16
17
18
19

21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37

DI16 / START

DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
DI9
DI10
DI11
DI12
DI13
DI14
DI15

GND
+5 V

SYNC

DO16

DO1
DO2
DO3
DO4
DO5
DO6
DO7
DO8

DO9
DO10
DO11
DO12
DO13
DO14
DO15

GND

EN_OE

+9...+27V

GND*

6.3.1. Di gital sig nal a nd ex ternal pow er con necto rs

connector — DB-37M.

any ci rcu it.

Type of digital in put-output signal connectors in E20-10: DRB-37F, r e le vant cable pa r t of

Attention! Metal edging (body) of cab le connec tor DB-37M shall not be connected with

External pow e r connector type: DJK-02A, ca bl e pa r t relevant to it — DJK-10A.

Fig. 6-3. Digital signal and external power connectors

Desig-

Common

Direc-

State after

Description

DI<16...1>

GND

Input

16-bit digital input: DI1-low bit, DI16-high bit,
DO<16...1>

GND

Output

Z-state

16-bit digital output: DO16 – high bit, D O1 – low
GND

- - -

Digital land

+5V

GND

Output

+4.75...+5.0 V

Power output +5V of external cir cuits. see p. 6.4.5

SYNC

GND

Input-

Input-output of ADC synchroniza tion signal ( pull-

START

GND

Input-

Input-output of data acquisiti on start signal,

+9...+27 V

GND*

Input

Volt age input of +9...+27 V from external power

EN_OE

GND

Input

Contr ol input for DO<16...1> line forced setting

it is required to close circuits EN_OE and GND on

Table 6-2. Conn ect or DIGI TA L I/O sig nal s

nation of

point

tion

output

output

connection

START and DI16 lines are combined

bit

up resistor is not available)

START and DI16 lines are com b in ed. Pul l-up
resistor of 4.7 kOhm t o circuit of +5 V

supply sour ce of 5W. On circuit GND* see in p.

6.5.3

mode t o active output upon module power fe eding
completion, in this case, software control function
is ignored with output enable. To active the mod e

cable part of digital signal conne ctors. If EN_OE
input is unconnected the output enable software
control mode is activated.

E20-10 User Manual

Signal

Typ

Input resistance

Maximum

input

Maximum

output

Pull-up resistor

Inputs

channels

AI

min. 5 MOhm

10 MOhm (rev.

±10 V

DAC

AO

Output shor t cir cuit
INT,

DI15

DI

4.7 kOh m

-0.2V...+5.2V

GND

4.7 kOh m

DI16/

DIO

4.7 kOh m if

input

-0.2V...+5.2V

GND

4.7 kOh m
DO1...

DOZ — — ±20 mA

—

SYNС

DIO

Min. 100 kOhm

-0.2...+ 5 .2 V

±20 mA if

6.4. Characterist ics of signal line inputs and output s

Attention!: Prior to connect E20-10 module to your system, it is required to strictly observe

the parameters specified in tables of this section.

The manufacturer shall not be liable for E20-10 fai lure caus ed by violation of

maximum permissible operation conditions.

The fol l owing symbols are given in tables of this section:

AI- analog input
DI – digital input
DOZ - Z-state transferability digital output
DIO - digital I-O
AIO - analog I-O

6.4.1. Operating mode

Module E20-10 has the following input and output signal line characteristics.

Table 6-3. Characteristics of signal lines inputs and outputs, operating mode

of

channel
outputs

DI1...

START

e

(rev. А)

configured for

permissible

conditions at

relativ e to

relativ e to

permissible

conditions at

may occur agai nst
AGND

relative to +5V

relative to +5V

DO16

Attention: It is not recommended to unload E20-10 more than 0,7.. .1 W total power on al l output
cir cu i ts E20-10 .

if configured for
input

relativ e to
GND

configured for
output

Signal

Type

Input resistance

Maximum

Maximum

ADC channel

AI

min. 1 kO hm

±10 V

—

DAC channel

AO

— — —

DI1...DI15

DI

min. 600 O hm

-0.2...+ 5 .2 V

—

DI16/START

DIO

min. 600 O hm

-0.2...+ 5 .2 V

-0.2...+ 5 .2 V

DO<1...16>

DOZ

-0.2...+ 5 .2 V
SYNС

DIO

min. 600 O hm

-0.2...+ 5 .2 V

6.4.2. Power-off mode

Module E20-10 switched off the external power supply source has the following input and output

signal line characteristics:

Table 6-4. Characteristics of signal lines inputs and outputs, off mode

inputs

outputs

permissible

voltage at inp ut

relative to GND

relative to GND

relative to GND

permissible

conditions at

output

relative to GND

relative to GND

E20-10 User Manual

Circuit

Maximum allowable output current

AGND-GND

0.1 А

AGND-GND*

0.1 А

GND-GND*

0.7 А

Parameter

Value

Rev. “А”, “В”

Rev. В.01

Operating vol tage range

+9.0…+27 V

+8.0…+40 V

Maximu m per mi ssible vol tage

−30…+30 V

−45…+45 V

Power input under oper a ting mode with off-

max. 5 W (rev. А)

6.4.3. Limiting through currents

Inside E20-10 circuits AGND, GND, GND*, presenting on module connectors are

interlinked (p. 6.5.3). This places certain restrictions on maximum permissible through currents
through circuits AGND-GND-GND*.

Attention! Maximu m permis s ible thr ough cu r rents exceeding ca n ca use E20-10failure.

Table6-5. Maximum permissible through currents

6.4.4. External power supply input characteristic

When E20-10 is energized not from AD adapter including in delivery package (p. 3.3.1) and

from external direct current source the following parameters shall be taken into account:

Table 6-6. External power supply input characteristics

load output circuits E20-10.

(engagem e nt t hreshold
+9,5 V)

min 4.5 W (rev. В)

max. 4.5 W

6.4.5. External power supp ly ou tputs c harac ter istic

When collecting currents from E20-10 to power external devices it is required to take into

account external power output characteristics.

Table 6-7. External power supply output s chara cteristi c

External circuit power supply

source

Maximum output current 2 x 35 mA 35 mA

Cur re nt protec tion stabiliz er ther mal

protection

Attention! It is not recommended to unload E20-10 more than 0,7...1 W total

power on all output circuits E20-10 .

±12V +5V

100 mA for E20-10 of
revisi on B.01

stabiliz er ther mal
protection

E20-10 User Manual

6.5. Specification and connection examples

This chapter contains certain major features for external circuits connecting to module E20-

10.

6.5.1. Connections to USB

The fol l owing features shall be taken into account:

• Speed of 20 M B/s (corresponds to data acquisition frequency of 10 MHz at zer o

int erframe d el a y) is cl ose to maxi mum op er ati o n a l spee d high-speed USB 2.0 interface. In
particula r, it m eans , that b ot h E20-10 connected to one USB-hub (or one USB-controller
of the computer) can operate up to 10 MB/s e ac h only.

• On the on e ha nd , m od ern USB3 . 0 – hubs sha ll pro vi de sp e e d of 20 MB/s for each

downstream port, on the other hand, hub's manufacturers are not obliged to provide such
speed and in the pursuit of the product cheapening the versions

• Under combined connecting high-speed and full-speed USB devices to the same USB-hub

the speed of USВ will be set based on the slowest device, i.e. full-speed only.

16

…are possible.

• At sp eed full-speed (USB 1.1) the maximum ac hievable spee d of dat a tr ansmission E20-

10 — 1 MB/s (ADC 500 kHz), it can be set via corresponding setting of interframe delay.

At higher frequencies FIFO buffer of E20-10will be overflowed, because USB full-speed
band wi dth capacity w i ll not pr o vi d e the r equ i red spe e d of spoo li n g f rom E20-10 (buffer
overflow will lead to data loss but not to service outage of E20-10).

• Whe n s everal E20-10 are used at speed of more than 10 M B/s it is recomm ended to

connect them to computer different controllers – in this ca s e, t here s houl d be no

bandwidt h ca pacit y problems ( oth erwi se , i nt ernal U SB-hub o n m other ca r d wi l l not
provide 20 MB/s for ea c h po r t) . If re qu ired, you can use additiona l PC I or PCI E x press

expansion cards for USB-ports in auxiliary USB-controllers on the basis: 1 card for 1
module E20-10 (the required s p ee d w il l be pr acti ca lly prov i d e d vi a U SB ).

• It should be noted, tha t when u sing several m o dules E20-10 at maximum speed with one

computer there are objective physical limits for: - phys ical re cording spee d on hard disk
(if you r s o ft wa re use s su c h recor di n g) ; - c hipset op eratio n s peed via c o mpu ter RAM,
bec ause data transmiss ion from E20-10 to computer RAM is via DMA (i.e. with computer
processor partial involvement); - co mpu ting load wit h e xteri or t a sks acti v ely work ing wit h
RAM.

• Maximum length of USB cable according to standard - 5 m.

Attention! To avoid E20-10 failures (particularly, at high operation speeds) it is highly

recommended not to use the computer remote USB e xpansion ports to co n n ect E20-10

17

(these are the ports that use pin double-row connectors

on mother ca r d s wi th ext en si on
cables and additional USB connectors, which are usually located either at the rear of the
system block on additional bars or moved forward of the computer case) due to the lack of
quality of these conn ections for a high-speed device l ike E20-10 on s ev er a l important

16

L-Card can not warrant third-party product quality; prior to buy the selected hub it is necessary to be clear maximum

speeds on downstream-ports.

17

in general, such USB connector is not even specified in USB specifications 1.1, 2.0 and 3.0 [10] [11]

character i s t i c s: unshi el ded connect or on mot h er ca rd, part ia l l y or fully unshield ed cabl e fr o m
this c o nnect or, improper ca ble shield connection and remote connector.

6.5.2. Multimodule connections

You must keep the following rules in multimodule configurations with E20-10:
If modules are interconnected via digital lines (including via synchronization and interrupt

lines) then modules GND lines shall be interconnected as well.

If d ifferen t modules a re conductive ly coupled via any ci rcuits but they use different PC or
dif f erent U SB-hubs f rom individual power sourc e s , then these PC or USB-hubs shall have common
ground (if gr ou n d ci rcuit i s pr ovide d) a nd mo du les GND c ir cu its sha l l b e i nt ercon ne c t e d.

When interc onnecting of bidirecti onal line s of diffe rent mod ules the incons istent sta te output
to output which can lead to lines overflow E20-10s hould be negated.

The m odu les connecting to USB issues are described in 6.5.1. For information on proper
use of GND, GND* and AGND circuits when connecting the devices, please, refer to 6.5.3.

Higher levels of through currents a re poten tial in multimod ule connections E20-10 (pp.6.5.3,

6.5.4.4-6.5.4.6). Penetrat io n methods: proper groundi ng, in-phase filters (specific recommendation

providin g de t a iled de s cripti o n o f c on n e ct i ng case ar e give n - o n de mand in L -CARD).

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9

AGND

AGND

AGND

AGND

AGND

GND

GND

GND*

Внутренняя
точка
соединения

ANALOG

USB

1

2

3

4

DIGITAL I/O

Фильтр

Filter

Internal
co nne ction point

6.5.3. Circuits GND, GND* and AGND

Connecting exter nal circui ts of module E20-10 shall be performed based on its i nternal conne cting
diagram for common wire s from different connectors –

Fig. 6-4.

Fig. 6-4. Circuits GND, GND* and AGND

Module E20-10 has no i nt er nal gal vanic separations, hence, GND, GND* and AGND
circuits have internal coupling (p. 6.5.3): common wire of digi tal circuits GND i n one point inside

E20-10 is connected to common wire of analog circuits AGND. External power source comm on
wire is connected to the same inter nal point E20-10 via in-phase EMC filter.

On principle, that common wire of USB interface from computer (connected to computer
case) is connected to common wires connection point inside of E20-10.

When co n nectin g E20-10 to extern a l circuits you should remember, that the most proper
connecting of E20-10 is that con ne cting w hich wou l d not resu lt in t hroug h c u r rents pas sage via
circuits: GND—AGND, GND—computer ca s e or AGN D—GND—computer case.

Attention! Presence of abovementioned through currents can degrade signal-noise rate in
E20-10 channels, cause unsteady operation of USB or USB-hub, and when exceeding of maximum

permissible through currents(table 6-5) E20-10 and connected equipment failure.

If such currents are unavoidable on any case in your system it is required to take measures to

minimis a tion them (pp .6.5.4.5, 6.5.4.6).

General recomm enda tion on ins trumen ts c onnec ting are given in special article [2].

Более
5 MOм

7 мкА
(тип.)

Вход ревизия А

10 MOм

0.6 мкА
(тип.)

Вход ревизия B

управляется программно

(“по умолчанию” - выключен)

Input

revision A

Input

revision B

controlled i n software

0.6 µA

10 MOhm

7 µA

(typical)

Maximum
5 MOhm

6.5.4. AD C inp ut co nnect ing

Some nitty-gritty iss ues on ADC inp ut connecting are de s cribed here in.

6.5.4.1. In trinsic input current of ADC analo g input

This cur rent was amplifie r co m pone nt property ap plied in r e visio n A. A mp lifier with
incom parably lower input c urrent ( abo ut 10 nA) may be applie d in revis ion B. But, due to the fact
of input curr ent existence of revisio n A co uld be used in different pr opositi ons (fo r ex am ple, as
sign a l external source connec ting sign), that in revision B the negative offset current c a n be live on
command (the r e w ith, offs et current is generated artificially) to be com patible with old revision, but
input of f se t curr en t is dea d by default in revision B, see fig. 6-5.

ADC input intrinsic c ur rent of E20-10 of revision А has negative sign, so,when
unconnected analog input of E20-10 the overswing to nega tive valu es sid e w ill be appeared.
This, on the one hand, le ads to de terminac y of unconnected analog in put state, one the other hand ,
places restrictions on signal internal resistance on direct current, because intrinsic input current
value multiplied by interna l resi stan ce o f signal s ource (via direct curre nt ) w ill suppl y c onsta nt
voltage of input offset signal of E20-10. For example, if source resistance is of 50 Ohm typical
offset voltage will make 0. 35 mV, and if 1 kOhm — 7 mV.

Fig. 6-5. Equivalent circuits of ADC input circuit via constant current (differences in

6.5.4.2. C onnecting to high -resistan ce output a nd alt ernate

For E20-10 of revision А, if your signal source outputs is alternate current output
conta i ning s eries coupling capa citor (i.e . on dir ect cu r re nt – disconnection or resistance of more
than 10 kOhm), then when connecting to such output it is required to connect additionally parallel
resistor (max. 1 kOhm prefera bly) to si gna l source out pu t

18

Of course, such resistor connectivity depends on type and output capability of signal source

("by default" – off)

curr ent output

revisions A and B)

18

. This resistor genera tes the req ui red

(typical)

E20-10 User Manual

source resistance on di re ct current and min imizes input cur re nt effect (p. 6.5.4.1) on ADC input
zero offset voltage. We can state, that: ADC input of E20-10 of revision А is incompatible with

signal sour ce with resistance of more than 10 kOhm on dir e ct curr e nt.

For E20-10 of revision В under same case the minimization of input offset voltage for ADC

input can be achieved by software disconnecting of offset input current and, in this case, conceptual
res tricti ons of rev ision A are ended.

Please note, tha t in all rev isions of E20-10 it will be preferable to have signal source low
resistance to optimize signal-to-noise r a tio

6.5.4.3. On standard feeler oscillogr aphic gaug e

connectivity

ADC input BNC connectors of E20-10 suggest the users on standard feeler gauge
connectivity to divider 1:1/1:10 r a ted at oscillograph in put resistance of 1 MOhm and input
capacitance of 15-30 pF. It should be noted, that such gauge on direct current under mode 1:10 in
relation to ADC input is equivalent to high-resistance sign al source (more than 10 kOhm ) and with

E20-10 of revision A such gauge under mode of 1:10 is incompatible with E20-10 revision А (p.

6.5.4.2), but compa tib le w ith E20-10 or revision В, if input current will be off in software (input

current is disconnected "by default" in revision В). It is required to match the gauge. Consider these
issues in details.

Standard fe eler oscillogr aphic gauge is, general ly, rated at oscillograph input resistance of 1
MOhm. Under mode of 1:10 the device input resistance serves as gauge voltage divider "lower
arm" of 1:10, w hile the gauge tr ansfer impedance ( a bout 9 MOhm) serves as divide r "upper a rm".

So, to prov ide divi ding fun ction 1:10 if osci llograph gauge i t is re quired to have c onnecting in
parallel to input E20-10 of r e s istor of 1.1 M O hm . This resistor connected in parallel to input

resistance E20-10 will provide required 1 MOhm cumulatively for standard feeler oscillographic
gauge load.

We can assume, that in mode 1: 1 the standard ga uge of the oscillos cope is rather well
mat ch e d in f r e quenc y ba n d up to 5 MH z with AD V in put of E20-10 of any revision, s ince in 1: 1
DC mode the thro ugh resistance of the gauge is not too high, and the inconsistency in al ternating
current affects the higher frequencies that do not fall within the bandwidth of the ADC input. In this
case, input c urrent c urtailability in E20-10 of revisio n B provides the gauge connectivity 1: 1 to
high-impedance signal sources, as in the case of a convention al oscilloscope.

Gau ge a c cu r a t e ma tc hing a cross the al t ernati n g cu r rent in 1:10 m od e can be pe rform e d wi th
operating tuning condenser located on the gauge BNC connector, if, of course, your gauge has such
a tuning.

The pa ra l lel co nn e ction to E 2 0 -10 input of a 1.1 MΩ resistor, as was recommended above,
can technically be done by switching the oscilloscope gauge via BNC load adapter

19

.

6.5.4.4. On eff ect of th rough curr ents on signal-to-noise

ratio

ADC input of E20-10 has bipolar, sing le-phase voltage input w it hout galvanic isolatio n (see
input types classification in 2).

19

This adapter is not delivered by L-card. When necessary L-Card is ready to consider the possibility of E20-10
modification release with input resistance of 1 MΩ. If you are interested in such E20-10 modification, please contact the
L-Card office or the conference at www.lcard.ru

If you intend to achieve the best signal-to-noise ratio when connecting ADC single-phase

input of E20-10 to an external device (signal source), you must provide zero current (across the
frequency bandwidth) passing along the screen of the coaxial cable of ADC input circuit, because,
voltage loss on through impedance of the cable screen circuit is largely summed with the v ol tage of
the usef u l signal a t ADC input, that leads to a deter ior a tion in th e signa l-to-noise ratio.

6.5.4.5. Ho w can you find out that the through -currents

degrade the signal-to-noi se ratio in you r connectio n
diagram?

Let us say, You have connected ADC input of E20-10 to external d evice and have f ou nd

disturbances absent at external device output within digitalized signal spectrum. Root cause
location:

• Disconnect coaxial cable connector from device (second cable end is connected to E20-

10) and cl ose c en t ral contac t of disconnected c onnector to its housing. If disturba nce in

digit a lize d si g na l ha s di sa p peare d this mea ns that it i s ge n er a ted not in E20-10 and not in
cable as a result of its f ailur e.

• Having connector central contact closed connect connector hou si ng t o de vi ce outpu t

connecto r housing. If disturbance is present , this means, th a t i t has been generated due to
through currents. If disturbance is absent, this me ans, that there is disturbanc e at device
output signal itself.

6.5.4.6. How to solve the problem if the through currents are

detected?

The following technical ways of solution will help you:

• Ground the connected devices el e ctrically close , shorten connecting wires.

• Use galvani c i so l a tion au xil ia ry equ i p m e nt in sy st em which brea k t hrough cu rr en t circuits

on common wires.

20

• Connect signal to ADC output of E20-10 via external in-p hase f il ter

compensate alternate through current and disturbance will be absent in the signal.

which will

6.5.4.7. On disconnected ADC inpu ts

Attention! Disconnected inp uts are recommende d t o be set i n i nt rinsic zero measurem en t

mode or they are not required to be sampled.

ADC input intrinsic c ur rent (exc ept of E20-10 of revision В with input current disconnected

in software) on ADC disconnected inputs can generate input voltage exceeding input signal
specified s ubrange. Wherever s ample the c orresp onding channel under input overload mode
during data acquisition, then it can cause interchannel passing moderate increase . So, disconnected
input should either be set in intrinsic zero measurement during normal operation - over load will be
eliminat e d, or b e u nsampled ( i. e. c ha n nel co de corres po n ding to disco n ne ct ed input shall be ab s e nt
in control list).

6.5.1. Di gital lin es an d sync hron izati on line s c onnec ting

All digital li nes of E20-10 (fig. 6-3) have GND common wire circuit above which the

connections with external digital nodes should be performed. GND circuit external connecting
should always base on its internal connecting (p.6.5.3)

20

To have technical help on technical details on such filter structure depending on signal source type, please, contact L­Card

E20-10 User Manual

To implement "master-slaves" conne ctio n diagr am the near located fr om 2- to 5- pcs. E20-

10 can be connected with twisted pairs by short e st pat h. Simi la r cir cuit s of all E20-10 are required

to be connecte d imp li citly (fig. 6-3): GND–GND, SYNC–SYNC , START–START. Whe n
connections performing with twisted pairs one of the wire in pair should always be a GND circuit.

Connections optimal topology with short twisted pairs - is when two twisted pairs per each
"slave" go separate way s fr o m " ma s t e r" accor d i n g to r a di a l pr inciple in shor test pa t h, a n d no n
optimal - is a sequent ial traversal topology. The compromise betwe en the f irst and the second
variant is app ropriate in practice. Short twisted pairs can be replaced with short screened wire
bridles (GND-screen).

The case of short connections of near located E20-10 has been described above, but there is
a te chnical pos sibility to sig nificant ly incre ase the length of conn ections and the num ber of
synchronized E20-10. If you retrans mit STA RT and SYNC si gnals many times us ing trans m itter
microci rcui t from mast er E20-10 (connect or power + 5V) then the number of E20-10 connected
according to "master-slave s" is unlimited tech nically! One of the examples of such connecting
base d o n M L VDS tech nolog y is descr i bed in L.[ 3] , see page. 66.

Specification

Value

Number of cha nnels

4 wit h "common ground" (single - phase)

ADC bit depth

14 bits

Sub-ranges o f input signal

±3 V; ±1 V; ±0,3 V – independe nt programmable
setting per channel

Limits of DC voltage maximum permissible
reduced fundamental error of measurement

±0.25 %

Limits of the perm iss ible relative basic error of

According to p. 7.1.1, 7.1.2

Limits of the permissible relative fundamental
error of the ADC conversion frequency

±0.005 %

Typical signal-to-no i se ra t io

70 dB (for E20-10 of revision A)
73 dB (forE20-10 of revisi on В)

Li mits of maxi mum permi ssible com plem entar y

within oper ation a l temper ature range, per 10 º C

0,5 against ma x imu m p ermi s sibl e fundamen tal

M aximum AD C conversion frequency

10.0

M inimum ADC c onvers ion frequency

1.00 MHz (lower data a cquisition f r equencies are

mechanism implementing data reduction)

7. Specifications

All E20-10 characteristics given below correspond to computer sta ndard USB 2.0 port

connecting.

The following specifications indicate the main parameters of E20-10 for its intended operat ing

mode.

Attention! E20-10 module performance limits as well as signal line additional features are

given in p. 6.4.

7.1. ADC

measuring the AC voltage

error against changes in ambient temperature

error limits

permissible using interframe delay internal

E20-10 User Manual

Ze ro of fset when ADC input is unconnected

Less than 1 mV (typical ly) for E20-10 of rev. V

ADC samp les frame p arameters:

– Frame size

From 1 to 8192 ADC frames (in firmware 2.00.0 7 or
older, see p. 3.3.4)

– ADC c hannels frame i nsi de sampling seque nce

arbitrary (programmable)

Interframe delay time

for E20-10 of revision В

programmable:

0-65535 ADC conversion frequency periods

Minimum data ac q u isition rate at maximum
MHz

7.8 kbyte/s (for E20-10 of revision A)
Maximum data ac quisition rate at zero in terf r ame
delay and ADC conversion frequency of 10 MHz

20 byt e/s

ADC conversion frequency spectrum in internal

F

= 30/k [MHz], where, k = {3, 4, 5, ..., 30}

ADC analog input DC input resistance

Minimum 5 MOhm (for E20-10 of revision А)

10±0.5 MOhm (forE20-10 of revision В)

Intrinsic input current o f analog input:

for E20-10 of revision А

-15...0 µA (typical value -7 µA)

for E20-10 of revision В

10 nA (typical value )

Typical val u e of co n versio n pa th upp er passba nd

E20-10-1, E20-10-D-1, E20-10-D-1-I

4.5 MHz (on subra nge ±3 V)

5.2 MHz (on subra nge ±1 V)

3.5 MHz (on subra nge ±0.3 V )

Inter-channel passage

- at constant volta ge

-50 dB

- at frequency of 1 kHz

-70 dB

- at frequency of 1 MHz

-60 dB

for E20-10 of revision В, min.:

- at constant volta ge

-70 dB

- at frequency of 1 kHz

-75 dB

- at frequency of 1 MHz

-65 dB

Resistance to overloads by input measuring
sign a l of DC volt age

±10 V (p. 6.4)

Data co rrect ab ility (c alibration using factory

Yes

E20-10) (p. 5.2.5)

for E20-10 of revision А

interframe delay and ADC conversion fr equency of 1

synchronization

freq ue ncy on level of -3 dB:

E20-10, E20-10-D, E20-10-D-I

0-255 ADC c onversion freque ncy periods

30 byt e/s (for E20-10 of revision B)

ADC

1.2 MH z

for E20-10 of revision А, max.:

calibration factors)

(for E20-10 of revision A – by software, in
computer , for E20-10 of revision В – by hardware

)]1(02,02,0[ −×+±

X

X

AC

)]1(03,02[ −×+±

X

X

AC

)]1(05,03[ −×+±

X

X

AC

)]

1

(1

,

015

[ −

×

+±

X

X

AC

Notes

2

К

AC

X

X =

3 X - is the value of the measured voltage.

Frequency range of input

sign a l, kHz

Limits of the permissible relative basic error of measuring the

AC voltage, %

)]1(02,02,0[ −×+±

X

X

AC

)]1

(03

,02[ −×+±

X

X

AC

)]1(

05

,03

[ −×+

±

X

X

AC

)]1(1,05[ −×+±

X

X

AC

)]

1(3

,030[ −×+±

X

X

AC

Notes

2

К

AC

X

X =

4 X is the value of the measured voltage.

7.1.1. E20-10, E20-10-I, E2 0-10-D-I

: limits of the

permissible relative basic error of measuring the ac
voltage

Freque ncy range of input

Limits of the permissible relative basic error of measuring the AC

signal , kHz

from 0.01 to 20 incl.

more tha n 20 to 300 incl.

more tha n 300 to 500 incl.

more tha n 500 to 1000

1 AC voltage measurement error is subj ect to li mitation for signa ls peak values of which do not

exceed measurement subrange specified value.

2 X

- is the AC voltage measurement limit,

AC

voltage subrange.

7.1.2. E20-10-1, E20-10-1-I , E20-10-D-1-I: lim its o f t he permissible relative basic error of measuring the ac voltage

voltage, %

where XK is the value of the specified

from 0.01 to 20 incl.

more tha n 20 to 300 incl.

more tha n 300 to 1000 incl.

more tha n 1000 to 2000 incl.

more tha n 2000 to 4900

1 AC voltage measurement error is subj ect to li mitation for signa ls peak values of which do not

exceed measurement subrange specified value.

2 AC voltage measurement error withi n input signa l frequency ranges exceeding 1000 k Hz is
subj ect to limitati on f or measurement ra nge of 1 V only under transmitte r s single-channel operat ional
mode.

3 X

- is the AC voltage measurement limit,

AC

where XK - is the value of the set

voltage subrange.

E20-10 User Manual

7.1.3. ADc synch ronization system

Parameter, characteristics

Value

Parameters of SYNC external signal under ADC

Input TTL-signal with period of 100 – 1000 ns, on­ns.

ADC synchronization signal parameters:

Propagation delay time from output

20 ns

Synchroni zation signal dela y time dispersion in

– STAR T signals

START e xternal signal duration, min.

50 ns

Param e t er, characteristics

Value

Number of channels

2

Bit depth

12 bits

Settling time21

8 µs

DC voltage rep roducing range

±5 V

Limits of the allowed reduced basic error of
repr oducing DC voltage

±0,3 %
Output current

2 mA

Li mits of maxi mum permi ssible com plem entar y

within oper ation a l temper ature range, per 10 º C

0,5 against ma x imu m p ermi s sible fundamental

Output re sista n ce to susta in ed sh ort cir cuit

Yes

Operational mode

Asynchronous

conversi on f requency e xternal synchr onization.

Propagation delay time in output:

– STARТ signa l, max.
– SYNC si gnal, max.

– STARТ signal, max.
– SYNC si gnal, max.

different modules E20-10:

– SYNC si gnals

7.2. DAC

off time of 1,90.. .2,10, with front/fall time of max. 5

One period of ADC start frequency
20 ns

One period of ADC start frequency

±8 ns
±one pe r iod of ADC start frequenc y

err or a ga i n st changes in ambient te mpera ture

21

This is output signal settling time for DAC used microcircuit without regard for much longer expected time of DAC

control software-based asynchronous delay (p.

error limits

5.2.7).

Param e t er, characteristics

Value

Digital lines quantity

- ADC start synchronization inputs

Output current:

max. 40 mA

Output logic levels

(com ply wit h s er i e s 74 H C T , TTL/CMOS 5 V)

Input logic levels

-0.2...+0.6 V ("log ical zero")

(com ply wit h s er i e s 74 H C T )

7.3. Dig it al l in e s

- general purpose input

- general purpose output

- data acquisition start synchronization inputs

- Digital li ne op erati ona l ou tput cur r ent

– Total load output current relatively to
connected GND circuit, outputs bein g in logical
item state

Attention! Di gital lines perfor ma nce li mits see p.6.4

16
16
1 (digital input one line alternative function)

Max. 8 mA (limiting current see p. 6.4)

0...+0.4 V ("logical zero")
Min. 2.4 V ("logical unit").

+2.4...+5.0 V ("logical unit").

E20-10 User Manual

Parameter

Value

Operational voltage:

E20-10

Power input (during operational voltage

– for E20-10 of revision А

to 5 W

Input in-phase interference filter

Yes

Stability under power voltage negative polarity

Provided

Parameters of power outpu t ±12V of external

7.4. Power

This appendix contains power input-out put cha ra cteristic s f or E20-10 (see also p. 6.4.4)

E20-10 power supply external source input
parameters

– for

of revisions А and B

+9.0...+27 V

(when i nitiation voltage shall be within the range of
+9.5…+27 V, operational capabi lity upon act uation is
within the range of +9.0...+27 V )

– for E20-10 of revi s ion B.01 +8.0...+40 V

supplying, with off -load output circuits of E20-

10):

– for E20-10 of revisions В and B.01 to 4.5 W
Galvanic isola ti on fr o m other cir cuits of E20-10 No

erroneous connection mode 22

External devices power outp ut +5V
par ame ters:

– output voltage
– output current

- current protection type

devices E20-10
– output voltage
– output current

- current protection type

22

actual situation: sometimes third-party supplies have network cards with power negative pole at connector central

contact; in cross-connection of such card to E20-10 the module will be operating but it will not operate from such card

23

under thermal protection actuating E20-10 normal operation is not provided

+5 V (+5% −10%)
35 mA ( 100 mA for E20-10 of revision B.01 )
voltage sta bilizer thermal pro t ectio n

23

±12 V ±5%
35 mA
voltage sta bilizer thermal pro t ectio n

Parameter

Value

Body dimensions (without connectors projected
parts)

142×132×40 m m

Weight

Max . 0.3 kg
Connector type Digital I/O

DB-37F

Connector type USB

DUSB-BRA42-T11

Analog output connector type
Analog inpu t c on n ector t y pe s

MDNR-9J
BNС – female cha s sis jack p lug

Power connector type

DJK-02A

Mean time between failures

Min. 40000 hours

Ser vice life

10 years

7.5. Physical properties

E20-10 User Manual

Parameter

Value

Nor ma l operat i n g c on diti on s:

– environment temperature, °С

20±5

– relativ e humid it y, %

from 30 to 80

– air-pressure, kP a

from 84 to 106

Parameter

Value

For stability under climatic influences, the converters, in addition to

group 3 with an extended ran ge of opera ting tem perat ures:

– environment temperature, °С

from +5 to +55

– rel a tive humi dity at an am bient tem perature of 25 °C, %

up to 90

– air-pressure, kP a

from 70 to 106.7

For stability under climatic influences, converters of designs with the

range of operating temperatures:

– environment temperature, °С

from -40 to +60

– relative humidity at ambient temperature of 30 °С, %

up to 90

– air-pressure, kP a

from 60 to 106.7

7.6. Operation conditions

7.6.1. No rmal condi tions

7.6.2. Op erating c onditions

the ve rsions with the letter in de x I, corr es pond to GO ST 22261,

letter index I correspond to GOST 22261, g roup 4 with an exte nded

External appearance

of abnormal

Possible reasons

Tro uble s hoot i ng mea s u re s

Computer operating

1) Connection with USB

Recover the contact, replace the cable

In signal spe ctrum

1) Poor cores screening

Use high qua lity scr eening

Suspicions on the

Your program may not

Check the suspect functions of E20-10 using

8. Problems solution under abnormal

situations

This Appendix attempts to classify possible abnormal situations which can occur in real

practice and provides troubleshooting recommendations to the user.

system records
unexpected
disappearance of
connection via USB
interface during the
operation. Indicator is
yellow for a short time
or consta ntly or blinks

digitalized by E20-10
the components you
have not in your
signal are present

cable is lost or USB cable is
defective

2) Thr ough currents vi a
common wires connected to
E20-10 devices in your
circuit are so high, that it
will lead to USB interface
unsteady operation.

2) Curre nt circuit provoking
this disturbance via common
wires is present in your
connection dia gram. When
coaxial cables closing from
the si gnal source ( without
braiding disconnection fr om
signal sourc e) the
di st ur bance exist s a nd when
the disturbance disappears
when cable is fully
disconnected from source, it
means in-phase disturba nce
behavior

Sta rt with detecting through curre nt flow circuit in
your connection diagram. To t his effect you should
di sconnect in series signal source and load
connectors (except power input and USB) and, if
upon next disconnecting USB interface oper ates
steady, it means, that you have fount external
device generating circuit of high through current
flow via USB. Then, it is re quired either to ground
common wire of detect ed device relatively to
computer housing or to isolate t his device
galvanically bu some means. See
recommendati ons i n Ch.6.

Appropriate mea sure s:
– Use in-phase EMC filter at output of r elevant
signal sourc e.

- Connect common wires of al l device s in one
groundi ng point by shortest way using wire of
maximum section.

- Use auxilary galvanic isolati on device of
minimum capacit y between part galvanically
isolated. See recommendations in Ch.

6.

fail ure of E20-10
equipment appeared
while operating with
E20-10 with your
software.

operate properly onE20-
10or E20-10 is actually
faulty.

E20-10 User Manual

programs d elivered by L-Card (or actually
applying provid ed programming exa mpl es). In
case the failure is confirmed, contact L-Card.

External appearance

of abnormal

Possible reasons

Tro uble s hoot i ng mea s u re s

When oper ating in

in your mea surement de sign

Take me asures to limit input voltage of E20-10

subrange of ±3 V
sig n if ic an t d isto r tio n s
occur during signa l
conversion,
meanwhile, the
operation of E20-10
module is restored
either upon switching
off and on the supply
voltage of E20-10, or
upon progra mmed
switc hover of the
measurement
subrange

voltage supplied to E20-10
input exceeds significantly
measurement range of
E20-10 having closed to
edges ±10 V of maximum
permissible voltage at E20­10 i nput or having exceeded
these edges.

signal.
If you provide detailed technical data on your
mea surement design L-Card technical support
consult on this issue.

will

8.1. How to be consulted

A tel e pho ne cal l t o L-CARD an d expla ini n g th e pro bl em " in la y pers on’ s t erm s" i s, a s a ru le, a

pure waste of time (both yours and another person's) because the specialist needs initial data
describ ing y our situa ti o n. T her e is a great amount of thes e initia l data (you can not remember all), so

it is extremely necessary to send them to L-Card

regular mail or personal delivery to

this b ook )

. The follow in g initia l data de scrib in g you r situa ti o n are requir e d:

L-Card, see the addresses on the reverse side of the title page of

in writing (email, website conference, fax,

• Your name and contact data.

• E20-10 serial number (see on the module body or relevant program-accessible information).

• What comput er (whic h c hipset) is used and what type of operating system is used.

• What sof tware and wha t device driver a re used (in dicate th e version and other information

which would help us to understand you).

• What softw are user settings of E20-10 are used (ADC conversion frequency, input subrange,

the number of channels sampled, duration of interframe delay, ADC synchronization and
data acquisition start modes).

• Exter na l c on n ections diagram (textual description of conne ctions or a diagram sketch),

numbers of connectors contacts and approximate length of wires must be specified.

• Wh at si gnal sources ar e used and what outp ut electrical parameters they have.

• Estimation o f levels of the signals applied to the product contacts, which type of signal is

used ( p oint out s peci fi c pa ramet er s of si gna l, if kn own, pu l s e or si nusoida l , s t ray or
periodica l , fr e quency bandw i d t h) .

• Under which conditions the product is being handled (laboratory, production).

• Describe the configuration of grounding circuits of the com puter , if the sour c e s of signals are

grounded and how.

• Finally, describe the observed negative impact providing this description with at least any

metric values or assessments!

If yo u do some work and pr ovide the s e c ompl et e i nitial da t a , our spe cia list wi l l b e ab l e to s en d

you the most accurate and correct answer within the shortest possible time!

9. Bibliography

1. E20-10 Progra m m er's manu a l . - М.: L-Card , 2008

2. Ga r manov A. V. Solutions of problems on elec tro-compatibility and interference protection during

connection of meas uring eq uipment th ro ugh the example of L -Card compa n y pr o duct. M.: L-

Card , 2002

3. E20-10 module. Typica l connection examples

4. Garmanov A. V. Experience of signa l/ interference ratio improvement during connection of AD C

in real practic e M.: M.: L -Card, 2010.

5. Terminology - is a periodic ally upd a ted L-Card webs ite section.

6. FAQ (frequency asked questions)- is a periodically updated L-Card web s i te se ction .

7. National Semiconductor. A Practical Guide To Cable Selection. - Appl ication No te 916

8. National Instruments. Field Wiring and Noise Considerations for Analog Signals. -Application

Note 25

9. National Instruments. Signal Conditioning Fundamentals for PC-Based Data Acquisition Systems.

- Application Note 48

10. Universal Serial Bus Specification. - Rev. 1.1, Sept . 1998

11. Universal Serial Bus Specification. - Rev. 2.0, April 2000

E20-10 User Manual

List o f t ables

Table5-1. Modes of synchronization on ADC conversion frequency (on SYNC signal) ..................... 32

Table5-2. Acquisition start synchronization modes (on START signal) ............................................... 32

Table 5-3. C a pa b i lity to se t additional permit condition s for ADC da t a re cording in bu f f er me m ory

E20-10: ................................................................................................................................................ 33

Table5-4. "On level" synchronization modes............................................................................................ 33

Table5-5. Acquisition stopping conditions................................................................................................ 34

Table. 6-1.On conne ctors analog signal assignment ................................................................................. 42

Table 6-2. Connector DIGITAL I/O signals ............................................................................................. 44

Table 6-3. Characteristi cs of signal lines inputs and outputs , op er a ting m od e ....................................... 45

Table 6-4. Characteristics of signal lines inputs and outputs, off mode .................................................. 46

Table6-5. Ma ximum permis sible through currents ................................................................................... 47

Table 6-6. External power supply input characteristics............................................................................ 47

Table 6-7. External power supply outputs characteristic.......................................................................... 48

List of fi gures

Fig. 3-1. E20-10 revision А appearance .................................................................................................. 15

Fig. 3-2. E20-10 revision В appearance .................................................................................................. 15

Fig. 5-1. Block diagr am E20-10 ................................................................................................................. 27

Fig. 5-2. Explanation of data acquisition equipment logic interaction in E20-10 .................................. 27

Fig. 5-3. Syn c hroniza tion m od e diagrams ................................................................................................. 36

Fig. 6-1. Analog input connectors .............................................................................................................. 41

Fig. 6-2. Analog output connectors............................................................................................................ 41

Fig. 6-3. Digital signal and external power connectors ............................................................................ 43

Fig. 6-4. Circuits GND, GND* and AGND .............................................................................................. 51

Fig. 6-5. Equivalent circuits of ADC input circuit via constant current (differences in revisions A and

B) ......................................................................................................................................................... 52