Lattice Semiconductor Corporation PALCE20V8H-25PC-4, PALCE20V8H-5JC-5, PALCE20V8H-7JC-5, PALCE20V8H-7PC-5, PALCE20V8Q-15JC-4 Datasheet

COM'L: H-5/7/10/15/25, Q-10/15/25 IND: H-15/25, Q-20/25

PALCE20V8 Family

EE CMOS 24-Pin Universal
Programmable Array Logic

DISTINCTIVE CHARACTERISTICS

Pin and function compatible with all PAL®

◆

Electrically erasable CMOS technology provides reconfigurable logic and full testability

◆

◆

High-speed CMOS technology

— 5-ns propagation delay for “-5” version
— 7.5-ns propagation delay for “-7” version

◆

Direct plug-in replacement for a wide range of 24-pin PAL devices

◆

Programmable enable/disable control

◆

Outputs individually programmable as registered or combinatorial
Peripheral Component Interconnect (PCI) compliant

◆

◆

Preloadable output registers for testability

◆

Automatic register reset on power-up
Cost-effective 24-pin plastic SKINNY DIP and 28-pin PLCC packages

◆

Extensive third-party software and programmer support

◆

◆

Fully tested for 100% programming and functional yields and high reliability

◆

Programmable output polarity
5-ns version utilizes a split leadframe for improved performance

◆

20V8 devices

GENERAL DESCRIPTION

The PALCE20V8 is an advanced PAL
erasable CMOS technology. Its macrocells provide a universal device architecture. The
PALCE20V8 is fully compatible with the GAL20V8 and can directly replace PAL20R8 series
devices and most 24-pin combinatorial PAL devices.

device built with low-power, high-speed, electrically-

Device logic is automatically configured according to the user’s design specification. A design is
implemented using any of a number of popular design software packages, allowing automatic
creation of a programming file based on Boolean or state equations. Design software also verifies
the design and can provide test vectors for the finished device. Programming can be
accomplished on standard PAL device programmers.

The P ALCE20V8 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to
implement complex logic functions easily and efficiently. Multiple levels of combinatorial logic
can always be reduced to sum-of-products form, taking advantage of the very wide input gates
available in PAL devices. The equations are programmed into the device through floating-gate
cells in the AND logic array that can be erased electrically.

Publication# 16491 Rev: E
Amendment/0 Issue Date: November 1998

The fixed OR array allows up to eight data product terms per output for logic functions. The
sum of these products feeds the output macrocell. Each macrocell can be programmed as
registered or combinatorial with an active-high or active-low output. The output configuration
is determined by two global bits and one local bit controlling four multiplexers in each
macrocell.

BLOCK DIAGRAM

– I

I

1

10

10

CLK/I

0

OE/I

Input
Mux.

11

Programmable AND Array

MACRO
MC

0

I

12

I/O

0

MACRO

MC

1

I/O

1

MACRO

MC

2

I/O

2

MACRO

MC

3

I/O

40 x 64

3

MACRO

MC

4

I/O

MACRO

MC

5

4

I/O

5

MACRO

MC

6

I/O

MACRO

MC

7

6

I/O

Input
Mux.

7

I

13

16491E

FUNCTIONAL DESCRIPTION

The PALCE20V8 is a universal PAL device. It has eight independently configurable macrocells

-MC

(MC

0

combinatorial I/O, or dedicated input. The programming matrix implements a programmable
AND logic array, which drives a fixed OR logic array. Buffers for device inputs have
complementary outputs to provide user-programmable input signal polarity. Pins 1 and 13 serve
either as array inputs or as clock (CLK) and output enable (OE

). Each macrocell can be configured as a registered output, combinatorial output,

7

) for all flip-flops.

Unused input pins should be tied directly to V

or GND. Product terms with all bits

CC

unprogrammed (disconnected) assume the logical HIGH state, and product terms with both true
and complement of any input signal connected assume a logical LOW state.

The programmable functions on the PALCE20V8 are automatically configured from the user’s
design specification, which can be in a number of formats. The design specification is processed

2 PALCE20V8 Family

by development software to verify the design and create a programming file. This file, once
downloaded to a programmer, configures the device according to the user’s desired function.

The user is given two design options with the PALCE20V8. First, it can be programmed as an
emulated PAL device. This includes the PAL20R8 series and most 24-pin combinatorial PAL
devices. The PAL device programmer manufacturer will supply device codes for the standard
P AL architectures to be used with the P ALCE20V8. The programmer will program the P ALCE20V8
to the corresponding PAL device architecture. This allows the user to use existing standard PAL
device JEDEC files without making any changes to them. Alternatively, the device can be
programmed directly as a P ALCE20V8. Here the user must use the PALCE20V8 device code. This
option provides full utilization of the macrocells, allowing non-standard architectures to be built.

To

Adjacent

Macrocell

1 1
0 X

1 0

OE

V

CC

1 1
1 0
0 0

0 1

SL0

X

SG1

DQ

SL1

X

*In macrocells MC0 and MC7, SG1 is replaced by SG0 on the feedback multiplexer.

CLK

Q

Figure 1. PALCE20V8 Macrocell

*SG1

1 1
0 X

1 0

1 0
1 1
0 X

SL0

I/O

X

From

X

Adjacent
Pin

16491E

PALCE20V8 Family 3

CONFIGURATION OPTIONS

Each macrocell can be configured as one of the following: registered output, combinatorial
output, combinatorial I/O or dedicated input. In the registered output configuration, the output
buffer is enabled by the OE
by a product term or always enabled. In the dedicated input configuration, the buffer is always
disabled. A macrocell configured as a dedicated input derives the input signal from an adjacent
I/O.

The macrocell configurations are controlled by the configuration control word. It contains 2
global bits (SG0 and SG1) and 16 local bits (SL0
determines whether registers will be allowed. SG1 determines whether the PALCE20V8 will
emulate a P AL20R8 family or a combinatorial device. Within each macrocell, SL0
with SG1, selects the configuration of the macrocell and SL1
or active high.

The configuration bits work by acting as control inputs for the multiplexers in the macrocell.
There are four multiplexers: a product term input, an enable select, an output select, and a
feedback select multiplexer. SG1 and SL0
and MC

, SG0 replaces SG1 on the feedback multiplexer.

7

These configurations are summarized in Table 1 and illustrated in Figure 2.

pin. In the combinatorial configuration, the buffer is either controlled

through SL0

0

are the control signals for all four multiplexers. In MC

x

and SL1

7

sets the output as either active low

x

through SL1

0

, in conjunction

x

). SG0

7

0

If the P ALCE20V8 is configured as a combinatorial device, the CLK and OE pins may be available
as inputs to the array. If the device is configured with registers, the CLK and OE

pins cannot be

used as data inputs.

Registered Output Configuration

The control bit settings are SG0 = 0, SG1 = 1 and SL0

= 0. There is only one registered

x

configuration. All eight product terms are available as inputs to the OR gate. Data polarity is

. SL1

determined by SL1
flop. SL1

is programmed as 1 for inverted output or 0 for non-inverted output. The flip-flop is

x

x

loaded on the LOW-to-HIGH transition of CLK. The feedback path is from Q
output buffer is enabled by OE

is an input to the exclusive-OR gate which is the D input to the flip-

x

on the register. The

.

Combinatorial Configurations

The PALCE20V8 has three combinatorial output configurations: dedicated output in a non­registered device, I/O in a non-registered device and I/O in a registered device.

Dedicated Output in a Non-Registered Device

The control settings are SG0 = 1, SG1 = 0, and SL0

= 0. All eight product terms are available to

x

the OR gate. Although the macrocell is a dedicated output, the feedback is used, with the
exception of pins 18(21) and 19(23). Pins 18(21) and 19(23) do not use feedback in this mode.

Note:

1. The pin number without parentheses refers to the SKINNY DIP package. The pin number in parentheses refers to the PLCC
package.

4 PALCE20V8 Family

Dedicated Input in a Non-Registered Device

The control bit settings are SG0 = 1, SG1 = 0 and SL0

= 1. The output buffer is disabled. The

x

feedback signal is an adjacent I/O pin.

Combinatorial I/O in a Non-Registered Device

The control settings are SG0 = 1, SG1 = 1, and SL0

= 1. Only seven product terms are available

x

to the OR gate. The eighth product term is used to enable the output buffer. The signal at the
I/O pin is fed back to the AND array via the feedback multiplexer. This allows the pin to be used
as an input.

Combinatorial I/O in a Registered Device

The control bit settings are SG0=0,SG1=1 and SL0

=1. Only seven product terms are available

x

to the OR gate. The eighth product term is used as the output enable. The feedback signal is the
corresponding I/O signal.

Table 1. Macrocell Configuration

Cell

SG0 SG1 SL0

Device Uses Registers Device Uses No Registers

0 1 0 Registered Output

011

X

Configuration

Combinatorial

I/O

Devices

Emulated SG0 SG1 SL0

PAL20R8, 20R6,

20R4

PAL20R6, 20R4 1 0 1 Input PAL20L2, 18L4, 16L6

100

X

Cell

Configuration

Combinatorial

Output

Devices

Emulated

PAL20L2, 18L4,

16L6, 14L8

111

Combinatorial

I/O

PAL20L8

PALCE20V8 Family 5

OE

CLK

a. Registered active Low

DQQ

OE

DQQ

CLK

b. Registered active high

c. Combinatorial I/O active low d. Combinatorial I/O active high

V

CC

Note 1 Note 1

e. Combinatorial output active low

Notes:

1. Feedback is not available on pins 18 (21) and 19 (23) in
the combinatorial output mode.

2. This macrocell configuration is not available on pins
18 (21) and 19 (23).

Figure 2. Macrocell Configurations

V

CC

f. Combinatorial output active high

Note 2

Adjacent I/O Pin

g. Dedicated input

16491E

6 PALCE20V8 Family

Power-Up Reset

All flip-flops power up to a logic LOW for predictable system initialization. Outputs of the
PALCE20V8 depend on whether they are selected as registered or combinatorial. If registered is
selected, the output will be HIGH. If combinatorial is selected, the output will be a function of
the logic.

Register Preload

The register on the PALCE20V8 can be preloaded from the output pins to facilitate functional
testing of complex state machine designs. This feature allows direct loading of arbitrary states,
making it unnecessary to cycle through long test vector sequences to reach a desired state. In
addition, transitions from illegal states can be verified by loading illegal states and observing
proper recovery.

Security Bit

A security bit is provided on the P ALCE20V8 as a deterrent to unauthorized copying of the array
configuration patterns. Once programmed, this bit defeats readback and verification of the
programmed pattern by a device programmer, securing proprietary designs from competitors.
The bit can only be erased in conjunction with the array during an erase cycle.

Electronic Signature Word

An electronic signature word is provided in the PALCE20V8. It consists of 64 bits of
programmable memory that can contain any user-defined data. The signature data is always
available to the user independent of the security bit.

Programming and Erasing

The PALCE20V8 can be programmed on standard logic programmers. It also may be erased to
reset a previously configured device back to its unprogrammed state. Erasure is automatically
performed by the programming hardware. No special erase operation is required.

Quality and Testability

The P ALCE20V8 offers a very high level of built-in quality. The erasability of the device provides
a direct means of verifying performance of all AC and DC parameters. In addition, this verifies
complete programmability and functionality of the device to provide the highest programming
and post-programming functional yields in the industry.

Technology

The high-speed P ALCE20V8H is fabricated with V antis’ advanced electrically erasable (EE) CMOS
process. The array connections are formed with proven EE cells. Inputs and outputs are
designed to be compatible with TTL devices. This technology provides strong input clamp
diodes, output slew-rate control, and a grounded substrate for clean switching.

PCI Compliance

PALCE20V8H devices in the -5/-7/-10 speed grades are fully compliant with the PCI Local Bus

Specification

published by the PCI Special Interest Group. The P ALCE20V8H’s predictable timing
ensures compliance with the PCI AC specifications independent of the design. On the other
hand, in CPLD and FPGA architectures without predictable timing, PCI compliance is dependent
upon routing and product term distribution.

PALCE20V8 Family 7

LOGIC DIAGRAM

CLK/I

0 3 4 7 8 1112 1516 1920 2324 2728 3132 3536 39

1

0

(2)

I

2

1

(3)

0

7

I

3

2

(4)

8

15

I

3

4

(5)

16

23

I

4

5

(6)

SG0

1
0

1 1

1 1
0 X

1 0

SL0

7

SG1

DQ

1 1
0 X

1 0

SL0

6

SG1

DQ

1 1
0 X

1 0

SL0

5

SG1

DQ

1 0
0 0

V

CC

0 1

1 1

0 X
1 0

Q

1 0
1 1
0 X

SG0

SL0

7

1 1
1 0
0 0

V

CC

0 1

1 1
0 X

1 0

Q

1 0

1 1

0 X

SG1

SL0

6

1 1
1 0
0 0

V

CC

0 1

1 1
0 X

1 0

Q

1 0
1 1

0 X

SG1

SL0

5

(28)

23
(27)

24

V

CC

I

13

I/O

22

7

(26)

I/O

21

6

(25)

I/O

20

5

(24)

24

31

I

6

5

(7)

03478111215161920 2427283132353639

23

8 PALCE20V8 Family

1 1

1 1
0 X

1 0

SL0

4

SG1

DQ

1 0
0 0

V

CC

0 1

1 1
0 X

1 0

Q

1 0
1 1

0 X

SG1

SL0

4

(23)

I/O

19

4

CLK OE

16491E

LOGIC DIAGRAM (CONTINUED)

0 3 4 7 8 11121516192023242728 3132353639

1 1

0 X

1 0

32

39

7

I

6

(9)

1 1

0 X

1 0

40

47

I

8

7

(10)

1 1

0 X

1 0

48

55

9

I

8

(11)

SG1

SG1

SG1

CLK OE

SL0

SL0

SL0

1 1
1 0
0 0

V

CC

0 1

3

1 1

DQ

Q

0 X
1 0

1 0
1 1

0 X

SG1

SL0

3

1 1
1 0
0 0

V

CC

0 1

18

(21)

I/O

3

2

1 1

DQ

Q

0 X

1 0

1 0
1 1
0 X

SG1

SL0

2

1 1
1 0
0 0

V

CC

0 1

17

(20)

I/O

2

1

1 1

DQ

Q

SG1

0 X
1 0

1 0
1 1
0 X

SL0

1

16

(19)

I/O

1

1 1

1 1

0 X

1 0

SL0

56

SG1

0

DQ

63

I

10

9

(12)

11

10

(13)

0 3 4 7 8 1112 1516 1920 2324 2728 3132 3536

39

SG0

0
1

1 0
0 0

V

CC

0 1

1 1
0 X

1 0

Q

1 0
1 1

0 X

SL0

SG0

0

(18)

14

(17)

13

(16)

I/O

15

0

I

12

OE/I

11

16491E-4

(concluded)

PALCE20V8 Family 9

ABSOLUTE MAXIMUM RATINGS

Storage Temperature. . . . . . . . . . . . . .-65 ° C to +150 ° C

Ambient Temperature

with Power Applied . . . . . . . . . . . . . .-55 ° C to +125 ° C

Supply Voltage

with Respect to Ground . . . . . . . . . . -0.5 V to +7.0 V

DC Input Voltage . . . . . . . . . . . -0.5 V to V

DC Output or I/O

Pin Voltage . . . . . . . . . . . . . . . . .-0.5 V to V

+ 0.5 V

CC

+ 0.5 V

CC

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (TA) Operating

in Free Air. . . . . . . . . . . . . . . . . . . . . . . 0°C to +75°C

Supply Voltage (VCC)

with Respect to Ground . . . . . . . . . +4.75 V to +5.25 V

Operating ranges define those limits between which the
functionality of the device is guaranteed.

Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V

Latchup Current (T

Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum
Ratings for extended periods may affect device reliability.
Programming conditions may differ.

= 0 °

C to 75°C) . . . . . . . . . 100 mA

A

DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES

Parameter

Symbol Parameter Description Test Description Min Max Unit

V

OH

V

OL

V

IH

V

IL

I

IH

I

IL

I

OZH

I

OZL

I

SC

I

CC

(Static)
I

CC

(Dynamic)

Output HIGH Voltage IOH = -3.2 mA, V

= VIH or VIL, VCC = Min 2.4 V

IN

Output LOW Voltage IOL = 24 mA, VIN = VIH or VIL, VCC = Min 0.5 V

Input HIGH Voltage

Input LOW Voltage

Input HIGH Leakage Current VIN = 5.25 V, V
Input LOW Leakage Current VIN = 0 V, V

Off-State Output Leakage Current HIGH

Off-State Output Leakage Current LOW

Output Short-Circuit Current V

Supply Current for -5

Supply Current for -7 and -10

Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)

Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)

= Max (Note 2) 10 µA

CC

= Max (Note 2) –100 µA

CC

= 5.25 V, VCC = Max

V

OUT

V

= V

or VIL (Note 2)

IN

IH

= 0 V, V

V

OUT

V

= V

IN

= 0.5 V, VCC = Max (Note 3) –30 –150 mA

OUT

Outputs Open (I
V

= Max

CC

Outputs Open (I
V

= Max, f = 25 MHz

CC

= Max

CC

or VIL (Note 2)

IH

OUT

OUT

= 0 mA), V

= 0 mA),

IN

= 0 V

2.0 V

0.8 V

10 µA

–100 µA

125 mA

115 mA

Notes:

1. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included.

2. I/O pin leakage is the worst case of I

and I

IL

(or IIH and I

OZL

OZH

).

3. Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.

= 0.5 V has been chosen to avoid test problems caused by tester ground degradation.

V

OUT

10 PALCE20V8H-5/7/10 (Com’l)

CAPACITANCE

1

Parameter

Symbol Parameter Description Test Conditions Typ Unit

C
C

IN
OUT

Input Capacitance V
Output Capacitance V

= 2.0 V

IN

= 2.0 V 8 pF

OUT

= 5.0 V, TA = 25°C,

V

CC

f = 1 MHz

5pF

Note:

1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where

capacitance may be affected.

SWITCHING CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES

Parameter

Symbol Parameter Description

t

PD

t

S

t

H

t

CO

t

SKEWR

t

WL

t

WH

Input or Feedback to Combinatorial Output 1 5 3 7.5 3 10 ns
Setup Time from Input or Feedback to Clock 3 5 7.5 ns
Hold Time 0 0 0 ns
Clock to Output 141537.5ns
Skew Between Registered Outputs (Note 3) 1 1 1 ns

LOW 3 4 6 ns

Clock Width

HIGH 3 4 6 ns
External Feedback 1/(t

f

MAX

Maximum
Frequency
(Note 4)

Internal Feedback
(f

)

CNT

No Feedback 1/(t

t

PZX

t

PXZ

t

EA

t

ER

OE to Output Enable 1616210ns
OE to Output Disable 1516210ns
Input to Output Enable Using Product Term Control 2639310ns
Input to Output Disable Using Product Term Control 2539310ns

) 142.8 100 66.7 MHz

S+tCO

) (Note 5) 166 125 71.4 MHz

1/(t

S+tCF

) 166 125 83.3 MHz

WH+tWL

-5 -7 -10

2

Max Min

2

Max Min

2

Max

1

UnitMin

Notes:

1. See “Switching Test Circuit” for test conditions.

2. Output delay minimums for t

PD

, tCO, t

PZX

, t

, tEA, and tER are defined under best case conditions. Future process improvements

PXZ

may alter these values; therefore, minimum values are recommended for simulation purposes only.

3. Skew testing takes into account pattern and switching direction differences between outputs that have equal loading.

4. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where

frequency may be affected.

is a calculated value and is not guaranteed. tCF can be found using the following equation:

5. t

CF

t

CF

= 1/f

(internal feedback) – tS.

MAX

PALCE20V8H-5/7/10 (Com’l) 11

ABSOLUTE MAXIMUM RATINGS

OPERATING RANGES

Storage Temperature. . . . . . . . . . . . . .-65°C to +150°C

Ambient Temperature

with Power Applied . . . . . . . . . . . . . .-55°C to +125°C

Supply Voltage

with Respect to Ground . . . . . . . . . . -0.5 V to +7.0 V

DC Input Voltage . . . . . . . . . . . -0.5 V to V

+ 0.5 V

CC

DC Output or I/O

Commercial (C) Devices

Ambient Temperature (TA)

Operating in Free Air. . . . . . . . . . . . . . . 0°C to +75°C

Supply Voltage (VCC)

with Respect to Ground . . . . . . . . . +4.75 V to +5.25 V

Operating ranges define those limits between which the
functionality of the device is guaranteed.

Pin Voltage . . . . . . . . . . . . . . . . .-0.5 V to VCC + 0.5 V

Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V

Latchup Current (TA = 0°C to 75°C) . . . . . . . . . 100 mA

Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum
Ratings for extended periods may affect device reliability.
Programming conditions may differ.

DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES

Parameter

Symbol Parameter Description Test Description Min Max Unit

V

OH

V

OL

V

IH

Output HIGH Voltage IOH = -3.2 mA, VIN = VIH or VIL, VCC = Min 2.4 V
Output LOW Voltage IOL = 24 mA, VIN = VIH or VIL, VCC = Min 0.5 V

Input HIGH Voltage

Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)

2.0 V

V

IL

I

IH

I

IL

I

OZH

I

OZL

I

SC

I

CC

(Dynamic)

Input LOW Voltage

Input HIGH Leakage Current VIN = 5.25 V, V
Input LOW Leakage Current VIN = 0 V, V

Off-State Output Leakage Current HIGH

Off-State Output Leakage Current LOW

Output Short-Circuit Current V

Supply Current for -10

Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)

= Max (Note 2) 10 µA

CC

= Max (Note 2) –100 µA

CC

= 5.25 V, VCC = Max

V

OUT

V

= V

or VIL (Note 2)

IN

IH

= 0 V, V

V

OUT

V

= V

IN

= 0.5 V, VCC = Max (Note 3) –30 –150 mA

OUT

Outputs Open (I
V

= Max, f = 15 MHz (Note 4)

CC

= Max

CC

or VIL (Note 2)

IH

OUT

= 0 mA),

0.8 V

10 µA

–100 µA

55 mA

Notes:

1. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included.

2. I/O pin leakage is the worst case of I

and I

IL

(or IIH and I

OZL

OZH

).

3. Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.

= 0.5 V has been chosen to avoid test problems caused by tester ground degradation.

V

OUT

4. This parameter is guaranteed worst case under test conditions. Refer to the I

vs. frequency graph for typical measurements.

CC

12 PALCE20V8Q-10 (Com’l)

CAPACITANCE

1

Parameter

Symbol Parameter Description Test Conditions Typ Unit

C
C

IN
OUT

Input Capacitance V
Output Capacitance V

= 2.0 V

IN

= 2.0 V 8 pF

OUT

= 5.0 V, TA = 25°C,

V

CC

f = 1 MHz

5pF

Note:

1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where

capacitance may be affected.

SWITCHING CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES

Parameter

Symbol Parameter Description

t

PD

t

S

t

H

t

CO

t

WL

t

WH

Input or Feedback to Combinatorial Output 310ns
Setup Time from Input or Feedback to Clock 7.5 ns
Hold Time 0ns
Clock to Output 3 7.5 ns

LOW 6ns

Clock Width

HIGH 6ns
External Feedback 1/(t

f

MAX

Maximum Frequency
(Note 3)

Internal Feedback (f

) 1/(tS+tCF) (Note 4) 71.4 MHz

CNT

) 66.7 MHz

S+tCO

-10

2

Max

1

UnitMin

No Feedback 1/(tWH+tWL) 83.3 MHz

t

PZX

t

PXZ

t

EA

t

ER

OE to Output Enable 210ns
OE to Output Disable 210ns
Input to Output Enable Using Product Term Control 310ns
Input to Output Disable Using Product Term Control 310ns

Notes:

1. See “Switching Test Circuit” for test conditions.

2. Output delay minimums for t

PD

, tCO, t

PZX

, t

, tEA, and tER are defined under best case conditions. Future process improvements

PXZ

may alter these values; therefore, minimum values are recommended for simulation purposes only.

3. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where

frequency may be affected.

is a calculated value and is not guaranteed. tCF can be found using the following equation:

4. t

CF

t

CF

= 1/f

(internal feedback) – tS.

MAX

PALCE20V8Q-10 (Com’l) 13

ABSOLUTE MAXIMUM RATINGS

OPERATING RANGES

Storage Temperature. . . . . . . . . . . . . .-65°C to +150°C

Ambient Temperature

with Power Applied . . . . . . . . . . . . . .-55°C to +125°C

Supply Voltage

with Respect to Ground . . . . . . . . . . -0.5 V to +7.0 V

DC Input Voltage . . . . . . . . . . . -0.5 V to V

+ 0.5 V

CC

DC Output or I/O

Commercial (C) Devices

Ambient Temperature (TA) Operating

in Free Air. . . . . . . . . . . . . . . . . . . . . . . 0°C to +75°C

Supply Voltage (VCC)

with Respect to Ground . . . . . . . . . +4.75 V to +5.25 V

Operating ranges define those limits between which the
functionality of the device is guaranteed.

Pin Voltage . . . . . . . . . . . . . . . . .-0.5 V to VCC + 0.5 V

Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V

Latchup Current (TA = 0°C to 75°C) . . . . . . . . . 100 mA

Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum
Ratings for extended periods may affect device reliability.
Programming conditions may differ.

DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES

Parameter

Symbol Parameter Description Test Description Min Max Unit

V

OH

V

OL

V

IH

Output HIGH Voltage IOH = -3.2 mA, VIN = VIH or VIL, VCC = Min 2.4 V
Output LOW Voltage IOL = 24 mA, VIN = VIH or VIL, VCC = Min 0.5 V

Input HIGH Voltage

Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)

2.0 V

V

I
I

I

I

I

I

IL

IH

IL

OZH

OZL

SC

CC

Input LOW Voltage

Input HIGH Leakage Current VIN = 5.25 V, V
Input LOW Leakage Current VIN = 0 V, V

Off-State Output Leakage Current HIGH

Off-State Output Leakage Current LOW

Output Short-Circuit Current V

Supply Current

Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)

= Max (Note 2) 10 µA

CC

= Max (Note 2) –100 µA

CC

= 5.25 V, VCC = Max

V

OUT

V

= V

or VIL (Note 2)

IN

IH

= 0 V, V

V

OUT

V

= V

IN

= 0.5 V, VCC = Max (Note 3) –30 –150 mA

OUT

Outputs Open (I
V

= Max, f = 15 MHz

CC

= Max

CC

or VIL (Note 2)

IH

OUT

= 0 mA),

H90
Q55

0.8 V

10 µA

–100 µA

Notes:

1. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included.

2. I/O pin leakage is the worst case of I

and I

IL

(or IIH and I

OZL

OZH

).

3. Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.

= 0.5 V has been chosen to avoid test problems caused by tester ground degradation.

V

OUT

mA

14 PALCE20V8H-15/25 Q-15/25 (Com’l)

CAPACITANCE

1

Parameter

Symbol Parameter Description Test Conditions Typ Unit

C
C

IN
OUT

Input Capacitance V
Output Capacitance V

= 2.0 V

IN

= 2.0 V 8 pF

OUT

= 5.0 V, TA = 25°C,

V

CC

f = 1 MHz

5pF

Note:

1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where

capacitance may be affected.

SWITCHING CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES

Parameter

Symbol Parameter Description

t
t
t
t
t
t

f

PD

S

H

CO

WL

WH

MAX

Input or Feedback to Combinatorial Output 15 25 ns
Setup Time from Input or Feedback to Clock 12 15 ns
Hold Time 0 0 ns
Clock to Output 10 12 ns

LOW 8 12 ns

Clock Width

HIGH 8 12 ns

Maximum
Frequency
(Note 2)

External Feedback 1/(t
Internal Feedback (f

) 1/(tS+tCF) (Note 3) 50 40 MHz

CNT

No Feedback 1/(tWH+tWL) 62.5 41.6 MHz

) 45.5 37 MHz

S+tCO

-15 -25

1

UnitMin Max Min Max

t

PZX

t

PXZ

t

EA

t

ER

OE to Output Enable 15 20 ns
OE to Output Disable 15 20 ns
Input to Output Enable Using Product Term Control 15 25 ns
Input to Output Disable Using Product Term Control 15 25 ns

Notes:

1. See “Switching Test Circuit” for test conditions.

2. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where

frequency may be affected.

is a calculated value and is not guaranteed. tCF can be found using the following equation:

3. t

CF

t

CF

= 1/f

(internal feedback) – tS.

MAX

PALCE20V8H-15/25 Q-15/25 (Com’l) 15

ABSOLUTE MAXIMUM RATINGS

OPERATING RANGES

Storage Temperature. . . . . . . . . . . . . .-65°C to +150°C

Ambient Temperature

with Power Applied . . . . . . . . . . . . . .-55°C to +125°C

Supply Voltage

with Respect to Ground . . . . . . . . . . -0.5 V to +7.0 V

DC Input Voltage . . . . . . . . . . . -0.5 V to V

+ 0.5 V

CC

DC Output or I/O

Industrial (I) Devices

Ambient Temperature (TA) Operating

in Free Air. . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C

Supply Voltage (VCC)

with Respect to Ground . . . . . . . . . . . +4.5 V to +5.5 V

Operating ranges define those limits between which the
functionality of the device is guaranteed.

Pin Voltage . . . . . . . . . . . . . . . . .-0.5 V to VCC + 0.5 V

Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V

Latchup Current (TA = -40°C to +85°C) . . . . . . 100 mA

Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum
Ratings for extended periods may affect device reliability.
Programming conditions may differ.

DC CHARACTERISTICS OVER INDUSTRIAL OPERATING RANGES

Parameter

Symbol Parameter Description Test Description Min Max Unit

V
V
V
V
I
I
I
I
I

I

OH

OL

IH

IL

IH

IL

OZH

OZL

SC

CC

Output HIGH Voltage IOH = -3.2 mA, VIN = VIH or VIL, VCC = Min 2.4 V
Output LOW Voltage IOL = 24 mA, VIN = VIH or VIL, VCC = Min 0.5 V
Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) 2.0 V
Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) 0.8 V
Input HIGH Leakage Current VIN = 5.5 V, V
Input LOW Leakage Current VIN = 0 V, V
Off-State Output Leakage Current HIGH V
Off-State Output Leakage Current LOW V
Output Short-Circuit Current V

Supply Current

= 5.5 V, VCC = Max , VIN = V

OUT

= 0 V, V

OUT

= 0.5 V, VCC = Max (Note 3) –30 –150 mA

OUT

Outputs Open (I
V

= Max, f = 15 MHz

CC

= Max (Note 2) 10 µA

CC

= Max (Note 2) –100 µA

CC

or VIL (Note 2) 10 µA

IH

= Max , VIN = V

CC

= 0 mA),

OUT

or VIL (Note 2) –100 µA

IH

H 130
Q65

mA

Notes:

1. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included.

2. I/O pin leakage is the worst case of I

and I

IL

(or IIH and I

OZL

OZH

).

3. Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.

= 0.5 V has been chosen to avoid test problems caused by tester ground degradation.

V

OUT

16 PALCE20V8H-15/25 Q-20/25 (ind)

CAPACITANCE

1

Parameter

Symbol Parameter Description Test Conditions Typ Unit

C
C

IN
OUT

Input Capacitance V
Output Capacitance V

= 2.0 V

IN

= 2.0 V 8 pF

OUT

= 5.0 V, TA = 25°C,

V

CC

f = 1 MHz

5pF

Note:

1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where

capacitance may be affected.

SWITCHING CHARACTERISTICS OVER INDUSTRIAL OPERATING RANGES

Parameter

Symbol Parameter Description

t

PD

t

S

t

H

t

CO

t

WL

t

WH

Input or Feedback to Combinatorial Output 15 20 25 ns
Setup Time from Input or Feedback to Clock 12 13 15 ns
Hold Time 0 0 0 ns
Clock to Output 10 11 12 ns

LOW 8 10 12 ns

Clock Width

HIGH 8 10 12 ns
External Feedback 1/(t

f

MAX

Maximum
Frequency
(Note 2)

Internal Feedback
(f

)

CNT

No Feedback 1/(t

t

PZX

t

PXZ

t

EA

t

ER

OE to Output Enable 15 18 20 ns
OE to Output Disable 15 18 20 ns
Input to Output Enable Using Product Term Control 15 18 25 ns
Input to Output Disable Using Product Term Control 15 18 25 ns

) 45.5 41.6 37 MHz

S+tCO

) (Note 3) 50 45.4 40 MHz

1/(t

S+tCF

) 62.5 50.0 41.6 MHz

WH+tWL

-15 -20 -25

1

UnitMin Max Min Max Min Max

Notes:

1. See “Switching Test Circuit” for test conditions.

2. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where

frequency may be affected.

is a calculated value and is not guaranteed. tCF can be found using the following equation:

3. t

CF

t

CF

= 1/f

(internal feedback) – tS.

MAX

PALCE20V8H-15/25 Q-20/25 (ind) 17

SWITCHING WAVEFORMS

V

T

Input or

Feedback

Registered

Output

b. Registered output

t

S

t

CO

V

T

t

H

V

T

Clock

16491E-6

V

T

V

T

Input

Output

d. Input to output disable/enable

t

ER

t

EA

V

OH

– 0.5V

V

OL

+ 0.5V

16491E-8

Input or

Feedback

Combinatorial

Output

Clock

V

T

t

PD

a. Combinatorial output

t

WH

t

WL

c. Clock width

V

T

16491E-5

V

T

16491E-7

OE

t

PXZ

Output

e. OE to output disable/enable

Notes:

1. V

= 1.5 V

T

2. Input pulse amplitude 0 V to 3.0 V.

3. Input rise and fall times 2 ns to 5 ns typical.

18 PALCE20V8 Family

V
V

OH
OL

– 0.5V
+ 0.5V

V

T

t

PZX

V

T

16491E-9

KEY TO SWITCHING WAVEFORMS

WAVEFORM INPUTS OUTPUTS

SWITCHING TEST CIRCUIT

5 V

Must be
Steady

May
Change
from H to L

May
Change
from L to H

Don’t Care,
Any Change
Permitted

Does Not
Apply

Will be
Steady

Will be
Changing
from H to L

Will be
Changing
from L to H

Changing,
State
Unknown

Center
Line is High­Impedance
“Off” State

KS000010-PAL

S

1

Specification S

tPD, t

CO

t

, t

PZX

EA

t

, t

PXZ

ER

R

1

Output

C

L

R

2

Commercial

1

C

L

1

R

2

Measured Output ValueR

Closed

Z → H: Open

Z → L: Closed

H → Z: Open

50 pF

390 Ω

200 Ω

H → Z: VOH – 0.5 V

5 pF H-5: 200 Ω

L → Z: Closed L → Z: V

16491E-10

1.5 V

1.5 V

+ 0.5 V

OL

PALCE20V8 Family 19

TYPICAL ICC CHARACTERISTICS

VCC = 5 V, TA = 25°C

150

(mA)

CC

I

125

100

75

50

25

20V8H-5

20V8H-7

20V8H-10
20V8H-15/25

20V8Q-15/25

0

01020304050

Frequency (MHz)

16491E-11

ICC vs. Frequency

The selected “typical” pattern utilized 50% of the device resources. Half of the macrocells were programmed as registered, and the
other half were programmed as combinatorial. Half of the available product terms were used for each macrocell. On any vector, half
of the outputs were switching.

By utilizing 50% of the device, a midpoint is defined for I
estimate the I

requirements for a particular design.

CC

. From this midpoint, a designer may scale the ICC graphs up or down to

CC

20 PALCE20V8 Family

ENDURANCE CHARACTERISTICS

The P ALCE20V8 is manufactured using Vantis’ advanced electrically-erasable (EE) CMOS process.
This technology uses an EE cell to replace the fuse link used in bipolar parts. As a result, the
device can be erased and reprogrammed—a feature which allows 100% testing at the factory.

Symbol Parameter Test Conditions Value Unit

t

DR

N Max Reprogramming Cycles Normal Programming Conditions 100 Cycles

Min Pattern Data Retention Time

Max Storage Temperature 10 Years
Max Operating Temperature 20 Years

ROBUSTNESS FEATURES

The PALCE20V8X-X/5 have some unique features that make them extremely robust, especially
when operating in high-speed design environments. Pull-up resistors on inputs and I/O pins
cause unconnected pins to default to a known state. Input clamping circuitry limits negative
overshoot, eliminating the possibility of false clocking caused by subsequent ringing. A special
noise filter makes the programming circuitry completely insensitive to any positive overshoot
that has a pulse width of less than about 100 ns for the /5 versions.

PALCE20V8 Family 21

INPUT/OUTPUT EQUIVALENT SCHEMATICS FOR PALCE20V8H-7 AND PALCE20V8H-5

V

CC

> 50 kΩ

V

CC

ESD

Protection

and

Clamping

Programming
Pins only

Provides ESD
Protection and
Clamping

V

CC

Programming

Voltage

Detection

Typical Input

V

CC

> 50 kΩ

Preload

Circuitry

Positive

Overshoot

Filter

Feedback

Programming

Circuitry

Input

16491E-12

Typical Output

Device Rev Letter

PALCE20V8H-7 A
PALCE20V8H-5 A

22 PALCE20V8 Family

INPUT/OUTPUT EQUIVALENT SCHEMATICS FOR /4 VERSIONS

V

CC

100 kΩ

V

0.5 kW

ESD

Protection

Input

CC

Device Rev Letter

PALCE20V8H-10 M
PALCE20V8H-15 L, M
PALCE20V8H-15 M
PALCE20V8H--25 M

V

CC

Preload

Circuitry

V

CC

100 kΩ

0.5 kΩ

Feedback

Input

I/O

Topside Marking:

Lattice/Vantis CMOS PLDs are marked on top of the
package in the following manner:

PALCEXXX
Datecode (3 numbers) Lot ID (4 characters)––(Rev Letter)

The Lot ID and Rev Letter are separated by two spaces.

16491E-13

PALCE20V8H-25 M

PALCE20V8 Family 23

POWER-UP RESET

The PALCE20V8 has been designed with the capability to reset during system power-up.
Following power-up, all flip-flops will be reset to LOW. The output state will be HIGH
independent of the logic polarity. This feature provides extra flexibility to the designer and is
especially valuable in simplifying state machine initialization. A timing diagram and parameter
table are shown below. Due to the synchronous operation of the power-up reset and the wide
range of ways V

can rise to its steady state, two conditions are required to ensure a valid

CC

power-up reset. These conditions are:

◆ The V

rise must be monotonic.

CC

◆ Following reset, the clock input must not be driven from LOW to HIGH until all applicable input

and feedback setup times are met.

Parameter Symbol Parameter Descriptions Min Max Unit

t

PR

t

S

t

WL

Power

Registered

Output

Clock

Power-Up Reset Time 1000 ns
Input or Feedback Setup Time
Clock Width LOW

4 V

t

PR

t

S

t

WL

See Switching Characteristics

V

CC

Figure 2. Power-Up Reset Waveform

24 PALCE20V8 Family

16491E-15

TYPICAL THERMAL CHARACTERISTICS

Measured at 25°C ambient. These parameters are not tested.

Parameter

Symbol Parameter Description

θ

jc

θ

ja

θ

jma

Plastic

The data listed for plastic
heat-flow paths in plastic-encapsulated devices are complex, making the
age surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the package.
Furthermore,
perature. Therefore, the measurements can only be used in a similar environment.

θ

Thermal impedance, junction to case 19 19 °C/W
Thermal impedance, junction to ambient 73 55 °C/W

200 lfpm air 61 45 °C/W

Thermal impedance, junction to ambient with air flow

Considerations

jc

θ

are for reference only and are not recommended for use in calculating junction temperatures. The

jc

θ

tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant tem-

jc

400 lfpm air 53 41 °C/W
600 lfpm air 50 38 °C/W
800 lfpm air 47 36 °C/W

θ

measurement relative to a specific location on the pack-

jc

Typ

UnitPDID PLCC

PALCE20V8 Family 25

CONNECTION DIAGRAMS

Top View

SKINNYDIP PLCC

CLK/I

GND

Note:

Pin 1 is marked for orientation.

1

0

2

I

1

3

I

2

4

I

3

5

I

4

6

I

5

7

I

6

8

I

7

9

I

8

10

I

9

11

I

10

12

24
23
22
21
20
19
18
17
16
15
14
13

V

CC

I

13

I/O

7

I/O

6

I/O

5

I/O

4

I/O

3

I/O

2

I/O

1

I/O

0

I

12

OE/I

11

16491E-16

NC

7

I2I1CLK/I0NC

4

3 2 1 28 27 26

5

I

3

6

I

4

7

I

5

8
9

I

6

10

I

7

11

I

8

VCCI13I/O

25
24
23
22
21
20
19

I/O

6

I/O

5

I/O

4

GND/NC *
I/O

3

I/O

2

I/O

1

12 13 14 15 16 17 18

16491E-17

0

I/O

9

I

10

I

GND

NC

11

12

I

OE/I

PIN DESIGNATIONS

CLK = Clock
GND = Ground
I = Input
I/O = Input/Output

NC = No Connect
OE = Output Enable

VCC = Supply Voltage

26 PALCE20V8 Family

ORDERING INFORMATION

Commercial and Industrial Products

Lattice/V antis programmable logic products for commercial and industrial applications are available with several ordering options.
The order number (Valid Combination) is formed by a combination of:

FAMILY TYPE

PAL = Programmable Array Logic

TECHNOLOGY

CE = CMOS Electrically Erasable

NUMBER OF
ARRAY INPUTS

OUTPUT TYPE

V = Versatile

NUMBER OF FLIP-FLOPS
OR OUTPUTS

POWER

H = Half Power (90–125 mA I
Q = Quarter Power (55 mA I

CC

CC

)

SPEED

-5 = 5 ns t

-7 = 7.5 ns t

-10 = 10 ns t

-12 = 12 ns t

-15 = 15 ns t

-20 = 20 ns t

-25 = 25 ns t

PD

PD
PD
PD
PD
PD
PD

PAL CE 20 V 8 H -5 J C

)

/5

PROGRAMMING DESIGNATOR

Blank = Initial Algorithm
/4 = First Revision
/5 = Second Revision

(Same Algorithm as /4)

OPERATING CONDITIONS

C = Commercial (0
I = Industrial (-40

°C to +75°C)

°C to +85°C)

PACKAGE TYPE

P = 24-Pin 300 mil Plastic SKINNY

DIP (PD3024)

J = 28-Pin Plastic Leaded Chip

Carrier (PL 028)

Valid Combinations

PALCE20V8H-5 JC

/5

PALCE20V8H-7

PC, JC

PALCE20V8H-10 /4
PALCE20V8H-15 PC, JC, PI, JI
PALCE20V8Q-15 PC, JC
PALCE20V8Q-20 PI, JI

/4

PALCE20V8H-25

PC, JC, PI, JI

PALCE20V8Q-25

Valid Combinations

V alid Combinations list configurations planned to be supported in volume for this device. Consult the local Lattice/V antis sales office
to confirm availability of specific valid combinations and to check on newly released combinations.

PALCE20V8 Family 27