Lattice Semiconductor Corporation PALCE20V8H-25PC-4, PALCE20V8H-5JC-5, PALCE20V8H-7JC-5, PALCE20V8H-7PC-5, PALCE20V8Q-15JC-4 Datasheet

COM'L: H-5/7/10/15/25, Q-10/15/25 IND: H-15/25, Q-20/25

PALCE20V8 Family

EE CMOS 24-Pin Universal
Programmable Array Logic

DISTINCTIVE CHARACTERISTICS

Pin and function compatible with all PAL®

◆

Electrically erasable CMOS technology provides reconfigurable logic and full testability

◆

◆

High-speed CMOS technology

— 5-ns propagation delay for “-5” version
— 7.5-ns propagation delay for “-7” version

◆

Direct plug-in replacement for a wide range of 24-pin PAL devices

◆

Programmable enable/disable control

◆

Outputs individually programmable as registered or combinatorial
Peripheral Component Interconnect (PCI) compliant

◆

◆

Preloadable output registers for testability

◆

Automatic register reset on power-up
Cost-effective 24-pin plastic SKINNY DIP and 28-pin PLCC packages

◆

Extensive third-party software and programmer support

◆

◆

Fully tested for 100% programming and functional yields and high reliability

◆

Programmable output polarity
5-ns version utilizes a split leadframe for improved performance

◆

20V8 devices

GENERAL DESCRIPTION

The PALCE20V8 is an advanced PAL
erasable CMOS technology. Its macrocells provide a universal device architecture. The
PALCE20V8 is fully compatible with the GAL20V8 and can directly replace PAL20R8 series
devices and most 24-pin combinatorial PAL devices.

device built with low-power, high-speed, electrically-

Device logic is automatically configured according to the user’s design specification. A design is
implemented using any of a number of popular design software packages, allowing automatic
creation of a programming file based on Boolean or state equations. Design software also verifies
the design and can provide test vectors for the finished device. Programming can be
accomplished on standard PAL device programmers.

The P ALCE20V8 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to
implement complex logic functions easily and efficiently. Multiple levels of combinatorial logic
can always be reduced to sum-of-products form, taking advantage of the very wide input gates
available in PAL devices. The equations are programmed into the device through floating-gate
cells in the AND logic array that can be erased electrically.

Publication# 16491 Rev: E
Amendment/0 Issue Date: November 1998

The fixed OR array allows up to eight data product terms per output for logic functions. The
sum of these products feeds the output macrocell. Each macrocell can be programmed as
registered or combinatorial with an active-high or active-low output. The output configuration
is determined by two global bits and one local bit controlling four multiplexers in each
macrocell.

BLOCK DIAGRAM

– I

I

1

10

10

CLK/I

0

OE/I

Input
Mux.

11

Programmable AND Array

MACRO
MC

0

I

12

I/O

0

MACRO

MC

1

I/O

1

MACRO

MC

2

I/O

2

MACRO

MC

3

I/O

40 x 64

3

MACRO

MC

4

I/O

MACRO

MC

5

4

I/O

5

MACRO

MC

6

I/O

MACRO

MC

7

6

I/O

Input
Mux.

7

I

13

16491E

FUNCTIONAL DESCRIPTION

The PALCE20V8 is a universal PAL device. It has eight independently configurable macrocells

-MC

(MC

0

combinatorial I/O, or dedicated input. The programming matrix implements a programmable
AND logic array, which drives a fixed OR logic array. Buffers for device inputs have
complementary outputs to provide user-programmable input signal polarity. Pins 1 and 13 serve
either as array inputs or as clock (CLK) and output enable (OE

). Each macrocell can be configured as a registered output, combinatorial output,

7

) for all flip-flops.

Unused input pins should be tied directly to V

or GND. Product terms with all bits

CC

unprogrammed (disconnected) assume the logical HIGH state, and product terms with both true
and complement of any input signal connected assume a logical LOW state.

The programmable functions on the PALCE20V8 are automatically configured from the user’s
design specification, which can be in a number of formats. The design specification is processed

2 PALCE20V8 Family

by development software to verify the design and create a programming file. This file, once
downloaded to a programmer, configures the device according to the user’s desired function.

The user is given two design options with the PALCE20V8. First, it can be programmed as an
emulated PAL device. This includes the PAL20R8 series and most 24-pin combinatorial PAL
devices. The PAL device programmer manufacturer will supply device codes for the standard
P AL architectures to be used with the P ALCE20V8. The programmer will program the P ALCE20V8
to the corresponding PAL device architecture. This allows the user to use existing standard PAL
device JEDEC files without making any changes to them. Alternatively, the device can be
programmed directly as a P ALCE20V8. Here the user must use the PALCE20V8 device code. This
option provides full utilization of the macrocells, allowing non-standard architectures to be built.

To

Adjacent

Macrocell

1 1
0 X

1 0

OE

V

CC

1 1
1 0
0 0

0 1

SL0

X

SG1

DQ

SL1

X

*In macrocells MC0 and MC7, SG1 is replaced by SG0 on the feedback multiplexer.

CLK

Q

Figure 1. PALCE20V8 Macrocell

*SG1

1 1
0 X

1 0

1 0
1 1
0 X

SL0

I/O

X

From

X

Adjacent
Pin

16491E

PALCE20V8 Family 3

CONFIGURATION OPTIONS

Each macrocell can be configured as one of the following: registered output, combinatorial
output, combinatorial I/O or dedicated input. In the registered output configuration, the output
buffer is enabled by the OE
by a product term or always enabled. In the dedicated input configuration, the buffer is always
disabled. A macrocell configured as a dedicated input derives the input signal from an adjacent
I/O.

The macrocell configurations are controlled by the configuration control word. It contains 2
global bits (SG0 and SG1) and 16 local bits (SL0
determines whether registers will be allowed. SG1 determines whether the PALCE20V8 will
emulate a P AL20R8 family or a combinatorial device. Within each macrocell, SL0
with SG1, selects the configuration of the macrocell and SL1
or active high.

The configuration bits work by acting as control inputs for the multiplexers in the macrocell.
There are four multiplexers: a product term input, an enable select, an output select, and a
feedback select multiplexer. SG1 and SL0
and MC

, SG0 replaces SG1 on the feedback multiplexer.

7

These configurations are summarized in Table 1 and illustrated in Figure 2.

pin. In the combinatorial configuration, the buffer is either controlled

through SL0

0

are the control signals for all four multiplexers. In MC

x

and SL1

7

sets the output as either active low

x

through SL1

0

, in conjunction

x

). SG0

7

0

If the P ALCE20V8 is configured as a combinatorial device, the CLK and OE pins may be available
as inputs to the array. If the device is configured with registers, the CLK and OE

pins cannot be

used as data inputs.

Registered Output Configuration

The control bit settings are SG0 = 0, SG1 = 1 and SL0

= 0. There is only one registered

x

configuration. All eight product terms are available as inputs to the OR gate. Data polarity is

. SL1

determined by SL1
flop. SL1

is programmed as 1 for inverted output or 0 for non-inverted output. The flip-flop is

x

x

loaded on the LOW-to-HIGH transition of CLK. The feedback path is from Q
output buffer is enabled by OE

is an input to the exclusive-OR gate which is the D input to the flip-

x

on the register. The

.

Combinatorial Configurations

The PALCE20V8 has three combinatorial output configurations: dedicated output in a non­registered device, I/O in a non-registered device and I/O in a registered device.

Dedicated Output in a Non-Registered Device

The control settings are SG0 = 1, SG1 = 0, and SL0

= 0. All eight product terms are available to

x

the OR gate. Although the macrocell is a dedicated output, the feedback is used, with the
exception of pins 18(21) and 19(23). Pins 18(21) and 19(23) do not use feedback in this mode.

Note:

1. The pin number without parentheses refers to the SKINNY DIP package. The pin number in parentheses refers to the PLCC
package.

4 PALCE20V8 Family

Dedicated Input in a Non-Registered Device

The control bit settings are SG0 = 1, SG1 = 0 and SL0

= 1. The output buffer is disabled. The

x

feedback signal is an adjacent I/O pin.

Combinatorial I/O in a Non-Registered Device

The control settings are SG0 = 1, SG1 = 1, and SL0

= 1. Only seven product terms are available

x

to the OR gate. The eighth product term is used to enable the output buffer. The signal at the
I/O pin is fed back to the AND array via the feedback multiplexer. This allows the pin to be used
as an input.

Combinatorial I/O in a Registered Device

The control bit settings are SG0=0,SG1=1 and SL0

=1. Only seven product terms are available

x

to the OR gate. The eighth product term is used as the output enable. The feedback signal is the
corresponding I/O signal.

Table 1. Macrocell Configuration

Cell

SG0 SG1 SL0

Device Uses Registers Device Uses No Registers

0 1 0 Registered Output

011

X

Configuration

Combinatorial

I/O

Devices

Emulated SG0 SG1 SL0

PAL20R8, 20R6,

20R4

PAL20R6, 20R4 1 0 1 Input PAL20L2, 18L4, 16L6

100

X

Cell

Configuration

Combinatorial

Output

Devices

Emulated

PAL20L2, 18L4,

16L6, 14L8

111

Combinatorial

I/O

PAL20L8

PALCE20V8 Family 5

OE

CLK

a. Registered active Low

DQQ

OE

DQQ

CLK

b. Registered active high

c. Combinatorial I/O active low d. Combinatorial I/O active high

V

CC

Note 1 Note 1

e. Combinatorial output active low

Notes:

1. Feedback is not available on pins 18 (21) and 19 (23) in
the combinatorial output mode.

2. This macrocell configuration is not available on pins
18 (21) and 19 (23).

Figure 2. Macrocell Configurations

V

CC

f. Combinatorial output active high

Note 2

Adjacent I/O Pin

g. Dedicated input

16491E

6 PALCE20V8 Family

Power-Up Reset

All flip-flops power up to a logic LOW for predictable system initialization. Outputs of the
PALCE20V8 depend on whether they are selected as registered or combinatorial. If registered is
selected, the output will be HIGH. If combinatorial is selected, the output will be a function of
the logic.

Register Preload

The register on the PALCE20V8 can be preloaded from the output pins to facilitate functional
testing of complex state machine designs. This feature allows direct loading of arbitrary states,
making it unnecessary to cycle through long test vector sequences to reach a desired state. In
addition, transitions from illegal states can be verified by loading illegal states and observing
proper recovery.

Security Bit

A security bit is provided on the P ALCE20V8 as a deterrent to unauthorized copying of the array
configuration patterns. Once programmed, this bit defeats readback and verification of the
programmed pattern by a device programmer, securing proprietary designs from competitors.
The bit can only be erased in conjunction with the array during an erase cycle.

Electronic Signature Word

An electronic signature word is provided in the PALCE20V8. It consists of 64 bits of
programmable memory that can contain any user-defined data. The signature data is always
available to the user independent of the security bit.

Programming and Erasing

The PALCE20V8 can be programmed on standard logic programmers. It also may be erased to
reset a previously configured device back to its unprogrammed state. Erasure is automatically
performed by the programming hardware. No special erase operation is required.

Quality and Testability

The P ALCE20V8 offers a very high level of built-in quality. The erasability of the device provides
a direct means of verifying performance of all AC and DC parameters. In addition, this verifies
complete programmability and functionality of the device to provide the highest programming
and post-programming functional yields in the industry.

Technology

The high-speed P ALCE20V8H is fabricated with V antis’ advanced electrically erasable (EE) CMOS
process. The array connections are formed with proven EE cells. Inputs and outputs are
designed to be compatible with TTL devices. This technology provides strong input clamp
diodes, output slew-rate control, and a grounded substrate for clean switching.

PCI Compliance

PALCE20V8H devices in the -5/-7/-10 speed grades are fully compliant with the PCI Local Bus

Specification

published by the PCI Special Interest Group. The P ALCE20V8H’s predictable timing
ensures compliance with the PCI AC specifications independent of the design. On the other
hand, in CPLD and FPGA architectures without predictable timing, PCI compliance is dependent
upon routing and product term distribution.

PALCE20V8 Family 7

LOGIC DIAGRAM

CLK/I

0 3 4 7 8 1112 1516 1920 2324 2728 3132 3536 39

1

0

(2)

I

2

1

(3)

0

7

I

3

2

(4)

8

15

I

3

4

(5)

16

23

I

4

5

(6)

SG0

1
0

1 1

1 1
0 X

1 0

SL0

7

SG1

DQ

1 1
0 X

1 0

SL0

6

SG1

DQ

1 1
0 X

1 0

SL0

5

SG1

DQ

1 0
0 0

V

CC

0 1

1 1

0 X
1 0

Q

1 0
1 1
0 X

SG0

SL0

7

1 1
1 0
0 0

V

CC

0 1

1 1
0 X

1 0

Q

1 0

1 1

0 X

SG1

SL0

6

1 1
1 0
0 0

V

CC

0 1

1 1
0 X

1 0

Q

1 0
1 1

0 X

SG1

SL0

5

(28)

23
(27)

24

V

CC

I

13

I/O

22

7

(26)

I/O

21

6

(25)

I/O

20

5

(24)

24

31

I

6

5

(7)

03478111215161920 2427283132353639

23

8 PALCE20V8 Family

1 1

1 1
0 X

1 0

SL0

4

SG1

DQ

1 0
0 0

V

CC

0 1

1 1
0 X

1 0

Q

1 0
1 1

0 X

SG1

SL0

4

(23)

I/O

19

4

CLK OE

16491E

LOGIC DIAGRAM (CONTINUED)

0 3 4 7 8 11121516192023242728 3132353639

1 1

0 X

1 0

32

39

7

I

6

(9)

1 1

0 X

1 0

40

47

I

8

7

(10)

1 1

0 X

1 0

48

55

9

I

8

(11)

SG1

SG1

SG1

CLK OE

SL0

SL0

SL0

1 1
1 0
0 0

V

CC

0 1

3

1 1

DQ

Q

0 X
1 0

1 0
1 1

0 X

SG1

SL0

3

1 1
1 0
0 0

V

CC

0 1

18

(21)

I/O

3

2

1 1

DQ

Q

0 X

1 0

1 0
1 1
0 X

SG1

SL0

2

1 1
1 0
0 0

V

CC

0 1

17

(20)

I/O

2

1

1 1

DQ

Q

SG1

0 X
1 0

1 0
1 1
0 X

SL0

1

16

(19)

I/O

1

1 1

1 1

0 X

1 0

SL0

56

SG1

0

DQ

63

I

10

9

(12)

11

10

(13)

0 3 4 7 8 1112 1516 1920 2324 2728 3132 3536

39

SG0

0
1

1 0
0 0

V

CC

0 1

1 1
0 X

1 0

Q

1 0
1 1

0 X

SL0

SG0

0

(18)

14

(17)

13

(16)

I/O

15

0

I

12

OE/I

11

16491E-4

(concluded)

PALCE20V8 Family 9