Lattice Semiconductor Corporation PALCE16V8H-10JC-4, PALCE16V8Q-15PC-4, PALCE16V8Q-20JI-4, PALCE16V8Q-20PI-4, PALCE16V8H-15SC-4 Datasheet

PALCE16V8
PALCE16V8Z

COM’L:H-5/7/10/15/25, Q-10/15/25 IND:H-10/15/25, Q-20/25
COM’L:-25 IND:-12/15/25

P ALCE16V8 and PALCE16V8Z Families

EE CMOS (Zero-Power) 20-Pin Universal
Programmable Array Logic

DISTINCTIVE CHARACTERISTICS

Pin and function compatible with all 20-pin PAL® devices

◆

Electrically erasable CMOS technology provides reconfigurable logic and full testability

◆

◆

High-speed CMOS technology

— 5-ns propagation delay for “-5” version
— 7.5-ns propagation delay for “-7” version

◆

Direct plug-in replacement for the PAL16R8 series

◆

Outputs programmable as registered or combinatorial in any combination

◆

Peripheral Component Interconnect (PCI) compliant
Programmable output polarity

◆

◆

Programmable enable/disable control

◆

Preloadable output registers for testability
Automatic register reset on power up

◆

Cost-effective 20-pin plastic DIP, PLCC, and SOIC packages

◆

◆

Extensive third-party software and programmer support

◆

Fully tested for 100% programming and functional yields and high reliability
5-ns version utilizes a split leadframe for improved performance

◆

GENERAL DESCRIPTION

The PALCE16V8 is an advanced PAL
erasable CMOS technology. It is functionally compatible with all 20-pin GAL devices. The
macrocells provide a universal device architecture. The PALCE16V8 will directly replace the
PAL16R8, with the exception of the PAL16C1.

The PALCE16V8Z provides zero standby power and high speed. At 30-µA maximum standby
current, the PALCE16V8Z allows battery-powered operation for an extended period.

The P ALCE16V8 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to
implement complex logic functions easily and efficiently. Multiple levels of combinatorial logic
can always be reduced to sum-of-products form, taking advantage of the very wide input gates
available in PAL devices. The equations are programmed into the device through floating-gate

USE GAL DEVICES FOR

cells in the AND logic array that can be erased electrically.
The fixed OR array allows up to eight data product terms per output for logic functions. The

sum of these products feeds the output macrocell. Each macrocell can be programmed as
registered or combinatorial with an active-high or active-low output. The output configuration
is determined by two global bits and one local bit controlling four multiplexers in each
macrocell.

device built with low-power, high-speed, electrically-

NEW DESIGNS

Publication# 16493 Rev: F
Amendment/0 Issue Date: September 2000

BLOCK DIAGRAM

I1 – I

8

8

CLK/I

0

OE/I

Programmable AND Array

MACRO

MC

0

9

I/O

0

MACRO

MC

1

I/O

1

MACRO

MC

2

I/O

2

MACRO

MC

3

I/O

3

32 x 64

MACRO

MC

4

I/O

4

MACRO

MC

5

I/O

5

MACRO

MC

6

I/O

6

MACRO

MC

7

I/O

7

16493E-1

FUNCTIONAL DESCRIPTION

The PALCE16V8 is a universal PAL device. The PALCE16V8Z is the zero-power version of the
PALCE16V8. It has all the architectural features of the PALCE16V8. In addition, the PALCE16V8Z
has zero standby power and an unused product term disable feature for reduced power

-

MC

consumption. It has eight independently configurable macrocells (MC
be configured as registered output, combinatorial output, combinatorial I/O or dedicated input.
The programming matrix implements a programmable AND logic array, which drives a fixed OR
logic array. Buffers for device inputs have complementary outputs to provide user­programmable input signal polarity. Pins 1 and 11 serve either as array inputs or as clock (CLK)
and output enable (OE

USE GAL DEVICES FOR

), respectively, for all flip-flops.

NEW DESIGNS

). Each macrocell can

0

7

Unused input pins should be tied directly to V

or GND. Product terms with all bits

CC

unprogrammed (disconnected) assume the logical HIGH state, and product terms with both true
and complement of any input signal connected assume a logical LOW state.

The programmable functions on the PALCE16V8 are automatically configured from the user’s
design specification. The design specification is processed by development software to verify
the design and create a programming file (JEDEC). This file, once downloaded to a programmer,
configures the device according to the user’s desired function.

The user is given two design options with the PALCE16V8. First, it can be programmed as a
standard P AL device from the P AL16R8 series. The P AL programmer manufacturer will supply
device codes for the standard PAL device architectures to be used with the PALCE16V8.
The programmer will program the P ALCE16V8 in the corresponding architecture. This allows
the user to use existing standard PAL device JEDEC files without making any changes to them.

2 PALCE16V8 and PALCE16V8Z Families

Alternatively, the device can be programmed as a PALCE16V8. Here the user must use the
PALCE16V8 device code. This option allows full utilization of the macrocell.

To

Adjacent

Macrocell

I/O

X

1 1
0 X

1 0

SG1

SL0

OE

V

CC

X

DQ

1 1
1 0
0 0

0 1

1 1
0 X

1 0

SL1

X

*In macrocells MC0 and MC7, SG1 is replaced by SG0 on the feedback multiplexer.

Figure 1. PALCE16V8 Macrocell

CLK

Q

1 0
1 1

*SG1

0 X

SL0

X

From
Adjacent
Pin

16493E-2

CONFIGURATION OPTIONS

Each macrocell can be configured as one of the following: registered output, combinatorial
output, combinatorial I/O, or dedicated input. In the registered output configuration, the output
buffer is enabled by the OE

pin. In the combinatorial configuration, the buffer is either controlled
by a product term or always enabled. In the dedicated input configuration, it is always disabled.
With the exception of MC

and MC

0

input signal from an adjacent I/O. MC

, a macrocell configured as a dedicated input derives the

7

NEW DESIGNS

derives its input from pin 11 (OE) and MC

0

from pin 1

7

(CLK).

USE GAL DEVICES FOR

The macrocell configurations are controlled by the configuration control word. It contains 2
global bits (SG0 and SG1) and 16 local bits (SL0

through SL0

0

determines whether registers will be allowed. SG1 determines whether the PALCE16V8 will
emulate a PAL16R8 family or a PAL10H8 family device. Within each macrocell, SL0
conjunction with SG1, selects the configuration of the macrocell, and SL1
either active low or active high for the individual macrocell.

and SL1

7

through SL1

0

sets the output as

x

, in

x

7

). SG0

The configuration bits work by acting as control inputs for the multiplexers in the macrocell.
There are four multiplexers: a product term input, an enable select, an output select, and a
feedback select multiplexer. SG1 and SL0

and MC

MC

0

the adjacent pin for MC

, SG0 replaces SG1 on the feedback multiplexer. This accommodates CLK being

7

and OE the adjacent pin for MC

7

PALCE16V8 and PALCE16V8Z Families 3

are the control signals for all four multiplexers. In

x

.

0

Registered Output Configuration

The control bit settings are SG0 = 0, SG1 = 1 and SL0

= 0. There is only one registered

x

configuration. All eight product terms are available as inputs to the OR gate. Data polarity is
determined by SL1
path is from Q

The flip-flop is loaded on the LOW-to-HIGH transition of CLK. The feedback

x.

on the register. The output buffer is enabled by OE.

Combinatorial Configurations

The PALCE16V8 has three combinatorial output configurations: dedicated output in a non­registered device, I/O in a non-registered device and I/O in a registered device.

Dedicated Output in a Non-Registered Device

The control bit settings are SG0 = 1, SG1 = 0 and SL0

= 0. All eight product terms are available

x

to the OR gate. Although the macrocell is a dedicated output, the feedback is used, with the
exception of pins 15 and 16. Pins 15 and 16 do not use feedback in this mode. Because CLK
and OE
1 will use the feedback path of MC

are not used in a non-registered device, pins 1 and 11 are available as input signals. Pin

, and pin 11 will use the feedback path of MC

7

.

0

Combinatorial I/O in a Non-Registered Device

The control bit settings are SG0 = 1, SG1 = 1, and SL0

= 1. Only seven product terms are

x

available to the OR gate. The eighth product term is used to enable the output buffer. The signal
at the I/O pin is fed back to the AND array via the feedback multiplexer. This allows the pin to
be used as an input.

Because CLK and OE
inputs. Pin 1 will use the feedback path of MC

are not used in a non-registered device, pins 1 and 11 are available as

,

and pin 11 will use the feedback path of MC

7

0

Combinatorial I/O in a Registered Device

.

The control bit settings are SG0 = 0, SG1 = 1 and SL0

= 1. Only seven product terms are available

x

to the OR gate. The eighth product term is used as the output enable. The feedback signal is the
corresponding I/O signal.

Dedicated Input Configuration

The control bit settings are SG0 = 1, SG1 = 0 and SL0
for MC

and MC

0

are pins 1 and 11. These configurations are summarized in Table 1 and illustrated in Figure 2.

SG0 SG1 SL0

0 1 0 Registered Output

011

, the feedback signal is an adjacent I/O. For MC

7

USE GAL DEVICES FOR

Cell

Configuration

X

Device Uses Registers Device Uses No Registers

Combinatorial

I/O

NEW DESIGNS

Table 1. Macrocell Configuration

Devices

Emulated SG0 SG1 SL0

PAL16R8, 16R6,

16R4

PAL16R6, 16R4 1 0 1 Input

= 1. The output buffer is disabled. Except

x

and MC

0

X

100

111

, the feedback signals

7

Cell

Configuration

Combinatorial

Output

Combinatorial

I/O

Devices

Emulated

PAL10H8, 12H6,

14H4, 16H2, 10L8,

12L6, 14L4, 16L2

PAL12H6, 14H4,

16H2, 12L6, 14L4,

PAL16L8

16L2

4 PALCE16V8 and PALCE16V8Z Families

Programmable Output Polarity

The polarity of each macrocell can be active-high or active-low, either to match output signal
needs or to reduce product terms. Programmable polarity allows Boolean expressions to be
written in their most compact form (true or inverted), and the output can still be of the desired
polarity. It can also save “DeMorganizing” efforts.

Selection is through a programmable bit SL1
of the AND/OR logic. The output is active high if SL1

which controls an exclusive-OR gate at the output

x

is 1 and active low if SL1

x

is 0.

x

NEW DESIGNS

USE GAL DEVICES FOR

PALCE16V8 and PALCE16V8Z Families 5

OE

CLK

a. Registered active low

DQQ

OE

DQQ

CLK

b. Registered active high

c. Combinatorial I/O active low d. Combinatorial I/O active high

V

CC

NEW DESIGNS

Note 1 Note 1

USE GAL DEVICES FOR

e. Combinatorial output active low

Notes:

1. Feedback is not available on pins 15 and 16 in the

combinatorial output mode.

2. This configuration is not available on pins 15 and 16.

Figure 2. Macrocell Configurations

V

CC

f. Combinatorial output active high

Adjacent I/O pin
Note 2

g. Dedicated input

16493E-2

6 PALCE16V8 and PALCE16V8Z Families

Power-Up Reset

All flip-flops power up to a logic LOW for predictable system initialization. Outputs of the
P ALCE16V8 will depend on whether they are selected as registered or combinatorial. If registered
is selected, the output will be HIGH. If combinatorial is selected, the output will be a function
of the logic.

Register Preload

The register on the PALCE16V8 can be preloaded from the output pins to facilitate functional
testing of complex state machine designs. This feature allows direct loading of arbitrary states,
making it unnecessary to cycle through long test vector sequences to reach a desired state. In
addition, transitions from illegal states can be verified by loading illegal states and observing
proper recovery.

Security Bit

A security bit is provided on the P ALCE16V8 as a deterrent to unauthorized copying of the array
configuration patterns. Once programmed, this bit defeats readback and verification of the
programmed pattern by a device programmer, securing proprietary designs from competitors.
The bit can only be erased in conjunction with the array during an erase cycle.

Electronic Signature Word

An electronic signature word is provided in the PALCE16V8 device. It consists of 64 bits of
programmable memory that can contain user-defined data. The signature data is always available
to the user independent of the security bit.

Programming and Erasing

The PALCE16V8 can be programmed on standard logic programmers. It also may be erased to
reset a previously configured device back to its unprogrammed state. Erasure is automatically
performed by the programming hardware. No special erase operation is required.

Quality and Testability

The P ALCE16V8 offers a very high level of built-in quality. The erasability of the device provides
a direct means of verifying performance of all AC and DC parameters. In addition, this verifies
complete programmability and functionality of the device to provide the highest programming
yields and post-programming functional yields in the industry.

Technology

The high-speed PALCE16V8 is fabricated with Vantis’ advanced electrically-erasable (EE) CMOS
process. The array connections are formed with proven EE cells. Inputs and outputs are
designed to be compatible with TTL devices. This technology provides strong input clamp
diodes, output slew-rate control, and a grounded substrate for clean switching.

USE GAL DEVICES FOR

NEW DESIGNS

PCI Compliance

PALCE16V8 devices in the -5/-7/-10 speed grades are fully compliant with the

Specification

ensures compliance with the PCI AC specifications independent of the design.

Zero-Standby Power Mode

The PALCE16V8Z features a zero-standby power mode. When none of the inputs switch for an
extended period (typically 50 ns), the PALCE16V8Z will go into standby mode, shutting down

published by the PCI Special Interest Group. The PALCE16V8’s predictable timing

PALCE16V8 and PALCE16V8Z Families 7

PCI Local Bus

most of its internal circuitry. The current will go to almost zero (ICC < 15 µA). The outputs will
maintain the states held before the device went into the standby mode. There is no speed
penalty associated with coming out of standby mode.

When any input switches, the internal circuitry is fully enabled, and power consumption returns
to normal. This feature results in considerable power savings for operation at low to medium
frequencies. This saving is illustrated in the I

Product-Term Disable

On a programmed PALCE16V8Z, any product terms that are not used are disabled. Power is cut
off from the product terms so that they do not draw current. As shown in the ICC vs. frequency
graph, product-term disabling results in considerable power savings. This saving is greater at the
higher frequencies.

Further hints on minimizing power consumption can be found in a separate document entitled,
Minimizing Power Consumption with Zero-Power PLDs.

vs. frequency graph.

CC

NEW DESIGNS

USE GAL DEVICES FOR

8 PALCE16V8 and PALCE16V8Z Families

LOGIC DIAGRAM

034781112151619202324272831

CLK/I

1

0

1 1

1 1
0 X

1 0

SL0

0

7

I

2

1

1 1
0 X

1 0

8

15

I

3

2

1 1
0 X

1 0

16

23

4

I

3

SG1

SL1

SL1

SG1

SG1

SL1

7

DQ

7

SL0

6

DQ

6

SL0

5

5

Q

DQ

Q

NEW DESIGNS

1 0
0 0

V

CC

0 1

1 1

0 X

1 0

Q

1 0

1 1

0 X

SG0

SL0

1 1
1 0
0 0

V

CC

0 1

1 1
0 X

1 0

1 0

1 1

0 X

SG1

SL0

1 1
1 0
0 0

V

CC

0 1

1 1
0 X

1 0

1 0
1 1

0 X

SG1

SL0

20

V

CC

I/O

19

7

7

18

I/O

6

6

17

I/O

5

5

USE GAL DEVICES FOR

1 1
0 X

1 0

SL0

SL1

SG1

4

DQ

4

CLK OE

24

31

5

I

4

03478111215161920 2427283123

1 1
1 0
0 0

V

CC

0 1

1 1
0 X

1 0

Q

1 0
1 1

0 X

SG1

SL0

4

16

I/O

4

16493E-2

PALCE16V8 and PALCE16V8Z Families 9

LOGIC DIAGRAM (CONTINUED)

034781112151619202324272831

1 1
0 X

1 0

32

39

6

I

5

1 1
0 X

1 0

40

47

7

I

6

1 1

0 X
1 0

48

55

8

I

7

SG1

SL1

SG1

SL1

SG1

SL1

CLK OE

1 1
1 0
0 0

V

CC

0 1

SL0

3

1 1

DQ

3

SL0

2

DQ

2

SL0

1

DQ

1

0 X
1 0

Q

1 0
1 1

0 X

SG1

SL0

3

1 1
1 0
0 0

V

CC

0 1

1 1
0 X

1 0

Q

1 0
1 1
0 X

SG1

SL0

2

1 1
1 0
0 0

V

CC

0 1

1 1
0 X

1 0

Q

1 0
1 1
0 X

SG1

SL0

1

15

I/O

3

14

I/O

2

13

I/O

1

1 1
0 X

1 0

SG1

SL1

0

I

8

GND 10

NEW DESIGNS

56

63

9

USE GAL DEVICES FOR

0 3 4 7 8 1112 15161920 2324 2728 31

10 PALCE16V8 and PALCE16V8Z Families

1 1
1 0
0 0

V

CC

0 1

SL0

0

1 1

DQ

Q

SG0

0 X
1 0

1 0
1 1

0 X

SL0

0

I/O012

11

OE/I

9

16493E-6

(concluded)