Lattice Semiconductor Corporation MACH221SP-7YC, MACH221SP-18YI, MACH221SP-15YC, MACH221SP-14YI, MACH221SP-12YI Datasheet

MACH 1 and 2 CPLD Families

High-Performance EE CMOS Programmable Logic

FEATURES

◆

High-performance electrically-erasable CMOS PLD families 32 to 128 macrocells

◆

44 to 100 pins in cost-effective PLCC, PQFP and TQFP packages

◆

SpeedLocking™ – guaranteed ﬁxed timing up to 16 product terms

◆

Commercial 5/5.5/6/7.5/10/12/15-ns tPD and Industrial 7.5/10/12/14/18-ns t Conﬁgurable macrocells

◆

— Programmable polarity — Registered or combinatorial outputs — Internal and I/O feedback paths — D-type or T-type ﬂip-ﬂops — Output Enables — Choice of clocks for each ﬂip-ﬂop — Input registers for MACH 2 family

JTAG (IEEE 1149.1)-compatible, 5-V in-system programming available

◆

Peripheral component interconnect (PCI) compliant at 5/5.5/6/7.5/10/12 ns

◆

Safe for mixed supply voltage system designs Bus-Friendly™ inputs and I/Os reduce risk of unwanted oscillatory outputs

◆

Programmable power-down mode results in power savings of up to 75%

◆

Supported by Vantis DesignDirect™ software for rapid logic development

— Supports HDL design methodologies with results optimized for Vantis — Flexibility to adapt to user requirements — Software partnerships that ensure customer success

◆

Lattice/Vantis and third-party hardware programming support

— Lattice/VantisPRO™ (formerly known as MACHPRO

®

) software for in-system programmability

support on PCs and Automated Test Equipment

— Programming support on all major programmers including Data I/O, BP Microsystems, Advin,

and System General

PD

Publication# 14051 Rev: K Amendment/0 Issue Date: November 1998

Table 1. MACH 1 and 2 Family Device Features

Feature MACH111 (SP) MACH131 (SP) MACH211 (SP) MACH221 (SP) MACH231 (SP)

Macrocells Maximum user I/O pins t

(ns)

PD

t

(ns)

S

t

(ns)

CO

f

(MHz)

CNT

Note:

1. Values in parentheses ( ) are for the SP version.

32 64 64 96 128 32 64 32 48 64

5.0 5.5 7.5 (6.0) 7.5 6.0 (10)

3.5 3.0 5.5 (5) 5.5 5 (6.5)

3.5 4 4.5 (4) 5 4 (6.5)

182 182 133 (166) 133 166 (100)

1

GENERAL DESCRIPTION

The MACH Programmable Logic Devices (CPLDs), addressing the growing need for speed in networking, telecommunications and computing. MACH 1 & 2 devices are available in speeds as fast as 5.0-ns

and in densities ranging from 32 to 128 macrocells (Tables 1 and 2). The overall beneﬁts for

t

PD

users include guaranteed high performance for entry-to-mid-level logic needs at a low cost.

®

1 & 2 families from Lattice/Vantis offer high-performance, low cost Complex

Table 2. MACH 1 and 2 Family Speed Grades

1

Device -5 -6 -7 -10 -12 -14 -15 -18

MACH111 MACH111SP MACH131 MACH131SP MACH211 MACH211SP MACH221 MACH221SP MACH231 MACH231SP

Notes:

1. C = Commercial, I = Industrial

2. -5 speed grade for MACH111 (SP) = 5.0 ns t

3. -5 speed grade for MACH131(SP) = 5.5 ns t

C (Note 2) C, I C, I C, I I C I C (Note 2) C, I C, I C, I I C I C (Note 3) C, I C, I C, I I C I C (Note 3) C, I C, I C, I I C I

C C, I C, I I C I

C C C, I C, I I C I

C C, I C, I I C I C C, I C, I I C I

CCCC, IICI

C C, I I C I

PD

The MACH 1 & 2 families consist of ten devices—ﬁve base options, each with a counterpart that includes JT AG-compatible in-system programming (ISP). These devices offer ﬁve different densityI/O combinations in Thin Quad Flat Pack (TQFP), Plastic Quad Flat Pack (PQFP), and Plastic Leaded Chip Carrier (PLCC) packages from 44 to 100 pins (Table 3). Each MACH 1 & 2 device is PCI compliant and includes other features such as SpeedLocking architecture for guaranteed ﬁxed timing, Bus-Friendly inputs and I/Os, and programmable power-down mode for extra power savings.

2 MACH 1 & 2 Families

Table 3. MACH 1 and 2 Family Package and I/O Options

Device 44-pin PLCC 44-pin TQFP 68-pin PLCC 84-pin PLCC 100-pin TQFP 100-pin PQFP

MACH111 MACH111SP MACH131 MACH131SP MACH211 MACH211SP MACH221 MACH221SP MACH231 MACH231SP

Note:

1. The MACH110, MACH120, MACH130, MACH210, MACHLV210, MACH215, MACH220 and MACH230 are not listed above and not recommended for new designs. However, they are still supported by Lattice/Vantis. For technical or sales support, please call your local Lattice/Vantis sales ofﬁce or visit our Web site at www.vantis.com for more information.

XX XX

X

XX XX XX

X

XX

Lattice/Vantis offers software design support for MACH devices in both the MACHXL

®

and DesignDirect development systems. The DesignDirect development system is the Lattice/Vantis implementation software that includes support for all Lattice/Vantis CPLD, FPGA, and SPLD devices. This system is supported under Windows ’95, ’98 and NT as well as Sun Solaris and HPUX.

DesignDirect software is designed for use with design entry, simulation and veriﬁcation software from leading-edge tool vendors such as Cadence, Exemplar Logic, Mentor Graphics, Model Technology, Synopsys, Synplicity, Viewlogic and others. It accepts EDIF 2 0 0 input netlists, generates JEDEC ﬁles for Lattice/Vantis PLDs and creates industry-standard EDIF, Verilog, VITAL compliant VHDL and SDF simulation netlists for design veriﬁcation.

DesignDirect software is also available in product conﬁgurations that include VHDL and Verilog synthesis from Exemplar Logic and VHDL, V erilog RTL and gate level timing simulation from Model Technology. Schematic capture and ABEL entry, as well as functional simulation, are also provided.

MACH 1 & 2 Families 3

1

FUNCTIONAL DESCRIPTION

Each MACH 1 and 2 device consists of multiple, optimized P AL matrix. The switch matrix allows communication between P AL blocks, and routes inputs to the P AL blocks. Together , the P AL blocks and switch matrix allow the logic designer to create lar ge designs in a single device instead of using multiple devices.

Clock/Input Pins

®

blocks interconnected by a switch

Output

Array and Allocator

I/O Pins

Note:

. There are no buried macrocells in MACH 1 devices. All macrocells are output macrocells.

Device PAL Blocks Macrocells per Block I/Os per Block Product Terms per Block

MACH111(SP) 21616 70 MACH131(SP) 41616 70 MACH211(SP) 416 8 68 MACH221(SP) 812 6 52 MACH231(SP) 816 8 68

PAL Block

Buried Macrocell Feedback Output Macrocell Feedback I/O Pin Feedback

Switch Matrix

Dedicated Input

Macrocells

Buried

Macrocells

(note 1)

PAL Block I/O PinsPAL Block

I/O Cells

I/O Pins

PAL Block

14051K-002

Figure 1. Overall Architecture of MACH 1 & 2 Devices

The switch matrix takes all dedicated inputs and signals from the input switch matrices and routes them as needed to the PAL blocks. Feedback signals that return to the same PAL block still must go through the switch matrix. This mechanism ensures that PAL blocks in MACH devices communicate with each other with guaranteed ﬁxed timing (SpeedLocking).

The switch matrix makes a MACH device more advanced than simply several PAL devices on a single chip. It allows the designer to think of the device not as a collection of blocks, but as a single programmable device; the software partitions the design into PAL blocks through the central switch matrix so that the designer does not have to be concerned with the internal architecture of the device.

4 MACH 1 & 2 Families

Each PAL block consists of the following elements:

◆

Product-term array

◆

Logic Allocator

◆

Macrocells

◆

I/O cells

Each PAL block additionally contains an asynchronous reset product term and an asynchronous preset product term. This allows the ﬂip-ﬂops within a single P AL block to be initialized as a bank. There are also output enable product terms that provide tri-state control for the I/O cells.

Product-Term Array

The product-term array consists of a number of product terms that form the basis of the logic being implemented. The inputs to the AND gates come from the switch matrix (Table 4), and are provided in both true and complement forms for efﬁcient logic implementation.

Because the number of product terms available for a given function is not ﬁxed, the full sum of products is not realized in the array. The product terms drive the logic allocator, which allocates the appropriate number of product terms to generate the function.

Table 4. PAL Block Inputs

Device Number of Inputs to PAL Block Device Number of Inputs to PAL Block

MACH111 MACH111SP MACH131 MACH131SP MACH211

26 26 26 26 26

MACH211SP MACH221 MACH221SP MACH231 MACH231SP

26 26 26 32 32

Logic Allocator

The logic allocator (Figure 2) is a block within which different product terms are allocated to the appropriate macrocells in groups of four product terms called “product term clusters”. The availability and distribution of product term clusters is automatically considered by the software as it ﬁts functions within the PAL block. The size of the product term clusters has been designed to provide high utilization of product terms. Complex functions using many product terms are possible, and when few product terms are used, there will be a minimal number of unused, or wasted, product terms left over.

The product term clusters do not “wrap” around the logic block. This means that the macrocells at the ends of the block have fewer product terms available (Tables 5, 6, 7, 8).

MACH 1 & 2 Families 5

To

n-2Ton-1

From

n-1

*

n

Product Term

Cluster

To

From

n+1

Logic

Allocator

n

*

From

n+2

*MACH 2 only

To Macrocell

n

14051K-003

Figure 2. Product Term Clusters and the Logic Allocator

Table 5. Logic Allocation for MACH111(SP)

Output Macrocell Available Clusters Output Macrocell Available Clusters

C

M

0

M

1

M

2

M

3

M

4

M

5

M

6

M

7

, C

0

1

C

, C

0

1

2

C

, C

1

2

3

C

, C

2

3

4

C

, C

3

4

5

C

, C

4

5

6

C

, C

5

6

7

C

, C

6

7

M

8

M

9

M

10

M

11

M

12

M

13

M

14

M

15

C C C C

C

10, 11, 12, 13,

C

8,

C

9,

C

14, C15

C

8,

9

C

9,

10

C

10,

11

C

11,

12

C

12,

13

C

13,

14

C

14,

15

Table 6. Logic Allocation for MACH131(SP)

Output Macrocell Available Clusters Output Macrocell Available Clusters

M

0

M

1

M

2

M

3

M

4

M

5

M

6

M

7

C0, C C0, C1, C C1, C2, C C2, C3, C C3, C4, C C4, C5, C C5, C6, C C6, C7, C

1

2 3 4 5 6 7 8

M

8

M

9

M

10

M

11

M

12

M

13

M

14

M

15

6 MACH 1 & 2 Families

C7, C8, C

C8, C9, C

, C10, C

C

9

C10, C11, C C11, C12, C C12, C13, C C13, C14, C

C14, C

9

10

11

12 13 14 15

15

Table 7. Logic Allocation for MACH211(SP) and MACH231(SP)

M

0

M

2

M

4

M

6

M

0

M

2

M

4

Macrocell

Available Clusters

C0, C1, C

2

M

1

M

3

M

5

M

7

C0, C1, C2, C C1, C2, C3, C

C2, C3, C4, C C3, C4, C5, C

C4, C5, C6, C C5, C6, C7, C

C6, C7, C8, C

3 4

5 6

7 8

9

M

8

M

9

M

10

M

11

M

12

M

13

M

14

M

15

Available ClustersOutput Buried Output Buried

C7, C8, C9, C

C8, C9, C10, C

C9, C10, C11, C

C10, C11, C12, C C11, C12, C13, C

C12, C13, C14, C

C13, C14, C

C14, C

10

11

12

13 14

15

Table 8. Logic Allocation for MACH221(SP)

Macrocell

Available Clusters

C0, C1, C

2

M

1

M

3

M

5

C0, C1, C2, C C1, C2, C3, C

C2, C3, C4, C C3, C4, C5, C

C4, C5, C6, C

3 4

5 6

7

M

6

M

7

M

8

M

9

M

10

M

11

Available ClustersOutput Buried Output Buried

C5, C6, C7, C C6, C7, C8, C

C7, C8, C9, C

C8, C9, C10, C

C9, C10, C

C10, C

8 9

10

11

Macrocell

There are two fundamental types of macrocell: the output macrocell and the buried macrocell. The buried macrocell is only found in MACH 2 devices. The use of buried macrocells effectively doubles the number of macrocells available without increasing the pin count.

Both macrocell types can generate registered or combinatorial outputs. For the MACH 2 series, a transparent-low latch conﬁguration is provided. If the register is used, it can be conﬁgured as a T-type or a D-type ﬂip-ﬂop. Register and latch functionality is deﬁned in Table 9. Programmable polarity (for output macrocells) and the T-type ﬂip-ﬂop both give the software a way to minimize the number of product terms needed. These choices can be made automatically by the software when it ﬁts the design into the device.

Table 9. Register/Latch Operation

Conﬁguration D/T CLK/LE Q+

X 0,1,↓ Q

D-Register

T-Register

Latch

0 ↑ 0 1 ↑ 1 X 0,1,↓ Q 0 ↑ Q 1 ↑ Q X1Q 000 101

MACH 1 & 2 Families 7

The output macrocell (Figure 3) sends its output back to the switch matrix, via internal feedback, and to the I/O cell. The feedback is always available regardless of the conﬁguration of the I/O cell. This allows for buried combinatorial or registered functions, freeing up the I/O pins for use as inputs if not needed as outputs. The basic output macrocell conﬁgurations are shown in Figure 4.

The buried macrocell (Figure 5) does not send its output to an I/O cell. The output of a buried macrocell is provided only as an internal feedback signal which feeds the switch matrix. This allows the designer to generate additional logic without requiring additional pins. The buried macrocell can also be used to register or latch inputs. The input register is a D-type ﬂip-ﬂop; the input latch is a transparent-low D-type latch. Once conﬁgured as a registered or latched input, the buried macrocell cannot generate logic from the product-term array. The basic buried macrocell conﬁgurations are shown in Figure 6.

PAL-Block

Asynchronous

Sum of Products

Preset

from Logic

Allocator

CLK

1

AP

1

QD/T/L

0

n

AR

0

1

To I/O Cell

0

PAL-Block

Asynchronous

Note:

1. Latch option available on MACH 2 devices only.

Reset

To

Switch Matrix

Figure 3. Output Macrocell

14051K-004

8 MACH 1 & 2 Families

From

Logic

Allocator

n

To I/O Cell

From

Logic

Allocator

n

To I/O Cell

From

Logic

Allocator

CLK CLK

To Switch

From Logic

Allocator

CLK

To Switch

Matrix

a. Combinatorial, active high

n

0 n

Matrix

c. D-type register, active high

DQ

n

0

n

Matrix

AP

AR

T

AP

AR

To Switch

Matrix

b. Combinatorial, active low

To I/O Cell

Q

To I/O Cell

From

Logic

Allocator

CLK CLK

From Logic

Allocator

CLK CLK

0 n

To Switch

Matrix

0 n

To Switch

Matrix

n

d. D-type register, active low

n

AP

DQ

AR

AP

Q

T

AR

To I/O Cell

e. T-type register, active high

From Logic

Allocator

CLK

0

CLK

n

To Switch

Matrix

g. Latch, active high (MACH 2 only)

n

From

AP

L

Q

G

AR

To I/O Cell

Logic

Allocator

CLK

0 n

To Switch

Matrix

h. Latch, active low (MACH 2 only)

Figure 4. Output Macrocell Conﬁgurations

MACH 1 & 2 Families 9

f. T-type register, active low

n

AP

Q

L

G

AR

To I/O Cell

14051K-005

PAL-Block

From I/O Pin

Asynchronous

Preset

1

Sum of Products

From Logic

Allocator

From Logic

Allocator

CLK CLK

From Logic

Allocator

CLK

0

CLK

n

From Logic

IC Allocator

PAL-Block

Asynchronous

Reset

n

To Switch

Matrix

n

0 n

To Switch

Matrix

To Switch

Matrix

CLK

0

CLK

n

Switch Matrix

a. Combinatorial

c. T-type register

n

e. Latch

1 0

AP

QD/T/L

0

AR

To

Figure 5. Buried Macrocell (MACH 2 only)

AP

TQ

AR

AP

LQ

G

AR

From Logic

Allocator

CLKÂ

CLÂK

CLK

0

CLK

n

To Switch

Matrix

CLK

0

CLK

n

To Switch

Matrix

0 n

To Switch

n

Matrix

b. D-type register

d. Input register

f. Input latch

DQ

AP

DQ

AR

AP

LQ

G

AR

14051K-030

AP

AR

From I/O Cell

14051K-006

Figure 6. Buried Macrocell Conﬁgurations (MACH 2 only)

10 MACH 1 & 2 Families

The ﬂip-ﬂops in either macrocell type can be clocked by one of several clock pins (Table 10). Registers are clocked on the rising edge of the clock input. Latches hold their data when the gate input is HIGH. Clock pins are also available as inputs, although care must be taken when a signal acts as both clock and input to the same device.

Table 10. Macrocell Clocks

Device Number of Clocks Available Device Number of Clocks Available

MACH111 4 MACH211SP 2 MACH111SP 2 MACH221 4 MACH131 4 MACH221SP 4 MACH131SP 4 MACH231 4 MACH211 4 MACH231SP 4

All ﬂip-ﬂops have asynchronous reset and preset. This is controlled by the common product terms that control all ﬂip-ﬂops within a PAL block. For a single PAL block, all ﬂip-ﬂops, whether in an output or a buried macrocell, are initialized together. The initialization functionality of the ﬂip-ﬂops is illustrated in Table 11.

Table 11. Asynchronous Reset/Preset Operation

Conﬁguration AR AP CLK/LE Q+

0 0 X See Table 9

Register

Latch

01 X 1 10 X 0 11 X 0 0 0 X See Table 9 0 1 0 Illegal 01 1 1 1 0 0 Illegal 10 1 0 1 1 0 Illegal 11 1 0

I/O Cells

The I/O cells (Figure 7) provide a three-state output buffer. The three-state buffer can be left permanently enabled for use only as an output, permanently disabled for use as an input, or it can be controlled by one of two product terms for bi-directional signals and bus connections. The two product terms provided are common to a bank of I/O cells.

MACH 1 & 2 Families 11

Output Enable

Product Terms

(Common to bank of

I/O Cells)

V

CC

From Output

Macrocell

To Switch

Matrix

01 11

10 00

To Buried

Macrocell

(MACH 2 only)

14051K-007

Figure 7. I/O Cell

SPEEDLOCKING FOR GUARANTEED FIXED TIMING

The unique MACH 1 & 2 architecture is designed for high performance—a metric that is met in both raw speed, and even more importantly, guaranteed ﬁxed speed. The design of the switch matrix and P AL blocks guarantee a ﬁxed pin-to-pin delay that is independent of the logic required by the design. Other non-Lattice/V antis CPLDs incur serious timing delays as product terms expand beyond their typical 4 or 5 product term limits (Figure 8). Speed and SpeedLocking combine to give designers easy access to the performance required in today’s designs.

MACH 1 & 2 SpeedLocking

• Patented Architecture

• Path Independent

• Logic/Routing Independent

• Guaranteed Fixed Timing

• Up to 16 Product Terms per Output

• Variab le

• Path Dependent

• Logic/Routing Dependent Delays

• Unpredictable

• 4-5 Product Terms before Delays

Non-MACH

SpeedLocking

Shared Expander Delay

8.8 ns Parallel Expander Delay

6.6 ns

5.8 ns

5 ns

5 PT 10 PT 15 PT

Product Terms

t

PD

(ns)

11 10

9 8

7 6

5

Figure 8. Timing in MACH 1 & 2 vs. Non-MACH Devices

12 MACH 1 & 2 Families

10.4 ns Non-MACH

7.4 ns

MACH 1 & 2

14051K-001

JTAG IN-SYSTEM PROGRAMMING

Programming devices in-system provides a number of signiﬁcant beneﬁts including: rapid prototyping, lower inventory levels, higher quality, and the ability to make in-ﬁeld modiﬁcations. All MACHxxxSP devices provide in-system programming (ISP) capability through their JT AG ports. This capability has been implemented in a manner that insures that the JTAG port remains compliant to the IEEE 1149.1 standard. By using JTAG as the communication interface through which ISP is achieved, customers beneﬁt from a standard, well-deﬁned interface.

MACHxxxSP devices can be programmed across the commercial temperature and voltage range. These devices tristate the outputs during programming. Lattice/Vantis provides its free PC-based Lattice/VantisPRO software to facilitate in-system programming. Lattice/VantisPRO software takes the JEDEC ﬁle output produced by V antis’ design implementation software, along with information about the JTAG chain, and creates a set of vectors that are used to drive the JTAG chain. Lattice/ VantisPRO software can use these vectors to drive a JTAG chain via the parallel port of a PC. Alternatively, Lattice/VantisPRO software can output ﬁles in formats understood by common automated test equipment. This equipment can then be used to program MACHxxxSP devices during the testing of a circuit board. For more information about in-system programming, refer to the separate document entitled MACH ISP Manual.

BUS-FRIENDLY INPUTS AND I/Os

The MACH 1 & 2 inputs and I/Os include two inverters in series which loop back to the input. This double inversion weakly holds the input at its last driven logic state. For the circuit diagram, please refer to the Input/Output Equivalent Schematics (page 393) in the General Information Section of the Vantis 1999 Data Book.

PCI COMPLIANT

The MACH 1 & 2 families in -5/-6/-7/-10/-12 speed grades are fully compliant with the PCI Local Bus Speciﬁcation published by the PCI Special Interest Group. The MACH 1 & 2 families’

predictable timing ensures compliance with the PCI AC speciﬁcations independent of the design.

POWER-DOWN MODE

The MACH 1 & 2 families feature a programmable low-power mode in which individual signal paths can be programmed for low power. These low-power speed paths will be slower than the non-low-power paths. This feature allows speed critical paths to run at maximum frequency while the rest of the paths operate in the low-power mode, resulting in power savings of up to 75%. If all of the signals in a PAL block are in low-power mode, then the total power is reduced even further.

SAFE FOR MIXED SUPPLY VOLTAGE SYSTEM DESIGNS

All MACHxxxSP and most of the MACH 1 & 2 devices are safe for mixed supply voltage system designs. These 5-V devices will not overdrive 3.3-V devices above the output voltage of 3.3 V, while they can accept inputs from other 3.3-V devices. The MACH 1 & 2 families provide easy-touse mixed-voltage design compatibility. For more information, refer to the Technical Note entitled Mixed Supply Design with MACH 1 & 2 SP Devices.

POWER-UP RESET

All ﬂip-ﬂops power-up to a logic LOW for predictable system initialization. The actual values of the outputs of the MACH devices will depend on the conﬁguration of the macrocell. To guarantee

MACH 1 & 2 Families 13

initialization values, the VCC rise must be monotonic and the clock must be inactive until the reset delay time has elapsed.

SECURITY BIT

A security bit is provided on the MACH devices as a deterrent to unauthorized copying of the array conﬁguration patterns. Once programmed, this bit defeats readback of the programmed pattern by a device programmer, securing proprietary designs from competitors. Programming and veriﬁcation are also defeated by the security bit. The bit can only be reset by erasing the entire device.

14 MACH 1 & 2 Families

MACH111(SP) AND MACH131(SP) PAL BLOCK

0 4 8 12 16 20 24 28 40324336

47

51

Output Enable Output Enable

Asynchronous Reset

Asynchronous Preset

Switch Matrix

0

63

0 4 8 12 16 20 24 28 40324336

16

I/O

Output

M

0

M

1

M

2

M

3

C

0

M

C C C C C C C C C C C C C C C

for MACH111, MACH131, MACH131SP

Output Enable

47

Output Enable

51

4

1

2

M

5

3

4

M

6

5

6

M

7

Logic Allocator

8

M

8

9

10

M

9

11

12

M

10

13

14

M

15

11

M

12

M

13

M

14

M

15

for MACH111SP

CLK

2 4

Macro Cell

Output Macro Cell

Cell

I/O Cell

I/O

14051K-013

MACH 1 & 2 Families 15