Lattice Semiconductor Corporation ISPLSI3256E-70LQ, ISPLSI3256E-70LB320, ISPLSI3256E-100LQ, ISPLSI3256E-100LB320 Datasheet

®

ispLSI

3256E

In-System Programmable High Density PLD

Features

• HIGH-DENSITY PROGRAMMABLE LOGIC
— 256 I/O Pins
— 12000 PLD Gates
— 512 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

2

• HIGH PERFORMANCE E
—

fmax = 100 MHz Maximum Operating Frequency
tpd = 10 ns Propagation Delay

—
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power

• IN-SYSTEM PROGRAMMABLE
— 5V In-System Programmable (ISP™) using Lattice
ISP or Boundary Scan Test (IEEE 1149.1) Protocol
— Increased Manufacturing Yields, Reduced Time-to-

Market, and Improved Product Quality

— Reprogram Soldered Devices for Faster Debugging

• 100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE

• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue

Logic and Structured Designs
— Five Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to Mini-

mize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global

Interconnectivity

• ispDesignEXPERT™ – LOGIC COMPILER AND COM­PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZER™

— PC and UNIX Platforms

CMOS® TECHNOLOGY

Functional Block Diagram

ORP

H3 H2 H1 H0

A0

A1

A2

ORP

A3

B0

ORP ORP

B1

B2

ORP

B3

C0 C1 C2 C3

ORP

ORP

OR

Array

AND Array

OR

Array

Global Routing Pool

ORP

ORP

G3

DQ

DQ

DQ

DQ

DQ

DQ

DQ

DQ

D0

ORP

ORP

G2 G1 G0

Twin
GLB

D1 D2

ORP

D3

Boundary

Scan

F3

F2

F1

F0

E3

ORP ORP

E2

E1

ORP ORP

E0

0139A/3256E

Description

The ispLSI 3256E is a High Density Programmable Logic
Device containing 512 Registers, 256 Universal I/O pins,
five Dedicated Clock Input Pins, 16 Output Routing Pools
(ORP) and a Global Routing Pool (GRP) which allows
complete inter-connectivity between all of these ele­ments. The ispLSI 3256E features 5V in-system
programmability and in-system diagnostic capabilities.
The ispLSI 3256E offers non-volatile reprogrammability
of the logic, as well as the interconnect to provide truly
reconfigurable systems.

The basic unit of logic on the ispLSI 3256E device is the
Twin Generic Logic Block (Twin GLB) labelled A0, A1...H3.
There are a total of 32 Twin GLBs in the ispLSI 3256E
device. Each Twin GLB has 24 inputs, a programmable
AND array and two OR/Exclusive-OR Arrays and eight
outputs which can be configured to be either combinato­rial or registered. All Twin GLB inputs come from the
GRP.

Copyright © 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. June 2002
Tel. [phone]; 1-800-LATTICE; FAX [phone]; http://www.latticesemi.com

3256e_08 1

Functional Block Diagram

Figure 1. ispLSI 3256E Functional Block Diagram

I/O 255

I/O 253

I/O 251

I/O 249

I/O 247

I/O 245

I/O 243

GOE0

GOE1

I/O 254

I/O 252

I/O 250

I/O 248

I/O 246

I/O 244

I/O 241

I/O 242

I/O 240

I/O 239

I/O 237

I/O 238

I/O 236

I/O 235

I/O 233

I/O 234

I/O 232

I/O 231

I/O 229

I/O 230

I/O 228

I/O 227

I/O 226

I/O 225

I/O 224

Specifications ispLSI 3256E

I/O 223

I/O 221

I/O 219

I/O 217

I/O 215

I/O 213

I/O 211

I/O 222

I/O 220

I/O 218

I/O 216

I/O 214

I/O 212

I/O 209

I/O 210

I/O 208

I/O 207

I/O 205

I/O 206

I/O 204

I/O 203

I/O 201

I/O 202

I/O 200

I/O 199

I/O 197

I/O 198

I/O 196

I/O 195

I/O 193

I/O 194

I/O 192

BSCAN/ispEN

TCLK/SCLK

TMS/MODE

I/O 1
I/O 3
I/O 5
I/O 7

I/O 9
I/O 11
I/O 13
I/O 15

I/O 17
I/O 19
I/O 21
I/O 23

I/O 25
I/O 27
I/O 29
I/O 31

I/O 33
I/O 35
I/O 37
I/O 39

I/O 41
I/O 43
I/O 45
I/O 47

I/O 49
I/O 51
I/O 53
I/O 55

I/O 57
I/O 59
I/O 61
I/O 63

TOE

I/O 0
I/O 2
I/O 4
I/O 6

I/O 8
I/O 10
I/O 12
I/O 14

I/O 16
I/O 18
I/O 20
I/O 22

I/O 24
I/O 26
I/O 28
I/O 30

I/O 32
I/O 34
I/O 36
I/O 38

I/O 40
I/O 42
I/O 44
I/O 46

I/O 48
I/O 50
I/O 52
I/O 54

I/O 56
I/O 58
I/O 60
I/O 62

Generic

Logic

Blocks

A0

A1

A2

Input Bus

A3

B0

ORP ORP

B1

Input Bus

B2

ORP ORP

B3

ORP

H2 H1 H0

H3

Input Bus Input Bus

ORP ORP

ORP

G2 G1 G0

G3

Global Routing Pool

(GRP)

ISP and

Boundary

Scan TAP

F3

F2

F1

F0

E3

E2

E1

E0

ORP ORP

ORP ORP

TDI/SDI
TRST
TDO/SDO

Input Bus

Input Bus

I/O 190
I/O 188
I/O 186
I/O 184

I/O 182
I/O 180
I/O 178
I/O 176

I/O 174
I/O 172
I/O 170
I/O 168

I/O 166
I/O 164
I/O 162
I/O 160

I/O 158
I/O 156
I/O 154
I/O 152

I/O 150
I/O 148
I/O 146
I/O 144

I/O 142
I/O 140
I/O 138
I/O 136

I/O 134
I/O 132
I/O 130
I/O 128

I/O 191
I/O 189
I/O 187
I/O 185

I/O 183
I/O 181
I/O 179
I/O 177

I/O 175
I/O 173
I/O 171
I/O 169

I/O 167
I/O 165
I/O 163
I/O 161

I/O 159
I/O 157
I/O 155
I/O 153

I/O 151
I/O 149
I/O 147
I/O 145

I/O 143
I/O 141
I/O 139
I/O 137

I/O 135
I/O 133
I/O 131
I/O 129

RESET

Megablock

C1 C2 C3

C0

ORP ORP

ORP ORP

Input Bus Input Bus

I/O 88

I/O 90

I/O 92

I/O 64

I/O 66

I/O 65

I/O 67

I/O 68

I/O 70

I/O 69

I/O 71

I/O 72

I/O 74

I/O 73

I/O 75

I/O 76

I/O 78

I/O 77

I/O 79

I/O 80

I/O 82

I/O 81

I/O 83

I/O 84

I/O 85

I/O 86

I/O 87

I/O 89

I/O 91

I/O 94

I/O 93

I/O 95

2

D0

I/O 96

I/O 98

I/O 97

I/O 99

D1 D2 D3

I/O 100

I/O 102

I/O 104

I/O 106

I/O 108

I/O 110

I/O 101

I/O 103

I/O 105

I/O 107

I/O 109

I/O 111

I/O 112

I/O 114

I/O 113

I/O 115

I/O 116

I/O 118

I/O 117

I/O 119

I/O 120

I/O 122

I/O 121

I/O 123

I/O 124

I/O 126

I/O 125

I/O 127

CLK 1

CLK 0

Y0

Y1Y2Y3

IOCLK 1

CLK 2

IOCLK 0

Y4

0139isp/3256E

Description (continued)

Specifications ispLSI 3256E

All local logic block outputs are brought back into the
GRP so they can be connected to the inputs of any other
logic block on the device. The device also has 256 I/O
cells, each of which is directly connected to an I/O pin.
Each I/O cell can be individually programmed to be a
combinatorial input, a registered input, a latched input, an
output or a bidirectional I/O pin with 3-state control. The
signal levels are TTL compatible voltages and the output
drivers can source 4 mA or sink 8 mA. Each output can
be programmed independently for fast or slow output
slew rate to minimize overall output switching noise.

The 256 I/O Cells are grouped into 16 sets of 16 bits.
Pairs of these I/O groups are associated with a logic
Megablock through the use of the ORP. Each Megablock
is able to provide one Product Term Output Enable
(PTOE) signal which is globally distributed to all I/O cells.
That PTOE signal can be generated within any GLB in the
Megablock. Each I/O cell can select either a Global OE
or a PTOE.

Four Twin GLBs, 32 I/O Cells and two ORPs are con­nected together to make a logic Megablock. The
Megablock is defined by the resources that it shares. The
outputs of the four Twin GLBs are connected to a set of
32 I/O cells by the ORP. The ispLSI 3256E device
contains eight of these Megablocks.

Clocks in the ispLSI 3256E device are provided through
five dedicated clock pins. The five pins provide three
clocks to the Twin GLBs and two clocks to the I/O cells.

The table below lists key attributes of the device along
with the number of resources available.

An additional feature of the ispLSI 3256E is its Boundary
Scan capability, which is composed of cells connected
between the on-chip system logic and the device’s input
and output pins. All I/O pins have associated boundary
scan registers, with 3-state I/O using three boundary
scan registers and inputs using one.

The ispLSI 3256E supports all IEEE 1149.1 mandatory
instructions, which include BYPASS, EXTEST and
SAMPLE.

Key Attributes of the ispLSI 3256E

etubirttAytitnauQ

sBLGniwT 23

sretsigeR 215

sniPO/I 652

skcolClabolG 5

The GRP has as its inputs the outputs from all of the Twin
GLBs and all of the inputs from the bidirectional I/O cells.
All of these signals are made available to the inputs of the
Twin GLBs. Delays through the GRP have been equal­ized to minimize timing skew and logic glitching.

EOlabolG 2

EOtseT 1

E6523/300-elbaT

3

Specifications ispLSI 3256E

Absolute Maximum Ratings

1

Supply Voltage Vcc...........................................................................-0.5 to +7.0V

Input Voltage Applied........................................................................-2.5 to VCC +1.0V

Off-State Output Voltage Applied .....................................................-2.5 to VCC +1.0V

Storage Temperature........................................................................-65 to 150°C

Case Temp. with Power Applied ......................................................-55 to 125°C

Max. Junction Temp. (TJ) with Power Applied (304-Pin PQFP) ......150°C

Max. Junction Temp. (TJ) with Power Applied (320-Ball BGA)........140°C

1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).

DC Recommended Operating Condition

T
V
V
V

A

SYMBOL

CC
IL
IH

PARAMETER

Ambient Temperature
Supply Voltage
Input Low Voltage
Input High Voltage

MIN. MAX. UNITS

0

4.75
0

2.0

70

5.25

0.8

V +1

CC

Table 2-0005/3256E

°C

V
V
V

Capacitance (TA=25°C,f=1.0 MHz)

SYMBOL

C

1

C

2

I/O Capacitance
Clock Capacitance

PARAMETER

Data Retention Specifications

PARAMETER

Data Retention
ispLSI Erase/Reprogram Cycles

UNITSTYPICAL TEST CONDITIONS

10
15

MINIMUM MAXIMUM UNITS

20

10000

pf V = 5.0V, V = 2.0V
pf V = 5.0V, V = 2.0V

–
–

CC I/O

CC Y

Table 2-0006/3256E

Years

Cycles

Table 2-0008/3256E

4

Switching Test Conditions

Specifications ispLSI 3256E

Input Pulse Levels
Input Rise and Fall Time

Input Timing Reference Levels
Output Timing Reference Levels
Output Load

3-state levels are measured 0.5V from

GND to 3.0V

≤ 3ns 10% to 90%

1.5V

1.5V

See Figure 2

Table 2-0003/3256E

steady-state active level.

Output Load conditions (See Figure 2)

TEST CONDITION R1 R2 CL

A 470Ω 390Ω 35pF

Active High

B

Active Low
Active High to Z

at V -0.5V

C

Active Low to Z
at V +0.5V

OH

OL

∞ 390Ω 35pF

470Ω 390Ω 35pF

∞ 390Ω 5pF

470Ω 390Ω 5pF

DC Electrical Characteristics

Table 2 - 0004A

Figure 2. Test Load

Device
Output

*C

includes Test Fixture and Probe Capacitance.

L

+ 5V

R

1

Test

Point

R

2

C

*

L

0213A

Over Recommended Operating Conditions

SYMBOL

V

OL

V

OH

I

IL

I

IH

I

IL-isp

I

IL-PU

1

I

OS

2,4

I

CC

Output Low Voltage
Output High Voltage
Input or I/O Low Leakage Current
Input or I/O High Leakage Current
Bscan/ispEN Input Low Leakage Current
I/O Active Pull-Up Current
Output Short Circuit Current

Operating Power Supply Current

PARAMETER

I = 8 mA

OL

I = -4 mA

OH

0V ≤ V ≤ V (Max.)

3.5V ≤ V ≤ V
0V ≤ V ≤ V
0V ≤ V ≤ V
V = 5V, V = 0.5V

CC OUT

V = 0.0V, V = 3.0V

IL IH

f = 1 MHz

TOGGLE

1. One output at a time for a maximum duration of one second. V = 0.5V was selected to avoid test problems

CONDITION MIN. TYP. MAX. UNITS

–

IN IL

IN

IN IL

IN CC

IL

2.4
–
–
–
–
–

–

OUT

by tester ground degradation. Characterized but not 100% tested.

2. Measured using sixteen 16-bit counters.

3. Typical values are at V

4. Maximum I

varies widely with specific device configuration and operating frequency. Refer to the Power Consumption

CC

= 5V and TA = 25°C.

CC

section of this datasheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate
maximum I

CC

.

3

–
–
–
–
–
–
–

300

Table 2 - 0007isp/3256E

0.4
–

-10
10

-150

-150

-200
–

V
V

µA
µA
µA
µA

mA
mA

5